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r600g: Removed debug code.
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_screen.h"
29 #include "r600_context.h"
30 #include "r600_shader.h"
31 #include "r600_asm.h"
32 #include "r600_sq.h"
33 #include "r600_opcodes.h"
34 #include "r600d.h"
35 #include <stdio.h>
36 #include <errno.h>
37
38
39 struct r600_shader_tgsi_instruction;
40
41 struct r600_shader_ctx {
42 struct tgsi_shader_info info;
43 struct tgsi_parse_context parse;
44 const struct tgsi_token *tokens;
45 unsigned type;
46 unsigned file_offset[TGSI_FILE_COUNT];
47 unsigned temp_reg;
48 struct r600_shader_tgsi_instruction *inst_info;
49 struct r600_bc *bc;
50 struct r600_shader *shader;
51 u32 value[4];
52 u32 *literals;
53 u32 nliterals;
54 u32 max_driver_temp_used;
55 };
56
57 struct r600_shader_tgsi_instruction {
58 unsigned tgsi_opcode;
59 unsigned is_op3;
60 unsigned r600_opcode;
61 int (*process)(struct r600_shader_ctx *ctx);
62 };
63
64 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
65 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
66
67 static int r600_shader_update(struct pipe_context *ctx, struct r600_shader *shader)
68 {
69 struct r600_context *rctx = r600_context(ctx);
70 const struct util_format_description *desc;
71 enum pipe_format resource_format[160];
72 unsigned i, nresources = 0;
73 struct r600_bc *bc = &shader->bc;
74 struct r600_bc_cf *cf;
75 struct r600_bc_vtx *vtx;
76
77 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
78 return 0;
79 for (i = 0; i < rctx->vertex_elements->count; i++) {
80 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
81 }
82 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
83 switch (cf->inst) {
84 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
85 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
86 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
87 desc = util_format_description(resource_format[vtx->buffer_id]);
88 if (desc == NULL) {
89 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
90 return -EINVAL;
91 }
92 vtx->dst_sel_x = desc->swizzle[0];
93 vtx->dst_sel_y = desc->swizzle[1];
94 vtx->dst_sel_z = desc->swizzle[2];
95 vtx->dst_sel_w = desc->swizzle[3];
96 }
97 break;
98 default:
99 break;
100 }
101 }
102 return r600_bc_build(&shader->bc);
103 }
104
105 int r600_pipe_shader_create(struct pipe_context *ctx,
106 struct r600_context_state *rpshader,
107 const struct tgsi_token *tokens)
108 {
109 struct r600_screen *rscreen = r600_screen(ctx->screen);
110 int r;
111
112 //fprintf(stderr, "--------------------------------------------------------------\n");
113 //tgsi_dump(tokens, 0);
114 if (rpshader == NULL)
115 return -ENOMEM;
116 rpshader->shader.family = radeon_get_family(rscreen->rw);
117 rpshader->shader.use_mem_constant = rscreen->use_mem_constant;
118 r = r600_shader_from_tgsi(tokens, &rpshader->shader);
119 if (r) {
120 R600_ERR("translation from TGSI failed !\n");
121 return r;
122 }
123 r = r600_bc_build(&rpshader->shader.bc);
124 if (r) {
125 R600_ERR("building bytecode failed !\n");
126 return r;
127 }
128 //fprintf(stderr, "______________________________________________________________\n");
129 return 0;
130 }
131
132 static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_state *rpshader)
133 {
134 struct r600_context *rctx = r600_context(ctx);
135 struct radeon_state *state;
136
137 state = &rpshader->rstate[0];
138 radeon_state_fini(&rpshader->rstate[0]);
139
140 return rctx->vtbl->vs_shader(rctx, rpshader, state);
141 }
142
143 static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_state *rpshader)
144 {
145 struct r600_context *rctx = r600_context(ctx);
146 struct radeon_state *state;
147
148 state = &rpshader->rstate[0];
149 radeon_state_fini(state);
150
151 return rctx->vtbl->ps_shader(rctx, rpshader, state);
152 }
153
154 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_context_state *rpshader)
155 {
156 struct r600_screen *rscreen = r600_screen(ctx->screen);
157 struct r600_context *rctx = r600_context(ctx);
158 struct r600_shader *rshader = &rpshader->shader;
159 int r;
160 void *data;
161
162 /* copy new shader */
163 radeon_ws_bo_reference(rscreen->rw, &rpshader->bo, NULL);
164 rpshader->bo = NULL;
165 rpshader->bo = radeon_ws_bo(rscreen->rw, rshader->bc.ndw * 4,
166 4096, 0);
167 if (rpshader->bo == NULL) {
168 return -ENOMEM;
169 }
170 data = radeon_ws_bo_map(rscreen->rw, rpshader->bo, 0, ctx);
171 memcpy(data, rshader->bc.bytecode, rshader->bc.ndw * 4);
172 radeon_ws_bo_unmap(rscreen->rw, rpshader->bo);
173 /* build state */
174 rshader->flat_shade = rctx->flat_shade;
175 switch (rshader->processor_type) {
176 case TGSI_PROCESSOR_VERTEX:
177 r = r600_pipe_shader_vs(ctx, rpshader);
178 break;
179 case TGSI_PROCESSOR_FRAGMENT:
180 r = r600_pipe_shader_ps(ctx, rpshader);
181 break;
182 default:
183 r = -EINVAL;
184 break;
185 }
186 return r;
187 }
188
189 int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_context_state *rpshader)
190 {
191 struct r600_context *rctx = r600_context(ctx);
192 int r;
193
194 if (rpshader == NULL)
195 return -EINVAL;
196 /* there should be enough input */
197 if (rctx->vertex_elements->count < rpshader->shader.bc.nresource) {
198 R600_ERR("%d resources provided, expecting %d\n",
199 rctx->vertex_elements->count, rpshader->shader.bc.nresource);
200 return -EINVAL;
201 }
202 r = r600_shader_update(ctx, &rpshader->shader);
203 if (r)
204 return r;
205 return r600_pipe_shader(ctx, rpshader);
206 }
207
208 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
209 {
210 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
211 int j;
212
213 if (i->Instruction.NumDstRegs > 1) {
214 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
215 return -EINVAL;
216 }
217 if (i->Instruction.Predicate) {
218 R600_ERR("predicate unsupported\n");
219 return -EINVAL;
220 }
221 #if 0
222 if (i->Instruction.Label) {
223 R600_ERR("label unsupported\n");
224 return -EINVAL;
225 }
226 #endif
227 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
228 if (i->Src[j].Register.Dimension ||
229 i->Src[j].Register.Absolute) {
230 R600_ERR("unsupported src %d (dimension %d|absolute %d)\n", j,
231 i->Src[j].Register.Dimension,
232 i->Src[j].Register.Absolute);
233 return -EINVAL;
234 }
235 }
236 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
237 if (i->Dst[j].Register.Dimension) {
238 R600_ERR("unsupported dst (dimension)\n");
239 return -EINVAL;
240 }
241 }
242 return 0;
243 }
244
245 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int gpr)
246 {
247 int i, r;
248 struct r600_bc_alu alu;
249
250 for (i = 0; i < 8; i++) {
251 memset(&alu, 0, sizeof(struct r600_bc_alu));
252
253 if (i < 4)
254 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
255 else
256 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
257
258 if ((i > 1) && (i < 6)) {
259 alu.dst.sel = ctx->shader->input[gpr].gpr;
260 alu.dst.write = 1;
261 }
262
263 alu.dst.chan = i % 4;
264 alu.src[0].chan = (1 - (i % 2));
265 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + gpr;
266
267 alu.bank_swizzle_force = SQ_ALU_VEC_210;
268 if ((i % 4) == 3)
269 alu.last = 1;
270 r = r600_bc_add_alu(ctx->bc, &alu);
271 if (r)
272 return r;
273 }
274 return 0;
275 }
276
277
278 static int tgsi_declaration(struct r600_shader_ctx *ctx)
279 {
280 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
281 struct r600_bc_vtx vtx;
282 unsigned i;
283 int r;
284
285 switch (d->Declaration.File) {
286 case TGSI_FILE_INPUT:
287 i = ctx->shader->ninput++;
288 ctx->shader->input[i].name = d->Semantic.Name;
289 ctx->shader->input[i].sid = d->Semantic.Index;
290 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
291 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
292 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
293 /* turn input into fetch */
294 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
295 vtx.inst = 0;
296 vtx.fetch_type = 0;
297 vtx.buffer_id = i;
298 /* register containing the index into the buffer */
299 vtx.src_gpr = 0;
300 vtx.src_sel_x = 0;
301 vtx.mega_fetch_count = 0x1F;
302 vtx.dst_gpr = ctx->shader->input[i].gpr;
303 vtx.dst_sel_x = 0;
304 vtx.dst_sel_y = 1;
305 vtx.dst_sel_z = 2;
306 vtx.dst_sel_w = 3;
307 r = r600_bc_add_vtx(ctx->bc, &vtx);
308 if (r)
309 return r;
310 }
311 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == 2) {
312 /* turn input into interpolate on EG */
313 evergreen_interp_alu(ctx, i);
314 }
315 break;
316 case TGSI_FILE_OUTPUT:
317 i = ctx->shader->noutput++;
318 ctx->shader->output[i].name = d->Semantic.Name;
319 ctx->shader->output[i].sid = d->Semantic.Index;
320 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
321 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
322 break;
323 case TGSI_FILE_CONSTANT:
324 case TGSI_FILE_TEMPORARY:
325 case TGSI_FILE_SAMPLER:
326 case TGSI_FILE_ADDRESS:
327 break;
328 default:
329 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
330 return -EINVAL;
331 }
332 return 0;
333 }
334
335 static int r600_get_temp(struct r600_shader_ctx *ctx)
336 {
337 return ctx->temp_reg + ctx->max_driver_temp_used++;
338 }
339
340 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
341 {
342 struct tgsi_full_immediate *immediate;
343 struct r600_shader_ctx ctx;
344 struct r600_bc_output output[32];
345 unsigned output_done, noutput;
346 unsigned opcode;
347 int i, r = 0, pos0;
348
349 ctx.bc = &shader->bc;
350 ctx.shader = shader;
351 r = r600_bc_init(ctx.bc, shader->family);
352 if (r)
353 return r;
354 ctx.bc->use_mem_constant = shader->use_mem_constant;
355 ctx.tokens = tokens;
356 tgsi_scan_shader(tokens, &ctx.info);
357 tgsi_parse_init(&ctx.parse, tokens);
358 ctx.type = ctx.parse.FullHeader.Processor.Processor;
359 shader->processor_type = ctx.type;
360
361 /* register allocations */
362 /* Values [0,127] correspond to GPR[0..127].
363 * Values [128,159] correspond to constant buffer bank 0
364 * Values [160,191] correspond to constant buffer bank 1
365 * Values [256,511] correspond to cfile constants c[0..255].
366 * Other special values are shown in the list below.
367 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
368 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
369 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
370 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
371 * 248 SQ_ALU_SRC_0: special constant 0.0.
372 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
373 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
374 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
375 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
376 * 253 SQ_ALU_SRC_LITERAL: literal constant.
377 * 254 SQ_ALU_SRC_PV: previous vector result.
378 * 255 SQ_ALU_SRC_PS: previous scalar result.
379 */
380 for (i = 0; i < TGSI_FILE_COUNT; i++) {
381 ctx.file_offset[i] = 0;
382 }
383 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
384 ctx.file_offset[TGSI_FILE_INPUT] = 1;
385 }
386 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
387 ctx.info.file_count[TGSI_FILE_INPUT];
388 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
389 ctx.info.file_count[TGSI_FILE_OUTPUT];
390 if (ctx.shader->use_mem_constant)
391 ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
392 else
393 ctx.file_offset[TGSI_FILE_CONSTANT] = 256;
394
395 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
396 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
397 ctx.info.file_count[TGSI_FILE_TEMPORARY];
398
399 ctx.nliterals = 0;
400 ctx.literals = NULL;
401
402 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
403 tgsi_parse_token(&ctx.parse);
404 switch (ctx.parse.FullToken.Token.Type) {
405 case TGSI_TOKEN_TYPE_IMMEDIATE:
406 immediate = &ctx.parse.FullToken.FullImmediate;
407 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
408 if(ctx.literals == NULL) {
409 r = -ENOMEM;
410 goto out_err;
411 }
412 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
413 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
414 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
415 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
416 ctx.nliterals++;
417 break;
418 case TGSI_TOKEN_TYPE_DECLARATION:
419 r = tgsi_declaration(&ctx);
420 if (r)
421 goto out_err;
422 break;
423 case TGSI_TOKEN_TYPE_INSTRUCTION:
424 r = tgsi_is_supported(&ctx);
425 if (r)
426 goto out_err;
427 ctx.max_driver_temp_used = 0;
428 /* reserve first tmp for everyone */
429 r600_get_temp(&ctx);
430 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
431 if (ctx.bc->chiprev == 2)
432 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
433 else
434 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
435 r = ctx.inst_info->process(&ctx);
436 if (r)
437 goto out_err;
438 r = r600_bc_add_literal(ctx.bc, ctx.value);
439 if (r)
440 goto out_err;
441 break;
442 default:
443 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
444 r = -EINVAL;
445 goto out_err;
446 }
447 }
448 /* export output */
449 noutput = shader->noutput;
450 for (i = 0, pos0 = 0; i < noutput; i++) {
451 memset(&output[i], 0, sizeof(struct r600_bc_output));
452 output[i].gpr = shader->output[i].gpr;
453 output[i].elem_size = 3;
454 output[i].swizzle_x = 0;
455 output[i].swizzle_y = 1;
456 output[i].swizzle_z = 2;
457 output[i].swizzle_w = 3;
458 output[i].barrier = 1;
459 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
460 output[i].array_base = i - pos0;
461 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
462 switch (ctx.type) {
463 case TGSI_PROCESSOR_VERTEX:
464 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
465 output[i].array_base = 60;
466 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
467 /* position doesn't count in array_base */
468 pos0++;
469 }
470 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
471 output[i].array_base = 61;
472 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
473 /* position doesn't count in array_base */
474 pos0++;
475 }
476 break;
477 case TGSI_PROCESSOR_FRAGMENT:
478 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
479 output[i].array_base = shader->output[i].sid;
480 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
481 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
482 output[i].array_base = 61;
483 output[i].swizzle_x = 2;
484 output[i].swizzle_y = output[i].swizzle_z = output[i].swizzle_w = 7;
485 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
486 } else {
487 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
488 r = -EINVAL;
489 goto out_err;
490 }
491 break;
492 default:
493 R600_ERR("unsupported processor type %d\n", ctx.type);
494 r = -EINVAL;
495 goto out_err;
496 }
497 }
498 /* add fake param output for vertex shader if no param is exported */
499 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
500 for (i = 0, pos0 = 0; i < noutput; i++) {
501 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
502 pos0 = 1;
503 break;
504 }
505 }
506 if (!pos0) {
507 memset(&output[i], 0, sizeof(struct r600_bc_output));
508 output[i].gpr = 0;
509 output[i].elem_size = 3;
510 output[i].swizzle_x = 0;
511 output[i].swizzle_y = 1;
512 output[i].swizzle_z = 2;
513 output[i].swizzle_w = 3;
514 output[i].barrier = 1;
515 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
516 output[i].array_base = 0;
517 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
518 noutput++;
519 }
520 }
521 /* add fake pixel export */
522 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
523 memset(&output[0], 0, sizeof(struct r600_bc_output));
524 output[0].gpr = 0;
525 output[0].elem_size = 3;
526 output[0].swizzle_x = 7;
527 output[0].swizzle_y = 7;
528 output[0].swizzle_z = 7;
529 output[0].swizzle_w = 7;
530 output[0].barrier = 1;
531 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
532 output[0].array_base = 0;
533 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
534 noutput++;
535 }
536 /* set export done on last export of each type */
537 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
538 if (i == (noutput - 1)) {
539 output[i].end_of_program = 1;
540 }
541 if (!(output_done & (1 << output[i].type))) {
542 output_done |= (1 << output[i].type);
543 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
544 }
545 }
546 /* add output to bytecode */
547 for (i = 0; i < noutput; i++) {
548 r = r600_bc_add_output(ctx.bc, &output[i]);
549 if (r)
550 goto out_err;
551 }
552 free(ctx.literals);
553 tgsi_parse_free(&ctx.parse);
554 return 0;
555 out_err:
556 free(ctx.literals);
557 tgsi_parse_free(&ctx.parse);
558 return r;
559 }
560
561 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
562 {
563 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
564 return -EINVAL;
565 }
566
567 static int tgsi_end(struct r600_shader_ctx *ctx)
568 {
569 return 0;
570 }
571
572 static int tgsi_src(struct r600_shader_ctx *ctx,
573 const struct tgsi_full_src_register *tgsi_src,
574 struct r600_bc_alu_src *r600_src)
575 {
576 int index;
577 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
578 r600_src->sel = tgsi_src->Register.Index;
579 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
580 r600_src->sel = 0;
581 index = tgsi_src->Register.Index;
582 ctx->value[0] = ctx->literals[index * 4 + 0];
583 ctx->value[1] = ctx->literals[index * 4 + 1];
584 ctx->value[2] = ctx->literals[index * 4 + 2];
585 ctx->value[3] = ctx->literals[index * 4 + 3];
586 }
587 if (tgsi_src->Register.Indirect)
588 r600_src->rel = V_SQ_REL_RELATIVE;
589 r600_src->neg = tgsi_src->Register.Negate;
590 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
591 return 0;
592 }
593
594 static int tgsi_dst(struct r600_shader_ctx *ctx,
595 const struct tgsi_full_dst_register *tgsi_dst,
596 unsigned swizzle,
597 struct r600_bc_alu_dst *r600_dst)
598 {
599 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
600
601 r600_dst->sel = tgsi_dst->Register.Index;
602 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
603 r600_dst->chan = swizzle;
604 r600_dst->write = 1;
605 if (tgsi_dst->Register.Indirect)
606 r600_dst->rel = V_SQ_REL_RELATIVE;
607 if (inst->Instruction.Saturate) {
608 r600_dst->clamp = 1;
609 }
610 return 0;
611 }
612
613 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
614 {
615 switch (swizzle) {
616 case 0:
617 return tgsi_src->Register.SwizzleX;
618 case 1:
619 return tgsi_src->Register.SwizzleY;
620 case 2:
621 return tgsi_src->Register.SwizzleZ;
622 case 3:
623 return tgsi_src->Register.SwizzleW;
624 default:
625 return 0;
626 }
627 }
628
629 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
630 {
631 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
632 struct r600_bc_alu alu;
633 int i, j, k, nconst, r;
634
635 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
636 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
637 nconst++;
638 }
639 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
640 if (r) {
641 return r;
642 }
643 }
644 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
645 if (inst->Src[j].Register.File == TGSI_FILE_CONSTANT && j > 0) {
646 int treg = r600_get_temp(ctx);
647 for (k = 0; k < 4; k++) {
648 memset(&alu, 0, sizeof(struct r600_bc_alu));
649 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
650 alu.src[0].sel = r600_src[j].sel;
651 alu.src[0].chan = k;
652 alu.dst.sel = treg;
653 alu.dst.chan = k;
654 alu.dst.write = 1;
655 if (k == 3)
656 alu.last = 1;
657 r = r600_bc_add_alu(ctx->bc, &alu);
658 if (r)
659 return r;
660 }
661 r600_src[j].sel = treg;
662 j--;
663 }
664 }
665 return 0;
666 }
667
668 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
669 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
670 {
671 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
672 struct r600_bc_alu alu;
673 int i, j, k, nliteral, r;
674
675 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
676 if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
677 nliteral++;
678 }
679 }
680 for (i = 0, j = 0; i < inst->Instruction.NumSrcRegs; i++) {
681 if (inst->Src[j].Register.File == TGSI_FILE_IMMEDIATE) {
682 int treg = r600_get_temp(ctx);
683 for (k = 0; k < 4; k++) {
684 memset(&alu, 0, sizeof(struct r600_bc_alu));
685 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
686 alu.src[0].sel = r600_src[j].sel;
687 alu.src[0].chan = k;
688 alu.dst.sel = treg;
689 alu.dst.chan = k;
690 alu.dst.write = 1;
691 if (k == 3)
692 alu.last = 1;
693 r = r600_bc_add_alu(ctx->bc, &alu);
694 if (r)
695 return r;
696 }
697 r = r600_bc_add_literal(ctx->bc, ctx->value);
698 if (r)
699 return r;
700 r600_src[j].sel = treg;
701 j++;
702 }
703 }
704 return 0;
705 }
706
707 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
708 {
709 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
710 struct r600_bc_alu_src r600_src[3];
711 struct r600_bc_alu alu;
712 int i, j, r;
713 int lasti = 0;
714
715 for (i = 0; i < 4; i++) {
716 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
717 lasti = i;
718 }
719 }
720
721 r = tgsi_split_constant(ctx, r600_src);
722 if (r)
723 return r;
724 for (i = 0; i < lasti + 1; i++) {
725 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
726 continue;
727
728 memset(&alu, 0, sizeof(struct r600_bc_alu));
729 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
730 if (r)
731 return r;
732
733 alu.inst = ctx->inst_info->r600_opcode;
734 if (!swap) {
735 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
736 alu.src[j] = r600_src[j];
737 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
738 }
739 } else {
740 alu.src[0] = r600_src[1];
741 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
742
743 alu.src[1] = r600_src[0];
744 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
745 }
746 /* handle some special cases */
747 switch (ctx->inst_info->tgsi_opcode) {
748 case TGSI_OPCODE_SUB:
749 alu.src[1].neg = 1;
750 break;
751 case TGSI_OPCODE_ABS:
752 alu.src[0].abs = 1;
753 break;
754 default:
755 break;
756 }
757 if (i == lasti) {
758 alu.last = 1;
759 }
760 r = r600_bc_add_alu(ctx->bc, &alu);
761 if (r)
762 return r;
763 }
764 return 0;
765 }
766
767 static int tgsi_op2(struct r600_shader_ctx *ctx)
768 {
769 return tgsi_op2_s(ctx, 0);
770 }
771
772 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
773 {
774 return tgsi_op2_s(ctx, 1);
775 }
776
777 /*
778 * r600 - trunc to -PI..PI range
779 * r700 - normalize by dividing by 2PI
780 * see fdo bug 27901
781 */
782 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
783 struct r600_bc_alu_src r600_src[3])
784 {
785 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
786 int r;
787 uint32_t lit_vals[4];
788 struct r600_bc_alu alu;
789
790 memset(lit_vals, 0, 4*4);
791 r = tgsi_split_constant(ctx, r600_src);
792 if (r)
793 return r;
794
795 r = tgsi_split_literal_constant(ctx, r600_src);
796 if (r)
797 return r;
798
799 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
800 lit_vals[1] = fui(0.5f);
801
802 memset(&alu, 0, sizeof(struct r600_bc_alu));
803 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
804 alu.is_op3 = 1;
805
806 alu.dst.chan = 0;
807 alu.dst.sel = ctx->temp_reg;
808 alu.dst.write = 1;
809
810 alu.src[0] = r600_src[0];
811 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
812
813 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
814 alu.src[1].chan = 0;
815 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
816 alu.src[2].chan = 1;
817 alu.last = 1;
818 r = r600_bc_add_alu(ctx->bc, &alu);
819 if (r)
820 return r;
821 r = r600_bc_add_literal(ctx->bc, lit_vals);
822 if (r)
823 return r;
824
825 memset(&alu, 0, sizeof(struct r600_bc_alu));
826 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
827
828 alu.dst.chan = 0;
829 alu.dst.sel = ctx->temp_reg;
830 alu.dst.write = 1;
831
832 alu.src[0].sel = ctx->temp_reg;
833 alu.src[0].chan = 0;
834 alu.last = 1;
835 r = r600_bc_add_alu(ctx->bc, &alu);
836 if (r)
837 return r;
838
839 if (ctx->bc->chiprev == 0) {
840 lit_vals[0] = fui(3.1415926535897f * 2.0f);
841 lit_vals[1] = fui(-3.1415926535897f);
842 } else {
843 lit_vals[0] = fui(1.0f);
844 lit_vals[1] = fui(-0.5f);
845 }
846
847 memset(&alu, 0, sizeof(struct r600_bc_alu));
848 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
849 alu.is_op3 = 1;
850
851 alu.dst.chan = 0;
852 alu.dst.sel = ctx->temp_reg;
853 alu.dst.write = 1;
854
855 alu.src[0].sel = ctx->temp_reg;
856 alu.src[0].chan = 0;
857
858 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
859 alu.src[1].chan = 0;
860 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
861 alu.src[2].chan = 1;
862 alu.last = 1;
863 r = r600_bc_add_alu(ctx->bc, &alu);
864 if (r)
865 return r;
866 r = r600_bc_add_literal(ctx->bc, lit_vals);
867 if (r)
868 return r;
869 return 0;
870 }
871
872 static int tgsi_trig(struct r600_shader_ctx *ctx)
873 {
874 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
875 struct r600_bc_alu_src r600_src[3];
876 struct r600_bc_alu alu;
877 int i, r;
878 int lasti = 0;
879
880 r = tgsi_setup_trig(ctx, r600_src);
881 if (r)
882 return r;
883
884 memset(&alu, 0, sizeof(struct r600_bc_alu));
885 alu.inst = ctx->inst_info->r600_opcode;
886 alu.dst.chan = 0;
887 alu.dst.sel = ctx->temp_reg;
888 alu.dst.write = 1;
889
890 alu.src[0].sel = ctx->temp_reg;
891 alu.src[0].chan = 0;
892 alu.last = 1;
893 r = r600_bc_add_alu(ctx->bc, &alu);
894 if (r)
895 return r;
896
897 /* replicate result */
898 for (i = 0; i < 4; i++) {
899 if (inst->Dst[0].Register.WriteMask & (1 << i))
900 lasti = i;
901 }
902 for (i = 0; i < lasti + 1; i++) {
903 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
904 continue;
905
906 memset(&alu, 0, sizeof(struct r600_bc_alu));
907 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
908
909 alu.src[0].sel = ctx->temp_reg;
910 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
911 if (r)
912 return r;
913 if (i == lasti)
914 alu.last = 1;
915 r = r600_bc_add_alu(ctx->bc, &alu);
916 if (r)
917 return r;
918 }
919 return 0;
920 }
921
922 static int tgsi_scs(struct r600_shader_ctx *ctx)
923 {
924 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
925 struct r600_bc_alu_src r600_src[3];
926 struct r600_bc_alu alu;
927 int r;
928
929 /* We'll only need the trig stuff if we are going to write to the
930 * X or Y components of the destination vector.
931 */
932 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
933 r = tgsi_setup_trig(ctx, r600_src);
934 if (r)
935 return r;
936 }
937
938 /* dst.x = COS */
939 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
940 memset(&alu, 0, sizeof(struct r600_bc_alu));
941 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
942 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
943 if (r)
944 return r;
945
946 alu.src[0].sel = ctx->temp_reg;
947 alu.src[0].chan = 0;
948 alu.last = 1;
949 r = r600_bc_add_alu(ctx->bc, &alu);
950 if (r)
951 return r;
952 }
953
954 /* dst.y = SIN */
955 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
956 memset(&alu, 0, sizeof(struct r600_bc_alu));
957 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
958 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
959 if (r)
960 return r;
961
962 alu.src[0].sel = ctx->temp_reg;
963 alu.src[0].chan = 0;
964 alu.last = 1;
965 r = r600_bc_add_alu(ctx->bc, &alu);
966 if (r)
967 return r;
968 }
969
970 /* dst.z = 0.0; */
971 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
972 memset(&alu, 0, sizeof(struct r600_bc_alu));
973
974 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
975
976 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
977 if (r)
978 return r;
979
980 alu.src[0].sel = V_SQ_ALU_SRC_0;
981 alu.src[0].chan = 0;
982
983 alu.last = 1;
984
985 r = r600_bc_add_alu(ctx->bc, &alu);
986 if (r)
987 return r;
988
989 r = r600_bc_add_literal(ctx->bc, ctx->value);
990 if (r)
991 return r;
992 }
993
994 /* dst.w = 1.0; */
995 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
996 memset(&alu, 0, sizeof(struct r600_bc_alu));
997
998 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
999
1000 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1001 if (r)
1002 return r;
1003
1004 alu.src[0].sel = V_SQ_ALU_SRC_1;
1005 alu.src[0].chan = 0;
1006
1007 alu.last = 1;
1008
1009 r = r600_bc_add_alu(ctx->bc, &alu);
1010 if (r)
1011 return r;
1012
1013 r = r600_bc_add_literal(ctx->bc, ctx->value);
1014 if (r)
1015 return r;
1016 }
1017
1018 return 0;
1019 }
1020
1021 static int tgsi_kill(struct r600_shader_ctx *ctx)
1022 {
1023 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1024 struct r600_bc_alu alu;
1025 int i, r;
1026
1027 for (i = 0; i < 4; i++) {
1028 memset(&alu, 0, sizeof(struct r600_bc_alu));
1029 alu.inst = ctx->inst_info->r600_opcode;
1030
1031 alu.dst.chan = i;
1032
1033 alu.src[0].sel = V_SQ_ALU_SRC_0;
1034
1035 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1036 alu.src[1].sel = V_SQ_ALU_SRC_1;
1037 alu.src[1].neg = 1;
1038 } else {
1039 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1040 if (r)
1041 return r;
1042 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1043 }
1044 if (i == 3) {
1045 alu.last = 1;
1046 }
1047 r = r600_bc_add_alu(ctx->bc, &alu);
1048 if (r)
1049 return r;
1050 }
1051 r = r600_bc_add_literal(ctx->bc, ctx->value);
1052 if (r)
1053 return r;
1054
1055 /* kill must be last in ALU */
1056 ctx->bc->force_add_cf = 1;
1057 ctx->shader->uses_kill = TRUE;
1058 return 0;
1059 }
1060
1061 static int tgsi_lit(struct r600_shader_ctx *ctx)
1062 {
1063 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1064 struct r600_bc_alu alu;
1065 struct r600_bc_alu_src r600_src[3];
1066 int r;
1067
1068 r = tgsi_split_constant(ctx, r600_src);
1069 if (r)
1070 return r;
1071 r = tgsi_split_literal_constant(ctx, r600_src);
1072 if (r)
1073 return r;
1074
1075 /* dst.x, <- 1.0 */
1076 memset(&alu, 0, sizeof(struct r600_bc_alu));
1077 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1078 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1079 alu.src[0].chan = 0;
1080 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1081 if (r)
1082 return r;
1083 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1084 r = r600_bc_add_alu(ctx->bc, &alu);
1085 if (r)
1086 return r;
1087
1088 /* dst.y = max(src.x, 0.0) */
1089 memset(&alu, 0, sizeof(struct r600_bc_alu));
1090 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1091 alu.src[0] = r600_src[0];
1092 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1093 alu.src[1].chan = 0;
1094 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1095 if (r)
1096 return r;
1097 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1098 r = r600_bc_add_alu(ctx->bc, &alu);
1099 if (r)
1100 return r;
1101
1102 /* dst.w, <- 1.0 */
1103 memset(&alu, 0, sizeof(struct r600_bc_alu));
1104 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1105 alu.src[0].sel = V_SQ_ALU_SRC_1;
1106 alu.src[0].chan = 0;
1107 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1108 if (r)
1109 return r;
1110 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1111 alu.last = 1;
1112 r = r600_bc_add_alu(ctx->bc, &alu);
1113 if (r)
1114 return r;
1115
1116 r = r600_bc_add_literal(ctx->bc, ctx->value);
1117 if (r)
1118 return r;
1119
1120 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1121 {
1122 int chan;
1123 int sel;
1124
1125 /* dst.z = log(src.y) */
1126 memset(&alu, 0, sizeof(struct r600_bc_alu));
1127 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1128 alu.src[0] = r600_src[0];
1129 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1130 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1131 if (r)
1132 return r;
1133 alu.last = 1;
1134 r = r600_bc_add_alu(ctx->bc, &alu);
1135 if (r)
1136 return r;
1137
1138 r = r600_bc_add_literal(ctx->bc, ctx->value);
1139 if (r)
1140 return r;
1141
1142 chan = alu.dst.chan;
1143 sel = alu.dst.sel;
1144
1145 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1146 memset(&alu, 0, sizeof(struct r600_bc_alu));
1147 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1148 alu.src[0] = r600_src[0];
1149 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1150 alu.src[1].sel = sel;
1151 alu.src[1].chan = chan;
1152
1153 alu.src[2] = r600_src[0];
1154 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1155 alu.dst.sel = ctx->temp_reg;
1156 alu.dst.chan = 0;
1157 alu.dst.write = 1;
1158 alu.is_op3 = 1;
1159 alu.last = 1;
1160 r = r600_bc_add_alu(ctx->bc, &alu);
1161 if (r)
1162 return r;
1163
1164 r = r600_bc_add_literal(ctx->bc, ctx->value);
1165 if (r)
1166 return r;
1167 /* dst.z = exp(tmp.x) */
1168 memset(&alu, 0, sizeof(struct r600_bc_alu));
1169 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1170 alu.src[0].sel = ctx->temp_reg;
1171 alu.src[0].chan = 0;
1172 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1173 if (r)
1174 return r;
1175 alu.last = 1;
1176 r = r600_bc_add_alu(ctx->bc, &alu);
1177 if (r)
1178 return r;
1179 }
1180 return 0;
1181 }
1182
1183 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1184 {
1185 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1186 struct r600_bc_alu alu;
1187 int i, r;
1188
1189 memset(&alu, 0, sizeof(struct r600_bc_alu));
1190
1191 /* FIXME:
1192 * For state trackers other than OpenGL, we'll want to use
1193 * _RECIPSQRT_IEEE instead.
1194 */
1195 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1196
1197 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1198 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1199 if (r)
1200 return r;
1201 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1202 alu.src[i].abs = 1;
1203 }
1204 alu.dst.sel = ctx->temp_reg;
1205 alu.dst.write = 1;
1206 alu.last = 1;
1207 r = r600_bc_add_alu(ctx->bc, &alu);
1208 if (r)
1209 return r;
1210 r = r600_bc_add_literal(ctx->bc, ctx->value);
1211 if (r)
1212 return r;
1213 /* replicate result */
1214 return tgsi_helper_tempx_replicate(ctx);
1215 }
1216
1217 static int tgsi_trans(struct r600_shader_ctx *ctx)
1218 {
1219 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1220 struct r600_bc_alu alu;
1221 int i, j, r;
1222
1223 for (i = 0; i < 4; i++) {
1224 memset(&alu, 0, sizeof(struct r600_bc_alu));
1225 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
1226 alu.inst = ctx->inst_info->r600_opcode;
1227 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1228 r = tgsi_src(ctx, &inst->Src[j], &alu.src[j]);
1229 if (r)
1230 return r;
1231 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1232 }
1233 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1234 if (r)
1235 return r;
1236 alu.last = 1;
1237 r = r600_bc_add_alu(ctx->bc, &alu);
1238 if (r)
1239 return r;
1240 }
1241 }
1242 return 0;
1243 }
1244
1245 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1246 {
1247 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1248 struct r600_bc_alu alu;
1249 int i, r;
1250
1251 for (i = 0; i < 4; i++) {
1252 memset(&alu, 0, sizeof(struct r600_bc_alu));
1253 alu.src[0].sel = ctx->temp_reg;
1254 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1255 alu.dst.chan = i;
1256 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1257 if (r)
1258 return r;
1259 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1260 if (i == 3)
1261 alu.last = 1;
1262 r = r600_bc_add_alu(ctx->bc, &alu);
1263 if (r)
1264 return r;
1265 }
1266 return 0;
1267 }
1268
1269 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1270 {
1271 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1272 struct r600_bc_alu alu;
1273 int i, r;
1274
1275 memset(&alu, 0, sizeof(struct r600_bc_alu));
1276 alu.inst = ctx->inst_info->r600_opcode;
1277 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1278 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1279 if (r)
1280 return r;
1281 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1282 }
1283 alu.dst.sel = ctx->temp_reg;
1284 alu.dst.write = 1;
1285 alu.last = 1;
1286 r = r600_bc_add_alu(ctx->bc, &alu);
1287 if (r)
1288 return r;
1289 r = r600_bc_add_literal(ctx->bc, ctx->value);
1290 if (r)
1291 return r;
1292 /* replicate result */
1293 return tgsi_helper_tempx_replicate(ctx);
1294 }
1295
1296 static int tgsi_pow(struct r600_shader_ctx *ctx)
1297 {
1298 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1299 struct r600_bc_alu alu;
1300 int r;
1301
1302 /* LOG2(a) */
1303 memset(&alu, 0, sizeof(struct r600_bc_alu));
1304 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1305 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1306 if (r)
1307 return r;
1308 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1309 alu.dst.sel = ctx->temp_reg;
1310 alu.dst.write = 1;
1311 alu.last = 1;
1312 r = r600_bc_add_alu(ctx->bc, &alu);
1313 if (r)
1314 return r;
1315 r = r600_bc_add_literal(ctx->bc,ctx->value);
1316 if (r)
1317 return r;
1318 /* b * LOG2(a) */
1319 memset(&alu, 0, sizeof(struct r600_bc_alu));
1320 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE);
1321 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1322 if (r)
1323 return r;
1324 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1325 alu.src[1].sel = ctx->temp_reg;
1326 alu.dst.sel = ctx->temp_reg;
1327 alu.dst.write = 1;
1328 alu.last = 1;
1329 r = r600_bc_add_alu(ctx->bc, &alu);
1330 if (r)
1331 return r;
1332 r = r600_bc_add_literal(ctx->bc,ctx->value);
1333 if (r)
1334 return r;
1335 /* POW(a,b) = EXP2(b * LOG2(a))*/
1336 memset(&alu, 0, sizeof(struct r600_bc_alu));
1337 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1338 alu.src[0].sel = ctx->temp_reg;
1339 alu.dst.sel = ctx->temp_reg;
1340 alu.dst.write = 1;
1341 alu.last = 1;
1342 r = r600_bc_add_alu(ctx->bc, &alu);
1343 if (r)
1344 return r;
1345 r = r600_bc_add_literal(ctx->bc,ctx->value);
1346 if (r)
1347 return r;
1348 return tgsi_helper_tempx_replicate(ctx);
1349 }
1350
1351 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1352 {
1353 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1354 struct r600_bc_alu alu;
1355 struct r600_bc_alu_src r600_src[3];
1356 int i, r;
1357
1358 r = tgsi_split_constant(ctx, r600_src);
1359 if (r)
1360 return r;
1361
1362 /* tmp = (src > 0 ? 1 : src) */
1363 for (i = 0; i < 4; i++) {
1364 memset(&alu, 0, sizeof(struct r600_bc_alu));
1365 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1366 alu.is_op3 = 1;
1367
1368 alu.dst.sel = ctx->temp_reg;
1369 alu.dst.chan = i;
1370
1371 alu.src[0] = r600_src[0];
1372 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1373
1374 alu.src[1].sel = V_SQ_ALU_SRC_1;
1375
1376 alu.src[2] = r600_src[0];
1377 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1378 if (i == 3)
1379 alu.last = 1;
1380 r = r600_bc_add_alu(ctx->bc, &alu);
1381 if (r)
1382 return r;
1383 }
1384 r = r600_bc_add_literal(ctx->bc, ctx->value);
1385 if (r)
1386 return r;
1387
1388 /* dst = (-tmp > 0 ? -1 : tmp) */
1389 for (i = 0; i < 4; i++) {
1390 memset(&alu, 0, sizeof(struct r600_bc_alu));
1391 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1392 alu.is_op3 = 1;
1393 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1394 if (r)
1395 return r;
1396
1397 alu.src[0].sel = ctx->temp_reg;
1398 alu.src[0].chan = i;
1399 alu.src[0].neg = 1;
1400
1401 alu.src[1].sel = V_SQ_ALU_SRC_1;
1402 alu.src[1].neg = 1;
1403
1404 alu.src[2].sel = ctx->temp_reg;
1405 alu.src[2].chan = i;
1406
1407 if (i == 3)
1408 alu.last = 1;
1409 r = r600_bc_add_alu(ctx->bc, &alu);
1410 if (r)
1411 return r;
1412 }
1413 return 0;
1414 }
1415
1416 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1417 {
1418 struct r600_bc_alu alu;
1419 int i, r;
1420
1421 r = r600_bc_add_literal(ctx->bc, ctx->value);
1422 if (r)
1423 return r;
1424 for (i = 0; i < 4; i++) {
1425 memset(&alu, 0, sizeof(struct r600_bc_alu));
1426 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1427 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1428 alu.dst.chan = i;
1429 } else {
1430 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1431 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1432 if (r)
1433 return r;
1434 alu.src[0].sel = ctx->temp_reg;
1435 alu.src[0].chan = i;
1436 }
1437 if (i == 3) {
1438 alu.last = 1;
1439 }
1440 r = r600_bc_add_alu(ctx->bc, &alu);
1441 if (r)
1442 return r;
1443 }
1444 return 0;
1445 }
1446
1447 static int tgsi_op3(struct r600_shader_ctx *ctx)
1448 {
1449 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1450 struct r600_bc_alu_src r600_src[3];
1451 struct r600_bc_alu alu;
1452 int i, j, r;
1453
1454 r = tgsi_split_constant(ctx, r600_src);
1455 if (r)
1456 return r;
1457 /* do it in 2 step as op3 doesn't support writemask */
1458 for (i = 0; i < 4; i++) {
1459 memset(&alu, 0, sizeof(struct r600_bc_alu));
1460 alu.inst = ctx->inst_info->r600_opcode;
1461 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1462 alu.src[j] = r600_src[j];
1463 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1464 }
1465 alu.dst.sel = ctx->temp_reg;
1466 alu.dst.chan = i;
1467 alu.dst.write = 1;
1468 alu.is_op3 = 1;
1469 if (i == 3) {
1470 alu.last = 1;
1471 }
1472 r = r600_bc_add_alu(ctx->bc, &alu);
1473 if (r)
1474 return r;
1475 }
1476 return tgsi_helper_copy(ctx, inst);
1477 }
1478
1479 static int tgsi_dp(struct r600_shader_ctx *ctx)
1480 {
1481 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1482 struct r600_bc_alu_src r600_src[3];
1483 struct r600_bc_alu alu;
1484 int i, j, r;
1485
1486 r = tgsi_split_constant(ctx, r600_src);
1487 if (r)
1488 return r;
1489 for (i = 0; i < 4; i++) {
1490 memset(&alu, 0, sizeof(struct r600_bc_alu));
1491 alu.inst = ctx->inst_info->r600_opcode;
1492 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1493 alu.src[j] = r600_src[j];
1494 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1495 }
1496 alu.dst.sel = ctx->temp_reg;
1497 alu.dst.chan = i;
1498 alu.dst.write = 1;
1499 /* handle some special cases */
1500 switch (ctx->inst_info->tgsi_opcode) {
1501 case TGSI_OPCODE_DP2:
1502 if (i > 1) {
1503 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1504 alu.src[0].chan = alu.src[1].chan = 0;
1505 }
1506 break;
1507 case TGSI_OPCODE_DP3:
1508 if (i > 2) {
1509 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1510 alu.src[0].chan = alu.src[1].chan = 0;
1511 }
1512 break;
1513 case TGSI_OPCODE_DPH:
1514 if (i == 3) {
1515 alu.src[0].sel = V_SQ_ALU_SRC_1;
1516 alu.src[0].chan = 0;
1517 alu.src[0].neg = 0;
1518 }
1519 break;
1520 default:
1521 break;
1522 }
1523 if (i == 3) {
1524 alu.last = 1;
1525 }
1526 r = r600_bc_add_alu(ctx->bc, &alu);
1527 if (r)
1528 return r;
1529 }
1530 return tgsi_helper_copy(ctx, inst);
1531 }
1532
1533 static int tgsi_tex(struct r600_shader_ctx *ctx)
1534 {
1535 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1536 struct r600_bc_tex tex;
1537 struct r600_bc_alu alu;
1538 unsigned src_gpr;
1539 int r, i;
1540 int opcode;
1541 boolean src_not_temp = inst->Src[0].Register.File != TGSI_FILE_TEMPORARY;
1542 uint32_t lit_vals[4];
1543
1544 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1545
1546 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1547 /* Add perspective divide */
1548 memset(&alu, 0, sizeof(struct r600_bc_alu));
1549 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1550 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1551 if (r)
1552 return r;
1553
1554 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1555 alu.dst.sel = ctx->temp_reg;
1556 alu.dst.chan = 3;
1557 alu.last = 1;
1558 alu.dst.write = 1;
1559 r = r600_bc_add_alu(ctx->bc, &alu);
1560 if (r)
1561 return r;
1562
1563 for (i = 0; i < 3; i++) {
1564 memset(&alu, 0, sizeof(struct r600_bc_alu));
1565 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1566 alu.src[0].sel = ctx->temp_reg;
1567 alu.src[0].chan = 3;
1568 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1569 if (r)
1570 return r;
1571 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1572 alu.dst.sel = ctx->temp_reg;
1573 alu.dst.chan = i;
1574 alu.dst.write = 1;
1575 r = r600_bc_add_alu(ctx->bc, &alu);
1576 if (r)
1577 return r;
1578 }
1579 memset(&alu, 0, sizeof(struct r600_bc_alu));
1580 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1581 alu.src[0].sel = V_SQ_ALU_SRC_1;
1582 alu.src[0].chan = 0;
1583 alu.dst.sel = ctx->temp_reg;
1584 alu.dst.chan = 3;
1585 alu.last = 1;
1586 alu.dst.write = 1;
1587 r = r600_bc_add_alu(ctx->bc, &alu);
1588 if (r)
1589 return r;
1590 src_not_temp = FALSE;
1591 src_gpr = ctx->temp_reg;
1592 }
1593
1594 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1595 int src_chan, src2_chan;
1596
1597 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1598 for (i = 0; i < 4; i++) {
1599 memset(&alu, 0, sizeof(struct r600_bc_alu));
1600 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1601 switch (i) {
1602 case 0:
1603 src_chan = 2;
1604 src2_chan = 1;
1605 break;
1606 case 1:
1607 src_chan = 2;
1608 src2_chan = 0;
1609 break;
1610 case 2:
1611 src_chan = 0;
1612 src2_chan = 2;
1613 break;
1614 case 3:
1615 src_chan = 1;
1616 src2_chan = 2;
1617 break;
1618 }
1619 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1620 if (r)
1621 return r;
1622 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1623 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1624 if (r)
1625 return r;
1626 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1627 alu.dst.sel = ctx->temp_reg;
1628 alu.dst.chan = i;
1629 if (i == 3)
1630 alu.last = 1;
1631 alu.dst.write = 1;
1632 r = r600_bc_add_alu(ctx->bc, &alu);
1633 if (r)
1634 return r;
1635 }
1636
1637 /* tmp1.z = RCP_e(|tmp1.z|) */
1638 memset(&alu, 0, sizeof(struct r600_bc_alu));
1639 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1640 alu.src[0].sel = ctx->temp_reg;
1641 alu.src[0].chan = 2;
1642 alu.src[0].abs = 1;
1643 alu.dst.sel = ctx->temp_reg;
1644 alu.dst.chan = 2;
1645 alu.dst.write = 1;
1646 alu.last = 1;
1647 r = r600_bc_add_alu(ctx->bc, &alu);
1648 if (r)
1649 return r;
1650
1651 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1652 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1653 * muladd has no writemask, have to use another temp
1654 */
1655 memset(&alu, 0, sizeof(struct r600_bc_alu));
1656 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1657 alu.is_op3 = 1;
1658
1659 alu.src[0].sel = ctx->temp_reg;
1660 alu.src[0].chan = 0;
1661 alu.src[1].sel = ctx->temp_reg;
1662 alu.src[1].chan = 2;
1663
1664 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1665 alu.src[2].chan = 0;
1666
1667 alu.dst.sel = ctx->temp_reg;
1668 alu.dst.chan = 0;
1669 alu.dst.write = 1;
1670
1671 r = r600_bc_add_alu(ctx->bc, &alu);
1672 if (r)
1673 return r;
1674
1675 memset(&alu, 0, sizeof(struct r600_bc_alu));
1676 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1677 alu.is_op3 = 1;
1678
1679 alu.src[0].sel = ctx->temp_reg;
1680 alu.src[0].chan = 1;
1681 alu.src[1].sel = ctx->temp_reg;
1682 alu.src[1].chan = 2;
1683
1684 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1685 alu.src[2].chan = 0;
1686
1687 alu.dst.sel = ctx->temp_reg;
1688 alu.dst.chan = 1;
1689 alu.dst.write = 1;
1690
1691 alu.last = 1;
1692 r = r600_bc_add_alu(ctx->bc, &alu);
1693 if (r)
1694 return r;
1695
1696 lit_vals[0] = fui(1.5f);
1697
1698 r = r600_bc_add_literal(ctx->bc, lit_vals);
1699 if (r)
1700 return r;
1701 src_not_temp = FALSE;
1702 src_gpr = ctx->temp_reg;
1703 }
1704
1705 if (src_not_temp) {
1706 for (i = 0; i < 4; i++) {
1707 memset(&alu, 0, sizeof(struct r600_bc_alu));
1708 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1709 alu.src[0].sel = src_gpr;
1710 alu.src[0].chan = i;
1711 alu.dst.sel = ctx->temp_reg;
1712 alu.dst.chan = i;
1713 if (i == 3)
1714 alu.last = 1;
1715 alu.dst.write = 1;
1716 r = r600_bc_add_alu(ctx->bc, &alu);
1717 if (r)
1718 return r;
1719 }
1720 src_gpr = ctx->temp_reg;
1721 }
1722
1723 opcode = ctx->inst_info->r600_opcode;
1724 if (opcode == SQ_TEX_INST_SAMPLE &&
1725 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1726 opcode = SQ_TEX_INST_SAMPLE_C;
1727
1728 memset(&tex, 0, sizeof(struct r600_bc_tex));
1729 tex.inst = opcode;
1730 tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1731 tex.sampler_id = tex.resource_id;
1732 tex.src_gpr = src_gpr;
1733 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1734 tex.dst_sel_x = 0;
1735 tex.dst_sel_y = 1;
1736 tex.dst_sel_z = 2;
1737 tex.dst_sel_w = 3;
1738 tex.src_sel_x = 0;
1739 tex.src_sel_y = 1;
1740 tex.src_sel_z = 2;
1741 tex.src_sel_w = 3;
1742
1743 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1744 tex.src_sel_x = 1;
1745 tex.src_sel_y = 0;
1746 tex.src_sel_z = 3;
1747 tex.src_sel_w = 1;
1748 }
1749
1750 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1751 tex.coord_type_x = 1;
1752 tex.coord_type_y = 1;
1753 tex.coord_type_z = 1;
1754 tex.coord_type_w = 1;
1755 }
1756
1757 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1758 tex.src_sel_w = 2;
1759
1760 r = r600_bc_add_tex(ctx->bc, &tex);
1761 if (r)
1762 return r;
1763
1764 /* add shadow ambient support - gallium doesn't do it yet */
1765 return 0;
1766
1767 }
1768
1769 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1770 {
1771 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1772 struct r600_bc_alu_src r600_src[3];
1773 struct r600_bc_alu alu;
1774 unsigned i;
1775 int r;
1776
1777 r = tgsi_split_constant(ctx, r600_src);
1778 if (r)
1779 return r;
1780 /* 1 - src0 */
1781 for (i = 0; i < 4; i++) {
1782 memset(&alu, 0, sizeof(struct r600_bc_alu));
1783 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1784 alu.src[0].sel = V_SQ_ALU_SRC_1;
1785 alu.src[0].chan = 0;
1786 alu.src[1] = r600_src[0];
1787 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1788 alu.src[1].neg = 1;
1789 alu.dst.sel = ctx->temp_reg;
1790 alu.dst.chan = i;
1791 if (i == 3) {
1792 alu.last = 1;
1793 }
1794 alu.dst.write = 1;
1795 r = r600_bc_add_alu(ctx->bc, &alu);
1796 if (r)
1797 return r;
1798 }
1799 r = r600_bc_add_literal(ctx->bc, ctx->value);
1800 if (r)
1801 return r;
1802
1803 /* (1 - src0) * src2 */
1804 for (i = 0; i < 4; i++) {
1805 memset(&alu, 0, sizeof(struct r600_bc_alu));
1806 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1807 alu.src[0].sel = ctx->temp_reg;
1808 alu.src[0].chan = i;
1809 alu.src[1] = r600_src[2];
1810 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1811 alu.dst.sel = ctx->temp_reg;
1812 alu.dst.chan = i;
1813 if (i == 3) {
1814 alu.last = 1;
1815 }
1816 alu.dst.write = 1;
1817 r = r600_bc_add_alu(ctx->bc, &alu);
1818 if (r)
1819 return r;
1820 }
1821 r = r600_bc_add_literal(ctx->bc, ctx->value);
1822 if (r)
1823 return r;
1824
1825 /* src0 * src1 + (1 - src0) * src2 */
1826 for (i = 0; i < 4; i++) {
1827 memset(&alu, 0, sizeof(struct r600_bc_alu));
1828 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1829 alu.is_op3 = 1;
1830 alu.src[0] = r600_src[0];
1831 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1832 alu.src[1] = r600_src[1];
1833 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1834 alu.src[2].sel = ctx->temp_reg;
1835 alu.src[2].chan = i;
1836 alu.dst.sel = ctx->temp_reg;
1837 alu.dst.chan = i;
1838 if (i == 3) {
1839 alu.last = 1;
1840 }
1841 r = r600_bc_add_alu(ctx->bc, &alu);
1842 if (r)
1843 return r;
1844 }
1845 return tgsi_helper_copy(ctx, inst);
1846 }
1847
1848 static int tgsi_cmp(struct r600_shader_ctx *ctx)
1849 {
1850 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1851 struct r600_bc_alu_src r600_src[3];
1852 struct r600_bc_alu alu;
1853 int use_temp = 0;
1854 int i, r;
1855
1856 r = tgsi_split_constant(ctx, r600_src);
1857 if (r)
1858 return r;
1859
1860 if (inst->Dst[0].Register.WriteMask != 0xf)
1861 use_temp = 1;
1862
1863 for (i = 0; i < 4; i++) {
1864 memset(&alu, 0, sizeof(struct r600_bc_alu));
1865 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
1866 alu.src[0] = r600_src[0];
1867 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1868
1869 alu.src[1] = r600_src[2];
1870 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1871
1872 alu.src[2] = r600_src[1];
1873 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
1874
1875 if (use_temp)
1876 alu.dst.sel = ctx->temp_reg;
1877 else {
1878 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1879 if (r)
1880 return r;
1881 }
1882 alu.dst.chan = i;
1883 alu.dst.write = 1;
1884 alu.is_op3 = 1;
1885 if (i == 3)
1886 alu.last = 1;
1887 r = r600_bc_add_alu(ctx->bc, &alu);
1888 if (r)
1889 return r;
1890 }
1891 if (use_temp)
1892 return tgsi_helper_copy(ctx, inst);
1893 return 0;
1894 }
1895
1896 static int tgsi_xpd(struct r600_shader_ctx *ctx)
1897 {
1898 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1899 struct r600_bc_alu_src r600_src[3];
1900 struct r600_bc_alu alu;
1901 uint32_t use_temp = 0;
1902 int i, r;
1903
1904 if (inst->Dst[0].Register.WriteMask != 0xf)
1905 use_temp = 1;
1906
1907 r = tgsi_split_constant(ctx, r600_src);
1908 if (r)
1909 return r;
1910
1911 for (i = 0; i < 4; i++) {
1912 memset(&alu, 0, sizeof(struct r600_bc_alu));
1913 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1914
1915 alu.src[0] = r600_src[0];
1916 switch (i) {
1917 case 0:
1918 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
1919 break;
1920 case 1:
1921 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1922 break;
1923 case 2:
1924 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1925 break;
1926 case 3:
1927 alu.src[0].sel = V_SQ_ALU_SRC_0;
1928 alu.src[0].chan = i;
1929 }
1930
1931 alu.src[1] = r600_src[1];
1932 switch (i) {
1933 case 0:
1934 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
1935 break;
1936 case 1:
1937 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
1938 break;
1939 case 2:
1940 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
1941 break;
1942 case 3:
1943 alu.src[1].sel = V_SQ_ALU_SRC_0;
1944 alu.src[1].chan = i;
1945 }
1946
1947 alu.dst.sel = ctx->temp_reg;
1948 alu.dst.chan = i;
1949 alu.dst.write = 1;
1950
1951 if (i == 3)
1952 alu.last = 1;
1953 r = r600_bc_add_alu(ctx->bc, &alu);
1954 if (r)
1955 return r;
1956
1957 r = r600_bc_add_literal(ctx->bc, ctx->value);
1958 if (r)
1959 return r;
1960 }
1961
1962 for (i = 0; i < 4; i++) {
1963 memset(&alu, 0, sizeof(struct r600_bc_alu));
1964 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1965
1966 alu.src[0] = r600_src[0];
1967 switch (i) {
1968 case 0:
1969 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1970 break;
1971 case 1:
1972 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
1973 break;
1974 case 2:
1975 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1976 break;
1977 case 3:
1978 alu.src[0].sel = V_SQ_ALU_SRC_0;
1979 alu.src[0].chan = i;
1980 }
1981
1982 alu.src[1] = r600_src[1];
1983 switch (i) {
1984 case 0:
1985 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
1986 break;
1987 case 1:
1988 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
1989 break;
1990 case 2:
1991 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
1992 break;
1993 case 3:
1994 alu.src[1].sel = V_SQ_ALU_SRC_0;
1995 alu.src[1].chan = i;
1996 }
1997
1998 alu.src[2].sel = ctx->temp_reg;
1999 alu.src[2].neg = 1;
2000 alu.src[2].chan = i;
2001
2002 if (use_temp)
2003 alu.dst.sel = ctx->temp_reg;
2004 else {
2005 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2006 if (r)
2007 return r;
2008 }
2009 alu.dst.chan = i;
2010 alu.dst.write = 1;
2011 alu.is_op3 = 1;
2012 if (i == 3)
2013 alu.last = 1;
2014 r = r600_bc_add_alu(ctx->bc, &alu);
2015 if (r)
2016 return r;
2017
2018 r = r600_bc_add_literal(ctx->bc, ctx->value);
2019 if (r)
2020 return r;
2021 }
2022 if (use_temp)
2023 return tgsi_helper_copy(ctx, inst);
2024 return 0;
2025 }
2026
2027 static int tgsi_exp(struct r600_shader_ctx *ctx)
2028 {
2029 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2030 struct r600_bc_alu_src r600_src[3];
2031 struct r600_bc_alu alu;
2032 int r;
2033
2034 /* result.x = 2^floor(src); */
2035 if (inst->Dst[0].Register.WriteMask & 1) {
2036 memset(&alu, 0, sizeof(struct r600_bc_alu));
2037
2038 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2039 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2040 if (r)
2041 return r;
2042
2043 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2044
2045 alu.dst.sel = ctx->temp_reg;
2046 alu.dst.chan = 0;
2047 alu.dst.write = 1;
2048 alu.last = 1;
2049 r = r600_bc_add_alu(ctx->bc, &alu);
2050 if (r)
2051 return r;
2052
2053 r = r600_bc_add_literal(ctx->bc, ctx->value);
2054 if (r)
2055 return r;
2056
2057 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2058 alu.src[0].sel = ctx->temp_reg;
2059 alu.src[0].chan = 0;
2060
2061 alu.dst.sel = ctx->temp_reg;
2062 alu.dst.chan = 0;
2063 alu.dst.write = 1;
2064 alu.last = 1;
2065 r = r600_bc_add_alu(ctx->bc, &alu);
2066 if (r)
2067 return r;
2068
2069 r = r600_bc_add_literal(ctx->bc, ctx->value);
2070 if (r)
2071 return r;
2072 }
2073
2074 /* result.y = tmp - floor(tmp); */
2075 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2076 memset(&alu, 0, sizeof(struct r600_bc_alu));
2077
2078 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2079 alu.src[0] = r600_src[0];
2080 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2081 if (r)
2082 return r;
2083 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2084
2085 alu.dst.sel = ctx->temp_reg;
2086 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2087 // if (r)
2088 // return r;
2089 alu.dst.write = 1;
2090 alu.dst.chan = 1;
2091
2092 alu.last = 1;
2093
2094 r = r600_bc_add_alu(ctx->bc, &alu);
2095 if (r)
2096 return r;
2097 r = r600_bc_add_literal(ctx->bc, ctx->value);
2098 if (r)
2099 return r;
2100 }
2101
2102 /* result.z = RoughApprox2ToX(tmp);*/
2103 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2104 memset(&alu, 0, sizeof(struct r600_bc_alu));
2105 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2106 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2107 if (r)
2108 return r;
2109 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2110
2111 alu.dst.sel = ctx->temp_reg;
2112 alu.dst.write = 1;
2113 alu.dst.chan = 2;
2114
2115 alu.last = 1;
2116
2117 r = r600_bc_add_alu(ctx->bc, &alu);
2118 if (r)
2119 return r;
2120 r = r600_bc_add_literal(ctx->bc, ctx->value);
2121 if (r)
2122 return r;
2123 }
2124
2125 /* result.w = 1.0;*/
2126 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2127 memset(&alu, 0, sizeof(struct r600_bc_alu));
2128
2129 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2130 alu.src[0].sel = V_SQ_ALU_SRC_1;
2131 alu.src[0].chan = 0;
2132
2133 alu.dst.sel = ctx->temp_reg;
2134 alu.dst.chan = 3;
2135 alu.dst.write = 1;
2136 alu.last = 1;
2137 r = r600_bc_add_alu(ctx->bc, &alu);
2138 if (r)
2139 return r;
2140 r = r600_bc_add_literal(ctx->bc, ctx->value);
2141 if (r)
2142 return r;
2143 }
2144 return tgsi_helper_copy(ctx, inst);
2145 }
2146
2147 static int tgsi_log(struct r600_shader_ctx *ctx)
2148 {
2149 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2150 struct r600_bc_alu alu;
2151 int r;
2152
2153 /* result.x = floor(log2(src)); */
2154 if (inst->Dst[0].Register.WriteMask & 1) {
2155 memset(&alu, 0, sizeof(struct r600_bc_alu));
2156
2157 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2158 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2159 if (r)
2160 return r;
2161
2162 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2163
2164 alu.dst.sel = ctx->temp_reg;
2165 alu.dst.chan = 0;
2166 alu.dst.write = 1;
2167 alu.last = 1;
2168 r = r600_bc_add_alu(ctx->bc, &alu);
2169 if (r)
2170 return r;
2171
2172 r = r600_bc_add_literal(ctx->bc, ctx->value);
2173 if (r)
2174 return r;
2175
2176 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2177 alu.src[0].sel = ctx->temp_reg;
2178 alu.src[0].chan = 0;
2179
2180 alu.dst.sel = ctx->temp_reg;
2181 alu.dst.chan = 0;
2182 alu.dst.write = 1;
2183 alu.last = 1;
2184
2185 r = r600_bc_add_alu(ctx->bc, &alu);
2186 if (r)
2187 return r;
2188
2189 r = r600_bc_add_literal(ctx->bc, ctx->value);
2190 if (r)
2191 return r;
2192 }
2193
2194 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2195 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2196 memset(&alu, 0, sizeof(struct r600_bc_alu));
2197
2198 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2199 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2200 if (r)
2201 return r;
2202
2203 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2204
2205 alu.dst.sel = ctx->temp_reg;
2206 alu.dst.chan = 1;
2207 alu.dst.write = 1;
2208 alu.last = 1;
2209
2210 r = r600_bc_add_alu(ctx->bc, &alu);
2211 if (r)
2212 return r;
2213
2214 r = r600_bc_add_literal(ctx->bc, ctx->value);
2215 if (r)
2216 return r;
2217
2218 memset(&alu, 0, sizeof(struct r600_bc_alu));
2219
2220 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2221 alu.src[0].sel = ctx->temp_reg;
2222 alu.src[0].chan = 1;
2223
2224 alu.dst.sel = ctx->temp_reg;
2225 alu.dst.chan = 1;
2226 alu.dst.write = 1;
2227 alu.last = 1;
2228
2229 r = r600_bc_add_alu(ctx->bc, &alu);
2230 if (r)
2231 return r;
2232
2233 r = r600_bc_add_literal(ctx->bc, ctx->value);
2234 if (r)
2235 return r;
2236
2237 memset(&alu, 0, sizeof(struct r600_bc_alu));
2238
2239 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2240 alu.src[0].sel = ctx->temp_reg;
2241 alu.src[0].chan = 1;
2242
2243 alu.dst.sel = ctx->temp_reg;
2244 alu.dst.chan = 1;
2245 alu.dst.write = 1;
2246 alu.last = 1;
2247
2248 r = r600_bc_add_alu(ctx->bc, &alu);
2249 if (r)
2250 return r;
2251
2252 r = r600_bc_add_literal(ctx->bc, ctx->value);
2253 if (r)
2254 return r;
2255
2256 memset(&alu, 0, sizeof(struct r600_bc_alu));
2257
2258 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2259 alu.src[0].sel = ctx->temp_reg;
2260 alu.src[0].chan = 1;
2261
2262 alu.dst.sel = ctx->temp_reg;
2263 alu.dst.chan = 1;
2264 alu.dst.write = 1;
2265 alu.last = 1;
2266
2267 r = r600_bc_add_alu(ctx->bc, &alu);
2268 if (r)
2269 return r;
2270
2271 r = r600_bc_add_literal(ctx->bc, ctx->value);
2272 if (r)
2273 return r;
2274
2275 memset(&alu, 0, sizeof(struct r600_bc_alu));
2276
2277 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2278
2279 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2280 if (r)
2281 return r;
2282
2283 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2284
2285 alu.src[1].sel = ctx->temp_reg;
2286 alu.src[1].chan = 1;
2287
2288 alu.dst.sel = ctx->temp_reg;
2289 alu.dst.chan = 1;
2290 alu.dst.write = 1;
2291 alu.last = 1;
2292
2293 r = r600_bc_add_alu(ctx->bc, &alu);
2294 if (r)
2295 return r;
2296
2297 r = r600_bc_add_literal(ctx->bc, ctx->value);
2298 if (r)
2299 return r;
2300 }
2301
2302 /* result.z = log2(src);*/
2303 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2304 memset(&alu, 0, sizeof(struct r600_bc_alu));
2305
2306 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2307 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2308 if (r)
2309 return r;
2310
2311 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2312
2313 alu.dst.sel = ctx->temp_reg;
2314 alu.dst.write = 1;
2315 alu.dst.chan = 2;
2316 alu.last = 1;
2317
2318 r = r600_bc_add_alu(ctx->bc, &alu);
2319 if (r)
2320 return r;
2321
2322 r = r600_bc_add_literal(ctx->bc, ctx->value);
2323 if (r)
2324 return r;
2325 }
2326
2327 /* result.w = 1.0; */
2328 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2329 memset(&alu, 0, sizeof(struct r600_bc_alu));
2330
2331 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2332 alu.src[0].sel = V_SQ_ALU_SRC_1;
2333 alu.src[0].chan = 0;
2334
2335 alu.dst.sel = ctx->temp_reg;
2336 alu.dst.chan = 3;
2337 alu.dst.write = 1;
2338 alu.last = 1;
2339
2340 r = r600_bc_add_alu(ctx->bc, &alu);
2341 if (r)
2342 return r;
2343
2344 r = r600_bc_add_literal(ctx->bc, ctx->value);
2345 if (r)
2346 return r;
2347 }
2348
2349 return tgsi_helper_copy(ctx, inst);
2350 }
2351
2352 /* r6/7 only for now */
2353 static int tgsi_arl(struct r600_shader_ctx *ctx)
2354 {
2355 /* TODO from r600c, ar values don't persist between clauses */
2356 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2357 struct r600_bc_alu alu;
2358 int r;
2359 memset(&alu, 0, sizeof(struct r600_bc_alu));
2360
2361 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2362
2363 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2364 if (r)
2365 return r;
2366 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2367
2368 alu.last = 1;
2369
2370 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2371 if (r)
2372 return r;
2373 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2374 return 0;
2375 }
2376
2377 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2378 {
2379 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2380 struct r600_bc_alu alu;
2381 int i, r = 0;
2382
2383 for (i = 0; i < 4; i++) {
2384 memset(&alu, 0, sizeof(struct r600_bc_alu));
2385
2386 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2387 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2388 if (r)
2389 return r;
2390
2391 if (i == 0 || i == 3) {
2392 alu.src[0].sel = V_SQ_ALU_SRC_1;
2393 } else {
2394 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2395 if (r)
2396 return r;
2397 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2398 }
2399
2400 if (i == 0 || i == 2) {
2401 alu.src[1].sel = V_SQ_ALU_SRC_1;
2402 } else {
2403 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2404 if (r)
2405 return r;
2406 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2407 }
2408 if (i == 3)
2409 alu.last = 1;
2410 r = r600_bc_add_alu(ctx->bc, &alu);
2411 if (r)
2412 return r;
2413 }
2414 return 0;
2415 }
2416
2417 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2418 {
2419 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2420 struct r600_bc_alu alu;
2421 int r;
2422
2423 memset(&alu, 0, sizeof(struct r600_bc_alu));
2424 alu.inst = opcode;
2425 alu.predicate = 1;
2426
2427 alu.dst.sel = ctx->temp_reg;
2428 alu.dst.write = 1;
2429 alu.dst.chan = 0;
2430
2431 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2432 if (r)
2433 return r;
2434 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2435 alu.src[1].sel = V_SQ_ALU_SRC_0;
2436 alu.src[1].chan = 0;
2437
2438 alu.last = 1;
2439
2440 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2441 if (r)
2442 return r;
2443 return 0;
2444 }
2445
2446 static int pops(struct r600_shader_ctx *ctx, int pops)
2447 {
2448 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2449 ctx->bc->cf_last->pop_count = pops;
2450 return 0;
2451 }
2452
2453 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2454 {
2455 switch(reason) {
2456 case FC_PUSH_VPM:
2457 ctx->bc->callstack[ctx->bc->call_sp].current--;
2458 break;
2459 case FC_PUSH_WQM:
2460 case FC_LOOP:
2461 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2462 break;
2463 case FC_REP:
2464 /* TOODO : for 16 vp asic should -= 2; */
2465 ctx->bc->callstack[ctx->bc->call_sp].current --;
2466 break;
2467 }
2468 }
2469
2470 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2471 {
2472 if (check_max_only) {
2473 int diff;
2474 switch (reason) {
2475 case FC_PUSH_VPM:
2476 diff = 1;
2477 break;
2478 case FC_PUSH_WQM:
2479 diff = 4;
2480 break;
2481 default:
2482 assert(0);
2483 diff = 0;
2484 }
2485 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2486 ctx->bc->callstack[ctx->bc->call_sp].max) {
2487 ctx->bc->callstack[ctx->bc->call_sp].max =
2488 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2489 }
2490 return;
2491 }
2492 switch (reason) {
2493 case FC_PUSH_VPM:
2494 ctx->bc->callstack[ctx->bc->call_sp].current++;
2495 break;
2496 case FC_PUSH_WQM:
2497 case FC_LOOP:
2498 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2499 break;
2500 case FC_REP:
2501 ctx->bc->callstack[ctx->bc->call_sp].current++;
2502 break;
2503 }
2504
2505 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2506 ctx->bc->callstack[ctx->bc->call_sp].max) {
2507 ctx->bc->callstack[ctx->bc->call_sp].max =
2508 ctx->bc->callstack[ctx->bc->call_sp].current;
2509 }
2510 }
2511
2512 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2513 {
2514 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2515
2516 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2517 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2518 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2519 sp->num_mid++;
2520 }
2521
2522 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2523 {
2524 ctx->bc->fc_sp++;
2525 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2526 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2527 }
2528
2529 static void fc_poplevel(struct r600_shader_ctx *ctx)
2530 {
2531 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2532 if (sp->mid) {
2533 free(sp->mid);
2534 sp->mid = NULL;
2535 }
2536 sp->num_mid = 0;
2537 sp->start = NULL;
2538 sp->type = 0;
2539 ctx->bc->fc_sp--;
2540 }
2541
2542 #if 0
2543 static int emit_return(struct r600_shader_ctx *ctx)
2544 {
2545 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2546 return 0;
2547 }
2548
2549 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2550 {
2551
2552 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2553 ctx->bc->cf_last->pop_count = pops;
2554 /* TODO work out offset */
2555 return 0;
2556 }
2557
2558 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2559 {
2560 return 0;
2561 }
2562
2563 static void emit_testflag(struct r600_shader_ctx *ctx)
2564 {
2565
2566 }
2567
2568 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2569 {
2570 emit_testflag(ctx);
2571 emit_jump_to_offset(ctx, 1, 4);
2572 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2573 pops(ctx, ifidx + 1);
2574 emit_return(ctx);
2575 }
2576
2577 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2578 {
2579 emit_testflag(ctx);
2580
2581 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2582 ctx->bc->cf_last->pop_count = 1;
2583
2584 fc_set_mid(ctx, fc_sp);
2585
2586 pops(ctx, 1);
2587 }
2588 #endif
2589
2590 static int tgsi_if(struct r600_shader_ctx *ctx)
2591 {
2592 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2593
2594 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2595
2596 fc_pushlevel(ctx, FC_IF);
2597
2598 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2599 return 0;
2600 }
2601
2602 static int tgsi_else(struct r600_shader_ctx *ctx)
2603 {
2604 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2605 ctx->bc->cf_last->pop_count = 1;
2606
2607 fc_set_mid(ctx, ctx->bc->fc_sp);
2608 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2609 return 0;
2610 }
2611
2612 static int tgsi_endif(struct r600_shader_ctx *ctx)
2613 {
2614 pops(ctx, 1);
2615 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2616 R600_ERR("if/endif unbalanced in shader\n");
2617 return -1;
2618 }
2619
2620 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2621 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2622 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2623 } else {
2624 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2625 }
2626 fc_poplevel(ctx);
2627
2628 callstack_decrease_current(ctx, FC_PUSH_VPM);
2629 return 0;
2630 }
2631
2632 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2633 {
2634 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2635
2636 fc_pushlevel(ctx, FC_LOOP);
2637
2638 /* check stack depth */
2639 callstack_check_depth(ctx, FC_LOOP, 0);
2640 return 0;
2641 }
2642
2643 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2644 {
2645 int i;
2646
2647 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2648
2649 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2650 R600_ERR("loop/endloop in shader code are not paired.\n");
2651 return -EINVAL;
2652 }
2653
2654 /* fixup loop pointers - from r600isa
2655 LOOP END points to CF after LOOP START,
2656 LOOP START point to CF after LOOP END
2657 BRK/CONT point to LOOP END CF
2658 */
2659 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2660
2661 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2662
2663 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2664 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2665 }
2666 /* TODO add LOOPRET support */
2667 fc_poplevel(ctx);
2668 callstack_decrease_current(ctx, FC_LOOP);
2669 return 0;
2670 }
2671
2672 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2673 {
2674 unsigned int fscp;
2675
2676 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2677 {
2678 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2679 break;
2680 }
2681
2682 if (fscp == 0) {
2683 R600_ERR("Break not inside loop/endloop pair\n");
2684 return -EINVAL;
2685 }
2686
2687 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2688 ctx->bc->cf_last->pop_count = 1;
2689
2690 fc_set_mid(ctx, fscp);
2691
2692 pops(ctx, 1);
2693 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2694 return 0;
2695 }
2696
2697 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2698 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_arl},
2699 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2700 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2701
2702 /* FIXME:
2703 * For state trackers other than OpenGL, we'll want to use
2704 * _RECIP_IEEE instead.
2705 */
2706 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2707
2708 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2709 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2710 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2711 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2712 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2713 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2714 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2715 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2716 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2717 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2718 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2719 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2720 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2721 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2722 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2723 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2724 /* gap */
2725 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2726 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2727 /* gap */
2728 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2729 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2730 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2731 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2732 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2733 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2734 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2735 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2736 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2737 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2738 /* gap */
2739 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2740 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2741 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2742 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2743 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2744 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2745 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2746 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2747 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2748 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2749 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2750 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2751 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2752 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2753 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2754 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2755 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2756 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2757 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2758 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2759 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2760 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2761 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2762 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2763 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2764 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2765 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2766 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2767 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2768 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2769 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2770 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2771 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2772 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2773 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2774 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2775 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2776 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2777 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2778 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2779 {TGSI_OPCODE_TXL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2780 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2781 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2782 /* gap */
2783 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2784 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2785 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2786 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2787 /* gap */
2788 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2789 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2790 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2791 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2792 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2793 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2794 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2795 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2796 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2797 /* gap */
2798 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2799 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2800 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2801 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2802 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2803 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2804 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2805 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2806 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2807 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2808 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2809 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2810 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2811 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2812 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2813 /* gap */
2814 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2815 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2816 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2817 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2818 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2819 /* gap */
2820 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2821 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2822 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2823 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2824 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2825 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2826 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2827 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2828 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2829 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2830 /* gap */
2831 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2832 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2833 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2834 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2835 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2836 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2837 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2838 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2839 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2840 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2841 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2842 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2843 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2844 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2845 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2846 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2847 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2848 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2849 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2850 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2851 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2852 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2853 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2854 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2855 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2856 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2857 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2858 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2859 };
2860
2861 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
2862 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2863 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2864 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2865 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
2866 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
2867 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2868 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2869 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2870 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2871 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2872 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2873 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2874 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2875 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2876 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2877 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2878 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2879 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2880 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2881 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2882 /* gap */
2883 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2884 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2885 /* gap */
2886 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2887 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2888 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2889 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2890 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2891 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2892 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2893 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2894 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2895 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2896 /* gap */
2897 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2898 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2899 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2900 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2901 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2902 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2903 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2904 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2905 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2906 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2907 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2908 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2909 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2910 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2911 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2912 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2913 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2914 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2915 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2916 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2917 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2918 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2919 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2920 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2921 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2922 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2923 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2924 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2925 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2926 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2927 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2928 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2929 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2930 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2931 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2932 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2933 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2934 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2935 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2936 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2937 {TGSI_OPCODE_TXL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2938 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2939 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2940 /* gap */
2941 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2942 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2943 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2944 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2945 /* gap */
2946 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2947 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2948 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2949 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2950 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2951 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2952 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2953 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2954 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2955 /* gap */
2956 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2957 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2958 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2959 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2960 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2961 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2962 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2963 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2964 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2965 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2966 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2967 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2968 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2969 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2970 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2971 /* gap */
2972 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2973 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2974 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2975 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2976 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2977 /* gap */
2978 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2979 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2980 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2981 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2982 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2983 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2984 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2985 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2986 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2987 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2988 /* gap */
2989 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2990 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2991 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2992 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2993 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2994 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2995 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2996 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2997 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2998 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2999 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3000 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3001 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3002 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3003 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3004 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3005 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3006 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3007 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3008 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3009 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3010 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3011 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3012 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3013 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3014 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3015 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3016 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3017 };