2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
30 #include "sb/sb_public.h"
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
43 Why CAYMAN got loops for lots of instructions is explained here.
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
63 static int r600_shader_from_tgsi(struct r600_context
*rctx
,
64 struct r600_pipe_shader
*pipeshader
,
65 struct r600_shader_key key
);
68 static void r600_add_gpr_array(struct r600_shader
*ps
, int start_gpr
,
69 int size
, unsigned comp_mask
) {
74 if (ps
->num_arrays
== ps
->max_arrays
) {
76 ps
->arrays
= realloc(ps
->arrays
, ps
->max_arrays
*
77 sizeof(struct r600_shader_array
));
80 int n
= ps
->num_arrays
;
83 ps
->arrays
[n
].comp_mask
= comp_mask
;
84 ps
->arrays
[n
].gpr_start
= start_gpr
;
85 ps
->arrays
[n
].gpr_count
= size
;
88 static void r600_dump_streamout(struct pipe_stream_output_info
*so
)
92 fprintf(stderr
, "STREAMOUT\n");
93 for (i
= 0; i
< so
->num_outputs
; i
++) {
94 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
95 so
->output
[i
].start_component
;
96 fprintf(stderr
, " %i: MEM_STREAM0_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
97 i
, so
->output
[i
].output_buffer
,
98 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
99 so
->output
[i
].register_index
,
104 so
->output
[i
].dst_offset
< so
->output
[i
].start_component
? " (will lower)" : "");
108 static int store_shader(struct pipe_context
*ctx
,
109 struct r600_pipe_shader
*shader
)
111 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
114 if (shader
->bo
== NULL
) {
115 shader
->bo
= (struct r600_resource
*)
116 pipe_buffer_create(ctx
->screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_IMMUTABLE
, shader
->shader
.bc
.ndw
* 4);
117 if (shader
->bo
== NULL
) {
120 ptr
= r600_buffer_map_sync_with_rings(&rctx
->b
, shader
->bo
, PIPE_TRANSFER_WRITE
);
121 if (R600_BIG_ENDIAN
) {
122 for (i
= 0; i
< shader
->shader
.bc
.ndw
; ++i
) {
123 ptr
[i
] = util_cpu_to_le32(shader
->shader
.bc
.bytecode
[i
]);
126 memcpy(ptr
, shader
->shader
.bc
.bytecode
, shader
->shader
.bc
.ndw
* sizeof(*ptr
));
128 rctx
->b
.ws
->buffer_unmap(shader
->bo
->cs_buf
);
134 int r600_pipe_shader_create(struct pipe_context
*ctx
,
135 struct r600_pipe_shader
*shader
,
136 struct r600_shader_key key
)
138 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
139 struct r600_pipe_shader_selector
*sel
= shader
->selector
;
141 bool dump
= r600_can_dump_shader(&rctx
->screen
->b
, sel
->tokens
);
142 unsigned use_sb
= !(rctx
->screen
->b
.debug_flags
& DBG_NO_SB
);
143 unsigned sb_disasm
= use_sb
|| (rctx
->screen
->b
.debug_flags
& DBG_SB_DISASM
);
144 unsigned export_shader
= key
.vs_as_es
;
146 shader
->shader
.bc
.isa
= rctx
->isa
;
149 fprintf(stderr
, "--------------------------------------------------------------\n");
150 tgsi_dump(sel
->tokens
, 0);
152 if (sel
->so
.num_outputs
) {
153 r600_dump_streamout(&sel
->so
);
156 r
= r600_shader_from_tgsi(rctx
, shader
, key
);
158 R600_ERR("translation from TGSI failed !\n");
162 /* disable SB for geom shaders - it can't handle the CF_EMIT instructions */
163 use_sb
&= (shader
->shader
.processor_type
!= TGSI_PROCESSOR_GEOMETRY
);
164 /* disable SB for shaders using CF_INDEX_0/1 (sampler/ubo array indexing) as it doesn't handle those currently */
165 use_sb
&= !shader
->shader
.uses_index_registers
;
167 /* Check if the bytecode has already been built. When using the llvm
168 * backend, r600_shader_from_tgsi() will take care of building the
171 if (!shader
->shader
.bc
.bytecode
) {
172 r
= r600_bytecode_build(&shader
->shader
.bc
);
174 R600_ERR("building bytecode failed !\n");
179 if (dump
&& !sb_disasm
) {
180 fprintf(stderr
, "--------------------------------------------------------------\n");
181 r600_bytecode_disasm(&shader
->shader
.bc
);
182 fprintf(stderr
, "______________________________________________________________\n");
183 } else if ((dump
&& sb_disasm
) || use_sb
) {
184 r
= r600_sb_bytecode_process(rctx
, &shader
->shader
.bc
, &shader
->shader
,
187 R600_ERR("r600_sb_bytecode_process failed !\n");
192 if (shader
->gs_copy_shader
) {
195 r
= r600_sb_bytecode_process(rctx
, &shader
->gs_copy_shader
->shader
.bc
,
196 &shader
->gs_copy_shader
->shader
, dump
, 0);
201 if ((r
= store_shader(ctx
, shader
->gs_copy_shader
)))
205 /* Store the shader in a buffer. */
206 if ((r
= store_shader(ctx
, shader
)))
210 switch (shader
->shader
.processor_type
) {
211 case TGSI_PROCESSOR_GEOMETRY
:
212 if (rctx
->b
.chip_class
>= EVERGREEN
) {
213 evergreen_update_gs_state(ctx
, shader
);
214 evergreen_update_vs_state(ctx
, shader
->gs_copy_shader
);
216 r600_update_gs_state(ctx
, shader
);
217 r600_update_vs_state(ctx
, shader
->gs_copy_shader
);
220 case TGSI_PROCESSOR_VERTEX
:
221 if (rctx
->b
.chip_class
>= EVERGREEN
) {
223 evergreen_update_es_state(ctx
, shader
);
225 evergreen_update_vs_state(ctx
, shader
);
228 r600_update_es_state(ctx
, shader
);
230 r600_update_vs_state(ctx
, shader
);
233 case TGSI_PROCESSOR_FRAGMENT
:
234 if (rctx
->b
.chip_class
>= EVERGREEN
) {
235 evergreen_update_ps_state(ctx
, shader
);
237 r600_update_ps_state(ctx
, shader
);
247 r600_pipe_shader_destroy(ctx
, shader
);
251 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
253 pipe_resource_reference((struct pipe_resource
**)&shader
->bo
, NULL
);
254 r600_bytecode_clear(&shader
->shader
.bc
);
255 r600_release_command_buffer(&shader
->command_buffer
);
259 * tgsi -> r600 shader
261 struct r600_shader_tgsi_instruction
;
263 struct r600_shader_src
{
270 boolean kc_rel
; /* true if cache bank is indexed */
279 struct r600_shader_ctx
{
280 struct tgsi_shader_info info
;
281 struct tgsi_parse_context parse
;
282 const struct tgsi_token
*tokens
;
284 unsigned file_offset
[TGSI_FILE_COUNT
];
286 struct r600_shader_tgsi_instruction
*inst_info
;
287 struct r600_bytecode
*bc
;
288 struct r600_shader
*shader
;
289 struct r600_shader_src src
[4];
292 uint32_t max_driver_temp_used
;
294 /* needed for evergreen interpolation */
295 struct eg_interp eg_interpolators
[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
296 /* evergreen/cayman also store sample mask in face register */
298 /* sample id is .w component stored in fixed point position register */
299 int fixed_pt_position_gpr
;
301 boolean clip_vertex_write
;
303 unsigned edgeflag_output
;
306 int next_ring_offset
;
307 int gs_out_ring_offset
;
309 struct r600_shader
*gs_for_vs
;
310 int gs_export_gpr_treg
;
313 struct r600_shader_tgsi_instruction
{
314 unsigned tgsi_opcode
;
317 int (*process
)(struct r600_shader_ctx
*ctx
);
320 static int emit_gs_ring_writes(struct r600_shader_ctx
*ctx
, bool ind
);
321 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[], eg_shader_tgsi_instruction
[], cm_shader_tgsi_instruction
[];
322 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
);
323 static inline void callstack_push(struct r600_shader_ctx
*ctx
, unsigned reason
);
324 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
);
325 static int tgsi_else(struct r600_shader_ctx
*ctx
);
326 static int tgsi_endif(struct r600_shader_ctx
*ctx
);
327 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
);
328 static int tgsi_endloop(struct r600_shader_ctx
*ctx
);
329 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
);
330 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
,
331 unsigned int cb_idx
, unsigned cb_rel
, unsigned int offset
, unsigned ar_chan
,
332 unsigned int dst_reg
);
333 static void r600_bytecode_src(struct r600_bytecode_alu_src
*bc_src
,
334 const struct r600_shader_src
*shader_src
,
337 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
339 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
342 if (i
->Instruction
.NumDstRegs
> 1) {
343 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
346 if (i
->Instruction
.Predicate
) {
347 R600_ERR("predicate unsupported\n");
351 if (i
->Instruction
.Label
) {
352 R600_ERR("label unsupported\n");
356 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
357 if (i
->Src
[j
].Register
.Dimension
) {
358 switch (i
->Src
[j
].Register
.File
) {
359 case TGSI_FILE_CONSTANT
:
361 case TGSI_FILE_INPUT
:
362 if (ctx
->type
== TGSI_PROCESSOR_GEOMETRY
)
365 R600_ERR("unsupported src %d (dimension %d)\n", j
,
366 i
->Src
[j
].Register
.Dimension
);
371 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
372 if (i
->Dst
[j
].Register
.Dimension
) {
373 R600_ERR("unsupported dst (dimension)\n");
380 int eg_get_interpolator_index(unsigned interpolate
, unsigned location
)
382 if (interpolate
== TGSI_INTERPOLATE_COLOR
||
383 interpolate
== TGSI_INTERPOLATE_LINEAR
||
384 interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
386 int is_linear
= interpolate
== TGSI_INTERPOLATE_LINEAR
;
390 case TGSI_INTERPOLATE_LOC_CENTER
:
393 case TGSI_INTERPOLATE_LOC_CENTROID
:
396 case TGSI_INTERPOLATE_LOC_SAMPLE
:
401 return is_linear
* 3 + loc
;
407 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx
*ctx
,
410 int i
= eg_get_interpolator_index(
411 ctx
->shader
->input
[input
].interpolate
,
412 ctx
->shader
->input
[input
].interpolate_location
);
414 ctx
->shader
->input
[input
].ij_index
= ctx
->eg_interpolators
[i
].ij_index
;
417 static int evergreen_interp_alu(struct r600_shader_ctx
*ctx
, int input
)
420 struct r600_bytecode_alu alu
;
421 int gpr
= 0, base_chan
= 0;
422 int ij_index
= ctx
->shader
->input
[input
].ij_index
;
424 /* work out gpr and base_chan from index */
426 base_chan
= (2 * (ij_index
% 2)) + 1;
428 for (i
= 0; i
< 8; i
++) {
429 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
432 alu
.op
= ALU_OP2_INTERP_ZW
;
434 alu
.op
= ALU_OP2_INTERP_XY
;
436 if ((i
> 1) && (i
< 6)) {
437 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
441 alu
.dst
.chan
= i
% 4;
443 alu
.src
[0].sel
= gpr
;
444 alu
.src
[0].chan
= (base_chan
- (i
% 2));
446 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
448 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
451 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
458 static int evergreen_interp_flat(struct r600_shader_ctx
*ctx
, int input
)
461 struct r600_bytecode_alu alu
;
463 for (i
= 0; i
< 4; i
++) {
464 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
466 alu
.op
= ALU_OP1_INTERP_LOAD_P0
;
468 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
473 alu
.src
[0].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
478 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
486 * Special export handling in shaders
488 * shader export ARRAY_BASE for EXPORT_POS:
491 * 62, 63 are clip distance vectors
493 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
494 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
495 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
496 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
497 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
498 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
499 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
500 * exclusive from render target index)
501 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
504 * shader export ARRAY_BASE for EXPORT_PIXEL:
506 * 61 computed Z vector
508 * The use of the values exported in the computed Z vector are controlled
509 * by DB_SHADER_CONTROL:
510 * Z_EXPORT_ENABLE - Z as a float in RED
511 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
512 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
513 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
514 * DB_SOURCE_FORMAT - export control restrictions
519 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
520 static int r600_spi_sid(struct r600_shader_io
* io
)
522 int index
, name
= io
->name
;
524 /* These params are handled differently, they don't need
525 * semantic indices, so we'll use 0 for them.
527 if (name
== TGSI_SEMANTIC_POSITION
||
528 name
== TGSI_SEMANTIC_PSIZE
||
529 name
== TGSI_SEMANTIC_EDGEFLAG
||
530 name
== TGSI_SEMANTIC_FACE
||
531 name
== TGSI_SEMANTIC_SAMPLEMASK
)
534 if (name
== TGSI_SEMANTIC_GENERIC
) {
535 /* For generic params simply use sid from tgsi */
538 /* For non-generic params - pack name and sid into 8 bits */
539 index
= 0x80 | (name
<<3) | (io
->sid
);
542 /* Make sure that all really used indices have nonzero value, so
543 * we can just compare it to 0 later instead of comparing the name
544 * with different values to detect special cases. */
551 /* turn input into interpolate on EG */
552 static int evergreen_interp_input(struct r600_shader_ctx
*ctx
, int index
)
556 if (ctx
->shader
->input
[index
].spi_sid
) {
557 ctx
->shader
->input
[index
].lds_pos
= ctx
->shader
->nlds
++;
558 if (ctx
->shader
->input
[index
].interpolate
> 0) {
559 evergreen_interp_assign_ij_index(ctx
, index
);
561 r
= evergreen_interp_alu(ctx
, index
);
564 r
= evergreen_interp_flat(ctx
, index
);
570 static int select_twoside_color(struct r600_shader_ctx
*ctx
, int front
, int back
)
572 struct r600_bytecode_alu alu
;
574 int gpr_front
= ctx
->shader
->input
[front
].gpr
;
575 int gpr_back
= ctx
->shader
->input
[back
].gpr
;
577 for (i
= 0; i
< 4; i
++) {
578 memset(&alu
, 0, sizeof(alu
));
579 alu
.op
= ALU_OP3_CNDGT
;
582 alu
.dst
.sel
= gpr_front
;
583 alu
.src
[0].sel
= ctx
->face_gpr
;
584 alu
.src
[1].sel
= gpr_front
;
585 alu
.src
[2].sel
= gpr_back
;
592 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
599 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
601 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
602 int r
, i
, j
, count
= d
->Range
.Last
- d
->Range
.First
+ 1;
604 switch (d
->Declaration
.File
) {
605 case TGSI_FILE_INPUT
:
606 i
= ctx
->shader
->ninput
;
607 assert(i
< Elements(ctx
->shader
->input
));
608 ctx
->shader
->ninput
+= count
;
609 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
610 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
;
611 ctx
->shader
->input
[i
].interpolate
= d
->Interp
.Interpolate
;
612 ctx
->shader
->input
[i
].interpolate_location
= d
->Interp
.Location
;
613 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + d
->Range
.First
;
614 if (ctx
->type
== TGSI_PROCESSOR_FRAGMENT
) {
615 ctx
->shader
->input
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->input
[i
]);
616 switch (ctx
->shader
->input
[i
].name
) {
617 case TGSI_SEMANTIC_FACE
:
618 if (ctx
->face_gpr
!= -1)
619 ctx
->shader
->input
[i
].gpr
= ctx
->face_gpr
; /* already allocated by allocate_system_value_inputs */
621 ctx
->face_gpr
= ctx
->shader
->input
[i
].gpr
;
623 case TGSI_SEMANTIC_COLOR
:
626 case TGSI_SEMANTIC_POSITION
:
627 ctx
->fragcoord_input
= i
;
630 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
631 if ((r
= evergreen_interp_input(ctx
, i
)))
634 } else if (ctx
->type
== TGSI_PROCESSOR_GEOMETRY
) {
635 /* FIXME probably skip inputs if they aren't passed in the ring */
636 ctx
->shader
->input
[i
].ring_offset
= ctx
->next_ring_offset
;
637 ctx
->next_ring_offset
+= 16;
638 if (ctx
->shader
->input
[i
].name
== TGSI_SEMANTIC_PRIMID
)
639 ctx
->shader
->gs_prim_id_input
= true;
641 for (j
= 1; j
< count
; ++j
) {
642 ctx
->shader
->input
[i
+ j
] = ctx
->shader
->input
[i
];
643 ctx
->shader
->input
[i
+ j
].gpr
+= j
;
646 case TGSI_FILE_OUTPUT
:
647 i
= ctx
->shader
->noutput
++;
648 assert(i
< Elements(ctx
->shader
->output
));
649 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
650 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
;
651 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + d
->Range
.First
;
652 ctx
->shader
->output
[i
].interpolate
= d
->Interp
.Interpolate
;
653 ctx
->shader
->output
[i
].write_mask
= d
->Declaration
.UsageMask
;
654 if (ctx
->type
== TGSI_PROCESSOR_VERTEX
||
655 ctx
->type
== TGSI_PROCESSOR_GEOMETRY
) {
656 ctx
->shader
->output
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->output
[i
]);
657 switch (d
->Semantic
.Name
) {
658 case TGSI_SEMANTIC_CLIPDIST
:
659 ctx
->shader
->clip_dist_write
|= d
->Declaration
.UsageMask
<< (d
->Semantic
.Index
<< 2);
661 case TGSI_SEMANTIC_PSIZE
:
662 ctx
->shader
->vs_out_misc_write
= 1;
663 ctx
->shader
->vs_out_point_size
= 1;
665 case TGSI_SEMANTIC_EDGEFLAG
:
666 ctx
->shader
->vs_out_misc_write
= 1;
667 ctx
->shader
->vs_out_edgeflag
= 1;
668 ctx
->edgeflag_output
= i
;
670 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
671 ctx
->shader
->vs_out_misc_write
= 1;
672 ctx
->shader
->vs_out_viewport
= 1;
674 case TGSI_SEMANTIC_LAYER
:
675 ctx
->shader
->vs_out_misc_write
= 1;
676 ctx
->shader
->vs_out_layer
= 1;
678 case TGSI_SEMANTIC_CLIPVERTEX
:
679 ctx
->clip_vertex_write
= TRUE
;
683 if (ctx
->type
== TGSI_PROCESSOR_GEOMETRY
) {
684 ctx
->gs_out_ring_offset
+= 16;
686 } else if (ctx
->type
== TGSI_PROCESSOR_FRAGMENT
) {
687 switch (d
->Semantic
.Name
) {
688 case TGSI_SEMANTIC_COLOR
:
689 ctx
->shader
->nr_ps_max_color_exports
++;
694 case TGSI_FILE_TEMPORARY
:
695 if (ctx
->info
.indirect_files
& (1 << TGSI_FILE_TEMPORARY
)) {
696 if (d
->Array
.ArrayID
) {
697 r600_add_gpr_array(ctx
->shader
,
698 ctx
->file_offset
[TGSI_FILE_TEMPORARY
] +
700 d
->Range
.Last
- d
->Range
.First
+ 1, 0x0F);
705 case TGSI_FILE_CONSTANT
:
706 case TGSI_FILE_SAMPLER
:
707 case TGSI_FILE_ADDRESS
:
710 case TGSI_FILE_SYSTEM_VALUE
:
711 if (d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEMASK
||
712 d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEID
||
713 d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEPOS
) {
714 break; /* Already handled from allocate_system_value_inputs */
715 } else if (d
->Semantic
.Name
== TGSI_SEMANTIC_INSTANCEID
) {
716 if (!ctx
->native_integers
) {
717 struct r600_bytecode_alu alu
;
718 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
720 alu
.op
= ALU_OP1_INT_TO_FLT
;
729 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
733 } else if (d
->Semantic
.Name
== TGSI_SEMANTIC_VERTEXID
)
735 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_INVOCATIONID
)
738 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
744 static int r600_get_temp(struct r600_shader_ctx
*ctx
)
746 return ctx
->temp_reg
+ ctx
->max_driver_temp_used
++;
749 static int allocate_system_value_inputs(struct r600_shader_ctx
*ctx
, int gpr_offset
)
751 struct tgsi_parse_context parse
;
755 unsigned name
, alternate_name
;
757 { false, &ctx
->face_gpr
, TGSI_SEMANTIC_SAMPLEMASK
, ~0u }, /* lives in Front Face GPR.z */
759 { false, &ctx
->fixed_pt_position_gpr
, TGSI_SEMANTIC_SAMPLEID
, TGSI_SEMANTIC_SAMPLEPOS
} /* SAMPLEID is in Fixed Point Position GPR.w */
761 int i
, k
, num_regs
= 0;
763 if (tgsi_parse_init(&parse
, ctx
->tokens
) != TGSI_PARSE_OK
) {
767 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
768 while (!tgsi_parse_end_of_tokens(&parse
)) {
769 tgsi_parse_token(&parse
);
771 if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_INSTRUCTION
) {
772 const struct tgsi_full_instruction
*inst
= &parse
.FullToken
.FullInstruction
;
773 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
||
774 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
775 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_CENTROID
)
777 int interpolate
, location
, k
;
779 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
780 location
= TGSI_INTERPOLATE_LOC_CENTER
;
781 inputs
[1].enabled
= true; /* needs SAMPLEID */
782 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
783 location
= TGSI_INTERPOLATE_LOC_CENTER
;
784 /* Needs sample positions, currently those are always available */
786 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
789 interpolate
= ctx
->info
.input_interpolate
[inst
->Src
[0].Register
.Index
];
790 k
= eg_get_interpolator_index(interpolate
, location
);
791 ctx
->eg_interpolators
[k
].enabled
= true;
793 } else if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_DECLARATION
) {
794 struct tgsi_full_declaration
*d
= &parse
.FullToken
.FullDeclaration
;
795 if (d
->Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
796 for (k
= 0; k
< Elements(inputs
); k
++) {
797 if (d
->Semantic
.Name
== inputs
[k
].name
||
798 d
->Semantic
.Name
== inputs
[k
].alternate_name
) {
799 inputs
[k
].enabled
= true;
806 tgsi_parse_free(&parse
);
808 for (i
= 0; i
< Elements(inputs
); i
++) {
809 boolean enabled
= inputs
[i
].enabled
;
810 int *reg
= inputs
[i
].reg
;
811 unsigned name
= inputs
[i
].name
;
814 int gpr
= gpr_offset
+ num_regs
++;
816 // add to inputs, allocate a gpr
817 k
= ctx
->shader
->ninput
++;
818 ctx
->shader
->input
[k
].name
= name
;
819 ctx
->shader
->input
[k
].sid
= 0;
820 ctx
->shader
->input
[k
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
821 ctx
->shader
->input
[k
].interpolate_location
= TGSI_INTERPOLATE_LOC_CENTER
;
822 *reg
= ctx
->shader
->input
[k
].gpr
= gpr
;
826 return gpr_offset
+ num_regs
;
830 * for evergreen we need to scan the shader to find the number of GPRs we need to
831 * reserve for interpolation and system values
833 * we need to know if we are going to emit
834 * any sample or centroid inputs
835 * if perspective and linear are required
837 static int evergreen_gpr_count(struct r600_shader_ctx
*ctx
)
841 struct tgsi_parse_context parse
;
843 memset(&ctx
->eg_interpolators
, 0, sizeof(ctx
->eg_interpolators
));
845 for (i
= 0; i
< ctx
->info
.num_inputs
; i
++) {
847 /* skip position/face/mask/sampleid */
848 if (ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_POSITION
||
849 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_FACE
||
850 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_SAMPLEMASK
||
851 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_SAMPLEID
)
854 k
= eg_get_interpolator_index(
855 ctx
->info
.input_interpolate
[i
],
856 ctx
->info
.input_interpolate_loc
[i
]);
858 ctx
->eg_interpolators
[k
].enabled
= TRUE
;
861 if (tgsi_parse_init(&parse
, ctx
->tokens
) != TGSI_PARSE_OK
) {
865 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
866 while (!tgsi_parse_end_of_tokens(&parse
)) {
867 tgsi_parse_token(&parse
);
869 if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_INSTRUCTION
) {
870 const struct tgsi_full_instruction
*inst
= &parse
.FullToken
.FullInstruction
;
871 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
||
872 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
873 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_CENTROID
)
875 int interpolate
, location
, k
;
877 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
878 location
= TGSI_INTERPOLATE_LOC_CENTER
;
879 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
880 location
= TGSI_INTERPOLATE_LOC_CENTER
;
882 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
885 interpolate
= ctx
->info
.input_interpolate
[inst
->Src
[0].Register
.Index
];
886 k
= eg_get_interpolator_index(interpolate
, location
);
887 ctx
->eg_interpolators
[k
].enabled
= true;
892 tgsi_parse_free(&parse
);
894 /* assign gpr to each interpolator according to priority */
896 for (i
= 0; i
< Elements(ctx
->eg_interpolators
); i
++) {
897 if (ctx
->eg_interpolators
[i
].enabled
) {
898 ctx
->eg_interpolators
[i
].ij_index
= num_baryc
;
903 /* XXX PULL MODEL and LINE STIPPLE */
905 num_baryc
= (num_baryc
+ 1) >> 1;
906 return allocate_system_value_inputs(ctx
, num_baryc
);
909 /* sample_id_sel == NULL means fetch for current sample */
910 static int load_sample_position(struct r600_shader_ctx
*ctx
, struct r600_shader_src
*sample_id
, int chan_sel
)
912 struct r600_bytecode_vtx vtx
;
915 assert(ctx
->fixed_pt_position_gpr
!= -1);
917 t1
= r600_get_temp(ctx
);
919 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
920 vtx
.op
= FETCH_OP_VFETCH
;
921 vtx
.buffer_id
= R600_SAMPLE_POSITIONS_CONST_BUFFER
;
922 vtx
.fetch_type
= 2; /* VTX_FETCH_NO_INDEX_OFFSET */
923 if (sample_id
== NULL
) {
924 vtx
.src_gpr
= ctx
->fixed_pt_position_gpr
; // SAMPLEID is in .w;
928 struct r600_bytecode_alu alu
;
930 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
931 alu
.op
= ALU_OP1_MOV
;
932 r600_bytecode_src(&alu
.src
[0], sample_id
, chan_sel
);
936 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
943 vtx
.mega_fetch_count
= 16;
949 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
950 vtx
.num_format_all
= 2;
951 vtx
.format_comp_all
= 1;
952 vtx
.use_const_fields
= 0;
953 vtx
.offset
= 1; // first element is size of buffer
954 vtx
.endian
= r600_endian_swap(32);
955 vtx
.srf_mode_all
= 1; /* SRF_MODE_NO_ZERO */
957 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
964 static void tgsi_src(struct r600_shader_ctx
*ctx
,
965 const struct tgsi_full_src_register
*tgsi_src
,
966 struct r600_shader_src
*r600_src
)
968 memset(r600_src
, 0, sizeof(*r600_src
));
969 r600_src
->swizzle
[0] = tgsi_src
->Register
.SwizzleX
;
970 r600_src
->swizzle
[1] = tgsi_src
->Register
.SwizzleY
;
971 r600_src
->swizzle
[2] = tgsi_src
->Register
.SwizzleZ
;
972 r600_src
->swizzle
[3] = tgsi_src
->Register
.SwizzleW
;
973 r600_src
->neg
= tgsi_src
->Register
.Negate
;
974 r600_src
->abs
= tgsi_src
->Register
.Absolute
;
976 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
978 if ((tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleY
) &&
979 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleZ
) &&
980 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleW
)) {
982 index
= tgsi_src
->Register
.Index
* 4 + tgsi_src
->Register
.SwizzleX
;
983 r600_bytecode_special_constants(ctx
->literals
[index
], &r600_src
->sel
, &r600_src
->neg
);
984 if (r600_src
->sel
!= V_SQ_ALU_SRC_LITERAL
)
987 index
= tgsi_src
->Register
.Index
;
988 r600_src
->sel
= V_SQ_ALU_SRC_LITERAL
;
989 memcpy(r600_src
->value
, ctx
->literals
+ index
* 4, sizeof(r600_src
->value
));
990 } else if (tgsi_src
->Register
.File
== TGSI_FILE_SYSTEM_VALUE
) {
991 if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEMASK
) {
992 r600_src
->swizzle
[0] = 2; // Z value
993 r600_src
->swizzle
[1] = 2;
994 r600_src
->swizzle
[2] = 2;
995 r600_src
->swizzle
[3] = 2;
996 r600_src
->sel
= ctx
->face_gpr
;
997 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEID
) {
998 r600_src
->swizzle
[0] = 3; // W value
999 r600_src
->swizzle
[1] = 3;
1000 r600_src
->swizzle
[2] = 3;
1001 r600_src
->swizzle
[3] = 3;
1002 r600_src
->sel
= ctx
->fixed_pt_position_gpr
;
1003 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEPOS
) {
1004 r600_src
->swizzle
[0] = 0;
1005 r600_src
->swizzle
[1] = 1;
1006 r600_src
->swizzle
[2] = 4;
1007 r600_src
->swizzle
[3] = 4;
1008 r600_src
->sel
= load_sample_position(ctx
, NULL
, -1);
1009 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INSTANCEID
) {
1010 r600_src
->swizzle
[0] = 3;
1011 r600_src
->swizzle
[1] = 3;
1012 r600_src
->swizzle
[2] = 3;
1013 r600_src
->swizzle
[3] = 3;
1015 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_VERTEXID
) {
1016 r600_src
->swizzle
[0] = 0;
1017 r600_src
->swizzle
[1] = 0;
1018 r600_src
->swizzle
[2] = 0;
1019 r600_src
->swizzle
[3] = 0;
1021 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INVOCATIONID
) {
1022 r600_src
->swizzle
[0] = 3;
1023 r600_src
->swizzle
[1] = 3;
1024 r600_src
->swizzle
[2] = 3;
1025 r600_src
->swizzle
[3] = 3;
1029 if (tgsi_src
->Register
.Indirect
)
1030 r600_src
->rel
= V_SQ_REL_RELATIVE
;
1031 r600_src
->sel
= tgsi_src
->Register
.Index
;
1032 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
1034 if (tgsi_src
->Register
.File
== TGSI_FILE_CONSTANT
) {
1035 if (tgsi_src
->Register
.Dimension
) {
1036 r600_src
->kc_bank
= tgsi_src
->Dimension
.Index
;
1037 if (tgsi_src
->Dimension
.Indirect
) {
1038 r600_src
->kc_rel
= 1;
1044 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
,
1045 unsigned int cb_idx
, unsigned cb_rel
, unsigned int offset
, unsigned ar_chan
,
1046 unsigned int dst_reg
)
1048 struct r600_bytecode_vtx vtx
;
1049 unsigned int ar_reg
;
1053 struct r600_bytecode_alu alu
;
1055 memset(&alu
, 0, sizeof(alu
));
1057 alu
.op
= ALU_OP2_ADD_INT
;
1058 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
1059 alu
.src
[0].chan
= ar_chan
;
1061 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1062 alu
.src
[1].value
= offset
;
1064 alu
.dst
.sel
= dst_reg
;
1065 alu
.dst
.chan
= ar_chan
;
1069 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1074 ar_reg
= ctx
->bc
->ar_reg
;
1077 memset(&vtx
, 0, sizeof(vtx
));
1078 vtx
.buffer_id
= cb_idx
;
1079 vtx
.fetch_type
= 2; /* VTX_FETCH_NO_INDEX_OFFSET */
1080 vtx
.src_gpr
= ar_reg
;
1081 vtx
.src_sel_x
= ar_chan
;
1082 vtx
.mega_fetch_count
= 16;
1083 vtx
.dst_gpr
= dst_reg
;
1084 vtx
.dst_sel_x
= 0; /* SEL_X */
1085 vtx
.dst_sel_y
= 1; /* SEL_Y */
1086 vtx
.dst_sel_z
= 2; /* SEL_Z */
1087 vtx
.dst_sel_w
= 3; /* SEL_W */
1088 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1089 vtx
.num_format_all
= 2; /* NUM_FORMAT_SCALED */
1090 vtx
.format_comp_all
= 1; /* FORMAT_COMP_SIGNED */
1091 vtx
.endian
= r600_endian_swap(32);
1092 vtx
.buffer_index_mode
= cb_rel
; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1094 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
1100 static int fetch_gs_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1102 struct r600_bytecode_vtx vtx
;
1104 unsigned index
= src
->Register
.Index
;
1105 unsigned vtx_id
= src
->Dimension
.Index
;
1106 int offset_reg
= vtx_id
/ 3;
1107 int offset_chan
= vtx_id
% 3;
1109 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1110 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1112 if (offset_reg
== 0 && offset_chan
== 2)
1115 if (src
->Dimension
.Indirect
) {
1118 struct r600_bytecode_alu alu
;
1121 /* you have got to be shitting me -
1122 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1123 at least this is what fglrx seems to do. */
1124 for (i
= 0; i
< 3; i
++) {
1125 treg
[i
] = r600_get_temp(ctx
);
1127 t2
= r600_get_temp(ctx
);
1128 for (i
= 0; i
< 3; i
++) {
1129 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1130 alu
.op
= ALU_OP1_MOV
;
1132 alu
.src
[0].chan
= i
== 2 ? 3 : i
;
1133 alu
.dst
.sel
= treg
[i
];
1137 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1141 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1142 alu
.op
= ALU_OP1_MOV
;
1143 alu
.src
[0].sel
= treg
[0];
1148 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1155 memset(&vtx
, 0, sizeof(vtx
));
1156 vtx
.buffer_id
= R600_GS_RING_CONST_BUFFER
;
1157 vtx
.fetch_type
= 2; /* VTX_FETCH_NO_INDEX_OFFSET */
1158 vtx
.src_gpr
= offset_reg
;
1159 vtx
.src_sel_x
= offset_chan
;
1160 vtx
.offset
= index
* 16; /*bytes*/
1161 vtx
.mega_fetch_count
= 16;
1162 vtx
.dst_gpr
= dst_reg
;
1163 vtx
.dst_sel_x
= 0; /* SEL_X */
1164 vtx
.dst_sel_y
= 1; /* SEL_Y */
1165 vtx
.dst_sel_z
= 2; /* SEL_Z */
1166 vtx
.dst_sel_w
= 3; /* SEL_W */
1167 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
1168 vtx
.use_const_fields
= 1;
1170 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1173 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
1179 static int tgsi_split_gs_inputs(struct r600_shader_ctx
*ctx
)
1181 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1184 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1185 struct tgsi_full_src_register
*src
= &inst
->Src
[i
];
1187 if (src
->Register
.File
== TGSI_FILE_INPUT
) {
1188 if (ctx
->shader
->input
[src
->Register
.Index
].name
== TGSI_SEMANTIC_PRIMID
) {
1189 /* primitive id is in R0.z */
1190 ctx
->src
[i
].sel
= 0;
1191 ctx
->src
[i
].swizzle
[0] = 2;
1194 if (src
->Register
.File
== TGSI_FILE_INPUT
&& src
->Register
.Dimension
) {
1195 int treg
= r600_get_temp(ctx
);
1197 fetch_gs_input(ctx
, src
, treg
);
1198 ctx
->src
[i
].sel
= treg
;
1204 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
)
1206 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1207 struct r600_bytecode_alu alu
;
1208 int i
, j
, k
, nconst
, r
;
1210 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1211 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
1214 tgsi_src(ctx
, &inst
->Src
[i
], &ctx
->src
[i
]);
1216 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1217 if (inst
->Src
[i
].Register
.File
!= TGSI_FILE_CONSTANT
) {
1221 if (ctx
->src
[i
].kc_rel
)
1222 ctx
->shader
->uses_index_registers
= true;
1224 if (ctx
->src
[i
].rel
) {
1225 int chan
= inst
->Src
[i
].Indirect
.Swizzle
;
1226 int treg
= r600_get_temp(ctx
);
1227 if ((r
= tgsi_fetch_rel_const(ctx
, ctx
->src
[i
].kc_bank
, ctx
->src
[i
].kc_rel
, ctx
->src
[i
].sel
- 512, chan
, treg
)))
1230 ctx
->src
[i
].kc_bank
= 0;
1231 ctx
->src
[i
].kc_rel
= 0;
1232 ctx
->src
[i
].sel
= treg
;
1233 ctx
->src
[i
].rel
= 0;
1236 int treg
= r600_get_temp(ctx
);
1237 for (k
= 0; k
< 4; k
++) {
1238 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1239 alu
.op
= ALU_OP1_MOV
;
1240 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
1241 alu
.src
[0].chan
= k
;
1242 alu
.src
[0].rel
= ctx
->src
[i
].rel
;
1243 alu
.src
[0].kc_bank
= ctx
->src
[i
].kc_bank
;
1244 alu
.src
[0].kc_rel
= ctx
->src
[i
].kc_rel
;
1250 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1254 ctx
->src
[i
].sel
= treg
;
1262 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1263 static int tgsi_split_literal_constant(struct r600_shader_ctx
*ctx
)
1265 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1266 struct r600_bytecode_alu alu
;
1267 int i
, j
, k
, nliteral
, r
;
1269 for (i
= 0, nliteral
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1270 if (ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1274 for (i
= 0, j
= nliteral
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1275 if (j
> 0 && ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1276 int treg
= r600_get_temp(ctx
);
1277 for (k
= 0; k
< 4; k
++) {
1278 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1279 alu
.op
= ALU_OP1_MOV
;
1280 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
1281 alu
.src
[0].chan
= k
;
1282 alu
.src
[0].value
= ctx
->src
[i
].value
[k
];
1288 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1292 ctx
->src
[i
].sel
= treg
;
1299 static int process_twoside_color_inputs(struct r600_shader_ctx
*ctx
)
1301 int i
, r
, count
= ctx
->shader
->ninput
;
1303 for (i
= 0; i
< count
; i
++) {
1304 if (ctx
->shader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
) {
1305 r
= select_twoside_color(ctx
, i
, ctx
->shader
->input
[i
].back_color_input
);
1313 static int emit_streamout(struct r600_shader_ctx
*ctx
, struct pipe_stream_output_info
*so
)
1315 unsigned so_gpr
[PIPE_MAX_SHADER_OUTPUTS
];
1318 /* Sanity checking. */
1319 if (so
->num_outputs
> PIPE_MAX_SHADER_OUTPUTS
) {
1320 R600_ERR("Too many stream outputs: %d\n", so
->num_outputs
);
1324 for (i
= 0; i
< so
->num_outputs
; i
++) {
1325 if (so
->output
[i
].output_buffer
>= 4) {
1326 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1327 so
->output
[i
].output_buffer
);
1333 /* Initialize locations where the outputs are stored. */
1334 for (i
= 0; i
< so
->num_outputs
; i
++) {
1335 so_gpr
[i
] = ctx
->shader
->output
[so
->output
[i
].register_index
].gpr
;
1337 /* Lower outputs with dst_offset < start_component.
1339 * We can only output 4D vectors with a write mask, e.g. we can
1340 * only output the W component at offset 3, etc. If we want
1341 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1342 * to move it to X and output X. */
1343 if (so
->output
[i
].dst_offset
< so
->output
[i
].start_component
) {
1344 unsigned tmp
= r600_get_temp(ctx
);
1346 for (j
= 0; j
< so
->output
[i
].num_components
; j
++) {
1347 struct r600_bytecode_alu alu
;
1348 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1349 alu
.op
= ALU_OP1_MOV
;
1350 alu
.src
[0].sel
= so_gpr
[i
];
1351 alu
.src
[0].chan
= so
->output
[i
].start_component
+ j
;
1356 if (j
== so
->output
[i
].num_components
- 1)
1358 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1362 so
->output
[i
].start_component
= 0;
1367 /* Write outputs to buffers. */
1368 for (i
= 0; i
< so
->num_outputs
; i
++) {
1369 struct r600_bytecode_output output
;
1371 memset(&output
, 0, sizeof(struct r600_bytecode_output
));
1372 output
.gpr
= so_gpr
[i
];
1373 output
.elem_size
= so
->output
[i
].num_components
;
1374 output
.array_base
= so
->output
[i
].dst_offset
- so
->output
[i
].start_component
;
1375 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE
;
1376 output
.burst_count
= 1;
1377 /* array_size is an upper limit for the burst_count
1378 * with MEM_STREAM instructions */
1379 output
.array_size
= 0xFFF;
1380 output
.comp_mask
= ((1 << so
->output
[i
].num_components
) - 1) << so
->output
[i
].start_component
;
1381 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
1382 switch (so
->output
[i
].output_buffer
) {
1384 output
.op
= CF_OP_MEM_STREAM0_BUF0
;
1387 output
.op
= CF_OP_MEM_STREAM0_BUF1
;
1390 output
.op
= CF_OP_MEM_STREAM0_BUF2
;
1393 output
.op
= CF_OP_MEM_STREAM0_BUF3
;
1397 switch (so
->output
[i
].output_buffer
) {
1399 output
.op
= CF_OP_MEM_STREAM0
;
1402 output
.op
= CF_OP_MEM_STREAM1
;
1405 output
.op
= CF_OP_MEM_STREAM2
;
1408 output
.op
= CF_OP_MEM_STREAM3
;
1412 r
= r600_bytecode_add_output(ctx
->bc
, &output
);
1421 static void convert_edgeflag_to_int(struct r600_shader_ctx
*ctx
)
1423 struct r600_bytecode_alu alu
;
1426 if (!ctx
->shader
->vs_out_edgeflag
)
1429 reg
= ctx
->shader
->output
[ctx
->edgeflag_output
].gpr
;
1431 /* clamp(x, 0, 1) */
1432 memset(&alu
, 0, sizeof(alu
));
1433 alu
.op
= ALU_OP1_MOV
;
1434 alu
.src
[0].sel
= reg
;
1439 r600_bytecode_add_alu(ctx
->bc
, &alu
);
1441 memset(&alu
, 0, sizeof(alu
));
1442 alu
.op
= ALU_OP1_FLT_TO_INT
;
1443 alu
.src
[0].sel
= reg
;
1447 r600_bytecode_add_alu(ctx
->bc
, &alu
);
1450 static int generate_gs_copy_shader(struct r600_context
*rctx
,
1451 struct r600_pipe_shader
*gs
,
1452 struct pipe_stream_output_info
*so
)
1454 struct r600_shader_ctx ctx
= {};
1455 struct r600_shader
*gs_shader
= &gs
->shader
;
1456 struct r600_pipe_shader
*cshader
;
1457 int ocnt
= gs_shader
->noutput
;
1458 struct r600_bytecode_alu alu
;
1459 struct r600_bytecode_vtx vtx
;
1460 struct r600_bytecode_output output
;
1461 struct r600_bytecode_cf
*cf_jump
, *cf_pop
,
1462 *last_exp_pos
= NULL
, *last_exp_param
= NULL
;
1463 int i
, next_clip_pos
= 61, next_param
= 0;
1465 cshader
= calloc(1, sizeof(struct r600_pipe_shader
));
1469 memcpy(cshader
->shader
.output
, gs_shader
->output
, ocnt
*
1470 sizeof(struct r600_shader_io
));
1472 cshader
->shader
.noutput
= ocnt
;
1474 ctx
.shader
= &cshader
->shader
;
1475 ctx
.bc
= &ctx
.shader
->bc
;
1476 ctx
.type
= ctx
.bc
->type
= TGSI_PROCESSOR_VERTEX
;
1478 r600_bytecode_init(ctx
.bc
, rctx
->b
.chip_class
, rctx
->b
.family
,
1479 rctx
->screen
->has_compressed_msaa_texturing
);
1481 ctx
.bc
->isa
= rctx
->isa
;
1483 /* R0.x = R0.x & 0x3fffffff */
1484 memset(&alu
, 0, sizeof(alu
));
1485 alu
.op
= ALU_OP2_AND_INT
;
1486 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1487 alu
.src
[1].value
= 0x3fffffff;
1489 r600_bytecode_add_alu(ctx
.bc
, &alu
);
1491 /* R0.y = R0.x >> 30 */
1492 memset(&alu
, 0, sizeof(alu
));
1493 alu
.op
= ALU_OP2_LSHR_INT
;
1494 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1495 alu
.src
[1].value
= 0x1e;
1499 r600_bytecode_add_alu(ctx
.bc
, &alu
);
1501 /* PRED_SETE_INT __, R0.y, 0 */
1502 memset(&alu
, 0, sizeof(alu
));
1503 alu
.op
= ALU_OP2_PRED_SETE_INT
;
1504 alu
.src
[0].chan
= 1;
1505 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1506 alu
.execute_mask
= 1;
1507 alu
.update_pred
= 1;
1509 r600_bytecode_add_alu_type(ctx
.bc
, &alu
, CF_OP_ALU_PUSH_BEFORE
);
1511 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_JUMP
);
1512 cf_jump
= ctx
.bc
->cf_last
;
1514 /* fetch vertex data from GSVS ring */
1515 for (i
= 0; i
< ocnt
; ++i
) {
1516 struct r600_shader_io
*out
= &ctx
.shader
->output
[i
];
1518 out
->ring_offset
= i
* 16;
1520 memset(&vtx
, 0, sizeof(vtx
));
1521 vtx
.op
= FETCH_OP_VFETCH
;
1522 vtx
.buffer_id
= R600_GS_RING_CONST_BUFFER
;
1524 vtx
.offset
= out
->ring_offset
;
1525 vtx
.dst_gpr
= out
->gpr
;
1530 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1531 vtx
.use_const_fields
= 1;
1533 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1536 r600_bytecode_add_vtx(ctx
.bc
, &vtx
);
1539 /* XXX handle clipvertex, streamout? */
1540 emit_streamout(&ctx
, so
);
1542 /* export vertex data */
1543 /* XXX factor out common code with r600_shader_from_tgsi ? */
1544 for (i
= 0; i
< ocnt
; ++i
) {
1545 struct r600_shader_io
*out
= &ctx
.shader
->output
[i
];
1547 if (out
->name
== TGSI_SEMANTIC_CLIPVERTEX
)
1550 memset(&output
, 0, sizeof(output
));
1551 output
.gpr
= out
->gpr
;
1552 output
.elem_size
= 3;
1553 output
.swizzle_x
= 0;
1554 output
.swizzle_y
= 1;
1555 output
.swizzle_z
= 2;
1556 output
.swizzle_w
= 3;
1557 output
.burst_count
= 1;
1558 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
1559 output
.op
= CF_OP_EXPORT
;
1560 switch (out
->name
) {
1561 case TGSI_SEMANTIC_POSITION
:
1562 output
.array_base
= 60;
1563 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
1566 case TGSI_SEMANTIC_PSIZE
:
1567 output
.array_base
= 61;
1568 if (next_clip_pos
== 61)
1570 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
1571 output
.swizzle_y
= 7;
1572 output
.swizzle_z
= 7;
1573 output
.swizzle_w
= 7;
1574 ctx
.shader
->vs_out_misc_write
= 1;
1575 ctx
.shader
->vs_out_point_size
= 1;
1577 case TGSI_SEMANTIC_LAYER
:
1579 /* duplicate it as PARAM to pass to the pixel shader */
1580 output
.array_base
= next_param
++;
1581 r600_bytecode_add_output(ctx
.bc
, &output
);
1582 last_exp_param
= ctx
.bc
->cf_last
;
1584 output
.array_base
= 61;
1585 if (next_clip_pos
== 61)
1587 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
1588 output
.swizzle_x
= 7;
1589 output
.swizzle_y
= 7;
1590 output
.swizzle_z
= 0;
1591 output
.swizzle_w
= 7;
1592 ctx
.shader
->vs_out_misc_write
= 1;
1593 ctx
.shader
->vs_out_layer
= 1;
1595 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
1597 /* duplicate it as PARAM to pass to the pixel shader */
1598 output
.array_base
= next_param
++;
1599 r600_bytecode_add_output(ctx
.bc
, &output
);
1600 last_exp_param
= ctx
.bc
->cf_last
;
1602 output
.array_base
= 61;
1603 if (next_clip_pos
== 61)
1605 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
1606 ctx
.shader
->vs_out_misc_write
= 1;
1607 ctx
.shader
->vs_out_viewport
= 1;
1608 output
.swizzle_x
= 7;
1609 output
.swizzle_y
= 7;
1610 output
.swizzle_z
= 7;
1611 output
.swizzle_w
= 0;
1613 case TGSI_SEMANTIC_CLIPDIST
:
1614 /* spi_sid is 0 for clipdistance outputs that were generated
1615 * for clipvertex - we don't need to pass them to PS */
1616 ctx
.shader
->clip_dist_write
= gs
->shader
.clip_dist_write
;
1618 /* duplicate it as PARAM to pass to the pixel shader */
1619 output
.array_base
= next_param
++;
1620 r600_bytecode_add_output(ctx
.bc
, &output
);
1621 last_exp_param
= ctx
.bc
->cf_last
;
1623 output
.array_base
= next_clip_pos
++;
1624 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
1626 case TGSI_SEMANTIC_FOG
:
1627 output
.swizzle_y
= 4; /* 0 */
1628 output
.swizzle_z
= 4; /* 0 */
1629 output
.swizzle_w
= 5; /* 1 */
1632 output
.array_base
= next_param
++;
1635 r600_bytecode_add_output(ctx
.bc
, &output
);
1636 if (output
.type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
)
1637 last_exp_param
= ctx
.bc
->cf_last
;
1639 last_exp_pos
= ctx
.bc
->cf_last
;
1642 if (!last_exp_pos
) {
1643 memset(&output
, 0, sizeof(output
));
1645 output
.elem_size
= 3;
1646 output
.swizzle_x
= 7;
1647 output
.swizzle_y
= 7;
1648 output
.swizzle_z
= 7;
1649 output
.swizzle_w
= 7;
1650 output
.burst_count
= 1;
1652 output
.op
= CF_OP_EXPORT
;
1653 output
.array_base
= 60;
1654 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
1655 r600_bytecode_add_output(ctx
.bc
, &output
);
1656 last_exp_pos
= ctx
.bc
->cf_last
;
1659 if (!last_exp_param
) {
1660 memset(&output
, 0, sizeof(output
));
1662 output
.elem_size
= 3;
1663 output
.swizzle_x
= 7;
1664 output
.swizzle_y
= 7;
1665 output
.swizzle_z
= 7;
1666 output
.swizzle_w
= 7;
1667 output
.burst_count
= 1;
1669 output
.op
= CF_OP_EXPORT
;
1670 output
.array_base
= next_param
++;
1671 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
1672 r600_bytecode_add_output(ctx
.bc
, &output
);
1673 last_exp_param
= ctx
.bc
->cf_last
;
1676 last_exp_pos
->op
= CF_OP_EXPORT_DONE
;
1677 last_exp_param
->op
= CF_OP_EXPORT_DONE
;
1679 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_POP
);
1680 cf_pop
= ctx
.bc
->cf_last
;
1682 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
1683 cf_jump
->pop_count
= 1;
1684 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
1685 cf_pop
->pop_count
= 1;
1687 if (ctx
.bc
->chip_class
== CAYMAN
)
1688 cm_bytecode_add_cf_end(ctx
.bc
);
1690 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
1691 ctx
.bc
->cf_last
->end_of_program
= 1;
1694 gs
->gs_copy_shader
= cshader
;
1697 cshader
->shader
.ring_item_size
= ocnt
* 16;
1699 return r600_bytecode_build(ctx
.bc
);
1702 static int emit_gs_ring_writes(struct r600_shader_ctx
*ctx
, bool ind
)
1704 struct r600_bytecode_output output
;
1705 int i
, k
, ring_offset
;
1707 for (i
= 0; i
< ctx
->shader
->noutput
; i
++) {
1708 if (ctx
->gs_for_vs
) {
1709 /* for ES we need to lookup corresponding ring offset expected by GS
1710 * (map this output to GS input by name and sid) */
1711 /* FIXME precompute offsets */
1713 for(k
= 0; k
< ctx
->gs_for_vs
->ninput
; ++k
) {
1714 struct r600_shader_io
*in
= &ctx
->gs_for_vs
->input
[k
];
1715 struct r600_shader_io
*out
= &ctx
->shader
->output
[i
];
1716 if (in
->name
== out
->name
&& in
->sid
== out
->sid
)
1717 ring_offset
= in
->ring_offset
;
1720 if (ring_offset
== -1)
1723 ring_offset
= i
* 16;
1725 /* next_ring_offset after parsing input decls contains total size of
1726 * single vertex data, gs_next_vertex - current vertex index */
1728 ring_offset
+= ctx
->gs_out_ring_offset
* ctx
->gs_next_vertex
;
1730 /* get a temp and add the ring offset to the next vertex base in the shader */
1731 memset(&output
, 0, sizeof(struct r600_bytecode_output
));
1732 output
.gpr
= ctx
->shader
->output
[i
].gpr
;
1733 output
.elem_size
= 3;
1734 output
.comp_mask
= 0xF;
1735 output
.burst_count
= 1;
1738 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND
;
1740 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE
;
1741 output
.op
= CF_OP_MEM_RING
;
1745 output
.array_base
= ring_offset
>> 2; /* in dwords */
1746 output
.array_size
= 0xfff;
1747 output
.index_gpr
= ctx
->gs_export_gpr_treg
;
1749 output
.array_base
= ring_offset
>> 2; /* in dwords */
1750 r600_bytecode_add_output(ctx
->bc
, &output
);
1754 struct r600_bytecode_alu alu
;
1757 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1758 alu
.op
= ALU_OP2_ADD_INT
;
1759 alu
.src
[0].sel
= ctx
->gs_export_gpr_treg
;
1760 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1761 alu
.src
[1].value
= ctx
->gs_out_ring_offset
>> 4;
1762 alu
.dst
.sel
= ctx
->gs_export_gpr_treg
;
1765 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1769 ++ctx
->gs_next_vertex
;
1773 static int r600_shader_from_tgsi(struct r600_context
*rctx
,
1774 struct r600_pipe_shader
*pipeshader
,
1775 struct r600_shader_key key
)
1777 struct r600_screen
*rscreen
= rctx
->screen
;
1778 struct r600_shader
*shader
= &pipeshader
->shader
;
1779 struct tgsi_token
*tokens
= pipeshader
->selector
->tokens
;
1780 struct pipe_stream_output_info so
= pipeshader
->selector
->so
;
1781 struct tgsi_full_immediate
*immediate
;
1782 struct tgsi_full_property
*property
;
1783 struct r600_shader_ctx ctx
;
1784 struct r600_bytecode_output output
[32];
1785 unsigned output_done
, noutput
;
1788 int next_param_base
= 0, next_clip_base
;
1789 int max_color_exports
= MAX2(key
.nr_cbufs
, 1);
1790 /* Declarations used by llvm code */
1791 bool use_llvm
= false;
1793 bool ring_outputs
= false;
1794 bool pos_emitted
= false;
1796 #ifdef R600_USE_LLVM
1797 use_llvm
= rscreen
->b
.debug_flags
& DBG_LLVM
;
1799 ctx
.bc
= &shader
->bc
;
1800 ctx
.shader
= shader
;
1801 ctx
.native_integers
= true;
1803 shader
->vs_as_es
= key
.vs_as_es
;
1805 r600_bytecode_init(ctx
.bc
, rscreen
->b
.chip_class
, rscreen
->b
.family
,
1806 rscreen
->has_compressed_msaa_texturing
);
1807 ctx
.tokens
= tokens
;
1808 tgsi_scan_shader(tokens
, &ctx
.info
);
1809 shader
->indirect_files
= ctx
.info
.indirect_files
;
1810 indirect_gprs
= ctx
.info
.indirect_files
& ~(1 << TGSI_FILE_CONSTANT
);
1811 tgsi_parse_init(&ctx
.parse
, tokens
);
1812 ctx
.type
= ctx
.parse
.FullHeader
.Processor
.Processor
;
1813 shader
->processor_type
= ctx
.type
;
1814 ctx
.bc
->type
= shader
->processor_type
;
1816 ring_outputs
= key
.vs_as_es
|| (ctx
.type
== TGSI_PROCESSOR_GEOMETRY
);
1819 ctx
.gs_for_vs
= &rctx
->gs_shader
->current
->shader
;
1821 ctx
.gs_for_vs
= NULL
;
1824 ctx
.next_ring_offset
= 0;
1825 ctx
.gs_out_ring_offset
= 0;
1826 ctx
.gs_next_vertex
= 0;
1828 shader
->uses_index_registers
= false;
1830 ctx
.fixed_pt_position_gpr
= -1;
1831 ctx
.fragcoord_input
= -1;
1832 ctx
.colors_used
= 0;
1833 ctx
.clip_vertex_write
= 0;
1835 shader
->nr_ps_color_exports
= 0;
1836 shader
->nr_ps_max_color_exports
= 0;
1838 shader
->two_side
= key
.color_two_side
;
1840 /* register allocations */
1841 /* Values [0,127] correspond to GPR[0..127].
1842 * Values [128,159] correspond to constant buffer bank 0
1843 * Values [160,191] correspond to constant buffer bank 1
1844 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
1845 * Values [256,287] correspond to constant buffer bank 2 (EG)
1846 * Values [288,319] correspond to constant buffer bank 3 (EG)
1847 * Other special values are shown in the list below.
1848 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
1849 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
1850 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
1851 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
1852 * 248 SQ_ALU_SRC_0: special constant 0.0.
1853 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
1854 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
1855 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
1856 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1857 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1858 * 254 SQ_ALU_SRC_PV: previous vector result.
1859 * 255 SQ_ALU_SRC_PS: previous scalar result.
1861 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
1862 ctx
.file_offset
[i
] = 0;
1865 #ifdef R600_USE_LLVM
1866 if (use_llvm
&& ctx
.info
.indirect_files
&& (ctx
.info
.indirect_files
& (1 << TGSI_FILE_CONSTANT
)) != ctx
.info
.indirect_files
) {
1867 fprintf(stderr
, "Warning: R600 LLVM backend does not support "
1868 "indirect adressing. Falling back to TGSI "
1873 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
1874 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
1876 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_CALL_FS
);
1879 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
) {
1880 if (ctx
.bc
->chip_class
>= EVERGREEN
)
1881 ctx
.file_offset
[TGSI_FILE_INPUT
] = evergreen_gpr_count(&ctx
);
1883 ctx
.file_offset
[TGSI_FILE_INPUT
] = allocate_system_value_inputs(&ctx
, ctx
.file_offset
[TGSI_FILE_INPUT
]);
1885 if (ctx
.type
== TGSI_PROCESSOR_GEOMETRY
) {
1886 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
1887 ctx
.file_offset
[TGSI_FILE_INPUT
] = 2;
1889 ctx
.use_llvm
= use_llvm
;
1892 ctx
.file_offset
[TGSI_FILE_OUTPUT
] =
1893 ctx
.file_offset
[TGSI_FILE_INPUT
];
1895 ctx
.file_offset
[TGSI_FILE_OUTPUT
] =
1896 ctx
.file_offset
[TGSI_FILE_INPUT
] +
1897 ctx
.info
.file_max
[TGSI_FILE_INPUT
] + 1;
1899 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
1900 ctx
.info
.file_max
[TGSI_FILE_OUTPUT
] + 1;
1902 /* Outside the GPR range. This will be translated to one of the
1903 * kcache banks later. */
1904 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 512;
1906 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = V_SQ_ALU_SRC_LITERAL
;
1907 ctx
.bc
->ar_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
1908 ctx
.info
.file_max
[TGSI_FILE_TEMPORARY
] + 1;
1909 if (ctx
.type
== TGSI_PROCESSOR_GEOMETRY
) {
1910 ctx
.gs_export_gpr_treg
= ctx
.bc
->ar_reg
+ 1;
1911 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 2;
1912 ctx
.bc
->index_reg
[0] = ctx
.bc
->ar_reg
+ 3;
1913 ctx
.bc
->index_reg
[1] = ctx
.bc
->ar_reg
+ 4;
1915 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 1;
1916 ctx
.bc
->index_reg
[0] = ctx
.bc
->ar_reg
+ 2;
1917 ctx
.bc
->index_reg
[1] = ctx
.bc
->ar_reg
+ 3;
1920 if (indirect_gprs
) {
1921 shader
->max_arrays
= 0;
1922 shader
->num_arrays
= 0;
1924 if (ctx
.info
.indirect_files
& (1 << TGSI_FILE_INPUT
)) {
1925 r600_add_gpr_array(shader
, ctx
.file_offset
[TGSI_FILE_INPUT
],
1926 ctx
.file_offset
[TGSI_FILE_OUTPUT
] -
1927 ctx
.file_offset
[TGSI_FILE_INPUT
],
1930 if (ctx
.info
.indirect_files
& (1 << TGSI_FILE_OUTPUT
)) {
1931 r600_add_gpr_array(shader
, ctx
.file_offset
[TGSI_FILE_OUTPUT
],
1932 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] -
1933 ctx
.file_offset
[TGSI_FILE_OUTPUT
],
1939 ctx
.literals
= NULL
;
1940 shader
->fs_write_all
= FALSE
;
1941 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
1942 tgsi_parse_token(&ctx
.parse
);
1943 switch (ctx
.parse
.FullToken
.Token
.Type
) {
1944 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1945 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
1946 ctx
.literals
= realloc(ctx
.literals
, (ctx
.nliterals
+ 1) * 16);
1947 if(ctx
.literals
== NULL
) {
1951 ctx
.literals
[ctx
.nliterals
* 4 + 0] = immediate
->u
[0].Uint
;
1952 ctx
.literals
[ctx
.nliterals
* 4 + 1] = immediate
->u
[1].Uint
;
1953 ctx
.literals
[ctx
.nliterals
* 4 + 2] = immediate
->u
[2].Uint
;
1954 ctx
.literals
[ctx
.nliterals
* 4 + 3] = immediate
->u
[3].Uint
;
1957 case TGSI_TOKEN_TYPE_DECLARATION
:
1958 r
= tgsi_declaration(&ctx
);
1962 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1964 case TGSI_TOKEN_TYPE_PROPERTY
:
1965 property
= &ctx
.parse
.FullToken
.FullProperty
;
1966 switch (property
->Property
.PropertyName
) {
1967 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
:
1968 if (property
->u
[0].Data
== 1)
1969 shader
->fs_write_all
= TRUE
;
1971 case TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
:
1972 if (property
->u
[0].Data
== 1)
1973 shader
->vs_position_window_space
= TRUE
;
1975 case TGSI_PROPERTY_VS_PROHIBIT_UCPS
:
1976 /* we don't need this one */
1978 case TGSI_PROPERTY_GS_INPUT_PRIM
:
1979 shader
->gs_input_prim
= property
->u
[0].Data
;
1981 case TGSI_PROPERTY_GS_OUTPUT_PRIM
:
1982 shader
->gs_output_prim
= property
->u
[0].Data
;
1984 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
:
1985 shader
->gs_max_out_vertices
= property
->u
[0].Data
;
1987 case TGSI_PROPERTY_GS_INVOCATIONS
:
1988 shader
->gs_num_invocations
= property
->u
[0].Data
;
1993 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
1999 shader
->ring_item_size
= ctx
.next_ring_offset
;
2001 /* Process two side if needed */
2002 if (shader
->two_side
&& ctx
.colors_used
) {
2003 int i
, count
= ctx
.shader
->ninput
;
2004 unsigned next_lds_loc
= ctx
.shader
->nlds
;
2006 /* additional inputs will be allocated right after the existing inputs,
2007 * we won't need them after the color selection, so we don't need to
2008 * reserve these gprs for the rest of the shader code and to adjust
2009 * output offsets etc. */
2010 int gpr
= ctx
.file_offset
[TGSI_FILE_INPUT
] +
2011 ctx
.info
.file_max
[TGSI_FILE_INPUT
] + 1;
2013 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
2014 if (ctx
.face_gpr
== -1) {
2015 i
= ctx
.shader
->ninput
++;
2016 ctx
.shader
->input
[i
].name
= TGSI_SEMANTIC_FACE
;
2017 ctx
.shader
->input
[i
].spi_sid
= 0;
2018 ctx
.shader
->input
[i
].gpr
= gpr
++;
2019 ctx
.face_gpr
= ctx
.shader
->input
[i
].gpr
;
2022 for (i
= 0; i
< count
; i
++) {
2023 if (ctx
.shader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
) {
2024 int ni
= ctx
.shader
->ninput
++;
2025 memcpy(&ctx
.shader
->input
[ni
],&ctx
.shader
->input
[i
], sizeof(struct r600_shader_io
));
2026 ctx
.shader
->input
[ni
].name
= TGSI_SEMANTIC_BCOLOR
;
2027 ctx
.shader
->input
[ni
].spi_sid
= r600_spi_sid(&ctx
.shader
->input
[ni
]);
2028 ctx
.shader
->input
[ni
].gpr
= gpr
++;
2029 // TGSI to LLVM needs to know the lds position of inputs.
2030 // Non LLVM path computes it later (in process_twoside_color)
2031 ctx
.shader
->input
[ni
].lds_pos
= next_lds_loc
++;
2032 ctx
.shader
->input
[i
].back_color_input
= ni
;
2033 if (ctx
.bc
->chip_class
>= EVERGREEN
) {
2034 if ((r
= evergreen_interp_input(&ctx
, ni
)))
2041 /* LLVM backend setup */
2042 #ifdef R600_USE_LLVM
2044 struct radeon_llvm_context radeon_llvm_ctx
;
2046 bool dump
= r600_can_dump_shader(&rscreen
->b
, tokens
);
2047 boolean use_kill
= false;
2049 memset(&radeon_llvm_ctx
, 0, sizeof(radeon_llvm_ctx
));
2050 radeon_llvm_ctx
.type
= ctx
.type
;
2051 radeon_llvm_ctx
.two_side
= shader
->two_side
;
2052 radeon_llvm_ctx
.face_gpr
= ctx
.face_gpr
;
2053 radeon_llvm_ctx
.inputs_count
= ctx
.shader
->ninput
+ 1;
2054 radeon_llvm_ctx
.r600_inputs
= ctx
.shader
->input
;
2055 radeon_llvm_ctx
.r600_outputs
= ctx
.shader
->output
;
2056 radeon_llvm_ctx
.color_buffer_count
= max_color_exports
;
2057 radeon_llvm_ctx
.chip_class
= ctx
.bc
->chip_class
;
2058 radeon_llvm_ctx
.fs_color_all
= shader
->fs_write_all
&& (rscreen
->b
.chip_class
>= EVERGREEN
);
2059 radeon_llvm_ctx
.stream_outputs
= &so
;
2060 radeon_llvm_ctx
.clip_vertex
= ctx
.cv_output
;
2061 radeon_llvm_ctx
.alpha_to_one
= key
.alpha_to_one
;
2062 radeon_llvm_ctx
.has_compressed_msaa_texturing
=
2063 ctx
.bc
->has_compressed_msaa_texturing
;
2064 mod
= r600_tgsi_llvm(&radeon_llvm_ctx
, tokens
);
2065 ctx
.shader
->has_txq_cube_array_z_comp
= radeon_llvm_ctx
.has_txq_cube_array_z_comp
;
2066 ctx
.shader
->uses_tex_buffers
= radeon_llvm_ctx
.uses_tex_buffers
;
2068 if (r600_llvm_compile(mod
, rscreen
->b
.family
, ctx
.bc
, &use_kill
, dump
)) {
2069 radeon_llvm_dispose(&radeon_llvm_ctx
);
2071 fprintf(stderr
, "R600 LLVM backend failed to compile "
2072 "shader. Falling back to TGSI\n");
2074 ctx
.file_offset
[TGSI_FILE_OUTPUT
] =
2075 ctx
.file_offset
[TGSI_FILE_INPUT
];
2078 ctx
.shader
->uses_kill
= use_kill
;
2079 radeon_llvm_dispose(&radeon_llvm_ctx
);
2082 /* End of LLVM backend setup */
2084 if (shader
->fs_write_all
&& rscreen
->b
.chip_class
>= EVERGREEN
)
2085 shader
->nr_ps_max_color_exports
= 8;
2088 if (ctx
.fragcoord_input
>= 0) {
2089 if (ctx
.bc
->chip_class
== CAYMAN
) {
2090 for (j
= 0 ; j
< 4; j
++) {
2091 struct r600_bytecode_alu alu
;
2092 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2093 alu
.op
= ALU_OP1_RECIP_IEEE
;
2094 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
2095 alu
.src
[0].chan
= 3;
2097 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
2099 alu
.dst
.write
= (j
== 3);
2101 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
2105 struct r600_bytecode_alu alu
;
2106 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2107 alu
.op
= ALU_OP1_RECIP_IEEE
;
2108 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
2109 alu
.src
[0].chan
= 3;
2111 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
2115 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
2120 if (ctx
.type
== TGSI_PROCESSOR_GEOMETRY
) {
2121 struct r600_bytecode_alu alu
;
2124 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2125 alu
.op
= ALU_OP1_MOV
;
2126 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
2127 alu
.src
[0].value
= 0;
2128 alu
.dst
.sel
= ctx
.gs_export_gpr_treg
;
2131 r
= r600_bytecode_add_alu(ctx
.bc
, &alu
);
2135 if (shader
->two_side
&& ctx
.colors_used
) {
2136 if ((r
= process_twoside_color_inputs(&ctx
)))
2140 tgsi_parse_init(&ctx
.parse
, tokens
);
2141 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
2142 tgsi_parse_token(&ctx
.parse
);
2143 switch (ctx
.parse
.FullToken
.Token
.Type
) {
2144 case TGSI_TOKEN_TYPE_INSTRUCTION
:
2145 r
= tgsi_is_supported(&ctx
);
2148 ctx
.max_driver_temp_used
= 0;
2149 /* reserve first tmp for everyone */
2150 r600_get_temp(&ctx
);
2152 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
2153 if ((r
= tgsi_split_constant(&ctx
)))
2155 if ((r
= tgsi_split_literal_constant(&ctx
)))
2157 if (ctx
.type
== TGSI_PROCESSOR_GEOMETRY
)
2158 if ((r
= tgsi_split_gs_inputs(&ctx
)))
2160 if (ctx
.bc
->chip_class
== CAYMAN
)
2161 ctx
.inst_info
= &cm_shader_tgsi_instruction
[opcode
];
2162 else if (ctx
.bc
->chip_class
>= EVERGREEN
)
2163 ctx
.inst_info
= &eg_shader_tgsi_instruction
[opcode
];
2165 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
2166 r
= ctx
.inst_info
->process(&ctx
);
2176 /* Reset the temporary register counter. */
2177 ctx
.max_driver_temp_used
= 0;
2179 noutput
= shader
->noutput
;
2181 if (!ring_outputs
&& ctx
.clip_vertex_write
) {
2182 unsigned clipdist_temp
[2];
2184 clipdist_temp
[0] = r600_get_temp(&ctx
);
2185 clipdist_temp
[1] = r600_get_temp(&ctx
);
2187 /* need to convert a clipvertex write into clipdistance writes and not export
2188 the clip vertex anymore */
2190 memset(&shader
->output
[noutput
], 0, 2*sizeof(struct r600_shader_io
));
2191 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
2192 shader
->output
[noutput
].gpr
= clipdist_temp
[0];
2194 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
2195 shader
->output
[noutput
].gpr
= clipdist_temp
[1];
2198 /* reset spi_sid for clipvertex output to avoid confusing spi */
2199 shader
->output
[ctx
.cv_output
].spi_sid
= 0;
2201 shader
->clip_dist_write
= 0xFF;
2203 for (i
= 0; i
< 8; i
++) {
2207 for (j
= 0; j
< 4; j
++) {
2208 struct r600_bytecode_alu alu
;
2209 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2210 alu
.op
= ALU_OP2_DOT4
;
2211 alu
.src
[0].sel
= shader
->output
[ctx
.cv_output
].gpr
;
2212 alu
.src
[0].chan
= j
;
2214 alu
.src
[1].sel
= 512 + i
;
2215 alu
.src
[1].kc_bank
= R600_UCP_CONST_BUFFER
;
2216 alu
.src
[1].chan
= j
;
2218 alu
.dst
.sel
= clipdist_temp
[oreg
];
2220 alu
.dst
.write
= (j
== ochan
);
2224 r
= r600_bytecode_add_alu(ctx
.bc
, &alu
);
2231 /* Add stream outputs. */
2232 if (!ring_outputs
&& ctx
.type
== TGSI_PROCESSOR_VERTEX
&&
2233 so
.num_outputs
&& !use_llvm
)
2234 emit_streamout(&ctx
, &so
);
2236 convert_edgeflag_to_int(&ctx
);
2240 emit_gs_ring_writes(&ctx
, FALSE
);
2243 next_clip_base
= shader
->vs_out_misc_write
? 62 : 61;
2245 for (i
= 0, j
= 0; i
< noutput
; i
++, j
++) {
2246 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
2247 output
[j
].gpr
= shader
->output
[i
].gpr
;
2248 output
[j
].elem_size
= 3;
2249 output
[j
].swizzle_x
= 0;
2250 output
[j
].swizzle_y
= 1;
2251 output
[j
].swizzle_z
= 2;
2252 output
[j
].swizzle_w
= 3;
2253 output
[j
].burst_count
= 1;
2254 output
[j
].type
= -1;
2255 output
[j
].op
= CF_OP_EXPORT
;
2257 case TGSI_PROCESSOR_VERTEX
:
2258 switch (shader
->output
[i
].name
) {
2259 case TGSI_SEMANTIC_POSITION
:
2260 output
[j
].array_base
= 60;
2261 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2265 case TGSI_SEMANTIC_PSIZE
:
2266 output
[j
].array_base
= 61;
2267 output
[j
].swizzle_y
= 7;
2268 output
[j
].swizzle_z
= 7;
2269 output
[j
].swizzle_w
= 7;
2270 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2273 case TGSI_SEMANTIC_EDGEFLAG
:
2274 output
[j
].array_base
= 61;
2275 output
[j
].swizzle_x
= 7;
2276 output
[j
].swizzle_y
= 0;
2277 output
[j
].swizzle_z
= 7;
2278 output
[j
].swizzle_w
= 7;
2279 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2282 case TGSI_SEMANTIC_LAYER
:
2283 /* spi_sid is 0 for outputs that are
2284 * not consumed by PS */
2285 if (shader
->output
[i
].spi_sid
) {
2286 output
[j
].array_base
= next_param_base
++;
2287 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
2289 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
2291 output
[j
].array_base
= 61;
2292 output
[j
].swizzle_x
= 7;
2293 output
[j
].swizzle_y
= 7;
2294 output
[j
].swizzle_z
= 0;
2295 output
[j
].swizzle_w
= 7;
2296 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2299 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2300 /* spi_sid is 0 for outputs that are
2301 * not consumed by PS */
2302 if (shader
->output
[i
].spi_sid
) {
2303 output
[j
].array_base
= next_param_base
++;
2304 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
2306 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
2308 output
[j
].array_base
= 61;
2309 output
[j
].swizzle_x
= 7;
2310 output
[j
].swizzle_y
= 7;
2311 output
[j
].swizzle_z
= 7;
2312 output
[j
].swizzle_w
= 0;
2313 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2316 case TGSI_SEMANTIC_CLIPVERTEX
:
2319 case TGSI_SEMANTIC_CLIPDIST
:
2320 output
[j
].array_base
= next_clip_base
++;
2321 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2323 /* spi_sid is 0 for clipdistance outputs that were generated
2324 * for clipvertex - we don't need to pass them to PS */
2325 if (shader
->output
[i
].spi_sid
) {
2327 /* duplicate it as PARAM to pass to the pixel shader */
2328 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
2329 output
[j
].array_base
= next_param_base
++;
2330 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
2333 case TGSI_SEMANTIC_FOG
:
2334 output
[j
].swizzle_y
= 4; /* 0 */
2335 output
[j
].swizzle_z
= 4; /* 0 */
2336 output
[j
].swizzle_w
= 5; /* 1 */
2340 case TGSI_PROCESSOR_FRAGMENT
:
2341 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
2342 /* never export more colors than the number of CBs */
2343 if (shader
->output
[i
].sid
>= max_color_exports
) {
2348 output
[j
].swizzle_w
= key
.alpha_to_one
? 5 : 3;
2349 output
[j
].array_base
= shader
->output
[i
].sid
;
2350 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
2351 shader
->nr_ps_color_exports
++;
2352 if (shader
->fs_write_all
&& (rscreen
->b
.chip_class
>= EVERGREEN
)) {
2353 for (k
= 1; k
< max_color_exports
; k
++) {
2355 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
2356 output
[j
].gpr
= shader
->output
[i
].gpr
;
2357 output
[j
].elem_size
= 3;
2358 output
[j
].swizzle_x
= 0;
2359 output
[j
].swizzle_y
= 1;
2360 output
[j
].swizzle_z
= 2;
2361 output
[j
].swizzle_w
= key
.alpha_to_one
? 5 : 3;
2362 output
[j
].burst_count
= 1;
2363 output
[j
].array_base
= k
;
2364 output
[j
].op
= CF_OP_EXPORT
;
2365 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
2366 shader
->nr_ps_color_exports
++;
2369 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
2370 output
[j
].array_base
= 61;
2371 output
[j
].swizzle_x
= 2;
2372 output
[j
].swizzle_y
= 7;
2373 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
2374 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
2375 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
2376 output
[j
].array_base
= 61;
2377 output
[j
].swizzle_x
= 7;
2378 output
[j
].swizzle_y
= 1;
2379 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
2380 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
2381 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
) {
2382 output
[j
].array_base
= 61;
2383 output
[j
].swizzle_x
= 7;
2384 output
[j
].swizzle_y
= 7;
2385 output
[j
].swizzle_z
= 0;
2386 output
[j
].swizzle_w
= 7;
2387 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
2389 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
2395 R600_ERR("unsupported processor type %d\n", ctx
.type
);
2400 if (output
[j
].type
==-1) {
2401 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
2402 output
[j
].array_base
= next_param_base
++;
2406 /* add fake position export */
2407 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
&& pos_emitted
== false) {
2408 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
2410 output
[j
].elem_size
= 3;
2411 output
[j
].swizzle_x
= 7;
2412 output
[j
].swizzle_y
= 7;
2413 output
[j
].swizzle_z
= 7;
2414 output
[j
].swizzle_w
= 7;
2415 output
[j
].burst_count
= 1;
2416 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2417 output
[j
].array_base
= 60;
2418 output
[j
].op
= CF_OP_EXPORT
;
2422 /* add fake param output for vertex shader if no param is exported */
2423 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
&& next_param_base
== 0) {
2424 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
2426 output
[j
].elem_size
= 3;
2427 output
[j
].swizzle_x
= 7;
2428 output
[j
].swizzle_y
= 7;
2429 output
[j
].swizzle_z
= 7;
2430 output
[j
].swizzle_w
= 7;
2431 output
[j
].burst_count
= 1;
2432 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
2433 output
[j
].array_base
= 0;
2434 output
[j
].op
= CF_OP_EXPORT
;
2438 /* add fake pixel export */
2439 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& shader
->nr_ps_color_exports
== 0) {
2440 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
2442 output
[j
].elem_size
= 3;
2443 output
[j
].swizzle_x
= 7;
2444 output
[j
].swizzle_y
= 7;
2445 output
[j
].swizzle_z
= 7;
2446 output
[j
].swizzle_w
= 7;
2447 output
[j
].burst_count
= 1;
2448 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
2449 output
[j
].array_base
= 0;
2450 output
[j
].op
= CF_OP_EXPORT
;
2456 /* set export done on last export of each type */
2457 for (i
= noutput
- 1, output_done
= 0; i
>= 0; i
--) {
2458 if (!(output_done
& (1 << output
[i
].type
))) {
2459 output_done
|= (1 << output
[i
].type
);
2460 output
[i
].op
= CF_OP_EXPORT_DONE
;
2463 /* add output to bytecode */
2465 for (i
= 0; i
< noutput
; i
++) {
2466 r
= r600_bytecode_add_output(ctx
.bc
, &output
[i
]);
2473 /* add program end */
2475 if (ctx
.bc
->chip_class
== CAYMAN
)
2476 cm_bytecode_add_cf_end(ctx
.bc
);
2478 const struct cf_op_info
*last
= NULL
;
2480 if (ctx
.bc
->cf_last
)
2481 last
= r600_isa_cf(ctx
.bc
->cf_last
->op
);
2483 /* alu clause instructions don't have EOP bit, so add NOP */
2484 if (!last
|| last
->flags
& CF_ALU
|| ctx
.bc
->cf_last
->op
== CF_OP_LOOP_END
|| ctx
.bc
->cf_last
->op
== CF_OP_CALL_FS
)
2485 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
2487 ctx
.bc
->cf_last
->end_of_program
= 1;
2491 /* check GPR limit - we have 124 = 128 - 4
2492 * (4 are reserved as alu clause temporary registers) */
2493 if (ctx
.bc
->ngpr
> 124) {
2494 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx
.bc
->ngpr
);
2499 if (ctx
.type
== TGSI_PROCESSOR_GEOMETRY
) {
2500 if ((r
= generate_gs_copy_shader(rctx
, pipeshader
, &so
)))
2505 tgsi_parse_free(&ctx
.parse
);
2509 tgsi_parse_free(&ctx
.parse
);
2513 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
2515 R600_ERR("%s tgsi opcode unsupported\n",
2516 tgsi_get_opcode_name(ctx
->inst_info
->tgsi_opcode
));
2520 static int tgsi_end(struct r600_shader_ctx
*ctx
)
2525 static void r600_bytecode_src(struct r600_bytecode_alu_src
*bc_src
,
2526 const struct r600_shader_src
*shader_src
,
2529 bc_src
->sel
= shader_src
->sel
;
2530 bc_src
->chan
= shader_src
->swizzle
[chan
];
2531 bc_src
->neg
= shader_src
->neg
;
2532 bc_src
->abs
= shader_src
->abs
;
2533 bc_src
->rel
= shader_src
->rel
;
2534 bc_src
->value
= shader_src
->value
[bc_src
->chan
];
2535 bc_src
->kc_bank
= shader_src
->kc_bank
;
2536 bc_src
->kc_rel
= shader_src
->kc_rel
;
2539 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src
*bc_src
)
2545 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src
*bc_src
)
2547 bc_src
->neg
= !bc_src
->neg
;
2550 static void tgsi_dst(struct r600_shader_ctx
*ctx
,
2551 const struct tgsi_full_dst_register
*tgsi_dst
,
2553 struct r600_bytecode_alu_dst
*r600_dst
)
2555 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2557 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
2558 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
2559 r600_dst
->chan
= swizzle
;
2560 r600_dst
->write
= 1;
2561 if (tgsi_dst
->Register
.Indirect
)
2562 r600_dst
->rel
= V_SQ_REL_RELATIVE
;
2563 if (inst
->Instruction
.Saturate
) {
2564 r600_dst
->clamp
= 1;
2568 static int tgsi_last_instruction(unsigned writemask
)
2572 for (i
= 0; i
< 4; i
++) {
2573 if (writemask
& (1 << i
)) {
2580 static int tgsi_op2_s(struct r600_shader_ctx
*ctx
, int swap
, int trans_only
)
2582 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2583 struct r600_bytecode_alu alu
;
2584 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
2585 int i
, j
, r
, lasti
= tgsi_last_instruction(write_mask
);
2586 /* use temp register if trans_only and more than one dst component */
2587 int use_tmp
= trans_only
&& (write_mask
^ (1 << lasti
));
2589 for (i
= 0; i
<= lasti
; i
++) {
2590 if (!(write_mask
& (1 << i
)))
2593 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2595 alu
.dst
.sel
= ctx
->temp_reg
;
2599 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2601 alu
.op
= ctx
->inst_info
->op
;
2603 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
2604 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
2607 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
2608 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
2610 /* handle some special cases */
2611 switch (ctx
->inst_info
->tgsi_opcode
) {
2612 case TGSI_OPCODE_SUB
:
2613 r600_bytecode_src_toggle_neg(&alu
.src
[1]);
2615 case TGSI_OPCODE_ABS
:
2616 r600_bytecode_src_set_abs(&alu
.src
[0]);
2621 if (i
== lasti
|| trans_only
) {
2624 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2630 /* move result from temp to dst */
2631 for (i
= 0; i
<= lasti
; i
++) {
2632 if (!(write_mask
& (1 << i
)))
2635 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2636 alu
.op
= ALU_OP1_MOV
;
2637 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2638 alu
.src
[0].sel
= ctx
->temp_reg
;
2639 alu
.src
[0].chan
= i
;
2640 alu
.last
= (i
== lasti
);
2642 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2650 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
2652 return tgsi_op2_s(ctx
, 0, 0);
2655 static int tgsi_op2_swap(struct r600_shader_ctx
*ctx
)
2657 return tgsi_op2_s(ctx
, 1, 0);
2660 static int tgsi_op2_trans(struct r600_shader_ctx
*ctx
)
2662 return tgsi_op2_s(ctx
, 0, 1);
2665 static int tgsi_ineg(struct r600_shader_ctx
*ctx
)
2667 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2668 struct r600_bytecode_alu alu
;
2670 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
2672 for (i
= 0; i
< lasti
+ 1; i
++) {
2674 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
2676 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2677 alu
.op
= ctx
->inst_info
->op
;
2679 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2681 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
2683 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2688 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2696 static int cayman_emit_float_instr(struct r600_shader_ctx
*ctx
)
2698 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2700 struct r600_bytecode_alu alu
;
2701 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
2703 for (i
= 0 ; i
< last_slot
; i
++) {
2704 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2705 alu
.op
= ctx
->inst_info
->op
;
2706 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
2707 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], 0);
2709 /* RSQ should take the absolute value of src */
2710 if (ctx
->inst_info
->tgsi_opcode
== TGSI_OPCODE_RSQ
) {
2711 r600_bytecode_src_set_abs(&alu
.src
[j
]);
2714 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2715 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
2717 if (i
== last_slot
- 1)
2719 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2726 static int cayman_mul_int_instr(struct r600_shader_ctx
*ctx
)
2728 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2730 struct r600_bytecode_alu alu
;
2731 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
2732 int t1
= ctx
->temp_reg
;
2734 for (k
= 0; k
<= lasti
; k
++) {
2735 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << k
)))
2738 for (i
= 0 ; i
< 4; i
++) {
2739 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2740 alu
.op
= ctx
->inst_info
->op
;
2741 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
2742 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], k
);
2746 alu
.dst
.write
= (i
== k
);
2749 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2755 for (i
= 0 ; i
<= lasti
; i
++) {
2756 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
2758 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2759 alu
.op
= ALU_OP1_MOV
;
2760 alu
.src
[0].sel
= t1
;
2761 alu
.src
[0].chan
= i
;
2762 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2766 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2775 * r600 - trunc to -PI..PI range
2776 * r700 - normalize by dividing by 2PI
2779 static int tgsi_setup_trig(struct r600_shader_ctx
*ctx
)
2781 static float half_inv_pi
= 1.0 /(3.1415926535 * 2);
2782 static float double_pi
= 3.1415926535 * 2;
2783 static float neg_pi
= -3.1415926535;
2786 struct r600_bytecode_alu alu
;
2788 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2789 alu
.op
= ALU_OP3_MULADD
;
2793 alu
.dst
.sel
= ctx
->temp_reg
;
2796 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
2798 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2799 alu
.src
[1].chan
= 0;
2800 alu
.src
[1].value
= *(uint32_t *)&half_inv_pi
;
2801 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
2802 alu
.src
[2].chan
= 0;
2804 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2808 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2809 alu
.op
= ALU_OP1_FRACT
;
2812 alu
.dst
.sel
= ctx
->temp_reg
;
2815 alu
.src
[0].sel
= ctx
->temp_reg
;
2816 alu
.src
[0].chan
= 0;
2818 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2822 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2823 alu
.op
= ALU_OP3_MULADD
;
2827 alu
.dst
.sel
= ctx
->temp_reg
;
2830 alu
.src
[0].sel
= ctx
->temp_reg
;
2831 alu
.src
[0].chan
= 0;
2833 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2834 alu
.src
[1].chan
= 0;
2835 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
2836 alu
.src
[2].chan
= 0;
2838 if (ctx
->bc
->chip_class
== R600
) {
2839 alu
.src
[1].value
= *(uint32_t *)&double_pi
;
2840 alu
.src
[2].value
= *(uint32_t *)&neg_pi
;
2842 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
2843 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
2848 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2854 static int cayman_trig(struct r600_shader_ctx
*ctx
)
2856 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2857 struct r600_bytecode_alu alu
;
2858 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
2861 r
= tgsi_setup_trig(ctx
);
2866 for (i
= 0; i
< last_slot
; i
++) {
2867 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2868 alu
.op
= ctx
->inst_info
->op
;
2871 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2872 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
2874 alu
.src
[0].sel
= ctx
->temp_reg
;
2875 alu
.src
[0].chan
= 0;
2876 if (i
== last_slot
- 1)
2878 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2885 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
2887 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2888 struct r600_bytecode_alu alu
;
2890 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
2892 r
= tgsi_setup_trig(ctx
);
2896 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2897 alu
.op
= ctx
->inst_info
->op
;
2899 alu
.dst
.sel
= ctx
->temp_reg
;
2902 alu
.src
[0].sel
= ctx
->temp_reg
;
2903 alu
.src
[0].chan
= 0;
2905 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2909 /* replicate result */
2910 for (i
= 0; i
< lasti
+ 1; i
++) {
2911 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
2914 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2915 alu
.op
= ALU_OP1_MOV
;
2917 alu
.src
[0].sel
= ctx
->temp_reg
;
2918 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2921 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2928 static int tgsi_scs(struct r600_shader_ctx
*ctx
)
2930 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2931 struct r600_bytecode_alu alu
;
2934 /* We'll only need the trig stuff if we are going to write to the
2935 * X or Y components of the destination vector.
2937 if (likely(inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
)) {
2938 r
= tgsi_setup_trig(ctx
);
2944 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2945 if (ctx
->bc
->chip_class
== CAYMAN
) {
2946 for (i
= 0 ; i
< 3; i
++) {
2947 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2948 alu
.op
= ALU_OP1_COS
;
2949 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2955 alu
.src
[0].sel
= ctx
->temp_reg
;
2956 alu
.src
[0].chan
= 0;
2959 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2964 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2965 alu
.op
= ALU_OP1_COS
;
2966 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
2968 alu
.src
[0].sel
= ctx
->temp_reg
;
2969 alu
.src
[0].chan
= 0;
2971 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2978 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2979 if (ctx
->bc
->chip_class
== CAYMAN
) {
2980 for (i
= 0 ; i
< 3; i
++) {
2981 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2982 alu
.op
= ALU_OP1_SIN
;
2983 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2988 alu
.src
[0].sel
= ctx
->temp_reg
;
2989 alu
.src
[0].chan
= 0;
2992 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2997 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2998 alu
.op
= ALU_OP1_SIN
;
2999 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
3001 alu
.src
[0].sel
= ctx
->temp_reg
;
3002 alu
.src
[0].chan
= 0;
3004 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3011 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3012 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3014 alu
.op
= ALU_OP1_MOV
;
3016 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
3018 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
3019 alu
.src
[0].chan
= 0;
3023 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3029 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3030 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3032 alu
.op
= ALU_OP1_MOV
;
3034 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
3036 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
3037 alu
.src
[0].chan
= 0;
3041 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3049 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
3051 struct r600_bytecode_alu alu
;
3054 for (i
= 0; i
< 4; i
++) {
3055 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3056 alu
.op
= ctx
->inst_info
->op
;
3060 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
3062 if (ctx
->inst_info
->tgsi_opcode
== TGSI_OPCODE_KILL
) {
3063 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
3066 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3071 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3076 /* kill must be last in ALU */
3077 ctx
->bc
->force_add_cf
= 1;
3078 ctx
->shader
->uses_kill
= TRUE
;
3082 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
3084 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3085 struct r600_bytecode_alu alu
;
3088 /* tmp.x = max(src.y, 0.0) */
3089 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3090 alu
.op
= ALU_OP2_MAX
;
3091 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 1);
3092 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
3093 alu
.src
[1].chan
= 1;
3095 alu
.dst
.sel
= ctx
->temp_reg
;
3100 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3104 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
3110 if (ctx
->bc
->chip_class
== CAYMAN
) {
3111 for (i
= 0; i
< 3; i
++) {
3112 /* tmp.z = log(tmp.x) */
3113 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3114 alu
.op
= ALU_OP1_LOG_CLAMPED
;
3115 alu
.src
[0].sel
= ctx
->temp_reg
;
3116 alu
.src
[0].chan
= 0;
3117 alu
.dst
.sel
= ctx
->temp_reg
;
3125 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3130 /* tmp.z = log(tmp.x) */
3131 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3132 alu
.op
= ALU_OP1_LOG_CLAMPED
;
3133 alu
.src
[0].sel
= ctx
->temp_reg
;
3134 alu
.src
[0].chan
= 0;
3135 alu
.dst
.sel
= ctx
->temp_reg
;
3139 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3144 chan
= alu
.dst
.chan
;
3147 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
3148 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3149 alu
.op
= ALU_OP3_MUL_LIT
;
3150 alu
.src
[0].sel
= sel
;
3151 alu
.src
[0].chan
= chan
;
3152 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], 3);
3153 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], 0);
3154 alu
.dst
.sel
= ctx
->temp_reg
;
3159 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3163 if (ctx
->bc
->chip_class
== CAYMAN
) {
3164 for (i
= 0; i
< 3; i
++) {
3165 /* dst.z = exp(tmp.x) */
3166 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3167 alu
.op
= ALU_OP1_EXP_IEEE
;
3168 alu
.src
[0].sel
= ctx
->temp_reg
;
3169 alu
.src
[0].chan
= 0;
3170 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3176 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3181 /* dst.z = exp(tmp.x) */
3182 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3183 alu
.op
= ALU_OP1_EXP_IEEE
;
3184 alu
.src
[0].sel
= ctx
->temp_reg
;
3185 alu
.src
[0].chan
= 0;
3186 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
3188 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3195 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3196 alu
.op
= ALU_OP1_MOV
;
3197 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
; /*1.0*/
3198 alu
.src
[0].chan
= 0;
3199 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
3200 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
3201 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3205 /* dst.y = max(src.x, 0.0) */
3206 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3207 alu
.op
= ALU_OP2_MAX
;
3208 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
3209 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
3210 alu
.src
[1].chan
= 0;
3211 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
3212 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
3213 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3218 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3219 alu
.op
= ALU_OP1_MOV
;
3220 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
3221 alu
.src
[0].chan
= 0;
3222 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
3223 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
3225 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3232 static int tgsi_rsq(struct r600_shader_ctx
*ctx
)
3234 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3235 struct r600_bytecode_alu alu
;
3238 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3241 * For state trackers other than OpenGL, we'll want to use
3242 * _RECIPSQRT_IEEE instead.
3244 alu
.op
= ALU_OP1_RECIPSQRT_CLAMPED
;
3246 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
3247 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
3248 r600_bytecode_src_set_abs(&alu
.src
[i
]);
3250 alu
.dst
.sel
= ctx
->temp_reg
;
3253 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3256 /* replicate result */
3257 return tgsi_helper_tempx_replicate(ctx
);
3260 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
)
3262 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3263 struct r600_bytecode_alu alu
;
3266 for (i
= 0; i
< 4; i
++) {
3267 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3268 alu
.src
[0].sel
= ctx
->temp_reg
;
3269 alu
.op
= ALU_OP1_MOV
;
3271 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3272 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
3275 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3282 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
3284 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3285 struct r600_bytecode_alu alu
;
3288 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3289 alu
.op
= ctx
->inst_info
->op
;
3290 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
3291 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
3293 alu
.dst
.sel
= ctx
->temp_reg
;
3296 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3299 /* replicate result */
3300 return tgsi_helper_tempx_replicate(ctx
);
3303 static int cayman_pow(struct r600_shader_ctx
*ctx
)
3305 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3307 struct r600_bytecode_alu alu
;
3308 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
3310 for (i
= 0; i
< 3; i
++) {
3311 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3312 alu
.op
= ALU_OP1_LOG_IEEE
;
3313 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
3314 alu
.dst
.sel
= ctx
->temp_reg
;
3319 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3325 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3326 alu
.op
= ALU_OP2_MUL
;
3327 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
3328 alu
.src
[1].sel
= ctx
->temp_reg
;
3329 alu
.dst
.sel
= ctx
->temp_reg
;
3332 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3336 for (i
= 0; i
< last_slot
; i
++) {
3337 /* POW(a,b) = EXP2(b * LOG2(a))*/
3338 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3339 alu
.op
= ALU_OP1_EXP_IEEE
;
3340 alu
.src
[0].sel
= ctx
->temp_reg
;
3342 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3343 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
3344 if (i
== last_slot
- 1)
3346 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3353 static int tgsi_pow(struct r600_shader_ctx
*ctx
)
3355 struct r600_bytecode_alu alu
;
3359 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3360 alu
.op
= ALU_OP1_LOG_IEEE
;
3361 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
3362 alu
.dst
.sel
= ctx
->temp_reg
;
3365 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3369 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3370 alu
.op
= ALU_OP2_MUL
;
3371 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
3372 alu
.src
[1].sel
= ctx
->temp_reg
;
3373 alu
.dst
.sel
= ctx
->temp_reg
;
3376 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3379 /* POW(a,b) = EXP2(b * LOG2(a))*/
3380 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3381 alu
.op
= ALU_OP1_EXP_IEEE
;
3382 alu
.src
[0].sel
= ctx
->temp_reg
;
3383 alu
.dst
.sel
= ctx
->temp_reg
;
3386 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3389 return tgsi_helper_tempx_replicate(ctx
);
3392 static int tgsi_divmod(struct r600_shader_ctx
*ctx
, int mod
, int signed_op
)
3394 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3395 struct r600_bytecode_alu alu
;
3397 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3398 int tmp0
= ctx
->temp_reg
;
3399 int tmp1
= r600_get_temp(ctx
);
3400 int tmp2
= r600_get_temp(ctx
);
3401 int tmp3
= r600_get_temp(ctx
);
3404 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
3406 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
3407 * 2. tmp0.z = lo (tmp0.x * src2)
3408 * 3. tmp0.w = -tmp0.z
3409 * 4. tmp0.y = hi (tmp0.x * src2)
3410 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
3411 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
3412 * 7. tmp1.x = tmp0.x - tmp0.w
3413 * 8. tmp1.y = tmp0.x + tmp0.w
3414 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
3415 * 10. tmp0.z = hi(tmp0.x * src1) = q
3416 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
3418 * 12. tmp0.w = src1 - tmp0.y = r
3419 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
3420 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
3424 * 15. tmp1.z = tmp0.z + 1 = q + 1
3425 * 16. tmp1.w = tmp0.z - 1 = q - 1
3429 * 15. tmp1.z = tmp0.w - src2 = r - src2
3430 * 16. tmp1.w = tmp0.w + src2 = r + src2
3434 * 17. tmp1.x = tmp1.x & tmp1.y
3436 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
3437 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
3439 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
3440 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
3444 * Same as unsigned, using abs values of the operands,
3445 * and fixing the sign of the result in the end.
3448 for (i
= 0; i
< 4; i
++) {
3449 if (!(write_mask
& (1<<i
)))
3454 /* tmp2.x = -src0 */
3455 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3456 alu
.op
= ALU_OP2_SUB_INT
;
3462 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
3464 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3467 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3470 /* tmp2.y = -src1 */
3471 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3472 alu
.op
= ALU_OP2_SUB_INT
;
3478 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
3480 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
3483 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3486 /* tmp2.z sign bit is set if src0 and src2 signs are different */
3487 /* it will be a sign of the quotient */
3490 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3491 alu
.op
= ALU_OP2_XOR_INT
;
3497 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3498 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
3501 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3505 /* tmp2.x = |src0| */
3506 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3507 alu
.op
= ALU_OP3_CNDGE_INT
;
3514 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3515 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3516 alu
.src
[2].sel
= tmp2
;
3517 alu
.src
[2].chan
= 0;
3520 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3523 /* tmp2.y = |src1| */
3524 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3525 alu
.op
= ALU_OP3_CNDGE_INT
;
3532 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
3533 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
3534 alu
.src
[2].sel
= tmp2
;
3535 alu
.src
[2].chan
= 1;
3538 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3543 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
3544 if (ctx
->bc
->chip_class
== CAYMAN
) {
3545 /* tmp3.x = u2f(src2) */
3546 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3547 alu
.op
= ALU_OP1_UINT_TO_FLT
;
3554 alu
.src
[0].sel
= tmp2
;
3555 alu
.src
[0].chan
= 1;
3557 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
3561 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3564 /* tmp0.x = recip(tmp3.x) */
3565 for (j
= 0 ; j
< 3; j
++) {
3566 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3567 alu
.op
= ALU_OP1_RECIP_IEEE
;
3571 alu
.dst
.write
= (j
== 0);
3573 alu
.src
[0].sel
= tmp3
;
3574 alu
.src
[0].chan
= 0;
3578 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3582 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3583 alu
.op
= ALU_OP2_MUL
;
3585 alu
.src
[0].sel
= tmp0
;
3586 alu
.src
[0].chan
= 0;
3588 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
3589 alu
.src
[1].value
= 0x4f800000;
3594 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3598 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3599 alu
.op
= ALU_OP1_FLT_TO_UINT
;
3605 alu
.src
[0].sel
= tmp3
;
3606 alu
.src
[0].chan
= 0;
3609 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3613 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3614 alu
.op
= ALU_OP1_RECIP_UINT
;
3621 alu
.src
[0].sel
= tmp2
;
3622 alu
.src
[0].chan
= 1;
3624 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
3628 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3632 /* 2. tmp0.z = lo (tmp0.x * src2) */
3633 if (ctx
->bc
->chip_class
== CAYMAN
) {
3634 for (j
= 0 ; j
< 4; j
++) {
3635 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3636 alu
.op
= ALU_OP2_MULLO_UINT
;
3640 alu
.dst
.write
= (j
== 2);
3642 alu
.src
[0].sel
= tmp0
;
3643 alu
.src
[0].chan
= 0;
3645 alu
.src
[1].sel
= tmp2
;
3646 alu
.src
[1].chan
= 1;
3648 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
3651 alu
.last
= (j
== 3);
3652 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3656 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3657 alu
.op
= ALU_OP2_MULLO_UINT
;
3663 alu
.src
[0].sel
= tmp0
;
3664 alu
.src
[0].chan
= 0;
3666 alu
.src
[1].sel
= tmp2
;
3667 alu
.src
[1].chan
= 1;
3669 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
3673 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3677 /* 3. tmp0.w = -tmp0.z */
3678 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3679 alu
.op
= ALU_OP2_SUB_INT
;
3685 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
3686 alu
.src
[1].sel
= tmp0
;
3687 alu
.src
[1].chan
= 2;
3690 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3693 /* 4. tmp0.y = hi (tmp0.x * src2) */
3694 if (ctx
->bc
->chip_class
== CAYMAN
) {
3695 for (j
= 0 ; j
< 4; j
++) {
3696 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3697 alu
.op
= ALU_OP2_MULHI_UINT
;
3701 alu
.dst
.write
= (j
== 1);
3703 alu
.src
[0].sel
= tmp0
;
3704 alu
.src
[0].chan
= 0;
3707 alu
.src
[1].sel
= tmp2
;
3708 alu
.src
[1].chan
= 1;
3710 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
3712 alu
.last
= (j
== 3);
3713 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3717 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3718 alu
.op
= ALU_OP2_MULHI_UINT
;
3724 alu
.src
[0].sel
= tmp0
;
3725 alu
.src
[0].chan
= 0;
3728 alu
.src
[1].sel
= tmp2
;
3729 alu
.src
[1].chan
= 1;
3731 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
3735 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3739 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
3740 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3741 alu
.op
= ALU_OP3_CNDE_INT
;
3748 alu
.src
[0].sel
= tmp0
;
3749 alu
.src
[0].chan
= 1;
3750 alu
.src
[1].sel
= tmp0
;
3751 alu
.src
[1].chan
= 3;
3752 alu
.src
[2].sel
= tmp0
;
3753 alu
.src
[2].chan
= 2;
3756 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3759 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
3760 if (ctx
->bc
->chip_class
== CAYMAN
) {
3761 for (j
= 0 ; j
< 4; j
++) {
3762 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3763 alu
.op
= ALU_OP2_MULHI_UINT
;
3767 alu
.dst
.write
= (j
== 3);
3769 alu
.src
[0].sel
= tmp0
;
3770 alu
.src
[0].chan
= 2;
3772 alu
.src
[1].sel
= tmp0
;
3773 alu
.src
[1].chan
= 0;
3775 alu
.last
= (j
== 3);
3776 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3780 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3781 alu
.op
= ALU_OP2_MULHI_UINT
;
3787 alu
.src
[0].sel
= tmp0
;
3788 alu
.src
[0].chan
= 2;
3790 alu
.src
[1].sel
= tmp0
;
3791 alu
.src
[1].chan
= 0;
3794 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3798 /* 7. tmp1.x = tmp0.x - tmp0.w */
3799 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3800 alu
.op
= ALU_OP2_SUB_INT
;
3806 alu
.src
[0].sel
= tmp0
;
3807 alu
.src
[0].chan
= 0;
3808 alu
.src
[1].sel
= tmp0
;
3809 alu
.src
[1].chan
= 3;
3812 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3815 /* 8. tmp1.y = tmp0.x + tmp0.w */
3816 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3817 alu
.op
= ALU_OP2_ADD_INT
;
3823 alu
.src
[0].sel
= tmp0
;
3824 alu
.src
[0].chan
= 0;
3825 alu
.src
[1].sel
= tmp0
;
3826 alu
.src
[1].chan
= 3;
3829 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3832 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
3833 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3834 alu
.op
= ALU_OP3_CNDE_INT
;
3841 alu
.src
[0].sel
= tmp0
;
3842 alu
.src
[0].chan
= 1;
3843 alu
.src
[1].sel
= tmp1
;
3844 alu
.src
[1].chan
= 1;
3845 alu
.src
[2].sel
= tmp1
;
3846 alu
.src
[2].chan
= 0;
3849 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3852 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
3853 if (ctx
->bc
->chip_class
== CAYMAN
) {
3854 for (j
= 0 ; j
< 4; j
++) {
3855 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3856 alu
.op
= ALU_OP2_MULHI_UINT
;
3860 alu
.dst
.write
= (j
== 2);
3862 alu
.src
[0].sel
= tmp0
;
3863 alu
.src
[0].chan
= 0;
3866 alu
.src
[1].sel
= tmp2
;
3867 alu
.src
[1].chan
= 0;
3869 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3872 alu
.last
= (j
== 3);
3873 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3877 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3878 alu
.op
= ALU_OP2_MULHI_UINT
;
3884 alu
.src
[0].sel
= tmp0
;
3885 alu
.src
[0].chan
= 0;
3888 alu
.src
[1].sel
= tmp2
;
3889 alu
.src
[1].chan
= 0;
3891 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3895 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3899 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
3900 if (ctx
->bc
->chip_class
== CAYMAN
) {
3901 for (j
= 0 ; j
< 4; j
++) {
3902 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3903 alu
.op
= ALU_OP2_MULLO_UINT
;
3907 alu
.dst
.write
= (j
== 1);
3910 alu
.src
[0].sel
= tmp2
;
3911 alu
.src
[0].chan
= 1;
3913 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
3916 alu
.src
[1].sel
= tmp0
;
3917 alu
.src
[1].chan
= 2;
3919 alu
.last
= (j
== 3);
3920 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3924 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3925 alu
.op
= ALU_OP2_MULLO_UINT
;
3932 alu
.src
[0].sel
= tmp2
;
3933 alu
.src
[0].chan
= 1;
3935 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
3938 alu
.src
[1].sel
= tmp0
;
3939 alu
.src
[1].chan
= 2;
3942 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3946 /* 12. tmp0.w = src1 - tmp0.y = r */
3947 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3948 alu
.op
= ALU_OP2_SUB_INT
;
3955 alu
.src
[0].sel
= tmp2
;
3956 alu
.src
[0].chan
= 0;
3958 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3961 alu
.src
[1].sel
= tmp0
;
3962 alu
.src
[1].chan
= 1;
3965 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3968 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
3969 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3970 alu
.op
= ALU_OP2_SETGE_UINT
;
3976 alu
.src
[0].sel
= tmp0
;
3977 alu
.src
[0].chan
= 3;
3979 alu
.src
[1].sel
= tmp2
;
3980 alu
.src
[1].chan
= 1;
3982 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
3986 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3989 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
3990 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3991 alu
.op
= ALU_OP2_SETGE_UINT
;
3998 alu
.src
[0].sel
= tmp2
;
3999 alu
.src
[0].chan
= 0;
4001 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4004 alu
.src
[1].sel
= tmp0
;
4005 alu
.src
[1].chan
= 1;
4008 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4011 if (mod
) { /* UMOD */
4013 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
4014 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4015 alu
.op
= ALU_OP2_SUB_INT
;
4021 alu
.src
[0].sel
= tmp0
;
4022 alu
.src
[0].chan
= 3;
4025 alu
.src
[1].sel
= tmp2
;
4026 alu
.src
[1].chan
= 1;
4028 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
4032 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4035 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
4036 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4037 alu
.op
= ALU_OP2_ADD_INT
;
4043 alu
.src
[0].sel
= tmp0
;
4044 alu
.src
[0].chan
= 3;
4046 alu
.src
[1].sel
= tmp2
;
4047 alu
.src
[1].chan
= 1;
4049 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
4053 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4058 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
4059 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4060 alu
.op
= ALU_OP2_ADD_INT
;
4066 alu
.src
[0].sel
= tmp0
;
4067 alu
.src
[0].chan
= 2;
4068 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
4071 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4074 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
4075 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4076 alu
.op
= ALU_OP2_ADD_INT
;
4082 alu
.src
[0].sel
= tmp0
;
4083 alu
.src
[0].chan
= 2;
4084 alu
.src
[1].sel
= V_SQ_ALU_SRC_M_1_INT
;
4087 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4092 /* 17. tmp1.x = tmp1.x & tmp1.y */
4093 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4094 alu
.op
= ALU_OP2_AND_INT
;
4100 alu
.src
[0].sel
= tmp1
;
4101 alu
.src
[0].chan
= 0;
4102 alu
.src
[1].sel
= tmp1
;
4103 alu
.src
[1].chan
= 1;
4106 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4109 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
4110 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
4111 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4112 alu
.op
= ALU_OP3_CNDE_INT
;
4119 alu
.src
[0].sel
= tmp1
;
4120 alu
.src
[0].chan
= 0;
4121 alu
.src
[1].sel
= tmp0
;
4122 alu
.src
[1].chan
= mod
? 3 : 2;
4123 alu
.src
[2].sel
= tmp1
;
4124 alu
.src
[2].chan
= 2;
4127 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4130 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
4131 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4132 alu
.op
= ALU_OP3_CNDE_INT
;
4140 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4143 alu
.src
[0].sel
= tmp1
;
4144 alu
.src
[0].chan
= 1;
4145 alu
.src
[1].sel
= tmp1
;
4146 alu
.src
[1].chan
= 3;
4147 alu
.src
[2].sel
= tmp0
;
4148 alu
.src
[2].chan
= 2;
4151 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4156 /* fix the sign of the result */
4160 /* tmp0.x = -tmp0.z */
4161 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4162 alu
.op
= ALU_OP2_SUB_INT
;
4168 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4169 alu
.src
[1].sel
= tmp0
;
4170 alu
.src
[1].chan
= 2;
4173 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4176 /* sign of the remainder is the same as the sign of src0 */
4177 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
4178 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4179 alu
.op
= ALU_OP3_CNDGE_INT
;
4182 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4184 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4185 alu
.src
[1].sel
= tmp0
;
4186 alu
.src
[1].chan
= 2;
4187 alu
.src
[2].sel
= tmp0
;
4188 alu
.src
[2].chan
= 0;
4191 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4196 /* tmp0.x = -tmp0.z */
4197 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4198 alu
.op
= ALU_OP2_SUB_INT
;
4204 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4205 alu
.src
[1].sel
= tmp0
;
4206 alu
.src
[1].chan
= 2;
4209 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4212 /* fix the quotient sign (same as the sign of src0*src1) */
4213 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
4214 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4215 alu
.op
= ALU_OP3_CNDGE_INT
;
4218 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4220 alu
.src
[0].sel
= tmp2
;
4221 alu
.src
[0].chan
= 2;
4222 alu
.src
[1].sel
= tmp0
;
4223 alu
.src
[1].chan
= 2;
4224 alu
.src
[2].sel
= tmp0
;
4225 alu
.src
[2].chan
= 0;
4228 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4236 static int tgsi_udiv(struct r600_shader_ctx
*ctx
)
4238 return tgsi_divmod(ctx
, 0, 0);
4241 static int tgsi_umod(struct r600_shader_ctx
*ctx
)
4243 return tgsi_divmod(ctx
, 1, 0);
4246 static int tgsi_idiv(struct r600_shader_ctx
*ctx
)
4248 return tgsi_divmod(ctx
, 0, 1);
4251 static int tgsi_imod(struct r600_shader_ctx
*ctx
)
4253 return tgsi_divmod(ctx
, 1, 1);
4257 static int tgsi_f2i(struct r600_shader_ctx
*ctx
)
4259 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4260 struct r600_bytecode_alu alu
;
4262 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4263 int last_inst
= tgsi_last_instruction(write_mask
);
4265 for (i
= 0; i
< 4; i
++) {
4266 if (!(write_mask
& (1<<i
)))
4269 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4270 alu
.op
= ALU_OP1_TRUNC
;
4272 alu
.dst
.sel
= ctx
->temp_reg
;
4276 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4279 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4284 for (i
= 0; i
< 4; i
++) {
4285 if (!(write_mask
& (1<<i
)))
4288 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4289 alu
.op
= ctx
->inst_info
->op
;
4291 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4293 alu
.src
[0].sel
= ctx
->temp_reg
;
4294 alu
.src
[0].chan
= i
;
4296 if (i
== last_inst
|| alu
.op
== ALU_OP1_FLT_TO_UINT
)
4298 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4306 static int tgsi_iabs(struct r600_shader_ctx
*ctx
)
4308 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4309 struct r600_bytecode_alu alu
;
4311 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4312 int last_inst
= tgsi_last_instruction(write_mask
);
4315 for (i
= 0; i
< 4; i
++) {
4316 if (!(write_mask
& (1<<i
)))
4319 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4320 alu
.op
= ALU_OP2_SUB_INT
;
4322 alu
.dst
.sel
= ctx
->temp_reg
;
4326 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4327 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4331 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4336 /* dst = (src >= 0 ? src : tmp) */
4337 for (i
= 0; i
< 4; i
++) {
4338 if (!(write_mask
& (1<<i
)))
4341 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4342 alu
.op
= ALU_OP3_CNDGE_INT
;
4346 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4348 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4349 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4350 alu
.src
[2].sel
= ctx
->temp_reg
;
4351 alu
.src
[2].chan
= i
;
4355 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4362 static int tgsi_issg(struct r600_shader_ctx
*ctx
)
4364 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4365 struct r600_bytecode_alu alu
;
4367 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4368 int last_inst
= tgsi_last_instruction(write_mask
);
4370 /* tmp = (src >= 0 ? src : -1) */
4371 for (i
= 0; i
< 4; i
++) {
4372 if (!(write_mask
& (1<<i
)))
4375 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4376 alu
.op
= ALU_OP3_CNDGE_INT
;
4379 alu
.dst
.sel
= ctx
->temp_reg
;
4383 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4384 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4385 alu
.src
[2].sel
= V_SQ_ALU_SRC_M_1_INT
;
4389 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4394 /* dst = (tmp > 0 ? 1 : tmp) */
4395 for (i
= 0; i
< 4; i
++) {
4396 if (!(write_mask
& (1<<i
)))
4399 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4400 alu
.op
= ALU_OP3_CNDGT_INT
;
4404 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4406 alu
.src
[0].sel
= ctx
->temp_reg
;
4407 alu
.src
[0].chan
= i
;
4409 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
4411 alu
.src
[2].sel
= ctx
->temp_reg
;
4412 alu
.src
[2].chan
= i
;
4416 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4425 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
4427 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4428 struct r600_bytecode_alu alu
;
4431 /* tmp = (src > 0 ? 1 : src) */
4432 for (i
= 0; i
< 4; i
++) {
4433 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4434 alu
.op
= ALU_OP3_CNDGT
;
4437 alu
.dst
.sel
= ctx
->temp_reg
;
4440 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4441 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
4442 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
4446 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4451 /* dst = (-tmp > 0 ? -1 : tmp) */
4452 for (i
= 0; i
< 4; i
++) {
4453 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4454 alu
.op
= ALU_OP3_CNDGT
;
4456 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4458 alu
.src
[0].sel
= ctx
->temp_reg
;
4459 alu
.src
[0].chan
= i
;
4462 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
4465 alu
.src
[2].sel
= ctx
->temp_reg
;
4466 alu
.src
[2].chan
= i
;
4470 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4477 static int tgsi_bfi(struct r600_shader_ctx
*ctx
)
4479 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4480 struct r600_bytecode_alu alu
;
4483 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4484 int last_inst
= tgsi_last_instruction(write_mask
);
4488 for (i
= 0; i
< 4; i
++) {
4489 if (!(write_mask
& (1<<i
)))
4492 /* create mask tmp */
4493 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4494 alu
.op
= ALU_OP2_BFM_INT
;
4498 alu
.last
= i
== last_inst
;
4500 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[3], i
);
4501 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
4503 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4508 t2
= r600_get_temp(ctx
);
4510 for (i
= 0; i
< 4; i
++) {
4511 if (!(write_mask
& (1<<i
)))
4514 /* shift insert left */
4515 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4516 alu
.op
= ALU_OP2_LSHL_INT
;
4520 alu
.last
= i
== last_inst
;
4522 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
4523 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
4525 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4530 for (i
= 0; i
< 4; i
++) {
4531 if (!(write_mask
& (1<<i
)))
4534 /* actual bitfield insert */
4535 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4536 alu
.op
= ALU_OP3_BFI_INT
;
4538 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4541 alu
.last
= i
== last_inst
;
4543 alu
.src
[0].sel
= t1
;
4544 alu
.src
[0].chan
= i
;
4545 alu
.src
[1].sel
= t2
;
4546 alu
.src
[1].chan
= i
;
4547 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
4549 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4557 static int tgsi_msb(struct r600_shader_ctx
*ctx
)
4559 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4560 struct r600_bytecode_alu alu
;
4563 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4564 int last_inst
= tgsi_last_instruction(write_mask
);
4566 assert(ctx
->inst_info
->op
== ALU_OP1_FFBH_INT
||
4567 ctx
->inst_info
->op
== ALU_OP1_FFBH_UINT
);
4571 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
4572 for (i
= 0; i
< 4; i
++) {
4573 if (!(write_mask
& (1<<i
)))
4576 /* t1 = FFBH_INT / FFBH_UINT */
4577 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4578 alu
.op
= ctx
->inst_info
->op
;
4582 alu
.last
= i
== last_inst
;
4584 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4586 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4591 t2
= r600_get_temp(ctx
);
4593 for (i
= 0; i
< 4; i
++) {
4594 if (!(write_mask
& (1<<i
)))
4598 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4599 alu
.op
= ALU_OP2_SUB_INT
;
4603 alu
.last
= i
== last_inst
;
4605 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
4606 alu
.src
[0].value
= 31;
4607 alu
.src
[1].sel
= t1
;
4608 alu
.src
[1].chan
= i
;
4610 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4615 for (i
= 0; i
< 4; i
++) {
4616 if (!(write_mask
& (1<<i
)))
4619 /* result = t1 >= 0 ? t2 : t1 */
4620 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4621 alu
.op
= ALU_OP3_CNDGE_INT
;
4623 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4626 alu
.last
= i
== last_inst
;
4628 alu
.src
[0].sel
= t1
;
4629 alu
.src
[0].chan
= i
;
4630 alu
.src
[1].sel
= t2
;
4631 alu
.src
[1].chan
= i
;
4632 alu
.src
[2].sel
= t1
;
4633 alu
.src
[2].chan
= i
;
4635 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4643 static int tgsi_interp_egcm(struct r600_shader_ctx
*ctx
)
4645 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4646 struct r600_bytecode_alu alu
;
4647 int r
, i
= 0, k
, interp_gpr
, interp_base_chan
, tmp
, lasti
;
4651 assert(inst
->Src
[0].Register
.File
== TGSI_FILE_INPUT
);
4653 input
= inst
->Src
[0].Register
.Index
;
4655 /* Interpolators have been marked for use already by allocate_system_value_inputs */
4656 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
4657 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
4658 location
= TGSI_INTERPOLATE_LOC_CENTER
; /* sample offset will be added explicitly */
4661 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
4664 k
= eg_get_interpolator_index(ctx
->shader
->input
[input
].interpolate
, location
);
4667 interp_gpr
= ctx
->eg_interpolators
[k
].ij_index
/ 2;
4668 interp_base_chan
= 2 * (ctx
->eg_interpolators
[k
].ij_index
% 2);
4670 /* NOTE: currently offset is not perspective correct */
4671 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
4672 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
4673 int sample_gpr
= -1;
4674 int gradientsH
, gradientsV
;
4675 struct r600_bytecode_tex tex
;
4677 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
4678 sample_gpr
= load_sample_position(ctx
, &ctx
->src
[1], ctx
->src
[1].swizzle
[0]);
4681 gradientsH
= r600_get_temp(ctx
);
4682 gradientsV
= r600_get_temp(ctx
);
4683 for (i
= 0; i
< 2; i
++) {
4684 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
4685 tex
.op
= i
== 0 ? FETCH_OP_GET_GRADIENTS_H
: FETCH_OP_GET_GRADIENTS_V
;
4686 tex
.src_gpr
= interp_gpr
;
4687 tex
.src_sel_x
= interp_base_chan
+ 0;
4688 tex
.src_sel_y
= interp_base_chan
+ 1;
4691 tex
.dst_gpr
= i
== 0 ? gradientsH
: gradientsV
;
4696 tex
.inst_mod
= 1; // Use per pixel gradient calculation
4698 tex
.resource_id
= tex
.sampler_id
;
4699 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
4704 for (i
= 0; i
< 2; i
++) {
4705 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4706 alu
.op
= ALU_OP3_MULADD
;
4708 alu
.src
[0].sel
= gradientsH
;
4709 alu
.src
[0].chan
= i
;
4710 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
4711 alu
.src
[1].sel
= sample_gpr
;
4712 alu
.src
[1].chan
= 2;
4715 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], 0);
4717 alu
.src
[2].sel
= interp_gpr
;
4718 alu
.src
[2].chan
= interp_base_chan
+ i
;
4719 alu
.dst
.sel
= ctx
->temp_reg
;
4723 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4728 for (i
= 0; i
< 2; i
++) {
4729 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4730 alu
.op
= ALU_OP3_MULADD
;
4732 alu
.src
[0].sel
= gradientsV
;
4733 alu
.src
[0].chan
= i
;
4734 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
4735 alu
.src
[1].sel
= sample_gpr
;
4736 alu
.src
[1].chan
= 3;
4739 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], 1);
4741 alu
.src
[2].sel
= ctx
->temp_reg
;
4742 alu
.src
[2].chan
= i
;
4743 alu
.dst
.sel
= ctx
->temp_reg
;
4747 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4753 tmp
= r600_get_temp(ctx
);
4754 for (i
= 0; i
< 8; i
++) {
4755 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4756 alu
.op
= i
< 4 ? ALU_OP2_INTERP_ZW
: ALU_OP2_INTERP_XY
;
4759 if ((i
> 1 && i
< 6)) {
4765 alu
.dst
.chan
= i
% 4;
4767 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
4768 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
4769 alu
.src
[0].sel
= ctx
->temp_reg
;
4770 alu
.src
[0].chan
= 1 - (i
% 2);
4772 alu
.src
[0].sel
= interp_gpr
;
4773 alu
.src
[0].chan
= interp_base_chan
+ 1 - (i
% 2);
4775 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
4776 alu
.src
[1].chan
= 0;
4778 alu
.last
= i
% 4 == 3;
4779 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
4781 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4786 // INTERP can't swizzle dst
4787 lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4788 for (i
= 0; i
<= lasti
; i
++) {
4789 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4792 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4793 alu
.op
= ALU_OP1_MOV
;
4794 alu
.src
[0].sel
= tmp
;
4795 alu
.src
[0].chan
= ctx
->src
[0].swizzle
[i
];
4796 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4798 alu
.last
= i
== lasti
;
4799 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4808 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
4810 struct r600_bytecode_alu alu
;
4813 for (i
= 0; i
< 4; i
++) {
4814 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4815 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
4816 alu
.op
= ALU_OP0_NOP
;
4819 alu
.op
= ALU_OP1_MOV
;
4820 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4821 alu
.src
[0].sel
= ctx
->temp_reg
;
4822 alu
.src
[0].chan
= i
;
4827 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4834 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
4836 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4837 struct r600_bytecode_alu alu
;
4839 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4841 for (i
= 0; i
< lasti
+ 1; i
++) {
4842 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4845 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4846 alu
.op
= ctx
->inst_info
->op
;
4847 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4848 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
4851 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4858 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4865 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
4867 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4868 struct r600_bytecode_alu alu
;
4871 for (i
= 0; i
< 4; i
++) {
4872 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4873 alu
.op
= ctx
->inst_info
->op
;
4874 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4875 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
4878 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4880 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
4881 /* handle some special cases */
4882 switch (ctx
->inst_info
->tgsi_opcode
) {
4883 case TGSI_OPCODE_DP2
:
4885 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
4886 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
4889 case TGSI_OPCODE_DP3
:
4891 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
4892 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
4895 case TGSI_OPCODE_DPH
:
4897 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
4898 alu
.src
[0].chan
= 0;
4908 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4915 static inline boolean
tgsi_tex_src_requires_loading(struct r600_shader_ctx
*ctx
,
4918 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4919 return (inst
->Src
[index
].Register
.File
!= TGSI_FILE_TEMPORARY
&&
4920 inst
->Src
[index
].Register
.File
!= TGSI_FILE_INPUT
&&
4921 inst
->Src
[index
].Register
.File
!= TGSI_FILE_OUTPUT
) ||
4922 ctx
->src
[index
].neg
|| ctx
->src
[index
].abs
||
4923 (inst
->Src
[index
].Register
.File
== TGSI_FILE_INPUT
&& ctx
->type
== TGSI_PROCESSOR_GEOMETRY
);
4926 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx
*ctx
,
4929 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4930 return ctx
->file_offset
[inst
->Src
[index
].Register
.File
] + inst
->Src
[index
].Register
.Index
;
4933 static int do_vtx_fetch_inst(struct r600_shader_ctx
*ctx
, boolean src_requires_loading
)
4935 struct r600_bytecode_vtx vtx
;
4936 struct r600_bytecode_alu alu
;
4937 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4939 int id
= tgsi_tex_get_src_gpr(ctx
, 1);
4941 src_gpr
= tgsi_tex_get_src_gpr(ctx
, 0);
4942 if (src_requires_loading
) {
4943 for (i
= 0; i
< 4; i
++) {
4944 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4945 alu
.op
= ALU_OP1_MOV
;
4946 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4947 alu
.dst
.sel
= ctx
->temp_reg
;
4952 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4956 src_gpr
= ctx
->temp_reg
;
4959 memset(&vtx
, 0, sizeof(vtx
));
4960 vtx
.op
= FETCH_OP_VFETCH
;
4961 vtx
.buffer_id
= id
+ R600_MAX_CONST_BUFFERS
;
4962 vtx
.fetch_type
= 2; /* VTX_FETCH_NO_INDEX_OFFSET */
4963 vtx
.src_gpr
= src_gpr
;
4964 vtx
.mega_fetch_count
= 16;
4965 vtx
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
4966 vtx
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7; /* SEL_X */
4967 vtx
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7; /* SEL_Y */
4968 vtx
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7; /* SEL_Z */
4969 vtx
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7; /* SEL_W */
4970 vtx
.use_const_fields
= 1;
4972 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
4975 if (ctx
->bc
->chip_class
>= EVERGREEN
)
4978 for (i
= 0; i
< 4; i
++) {
4979 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4980 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4983 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4984 alu
.op
= ALU_OP2_AND_INT
;
4987 alu
.dst
.sel
= vtx
.dst_gpr
;
4990 alu
.src
[0].sel
= vtx
.dst_gpr
;
4991 alu
.src
[0].chan
= i
;
4993 alu
.src
[1].sel
= 512 + (id
* 2);
4994 alu
.src
[1].chan
= i
% 4;
4995 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
4999 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5004 if (inst
->Dst
[0].Register
.WriteMask
& 3) {
5005 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5006 alu
.op
= ALU_OP2_OR_INT
;
5009 alu
.dst
.sel
= vtx
.dst_gpr
;
5012 alu
.src
[0].sel
= vtx
.dst_gpr
;
5013 alu
.src
[0].chan
= 3;
5015 alu
.src
[1].sel
= 512 + (id
* 2) + 1;
5016 alu
.src
[1].chan
= 0;
5017 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
5020 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5027 static int r600_do_buffer_txq(struct r600_shader_ctx
*ctx
)
5029 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5030 struct r600_bytecode_alu alu
;
5032 int id
= tgsi_tex_get_src_gpr(ctx
, 1);
5034 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5035 alu
.op
= ALU_OP1_MOV
;
5037 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
5038 alu
.src
[0].sel
= 512 + (id
/ 4);
5039 alu
.src
[0].chan
= id
% 4;
5041 /* r600 we have them at channel 2 of the second dword */
5042 alu
.src
[0].sel
= 512 + (id
* 2) + 1;
5043 alu
.src
[0].chan
= 1;
5045 alu
.src
[0].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
5046 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
5048 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5054 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
5056 static float one_point_five
= 1.5f
;
5057 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5058 struct r600_bytecode_tex tex
;
5059 struct r600_bytecode_alu alu
;
5063 bool read_compressed_msaa
= ctx
->bc
->has_compressed_msaa_texturing
&&
5064 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
&&
5065 (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_MSAA
||
5066 inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY_MSAA
);
5068 bool txf_add_offsets
= inst
->Texture
.NumOffsets
&&
5069 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
&&
5070 inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
;
5072 /* Texture fetch instructions can only use gprs as source.
5073 * Also they cannot negate the source or take the absolute value */
5074 const boolean src_requires_loading
= (inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ_LZ
&&
5075 tgsi_tex_src_requires_loading(ctx
, 0)) ||
5076 read_compressed_msaa
|| txf_add_offsets
;
5078 boolean src_loaded
= FALSE
;
5079 unsigned sampler_src_reg
= inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ_LZ
? 0 : 1;
5080 int8_t offset_x
= 0, offset_y
= 0, offset_z
= 0;
5081 boolean has_txq_cube_array_z
= false;
5082 unsigned sampler_index_mode
;
5084 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
&&
5085 ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
5086 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)))
5087 if (inst
->Dst
[0].Register
.WriteMask
& 4) {
5088 ctx
->shader
->has_txq_cube_array_z_comp
= true;
5089 has_txq_cube_array_z
= true;
5092 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TEX2
||
5093 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
5094 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
||
5095 inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
)
5096 sampler_src_reg
= 2;
5098 /* TGSI moves the sampler to src reg 3 for TXD */
5099 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
)
5100 sampler_src_reg
= 3;
5102 sampler_index_mode
= inst
->Src
[sampler_src_reg
].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
5103 if (sampler_index_mode
)
5104 ctx
->shader
->uses_index_registers
= true;
5106 src_gpr
= tgsi_tex_get_src_gpr(ctx
, 0);
5108 if (inst
->Texture
.Texture
== TGSI_TEXTURE_BUFFER
) {
5109 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
) {
5110 ctx
->shader
->uses_tex_buffers
= true;
5111 return r600_do_buffer_txq(ctx
);
5113 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
) {
5114 if (ctx
->bc
->chip_class
< EVERGREEN
)
5115 ctx
->shader
->uses_tex_buffers
= true;
5116 return do_vtx_fetch_inst(ctx
, src_requires_loading
);
5120 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
5122 /* Add perspective divide */
5123 if (ctx
->bc
->chip_class
== CAYMAN
) {
5125 for (i
= 0; i
< 3; i
++) {
5126 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5127 alu
.op
= ALU_OP1_RECIP_IEEE
;
5128 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
5130 alu
.dst
.sel
= ctx
->temp_reg
;
5136 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5143 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5144 alu
.op
= ALU_OP1_RECIP_IEEE
;
5145 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
5147 alu
.dst
.sel
= ctx
->temp_reg
;
5148 alu
.dst
.chan
= out_chan
;
5151 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5156 for (i
= 0; i
< 3; i
++) {
5157 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5158 alu
.op
= ALU_OP2_MUL
;
5159 alu
.src
[0].sel
= ctx
->temp_reg
;
5160 alu
.src
[0].chan
= out_chan
;
5161 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5162 alu
.dst
.sel
= ctx
->temp_reg
;
5165 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5169 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5170 alu
.op
= ALU_OP1_MOV
;
5171 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
5172 alu
.src
[0].chan
= 0;
5173 alu
.dst
.sel
= ctx
->temp_reg
;
5177 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5181 src_gpr
= ctx
->temp_reg
;
5185 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
5186 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
5187 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
5188 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
5189 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ
&&
5190 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ_LZ
) {
5192 static const unsigned src0_swizzle
[] = {2, 2, 0, 1};
5193 static const unsigned src1_swizzle
[] = {1, 0, 2, 2};
5195 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
5196 for (i
= 0; i
< 4; i
++) {
5197 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5198 alu
.op
= ALU_OP2_CUBE
;
5199 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src0_swizzle
[i
]);
5200 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], src1_swizzle
[i
]);
5201 alu
.dst
.sel
= ctx
->temp_reg
;
5206 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5211 /* tmp1.z = RCP_e(|tmp1.z|) */
5212 if (ctx
->bc
->chip_class
== CAYMAN
) {
5213 for (i
= 0; i
< 3; i
++) {
5214 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5215 alu
.op
= ALU_OP1_RECIP_IEEE
;
5216 alu
.src
[0].sel
= ctx
->temp_reg
;
5217 alu
.src
[0].chan
= 2;
5219 alu
.dst
.sel
= ctx
->temp_reg
;
5225 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5230 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5231 alu
.op
= ALU_OP1_RECIP_IEEE
;
5232 alu
.src
[0].sel
= ctx
->temp_reg
;
5233 alu
.src
[0].chan
= 2;
5235 alu
.dst
.sel
= ctx
->temp_reg
;
5239 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5244 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
5245 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
5246 * muladd has no writemask, have to use another temp
5248 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5249 alu
.op
= ALU_OP3_MULADD
;
5252 alu
.src
[0].sel
= ctx
->temp_reg
;
5253 alu
.src
[0].chan
= 0;
5254 alu
.src
[1].sel
= ctx
->temp_reg
;
5255 alu
.src
[1].chan
= 2;
5257 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
5258 alu
.src
[2].chan
= 0;
5259 alu
.src
[2].value
= *(uint32_t *)&one_point_five
;
5261 alu
.dst
.sel
= ctx
->temp_reg
;
5265 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5269 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5270 alu
.op
= ALU_OP3_MULADD
;
5273 alu
.src
[0].sel
= ctx
->temp_reg
;
5274 alu
.src
[0].chan
= 1;
5275 alu
.src
[1].sel
= ctx
->temp_reg
;
5276 alu
.src
[1].chan
= 2;
5278 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
5279 alu
.src
[2].chan
= 0;
5280 alu
.src
[2].value
= *(uint32_t *)&one_point_five
;
5282 alu
.dst
.sel
= ctx
->temp_reg
;
5287 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5290 /* write initial compare value into Z component
5291 - W src 0 for shadow cube
5292 - X src 1 for shadow cube array */
5293 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
5294 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
5295 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5296 alu
.op
= ALU_OP1_MOV
;
5297 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
5298 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
5300 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
5301 alu
.dst
.sel
= ctx
->temp_reg
;
5305 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5310 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
5311 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
5312 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
5313 int mytmp
= r600_get_temp(ctx
);
5314 static const float eight
= 8.0f
;
5315 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5316 alu
.op
= ALU_OP1_MOV
;
5317 alu
.src
[0].sel
= ctx
->temp_reg
;
5318 alu
.src
[0].chan
= 3;
5319 alu
.dst
.sel
= mytmp
;
5323 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5327 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
5328 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5329 alu
.op
= ALU_OP3_MULADD
;
5331 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
5332 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
5333 alu
.src
[1].chan
= 0;
5334 alu
.src
[1].value
= *(uint32_t *)&eight
;
5335 alu
.src
[2].sel
= mytmp
;
5336 alu
.src
[2].chan
= 0;
5337 alu
.dst
.sel
= ctx
->temp_reg
;
5341 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5344 } else if (ctx
->bc
->chip_class
< EVERGREEN
) {
5345 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
5346 tex
.op
= FETCH_OP_SET_CUBEMAP_INDEX
;
5347 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
5348 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
5349 tex
.src_gpr
= r600_get_temp(ctx
);
5354 tex
.dst_sel_x
= tex
.dst_sel_y
= tex
.dst_sel_z
= tex
.dst_sel_w
= 7;
5355 tex
.coord_type_x
= 1;
5356 tex
.coord_type_y
= 1;
5357 tex
.coord_type_z
= 1;
5358 tex
.coord_type_w
= 1;
5359 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5360 alu
.op
= ALU_OP1_MOV
;
5361 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
5362 alu
.dst
.sel
= tex
.src_gpr
;
5366 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5370 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
5377 /* for cube forms of lod and bias we need to route things */
5378 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB
||
5379 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL
||
5380 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
5381 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
) {
5382 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5383 alu
.op
= ALU_OP1_MOV
;
5384 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
5385 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
)
5386 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
5388 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
5389 alu
.dst
.sel
= ctx
->temp_reg
;
5393 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5399 src_gpr
= ctx
->temp_reg
;
5402 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
) {
5403 int temp_h
= 0, temp_v
= 0;
5406 /* if we've already loaded the src (i.e. CUBE don't reload it). */
5407 if (src_loaded
== TRUE
)
5411 for (i
= start_val
; i
< 3; i
++) {
5412 int treg
= r600_get_temp(ctx
);
5421 for (j
= 0; j
< 4; j
++) {
5422 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5423 alu
.op
= ALU_OP1_MOV
;
5424 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[i
], j
);
5430 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5435 for (i
= 1; i
< 3; i
++) {
5436 /* set gradients h/v */
5437 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
5438 tex
.op
= (i
== 1) ? FETCH_OP_SET_GRADIENTS_H
:
5439 FETCH_OP_SET_GRADIENTS_V
;
5440 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
5441 tex
.sampler_index_mode
= sampler_index_mode
;
5442 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
5443 tex
.resource_index_mode
= sampler_index_mode
;
5445 tex
.src_gpr
= (i
== 1) ? temp_h
: temp_v
;
5451 tex
.dst_gpr
= r600_get_temp(ctx
); /* just to avoid confusing the asm scheduler */
5452 tex
.dst_sel_x
= tex
.dst_sel_y
= tex
.dst_sel_z
= tex
.dst_sel_w
= 7;
5453 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
5454 tex
.coord_type_x
= 1;
5455 tex
.coord_type_y
= 1;
5456 tex
.coord_type_z
= 1;
5457 tex
.coord_type_w
= 1;
5459 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
5465 if (src_requires_loading
&& !src_loaded
) {
5466 for (i
= 0; i
< 4; i
++) {
5467 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5468 alu
.op
= ALU_OP1_MOV
;
5469 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5470 alu
.dst
.sel
= ctx
->temp_reg
;
5475 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5480 src_gpr
= ctx
->temp_reg
;
5483 /* get offset values */
5484 if (inst
->Texture
.NumOffsets
) {
5485 assert(inst
->Texture
.NumOffsets
== 1);
5487 /* The texture offset feature doesn't work with the TXF instruction
5488 * and must be emulated by adding the offset to the texture coordinates. */
5489 if (txf_add_offsets
) {
5490 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
5492 switch (inst
->Texture
.Texture
) {
5493 case TGSI_TEXTURE_3D
:
5494 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5495 alu
.op
= ALU_OP2_ADD_INT
;
5496 alu
.src
[0].sel
= src_gpr
;
5497 alu
.src
[0].chan
= 2;
5498 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
5499 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleZ
];
5500 alu
.dst
.sel
= src_gpr
;
5504 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5509 case TGSI_TEXTURE_2D
:
5510 case TGSI_TEXTURE_SHADOW2D
:
5511 case TGSI_TEXTURE_RECT
:
5512 case TGSI_TEXTURE_SHADOWRECT
:
5513 case TGSI_TEXTURE_2D_ARRAY
:
5514 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
5515 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5516 alu
.op
= ALU_OP2_ADD_INT
;
5517 alu
.src
[0].sel
= src_gpr
;
5518 alu
.src
[0].chan
= 1;
5519 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
5520 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleY
];
5521 alu
.dst
.sel
= src_gpr
;
5525 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5530 case TGSI_TEXTURE_1D
:
5531 case TGSI_TEXTURE_SHADOW1D
:
5532 case TGSI_TEXTURE_1D_ARRAY
:
5533 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
5534 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5535 alu
.op
= ALU_OP2_ADD_INT
;
5536 alu
.src
[0].sel
= src_gpr
;
5537 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
5538 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleX
];
5539 alu
.dst
.sel
= src_gpr
;
5542 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5546 /* texture offsets do not apply to other texture targets */
5549 switch (inst
->Texture
.Texture
) {
5550 case TGSI_TEXTURE_3D
:
5551 offset_z
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleZ
] << 1;
5553 case TGSI_TEXTURE_2D
:
5554 case TGSI_TEXTURE_SHADOW2D
:
5555 case TGSI_TEXTURE_RECT
:
5556 case TGSI_TEXTURE_SHADOWRECT
:
5557 case TGSI_TEXTURE_2D_ARRAY
:
5558 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
5559 offset_y
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleY
] << 1;
5561 case TGSI_TEXTURE_1D
:
5562 case TGSI_TEXTURE_SHADOW1D
:
5563 case TGSI_TEXTURE_1D_ARRAY
:
5564 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
5565 offset_x
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleX
] << 1;
5570 /* Obtain the sample index for reading a compressed MSAA color texture.
5571 * To read the FMASK, we use the ldfptr instruction, which tells us
5572 * where the samples are stored.
5573 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
5574 * which is the identity mapping. Each nibble says which physical sample
5575 * should be fetched to get that sample.
5577 * Assume src.z contains the sample index. It should be modified like this:
5578 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
5579 * Then fetch the texel with src.
5581 if (read_compressed_msaa
) {
5582 unsigned sample_chan
= 3;
5583 unsigned temp
= r600_get_temp(ctx
);
5586 /* temp.w = ldfptr() */
5587 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
5588 tex
.op
= FETCH_OP_LD
;
5589 tex
.inst_mod
= 1; /* to indicate this is ldfptr */
5590 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
5591 tex
.sampler_index_mode
= sampler_index_mode
;
5592 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
5593 tex
.resource_index_mode
= sampler_index_mode
;
5594 tex
.src_gpr
= src_gpr
;
5596 tex
.dst_sel_x
= 7; /* mask out these components */
5599 tex
.dst_sel_w
= 0; /* store X */
5604 tex
.offset_x
= offset_x
;
5605 tex
.offset_y
= offset_y
;
5606 tex
.offset_z
= offset_z
;
5607 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
5611 /* temp.x = sample_index*4 */
5612 if (ctx
->bc
->chip_class
== CAYMAN
) {
5613 for (i
= 0 ; i
< 4; i
++) {
5614 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5615 alu
.op
= ALU_OP2_MULLO_INT
;
5616 alu
.src
[0].sel
= src_gpr
;
5617 alu
.src
[0].chan
= sample_chan
;
5618 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
5619 alu
.src
[1].value
= 4;
5622 alu
.dst
.write
= i
== 0;
5625 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5630 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5631 alu
.op
= ALU_OP2_MULLO_INT
;
5632 alu
.src
[0].sel
= src_gpr
;
5633 alu
.src
[0].chan
= sample_chan
;
5634 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
5635 alu
.src
[1].value
= 4;
5640 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5645 /* sample_index = temp.w >> temp.x */
5646 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5647 alu
.op
= ALU_OP2_LSHR_INT
;
5648 alu
.src
[0].sel
= temp
;
5649 alu
.src
[0].chan
= 3;
5650 alu
.src
[1].sel
= temp
;
5651 alu
.src
[1].chan
= 0;
5652 alu
.dst
.sel
= src_gpr
;
5653 alu
.dst
.chan
= sample_chan
;
5656 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5660 /* sample_index & 0xF */
5661 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5662 alu
.op
= ALU_OP2_AND_INT
;
5663 alu
.src
[0].sel
= src_gpr
;
5664 alu
.src
[0].chan
= sample_chan
;
5665 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
5666 alu
.src
[1].value
= 0xF;
5667 alu
.dst
.sel
= src_gpr
;
5668 alu
.dst
.chan
= sample_chan
;
5671 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5675 /* visualize the FMASK */
5676 for (i
= 0; i
< 4; i
++) {
5677 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5678 alu
.op
= ALU_OP1_INT_TO_FLT
;
5679 alu
.src
[0].sel
= src_gpr
;
5680 alu
.src
[0].chan
= sample_chan
;
5681 alu
.dst
.sel
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
5685 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5693 /* does this shader want a num layers from TXQ for a cube array? */
5694 if (has_txq_cube_array_z
) {
5695 int id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
5697 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5698 alu
.op
= ALU_OP1_MOV
;
5700 alu
.src
[0].sel
= 512 + (id
/ 4);
5701 alu
.src
[0].kc_bank
= R600_TXQ_CONST_BUFFER
;
5702 alu
.src
[0].chan
= id
% 4;
5703 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
5705 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5708 /* disable writemask from texture instruction */
5709 inst
->Dst
[0].Register
.WriteMask
&= ~4;
5712 opcode
= ctx
->inst_info
->op
;
5713 if (opcode
== FETCH_OP_GATHER4
&&
5714 inst
->TexOffsets
[0].File
!= TGSI_FILE_NULL
&&
5715 inst
->TexOffsets
[0].File
!= TGSI_FILE_IMMEDIATE
) {
5716 opcode
= FETCH_OP_GATHER4_O
;
5718 /* GATHER4_O/GATHER4_C_O use offset values loaded by
5719 SET_TEXTURE_OFFSETS instruction. The immediate offset values
5720 encoded in the instruction are ignored. */
5721 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
5722 tex
.op
= FETCH_OP_SET_TEXTURE_OFFSETS
;
5723 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
5724 tex
.sampler_index_mode
= sampler_index_mode
;
5725 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
5726 tex
.resource_index_mode
= sampler_index_mode
;
5728 tex
.src_gpr
= ctx
->file_offset
[inst
->TexOffsets
[0].File
] + inst
->TexOffsets
[0].Index
;
5729 tex
.src_sel_x
= inst
->TexOffsets
[0].SwizzleX
;
5730 tex
.src_sel_y
= inst
->TexOffsets
[0].SwizzleY
;
5731 tex
.src_sel_z
= inst
->TexOffsets
[0].SwizzleZ
;
5739 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
5744 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
5745 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
5746 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
5747 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
5748 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
5749 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
5750 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
5752 case FETCH_OP_SAMPLE
:
5753 opcode
= FETCH_OP_SAMPLE_C
;
5755 case FETCH_OP_SAMPLE_L
:
5756 opcode
= FETCH_OP_SAMPLE_C_L
;
5758 case FETCH_OP_SAMPLE_LB
:
5759 opcode
= FETCH_OP_SAMPLE_C_LB
;
5761 case FETCH_OP_SAMPLE_G
:
5762 opcode
= FETCH_OP_SAMPLE_C_G
;
5764 /* Texture gather variants */
5765 case FETCH_OP_GATHER4
:
5766 opcode
= FETCH_OP_GATHER4_C
;
5768 case FETCH_OP_GATHER4_O
:
5769 opcode
= FETCH_OP_GATHER4_C_O
;
5774 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
5777 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
5778 tex
.sampler_index_mode
= sampler_index_mode
;
5779 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
5780 tex
.resource_index_mode
= sampler_index_mode
;
5781 tex
.src_gpr
= src_gpr
;
5782 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
5784 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_DDX_FINE
||
5785 inst
->Instruction
.Opcode
== TGSI_OPCODE_DDY_FINE
) {
5786 tex
.inst_mod
= 1; /* per pixel gradient calculation instead of per 2x2 quad */
5789 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
) {
5790 int8_t texture_component_select
= ctx
->literals
[4 * inst
->Src
[1].Register
.Index
+ inst
->Src
[1].Register
.SwizzleX
];
5791 tex
.inst_mod
= texture_component_select
;
5793 if (ctx
->bc
->chip_class
== CAYMAN
) {
5794 /* GATHER4 result order is different from TGSI TG4 */
5795 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 0 : 7;
5796 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 1 : 7;
5797 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 2 : 7;
5798 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
5800 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
5801 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
5802 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
5803 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
5806 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LODQ
) {
5807 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
5808 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
5813 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
5814 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
5815 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
5816 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
5820 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ_LZ
) {
5825 } else if (src_loaded
) {
5831 tex
.src_sel_x
= ctx
->src
[0].swizzle
[0];
5832 tex
.src_sel_y
= ctx
->src
[0].swizzle
[1];
5833 tex
.src_sel_z
= ctx
->src
[0].swizzle
[2];
5834 tex
.src_sel_w
= ctx
->src
[0].swizzle
[3];
5835 tex
.src_rel
= ctx
->src
[0].rel
;
5838 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
5839 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
5840 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
5841 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
5845 tex
.src_sel_w
= 2; /* route Z compare or Lod value into W */
5848 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
&&
5849 inst
->Texture
.Texture
!= TGSI_TEXTURE_SHADOWRECT
) {
5850 tex
.coord_type_x
= 1;
5851 tex
.coord_type_y
= 1;
5853 tex
.coord_type_z
= 1;
5854 tex
.coord_type_w
= 1;
5856 tex
.offset_x
= offset_x
;
5857 tex
.offset_y
= offset_y
;
5858 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
&&
5859 (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
||
5860 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
)) {
5864 tex
.offset_z
= offset_z
;
5867 /* Put the depth for comparison in W.
5868 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
5869 * Some instructions expect the depth in Z. */
5870 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
5871 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
5872 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
5873 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) &&
5874 opcode
!= FETCH_OP_SAMPLE_C_L
&&
5875 opcode
!= FETCH_OP_SAMPLE_C_LB
) {
5876 tex
.src_sel_w
= tex
.src_sel_z
;
5879 if (inst
->Texture
.Texture
== TGSI_TEXTURE_1D_ARRAY
||
5880 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) {
5881 if (opcode
== FETCH_OP_SAMPLE_C_L
||
5882 opcode
== FETCH_OP_SAMPLE_C_LB
) {
5883 /* the array index is read from Y */
5884 tex
.coord_type_y
= 0;
5886 /* the array index is read from Z */
5887 tex
.coord_type_z
= 0;
5888 tex
.src_sel_z
= tex
.src_sel_y
;
5890 } else if (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
||
5891 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
5892 ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
5893 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
5894 (ctx
->bc
->chip_class
>= EVERGREEN
)))
5895 /* the array index is read from Z */
5896 tex
.coord_type_z
= 0;
5898 /* mask unused source components */
5899 if (opcode
== FETCH_OP_SAMPLE
|| opcode
== FETCH_OP_GATHER4
) {
5900 switch (inst
->Texture
.Texture
) {
5901 case TGSI_TEXTURE_2D
:
5902 case TGSI_TEXTURE_RECT
:
5906 case TGSI_TEXTURE_1D_ARRAY
:
5910 case TGSI_TEXTURE_1D
:
5918 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
5922 /* add shadow ambient support - gallium doesn't do it yet */
5926 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
5928 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5929 struct r600_bytecode_alu alu
;
5930 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
5934 /* optimize if it's just an equal balance */
5935 if (ctx
->src
[0].sel
== V_SQ_ALU_SRC_0_5
) {
5936 for (i
= 0; i
< lasti
+ 1; i
++) {
5937 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
5940 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5941 alu
.op
= ALU_OP2_ADD
;
5942 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5943 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
5945 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5950 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5958 for (i
= 0; i
< lasti
+ 1; i
++) {
5959 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
5962 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5963 alu
.op
= ALU_OP2_ADD
;
5964 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
5965 alu
.src
[0].chan
= 0;
5966 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5967 r600_bytecode_src_toggle_neg(&alu
.src
[1]);
5968 alu
.dst
.sel
= ctx
->temp_reg
;
5974 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5979 /* (1 - src0) * src2 */
5980 for (i
= 0; i
< lasti
+ 1; i
++) {
5981 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
5984 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5985 alu
.op
= ALU_OP2_MUL
;
5986 alu
.src
[0].sel
= ctx
->temp_reg
;
5987 alu
.src
[0].chan
= i
;
5988 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
5989 alu
.dst
.sel
= ctx
->temp_reg
;
5995 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6000 /* src0 * src1 + (1 - src0) * src2 */
6001 for (i
= 0; i
< lasti
+ 1; i
++) {
6002 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6005 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6006 alu
.op
= ALU_OP3_MULADD
;
6008 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6009 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
6010 alu
.src
[2].sel
= ctx
->temp_reg
;
6011 alu
.src
[2].chan
= i
;
6013 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6018 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6025 static int tgsi_cmp(struct r600_shader_ctx
*ctx
)
6027 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6028 struct r600_bytecode_alu alu
;
6030 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6032 for (i
= 0; i
< lasti
+ 1; i
++) {
6033 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6036 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6037 alu
.op
= ALU_OP3_CNDGE
;
6038 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6039 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
6040 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[1], i
);
6041 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6047 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6054 static int tgsi_ucmp(struct r600_shader_ctx
*ctx
)
6056 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6057 struct r600_bytecode_alu alu
;
6059 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6061 for (i
= 0; i
< lasti
+ 1; i
++) {
6062 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6065 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6066 alu
.op
= ALU_OP3_CNDGE_INT
;
6067 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6068 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
6069 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[1], i
);
6070 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6076 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6083 static int tgsi_xpd(struct r600_shader_ctx
*ctx
)
6085 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6086 static const unsigned int src0_swizzle
[] = {2, 0, 1};
6087 static const unsigned int src1_swizzle
[] = {1, 2, 0};
6088 struct r600_bytecode_alu alu
;
6089 uint32_t use_temp
= 0;
6092 if (inst
->Dst
[0].Register
.WriteMask
!= 0xf)
6095 for (i
= 0; i
< 4; i
++) {
6096 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6097 alu
.op
= ALU_OP2_MUL
;
6099 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src0_swizzle
[i
]);
6100 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], src1_swizzle
[i
]);
6102 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
6103 alu
.src
[0].chan
= i
;
6104 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
6105 alu
.src
[1].chan
= i
;
6108 alu
.dst
.sel
= ctx
->temp_reg
;
6114 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6119 for (i
= 0; i
< 4; i
++) {
6120 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6121 alu
.op
= ALU_OP3_MULADD
;
6124 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src1_swizzle
[i
]);
6125 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], src0_swizzle
[i
]);
6127 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
6128 alu
.src
[0].chan
= i
;
6129 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
6130 alu
.src
[1].chan
= i
;
6133 alu
.src
[2].sel
= ctx
->temp_reg
;
6135 alu
.src
[2].chan
= i
;
6138 alu
.dst
.sel
= ctx
->temp_reg
;
6140 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6146 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6151 return tgsi_helper_copy(ctx
, inst
);
6155 static int tgsi_exp(struct r600_shader_ctx
*ctx
)
6157 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6158 struct r600_bytecode_alu alu
;
6162 /* result.x = 2^floor(src); */
6163 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
6164 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6166 alu
.op
= ALU_OP1_FLOOR
;
6167 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
6169 alu
.dst
.sel
= ctx
->temp_reg
;
6173 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6177 if (ctx
->bc
->chip_class
== CAYMAN
) {
6178 for (i
= 0; i
< 3; i
++) {
6179 alu
.op
= ALU_OP1_EXP_IEEE
;
6180 alu
.src
[0].sel
= ctx
->temp_reg
;
6181 alu
.src
[0].chan
= 0;
6183 alu
.dst
.sel
= ctx
->temp_reg
;
6185 alu
.dst
.write
= i
== 0;
6187 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6192 alu
.op
= ALU_OP1_EXP_IEEE
;
6193 alu
.src
[0].sel
= ctx
->temp_reg
;
6194 alu
.src
[0].chan
= 0;
6196 alu
.dst
.sel
= ctx
->temp_reg
;
6200 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6206 /* result.y = tmp - floor(tmp); */
6207 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
6208 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6210 alu
.op
= ALU_OP1_FRACT
;
6211 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
6213 alu
.dst
.sel
= ctx
->temp_reg
;
6215 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6224 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6229 /* result.z = RoughApprox2ToX(tmp);*/
6230 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 0x1) {
6231 if (ctx
->bc
->chip_class
== CAYMAN
) {
6232 for (i
= 0; i
< 3; i
++) {
6233 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6234 alu
.op
= ALU_OP1_EXP_IEEE
;
6235 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
6237 alu
.dst
.sel
= ctx
->temp_reg
;
6244 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6249 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6250 alu
.op
= ALU_OP1_EXP_IEEE
;
6251 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
6253 alu
.dst
.sel
= ctx
->temp_reg
;
6259 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6265 /* result.w = 1.0;*/
6266 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 0x1) {
6267 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6269 alu
.op
= ALU_OP1_MOV
;
6270 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
6271 alu
.src
[0].chan
= 0;
6273 alu
.dst
.sel
= ctx
->temp_reg
;
6277 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6281 return tgsi_helper_copy(ctx
, inst
);
6284 static int tgsi_log(struct r600_shader_ctx
*ctx
)
6286 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6287 struct r600_bytecode_alu alu
;
6291 /* result.x = floor(log2(|src|)); */
6292 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
6293 if (ctx
->bc
->chip_class
== CAYMAN
) {
6294 for (i
= 0; i
< 3; i
++) {
6295 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6297 alu
.op
= ALU_OP1_LOG_IEEE
;
6298 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
6299 r600_bytecode_src_set_abs(&alu
.src
[0]);
6301 alu
.dst
.sel
= ctx
->temp_reg
;
6307 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6313 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6315 alu
.op
= ALU_OP1_LOG_IEEE
;
6316 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
6317 r600_bytecode_src_set_abs(&alu
.src
[0]);
6319 alu
.dst
.sel
= ctx
->temp_reg
;
6323 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6328 alu
.op
= ALU_OP1_FLOOR
;
6329 alu
.src
[0].sel
= ctx
->temp_reg
;
6330 alu
.src
[0].chan
= 0;
6332 alu
.dst
.sel
= ctx
->temp_reg
;
6337 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6342 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
6343 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
6345 if (ctx
->bc
->chip_class
== CAYMAN
) {
6346 for (i
= 0; i
< 3; i
++) {
6347 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6349 alu
.op
= ALU_OP1_LOG_IEEE
;
6350 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
6351 r600_bytecode_src_set_abs(&alu
.src
[0]);
6353 alu
.dst
.sel
= ctx
->temp_reg
;
6360 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6365 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6367 alu
.op
= ALU_OP1_LOG_IEEE
;
6368 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
6369 r600_bytecode_src_set_abs(&alu
.src
[0]);
6371 alu
.dst
.sel
= ctx
->temp_reg
;
6376 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6381 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6383 alu
.op
= ALU_OP1_FLOOR
;
6384 alu
.src
[0].sel
= ctx
->temp_reg
;
6385 alu
.src
[0].chan
= 1;
6387 alu
.dst
.sel
= ctx
->temp_reg
;
6392 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6396 if (ctx
->bc
->chip_class
== CAYMAN
) {
6397 for (i
= 0; i
< 3; i
++) {
6398 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6399 alu
.op
= ALU_OP1_EXP_IEEE
;
6400 alu
.src
[0].sel
= ctx
->temp_reg
;
6401 alu
.src
[0].chan
= 1;
6403 alu
.dst
.sel
= ctx
->temp_reg
;
6410 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6415 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6416 alu
.op
= ALU_OP1_EXP_IEEE
;
6417 alu
.src
[0].sel
= ctx
->temp_reg
;
6418 alu
.src
[0].chan
= 1;
6420 alu
.dst
.sel
= ctx
->temp_reg
;
6425 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6430 if (ctx
->bc
->chip_class
== CAYMAN
) {
6431 for (i
= 0; i
< 3; i
++) {
6432 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6433 alu
.op
= ALU_OP1_RECIP_IEEE
;
6434 alu
.src
[0].sel
= ctx
->temp_reg
;
6435 alu
.src
[0].chan
= 1;
6437 alu
.dst
.sel
= ctx
->temp_reg
;
6444 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6449 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6450 alu
.op
= ALU_OP1_RECIP_IEEE
;
6451 alu
.src
[0].sel
= ctx
->temp_reg
;
6452 alu
.src
[0].chan
= 1;
6454 alu
.dst
.sel
= ctx
->temp_reg
;
6459 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6464 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6466 alu
.op
= ALU_OP2_MUL
;
6468 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
6469 r600_bytecode_src_set_abs(&alu
.src
[0]);
6471 alu
.src
[1].sel
= ctx
->temp_reg
;
6472 alu
.src
[1].chan
= 1;
6474 alu
.dst
.sel
= ctx
->temp_reg
;
6479 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6484 /* result.z = log2(|src|);*/
6485 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 1) {
6486 if (ctx
->bc
->chip_class
== CAYMAN
) {
6487 for (i
= 0; i
< 3; i
++) {
6488 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6490 alu
.op
= ALU_OP1_LOG_IEEE
;
6491 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
6492 r600_bytecode_src_set_abs(&alu
.src
[0]);
6494 alu
.dst
.sel
= ctx
->temp_reg
;
6501 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6506 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6508 alu
.op
= ALU_OP1_LOG_IEEE
;
6509 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
6510 r600_bytecode_src_set_abs(&alu
.src
[0]);
6512 alu
.dst
.sel
= ctx
->temp_reg
;
6517 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6523 /* result.w = 1.0; */
6524 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 1) {
6525 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6527 alu
.op
= ALU_OP1_MOV
;
6528 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
6529 alu
.src
[0].chan
= 0;
6531 alu
.dst
.sel
= ctx
->temp_reg
;
6536 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6541 return tgsi_helper_copy(ctx
, inst
);
6544 static int tgsi_eg_arl(struct r600_shader_ctx
*ctx
)
6546 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6547 struct r600_bytecode_alu alu
;
6549 int i
, lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6550 unsigned reg
= inst
->Dst
[0].Register
.Index
> 0 ? ctx
->bc
->index_reg
[inst
->Dst
[0].Register
.Index
- 1] : ctx
->bc
->ar_reg
;
6552 assert(inst
->Dst
[0].Register
.Index
< 3);
6553 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6555 switch (inst
->Instruction
.Opcode
) {
6556 case TGSI_OPCODE_ARL
:
6557 alu
.op
= ALU_OP1_FLT_TO_INT_FLOOR
;
6559 case TGSI_OPCODE_ARR
:
6560 alu
.op
= ALU_OP1_FLT_TO_INT
;
6562 case TGSI_OPCODE_UARL
:
6563 alu
.op
= ALU_OP1_MOV
;
6570 for (i
= 0; i
<= lasti
; ++i
) {
6571 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6573 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6574 alu
.last
= i
== lasti
;
6578 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6583 if (inst
->Dst
[0].Register
.Index
> 0)
6584 ctx
->bc
->index_loaded
[inst
->Dst
[0].Register
.Index
- 1] = 0;
6586 ctx
->bc
->ar_loaded
= 0;
6590 static int tgsi_r600_arl(struct r600_shader_ctx
*ctx
)
6592 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6593 struct r600_bytecode_alu alu
;
6595 int i
, lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6597 switch (inst
->Instruction
.Opcode
) {
6598 case TGSI_OPCODE_ARL
:
6599 memset(&alu
, 0, sizeof(alu
));
6600 alu
.op
= ALU_OP1_FLOOR
;
6601 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
6603 for (i
= 0; i
<= lasti
; ++i
) {
6604 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
6606 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6607 alu
.last
= i
== lasti
;
6608 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
6613 memset(&alu
, 0, sizeof(alu
));
6614 alu
.op
= ALU_OP1_FLT_TO_INT
;
6615 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
6616 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
6618 /* FLT_TO_INT is trans-only on r600/r700 */
6620 for (i
= 0; i
<= lasti
; ++i
) {
6622 alu
.src
[0].chan
= i
;
6623 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
6627 case TGSI_OPCODE_ARR
:
6628 memset(&alu
, 0, sizeof(alu
));
6629 alu
.op
= ALU_OP1_FLT_TO_INT
;
6630 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
6632 /* FLT_TO_INT is trans-only on r600/r700 */
6634 for (i
= 0; i
<= lasti
; ++i
) {
6635 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
6637 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6638 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
6643 case TGSI_OPCODE_UARL
:
6644 memset(&alu
, 0, sizeof(alu
));
6645 alu
.op
= ALU_OP1_MOV
;
6646 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
6648 for (i
= 0; i
<= lasti
; ++i
) {
6649 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
6651 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6652 alu
.last
= i
== lasti
;
6653 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
6663 ctx
->bc
->ar_loaded
= 0;
6667 static int tgsi_opdst(struct r600_shader_ctx
*ctx
)
6669 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6670 struct r600_bytecode_alu alu
;
6673 for (i
= 0; i
< 4; i
++) {
6674 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6676 alu
.op
= ALU_OP2_MUL
;
6677 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6679 if (i
== 0 || i
== 3) {
6680 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
6682 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6685 if (i
== 0 || i
== 2) {
6686 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
6688 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
6692 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6699 static int emit_logic_pred(struct r600_shader_ctx
*ctx
, int opcode
, int alu_type
)
6701 struct r600_bytecode_alu alu
;
6704 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6706 alu
.execute_mask
= 1;
6707 alu
.update_pred
= 1;
6709 alu
.dst
.sel
= ctx
->temp_reg
;
6713 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
6714 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
6715 alu
.src
[1].chan
= 0;
6719 r
= r600_bytecode_add_alu_type(ctx
->bc
, &alu
, alu_type
);
6725 static int pops(struct r600_shader_ctx
*ctx
, int pops
)
6727 unsigned force_pop
= ctx
->bc
->force_add_cf
;
6731 if (ctx
->bc
->cf_last
) {
6732 if (ctx
->bc
->cf_last
->op
== CF_OP_ALU
)
6734 else if (ctx
->bc
->cf_last
->op
== CF_OP_ALU_POP_AFTER
)
6739 ctx
->bc
->cf_last
->op
= CF_OP_ALU_POP_AFTER
;
6740 ctx
->bc
->force_add_cf
= 1;
6741 } else if (alu_pop
== 2) {
6742 ctx
->bc
->cf_last
->op
= CF_OP_ALU_POP2_AFTER
;
6743 ctx
->bc
->force_add_cf
= 1;
6750 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_POP
);
6751 ctx
->bc
->cf_last
->pop_count
= pops
;
6752 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
6758 static inline void callstack_update_max_depth(struct r600_shader_ctx
*ctx
,
6761 struct r600_stack_info
*stack
= &ctx
->bc
->stack
;
6762 unsigned elements
, entries
;
6764 unsigned entry_size
= stack
->entry_size
;
6766 elements
= (stack
->loop
+ stack
->push_wqm
) * entry_size
;
6767 elements
+= stack
->push
;
6769 switch (ctx
->bc
->chip_class
) {
6772 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
6773 * the stack must be reserved to hold the current active/continue
6775 if (reason
== FC_PUSH_VPM
) {
6781 /* r9xx: any stack operation on empty stack consumes 2 additional
6786 /* FIXME: do the two elements added above cover the cases for the
6790 /* r8xx+: 2 extra elements are not always required, but one extra
6791 * element must be added for each of the following cases:
6792 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
6794 * (Currently we don't use ALU_ELSE_AFTER.)
6795 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
6796 * PUSH instruction executed.
6798 * NOTE: it seems we also need to reserve additional element in some
6799 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
6800 * then STACK_SIZE should be 2 instead of 1 */
6801 if (reason
== FC_PUSH_VPM
) {
6811 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
6812 * for all chips, so we use 4 in the final formula, not the real entry_size
6816 entries
= (elements
+ (entry_size
- 1)) / entry_size
;
6818 if (entries
> stack
->max_entries
)
6819 stack
->max_entries
= entries
;
6822 static inline void callstack_pop(struct r600_shader_ctx
*ctx
, unsigned reason
)
6826 --ctx
->bc
->stack
.push
;
6827 assert(ctx
->bc
->stack
.push
>= 0);
6830 --ctx
->bc
->stack
.push_wqm
;
6831 assert(ctx
->bc
->stack
.push_wqm
>= 0);
6834 --ctx
->bc
->stack
.loop
;
6835 assert(ctx
->bc
->stack
.loop
>= 0);
6843 static inline void callstack_push(struct r600_shader_ctx
*ctx
, unsigned reason
)
6847 ++ctx
->bc
->stack
.push
;
6850 ++ctx
->bc
->stack
.push_wqm
;
6852 ++ctx
->bc
->stack
.loop
;
6858 callstack_update_max_depth(ctx
, reason
);
6861 static void fc_set_mid(struct r600_shader_ctx
*ctx
, int fc_sp
)
6863 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[fc_sp
];
6865 sp
->mid
= realloc((void *)sp
->mid
,
6866 sizeof(struct r600_bytecode_cf
*) * (sp
->num_mid
+ 1));
6867 sp
->mid
[sp
->num_mid
] = ctx
->bc
->cf_last
;
6871 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
)
6874 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
= type
;
6875 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
= ctx
->bc
->cf_last
;
6878 static void fc_poplevel(struct r600_shader_ctx
*ctx
)
6880 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
];
6890 static int emit_return(struct r600_shader_ctx
*ctx
)
6892 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_RETURN
));
6896 static int emit_jump_to_offset(struct r600_shader_ctx
*ctx
, int pops
, int offset
)
6899 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
));
6900 ctx
->bc
->cf_last
->pop_count
= pops
;
6901 /* XXX work out offset */
6905 static int emit_setret_in_loop_flag(struct r600_shader_ctx
*ctx
, unsigned flag_value
)
6910 static void emit_testflag(struct r600_shader_ctx
*ctx
)
6915 static void emit_return_on_flag(struct r600_shader_ctx
*ctx
, unsigned ifidx
)
6918 emit_jump_to_offset(ctx
, 1, 4);
6919 emit_setret_in_loop_flag(ctx
, V_SQ_ALU_SRC_0
);
6920 pops(ctx
, ifidx
+ 1);
6924 static void break_loop_on_flag(struct r600_shader_ctx
*ctx
, unsigned fc_sp
)
6928 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
6929 ctx
->bc
->cf_last
->pop_count
= 1;
6931 fc_set_mid(ctx
, fc_sp
);
6937 static int emit_if(struct r600_shader_ctx
*ctx
, int opcode
)
6939 int alu_type
= CF_OP_ALU_PUSH_BEFORE
;
6941 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
6942 * LOOP_STARTxxx for nested loops may put the branch stack into a state
6943 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
6944 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
6945 if (ctx
->bc
->chip_class
== CAYMAN
&& ctx
->bc
->stack
.loop
> 1) {
6946 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_PUSH
);
6947 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
6948 alu_type
= CF_OP_ALU
;
6951 emit_logic_pred(ctx
, opcode
, alu_type
);
6953 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
);
6955 fc_pushlevel(ctx
, FC_IF
);
6957 callstack_push(ctx
, FC_PUSH_VPM
);
6961 static int tgsi_if(struct r600_shader_ctx
*ctx
)
6963 return emit_if(ctx
, ALU_OP2_PRED_SETNE
);
6966 static int tgsi_uif(struct r600_shader_ctx
*ctx
)
6968 return emit_if(ctx
, ALU_OP2_PRED_SETNE_INT
);
6971 static int tgsi_else(struct r600_shader_ctx
*ctx
)
6973 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_ELSE
);
6974 ctx
->bc
->cf_last
->pop_count
= 1;
6976 fc_set_mid(ctx
, ctx
->bc
->fc_sp
);
6977 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
;
6981 static int tgsi_endif(struct r600_shader_ctx
*ctx
)
6984 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_IF
) {
6985 R600_ERR("if/endif unbalanced in shader\n");
6989 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
== NULL
) {
6990 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
6991 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->pop_count
= 1;
6993 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[0]->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
6997 callstack_pop(ctx
, FC_PUSH_VPM
);
7001 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
)
7003 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
7004 * limited to 4096 iterations, like the other LOOP_* instructions. */
7005 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_LOOP_START_DX10
);
7007 fc_pushlevel(ctx
, FC_LOOP
);
7009 /* check stack depth */
7010 callstack_push(ctx
, FC_LOOP
);
7014 static int tgsi_endloop(struct r600_shader_ctx
*ctx
)
7018 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_LOOP_END
);
7020 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_LOOP
) {
7021 R600_ERR("loop/endloop in shader code are not paired.\n");
7025 /* fixup loop pointers - from r600isa
7026 LOOP END points to CF after LOOP START,
7027 LOOP START point to CF after LOOP END
7028 BRK/CONT point to LOOP END CF
7030 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->id
+ 2;
7032 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
7034 for (i
= 0; i
< ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].num_mid
; i
++) {
7035 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[i
]->cf_addr
= ctx
->bc
->cf_last
->id
;
7037 /* XXX add LOOPRET support */
7039 callstack_pop(ctx
, FC_LOOP
);
7043 static int tgsi_loop_breakc(struct r600_shader_ctx
*ctx
)
7048 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
7050 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
].type
)
7054 R600_ERR("BREAKC not inside loop/endloop pair\n");
7058 if (ctx
->bc
->chip_class
== EVERGREEN
&&
7059 ctx
->bc
->family
!= CHIP_CYPRESS
&&
7060 ctx
->bc
->family
!= CHIP_JUNIPER
) {
7061 /* HW bug: ALU_BREAK does not save the active mask correctly */
7066 r
= r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_LOOP_BREAK
);
7069 fc_set_mid(ctx
, fscp
);
7071 return tgsi_endif(ctx
);
7073 r
= emit_logic_pred(ctx
, ALU_OP2_PRED_SETE_INT
, CF_OP_ALU_BREAK
);
7076 fc_set_mid(ctx
, fscp
);
7082 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
)
7086 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
7088 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
].type
)
7093 R600_ERR("Break not inside loop/endloop pair\n");
7097 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
7099 fc_set_mid(ctx
, fscp
);
7104 static int tgsi_gs_emit(struct r600_shader_ctx
*ctx
)
7106 if (ctx
->inst_info
->op
== CF_OP_EMIT_VERTEX
)
7107 emit_gs_ring_writes(ctx
, TRUE
);
7109 return r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
7112 static int tgsi_umad(struct r600_shader_ctx
*ctx
)
7114 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7115 struct r600_bytecode_alu alu
;
7117 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
7120 for (i
= 0; i
< lasti
+ 1; i
++) {
7121 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7124 if (ctx
->bc
->chip_class
== CAYMAN
) {
7125 for (j
= 0 ; j
< 4; j
++) {
7126 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7128 alu
.op
= ALU_OP2_MULLO_UINT
;
7129 for (k
= 0; k
< inst
->Instruction
.NumSrcRegs
; k
++) {
7130 r600_bytecode_src(&alu
.src
[k
], &ctx
->src
[k
], i
);
7133 alu
.dst
.sel
= ctx
->temp_reg
;
7134 alu
.dst
.write
= (j
== i
);
7137 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7142 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7145 alu
.dst
.sel
= ctx
->temp_reg
;
7148 alu
.op
= ALU_OP2_MULLO_UINT
;
7149 for (j
= 0; j
< 2; j
++) {
7150 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
7154 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7161 for (i
= 0; i
< lasti
+ 1; i
++) {
7162 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7165 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7166 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
7168 alu
.op
= ALU_OP2_ADD_INT
;
7170 alu
.src
[0].sel
= ctx
->temp_reg
;
7171 alu
.src
[0].chan
= i
;
7173 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
7177 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7184 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
7185 {TGSI_OPCODE_ARL
, 0, ALU_OP0_NOP
, tgsi_r600_arl
},
7186 {TGSI_OPCODE_MOV
, 0, ALU_OP1_MOV
, tgsi_op2
},
7187 {TGSI_OPCODE_LIT
, 0, ALU_OP0_NOP
, tgsi_lit
},
7190 * For state trackers other than OpenGL, we'll want to use
7191 * _RECIP_IEEE instead.
7193 {TGSI_OPCODE_RCP
, 0, ALU_OP1_RECIP_CLAMPED
, tgsi_trans_srcx_replicate
},
7195 {TGSI_OPCODE_RSQ
, 0, ALU_OP0_NOP
, tgsi_rsq
},
7196 {TGSI_OPCODE_EXP
, 0, ALU_OP0_NOP
, tgsi_exp
},
7197 {TGSI_OPCODE_LOG
, 0, ALU_OP0_NOP
, tgsi_log
},
7198 {TGSI_OPCODE_MUL
, 0, ALU_OP2_MUL
, tgsi_op2
},
7199 {TGSI_OPCODE_ADD
, 0, ALU_OP2_ADD
, tgsi_op2
},
7200 {TGSI_OPCODE_DP3
, 0, ALU_OP2_DOT4
, tgsi_dp
},
7201 {TGSI_OPCODE_DP4
, 0, ALU_OP2_DOT4
, tgsi_dp
},
7202 {TGSI_OPCODE_DST
, 0, ALU_OP0_NOP
, tgsi_opdst
},
7203 {TGSI_OPCODE_MIN
, 0, ALU_OP2_MIN
, tgsi_op2
},
7204 {TGSI_OPCODE_MAX
, 0, ALU_OP2_MAX
, tgsi_op2
},
7205 {TGSI_OPCODE_SLT
, 0, ALU_OP2_SETGT
, tgsi_op2_swap
},
7206 {TGSI_OPCODE_SGE
, 0, ALU_OP2_SETGE
, tgsi_op2
},
7207 {TGSI_OPCODE_MAD
, 1, ALU_OP3_MULADD
, tgsi_op3
},
7208 {TGSI_OPCODE_SUB
, 0, ALU_OP2_ADD
, tgsi_op2
},
7209 {TGSI_OPCODE_LRP
, 0, ALU_OP0_NOP
, tgsi_lrp
},
7210 {TGSI_OPCODE_CND
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7211 {TGSI_OPCODE_SQRT
, 0, ALU_OP1_SQRT_IEEE
, tgsi_trans_srcx_replicate
},
7212 {TGSI_OPCODE_DP2A
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7213 {22, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7214 {23, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7215 {TGSI_OPCODE_FRC
, 0, ALU_OP1_FRACT
, tgsi_op2
},
7216 {TGSI_OPCODE_CLAMP
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7217 {TGSI_OPCODE_FLR
, 0, ALU_OP1_FLOOR
, tgsi_op2
},
7218 {TGSI_OPCODE_ROUND
, 0, ALU_OP1_RNDNE
, tgsi_op2
},
7219 {TGSI_OPCODE_EX2
, 0, ALU_OP1_EXP_IEEE
, tgsi_trans_srcx_replicate
},
7220 {TGSI_OPCODE_LG2
, 0, ALU_OP1_LOG_IEEE
, tgsi_trans_srcx_replicate
},
7221 {TGSI_OPCODE_POW
, 0, ALU_OP0_NOP
, tgsi_pow
},
7222 {TGSI_OPCODE_XPD
, 0, ALU_OP0_NOP
, tgsi_xpd
},
7223 {32, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7224 {TGSI_OPCODE_ABS
, 0, ALU_OP1_MOV
, tgsi_op2
},
7225 {34, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7226 {TGSI_OPCODE_DPH
, 0, ALU_OP2_DOT4
, tgsi_dp
},
7227 {TGSI_OPCODE_COS
, 0, ALU_OP1_COS
, tgsi_trig
},
7228 {TGSI_OPCODE_DDX
, 0, FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
7229 {TGSI_OPCODE_DDY
, 0, FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
7230 {TGSI_OPCODE_KILL
, 0, ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
7231 {TGSI_OPCODE_PK2H
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7232 {TGSI_OPCODE_PK2US
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7233 {TGSI_OPCODE_PK4B
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7234 {TGSI_OPCODE_PK4UB
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7235 {TGSI_OPCODE_RFL
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7236 {TGSI_OPCODE_SEQ
, 0, ALU_OP2_SETE
, tgsi_op2
},
7237 {TGSI_OPCODE_SFL
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7238 {TGSI_OPCODE_SGT
, 0, ALU_OP2_SETGT
, tgsi_op2
},
7239 {TGSI_OPCODE_SIN
, 0, ALU_OP1_SIN
, tgsi_trig
},
7240 {TGSI_OPCODE_SLE
, 0, ALU_OP2_SETGE
, tgsi_op2_swap
},
7241 {TGSI_OPCODE_SNE
, 0, ALU_OP2_SETNE
, tgsi_op2
},
7242 {TGSI_OPCODE_STR
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7243 {TGSI_OPCODE_TEX
, 0, FETCH_OP_SAMPLE
, tgsi_tex
},
7244 {TGSI_OPCODE_TXD
, 0, FETCH_OP_SAMPLE_G
, tgsi_tex
},
7245 {TGSI_OPCODE_TXP
, 0, FETCH_OP_SAMPLE
, tgsi_tex
},
7246 {TGSI_OPCODE_UP2H
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7247 {TGSI_OPCODE_UP2US
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7248 {TGSI_OPCODE_UP4B
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7249 {TGSI_OPCODE_UP4UB
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7250 {59, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7251 {60, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7252 {TGSI_OPCODE_ARR
, 0, ALU_OP0_NOP
, tgsi_r600_arl
},
7253 {TGSI_OPCODE_BRA
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7254 {TGSI_OPCODE_CAL
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7255 {TGSI_OPCODE_RET
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7256 {TGSI_OPCODE_SSG
, 0, ALU_OP0_NOP
, tgsi_ssg
},
7257 {TGSI_OPCODE_CMP
, 0, ALU_OP0_NOP
, tgsi_cmp
},
7258 {TGSI_OPCODE_SCS
, 0, ALU_OP0_NOP
, tgsi_scs
},
7259 {TGSI_OPCODE_TXB
, 0, FETCH_OP_SAMPLE_LB
, tgsi_tex
},
7260 {69, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7261 {TGSI_OPCODE_DIV
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7262 {TGSI_OPCODE_DP2
, 0, ALU_OP2_DOT4
, tgsi_dp
},
7263 {TGSI_OPCODE_TXL
, 0, FETCH_OP_SAMPLE_L
, tgsi_tex
},
7264 {TGSI_OPCODE_BRK
, 0, CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
7265 {TGSI_OPCODE_IF
, 0, ALU_OP0_NOP
, tgsi_if
},
7266 {TGSI_OPCODE_UIF
, 0, ALU_OP0_NOP
, tgsi_uif
},
7267 {76, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7268 {TGSI_OPCODE_ELSE
, 0, ALU_OP0_NOP
, tgsi_else
},
7269 {TGSI_OPCODE_ENDIF
, 0, ALU_OP0_NOP
, tgsi_endif
},
7270 {TGSI_OPCODE_DDX_FINE
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7271 {TGSI_OPCODE_DDY_FINE
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7272 {TGSI_OPCODE_PUSHA
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7273 {TGSI_OPCODE_POPA
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7274 {TGSI_OPCODE_CEIL
, 0, ALU_OP1_CEIL
, tgsi_op2
},
7275 {TGSI_OPCODE_I2F
, 0, ALU_OP1_INT_TO_FLT
, tgsi_op2_trans
},
7276 {TGSI_OPCODE_NOT
, 0, ALU_OP1_NOT_INT
, tgsi_op2
},
7277 {TGSI_OPCODE_TRUNC
, 0, ALU_OP1_TRUNC
, tgsi_op2
},
7278 {TGSI_OPCODE_SHL
, 0, ALU_OP2_LSHL_INT
, tgsi_op2_trans
},
7279 {88, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7280 {TGSI_OPCODE_AND
, 0, ALU_OP2_AND_INT
, tgsi_op2
},
7281 {TGSI_OPCODE_OR
, 0, ALU_OP2_OR_INT
, tgsi_op2
},
7282 {TGSI_OPCODE_MOD
, 0, ALU_OP0_NOP
, tgsi_imod
},
7283 {TGSI_OPCODE_XOR
, 0, ALU_OP2_XOR_INT
, tgsi_op2
},
7284 {TGSI_OPCODE_SAD
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7285 {TGSI_OPCODE_TXF
, 0, FETCH_OP_LD
, tgsi_tex
},
7286 {TGSI_OPCODE_TXQ
, 0, FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
7287 {TGSI_OPCODE_CONT
, 0, CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
7288 {TGSI_OPCODE_EMIT
, 0, CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
7289 {TGSI_OPCODE_ENDPRIM
, 0, CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
7290 {TGSI_OPCODE_BGNLOOP
, 0, ALU_OP0_NOP
, tgsi_bgnloop
},
7291 {TGSI_OPCODE_BGNSUB
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7292 {TGSI_OPCODE_ENDLOOP
, 0, ALU_OP0_NOP
, tgsi_endloop
},
7293 {TGSI_OPCODE_ENDSUB
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7294 {TGSI_OPCODE_TXQ_LZ
, 0, FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
7295 {104, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7296 {105, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7297 {106, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7298 {TGSI_OPCODE_NOP
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7299 {TGSI_OPCODE_FSEQ
, 0, ALU_OP2_SETE_DX10
, tgsi_op2
},
7300 {TGSI_OPCODE_FSGE
, 0, ALU_OP2_SETGE_DX10
, tgsi_op2
},
7301 {TGSI_OPCODE_FSLT
, 0, ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
7302 {TGSI_OPCODE_FSNE
, 0, ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
7303 {112, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7304 {TGSI_OPCODE_CALLNZ
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7305 {114, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7306 {TGSI_OPCODE_BREAKC
, 0, ALU_OP0_NOP
, tgsi_loop_breakc
},
7307 {TGSI_OPCODE_KILL_IF
, 0, ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
7308 {TGSI_OPCODE_END
, 0, ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
7309 {118, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7310 {TGSI_OPCODE_F2I
, 0, ALU_OP1_FLT_TO_INT
, tgsi_op2_trans
},
7311 {TGSI_OPCODE_IDIV
, 0, ALU_OP0_NOP
, tgsi_idiv
},
7312 {TGSI_OPCODE_IMAX
, 0, ALU_OP2_MAX_INT
, tgsi_op2
},
7313 {TGSI_OPCODE_IMIN
, 0, ALU_OP2_MIN_INT
, tgsi_op2
},
7314 {TGSI_OPCODE_INEG
, 0, ALU_OP2_SUB_INT
, tgsi_ineg
},
7315 {TGSI_OPCODE_ISGE
, 0, ALU_OP2_SETGE_INT
, tgsi_op2
},
7316 {TGSI_OPCODE_ISHR
, 0, ALU_OP2_ASHR_INT
, tgsi_op2_trans
},
7317 {TGSI_OPCODE_ISLT
, 0, ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
7318 {TGSI_OPCODE_F2U
, 0, ALU_OP1_FLT_TO_UINT
, tgsi_op2_trans
},
7319 {TGSI_OPCODE_U2F
, 0, ALU_OP1_UINT_TO_FLT
, tgsi_op2_trans
},
7320 {TGSI_OPCODE_UADD
, 0, ALU_OP2_ADD_INT
, tgsi_op2
},
7321 {TGSI_OPCODE_UDIV
, 0, ALU_OP0_NOP
, tgsi_udiv
},
7322 {TGSI_OPCODE_UMAD
, 0, ALU_OP0_NOP
, tgsi_umad
},
7323 {TGSI_OPCODE_UMAX
, 0, ALU_OP2_MAX_UINT
, tgsi_op2
},
7324 {TGSI_OPCODE_UMIN
, 0, ALU_OP2_MIN_UINT
, tgsi_op2
},
7325 {TGSI_OPCODE_UMOD
, 0, ALU_OP0_NOP
, tgsi_umod
},
7326 {TGSI_OPCODE_UMUL
, 0, ALU_OP2_MULLO_UINT
, tgsi_op2_trans
},
7327 {TGSI_OPCODE_USEQ
, 0, ALU_OP2_SETE_INT
, tgsi_op2
},
7328 {TGSI_OPCODE_USGE
, 0, ALU_OP2_SETGE_UINT
, tgsi_op2
},
7329 {TGSI_OPCODE_USHR
, 0, ALU_OP2_LSHR_INT
, tgsi_op2_trans
},
7330 {TGSI_OPCODE_USLT
, 0, ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
7331 {TGSI_OPCODE_USNE
, 0, ALU_OP2_SETNE_INT
, tgsi_op2_swap
},
7332 {TGSI_OPCODE_SWITCH
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7333 {TGSI_OPCODE_CASE
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7334 {TGSI_OPCODE_DEFAULT
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7335 {TGSI_OPCODE_ENDSWITCH
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7336 {TGSI_OPCODE_SAMPLE
, 0, 0, tgsi_unsupported
},
7337 {TGSI_OPCODE_SAMPLE_I
, 0, 0, tgsi_unsupported
},
7338 {TGSI_OPCODE_SAMPLE_I_MS
, 0, 0, tgsi_unsupported
},
7339 {TGSI_OPCODE_SAMPLE_B
, 0, 0, tgsi_unsupported
},
7340 {TGSI_OPCODE_SAMPLE_C
, 0, 0, tgsi_unsupported
},
7341 {TGSI_OPCODE_SAMPLE_C_LZ
, 0, 0, tgsi_unsupported
},
7342 {TGSI_OPCODE_SAMPLE_D
, 0, 0, tgsi_unsupported
},
7343 {TGSI_OPCODE_SAMPLE_L
, 0, 0, tgsi_unsupported
},
7344 {TGSI_OPCODE_GATHER4
, 0, 0, tgsi_unsupported
},
7345 {TGSI_OPCODE_SVIEWINFO
, 0, 0, tgsi_unsupported
},
7346 {TGSI_OPCODE_SAMPLE_POS
, 0, 0, tgsi_unsupported
},
7347 {TGSI_OPCODE_SAMPLE_INFO
, 0, 0, tgsi_unsupported
},
7348 {TGSI_OPCODE_UARL
, 0, ALU_OP1_MOVA_INT
, tgsi_r600_arl
},
7349 {TGSI_OPCODE_UCMP
, 0, ALU_OP0_NOP
, tgsi_ucmp
},
7350 {TGSI_OPCODE_IABS
, 0, 0, tgsi_iabs
},
7351 {TGSI_OPCODE_ISSG
, 0, 0, tgsi_issg
},
7352 {TGSI_OPCODE_LOAD
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7353 {TGSI_OPCODE_STORE
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7354 {TGSI_OPCODE_MFENCE
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7355 {TGSI_OPCODE_LFENCE
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7356 {TGSI_OPCODE_SFENCE
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7357 {TGSI_OPCODE_BARRIER
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7358 {TGSI_OPCODE_ATOMUADD
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7359 {TGSI_OPCODE_ATOMXCHG
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7360 {TGSI_OPCODE_ATOMCAS
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7361 {TGSI_OPCODE_ATOMAND
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7362 {TGSI_OPCODE_ATOMOR
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7363 {TGSI_OPCODE_ATOMXOR
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7364 {TGSI_OPCODE_ATOMUMIN
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7365 {TGSI_OPCODE_ATOMUMAX
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7366 {TGSI_OPCODE_ATOMIMIN
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7367 {TGSI_OPCODE_ATOMIMAX
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7368 {TGSI_OPCODE_TEX2
, 0, FETCH_OP_SAMPLE
, tgsi_tex
},
7369 {TGSI_OPCODE_TXB2
, 0, FETCH_OP_SAMPLE_LB
, tgsi_tex
},
7370 {TGSI_OPCODE_TXL2
, 0, FETCH_OP_SAMPLE_L
, tgsi_tex
},
7371 {TGSI_OPCODE_IMUL_HI
, 0, ALU_OP2_MULHI_INT
, tgsi_op2_trans
},
7372 {TGSI_OPCODE_UMUL_HI
, 0, ALU_OP2_MULHI_UINT
, tgsi_op2_trans
},
7373 {TGSI_OPCODE_TG4
, 0, FETCH_OP_GATHER4
, tgsi_unsupported
},
7374 {TGSI_OPCODE_LODQ
, 0, FETCH_OP_GET_LOD
, tgsi_unsupported
},
7375 {TGSI_OPCODE_IBFE
, 1, ALU_OP3_BFE_INT
, tgsi_unsupported
},
7376 {TGSI_OPCODE_UBFE
, 1, ALU_OP3_BFE_UINT
, tgsi_unsupported
},
7377 {TGSI_OPCODE_BFI
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7378 {TGSI_OPCODE_BREV
, 0, ALU_OP1_BFREV_INT
, tgsi_unsupported
},
7379 {TGSI_OPCODE_POPC
, 0, ALU_OP1_BCNT_INT
, tgsi_unsupported
},
7380 {TGSI_OPCODE_LSB
, 0, ALU_OP1_FFBL_INT
, tgsi_unsupported
},
7381 {TGSI_OPCODE_IMSB
, 0, ALU_OP1_FFBH_INT
, tgsi_unsupported
},
7382 {TGSI_OPCODE_UMSB
, 0, ALU_OP1_FFBH_UINT
, tgsi_unsupported
},
7383 {TGSI_OPCODE_INTERP_CENTROID
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7384 {TGSI_OPCODE_INTERP_SAMPLE
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7385 {TGSI_OPCODE_INTERP_OFFSET
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7386 {TGSI_OPCODE_LAST
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7389 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction
[] = {
7390 {TGSI_OPCODE_ARL
, 0, ALU_OP0_NOP
, tgsi_eg_arl
},
7391 {TGSI_OPCODE_MOV
, 0, ALU_OP1_MOV
, tgsi_op2
},
7392 {TGSI_OPCODE_LIT
, 0, ALU_OP0_NOP
, tgsi_lit
},
7393 {TGSI_OPCODE_RCP
, 0, ALU_OP1_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
7394 {TGSI_OPCODE_RSQ
, 0, ALU_OP1_RECIPSQRT_IEEE
, tgsi_rsq
},
7395 {TGSI_OPCODE_EXP
, 0, ALU_OP0_NOP
, tgsi_exp
},
7396 {TGSI_OPCODE_LOG
, 0, ALU_OP0_NOP
, tgsi_log
},
7397 {TGSI_OPCODE_MUL
, 0, ALU_OP2_MUL
, tgsi_op2
},
7398 {TGSI_OPCODE_ADD
, 0, ALU_OP2_ADD
, tgsi_op2
},
7399 {TGSI_OPCODE_DP3
, 0, ALU_OP2_DOT4
, tgsi_dp
},
7400 {TGSI_OPCODE_DP4
, 0, ALU_OP2_DOT4
, tgsi_dp
},
7401 {TGSI_OPCODE_DST
, 0, ALU_OP0_NOP
, tgsi_opdst
},
7402 {TGSI_OPCODE_MIN
, 0, ALU_OP2_MIN
, tgsi_op2
},
7403 {TGSI_OPCODE_MAX
, 0, ALU_OP2_MAX
, tgsi_op2
},
7404 {TGSI_OPCODE_SLT
, 0, ALU_OP2_SETGT
, tgsi_op2_swap
},
7405 {TGSI_OPCODE_SGE
, 0, ALU_OP2_SETGE
, tgsi_op2
},
7406 {TGSI_OPCODE_MAD
, 1, ALU_OP3_MULADD
, tgsi_op3
},
7407 {TGSI_OPCODE_SUB
, 0, ALU_OP2_ADD
, tgsi_op2
},
7408 {TGSI_OPCODE_LRP
, 0, ALU_OP0_NOP
, tgsi_lrp
},
7409 {TGSI_OPCODE_CND
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7410 {TGSI_OPCODE_SQRT
, 0, ALU_OP1_SQRT_IEEE
, tgsi_trans_srcx_replicate
},
7411 {TGSI_OPCODE_DP2A
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7412 {22, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7413 {23, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7414 {TGSI_OPCODE_FRC
, 0, ALU_OP1_FRACT
, tgsi_op2
},
7415 {TGSI_OPCODE_CLAMP
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7416 {TGSI_OPCODE_FLR
, 0, ALU_OP1_FLOOR
, tgsi_op2
},
7417 {TGSI_OPCODE_ROUND
, 0, ALU_OP1_RNDNE
, tgsi_op2
},
7418 {TGSI_OPCODE_EX2
, 0, ALU_OP1_EXP_IEEE
, tgsi_trans_srcx_replicate
},
7419 {TGSI_OPCODE_LG2
, 0, ALU_OP1_LOG_IEEE
, tgsi_trans_srcx_replicate
},
7420 {TGSI_OPCODE_POW
, 0, ALU_OP0_NOP
, tgsi_pow
},
7421 {TGSI_OPCODE_XPD
, 0, ALU_OP0_NOP
, tgsi_xpd
},
7422 {32, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7423 {TGSI_OPCODE_ABS
, 0, ALU_OP1_MOV
, tgsi_op2
},
7424 {34, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7425 {TGSI_OPCODE_DPH
, 0, ALU_OP2_DOT4
, tgsi_dp
},
7426 {TGSI_OPCODE_COS
, 0, ALU_OP1_COS
, tgsi_trig
},
7427 {TGSI_OPCODE_DDX
, 0, FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
7428 {TGSI_OPCODE_DDY
, 0, FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
7429 {TGSI_OPCODE_KILL
, 0, ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
7430 {TGSI_OPCODE_PK2H
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7431 {TGSI_OPCODE_PK2US
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7432 {TGSI_OPCODE_PK4B
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7433 {TGSI_OPCODE_PK4UB
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7434 {TGSI_OPCODE_RFL
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7435 {TGSI_OPCODE_SEQ
, 0, ALU_OP2_SETE
, tgsi_op2
},
7436 {TGSI_OPCODE_SFL
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7437 {TGSI_OPCODE_SGT
, 0, ALU_OP2_SETGT
, tgsi_op2
},
7438 {TGSI_OPCODE_SIN
, 0, ALU_OP1_SIN
, tgsi_trig
},
7439 {TGSI_OPCODE_SLE
, 0, ALU_OP2_SETGE
, tgsi_op2_swap
},
7440 {TGSI_OPCODE_SNE
, 0, ALU_OP2_SETNE
, tgsi_op2
},
7441 {TGSI_OPCODE_STR
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7442 {TGSI_OPCODE_TEX
, 0, FETCH_OP_SAMPLE
, tgsi_tex
},
7443 {TGSI_OPCODE_TXD
, 0, FETCH_OP_SAMPLE_G
, tgsi_tex
},
7444 {TGSI_OPCODE_TXP
, 0, FETCH_OP_SAMPLE
, tgsi_tex
},
7445 {TGSI_OPCODE_UP2H
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7446 {TGSI_OPCODE_UP2US
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7447 {TGSI_OPCODE_UP4B
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7448 {TGSI_OPCODE_UP4UB
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7449 {59, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7450 {60, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7451 {TGSI_OPCODE_ARR
, 0, ALU_OP0_NOP
, tgsi_eg_arl
},
7452 {TGSI_OPCODE_BRA
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7453 {TGSI_OPCODE_CAL
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7454 {TGSI_OPCODE_RET
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7455 {TGSI_OPCODE_SSG
, 0, ALU_OP0_NOP
, tgsi_ssg
},
7456 {TGSI_OPCODE_CMP
, 0, ALU_OP0_NOP
, tgsi_cmp
},
7457 {TGSI_OPCODE_SCS
, 0, ALU_OP0_NOP
, tgsi_scs
},
7458 {TGSI_OPCODE_TXB
, 0, FETCH_OP_SAMPLE_LB
, tgsi_tex
},
7459 {69, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7460 {TGSI_OPCODE_DIV
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7461 {TGSI_OPCODE_DP2
, 0, ALU_OP2_DOT4
, tgsi_dp
},
7462 {TGSI_OPCODE_TXL
, 0, FETCH_OP_SAMPLE_L
, tgsi_tex
},
7463 {TGSI_OPCODE_BRK
, 0, CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
7464 {TGSI_OPCODE_IF
, 0, ALU_OP0_NOP
, tgsi_if
},
7465 {TGSI_OPCODE_UIF
, 0, ALU_OP0_NOP
, tgsi_uif
},
7466 {76, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7467 {TGSI_OPCODE_ELSE
, 0, ALU_OP0_NOP
, tgsi_else
},
7468 {TGSI_OPCODE_ENDIF
, 0, ALU_OP0_NOP
, tgsi_endif
},
7469 {TGSI_OPCODE_DDX_FINE
, 0, FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
7470 {TGSI_OPCODE_DDY_FINE
, 0, FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
7471 {TGSI_OPCODE_PUSHA
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7472 {TGSI_OPCODE_POPA
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7473 {TGSI_OPCODE_CEIL
, 0, ALU_OP1_CEIL
, tgsi_op2
},
7474 {TGSI_OPCODE_I2F
, 0, ALU_OP1_INT_TO_FLT
, tgsi_op2_trans
},
7475 {TGSI_OPCODE_NOT
, 0, ALU_OP1_NOT_INT
, tgsi_op2
},
7476 {TGSI_OPCODE_TRUNC
, 0, ALU_OP1_TRUNC
, tgsi_op2
},
7477 {TGSI_OPCODE_SHL
, 0, ALU_OP2_LSHL_INT
, tgsi_op2
},
7478 {88, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7479 {TGSI_OPCODE_AND
, 0, ALU_OP2_AND_INT
, tgsi_op2
},
7480 {TGSI_OPCODE_OR
, 0, ALU_OP2_OR_INT
, tgsi_op2
},
7481 {TGSI_OPCODE_MOD
, 0, ALU_OP0_NOP
, tgsi_imod
},
7482 {TGSI_OPCODE_XOR
, 0, ALU_OP2_XOR_INT
, tgsi_op2
},
7483 {TGSI_OPCODE_SAD
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7484 {TGSI_OPCODE_TXF
, 0, FETCH_OP_LD
, tgsi_tex
},
7485 {TGSI_OPCODE_TXQ
, 0, FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
7486 {TGSI_OPCODE_CONT
, 0, CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
7487 {TGSI_OPCODE_EMIT
, 0, CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
7488 {TGSI_OPCODE_ENDPRIM
, 0, CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
7489 {TGSI_OPCODE_BGNLOOP
, 0, ALU_OP0_NOP
, tgsi_bgnloop
},
7490 {TGSI_OPCODE_BGNSUB
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7491 {TGSI_OPCODE_ENDLOOP
, 0, ALU_OP0_NOP
, tgsi_endloop
},
7492 {TGSI_OPCODE_ENDSUB
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7493 {TGSI_OPCODE_TXQ_LZ
, 0, FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
7494 {104, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7495 {105, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7496 {106, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7497 {TGSI_OPCODE_NOP
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7498 {TGSI_OPCODE_FSEQ
, 0, ALU_OP2_SETE_DX10
, tgsi_op2
},
7499 {TGSI_OPCODE_FSGE
, 0, ALU_OP2_SETGE_DX10
, tgsi_op2
},
7500 {TGSI_OPCODE_FSLT
, 0, ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
7501 {TGSI_OPCODE_FSNE
, 0, ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
7502 {112, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7503 {TGSI_OPCODE_CALLNZ
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7504 {114, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7505 {TGSI_OPCODE_BREAKC
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7506 {TGSI_OPCODE_KILL_IF
, 0, ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
7507 {TGSI_OPCODE_END
, 0, ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
7508 {118, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7509 {TGSI_OPCODE_F2I
, 0, ALU_OP1_FLT_TO_INT
, tgsi_f2i
},
7510 {TGSI_OPCODE_IDIV
, 0, ALU_OP0_NOP
, tgsi_idiv
},
7511 {TGSI_OPCODE_IMAX
, 0, ALU_OP2_MAX_INT
, tgsi_op2
},
7512 {TGSI_OPCODE_IMIN
, 0, ALU_OP2_MIN_INT
, tgsi_op2
},
7513 {TGSI_OPCODE_INEG
, 0, ALU_OP2_SUB_INT
, tgsi_ineg
},
7514 {TGSI_OPCODE_ISGE
, 0, ALU_OP2_SETGE_INT
, tgsi_op2
},
7515 {TGSI_OPCODE_ISHR
, 0, ALU_OP2_ASHR_INT
, tgsi_op2
},
7516 {TGSI_OPCODE_ISLT
, 0, ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
7517 {TGSI_OPCODE_F2U
, 0, ALU_OP1_FLT_TO_UINT
, tgsi_f2i
},
7518 {TGSI_OPCODE_U2F
, 0, ALU_OP1_UINT_TO_FLT
, tgsi_op2_trans
},
7519 {TGSI_OPCODE_UADD
, 0, ALU_OP2_ADD_INT
, tgsi_op2
},
7520 {TGSI_OPCODE_UDIV
, 0, ALU_OP0_NOP
, tgsi_udiv
},
7521 {TGSI_OPCODE_UMAD
, 0, ALU_OP0_NOP
, tgsi_umad
},
7522 {TGSI_OPCODE_UMAX
, 0, ALU_OP2_MAX_UINT
, tgsi_op2
},
7523 {TGSI_OPCODE_UMIN
, 0, ALU_OP2_MIN_UINT
, tgsi_op2
},
7524 {TGSI_OPCODE_UMOD
, 0, ALU_OP0_NOP
, tgsi_umod
},
7525 {TGSI_OPCODE_UMUL
, 0, ALU_OP2_MULLO_UINT
, tgsi_op2_trans
},
7526 {TGSI_OPCODE_USEQ
, 0, ALU_OP2_SETE_INT
, tgsi_op2
},
7527 {TGSI_OPCODE_USGE
, 0, ALU_OP2_SETGE_UINT
, tgsi_op2
},
7528 {TGSI_OPCODE_USHR
, 0, ALU_OP2_LSHR_INT
, tgsi_op2
},
7529 {TGSI_OPCODE_USLT
, 0, ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
7530 {TGSI_OPCODE_USNE
, 0, ALU_OP2_SETNE_INT
, tgsi_op2
},
7531 {TGSI_OPCODE_SWITCH
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7532 {TGSI_OPCODE_CASE
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7533 {TGSI_OPCODE_DEFAULT
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7534 {TGSI_OPCODE_ENDSWITCH
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7535 {TGSI_OPCODE_SAMPLE
, 0, 0, tgsi_unsupported
},
7536 {TGSI_OPCODE_SAMPLE_I
, 0, 0, tgsi_unsupported
},
7537 {TGSI_OPCODE_SAMPLE_I_MS
, 0, 0, tgsi_unsupported
},
7538 {TGSI_OPCODE_SAMPLE_B
, 0, 0, tgsi_unsupported
},
7539 {TGSI_OPCODE_SAMPLE_C
, 0, 0, tgsi_unsupported
},
7540 {TGSI_OPCODE_SAMPLE_C_LZ
, 0, 0, tgsi_unsupported
},
7541 {TGSI_OPCODE_SAMPLE_D
, 0, 0, tgsi_unsupported
},
7542 {TGSI_OPCODE_SAMPLE_L
, 0, 0, tgsi_unsupported
},
7543 {TGSI_OPCODE_GATHER4
, 0, 0, tgsi_unsupported
},
7544 {TGSI_OPCODE_SVIEWINFO
, 0, 0, tgsi_unsupported
},
7545 {TGSI_OPCODE_SAMPLE_POS
, 0, 0, tgsi_unsupported
},
7546 {TGSI_OPCODE_SAMPLE_INFO
, 0, 0, tgsi_unsupported
},
7547 {TGSI_OPCODE_UARL
, 0, ALU_OP1_MOVA_INT
, tgsi_eg_arl
},
7548 {TGSI_OPCODE_UCMP
, 0, ALU_OP0_NOP
, tgsi_ucmp
},
7549 {TGSI_OPCODE_IABS
, 0, 0, tgsi_iabs
},
7550 {TGSI_OPCODE_ISSG
, 0, 0, tgsi_issg
},
7551 {TGSI_OPCODE_LOAD
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7552 {TGSI_OPCODE_STORE
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7553 {TGSI_OPCODE_MFENCE
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7554 {TGSI_OPCODE_LFENCE
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7555 {TGSI_OPCODE_SFENCE
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7556 {TGSI_OPCODE_BARRIER
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7557 {TGSI_OPCODE_ATOMUADD
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7558 {TGSI_OPCODE_ATOMXCHG
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7559 {TGSI_OPCODE_ATOMCAS
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7560 {TGSI_OPCODE_ATOMAND
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7561 {TGSI_OPCODE_ATOMOR
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7562 {TGSI_OPCODE_ATOMXOR
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7563 {TGSI_OPCODE_ATOMUMIN
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7564 {TGSI_OPCODE_ATOMUMAX
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7565 {TGSI_OPCODE_ATOMIMIN
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7566 {TGSI_OPCODE_ATOMIMAX
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7567 {TGSI_OPCODE_TEX2
, 0, FETCH_OP_SAMPLE
, tgsi_tex
},
7568 {TGSI_OPCODE_TXB2
, 0, FETCH_OP_SAMPLE_LB
, tgsi_tex
},
7569 {TGSI_OPCODE_TXL2
, 0, FETCH_OP_SAMPLE_L
, tgsi_tex
},
7570 {TGSI_OPCODE_IMUL_HI
, 0, ALU_OP2_MULHI_INT
, tgsi_op2_trans
},
7571 {TGSI_OPCODE_UMUL_HI
, 0, ALU_OP2_MULHI_UINT
, tgsi_op2_trans
},
7572 {TGSI_OPCODE_TG4
, 0, FETCH_OP_GATHER4
, tgsi_tex
},
7573 {TGSI_OPCODE_LODQ
, 0, FETCH_OP_GET_LOD
, tgsi_tex
},
7574 {TGSI_OPCODE_IBFE
, 1, ALU_OP3_BFE_INT
, tgsi_op3
},
7575 {TGSI_OPCODE_UBFE
, 1, ALU_OP3_BFE_UINT
, tgsi_op3
},
7576 {TGSI_OPCODE_BFI
, 0, ALU_OP0_NOP
, tgsi_bfi
},
7577 {TGSI_OPCODE_BREV
, 0, ALU_OP1_BFREV_INT
, tgsi_op2
},
7578 {TGSI_OPCODE_POPC
, 0, ALU_OP1_BCNT_INT
, tgsi_op2
},
7579 {TGSI_OPCODE_LSB
, 0, ALU_OP1_FFBL_INT
, tgsi_op2
},
7580 {TGSI_OPCODE_IMSB
, 0, ALU_OP1_FFBH_INT
, tgsi_msb
},
7581 {TGSI_OPCODE_UMSB
, 0, ALU_OP1_FFBH_UINT
, tgsi_msb
},
7582 {TGSI_OPCODE_INTERP_CENTROID
, 0, ALU_OP0_NOP
, tgsi_interp_egcm
},
7583 {TGSI_OPCODE_INTERP_SAMPLE
, 0, ALU_OP0_NOP
, tgsi_interp_egcm
},
7584 {TGSI_OPCODE_INTERP_OFFSET
, 0, ALU_OP0_NOP
, tgsi_interp_egcm
},
7585 {TGSI_OPCODE_LAST
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7588 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction
[] = {
7589 {TGSI_OPCODE_ARL
, 0, ALU_OP0_NOP
, tgsi_eg_arl
},
7590 {TGSI_OPCODE_MOV
, 0, ALU_OP1_MOV
, tgsi_op2
},
7591 {TGSI_OPCODE_LIT
, 0, ALU_OP0_NOP
, tgsi_lit
},
7592 {TGSI_OPCODE_RCP
, 0, ALU_OP1_RECIP_IEEE
, cayman_emit_float_instr
},
7593 {TGSI_OPCODE_RSQ
, 0, ALU_OP1_RECIPSQRT_IEEE
, cayman_emit_float_instr
},
7594 {TGSI_OPCODE_EXP
, 0, ALU_OP0_NOP
, tgsi_exp
},
7595 {TGSI_OPCODE_LOG
, 0, ALU_OP0_NOP
, tgsi_log
},
7596 {TGSI_OPCODE_MUL
, 0, ALU_OP2_MUL
, tgsi_op2
},
7597 {TGSI_OPCODE_ADD
, 0, ALU_OP2_ADD
, tgsi_op2
},
7598 {TGSI_OPCODE_DP3
, 0, ALU_OP2_DOT4
, tgsi_dp
},
7599 {TGSI_OPCODE_DP4
, 0, ALU_OP2_DOT4
, tgsi_dp
},
7600 {TGSI_OPCODE_DST
, 0, ALU_OP0_NOP
, tgsi_opdst
},
7601 {TGSI_OPCODE_MIN
, 0, ALU_OP2_MIN
, tgsi_op2
},
7602 {TGSI_OPCODE_MAX
, 0, ALU_OP2_MAX
, tgsi_op2
},
7603 {TGSI_OPCODE_SLT
, 0, ALU_OP2_SETGT
, tgsi_op2_swap
},
7604 {TGSI_OPCODE_SGE
, 0, ALU_OP2_SETGE
, tgsi_op2
},
7605 {TGSI_OPCODE_MAD
, 1, ALU_OP3_MULADD
, tgsi_op3
},
7606 {TGSI_OPCODE_SUB
, 0, ALU_OP2_ADD
, tgsi_op2
},
7607 {TGSI_OPCODE_LRP
, 0, ALU_OP0_NOP
, tgsi_lrp
},
7608 {TGSI_OPCODE_CND
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7609 {TGSI_OPCODE_SQRT
, 0, ALU_OP1_SQRT_IEEE
, cayman_emit_float_instr
},
7610 {TGSI_OPCODE_DP2A
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7611 {22, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7612 {23, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7613 {TGSI_OPCODE_FRC
, 0, ALU_OP1_FRACT
, tgsi_op2
},
7614 {TGSI_OPCODE_CLAMP
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7615 {TGSI_OPCODE_FLR
, 0, ALU_OP1_FLOOR
, tgsi_op2
},
7616 {TGSI_OPCODE_ROUND
, 0, ALU_OP1_RNDNE
, tgsi_op2
},
7617 {TGSI_OPCODE_EX2
, 0, ALU_OP1_EXP_IEEE
, cayman_emit_float_instr
},
7618 {TGSI_OPCODE_LG2
, 0, ALU_OP1_LOG_IEEE
, cayman_emit_float_instr
},
7619 {TGSI_OPCODE_POW
, 0, ALU_OP0_NOP
, cayman_pow
},
7620 {TGSI_OPCODE_XPD
, 0, ALU_OP0_NOP
, tgsi_xpd
},
7621 {32, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7622 {TGSI_OPCODE_ABS
, 0, ALU_OP1_MOV
, tgsi_op2
},
7623 {34, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7624 {TGSI_OPCODE_DPH
, 0, ALU_OP2_DOT4
, tgsi_dp
},
7625 {TGSI_OPCODE_COS
, 0, ALU_OP1_COS
, cayman_trig
},
7626 {TGSI_OPCODE_DDX
, 0, FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
7627 {TGSI_OPCODE_DDY
, 0, FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
7628 {TGSI_OPCODE_KILL
, 0, ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
7629 {TGSI_OPCODE_PK2H
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7630 {TGSI_OPCODE_PK2US
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7631 {TGSI_OPCODE_PK4B
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7632 {TGSI_OPCODE_PK4UB
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7633 {TGSI_OPCODE_RFL
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7634 {TGSI_OPCODE_SEQ
, 0, ALU_OP2_SETE
, tgsi_op2
},
7635 {TGSI_OPCODE_SFL
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7636 {TGSI_OPCODE_SGT
, 0, ALU_OP2_SETGT
, tgsi_op2
},
7637 {TGSI_OPCODE_SIN
, 0, ALU_OP1_SIN
, cayman_trig
},
7638 {TGSI_OPCODE_SLE
, 0, ALU_OP2_SETGE
, tgsi_op2_swap
},
7639 {TGSI_OPCODE_SNE
, 0, ALU_OP2_SETNE
, tgsi_op2
},
7640 {TGSI_OPCODE_STR
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7641 {TGSI_OPCODE_TEX
, 0, FETCH_OP_SAMPLE
, tgsi_tex
},
7642 {TGSI_OPCODE_TXD
, 0, FETCH_OP_SAMPLE_G
, tgsi_tex
},
7643 {TGSI_OPCODE_TXP
, 0, FETCH_OP_SAMPLE
, tgsi_tex
},
7644 {TGSI_OPCODE_UP2H
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7645 {TGSI_OPCODE_UP2US
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7646 {TGSI_OPCODE_UP4B
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7647 {TGSI_OPCODE_UP4UB
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7648 {59, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7649 {60, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7650 {TGSI_OPCODE_ARR
, 0, ALU_OP0_NOP
, tgsi_eg_arl
},
7651 {TGSI_OPCODE_BRA
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7652 {TGSI_OPCODE_CAL
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7653 {TGSI_OPCODE_RET
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7654 {TGSI_OPCODE_SSG
, 0, ALU_OP0_NOP
, tgsi_ssg
},
7655 {TGSI_OPCODE_CMP
, 0, ALU_OP0_NOP
, tgsi_cmp
},
7656 {TGSI_OPCODE_SCS
, 0, ALU_OP0_NOP
, tgsi_scs
},
7657 {TGSI_OPCODE_TXB
, 0, FETCH_OP_SAMPLE_LB
, tgsi_tex
},
7658 {69, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7659 {TGSI_OPCODE_DIV
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7660 {TGSI_OPCODE_DP2
, 0, ALU_OP2_DOT4
, tgsi_dp
},
7661 {TGSI_OPCODE_TXL
, 0, FETCH_OP_SAMPLE_L
, tgsi_tex
},
7662 {TGSI_OPCODE_BRK
, 0, CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
7663 {TGSI_OPCODE_IF
, 0, ALU_OP0_NOP
, tgsi_if
},
7664 {TGSI_OPCODE_UIF
, 0, ALU_OP0_NOP
, tgsi_uif
},
7665 {76, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7666 {TGSI_OPCODE_ELSE
, 0, ALU_OP0_NOP
, tgsi_else
},
7667 {TGSI_OPCODE_ENDIF
, 0, ALU_OP0_NOP
, tgsi_endif
},
7668 {TGSI_OPCODE_DDX_FINE
, 0, FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
7669 {TGSI_OPCODE_DDY_FINE
, 0, FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
7670 {TGSI_OPCODE_PUSHA
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7671 {TGSI_OPCODE_POPA
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7672 {TGSI_OPCODE_CEIL
, 0, ALU_OP1_CEIL
, tgsi_op2
},
7673 {TGSI_OPCODE_I2F
, 0, ALU_OP1_INT_TO_FLT
, tgsi_op2
},
7674 {TGSI_OPCODE_NOT
, 0, ALU_OP1_NOT_INT
, tgsi_op2
},
7675 {TGSI_OPCODE_TRUNC
, 0, ALU_OP1_TRUNC
, tgsi_op2
},
7676 {TGSI_OPCODE_SHL
, 0, ALU_OP2_LSHL_INT
, tgsi_op2
},
7677 {88, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7678 {TGSI_OPCODE_AND
, 0, ALU_OP2_AND_INT
, tgsi_op2
},
7679 {TGSI_OPCODE_OR
, 0, ALU_OP2_OR_INT
, tgsi_op2
},
7680 {TGSI_OPCODE_MOD
, 0, ALU_OP0_NOP
, tgsi_imod
},
7681 {TGSI_OPCODE_XOR
, 0, ALU_OP2_XOR_INT
, tgsi_op2
},
7682 {TGSI_OPCODE_SAD
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7683 {TGSI_OPCODE_TXF
, 0, FETCH_OP_LD
, tgsi_tex
},
7684 {TGSI_OPCODE_TXQ
, 0, FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
7685 {TGSI_OPCODE_CONT
, 0, CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
7686 {TGSI_OPCODE_EMIT
, 0, CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
7687 {TGSI_OPCODE_ENDPRIM
, 0, CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
7688 {TGSI_OPCODE_BGNLOOP
, 0, ALU_OP0_NOP
, tgsi_bgnloop
},
7689 {TGSI_OPCODE_BGNSUB
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7690 {TGSI_OPCODE_ENDLOOP
, 0, ALU_OP0_NOP
, tgsi_endloop
},
7691 {TGSI_OPCODE_ENDSUB
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7692 {TGSI_OPCODE_TXQ_LZ
, 0, FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
7693 {104, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7694 {105, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7695 {106, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7696 {TGSI_OPCODE_NOP
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7697 {TGSI_OPCODE_FSEQ
, 0, ALU_OP2_SETE_DX10
, tgsi_op2
},
7698 {TGSI_OPCODE_FSGE
, 0, ALU_OP2_SETGE_DX10
, tgsi_op2
},
7699 {TGSI_OPCODE_FSLT
, 0, ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
7700 {TGSI_OPCODE_FSNE
, 0, ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
7701 {112, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7702 {TGSI_OPCODE_CALLNZ
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7703 {114, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7704 {TGSI_OPCODE_BREAKC
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7705 {TGSI_OPCODE_KILL_IF
, 0, ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
7706 {TGSI_OPCODE_END
, 0, ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
7707 {118, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7708 {TGSI_OPCODE_F2I
, 0, ALU_OP1_FLT_TO_INT
, tgsi_op2
},
7709 {TGSI_OPCODE_IDIV
, 0, ALU_OP0_NOP
, tgsi_idiv
},
7710 {TGSI_OPCODE_IMAX
, 0, ALU_OP2_MAX_INT
, tgsi_op2
},
7711 {TGSI_OPCODE_IMIN
, 0, ALU_OP2_MIN_INT
, tgsi_op2
},
7712 {TGSI_OPCODE_INEG
, 0, ALU_OP2_SUB_INT
, tgsi_ineg
},
7713 {TGSI_OPCODE_ISGE
, 0, ALU_OP2_SETGE_INT
, tgsi_op2
},
7714 {TGSI_OPCODE_ISHR
, 0, ALU_OP2_ASHR_INT
, tgsi_op2
},
7715 {TGSI_OPCODE_ISLT
, 0, ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
7716 {TGSI_OPCODE_F2U
, 0, ALU_OP1_FLT_TO_UINT
, tgsi_op2
},
7717 {TGSI_OPCODE_U2F
, 0, ALU_OP1_UINT_TO_FLT
, tgsi_op2
},
7718 {TGSI_OPCODE_UADD
, 0, ALU_OP2_ADD_INT
, tgsi_op2
},
7719 {TGSI_OPCODE_UDIV
, 0, ALU_OP0_NOP
, tgsi_udiv
},
7720 {TGSI_OPCODE_UMAD
, 0, ALU_OP0_NOP
, tgsi_umad
},
7721 {TGSI_OPCODE_UMAX
, 0, ALU_OP2_MAX_UINT
, tgsi_op2
},
7722 {TGSI_OPCODE_UMIN
, 0, ALU_OP2_MIN_UINT
, tgsi_op2
},
7723 {TGSI_OPCODE_UMOD
, 0, ALU_OP0_NOP
, tgsi_umod
},
7724 {TGSI_OPCODE_UMUL
, 0, ALU_OP2_MULLO_INT
, cayman_mul_int_instr
},
7725 {TGSI_OPCODE_USEQ
, 0, ALU_OP2_SETE_INT
, tgsi_op2
},
7726 {TGSI_OPCODE_USGE
, 0, ALU_OP2_SETGE_UINT
, tgsi_op2
},
7727 {TGSI_OPCODE_USHR
, 0, ALU_OP2_LSHR_INT
, tgsi_op2
},
7728 {TGSI_OPCODE_USLT
, 0, ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
7729 {TGSI_OPCODE_USNE
, 0, ALU_OP2_SETNE_INT
, tgsi_op2
},
7730 {TGSI_OPCODE_SWITCH
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7731 {TGSI_OPCODE_CASE
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7732 {TGSI_OPCODE_DEFAULT
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7733 {TGSI_OPCODE_ENDSWITCH
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7734 {TGSI_OPCODE_SAMPLE
, 0, 0, tgsi_unsupported
},
7735 {TGSI_OPCODE_SAMPLE_I
, 0, 0, tgsi_unsupported
},
7736 {TGSI_OPCODE_SAMPLE_I_MS
, 0, 0, tgsi_unsupported
},
7737 {TGSI_OPCODE_SAMPLE_B
, 0, 0, tgsi_unsupported
},
7738 {TGSI_OPCODE_SAMPLE_C
, 0, 0, tgsi_unsupported
},
7739 {TGSI_OPCODE_SAMPLE_C_LZ
, 0, 0, tgsi_unsupported
},
7740 {TGSI_OPCODE_SAMPLE_D
, 0, 0, tgsi_unsupported
},
7741 {TGSI_OPCODE_SAMPLE_L
, 0, 0, tgsi_unsupported
},
7742 {TGSI_OPCODE_GATHER4
, 0, 0, tgsi_unsupported
},
7743 {TGSI_OPCODE_SVIEWINFO
, 0, 0, tgsi_unsupported
},
7744 {TGSI_OPCODE_SAMPLE_POS
, 0, 0, tgsi_unsupported
},
7745 {TGSI_OPCODE_SAMPLE_INFO
, 0, 0, tgsi_unsupported
},
7746 {TGSI_OPCODE_UARL
, 0, ALU_OP1_MOVA_INT
, tgsi_eg_arl
},
7747 {TGSI_OPCODE_UCMP
, 0, ALU_OP0_NOP
, tgsi_ucmp
},
7748 {TGSI_OPCODE_IABS
, 0, 0, tgsi_iabs
},
7749 {TGSI_OPCODE_ISSG
, 0, 0, tgsi_issg
},
7750 {TGSI_OPCODE_LOAD
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7751 {TGSI_OPCODE_STORE
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7752 {TGSI_OPCODE_MFENCE
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7753 {TGSI_OPCODE_LFENCE
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7754 {TGSI_OPCODE_SFENCE
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7755 {TGSI_OPCODE_BARRIER
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7756 {TGSI_OPCODE_ATOMUADD
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7757 {TGSI_OPCODE_ATOMXCHG
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7758 {TGSI_OPCODE_ATOMCAS
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7759 {TGSI_OPCODE_ATOMAND
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7760 {TGSI_OPCODE_ATOMOR
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7761 {TGSI_OPCODE_ATOMXOR
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7762 {TGSI_OPCODE_ATOMUMIN
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7763 {TGSI_OPCODE_ATOMUMAX
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7764 {TGSI_OPCODE_ATOMIMIN
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7765 {TGSI_OPCODE_ATOMIMAX
, 0, ALU_OP0_NOP
, tgsi_unsupported
},
7766 {TGSI_OPCODE_TEX2
, 0, FETCH_OP_SAMPLE
, tgsi_tex
},
7767 {TGSI_OPCODE_TXB2
, 0, FETCH_OP_SAMPLE_LB
, tgsi_tex
},
7768 {TGSI_OPCODE_TXL2
, 0, FETCH_OP_SAMPLE_L
, tgsi_tex
},
7769 {TGSI_OPCODE_IMUL_HI
, 0, ALU_OP2_MULHI_INT
, cayman_mul_int_instr
},
7770 {TGSI_OPCODE_UMUL_HI
, 0, ALU_OP2_MULHI_UINT
, cayman_mul_int_instr
},
7771 {TGSI_OPCODE_TG4
, 0, FETCH_OP_GATHER4
, tgsi_tex
},
7772 {TGSI_OPCODE_LODQ
, 0, FETCH_OP_GET_LOD
, tgsi_tex
},
7773 {TGSI_OPCODE_IBFE
, 1, ALU_OP3_BFE_INT
, tgsi_op3
},
7774 {TGSI_OPCODE_UBFE
, 1, ALU_OP3_BFE_UINT
, tgsi_op3
},
7775 {TGSI_OPCODE_BFI
, 0, ALU_OP0_NOP
, tgsi_bfi
},
7776 {TGSI_OPCODE_BREV
, 0, ALU_OP1_BFREV_INT
, tgsi_op2
},
7777 {TGSI_OPCODE_POPC
, 0, ALU_OP1_BCNT_INT
, tgsi_op2
},
7778 {TGSI_OPCODE_LSB
, 0, ALU_OP1_FFBL_INT
, tgsi_op2
},
7779 {TGSI_OPCODE_IMSB
, 0, ALU_OP1_FFBH_INT
, tgsi_msb
},
7780 {TGSI_OPCODE_UMSB
, 0, ALU_OP1_FFBH_UINT
, tgsi_msb
},
7781 {TGSI_OPCODE_INTERP_CENTROID
, 0, ALU_OP0_NOP
, tgsi_interp_egcm
},
7782 {TGSI_OPCODE_INTERP_SAMPLE
, 0, ALU_OP0_NOP
, tgsi_interp_egcm
},
7783 {TGSI_OPCODE_INTERP_OFFSET
, 0, ALU_OP0_NOP
, tgsi_interp_egcm
},
7784 {TGSI_OPCODE_LAST
, 0, ALU_OP0_NOP
, tgsi_unsupported
},