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r600g: delete old path
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36
37 struct r600_shader_tgsi_instruction;
38
39 struct r600_shader_ctx {
40 struct tgsi_shader_info info;
41 struct tgsi_parse_context parse;
42 const struct tgsi_token *tokens;
43 unsigned type;
44 unsigned file_offset[TGSI_FILE_COUNT];
45 unsigned temp_reg;
46 struct r600_shader_tgsi_instruction *inst_info;
47 struct r600_bc *bc;
48 struct r600_shader *shader;
49 u32 value[4];
50 u32 *literals;
51 u32 nliterals;
52 u32 max_driver_temp_used;
53 };
54
55 struct r600_shader_tgsi_instruction {
56 unsigned tgsi_opcode;
57 unsigned is_op3;
58 unsigned r600_opcode;
59 int (*process)(struct r600_shader_ctx *ctx);
60 };
61
62 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
63 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
64
65 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
66 {
67 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
68 int j;
69
70 if (i->Instruction.NumDstRegs > 1) {
71 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
72 return -EINVAL;
73 }
74 if (i->Instruction.Predicate) {
75 R600_ERR("predicate unsupported\n");
76 return -EINVAL;
77 }
78 #if 0
79 if (i->Instruction.Label) {
80 R600_ERR("label unsupported\n");
81 return -EINVAL;
82 }
83 #endif
84 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
85 if (i->Src[j].Register.Dimension ||
86 i->Src[j].Register.Absolute) {
87 R600_ERR("unsupported src %d (dimension %d|absolute %d)\n", j,
88 i->Src[j].Register.Dimension,
89 i->Src[j].Register.Absolute);
90 return -EINVAL;
91 }
92 }
93 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
94 if (i->Dst[j].Register.Dimension) {
95 R600_ERR("unsupported dst (dimension)\n");
96 return -EINVAL;
97 }
98 }
99 return 0;
100 }
101
102 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int gpr)
103 {
104 int i, r;
105 struct r600_bc_alu alu;
106
107 for (i = 0; i < 8; i++) {
108 memset(&alu, 0, sizeof(struct r600_bc_alu));
109
110 if (i < 4)
111 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
112 else
113 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
114
115 if ((i > 1) && (i < 6)) {
116 alu.dst.sel = ctx->shader->input[gpr].gpr;
117 alu.dst.write = 1;
118 }
119
120 alu.dst.chan = i % 4;
121 alu.src[0].chan = (1 - (i % 2));
122 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + gpr;
123
124 alu.bank_swizzle_force = SQ_ALU_VEC_210;
125 if ((i % 4) == 3)
126 alu.last = 1;
127 r = r600_bc_add_alu(ctx->bc, &alu);
128 if (r)
129 return r;
130 }
131 return 0;
132 }
133
134
135 static int tgsi_declaration(struct r600_shader_ctx *ctx)
136 {
137 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
138 struct r600_bc_vtx vtx;
139 unsigned i;
140 int r;
141
142 switch (d->Declaration.File) {
143 case TGSI_FILE_INPUT:
144 i = ctx->shader->ninput++;
145 ctx->shader->input[i].name = d->Semantic.Name;
146 ctx->shader->input[i].sid = d->Semantic.Index;
147 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
148 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
149 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
150 /* turn input into fetch */
151 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
152 vtx.inst = 0;
153 vtx.fetch_type = 0;
154 vtx.buffer_id = i;
155 /* register containing the index into the buffer */
156 vtx.src_gpr = 0;
157 vtx.src_sel_x = 0;
158 vtx.mega_fetch_count = 0x1F;
159 vtx.dst_gpr = ctx->shader->input[i].gpr;
160 vtx.dst_sel_x = 0;
161 vtx.dst_sel_y = 1;
162 vtx.dst_sel_z = 2;
163 vtx.dst_sel_w = 3;
164 r = r600_bc_add_vtx(ctx->bc, &vtx);
165 if (r)
166 return r;
167 }
168 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == 2) {
169 /* turn input into interpolate on EG */
170 evergreen_interp_alu(ctx, i);
171 }
172 break;
173 case TGSI_FILE_OUTPUT:
174 i = ctx->shader->noutput++;
175 ctx->shader->output[i].name = d->Semantic.Name;
176 ctx->shader->output[i].sid = d->Semantic.Index;
177 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
178 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
179 break;
180 case TGSI_FILE_CONSTANT:
181 case TGSI_FILE_TEMPORARY:
182 case TGSI_FILE_SAMPLER:
183 case TGSI_FILE_ADDRESS:
184 break;
185 default:
186 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
187 return -EINVAL;
188 }
189 return 0;
190 }
191
192 static int r600_get_temp(struct r600_shader_ctx *ctx)
193 {
194 return ctx->temp_reg + ctx->max_driver_temp_used++;
195 }
196
197 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
198 {
199 struct tgsi_full_immediate *immediate;
200 struct r600_shader_ctx ctx;
201 struct r600_bc_output output[32];
202 unsigned output_done, noutput;
203 unsigned opcode;
204 int i, r = 0, pos0;
205
206 ctx.bc = &shader->bc;
207 ctx.shader = shader;
208 r = r600_bc_init(ctx.bc, shader->family);
209 if (r)
210 return r;
211 ctx.bc->use_mem_constant = shader->use_mem_constant;
212 ctx.tokens = tokens;
213 tgsi_scan_shader(tokens, &ctx.info);
214 tgsi_parse_init(&ctx.parse, tokens);
215 ctx.type = ctx.parse.FullHeader.Processor.Processor;
216 shader->processor_type = ctx.type;
217
218 /* register allocations */
219 /* Values [0,127] correspond to GPR[0..127].
220 * Values [128,159] correspond to constant buffer bank 0
221 * Values [160,191] correspond to constant buffer bank 1
222 * Values [256,511] correspond to cfile constants c[0..255].
223 * Other special values are shown in the list below.
224 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
225 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
226 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
227 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
228 * 248 SQ_ALU_SRC_0: special constant 0.0.
229 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
230 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
231 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
232 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
233 * 253 SQ_ALU_SRC_LITERAL: literal constant.
234 * 254 SQ_ALU_SRC_PV: previous vector result.
235 * 255 SQ_ALU_SRC_PS: previous scalar result.
236 */
237 for (i = 0; i < TGSI_FILE_COUNT; i++) {
238 ctx.file_offset[i] = 0;
239 }
240 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
241 ctx.file_offset[TGSI_FILE_INPUT] = 1;
242 }
243 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
244 ctx.info.file_count[TGSI_FILE_INPUT];
245 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
246 ctx.info.file_count[TGSI_FILE_OUTPUT];
247 if (ctx.shader->use_mem_constant)
248 ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
249 else
250 ctx.file_offset[TGSI_FILE_CONSTANT] = 256;
251
252 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
253 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
254 ctx.info.file_count[TGSI_FILE_TEMPORARY];
255
256 ctx.nliterals = 0;
257 ctx.literals = NULL;
258
259 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
260 tgsi_parse_token(&ctx.parse);
261 switch (ctx.parse.FullToken.Token.Type) {
262 case TGSI_TOKEN_TYPE_IMMEDIATE:
263 immediate = &ctx.parse.FullToken.FullImmediate;
264 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
265 if(ctx.literals == NULL) {
266 r = -ENOMEM;
267 goto out_err;
268 }
269 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
270 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
271 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
272 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
273 ctx.nliterals++;
274 break;
275 case TGSI_TOKEN_TYPE_DECLARATION:
276 r = tgsi_declaration(&ctx);
277 if (r)
278 goto out_err;
279 break;
280 case TGSI_TOKEN_TYPE_INSTRUCTION:
281 r = tgsi_is_supported(&ctx);
282 if (r)
283 goto out_err;
284 ctx.max_driver_temp_used = 0;
285 /* reserve first tmp for everyone */
286 r600_get_temp(&ctx);
287 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
288 if (ctx.bc->chiprev == 2)
289 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
290 else
291 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
292 r = ctx.inst_info->process(&ctx);
293 if (r)
294 goto out_err;
295 r = r600_bc_add_literal(ctx.bc, ctx.value);
296 if (r)
297 goto out_err;
298 break;
299 default:
300 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
301 r = -EINVAL;
302 goto out_err;
303 }
304 }
305 /* export output */
306 noutput = shader->noutput;
307 for (i = 0, pos0 = 0; i < noutput; i++) {
308 memset(&output[i], 0, sizeof(struct r600_bc_output));
309 output[i].gpr = shader->output[i].gpr;
310 output[i].elem_size = 3;
311 output[i].swizzle_x = 0;
312 output[i].swizzle_y = 1;
313 output[i].swizzle_z = 2;
314 output[i].swizzle_w = 3;
315 output[i].barrier = 1;
316 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
317 output[i].array_base = i - pos0;
318 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
319 switch (ctx.type) {
320 case TGSI_PROCESSOR_VERTEX:
321 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
322 output[i].array_base = 60;
323 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
324 /* position doesn't count in array_base */
325 pos0++;
326 }
327 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
328 output[i].array_base = 61;
329 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
330 /* position doesn't count in array_base */
331 pos0++;
332 }
333 break;
334 case TGSI_PROCESSOR_FRAGMENT:
335 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
336 output[i].array_base = shader->output[i].sid;
337 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
338 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
339 output[i].array_base = 61;
340 output[i].swizzle_x = 2;
341 output[i].swizzle_y = output[i].swizzle_z = output[i].swizzle_w = 7;
342 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
343 } else {
344 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
345 r = -EINVAL;
346 goto out_err;
347 }
348 break;
349 default:
350 R600_ERR("unsupported processor type %d\n", ctx.type);
351 r = -EINVAL;
352 goto out_err;
353 }
354 }
355 /* add fake param output for vertex shader if no param is exported */
356 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
357 for (i = 0, pos0 = 0; i < noutput; i++) {
358 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
359 pos0 = 1;
360 break;
361 }
362 }
363 if (!pos0) {
364 memset(&output[i], 0, sizeof(struct r600_bc_output));
365 output[i].gpr = 0;
366 output[i].elem_size = 3;
367 output[i].swizzle_x = 0;
368 output[i].swizzle_y = 1;
369 output[i].swizzle_z = 2;
370 output[i].swizzle_w = 3;
371 output[i].barrier = 1;
372 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
373 output[i].array_base = 0;
374 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
375 noutput++;
376 }
377 }
378 /* add fake pixel export */
379 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
380 memset(&output[0], 0, sizeof(struct r600_bc_output));
381 output[0].gpr = 0;
382 output[0].elem_size = 3;
383 output[0].swizzle_x = 7;
384 output[0].swizzle_y = 7;
385 output[0].swizzle_z = 7;
386 output[0].swizzle_w = 7;
387 output[0].barrier = 1;
388 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
389 output[0].array_base = 0;
390 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
391 noutput++;
392 }
393 /* set export done on last export of each type */
394 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
395 if (i == (noutput - 1)) {
396 output[i].end_of_program = 1;
397 }
398 if (!(output_done & (1 << output[i].type))) {
399 output_done |= (1 << output[i].type);
400 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
401 }
402 }
403 /* add output to bytecode */
404 for (i = 0; i < noutput; i++) {
405 r = r600_bc_add_output(ctx.bc, &output[i]);
406 if (r)
407 goto out_err;
408 }
409 free(ctx.literals);
410 tgsi_parse_free(&ctx.parse);
411 return 0;
412 out_err:
413 free(ctx.literals);
414 tgsi_parse_free(&ctx.parse);
415 return r;
416 }
417
418 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
419 {
420 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
421 return -EINVAL;
422 }
423
424 static int tgsi_end(struct r600_shader_ctx *ctx)
425 {
426 return 0;
427 }
428
429 static int tgsi_src(struct r600_shader_ctx *ctx,
430 const struct tgsi_full_src_register *tgsi_src,
431 struct r600_bc_alu_src *r600_src)
432 {
433 int index;
434 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
435 r600_src->sel = tgsi_src->Register.Index;
436 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
437 r600_src->sel = 0;
438 index = tgsi_src->Register.Index;
439 ctx->value[0] = ctx->literals[index * 4 + 0];
440 ctx->value[1] = ctx->literals[index * 4 + 1];
441 ctx->value[2] = ctx->literals[index * 4 + 2];
442 ctx->value[3] = ctx->literals[index * 4 + 3];
443 }
444 if (tgsi_src->Register.Indirect)
445 r600_src->rel = V_SQ_REL_RELATIVE;
446 r600_src->neg = tgsi_src->Register.Negate;
447 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
448 return 0;
449 }
450
451 static int tgsi_dst(struct r600_shader_ctx *ctx,
452 const struct tgsi_full_dst_register *tgsi_dst,
453 unsigned swizzle,
454 struct r600_bc_alu_dst *r600_dst)
455 {
456 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
457
458 r600_dst->sel = tgsi_dst->Register.Index;
459 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
460 r600_dst->chan = swizzle;
461 r600_dst->write = 1;
462 if (tgsi_dst->Register.Indirect)
463 r600_dst->rel = V_SQ_REL_RELATIVE;
464 if (inst->Instruction.Saturate) {
465 r600_dst->clamp = 1;
466 }
467 return 0;
468 }
469
470 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
471 {
472 switch (swizzle) {
473 case 0:
474 return tgsi_src->Register.SwizzleX;
475 case 1:
476 return tgsi_src->Register.SwizzleY;
477 case 2:
478 return tgsi_src->Register.SwizzleZ;
479 case 3:
480 return tgsi_src->Register.SwizzleW;
481 default:
482 return 0;
483 }
484 }
485
486 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
487 {
488 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
489 struct r600_bc_alu alu;
490 int i, j, k, nconst, r;
491
492 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
493 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
494 nconst++;
495 }
496 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
497 if (r) {
498 return r;
499 }
500 }
501 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
502 if (inst->Src[j].Register.File == TGSI_FILE_CONSTANT && j > 0) {
503 int treg = r600_get_temp(ctx);
504 for (k = 0; k < 4; k++) {
505 memset(&alu, 0, sizeof(struct r600_bc_alu));
506 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
507 alu.src[0].sel = r600_src[j].sel;
508 alu.src[0].chan = k;
509 alu.dst.sel = treg;
510 alu.dst.chan = k;
511 alu.dst.write = 1;
512 if (k == 3)
513 alu.last = 1;
514 r = r600_bc_add_alu(ctx->bc, &alu);
515 if (r)
516 return r;
517 }
518 r600_src[j].sel = treg;
519 j--;
520 }
521 }
522 return 0;
523 }
524
525 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
526 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
527 {
528 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
529 struct r600_bc_alu alu;
530 int i, j, k, nliteral, r;
531
532 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
533 if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
534 nliteral++;
535 }
536 }
537 for (i = 0, j = 0; i < inst->Instruction.NumSrcRegs; i++) {
538 if (inst->Src[j].Register.File == TGSI_FILE_IMMEDIATE) {
539 int treg = r600_get_temp(ctx);
540 for (k = 0; k < 4; k++) {
541 memset(&alu, 0, sizeof(struct r600_bc_alu));
542 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
543 alu.src[0].sel = r600_src[j].sel;
544 alu.src[0].chan = k;
545 alu.dst.sel = treg;
546 alu.dst.chan = k;
547 alu.dst.write = 1;
548 if (k == 3)
549 alu.last = 1;
550 r = r600_bc_add_alu(ctx->bc, &alu);
551 if (r)
552 return r;
553 }
554 r = r600_bc_add_literal(ctx->bc, ctx->value);
555 if (r)
556 return r;
557 r600_src[j].sel = treg;
558 j++;
559 }
560 }
561 return 0;
562 }
563
564 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
565 {
566 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
567 struct r600_bc_alu_src r600_src[3];
568 struct r600_bc_alu alu;
569 int i, j, r;
570 int lasti = 0;
571
572 for (i = 0; i < 4; i++) {
573 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
574 lasti = i;
575 }
576 }
577
578 r = tgsi_split_constant(ctx, r600_src);
579 if (r)
580 return r;
581 for (i = 0; i < lasti + 1; i++) {
582 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
583 continue;
584
585 memset(&alu, 0, sizeof(struct r600_bc_alu));
586 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
587 if (r)
588 return r;
589
590 alu.inst = ctx->inst_info->r600_opcode;
591 if (!swap) {
592 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
593 alu.src[j] = r600_src[j];
594 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
595 }
596 } else {
597 alu.src[0] = r600_src[1];
598 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
599
600 alu.src[1] = r600_src[0];
601 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
602 }
603 /* handle some special cases */
604 switch (ctx->inst_info->tgsi_opcode) {
605 case TGSI_OPCODE_SUB:
606 alu.src[1].neg = 1;
607 break;
608 case TGSI_OPCODE_ABS:
609 alu.src[0].abs = 1;
610 break;
611 default:
612 break;
613 }
614 if (i == lasti) {
615 alu.last = 1;
616 }
617 r = r600_bc_add_alu(ctx->bc, &alu);
618 if (r)
619 return r;
620 }
621 return 0;
622 }
623
624 static int tgsi_op2(struct r600_shader_ctx *ctx)
625 {
626 return tgsi_op2_s(ctx, 0);
627 }
628
629 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
630 {
631 return tgsi_op2_s(ctx, 1);
632 }
633
634 /*
635 * r600 - trunc to -PI..PI range
636 * r700 - normalize by dividing by 2PI
637 * see fdo bug 27901
638 */
639 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
640 struct r600_bc_alu_src r600_src[3])
641 {
642 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
643 int r;
644 uint32_t lit_vals[4];
645 struct r600_bc_alu alu;
646
647 memset(lit_vals, 0, 4*4);
648 r = tgsi_split_constant(ctx, r600_src);
649 if (r)
650 return r;
651
652 r = tgsi_split_literal_constant(ctx, r600_src);
653 if (r)
654 return r;
655
656 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
657 lit_vals[1] = fui(0.5f);
658
659 memset(&alu, 0, sizeof(struct r600_bc_alu));
660 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
661 alu.is_op3 = 1;
662
663 alu.dst.chan = 0;
664 alu.dst.sel = ctx->temp_reg;
665 alu.dst.write = 1;
666
667 alu.src[0] = r600_src[0];
668 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
669
670 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
671 alu.src[1].chan = 0;
672 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
673 alu.src[2].chan = 1;
674 alu.last = 1;
675 r = r600_bc_add_alu(ctx->bc, &alu);
676 if (r)
677 return r;
678 r = r600_bc_add_literal(ctx->bc, lit_vals);
679 if (r)
680 return r;
681
682 memset(&alu, 0, sizeof(struct r600_bc_alu));
683 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
684
685 alu.dst.chan = 0;
686 alu.dst.sel = ctx->temp_reg;
687 alu.dst.write = 1;
688
689 alu.src[0].sel = ctx->temp_reg;
690 alu.src[0].chan = 0;
691 alu.last = 1;
692 r = r600_bc_add_alu(ctx->bc, &alu);
693 if (r)
694 return r;
695
696 if (ctx->bc->chiprev == 0) {
697 lit_vals[0] = fui(3.1415926535897f * 2.0f);
698 lit_vals[1] = fui(-3.1415926535897f);
699 } else {
700 lit_vals[0] = fui(1.0f);
701 lit_vals[1] = fui(-0.5f);
702 }
703
704 memset(&alu, 0, sizeof(struct r600_bc_alu));
705 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
706 alu.is_op3 = 1;
707
708 alu.dst.chan = 0;
709 alu.dst.sel = ctx->temp_reg;
710 alu.dst.write = 1;
711
712 alu.src[0].sel = ctx->temp_reg;
713 alu.src[0].chan = 0;
714
715 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
716 alu.src[1].chan = 0;
717 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
718 alu.src[2].chan = 1;
719 alu.last = 1;
720 r = r600_bc_add_alu(ctx->bc, &alu);
721 if (r)
722 return r;
723 r = r600_bc_add_literal(ctx->bc, lit_vals);
724 if (r)
725 return r;
726 return 0;
727 }
728
729 static int tgsi_trig(struct r600_shader_ctx *ctx)
730 {
731 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
732 struct r600_bc_alu_src r600_src[3];
733 struct r600_bc_alu alu;
734 int i, r;
735 int lasti = 0;
736
737 r = tgsi_setup_trig(ctx, r600_src);
738 if (r)
739 return r;
740
741 memset(&alu, 0, sizeof(struct r600_bc_alu));
742 alu.inst = ctx->inst_info->r600_opcode;
743 alu.dst.chan = 0;
744 alu.dst.sel = ctx->temp_reg;
745 alu.dst.write = 1;
746
747 alu.src[0].sel = ctx->temp_reg;
748 alu.src[0].chan = 0;
749 alu.last = 1;
750 r = r600_bc_add_alu(ctx->bc, &alu);
751 if (r)
752 return r;
753
754 /* replicate result */
755 for (i = 0; i < 4; i++) {
756 if (inst->Dst[0].Register.WriteMask & (1 << i))
757 lasti = i;
758 }
759 for (i = 0; i < lasti + 1; i++) {
760 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
761 continue;
762
763 memset(&alu, 0, sizeof(struct r600_bc_alu));
764 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
765
766 alu.src[0].sel = ctx->temp_reg;
767 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
768 if (r)
769 return r;
770 if (i == lasti)
771 alu.last = 1;
772 r = r600_bc_add_alu(ctx->bc, &alu);
773 if (r)
774 return r;
775 }
776 return 0;
777 }
778
779 static int tgsi_scs(struct r600_shader_ctx *ctx)
780 {
781 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
782 struct r600_bc_alu_src r600_src[3];
783 struct r600_bc_alu alu;
784 int r;
785
786 /* We'll only need the trig stuff if we are going to write to the
787 * X or Y components of the destination vector.
788 */
789 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
790 r = tgsi_setup_trig(ctx, r600_src);
791 if (r)
792 return r;
793 }
794
795 /* dst.x = COS */
796 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
797 memset(&alu, 0, sizeof(struct r600_bc_alu));
798 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
799 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
800 if (r)
801 return r;
802
803 alu.src[0].sel = ctx->temp_reg;
804 alu.src[0].chan = 0;
805 alu.last = 1;
806 r = r600_bc_add_alu(ctx->bc, &alu);
807 if (r)
808 return r;
809 }
810
811 /* dst.y = SIN */
812 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
813 memset(&alu, 0, sizeof(struct r600_bc_alu));
814 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
815 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
816 if (r)
817 return r;
818
819 alu.src[0].sel = ctx->temp_reg;
820 alu.src[0].chan = 0;
821 alu.last = 1;
822 r = r600_bc_add_alu(ctx->bc, &alu);
823 if (r)
824 return r;
825 }
826
827 /* dst.z = 0.0; */
828 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
829 memset(&alu, 0, sizeof(struct r600_bc_alu));
830
831 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
832
833 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
834 if (r)
835 return r;
836
837 alu.src[0].sel = V_SQ_ALU_SRC_0;
838 alu.src[0].chan = 0;
839
840 alu.last = 1;
841
842 r = r600_bc_add_alu(ctx->bc, &alu);
843 if (r)
844 return r;
845
846 r = r600_bc_add_literal(ctx->bc, ctx->value);
847 if (r)
848 return r;
849 }
850
851 /* dst.w = 1.0; */
852 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
853 memset(&alu, 0, sizeof(struct r600_bc_alu));
854
855 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
856
857 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
858 if (r)
859 return r;
860
861 alu.src[0].sel = V_SQ_ALU_SRC_1;
862 alu.src[0].chan = 0;
863
864 alu.last = 1;
865
866 r = r600_bc_add_alu(ctx->bc, &alu);
867 if (r)
868 return r;
869
870 r = r600_bc_add_literal(ctx->bc, ctx->value);
871 if (r)
872 return r;
873 }
874
875 return 0;
876 }
877
878 static int tgsi_kill(struct r600_shader_ctx *ctx)
879 {
880 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
881 struct r600_bc_alu alu;
882 int i, r;
883
884 for (i = 0; i < 4; i++) {
885 memset(&alu, 0, sizeof(struct r600_bc_alu));
886 alu.inst = ctx->inst_info->r600_opcode;
887
888 alu.dst.chan = i;
889
890 alu.src[0].sel = V_SQ_ALU_SRC_0;
891
892 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
893 alu.src[1].sel = V_SQ_ALU_SRC_1;
894 alu.src[1].neg = 1;
895 } else {
896 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
897 if (r)
898 return r;
899 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
900 }
901 if (i == 3) {
902 alu.last = 1;
903 }
904 r = r600_bc_add_alu(ctx->bc, &alu);
905 if (r)
906 return r;
907 }
908 r = r600_bc_add_literal(ctx->bc, ctx->value);
909 if (r)
910 return r;
911
912 /* kill must be last in ALU */
913 ctx->bc->force_add_cf = 1;
914 ctx->shader->uses_kill = TRUE;
915 return 0;
916 }
917
918 static int tgsi_lit(struct r600_shader_ctx *ctx)
919 {
920 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
921 struct r600_bc_alu alu;
922 struct r600_bc_alu_src r600_src[3];
923 int r;
924
925 r = tgsi_split_constant(ctx, r600_src);
926 if (r)
927 return r;
928 r = tgsi_split_literal_constant(ctx, r600_src);
929 if (r)
930 return r;
931
932 /* dst.x, <- 1.0 */
933 memset(&alu, 0, sizeof(struct r600_bc_alu));
934 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
935 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
936 alu.src[0].chan = 0;
937 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
938 if (r)
939 return r;
940 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
941 r = r600_bc_add_alu(ctx->bc, &alu);
942 if (r)
943 return r;
944
945 /* dst.y = max(src.x, 0.0) */
946 memset(&alu, 0, sizeof(struct r600_bc_alu));
947 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
948 alu.src[0] = r600_src[0];
949 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
950 alu.src[1].chan = 0;
951 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
952 if (r)
953 return r;
954 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
955 r = r600_bc_add_alu(ctx->bc, &alu);
956 if (r)
957 return r;
958
959 /* dst.w, <- 1.0 */
960 memset(&alu, 0, sizeof(struct r600_bc_alu));
961 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
962 alu.src[0].sel = V_SQ_ALU_SRC_1;
963 alu.src[0].chan = 0;
964 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
965 if (r)
966 return r;
967 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
968 alu.last = 1;
969 r = r600_bc_add_alu(ctx->bc, &alu);
970 if (r)
971 return r;
972
973 r = r600_bc_add_literal(ctx->bc, ctx->value);
974 if (r)
975 return r;
976
977 if (inst->Dst[0].Register.WriteMask & (1 << 2))
978 {
979 int chan;
980 int sel;
981
982 /* dst.z = log(src.y) */
983 memset(&alu, 0, sizeof(struct r600_bc_alu));
984 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
985 alu.src[0] = r600_src[0];
986 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
987 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
988 if (r)
989 return r;
990 alu.last = 1;
991 r = r600_bc_add_alu(ctx->bc, &alu);
992 if (r)
993 return r;
994
995 r = r600_bc_add_literal(ctx->bc, ctx->value);
996 if (r)
997 return r;
998
999 chan = alu.dst.chan;
1000 sel = alu.dst.sel;
1001
1002 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1003 memset(&alu, 0, sizeof(struct r600_bc_alu));
1004 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1005 alu.src[0] = r600_src[0];
1006 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1007 alu.src[1].sel = sel;
1008 alu.src[1].chan = chan;
1009
1010 alu.src[2] = r600_src[0];
1011 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1012 alu.dst.sel = ctx->temp_reg;
1013 alu.dst.chan = 0;
1014 alu.dst.write = 1;
1015 alu.is_op3 = 1;
1016 alu.last = 1;
1017 r = r600_bc_add_alu(ctx->bc, &alu);
1018 if (r)
1019 return r;
1020
1021 r = r600_bc_add_literal(ctx->bc, ctx->value);
1022 if (r)
1023 return r;
1024 /* dst.z = exp(tmp.x) */
1025 memset(&alu, 0, sizeof(struct r600_bc_alu));
1026 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1027 alu.src[0].sel = ctx->temp_reg;
1028 alu.src[0].chan = 0;
1029 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1030 if (r)
1031 return r;
1032 alu.last = 1;
1033 r = r600_bc_add_alu(ctx->bc, &alu);
1034 if (r)
1035 return r;
1036 }
1037 return 0;
1038 }
1039
1040 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1041 {
1042 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1043 struct r600_bc_alu alu;
1044 int i, r;
1045
1046 memset(&alu, 0, sizeof(struct r600_bc_alu));
1047
1048 /* FIXME:
1049 * For state trackers other than OpenGL, we'll want to use
1050 * _RECIPSQRT_IEEE instead.
1051 */
1052 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1053
1054 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1055 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1056 if (r)
1057 return r;
1058 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1059 alu.src[i].abs = 1;
1060 }
1061 alu.dst.sel = ctx->temp_reg;
1062 alu.dst.write = 1;
1063 alu.last = 1;
1064 r = r600_bc_add_alu(ctx->bc, &alu);
1065 if (r)
1066 return r;
1067 r = r600_bc_add_literal(ctx->bc, ctx->value);
1068 if (r)
1069 return r;
1070 /* replicate result */
1071 return tgsi_helper_tempx_replicate(ctx);
1072 }
1073
1074 static int tgsi_trans(struct r600_shader_ctx *ctx)
1075 {
1076 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1077 struct r600_bc_alu alu;
1078 int i, j, r;
1079
1080 for (i = 0; i < 4; i++) {
1081 memset(&alu, 0, sizeof(struct r600_bc_alu));
1082 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
1083 alu.inst = ctx->inst_info->r600_opcode;
1084 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1085 r = tgsi_src(ctx, &inst->Src[j], &alu.src[j]);
1086 if (r)
1087 return r;
1088 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1089 }
1090 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1091 if (r)
1092 return r;
1093 alu.last = 1;
1094 r = r600_bc_add_alu(ctx->bc, &alu);
1095 if (r)
1096 return r;
1097 }
1098 }
1099 return 0;
1100 }
1101
1102 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1103 {
1104 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1105 struct r600_bc_alu alu;
1106 int i, r;
1107
1108 for (i = 0; i < 4; i++) {
1109 memset(&alu, 0, sizeof(struct r600_bc_alu));
1110 alu.src[0].sel = ctx->temp_reg;
1111 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1112 alu.dst.chan = i;
1113 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1114 if (r)
1115 return r;
1116 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1117 if (i == 3)
1118 alu.last = 1;
1119 r = r600_bc_add_alu(ctx->bc, &alu);
1120 if (r)
1121 return r;
1122 }
1123 return 0;
1124 }
1125
1126 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1127 {
1128 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1129 struct r600_bc_alu alu;
1130 int i, r;
1131
1132 memset(&alu, 0, sizeof(struct r600_bc_alu));
1133 alu.inst = ctx->inst_info->r600_opcode;
1134 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1135 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1136 if (r)
1137 return r;
1138 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1139 }
1140 alu.dst.sel = ctx->temp_reg;
1141 alu.dst.write = 1;
1142 alu.last = 1;
1143 r = r600_bc_add_alu(ctx->bc, &alu);
1144 if (r)
1145 return r;
1146 r = r600_bc_add_literal(ctx->bc, ctx->value);
1147 if (r)
1148 return r;
1149 /* replicate result */
1150 return tgsi_helper_tempx_replicate(ctx);
1151 }
1152
1153 static int tgsi_pow(struct r600_shader_ctx *ctx)
1154 {
1155 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1156 struct r600_bc_alu alu;
1157 int r;
1158
1159 /* LOG2(a) */
1160 memset(&alu, 0, sizeof(struct r600_bc_alu));
1161 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1162 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1163 if (r)
1164 return r;
1165 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1166 alu.dst.sel = ctx->temp_reg;
1167 alu.dst.write = 1;
1168 alu.last = 1;
1169 r = r600_bc_add_alu(ctx->bc, &alu);
1170 if (r)
1171 return r;
1172 r = r600_bc_add_literal(ctx->bc,ctx->value);
1173 if (r)
1174 return r;
1175 /* b * LOG2(a) */
1176 memset(&alu, 0, sizeof(struct r600_bc_alu));
1177 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE);
1178 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1179 if (r)
1180 return r;
1181 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1182 alu.src[1].sel = ctx->temp_reg;
1183 alu.dst.sel = ctx->temp_reg;
1184 alu.dst.write = 1;
1185 alu.last = 1;
1186 r = r600_bc_add_alu(ctx->bc, &alu);
1187 if (r)
1188 return r;
1189 r = r600_bc_add_literal(ctx->bc,ctx->value);
1190 if (r)
1191 return r;
1192 /* POW(a,b) = EXP2(b * LOG2(a))*/
1193 memset(&alu, 0, sizeof(struct r600_bc_alu));
1194 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1195 alu.src[0].sel = ctx->temp_reg;
1196 alu.dst.sel = ctx->temp_reg;
1197 alu.dst.write = 1;
1198 alu.last = 1;
1199 r = r600_bc_add_alu(ctx->bc, &alu);
1200 if (r)
1201 return r;
1202 r = r600_bc_add_literal(ctx->bc,ctx->value);
1203 if (r)
1204 return r;
1205 return tgsi_helper_tempx_replicate(ctx);
1206 }
1207
1208 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1209 {
1210 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1211 struct r600_bc_alu alu;
1212 struct r600_bc_alu_src r600_src[3];
1213 int i, r;
1214
1215 r = tgsi_split_constant(ctx, r600_src);
1216 if (r)
1217 return r;
1218
1219 /* tmp = (src > 0 ? 1 : src) */
1220 for (i = 0; i < 4; i++) {
1221 memset(&alu, 0, sizeof(struct r600_bc_alu));
1222 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1223 alu.is_op3 = 1;
1224
1225 alu.dst.sel = ctx->temp_reg;
1226 alu.dst.chan = i;
1227
1228 alu.src[0] = r600_src[0];
1229 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1230
1231 alu.src[1].sel = V_SQ_ALU_SRC_1;
1232
1233 alu.src[2] = r600_src[0];
1234 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1235 if (i == 3)
1236 alu.last = 1;
1237 r = r600_bc_add_alu(ctx->bc, &alu);
1238 if (r)
1239 return r;
1240 }
1241 r = r600_bc_add_literal(ctx->bc, ctx->value);
1242 if (r)
1243 return r;
1244
1245 /* dst = (-tmp > 0 ? -1 : tmp) */
1246 for (i = 0; i < 4; i++) {
1247 memset(&alu, 0, sizeof(struct r600_bc_alu));
1248 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1249 alu.is_op3 = 1;
1250 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1251 if (r)
1252 return r;
1253
1254 alu.src[0].sel = ctx->temp_reg;
1255 alu.src[0].chan = i;
1256 alu.src[0].neg = 1;
1257
1258 alu.src[1].sel = V_SQ_ALU_SRC_1;
1259 alu.src[1].neg = 1;
1260
1261 alu.src[2].sel = ctx->temp_reg;
1262 alu.src[2].chan = i;
1263
1264 if (i == 3)
1265 alu.last = 1;
1266 r = r600_bc_add_alu(ctx->bc, &alu);
1267 if (r)
1268 return r;
1269 }
1270 return 0;
1271 }
1272
1273 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1274 {
1275 struct r600_bc_alu alu;
1276 int i, r;
1277
1278 r = r600_bc_add_literal(ctx->bc, ctx->value);
1279 if (r)
1280 return r;
1281 for (i = 0; i < 4; i++) {
1282 memset(&alu, 0, sizeof(struct r600_bc_alu));
1283 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1284 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1285 alu.dst.chan = i;
1286 } else {
1287 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1288 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1289 if (r)
1290 return r;
1291 alu.src[0].sel = ctx->temp_reg;
1292 alu.src[0].chan = i;
1293 }
1294 if (i == 3) {
1295 alu.last = 1;
1296 }
1297 r = r600_bc_add_alu(ctx->bc, &alu);
1298 if (r)
1299 return r;
1300 }
1301 return 0;
1302 }
1303
1304 static int tgsi_op3(struct r600_shader_ctx *ctx)
1305 {
1306 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1307 struct r600_bc_alu_src r600_src[3];
1308 struct r600_bc_alu alu;
1309 int i, j, r;
1310
1311 r = tgsi_split_constant(ctx, r600_src);
1312 if (r)
1313 return r;
1314 /* do it in 2 step as op3 doesn't support writemask */
1315 for (i = 0; i < 4; i++) {
1316 memset(&alu, 0, sizeof(struct r600_bc_alu));
1317 alu.inst = ctx->inst_info->r600_opcode;
1318 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1319 alu.src[j] = r600_src[j];
1320 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1321 }
1322 alu.dst.sel = ctx->temp_reg;
1323 alu.dst.chan = i;
1324 alu.dst.write = 1;
1325 alu.is_op3 = 1;
1326 if (i == 3) {
1327 alu.last = 1;
1328 }
1329 r = r600_bc_add_alu(ctx->bc, &alu);
1330 if (r)
1331 return r;
1332 }
1333 return tgsi_helper_copy(ctx, inst);
1334 }
1335
1336 static int tgsi_dp(struct r600_shader_ctx *ctx)
1337 {
1338 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1339 struct r600_bc_alu_src r600_src[3];
1340 struct r600_bc_alu alu;
1341 int i, j, r;
1342
1343 r = tgsi_split_constant(ctx, r600_src);
1344 if (r)
1345 return r;
1346 for (i = 0; i < 4; i++) {
1347 memset(&alu, 0, sizeof(struct r600_bc_alu));
1348 alu.inst = ctx->inst_info->r600_opcode;
1349 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1350 alu.src[j] = r600_src[j];
1351 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1352 }
1353 alu.dst.sel = ctx->temp_reg;
1354 alu.dst.chan = i;
1355 alu.dst.write = 1;
1356 /* handle some special cases */
1357 switch (ctx->inst_info->tgsi_opcode) {
1358 case TGSI_OPCODE_DP2:
1359 if (i > 1) {
1360 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1361 alu.src[0].chan = alu.src[1].chan = 0;
1362 }
1363 break;
1364 case TGSI_OPCODE_DP3:
1365 if (i > 2) {
1366 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1367 alu.src[0].chan = alu.src[1].chan = 0;
1368 }
1369 break;
1370 case TGSI_OPCODE_DPH:
1371 if (i == 3) {
1372 alu.src[0].sel = V_SQ_ALU_SRC_1;
1373 alu.src[0].chan = 0;
1374 alu.src[0].neg = 0;
1375 }
1376 break;
1377 default:
1378 break;
1379 }
1380 if (i == 3) {
1381 alu.last = 1;
1382 }
1383 r = r600_bc_add_alu(ctx->bc, &alu);
1384 if (r)
1385 return r;
1386 }
1387 return tgsi_helper_copy(ctx, inst);
1388 }
1389
1390 static int tgsi_tex(struct r600_shader_ctx *ctx)
1391 {
1392 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1393 struct r600_bc_tex tex;
1394 struct r600_bc_alu alu;
1395 unsigned src_gpr;
1396 int r, i;
1397 int opcode;
1398 boolean src_not_temp = inst->Src[0].Register.File != TGSI_FILE_TEMPORARY;
1399 uint32_t lit_vals[4];
1400
1401 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1402
1403 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1404 /* Add perspective divide */
1405 memset(&alu, 0, sizeof(struct r600_bc_alu));
1406 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1407 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1408 if (r)
1409 return r;
1410
1411 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1412 alu.dst.sel = ctx->temp_reg;
1413 alu.dst.chan = 3;
1414 alu.last = 1;
1415 alu.dst.write = 1;
1416 r = r600_bc_add_alu(ctx->bc, &alu);
1417 if (r)
1418 return r;
1419
1420 for (i = 0; i < 3; i++) {
1421 memset(&alu, 0, sizeof(struct r600_bc_alu));
1422 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1423 alu.src[0].sel = ctx->temp_reg;
1424 alu.src[0].chan = 3;
1425 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1426 if (r)
1427 return r;
1428 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1429 alu.dst.sel = ctx->temp_reg;
1430 alu.dst.chan = i;
1431 alu.dst.write = 1;
1432 r = r600_bc_add_alu(ctx->bc, &alu);
1433 if (r)
1434 return r;
1435 }
1436 memset(&alu, 0, sizeof(struct r600_bc_alu));
1437 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1438 alu.src[0].sel = V_SQ_ALU_SRC_1;
1439 alu.src[0].chan = 0;
1440 alu.dst.sel = ctx->temp_reg;
1441 alu.dst.chan = 3;
1442 alu.last = 1;
1443 alu.dst.write = 1;
1444 r = r600_bc_add_alu(ctx->bc, &alu);
1445 if (r)
1446 return r;
1447 src_not_temp = FALSE;
1448 src_gpr = ctx->temp_reg;
1449 }
1450
1451 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1452 int src_chan, src2_chan;
1453
1454 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1455 for (i = 0; i < 4; i++) {
1456 memset(&alu, 0, sizeof(struct r600_bc_alu));
1457 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1458 switch (i) {
1459 case 0:
1460 src_chan = 2;
1461 src2_chan = 1;
1462 break;
1463 case 1:
1464 src_chan = 2;
1465 src2_chan = 0;
1466 break;
1467 case 2:
1468 src_chan = 0;
1469 src2_chan = 2;
1470 break;
1471 case 3:
1472 src_chan = 1;
1473 src2_chan = 2;
1474 break;
1475 default:
1476 assert(0);
1477 src_chan = 0;
1478 src2_chan = 0;
1479 break;
1480 }
1481 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1482 if (r)
1483 return r;
1484 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1485 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1486 if (r)
1487 return r;
1488 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1489 alu.dst.sel = ctx->temp_reg;
1490 alu.dst.chan = i;
1491 if (i == 3)
1492 alu.last = 1;
1493 alu.dst.write = 1;
1494 r = r600_bc_add_alu(ctx->bc, &alu);
1495 if (r)
1496 return r;
1497 }
1498
1499 /* tmp1.z = RCP_e(|tmp1.z|) */
1500 memset(&alu, 0, sizeof(struct r600_bc_alu));
1501 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1502 alu.src[0].sel = ctx->temp_reg;
1503 alu.src[0].chan = 2;
1504 alu.src[0].abs = 1;
1505 alu.dst.sel = ctx->temp_reg;
1506 alu.dst.chan = 2;
1507 alu.dst.write = 1;
1508 alu.last = 1;
1509 r = r600_bc_add_alu(ctx->bc, &alu);
1510 if (r)
1511 return r;
1512
1513 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1514 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1515 * muladd has no writemask, have to use another temp
1516 */
1517 memset(&alu, 0, sizeof(struct r600_bc_alu));
1518 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1519 alu.is_op3 = 1;
1520
1521 alu.src[0].sel = ctx->temp_reg;
1522 alu.src[0].chan = 0;
1523 alu.src[1].sel = ctx->temp_reg;
1524 alu.src[1].chan = 2;
1525
1526 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1527 alu.src[2].chan = 0;
1528
1529 alu.dst.sel = ctx->temp_reg;
1530 alu.dst.chan = 0;
1531 alu.dst.write = 1;
1532
1533 r = r600_bc_add_alu(ctx->bc, &alu);
1534 if (r)
1535 return r;
1536
1537 memset(&alu, 0, sizeof(struct r600_bc_alu));
1538 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1539 alu.is_op3 = 1;
1540
1541 alu.src[0].sel = ctx->temp_reg;
1542 alu.src[0].chan = 1;
1543 alu.src[1].sel = ctx->temp_reg;
1544 alu.src[1].chan = 2;
1545
1546 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1547 alu.src[2].chan = 0;
1548
1549 alu.dst.sel = ctx->temp_reg;
1550 alu.dst.chan = 1;
1551 alu.dst.write = 1;
1552
1553 alu.last = 1;
1554 r = r600_bc_add_alu(ctx->bc, &alu);
1555 if (r)
1556 return r;
1557
1558 lit_vals[0] = fui(1.5f);
1559
1560 r = r600_bc_add_literal(ctx->bc, lit_vals);
1561 if (r)
1562 return r;
1563 src_not_temp = FALSE;
1564 src_gpr = ctx->temp_reg;
1565 }
1566
1567 if (src_not_temp) {
1568 for (i = 0; i < 4; i++) {
1569 memset(&alu, 0, sizeof(struct r600_bc_alu));
1570 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1571 alu.src[0].sel = src_gpr;
1572 alu.src[0].chan = i;
1573 alu.dst.sel = ctx->temp_reg;
1574 alu.dst.chan = i;
1575 if (i == 3)
1576 alu.last = 1;
1577 alu.dst.write = 1;
1578 r = r600_bc_add_alu(ctx->bc, &alu);
1579 if (r)
1580 return r;
1581 }
1582 src_gpr = ctx->temp_reg;
1583 }
1584
1585 opcode = ctx->inst_info->r600_opcode;
1586 if (opcode == SQ_TEX_INST_SAMPLE &&
1587 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1588 opcode = SQ_TEX_INST_SAMPLE_C;
1589
1590 memset(&tex, 0, sizeof(struct r600_bc_tex));
1591 tex.inst = opcode;
1592 tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1593 tex.sampler_id = tex.resource_id;
1594 tex.src_gpr = src_gpr;
1595 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1596 tex.dst_sel_x = 0;
1597 tex.dst_sel_y = 1;
1598 tex.dst_sel_z = 2;
1599 tex.dst_sel_w = 3;
1600 tex.src_sel_x = 0;
1601 tex.src_sel_y = 1;
1602 tex.src_sel_z = 2;
1603 tex.src_sel_w = 3;
1604
1605 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1606 tex.src_sel_x = 1;
1607 tex.src_sel_y = 0;
1608 tex.src_sel_z = 3;
1609 tex.src_sel_w = 1;
1610 }
1611
1612 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1613 tex.coord_type_x = 1;
1614 tex.coord_type_y = 1;
1615 tex.coord_type_z = 1;
1616 tex.coord_type_w = 1;
1617 }
1618
1619 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1620 tex.src_sel_w = 2;
1621
1622 r = r600_bc_add_tex(ctx->bc, &tex);
1623 if (r)
1624 return r;
1625
1626 /* add shadow ambient support - gallium doesn't do it yet */
1627 return 0;
1628
1629 }
1630
1631 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1632 {
1633 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1634 struct r600_bc_alu_src r600_src[3];
1635 struct r600_bc_alu alu;
1636 unsigned i;
1637 int r;
1638
1639 r = tgsi_split_constant(ctx, r600_src);
1640 if (r)
1641 return r;
1642 /* 1 - src0 */
1643 for (i = 0; i < 4; i++) {
1644 memset(&alu, 0, sizeof(struct r600_bc_alu));
1645 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1646 alu.src[0].sel = V_SQ_ALU_SRC_1;
1647 alu.src[0].chan = 0;
1648 alu.src[1] = r600_src[0];
1649 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1650 alu.src[1].neg = 1;
1651 alu.dst.sel = ctx->temp_reg;
1652 alu.dst.chan = i;
1653 if (i == 3) {
1654 alu.last = 1;
1655 }
1656 alu.dst.write = 1;
1657 r = r600_bc_add_alu(ctx->bc, &alu);
1658 if (r)
1659 return r;
1660 }
1661 r = r600_bc_add_literal(ctx->bc, ctx->value);
1662 if (r)
1663 return r;
1664
1665 /* (1 - src0) * src2 */
1666 for (i = 0; i < 4; i++) {
1667 memset(&alu, 0, sizeof(struct r600_bc_alu));
1668 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1669 alu.src[0].sel = ctx->temp_reg;
1670 alu.src[0].chan = i;
1671 alu.src[1] = r600_src[2];
1672 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1673 alu.dst.sel = ctx->temp_reg;
1674 alu.dst.chan = i;
1675 if (i == 3) {
1676 alu.last = 1;
1677 }
1678 alu.dst.write = 1;
1679 r = r600_bc_add_alu(ctx->bc, &alu);
1680 if (r)
1681 return r;
1682 }
1683 r = r600_bc_add_literal(ctx->bc, ctx->value);
1684 if (r)
1685 return r;
1686
1687 /* src0 * src1 + (1 - src0) * src2 */
1688 for (i = 0; i < 4; i++) {
1689 memset(&alu, 0, sizeof(struct r600_bc_alu));
1690 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1691 alu.is_op3 = 1;
1692 alu.src[0] = r600_src[0];
1693 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1694 alu.src[1] = r600_src[1];
1695 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1696 alu.src[2].sel = ctx->temp_reg;
1697 alu.src[2].chan = i;
1698 alu.dst.sel = ctx->temp_reg;
1699 alu.dst.chan = i;
1700 if (i == 3) {
1701 alu.last = 1;
1702 }
1703 r = r600_bc_add_alu(ctx->bc, &alu);
1704 if (r)
1705 return r;
1706 }
1707 return tgsi_helper_copy(ctx, inst);
1708 }
1709
1710 static int tgsi_cmp(struct r600_shader_ctx *ctx)
1711 {
1712 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1713 struct r600_bc_alu_src r600_src[3];
1714 struct r600_bc_alu alu;
1715 int use_temp = 0;
1716 int i, r;
1717
1718 r = tgsi_split_constant(ctx, r600_src);
1719 if (r)
1720 return r;
1721
1722 if (inst->Dst[0].Register.WriteMask != 0xf)
1723 use_temp = 1;
1724
1725 for (i = 0; i < 4; i++) {
1726 memset(&alu, 0, sizeof(struct r600_bc_alu));
1727 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
1728 alu.src[0] = r600_src[0];
1729 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1730
1731 alu.src[1] = r600_src[2];
1732 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1733
1734 alu.src[2] = r600_src[1];
1735 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
1736
1737 if (use_temp)
1738 alu.dst.sel = ctx->temp_reg;
1739 else {
1740 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1741 if (r)
1742 return r;
1743 }
1744 alu.dst.chan = i;
1745 alu.dst.write = 1;
1746 alu.is_op3 = 1;
1747 if (i == 3)
1748 alu.last = 1;
1749 r = r600_bc_add_alu(ctx->bc, &alu);
1750 if (r)
1751 return r;
1752 }
1753 if (use_temp)
1754 return tgsi_helper_copy(ctx, inst);
1755 return 0;
1756 }
1757
1758 static int tgsi_xpd(struct r600_shader_ctx *ctx)
1759 {
1760 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1761 struct r600_bc_alu_src r600_src[3];
1762 struct r600_bc_alu alu;
1763 uint32_t use_temp = 0;
1764 int i, r;
1765
1766 if (inst->Dst[0].Register.WriteMask != 0xf)
1767 use_temp = 1;
1768
1769 r = tgsi_split_constant(ctx, r600_src);
1770 if (r)
1771 return r;
1772
1773 for (i = 0; i < 4; i++) {
1774 memset(&alu, 0, sizeof(struct r600_bc_alu));
1775 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1776
1777 alu.src[0] = r600_src[0];
1778 switch (i) {
1779 case 0:
1780 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
1781 break;
1782 case 1:
1783 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1784 break;
1785 case 2:
1786 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1787 break;
1788 case 3:
1789 alu.src[0].sel = V_SQ_ALU_SRC_0;
1790 alu.src[0].chan = i;
1791 }
1792
1793 alu.src[1] = r600_src[1];
1794 switch (i) {
1795 case 0:
1796 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
1797 break;
1798 case 1:
1799 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
1800 break;
1801 case 2:
1802 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
1803 break;
1804 case 3:
1805 alu.src[1].sel = V_SQ_ALU_SRC_0;
1806 alu.src[1].chan = i;
1807 }
1808
1809 alu.dst.sel = ctx->temp_reg;
1810 alu.dst.chan = i;
1811 alu.dst.write = 1;
1812
1813 if (i == 3)
1814 alu.last = 1;
1815 r = r600_bc_add_alu(ctx->bc, &alu);
1816 if (r)
1817 return r;
1818
1819 r = r600_bc_add_literal(ctx->bc, ctx->value);
1820 if (r)
1821 return r;
1822 }
1823
1824 for (i = 0; i < 4; i++) {
1825 memset(&alu, 0, sizeof(struct r600_bc_alu));
1826 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1827
1828 alu.src[0] = r600_src[0];
1829 switch (i) {
1830 case 0:
1831 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1832 break;
1833 case 1:
1834 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
1835 break;
1836 case 2:
1837 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1838 break;
1839 case 3:
1840 alu.src[0].sel = V_SQ_ALU_SRC_0;
1841 alu.src[0].chan = i;
1842 }
1843
1844 alu.src[1] = r600_src[1];
1845 switch (i) {
1846 case 0:
1847 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
1848 break;
1849 case 1:
1850 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
1851 break;
1852 case 2:
1853 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
1854 break;
1855 case 3:
1856 alu.src[1].sel = V_SQ_ALU_SRC_0;
1857 alu.src[1].chan = i;
1858 }
1859
1860 alu.src[2].sel = ctx->temp_reg;
1861 alu.src[2].neg = 1;
1862 alu.src[2].chan = i;
1863
1864 if (use_temp)
1865 alu.dst.sel = ctx->temp_reg;
1866 else {
1867 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1868 if (r)
1869 return r;
1870 }
1871 alu.dst.chan = i;
1872 alu.dst.write = 1;
1873 alu.is_op3 = 1;
1874 if (i == 3)
1875 alu.last = 1;
1876 r = r600_bc_add_alu(ctx->bc, &alu);
1877 if (r)
1878 return r;
1879
1880 r = r600_bc_add_literal(ctx->bc, ctx->value);
1881 if (r)
1882 return r;
1883 }
1884 if (use_temp)
1885 return tgsi_helper_copy(ctx, inst);
1886 return 0;
1887 }
1888
1889 static int tgsi_exp(struct r600_shader_ctx *ctx)
1890 {
1891 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1892 struct r600_bc_alu_src r600_src[3];
1893 struct r600_bc_alu alu;
1894 int r;
1895
1896 /* result.x = 2^floor(src); */
1897 if (inst->Dst[0].Register.WriteMask & 1) {
1898 memset(&alu, 0, sizeof(struct r600_bc_alu));
1899
1900 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
1901 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1902 if (r)
1903 return r;
1904
1905 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1906
1907 alu.dst.sel = ctx->temp_reg;
1908 alu.dst.chan = 0;
1909 alu.dst.write = 1;
1910 alu.last = 1;
1911 r = r600_bc_add_alu(ctx->bc, &alu);
1912 if (r)
1913 return r;
1914
1915 r = r600_bc_add_literal(ctx->bc, ctx->value);
1916 if (r)
1917 return r;
1918
1919 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1920 alu.src[0].sel = ctx->temp_reg;
1921 alu.src[0].chan = 0;
1922
1923 alu.dst.sel = ctx->temp_reg;
1924 alu.dst.chan = 0;
1925 alu.dst.write = 1;
1926 alu.last = 1;
1927 r = r600_bc_add_alu(ctx->bc, &alu);
1928 if (r)
1929 return r;
1930
1931 r = r600_bc_add_literal(ctx->bc, ctx->value);
1932 if (r)
1933 return r;
1934 }
1935
1936 /* result.y = tmp - floor(tmp); */
1937 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
1938 memset(&alu, 0, sizeof(struct r600_bc_alu));
1939
1940 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
1941 alu.src[0] = r600_src[0];
1942 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1943 if (r)
1944 return r;
1945 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1946
1947 alu.dst.sel = ctx->temp_reg;
1948 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1949 // if (r)
1950 // return r;
1951 alu.dst.write = 1;
1952 alu.dst.chan = 1;
1953
1954 alu.last = 1;
1955
1956 r = r600_bc_add_alu(ctx->bc, &alu);
1957 if (r)
1958 return r;
1959 r = r600_bc_add_literal(ctx->bc, ctx->value);
1960 if (r)
1961 return r;
1962 }
1963
1964 /* result.z = RoughApprox2ToX(tmp);*/
1965 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
1966 memset(&alu, 0, sizeof(struct r600_bc_alu));
1967 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1968 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1969 if (r)
1970 return r;
1971 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1972
1973 alu.dst.sel = ctx->temp_reg;
1974 alu.dst.write = 1;
1975 alu.dst.chan = 2;
1976
1977 alu.last = 1;
1978
1979 r = r600_bc_add_alu(ctx->bc, &alu);
1980 if (r)
1981 return r;
1982 r = r600_bc_add_literal(ctx->bc, ctx->value);
1983 if (r)
1984 return r;
1985 }
1986
1987 /* result.w = 1.0;*/
1988 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
1989 memset(&alu, 0, sizeof(struct r600_bc_alu));
1990
1991 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1992 alu.src[0].sel = V_SQ_ALU_SRC_1;
1993 alu.src[0].chan = 0;
1994
1995 alu.dst.sel = ctx->temp_reg;
1996 alu.dst.chan = 3;
1997 alu.dst.write = 1;
1998 alu.last = 1;
1999 r = r600_bc_add_alu(ctx->bc, &alu);
2000 if (r)
2001 return r;
2002 r = r600_bc_add_literal(ctx->bc, ctx->value);
2003 if (r)
2004 return r;
2005 }
2006 return tgsi_helper_copy(ctx, inst);
2007 }
2008
2009 static int tgsi_log(struct r600_shader_ctx *ctx)
2010 {
2011 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2012 struct r600_bc_alu alu;
2013 int r;
2014
2015 /* result.x = floor(log2(src)); */
2016 if (inst->Dst[0].Register.WriteMask & 1) {
2017 memset(&alu, 0, sizeof(struct r600_bc_alu));
2018
2019 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2020 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2021 if (r)
2022 return r;
2023
2024 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2025
2026 alu.dst.sel = ctx->temp_reg;
2027 alu.dst.chan = 0;
2028 alu.dst.write = 1;
2029 alu.last = 1;
2030 r = r600_bc_add_alu(ctx->bc, &alu);
2031 if (r)
2032 return r;
2033
2034 r = r600_bc_add_literal(ctx->bc, ctx->value);
2035 if (r)
2036 return r;
2037
2038 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2039 alu.src[0].sel = ctx->temp_reg;
2040 alu.src[0].chan = 0;
2041
2042 alu.dst.sel = ctx->temp_reg;
2043 alu.dst.chan = 0;
2044 alu.dst.write = 1;
2045 alu.last = 1;
2046
2047 r = r600_bc_add_alu(ctx->bc, &alu);
2048 if (r)
2049 return r;
2050
2051 r = r600_bc_add_literal(ctx->bc, ctx->value);
2052 if (r)
2053 return r;
2054 }
2055
2056 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2057 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2058 memset(&alu, 0, sizeof(struct r600_bc_alu));
2059
2060 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2061 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2062 if (r)
2063 return r;
2064
2065 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2066
2067 alu.dst.sel = ctx->temp_reg;
2068 alu.dst.chan = 1;
2069 alu.dst.write = 1;
2070 alu.last = 1;
2071
2072 r = r600_bc_add_alu(ctx->bc, &alu);
2073 if (r)
2074 return r;
2075
2076 r = r600_bc_add_literal(ctx->bc, ctx->value);
2077 if (r)
2078 return r;
2079
2080 memset(&alu, 0, sizeof(struct r600_bc_alu));
2081
2082 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2083 alu.src[0].sel = ctx->temp_reg;
2084 alu.src[0].chan = 1;
2085
2086 alu.dst.sel = ctx->temp_reg;
2087 alu.dst.chan = 1;
2088 alu.dst.write = 1;
2089 alu.last = 1;
2090
2091 r = r600_bc_add_alu(ctx->bc, &alu);
2092 if (r)
2093 return r;
2094
2095 r = r600_bc_add_literal(ctx->bc, ctx->value);
2096 if (r)
2097 return r;
2098
2099 memset(&alu, 0, sizeof(struct r600_bc_alu));
2100
2101 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2102 alu.src[0].sel = ctx->temp_reg;
2103 alu.src[0].chan = 1;
2104
2105 alu.dst.sel = ctx->temp_reg;
2106 alu.dst.chan = 1;
2107 alu.dst.write = 1;
2108 alu.last = 1;
2109
2110 r = r600_bc_add_alu(ctx->bc, &alu);
2111 if (r)
2112 return r;
2113
2114 r = r600_bc_add_literal(ctx->bc, ctx->value);
2115 if (r)
2116 return r;
2117
2118 memset(&alu, 0, sizeof(struct r600_bc_alu));
2119
2120 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2121 alu.src[0].sel = ctx->temp_reg;
2122 alu.src[0].chan = 1;
2123
2124 alu.dst.sel = ctx->temp_reg;
2125 alu.dst.chan = 1;
2126 alu.dst.write = 1;
2127 alu.last = 1;
2128
2129 r = r600_bc_add_alu(ctx->bc, &alu);
2130 if (r)
2131 return r;
2132
2133 r = r600_bc_add_literal(ctx->bc, ctx->value);
2134 if (r)
2135 return r;
2136
2137 memset(&alu, 0, sizeof(struct r600_bc_alu));
2138
2139 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2140
2141 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2142 if (r)
2143 return r;
2144
2145 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2146
2147 alu.src[1].sel = ctx->temp_reg;
2148 alu.src[1].chan = 1;
2149
2150 alu.dst.sel = ctx->temp_reg;
2151 alu.dst.chan = 1;
2152 alu.dst.write = 1;
2153 alu.last = 1;
2154
2155 r = r600_bc_add_alu(ctx->bc, &alu);
2156 if (r)
2157 return r;
2158
2159 r = r600_bc_add_literal(ctx->bc, ctx->value);
2160 if (r)
2161 return r;
2162 }
2163
2164 /* result.z = log2(src);*/
2165 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2166 memset(&alu, 0, sizeof(struct r600_bc_alu));
2167
2168 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2169 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2170 if (r)
2171 return r;
2172
2173 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2174
2175 alu.dst.sel = ctx->temp_reg;
2176 alu.dst.write = 1;
2177 alu.dst.chan = 2;
2178 alu.last = 1;
2179
2180 r = r600_bc_add_alu(ctx->bc, &alu);
2181 if (r)
2182 return r;
2183
2184 r = r600_bc_add_literal(ctx->bc, ctx->value);
2185 if (r)
2186 return r;
2187 }
2188
2189 /* result.w = 1.0; */
2190 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2191 memset(&alu, 0, sizeof(struct r600_bc_alu));
2192
2193 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2194 alu.src[0].sel = V_SQ_ALU_SRC_1;
2195 alu.src[0].chan = 0;
2196
2197 alu.dst.sel = ctx->temp_reg;
2198 alu.dst.chan = 3;
2199 alu.dst.write = 1;
2200 alu.last = 1;
2201
2202 r = r600_bc_add_alu(ctx->bc, &alu);
2203 if (r)
2204 return r;
2205
2206 r = r600_bc_add_literal(ctx->bc, ctx->value);
2207 if (r)
2208 return r;
2209 }
2210
2211 return tgsi_helper_copy(ctx, inst);
2212 }
2213
2214 /* r6/7 only for now */
2215 static int tgsi_arl(struct r600_shader_ctx *ctx)
2216 {
2217 /* TODO from r600c, ar values don't persist between clauses */
2218 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2219 struct r600_bc_alu alu;
2220 int r;
2221 memset(&alu, 0, sizeof(struct r600_bc_alu));
2222
2223 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2224
2225 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2226 if (r)
2227 return r;
2228 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2229
2230 alu.last = 1;
2231
2232 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2233 if (r)
2234 return r;
2235 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2236 return 0;
2237 }
2238
2239 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2240 {
2241 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2242 struct r600_bc_alu alu;
2243 int i, r = 0;
2244
2245 for (i = 0; i < 4; i++) {
2246 memset(&alu, 0, sizeof(struct r600_bc_alu));
2247
2248 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2249 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2250 if (r)
2251 return r;
2252
2253 if (i == 0 || i == 3) {
2254 alu.src[0].sel = V_SQ_ALU_SRC_1;
2255 } else {
2256 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2257 if (r)
2258 return r;
2259 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2260 }
2261
2262 if (i == 0 || i == 2) {
2263 alu.src[1].sel = V_SQ_ALU_SRC_1;
2264 } else {
2265 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2266 if (r)
2267 return r;
2268 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2269 }
2270 if (i == 3)
2271 alu.last = 1;
2272 r = r600_bc_add_alu(ctx->bc, &alu);
2273 if (r)
2274 return r;
2275 }
2276 return 0;
2277 }
2278
2279 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2280 {
2281 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2282 struct r600_bc_alu alu;
2283 int r;
2284
2285 memset(&alu, 0, sizeof(struct r600_bc_alu));
2286 alu.inst = opcode;
2287 alu.predicate = 1;
2288
2289 alu.dst.sel = ctx->temp_reg;
2290 alu.dst.write = 1;
2291 alu.dst.chan = 0;
2292
2293 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2294 if (r)
2295 return r;
2296 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2297 alu.src[1].sel = V_SQ_ALU_SRC_0;
2298 alu.src[1].chan = 0;
2299
2300 alu.last = 1;
2301
2302 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2303 if (r)
2304 return r;
2305 return 0;
2306 }
2307
2308 static int pops(struct r600_shader_ctx *ctx, int pops)
2309 {
2310 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2311 ctx->bc->cf_last->pop_count = pops;
2312 return 0;
2313 }
2314
2315 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2316 {
2317 switch(reason) {
2318 case FC_PUSH_VPM:
2319 ctx->bc->callstack[ctx->bc->call_sp].current--;
2320 break;
2321 case FC_PUSH_WQM:
2322 case FC_LOOP:
2323 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2324 break;
2325 case FC_REP:
2326 /* TOODO : for 16 vp asic should -= 2; */
2327 ctx->bc->callstack[ctx->bc->call_sp].current --;
2328 break;
2329 }
2330 }
2331
2332 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2333 {
2334 if (check_max_only) {
2335 int diff;
2336 switch (reason) {
2337 case FC_PUSH_VPM:
2338 diff = 1;
2339 break;
2340 case FC_PUSH_WQM:
2341 diff = 4;
2342 break;
2343 default:
2344 assert(0);
2345 diff = 0;
2346 }
2347 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2348 ctx->bc->callstack[ctx->bc->call_sp].max) {
2349 ctx->bc->callstack[ctx->bc->call_sp].max =
2350 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2351 }
2352 return;
2353 }
2354 switch (reason) {
2355 case FC_PUSH_VPM:
2356 ctx->bc->callstack[ctx->bc->call_sp].current++;
2357 break;
2358 case FC_PUSH_WQM:
2359 case FC_LOOP:
2360 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2361 break;
2362 case FC_REP:
2363 ctx->bc->callstack[ctx->bc->call_sp].current++;
2364 break;
2365 }
2366
2367 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2368 ctx->bc->callstack[ctx->bc->call_sp].max) {
2369 ctx->bc->callstack[ctx->bc->call_sp].max =
2370 ctx->bc->callstack[ctx->bc->call_sp].current;
2371 }
2372 }
2373
2374 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2375 {
2376 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2377
2378 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2379 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2380 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2381 sp->num_mid++;
2382 }
2383
2384 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2385 {
2386 ctx->bc->fc_sp++;
2387 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2388 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2389 }
2390
2391 static void fc_poplevel(struct r600_shader_ctx *ctx)
2392 {
2393 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2394 if (sp->mid) {
2395 free(sp->mid);
2396 sp->mid = NULL;
2397 }
2398 sp->num_mid = 0;
2399 sp->start = NULL;
2400 sp->type = 0;
2401 ctx->bc->fc_sp--;
2402 }
2403
2404 #if 0
2405 static int emit_return(struct r600_shader_ctx *ctx)
2406 {
2407 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2408 return 0;
2409 }
2410
2411 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2412 {
2413
2414 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2415 ctx->bc->cf_last->pop_count = pops;
2416 /* TODO work out offset */
2417 return 0;
2418 }
2419
2420 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2421 {
2422 return 0;
2423 }
2424
2425 static void emit_testflag(struct r600_shader_ctx *ctx)
2426 {
2427
2428 }
2429
2430 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2431 {
2432 emit_testflag(ctx);
2433 emit_jump_to_offset(ctx, 1, 4);
2434 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2435 pops(ctx, ifidx + 1);
2436 emit_return(ctx);
2437 }
2438
2439 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2440 {
2441 emit_testflag(ctx);
2442
2443 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2444 ctx->bc->cf_last->pop_count = 1;
2445
2446 fc_set_mid(ctx, fc_sp);
2447
2448 pops(ctx, 1);
2449 }
2450 #endif
2451
2452 static int tgsi_if(struct r600_shader_ctx *ctx)
2453 {
2454 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2455
2456 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2457
2458 fc_pushlevel(ctx, FC_IF);
2459
2460 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2461 return 0;
2462 }
2463
2464 static int tgsi_else(struct r600_shader_ctx *ctx)
2465 {
2466 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2467 ctx->bc->cf_last->pop_count = 1;
2468
2469 fc_set_mid(ctx, ctx->bc->fc_sp);
2470 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2471 return 0;
2472 }
2473
2474 static int tgsi_endif(struct r600_shader_ctx *ctx)
2475 {
2476 pops(ctx, 1);
2477 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2478 R600_ERR("if/endif unbalanced in shader\n");
2479 return -1;
2480 }
2481
2482 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2483 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2484 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2485 } else {
2486 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2487 }
2488 fc_poplevel(ctx);
2489
2490 callstack_decrease_current(ctx, FC_PUSH_VPM);
2491 return 0;
2492 }
2493
2494 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2495 {
2496 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2497
2498 fc_pushlevel(ctx, FC_LOOP);
2499
2500 /* check stack depth */
2501 callstack_check_depth(ctx, FC_LOOP, 0);
2502 return 0;
2503 }
2504
2505 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2506 {
2507 int i;
2508
2509 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2510
2511 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2512 R600_ERR("loop/endloop in shader code are not paired.\n");
2513 return -EINVAL;
2514 }
2515
2516 /* fixup loop pointers - from r600isa
2517 LOOP END points to CF after LOOP START,
2518 LOOP START point to CF after LOOP END
2519 BRK/CONT point to LOOP END CF
2520 */
2521 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2522
2523 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2524
2525 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2526 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2527 }
2528 /* TODO add LOOPRET support */
2529 fc_poplevel(ctx);
2530 callstack_decrease_current(ctx, FC_LOOP);
2531 return 0;
2532 }
2533
2534 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2535 {
2536 unsigned int fscp;
2537
2538 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2539 {
2540 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2541 break;
2542 }
2543
2544 if (fscp == 0) {
2545 R600_ERR("Break not inside loop/endloop pair\n");
2546 return -EINVAL;
2547 }
2548
2549 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2550 ctx->bc->cf_last->pop_count = 1;
2551
2552 fc_set_mid(ctx, fscp);
2553
2554 pops(ctx, 1);
2555 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2556 return 0;
2557 }
2558
2559 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2560 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_arl},
2561 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2562 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2563
2564 /* FIXME:
2565 * For state trackers other than OpenGL, we'll want to use
2566 * _RECIP_IEEE instead.
2567 */
2568 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2569
2570 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2571 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2572 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2573 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2574 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2575 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2576 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2577 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2578 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2579 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2580 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2581 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2582 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2583 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2584 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2585 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2586 /* gap */
2587 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2588 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2589 /* gap */
2590 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2591 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2592 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2593 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2594 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2595 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2596 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2597 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2598 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2599 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2600 /* gap */
2601 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2602 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2603 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2604 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2605 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2606 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2607 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2608 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2609 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2610 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2611 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2612 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2613 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2614 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2615 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2616 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2617 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2618 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2619 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2620 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2621 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2622 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2623 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2624 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2625 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2626 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2627 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2628 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2629 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2630 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2631 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2632 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2633 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2634 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2635 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2636 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2637 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2638 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2639 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2640 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2641 {TGSI_OPCODE_TXL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2642 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2643 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2644 /* gap */
2645 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2646 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2647 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2648 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2649 /* gap */
2650 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2651 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2652 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2653 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2654 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2655 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2656 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2657 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2658 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2659 /* gap */
2660 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2661 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2662 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2663 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2664 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2665 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2666 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2667 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2668 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2669 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2670 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2671 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2672 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2673 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2674 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2675 /* gap */
2676 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2677 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2678 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2679 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2680 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2681 /* gap */
2682 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2683 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2684 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2685 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2686 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2687 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2688 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2689 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2690 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2691 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2692 /* gap */
2693 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2694 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2695 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2696 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2697 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2698 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2699 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2700 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2701 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2702 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2703 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2704 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2705 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2706 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2707 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2708 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2709 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2710 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2711 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2712 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2713 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2714 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2715 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2716 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2717 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2718 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2719 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2720 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2721 };
2722
2723 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
2724 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2725 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2726 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2727 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
2728 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
2729 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2730 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2731 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2732 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2733 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2734 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2735 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2736 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2737 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2738 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2739 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2740 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2741 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2742 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2743 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2744 /* gap */
2745 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2746 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2747 /* gap */
2748 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2749 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2750 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2751 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2752 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2753 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2754 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2755 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2756 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2757 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2758 /* gap */
2759 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2760 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2761 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2762 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2763 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2764 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2765 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2766 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2767 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2768 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2769 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2770 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2771 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2772 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2773 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2774 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2775 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2776 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2777 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2778 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2779 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2780 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2781 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2782 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2783 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2784 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2785 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2786 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2787 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2788 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2789 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2790 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2791 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2792 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2793 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2794 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2795 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2796 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2797 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2798 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2799 {TGSI_OPCODE_TXL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2800 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2801 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2802 /* gap */
2803 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2804 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2805 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2806 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2807 /* gap */
2808 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2809 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2810 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2811 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2812 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2813 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2814 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2815 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2816 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2817 /* gap */
2818 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2819 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2820 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2821 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2822 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2823 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2824 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2825 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2826 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2827 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2828 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2829 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2830 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2831 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2832 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2833 /* gap */
2834 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2835 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2836 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2837 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2838 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2839 /* gap */
2840 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2841 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2842 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2843 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2844 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2845 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2846 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2847 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2848 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2849 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2850 /* gap */
2851 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2852 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2853 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2854 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2855 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2856 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2857 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2858 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2859 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2860 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2861 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2862 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2863 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2864 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2865 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2866 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2867 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2868 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2869 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2870 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2871 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2872 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2873 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2874 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2875 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2876 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2877 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2878 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2879 };