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r600g: DP4 also supports writemasking
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
37 {
38 struct r600_pipe_state *rstate = &shader->rstate;
39 struct r600_shader *rshader = &shader->shader;
40 unsigned spi_vs_out_id[10];
41 unsigned i, tmp;
42
43 /* clear previous register */
44 rstate->nregs = 0;
45
46 /* so far never got proper semantic id from tgsi */
47 /* FIXME better to move this in config things so they get emited
48 * only one time per cs
49 */
50 for (i = 0; i < 10; i++) {
51 spi_vs_out_id[i] = 0;
52 }
53 for (i = 0; i < 32; i++) {
54 tmp = i << ((i & 3) * 8);
55 spi_vs_out_id[i / 4] |= tmp;
56 }
57 for (i = 0; i < 10; i++) {
58 r600_pipe_state_add_reg(rstate,
59 R_028614_SPI_VS_OUT_ID_0 + i * 4,
60 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
61 }
62
63 r600_pipe_state_add_reg(rstate,
64 R_0286C4_SPI_VS_OUT_CONFIG,
65 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
66 0xFFFFFFFF, NULL);
67 r600_pipe_state_add_reg(rstate,
68 R_028868_SQ_PGM_RESOURCES_VS,
69 S_028868_NUM_GPRS(rshader->bc.ngpr) |
70 S_028868_STACK_SIZE(rshader->bc.nstack),
71 0xFFFFFFFF, NULL);
72 r600_pipe_state_add_reg(rstate,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS,
74 0x00000000, 0xFFFFFFFF, NULL);
75 r600_pipe_state_add_reg(rstate,
76 R_028858_SQ_PGM_START_VS,
77 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
78
79 r600_pipe_state_add_reg(rstate,
80 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
81 0xFFFFFFFF, NULL);
82
83 }
84
85 int r600_find_vs_semantic_index(struct r600_shader *vs,
86 struct r600_shader *ps, int id)
87 {
88 struct r600_shader_io *input = &ps->input[id];
89
90 for (int i = 0; i < vs->noutput; i++) {
91 if (input->name == vs->output[i].name &&
92 input->sid == vs->output[i].sid) {
93 return i - 1;
94 }
95 }
96 return 0;
97 }
98
99 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
100 {
101 struct r600_pipe_state *rstate = &shader->rstate;
102 struct r600_shader *rshader = &shader->shader;
103 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
104 int pos_index = -1, face_index = -1;
105
106 rstate->nregs = 0;
107
108 for (i = 0; i < rshader->ninput; i++) {
109 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
110 pos_index = i;
111 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
112 face_index = i;
113 }
114
115 for (i = 0; i < rshader->noutput; i++) {
116 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
117 r600_pipe_state_add_reg(rstate,
118 R_02880C_DB_SHADER_CONTROL,
119 S_02880C_Z_EXPORT_ENABLE(1),
120 S_02880C_Z_EXPORT_ENABLE(1), NULL);
121 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
122 r600_pipe_state_add_reg(rstate,
123 R_02880C_DB_SHADER_CONTROL,
124 S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
125 S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL);
126 }
127
128 exports_ps = 0;
129 num_cout = 0;
130 for (i = 0; i < rshader->noutput; i++) {
131 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
132 exports_ps |= 1;
133 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
134 num_cout++;
135 }
136 }
137 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
138 if (!exports_ps) {
139 /* always at least export 1 component per pixel */
140 exports_ps = 2;
141 }
142
143 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
144 S_0286CC_PERSP_GRADIENT_ENA(1);
145 spi_input_z = 0;
146 if (pos_index != -1) {
147 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
148 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
149 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
150 S_0286CC_BARYC_SAMPLE_CNTL(1));
151 spi_input_z |= 1;
152 }
153
154 spi_ps_in_control_1 = 0;
155 if (face_index != -1) {
156 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
157 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
158 }
159
160 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
161 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
162 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
163 r600_pipe_state_add_reg(rstate,
164 R_028840_SQ_PGM_START_PS,
165 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
166 r600_pipe_state_add_reg(rstate,
167 R_028850_SQ_PGM_RESOURCES_PS,
168 S_028868_NUM_GPRS(rshader->bc.ngpr) |
169 S_028868_STACK_SIZE(rshader->bc.nstack),
170 0xFFFFFFFF, NULL);
171 r600_pipe_state_add_reg(rstate,
172 R_028854_SQ_PGM_EXPORTS_PS,
173 exports_ps, 0xFFFFFFFF, NULL);
174 r600_pipe_state_add_reg(rstate,
175 R_0288CC_SQ_PGM_CF_OFFSET_PS,
176 0x00000000, 0xFFFFFFFF, NULL);
177
178 if (rshader->uses_kill) {
179 /* only set some bits here, the other bits are set in the dsa state */
180 r600_pipe_state_add_reg(rstate,
181 R_02880C_DB_SHADER_CONTROL,
182 S_02880C_KILL_ENABLE(1),
183 S_02880C_KILL_ENABLE(1), NULL);
184 }
185 r600_pipe_state_add_reg(rstate,
186 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
187 0xFFFFFFFF, NULL);
188 }
189
190 int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
191 {
192 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
193 struct r600_shader *rshader = &shader->shader;
194 void *ptr;
195
196 /* copy new shader */
197 if (shader->bo == NULL) {
198 shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0, 0);
199 if (shader->bo == NULL) {
200 return -ENOMEM;
201 }
202 ptr = r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
203 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
204 r600_bo_unmap(rctx->radeon, shader->bo);
205 }
206 /* build state */
207 switch (rshader->processor_type) {
208 case TGSI_PROCESSOR_VERTEX:
209 if (rshader->family >= CHIP_CEDAR) {
210 evergreen_pipe_shader_vs(ctx, shader);
211 } else {
212 r600_pipe_shader_vs(ctx, shader);
213 }
214 break;
215 case TGSI_PROCESSOR_FRAGMENT:
216 if (rshader->family >= CHIP_CEDAR) {
217 evergreen_pipe_shader_ps(ctx, shader);
218 } else {
219 r600_pipe_shader_ps(ctx, shader);
220 }
221 break;
222 default:
223 return -EINVAL;
224 }
225 return 0;
226 }
227
228 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
229 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
230 {
231 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
232 int r;
233
234 //fprintf(stderr, "--------------------------------------------------------------\n");
235 //tgsi_dump(tokens, 0);
236 shader->shader.family = r600_get_family(rctx->radeon);
237 r = r600_shader_from_tgsi(tokens, &shader->shader);
238 if (r) {
239 R600_ERR("translation from TGSI failed !\n");
240 return r;
241 }
242 r = r600_bc_build(&shader->shader.bc);
243 if (r) {
244 R600_ERR("building bytecode failed !\n");
245 return r;
246 }
247 //r600_bc_dump(&shader->shader.bc);
248 //fprintf(stderr, "______________________________________________________________\n");
249 return r600_pipe_shader(ctx, shader);
250 }
251
252 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
253 {
254 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
255
256 r600_bo_reference(rctx->radeon, &shader->bo, NULL);
257 r600_bc_clear(&shader->shader.bc);
258 }
259
260 /*
261 * tgsi -> r600 shader
262 */
263 struct r600_shader_tgsi_instruction;
264
265 struct r600_shader_ctx {
266 struct tgsi_shader_info info;
267 struct tgsi_parse_context parse;
268 const struct tgsi_token *tokens;
269 unsigned type;
270 unsigned file_offset[TGSI_FILE_COUNT];
271 unsigned temp_reg;
272 struct r600_shader_tgsi_instruction *inst_info;
273 struct r600_bc *bc;
274 struct r600_shader *shader;
275 u32 value[4];
276 u32 *literals;
277 u32 nliterals;
278 u32 max_driver_temp_used;
279 /* needed for evergreen interpolation */
280 boolean input_centroid;
281 boolean input_linear;
282 boolean input_perspective;
283 int num_interp_gpr;
284 };
285
286 struct r600_shader_tgsi_instruction {
287 unsigned tgsi_opcode;
288 unsigned is_op3;
289 unsigned r600_opcode;
290 int (*process)(struct r600_shader_ctx *ctx);
291 };
292
293 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
294 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
295
296 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
297 {
298 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
299 int j;
300
301 if (i->Instruction.NumDstRegs > 1) {
302 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
303 return -EINVAL;
304 }
305 if (i->Instruction.Predicate) {
306 R600_ERR("predicate unsupported\n");
307 return -EINVAL;
308 }
309 #if 0
310 if (i->Instruction.Label) {
311 R600_ERR("label unsupported\n");
312 return -EINVAL;
313 }
314 #endif
315 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
316 if (i->Src[j].Register.Dimension) {
317 R600_ERR("unsupported src %d (dimension %d)\n", j,
318 i->Src[j].Register.Dimension);
319 return -EINVAL;
320 }
321 }
322 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
323 if (i->Dst[j].Register.Dimension) {
324 R600_ERR("unsupported dst (dimension)\n");
325 return -EINVAL;
326 }
327 }
328 return 0;
329 }
330
331 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
332 {
333 int i, r;
334 struct r600_bc_alu alu;
335 int gpr = 0, base_chan = 0;
336 int ij_index = 0;
337
338 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
339 ij_index = 0;
340 if (ctx->shader->input[input].centroid)
341 ij_index++;
342 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
343 ij_index = 0;
344 /* if we have perspective add one */
345 if (ctx->input_perspective) {
346 ij_index++;
347 /* if we have perspective centroid */
348 if (ctx->input_centroid)
349 ij_index++;
350 }
351 if (ctx->shader->input[input].centroid)
352 ij_index++;
353 }
354
355 /* work out gpr and base_chan from index */
356 gpr = ij_index / 2;
357 base_chan = (2 * (ij_index % 2)) + 1;
358
359 for (i = 0; i < 8; i++) {
360 memset(&alu, 0, sizeof(struct r600_bc_alu));
361
362 if (i < 4)
363 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
364 else
365 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
366
367 if ((i > 1) && (i < 6)) {
368 alu.dst.sel = ctx->shader->input[input].gpr;
369 alu.dst.write = 1;
370 }
371
372 alu.dst.chan = i % 4;
373
374 alu.src[0].sel = gpr;
375 alu.src[0].chan = (base_chan - (i % 2));
376
377 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
378
379 alu.bank_swizzle_force = SQ_ALU_VEC_210;
380 if ((i % 4) == 3)
381 alu.last = 1;
382 r = r600_bc_add_alu(ctx->bc, &alu);
383 if (r)
384 return r;
385 }
386 return 0;
387 }
388
389
390 static int tgsi_declaration(struct r600_shader_ctx *ctx)
391 {
392 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
393 unsigned i;
394
395 switch (d->Declaration.File) {
396 case TGSI_FILE_INPUT:
397 i = ctx->shader->ninput++;
398 ctx->shader->input[i].name = d->Semantic.Name;
399 ctx->shader->input[i].sid = d->Semantic.Index;
400 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
401 ctx->shader->input[i].centroid = d->Declaration.Centroid;
402 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
403 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == CHIPREV_EVERGREEN) {
404 /* turn input into interpolate on EG */
405 if (ctx->shader->input[i].name != TGSI_SEMANTIC_POSITION) {
406 if (ctx->shader->input[i].interpolate > 0) {
407 ctx->shader->input[i].lds_pos = ctx->shader->nlds++;
408 evergreen_interp_alu(ctx, i);
409 }
410 }
411 }
412 break;
413 case TGSI_FILE_OUTPUT:
414 i = ctx->shader->noutput++;
415 ctx->shader->output[i].name = d->Semantic.Name;
416 ctx->shader->output[i].sid = d->Semantic.Index;
417 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
418 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
419 break;
420 case TGSI_FILE_CONSTANT:
421 case TGSI_FILE_TEMPORARY:
422 case TGSI_FILE_SAMPLER:
423 case TGSI_FILE_ADDRESS:
424 break;
425 default:
426 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
427 return -EINVAL;
428 }
429 return 0;
430 }
431
432 static int r600_get_temp(struct r600_shader_ctx *ctx)
433 {
434 return ctx->temp_reg + ctx->max_driver_temp_used++;
435 }
436
437 /*
438 * for evergreen we need to scan the shader to find the number of GPRs we need to
439 * reserve for interpolation.
440 *
441 * we need to know if we are going to emit
442 * any centroid inputs
443 * if perspective and linear are required
444 */
445 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
446 {
447 int i;
448 int num_baryc;
449
450 ctx->input_linear = FALSE;
451 ctx->input_perspective = FALSE;
452 ctx->input_centroid = FALSE;
453 ctx->num_interp_gpr = 1;
454
455 /* any centroid inputs */
456 for (i = 0; i < ctx->info.num_inputs; i++) {
457 /* skip position/face */
458 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
459 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
460 continue;
461 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
462 ctx->input_linear = TRUE;
463 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
464 ctx->input_perspective = TRUE;
465 if (ctx->info.input_centroid[i])
466 ctx->input_centroid = TRUE;
467 }
468
469 num_baryc = 0;
470 /* ignoring sample for now */
471 if (ctx->input_perspective)
472 num_baryc++;
473 if (ctx->input_linear)
474 num_baryc++;
475 if (ctx->input_centroid)
476 num_baryc *= 2;
477
478 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
479
480 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
481 return ctx->num_interp_gpr;
482 }
483
484 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
485 {
486 struct tgsi_full_immediate *immediate;
487 struct r600_shader_ctx ctx;
488 struct r600_bc_output output[32];
489 unsigned output_done, noutput;
490 unsigned opcode;
491 int i, r = 0, pos0;
492
493 ctx.bc = &shader->bc;
494 ctx.shader = shader;
495 r = r600_bc_init(ctx.bc, shader->family);
496 if (r)
497 return r;
498 ctx.tokens = tokens;
499 tgsi_scan_shader(tokens, &ctx.info);
500 tgsi_parse_init(&ctx.parse, tokens);
501 ctx.type = ctx.parse.FullHeader.Processor.Processor;
502 shader->processor_type = ctx.type;
503 ctx.bc->type = shader->processor_type;
504
505 /* register allocations */
506 /* Values [0,127] correspond to GPR[0..127].
507 * Values [128,159] correspond to constant buffer bank 0
508 * Values [160,191] correspond to constant buffer bank 1
509 * Values [256,511] correspond to cfile constants c[0..255].
510 * Other special values are shown in the list below.
511 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
512 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
513 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
514 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
515 * 248 SQ_ALU_SRC_0: special constant 0.0.
516 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
517 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
518 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
519 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
520 * 253 SQ_ALU_SRC_LITERAL: literal constant.
521 * 254 SQ_ALU_SRC_PV: previous vector result.
522 * 255 SQ_ALU_SRC_PS: previous scalar result.
523 */
524 for (i = 0; i < TGSI_FILE_COUNT; i++) {
525 ctx.file_offset[i] = 0;
526 }
527 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
528 ctx.file_offset[TGSI_FILE_INPUT] = 1;
529 if (ctx.bc->chiprev == CHIPREV_EVERGREEN) {
530 r600_bc_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
531 } else {
532 r600_bc_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
533 }
534 }
535 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev == CHIPREV_EVERGREEN) {
536 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
537 }
538 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
539 ctx.info.file_count[TGSI_FILE_INPUT];
540 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
541 ctx.info.file_count[TGSI_FILE_OUTPUT];
542
543 ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
544
545 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
546 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
547 ctx.info.file_count[TGSI_FILE_TEMPORARY];
548
549 ctx.nliterals = 0;
550 ctx.literals = NULL;
551
552 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
553 tgsi_parse_token(&ctx.parse);
554 switch (ctx.parse.FullToken.Token.Type) {
555 case TGSI_TOKEN_TYPE_IMMEDIATE:
556 immediate = &ctx.parse.FullToken.FullImmediate;
557 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
558 if(ctx.literals == NULL) {
559 r = -ENOMEM;
560 goto out_err;
561 }
562 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
563 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
564 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
565 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
566 ctx.nliterals++;
567 break;
568 case TGSI_TOKEN_TYPE_DECLARATION:
569 r = tgsi_declaration(&ctx);
570 if (r)
571 goto out_err;
572 break;
573 case TGSI_TOKEN_TYPE_INSTRUCTION:
574 r = tgsi_is_supported(&ctx);
575 if (r)
576 goto out_err;
577 ctx.max_driver_temp_used = 0;
578 /* reserve first tmp for everyone */
579 r600_get_temp(&ctx);
580 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
581 if (ctx.bc->chiprev == CHIPREV_EVERGREEN)
582 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
583 else
584 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
585 r = ctx.inst_info->process(&ctx);
586 if (r)
587 goto out_err;
588 r = r600_bc_add_literal(ctx.bc, ctx.value);
589 if (r)
590 goto out_err;
591 break;
592 default:
593 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
594 r = -EINVAL;
595 goto out_err;
596 }
597 }
598 /* export output */
599 noutput = shader->noutput;
600 for (i = 0, pos0 = 0; i < noutput; i++) {
601 memset(&output[i], 0, sizeof(struct r600_bc_output));
602 output[i].gpr = shader->output[i].gpr;
603 output[i].elem_size = 3;
604 output[i].swizzle_x = 0;
605 output[i].swizzle_y = 1;
606 output[i].swizzle_z = 2;
607 output[i].swizzle_w = 3;
608 output[i].barrier = 1;
609 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
610 output[i].array_base = i - pos0;
611 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
612 switch (ctx.type) {
613 case TGSI_PROCESSOR_VERTEX:
614 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
615 output[i].array_base = 60;
616 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
617 /* position doesn't count in array_base */
618 pos0++;
619 }
620 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
621 output[i].array_base = 61;
622 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
623 /* position doesn't count in array_base */
624 pos0++;
625 }
626 break;
627 case TGSI_PROCESSOR_FRAGMENT:
628 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
629 output[i].array_base = shader->output[i].sid;
630 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
631 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
632 output[i].array_base = 61;
633 output[i].swizzle_x = 2;
634 output[i].swizzle_y = 7;
635 output[i].swizzle_z = output[i].swizzle_w = 7;
636 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
637 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
638 output[i].array_base = 61;
639 output[i].swizzle_x = 7;
640 output[i].swizzle_y = 1;
641 output[i].swizzle_z = output[i].swizzle_w = 7;
642 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
643 } else {
644 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
645 r = -EINVAL;
646 goto out_err;
647 }
648 break;
649 default:
650 R600_ERR("unsupported processor type %d\n", ctx.type);
651 r = -EINVAL;
652 goto out_err;
653 }
654 }
655 /* add fake param output for vertex shader if no param is exported */
656 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
657 for (i = 0, pos0 = 0; i < noutput; i++) {
658 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
659 pos0 = 1;
660 break;
661 }
662 }
663 if (!pos0) {
664 memset(&output[i], 0, sizeof(struct r600_bc_output));
665 output[i].gpr = 0;
666 output[i].elem_size = 3;
667 output[i].swizzle_x = 0;
668 output[i].swizzle_y = 1;
669 output[i].swizzle_z = 2;
670 output[i].swizzle_w = 3;
671 output[i].barrier = 1;
672 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
673 output[i].array_base = 0;
674 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
675 noutput++;
676 }
677 }
678 /* add fake pixel export */
679 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
680 memset(&output[0], 0, sizeof(struct r600_bc_output));
681 output[0].gpr = 0;
682 output[0].elem_size = 3;
683 output[0].swizzle_x = 7;
684 output[0].swizzle_y = 7;
685 output[0].swizzle_z = 7;
686 output[0].swizzle_w = 7;
687 output[0].barrier = 1;
688 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
689 output[0].array_base = 0;
690 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
691 noutput++;
692 }
693 /* set export done on last export of each type */
694 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
695 if (i == (noutput - 1)) {
696 output[i].end_of_program = 1;
697 }
698 if (!(output_done & (1 << output[i].type))) {
699 output_done |= (1 << output[i].type);
700 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
701 }
702 }
703 /* add output to bytecode */
704 for (i = 0; i < noutput; i++) {
705 r = r600_bc_add_output(ctx.bc, &output[i]);
706 if (r)
707 goto out_err;
708 }
709 free(ctx.literals);
710 tgsi_parse_free(&ctx.parse);
711 return 0;
712 out_err:
713 free(ctx.literals);
714 tgsi_parse_free(&ctx.parse);
715 return r;
716 }
717
718 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
719 {
720 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
721 return -EINVAL;
722 }
723
724 static int tgsi_end(struct r600_shader_ctx *ctx)
725 {
726 return 0;
727 }
728
729 static int tgsi_src(struct r600_shader_ctx *ctx,
730 const struct tgsi_full_src_register *tgsi_src,
731 struct r600_bc_alu_src *r600_src)
732 {
733 int index;
734 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
735 r600_src->sel = tgsi_src->Register.Index;
736 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
737 r600_src->sel = 0;
738 index = tgsi_src->Register.Index;
739 ctx->value[0] = ctx->literals[index * 4 + 0];
740 ctx->value[1] = ctx->literals[index * 4 + 1];
741 ctx->value[2] = ctx->literals[index * 4 + 2];
742 ctx->value[3] = ctx->literals[index * 4 + 3];
743 }
744 if (tgsi_src->Register.Indirect)
745 r600_src->rel = V_SQ_REL_RELATIVE;
746 r600_src->neg = tgsi_src->Register.Negate;
747 r600_src->abs = tgsi_src->Register.Absolute;
748 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
749 return 0;
750 }
751
752 static int tgsi_dst(struct r600_shader_ctx *ctx,
753 const struct tgsi_full_dst_register *tgsi_dst,
754 unsigned swizzle,
755 struct r600_bc_alu_dst *r600_dst)
756 {
757 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
758
759 r600_dst->sel = tgsi_dst->Register.Index;
760 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
761 r600_dst->chan = swizzle;
762 r600_dst->write = 1;
763 if (tgsi_dst->Register.Indirect)
764 r600_dst->rel = V_SQ_REL_RELATIVE;
765 if (inst->Instruction.Saturate) {
766 r600_dst->clamp = 1;
767 }
768 return 0;
769 }
770
771 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
772 {
773 switch (swizzle) {
774 case 0:
775 return tgsi_src->Register.SwizzleX;
776 case 1:
777 return tgsi_src->Register.SwizzleY;
778 case 2:
779 return tgsi_src->Register.SwizzleZ;
780 case 3:
781 return tgsi_src->Register.SwizzleW;
782 default:
783 return 0;
784 }
785 }
786
787 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
788 {
789 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
790 struct r600_bc_alu alu;
791 int i, j, k, nconst, r;
792
793 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
794 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
795 nconst++;
796 }
797 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
798 if (r) {
799 return r;
800 }
801 }
802 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
803 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
804 int treg = r600_get_temp(ctx);
805 for (k = 0; k < 4; k++) {
806 memset(&alu, 0, sizeof(struct r600_bc_alu));
807 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
808 alu.src[0].sel = r600_src[i].sel;
809 alu.src[0].chan = k;
810 alu.src[0].rel = r600_src[i].rel;
811 alu.dst.sel = treg;
812 alu.dst.chan = k;
813 alu.dst.write = 1;
814 if (k == 3)
815 alu.last = 1;
816 r = r600_bc_add_alu(ctx->bc, &alu);
817 if (r)
818 return r;
819 }
820 r600_src[i].sel = treg;
821 r600_src[i].rel =0;
822 j--;
823 }
824 }
825 return 0;
826 }
827
828 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
829 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
830 {
831 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
832 struct r600_bc_alu alu;
833 int i, j, k, nliteral, r;
834
835 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
836 if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
837 nliteral++;
838 }
839 }
840 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
841 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
842 int treg = r600_get_temp(ctx);
843 for (k = 0; k < 4; k++) {
844 memset(&alu, 0, sizeof(struct r600_bc_alu));
845 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
846 alu.src[0].sel = r600_src[i].sel;
847 alu.src[0].chan = k;
848 alu.dst.sel = treg;
849 alu.dst.chan = k;
850 alu.dst.write = 1;
851 if (k == 3)
852 alu.last = 1;
853 r = r600_bc_add_alu(ctx->bc, &alu);
854 if (r)
855 return r;
856 }
857 r = r600_bc_add_literal(ctx->bc, &ctx->literals[inst->Src[i].Register.Index * 4]);
858 if (r)
859 return r;
860 r600_src[i].sel = treg;
861 j--;
862 }
863 }
864 return 0;
865 }
866
867 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
868 {
869 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
870 struct r600_bc_alu_src r600_src[3];
871 struct r600_bc_alu alu;
872 int i, j, r;
873 int lasti = 0;
874
875 for (i = 0; i < 4; i++) {
876 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
877 lasti = i;
878 }
879 }
880
881 r = tgsi_split_constant(ctx, r600_src);
882 if (r)
883 return r;
884 r = tgsi_split_literal_constant(ctx, r600_src);
885 if (r)
886 return r;
887 for (i = 0; i < lasti + 1; i++) {
888 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
889 continue;
890
891 memset(&alu, 0, sizeof(struct r600_bc_alu));
892 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
893 if (r)
894 return r;
895
896 alu.inst = ctx->inst_info->r600_opcode;
897 if (!swap) {
898 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
899 alu.src[j] = r600_src[j];
900 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
901 }
902 } else {
903 alu.src[0] = r600_src[1];
904 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
905
906 alu.src[1] = r600_src[0];
907 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
908 }
909 /* handle some special cases */
910 switch (ctx->inst_info->tgsi_opcode) {
911 case TGSI_OPCODE_SUB:
912 alu.src[1].neg = 1;
913 break;
914 case TGSI_OPCODE_ABS:
915 alu.src[0].abs = 1;
916 break;
917 default:
918 break;
919 }
920 if (i == lasti) {
921 alu.last = 1;
922 }
923 r = r600_bc_add_alu(ctx->bc, &alu);
924 if (r)
925 return r;
926 }
927 return 0;
928 }
929
930 static int tgsi_op2(struct r600_shader_ctx *ctx)
931 {
932 return tgsi_op2_s(ctx, 0);
933 }
934
935 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
936 {
937 return tgsi_op2_s(ctx, 1);
938 }
939
940 /*
941 * r600 - trunc to -PI..PI range
942 * r700 - normalize by dividing by 2PI
943 * see fdo bug 27901
944 */
945 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
946 struct r600_bc_alu_src r600_src[3])
947 {
948 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
949 int r;
950 uint32_t lit_vals[4];
951 struct r600_bc_alu alu;
952
953 memset(lit_vals, 0, 4*4);
954 r = tgsi_split_constant(ctx, r600_src);
955 if (r)
956 return r;
957 r = tgsi_split_literal_constant(ctx, r600_src);
958 if (r)
959 return r;
960
961 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
962 lit_vals[1] = fui(0.5f);
963
964 memset(&alu, 0, sizeof(struct r600_bc_alu));
965 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
966 alu.is_op3 = 1;
967
968 alu.dst.chan = 0;
969 alu.dst.sel = ctx->temp_reg;
970 alu.dst.write = 1;
971
972 alu.src[0] = r600_src[0];
973 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
974
975 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
976 alu.src[1].chan = 0;
977 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
978 alu.src[2].chan = 1;
979 alu.last = 1;
980 r = r600_bc_add_alu(ctx->bc, &alu);
981 if (r)
982 return r;
983 r = r600_bc_add_literal(ctx->bc, lit_vals);
984 if (r)
985 return r;
986
987 memset(&alu, 0, sizeof(struct r600_bc_alu));
988 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
989
990 alu.dst.chan = 0;
991 alu.dst.sel = ctx->temp_reg;
992 alu.dst.write = 1;
993
994 alu.src[0].sel = ctx->temp_reg;
995 alu.src[0].chan = 0;
996 alu.last = 1;
997 r = r600_bc_add_alu(ctx->bc, &alu);
998 if (r)
999 return r;
1000
1001 if (ctx->bc->chiprev == CHIPREV_R600) {
1002 lit_vals[0] = fui(3.1415926535897f * 2.0f);
1003 lit_vals[1] = fui(-3.1415926535897f);
1004 } else {
1005 lit_vals[0] = fui(1.0f);
1006 lit_vals[1] = fui(-0.5f);
1007 }
1008
1009 memset(&alu, 0, sizeof(struct r600_bc_alu));
1010 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1011 alu.is_op3 = 1;
1012
1013 alu.dst.chan = 0;
1014 alu.dst.sel = ctx->temp_reg;
1015 alu.dst.write = 1;
1016
1017 alu.src[0].sel = ctx->temp_reg;
1018 alu.src[0].chan = 0;
1019
1020 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1021 alu.src[1].chan = 0;
1022 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1023 alu.src[2].chan = 1;
1024 alu.last = 1;
1025 r = r600_bc_add_alu(ctx->bc, &alu);
1026 if (r)
1027 return r;
1028 r = r600_bc_add_literal(ctx->bc, lit_vals);
1029 if (r)
1030 return r;
1031 return 0;
1032 }
1033
1034 static int tgsi_trig(struct r600_shader_ctx *ctx)
1035 {
1036 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1037 struct r600_bc_alu_src r600_src[3];
1038 struct r600_bc_alu alu;
1039 int i, r;
1040 int lasti = 0;
1041
1042 r = tgsi_setup_trig(ctx, r600_src);
1043 if (r)
1044 return r;
1045
1046 memset(&alu, 0, sizeof(struct r600_bc_alu));
1047 alu.inst = ctx->inst_info->r600_opcode;
1048 alu.dst.chan = 0;
1049 alu.dst.sel = ctx->temp_reg;
1050 alu.dst.write = 1;
1051
1052 alu.src[0].sel = ctx->temp_reg;
1053 alu.src[0].chan = 0;
1054 alu.last = 1;
1055 r = r600_bc_add_alu(ctx->bc, &alu);
1056 if (r)
1057 return r;
1058
1059 /* replicate result */
1060 for (i = 0; i < 4; i++) {
1061 if (inst->Dst[0].Register.WriteMask & (1 << i))
1062 lasti = i;
1063 }
1064 for (i = 0; i < lasti + 1; i++) {
1065 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1066 continue;
1067
1068 memset(&alu, 0, sizeof(struct r600_bc_alu));
1069 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1070
1071 alu.src[0].sel = ctx->temp_reg;
1072 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1073 if (r)
1074 return r;
1075 if (i == lasti)
1076 alu.last = 1;
1077 r = r600_bc_add_alu(ctx->bc, &alu);
1078 if (r)
1079 return r;
1080 }
1081 return 0;
1082 }
1083
1084 static int tgsi_scs(struct r600_shader_ctx *ctx)
1085 {
1086 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1087 struct r600_bc_alu_src r600_src[3];
1088 struct r600_bc_alu alu;
1089 int r;
1090
1091 /* We'll only need the trig stuff if we are going to write to the
1092 * X or Y components of the destination vector.
1093 */
1094 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1095 r = tgsi_setup_trig(ctx, r600_src);
1096 if (r)
1097 return r;
1098 }
1099
1100 /* dst.x = COS */
1101 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1102 memset(&alu, 0, sizeof(struct r600_bc_alu));
1103 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1104 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1105 if (r)
1106 return r;
1107
1108 alu.src[0].sel = ctx->temp_reg;
1109 alu.src[0].chan = 0;
1110 alu.last = 1;
1111 r = r600_bc_add_alu(ctx->bc, &alu);
1112 if (r)
1113 return r;
1114 }
1115
1116 /* dst.y = SIN */
1117 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1118 memset(&alu, 0, sizeof(struct r600_bc_alu));
1119 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1120 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1121 if (r)
1122 return r;
1123
1124 alu.src[0].sel = ctx->temp_reg;
1125 alu.src[0].chan = 0;
1126 alu.last = 1;
1127 r = r600_bc_add_alu(ctx->bc, &alu);
1128 if (r)
1129 return r;
1130 }
1131
1132 /* dst.z = 0.0; */
1133 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1134 memset(&alu, 0, sizeof(struct r600_bc_alu));
1135
1136 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1137
1138 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1139 if (r)
1140 return r;
1141
1142 alu.src[0].sel = V_SQ_ALU_SRC_0;
1143 alu.src[0].chan = 0;
1144
1145 alu.last = 1;
1146
1147 r = r600_bc_add_alu(ctx->bc, &alu);
1148 if (r)
1149 return r;
1150
1151 r = r600_bc_add_literal(ctx->bc, ctx->value);
1152 if (r)
1153 return r;
1154 }
1155
1156 /* dst.w = 1.0; */
1157 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1158 memset(&alu, 0, sizeof(struct r600_bc_alu));
1159
1160 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1161
1162 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1163 if (r)
1164 return r;
1165
1166 alu.src[0].sel = V_SQ_ALU_SRC_1;
1167 alu.src[0].chan = 0;
1168
1169 alu.last = 1;
1170
1171 r = r600_bc_add_alu(ctx->bc, &alu);
1172 if (r)
1173 return r;
1174
1175 r = r600_bc_add_literal(ctx->bc, ctx->value);
1176 if (r)
1177 return r;
1178 }
1179
1180 return 0;
1181 }
1182
1183 static int tgsi_kill(struct r600_shader_ctx *ctx)
1184 {
1185 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1186 struct r600_bc_alu alu;
1187 int i, r;
1188
1189 for (i = 0; i < 4; i++) {
1190 memset(&alu, 0, sizeof(struct r600_bc_alu));
1191 alu.inst = ctx->inst_info->r600_opcode;
1192
1193 alu.dst.chan = i;
1194
1195 alu.src[0].sel = V_SQ_ALU_SRC_0;
1196
1197 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1198 alu.src[1].sel = V_SQ_ALU_SRC_1;
1199 alu.src[1].neg = 1;
1200 } else {
1201 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1202 if (r)
1203 return r;
1204 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1205 }
1206 if (i == 3) {
1207 alu.last = 1;
1208 }
1209 r = r600_bc_add_alu(ctx->bc, &alu);
1210 if (r)
1211 return r;
1212 }
1213 r = r600_bc_add_literal(ctx->bc, ctx->value);
1214 if (r)
1215 return r;
1216
1217 /* kill must be last in ALU */
1218 ctx->bc->force_add_cf = 1;
1219 ctx->shader->uses_kill = TRUE;
1220 return 0;
1221 }
1222
1223 static int tgsi_lit(struct r600_shader_ctx *ctx)
1224 {
1225 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1226 struct r600_bc_alu alu;
1227 struct r600_bc_alu_src r600_src[3];
1228 int r;
1229
1230 r = tgsi_split_constant(ctx, r600_src);
1231 if (r)
1232 return r;
1233 r = tgsi_split_literal_constant(ctx, r600_src);
1234 if (r)
1235 return r;
1236
1237 /* dst.x, <- 1.0 */
1238 memset(&alu, 0, sizeof(struct r600_bc_alu));
1239 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1240 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1241 alu.src[0].chan = 0;
1242 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1243 if (r)
1244 return r;
1245 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1246 r = r600_bc_add_alu(ctx->bc, &alu);
1247 if (r)
1248 return r;
1249
1250 /* dst.y = max(src.x, 0.0) */
1251 memset(&alu, 0, sizeof(struct r600_bc_alu));
1252 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1253 alu.src[0] = r600_src[0];
1254 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1255 alu.src[1].chan = 0;
1256 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1257 if (r)
1258 return r;
1259 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1260 r = r600_bc_add_alu(ctx->bc, &alu);
1261 if (r)
1262 return r;
1263
1264 /* dst.w, <- 1.0 */
1265 memset(&alu, 0, sizeof(struct r600_bc_alu));
1266 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1267 alu.src[0].sel = V_SQ_ALU_SRC_1;
1268 alu.src[0].chan = 0;
1269 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1270 if (r)
1271 return r;
1272 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1273 alu.last = 1;
1274 r = r600_bc_add_alu(ctx->bc, &alu);
1275 if (r)
1276 return r;
1277
1278 r = r600_bc_add_literal(ctx->bc, ctx->value);
1279 if (r)
1280 return r;
1281
1282 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1283 {
1284 int chan;
1285 int sel;
1286
1287 /* dst.z = log(src.y) */
1288 memset(&alu, 0, sizeof(struct r600_bc_alu));
1289 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1290 alu.src[0] = r600_src[0];
1291 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1292 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1293 if (r)
1294 return r;
1295 alu.last = 1;
1296 r = r600_bc_add_alu(ctx->bc, &alu);
1297 if (r)
1298 return r;
1299
1300 r = r600_bc_add_literal(ctx->bc, ctx->value);
1301 if (r)
1302 return r;
1303
1304 chan = alu.dst.chan;
1305 sel = alu.dst.sel;
1306
1307 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1308 memset(&alu, 0, sizeof(struct r600_bc_alu));
1309 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1310 alu.src[0] = r600_src[0];
1311 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1312 alu.src[1].sel = sel;
1313 alu.src[1].chan = chan;
1314
1315 alu.src[2] = r600_src[0];
1316 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1317 alu.dst.sel = ctx->temp_reg;
1318 alu.dst.chan = 0;
1319 alu.dst.write = 1;
1320 alu.is_op3 = 1;
1321 alu.last = 1;
1322 r = r600_bc_add_alu(ctx->bc, &alu);
1323 if (r)
1324 return r;
1325
1326 r = r600_bc_add_literal(ctx->bc, ctx->value);
1327 if (r)
1328 return r;
1329 /* dst.z = exp(tmp.x) */
1330 memset(&alu, 0, sizeof(struct r600_bc_alu));
1331 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1332 alu.src[0].sel = ctx->temp_reg;
1333 alu.src[0].chan = 0;
1334 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1335 if (r)
1336 return r;
1337 alu.last = 1;
1338 r = r600_bc_add_alu(ctx->bc, &alu);
1339 if (r)
1340 return r;
1341 }
1342 return 0;
1343 }
1344
1345 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1346 {
1347 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1348 struct r600_bc_alu alu;
1349 int i, r;
1350
1351 memset(&alu, 0, sizeof(struct r600_bc_alu));
1352
1353 /* FIXME:
1354 * For state trackers other than OpenGL, we'll want to use
1355 * _RECIPSQRT_IEEE instead.
1356 */
1357 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1358
1359 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1360 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1361 if (r)
1362 return r;
1363 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1364 alu.src[i].abs = 1;
1365 }
1366 alu.dst.sel = ctx->temp_reg;
1367 alu.dst.write = 1;
1368 alu.last = 1;
1369 r = r600_bc_add_alu(ctx->bc, &alu);
1370 if (r)
1371 return r;
1372 r = r600_bc_add_literal(ctx->bc, ctx->value);
1373 if (r)
1374 return r;
1375 /* replicate result */
1376 return tgsi_helper_tempx_replicate(ctx);
1377 }
1378
1379 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1380 {
1381 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1382 struct r600_bc_alu alu;
1383 int i, r;
1384
1385 for (i = 0; i < 4; i++) {
1386 memset(&alu, 0, sizeof(struct r600_bc_alu));
1387 alu.src[0].sel = ctx->temp_reg;
1388 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1389 alu.dst.chan = i;
1390 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1391 if (r)
1392 return r;
1393 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1394 if (i == 3)
1395 alu.last = 1;
1396 r = r600_bc_add_alu(ctx->bc, &alu);
1397 if (r)
1398 return r;
1399 }
1400 return 0;
1401 }
1402
1403 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1404 {
1405 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1406 struct r600_bc_alu alu;
1407 int i, r;
1408
1409 memset(&alu, 0, sizeof(struct r600_bc_alu));
1410 alu.inst = ctx->inst_info->r600_opcode;
1411 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1412 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1413 if (r)
1414 return r;
1415 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1416 }
1417 alu.dst.sel = ctx->temp_reg;
1418 alu.dst.write = 1;
1419 alu.last = 1;
1420 r = r600_bc_add_alu(ctx->bc, &alu);
1421 if (r)
1422 return r;
1423 r = r600_bc_add_literal(ctx->bc, ctx->value);
1424 if (r)
1425 return r;
1426 /* replicate result */
1427 return tgsi_helper_tempx_replicate(ctx);
1428 }
1429
1430 static int tgsi_pow(struct r600_shader_ctx *ctx)
1431 {
1432 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1433 struct r600_bc_alu alu;
1434 int r;
1435
1436 /* LOG2(a) */
1437 memset(&alu, 0, sizeof(struct r600_bc_alu));
1438 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1439 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1440 if (r)
1441 return r;
1442 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1443 alu.dst.sel = ctx->temp_reg;
1444 alu.dst.write = 1;
1445 alu.last = 1;
1446 r = r600_bc_add_alu(ctx->bc, &alu);
1447 if (r)
1448 return r;
1449 r = r600_bc_add_literal(ctx->bc,ctx->value);
1450 if (r)
1451 return r;
1452 /* b * LOG2(a) */
1453 memset(&alu, 0, sizeof(struct r600_bc_alu));
1454 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE);
1455 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1456 if (r)
1457 return r;
1458 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1459 alu.src[1].sel = ctx->temp_reg;
1460 alu.dst.sel = ctx->temp_reg;
1461 alu.dst.write = 1;
1462 alu.last = 1;
1463 r = r600_bc_add_alu(ctx->bc, &alu);
1464 if (r)
1465 return r;
1466 r = r600_bc_add_literal(ctx->bc,ctx->value);
1467 if (r)
1468 return r;
1469 /* POW(a,b) = EXP2(b * LOG2(a))*/
1470 memset(&alu, 0, sizeof(struct r600_bc_alu));
1471 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1472 alu.src[0].sel = ctx->temp_reg;
1473 alu.dst.sel = ctx->temp_reg;
1474 alu.dst.write = 1;
1475 alu.last = 1;
1476 r = r600_bc_add_alu(ctx->bc, &alu);
1477 if (r)
1478 return r;
1479 r = r600_bc_add_literal(ctx->bc,ctx->value);
1480 if (r)
1481 return r;
1482 return tgsi_helper_tempx_replicate(ctx);
1483 }
1484
1485 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1486 {
1487 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1488 struct r600_bc_alu alu;
1489 struct r600_bc_alu_src r600_src[3];
1490 int i, r;
1491
1492 r = tgsi_split_constant(ctx, r600_src);
1493 if (r)
1494 return r;
1495 r = tgsi_split_literal_constant(ctx, r600_src);
1496 if (r)
1497 return r;
1498
1499 /* tmp = (src > 0 ? 1 : src) */
1500 for (i = 0; i < 4; i++) {
1501 memset(&alu, 0, sizeof(struct r600_bc_alu));
1502 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1503 alu.is_op3 = 1;
1504
1505 alu.dst.sel = ctx->temp_reg;
1506 alu.dst.chan = i;
1507
1508 alu.src[0] = r600_src[0];
1509 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1510
1511 alu.src[1].sel = V_SQ_ALU_SRC_1;
1512
1513 alu.src[2] = r600_src[0];
1514 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1515 if (i == 3)
1516 alu.last = 1;
1517 r = r600_bc_add_alu(ctx->bc, &alu);
1518 if (r)
1519 return r;
1520 }
1521 r = r600_bc_add_literal(ctx->bc, ctx->value);
1522 if (r)
1523 return r;
1524
1525 /* dst = (-tmp > 0 ? -1 : tmp) */
1526 for (i = 0; i < 4; i++) {
1527 memset(&alu, 0, sizeof(struct r600_bc_alu));
1528 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1529 alu.is_op3 = 1;
1530 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1531 if (r)
1532 return r;
1533
1534 alu.src[0].sel = ctx->temp_reg;
1535 alu.src[0].chan = i;
1536 alu.src[0].neg = 1;
1537
1538 alu.src[1].sel = V_SQ_ALU_SRC_1;
1539 alu.src[1].neg = 1;
1540
1541 alu.src[2].sel = ctx->temp_reg;
1542 alu.src[2].chan = i;
1543
1544 if (i == 3)
1545 alu.last = 1;
1546 r = r600_bc_add_alu(ctx->bc, &alu);
1547 if (r)
1548 return r;
1549 }
1550 return 0;
1551 }
1552
1553 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1554 {
1555 struct r600_bc_alu alu;
1556 int i, r;
1557
1558 r = r600_bc_add_literal(ctx->bc, ctx->value);
1559 if (r)
1560 return r;
1561 for (i = 0; i < 4; i++) {
1562 memset(&alu, 0, sizeof(struct r600_bc_alu));
1563 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1564 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1565 alu.dst.chan = i;
1566 } else {
1567 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1568 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1569 if (r)
1570 return r;
1571 alu.src[0].sel = ctx->temp_reg;
1572 alu.src[0].chan = i;
1573 }
1574 if (i == 3) {
1575 alu.last = 1;
1576 }
1577 r = r600_bc_add_alu(ctx->bc, &alu);
1578 if (r)
1579 return r;
1580 }
1581 return 0;
1582 }
1583
1584 static int tgsi_op3(struct r600_shader_ctx *ctx)
1585 {
1586 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1587 struct r600_bc_alu_src r600_src[3];
1588 struct r600_bc_alu alu;
1589 int i, j, r;
1590 int lasti = 0;
1591
1592 for (i = 0; i < 4; i++) {
1593 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
1594 lasti = i;
1595 }
1596 }
1597
1598 r = tgsi_split_constant(ctx, r600_src);
1599 if (r)
1600 return r;
1601 r = tgsi_split_literal_constant(ctx, r600_src);
1602 if (r)
1603 return r;
1604 for (i = 0; i < lasti + 1; i++) {
1605 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1606 continue;
1607
1608 memset(&alu, 0, sizeof(struct r600_bc_alu));
1609 alu.inst = ctx->inst_info->r600_opcode;
1610 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1611 alu.src[j] = r600_src[j];
1612 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1613 }
1614
1615 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1616 if (r)
1617 return r;
1618
1619 alu.dst.chan = i;
1620 alu.dst.write = 1;
1621 alu.is_op3 = 1;
1622 if (i == lasti) {
1623 alu.last = 1;
1624 }
1625 r = r600_bc_add_alu(ctx->bc, &alu);
1626 if (r)
1627 return r;
1628 }
1629 return 0;
1630 }
1631
1632 static int tgsi_dp(struct r600_shader_ctx *ctx)
1633 {
1634 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1635 struct r600_bc_alu_src r600_src[3];
1636 struct r600_bc_alu alu;
1637 int i, j, r;
1638
1639 r = tgsi_split_constant(ctx, r600_src);
1640 if (r)
1641 return r;
1642 r = tgsi_split_literal_constant(ctx, r600_src);
1643 if (r)
1644 return r;
1645 for (i = 0; i < 4; i++) {
1646 memset(&alu, 0, sizeof(struct r600_bc_alu));
1647 alu.inst = ctx->inst_info->r600_opcode;
1648 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1649 alu.src[j] = r600_src[j];
1650 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1651 }
1652
1653 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1654 if (r)
1655 return r;
1656
1657 alu.dst.chan = i;
1658 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1659 /* handle some special cases */
1660 switch (ctx->inst_info->tgsi_opcode) {
1661 case TGSI_OPCODE_DP2:
1662 if (i > 1) {
1663 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1664 alu.src[0].chan = alu.src[1].chan = 0;
1665 }
1666 break;
1667 case TGSI_OPCODE_DP3:
1668 if (i > 2) {
1669 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1670 alu.src[0].chan = alu.src[1].chan = 0;
1671 }
1672 break;
1673 case TGSI_OPCODE_DPH:
1674 if (i == 3) {
1675 alu.src[0].sel = V_SQ_ALU_SRC_1;
1676 alu.src[0].chan = 0;
1677 alu.src[0].neg = 0;
1678 }
1679 break;
1680 default:
1681 break;
1682 }
1683 if (i == 3) {
1684 alu.last = 1;
1685 }
1686 r = r600_bc_add_alu(ctx->bc, &alu);
1687 if (r)
1688 return r;
1689 }
1690 return 0;
1691 }
1692
1693 static int tgsi_tex(struct r600_shader_ctx *ctx)
1694 {
1695 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1696 struct r600_bc_tex tex;
1697 struct r600_bc_alu alu;
1698 unsigned src_gpr;
1699 int r, i;
1700 int opcode;
1701 boolean src_not_temp =
1702 inst->Src[0].Register.File != TGSI_FILE_TEMPORARY &&
1703 inst->Src[0].Register.File != TGSI_FILE_INPUT;
1704 uint32_t lit_vals[4];
1705
1706 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1707
1708 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1709 /* Add perspective divide */
1710 memset(&alu, 0, sizeof(struct r600_bc_alu));
1711 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1712 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1713 if (r)
1714 return r;
1715
1716 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1717 alu.dst.sel = ctx->temp_reg;
1718 alu.dst.chan = 3;
1719 alu.last = 1;
1720 alu.dst.write = 1;
1721 r = r600_bc_add_alu(ctx->bc, &alu);
1722 if (r)
1723 return r;
1724
1725 for (i = 0; i < 3; i++) {
1726 memset(&alu, 0, sizeof(struct r600_bc_alu));
1727 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1728 alu.src[0].sel = ctx->temp_reg;
1729 alu.src[0].chan = 3;
1730 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1731 if (r)
1732 return r;
1733 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1734 alu.dst.sel = ctx->temp_reg;
1735 alu.dst.chan = i;
1736 alu.dst.write = 1;
1737 r = r600_bc_add_alu(ctx->bc, &alu);
1738 if (r)
1739 return r;
1740 }
1741 memset(&alu, 0, sizeof(struct r600_bc_alu));
1742 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1743 alu.src[0].sel = V_SQ_ALU_SRC_1;
1744 alu.src[0].chan = 0;
1745 alu.dst.sel = ctx->temp_reg;
1746 alu.dst.chan = 3;
1747 alu.last = 1;
1748 alu.dst.write = 1;
1749 r = r600_bc_add_alu(ctx->bc, &alu);
1750 if (r)
1751 return r;
1752 src_not_temp = FALSE;
1753 src_gpr = ctx->temp_reg;
1754 }
1755
1756 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1757 int src_chan, src2_chan;
1758
1759 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1760 for (i = 0; i < 4; i++) {
1761 memset(&alu, 0, sizeof(struct r600_bc_alu));
1762 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1763 switch (i) {
1764 case 0:
1765 src_chan = 2;
1766 src2_chan = 1;
1767 break;
1768 case 1:
1769 src_chan = 2;
1770 src2_chan = 0;
1771 break;
1772 case 2:
1773 src_chan = 0;
1774 src2_chan = 2;
1775 break;
1776 case 3:
1777 src_chan = 1;
1778 src2_chan = 2;
1779 break;
1780 default:
1781 assert(0);
1782 src_chan = 0;
1783 src2_chan = 0;
1784 break;
1785 }
1786 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1787 if (r)
1788 return r;
1789 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1790 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1791 if (r)
1792 return r;
1793 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1794 alu.dst.sel = ctx->temp_reg;
1795 alu.dst.chan = i;
1796 if (i == 3)
1797 alu.last = 1;
1798 alu.dst.write = 1;
1799 r = r600_bc_add_alu(ctx->bc, &alu);
1800 if (r)
1801 return r;
1802 }
1803
1804 /* tmp1.z = RCP_e(|tmp1.z|) */
1805 memset(&alu, 0, sizeof(struct r600_bc_alu));
1806 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1807 alu.src[0].sel = ctx->temp_reg;
1808 alu.src[0].chan = 2;
1809 alu.src[0].abs = 1;
1810 alu.dst.sel = ctx->temp_reg;
1811 alu.dst.chan = 2;
1812 alu.dst.write = 1;
1813 alu.last = 1;
1814 r = r600_bc_add_alu(ctx->bc, &alu);
1815 if (r)
1816 return r;
1817
1818 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1819 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1820 * muladd has no writemask, have to use another temp
1821 */
1822 memset(&alu, 0, sizeof(struct r600_bc_alu));
1823 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1824 alu.is_op3 = 1;
1825
1826 alu.src[0].sel = ctx->temp_reg;
1827 alu.src[0].chan = 0;
1828 alu.src[1].sel = ctx->temp_reg;
1829 alu.src[1].chan = 2;
1830
1831 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1832 alu.src[2].chan = 0;
1833
1834 alu.dst.sel = ctx->temp_reg;
1835 alu.dst.chan = 0;
1836 alu.dst.write = 1;
1837
1838 r = r600_bc_add_alu(ctx->bc, &alu);
1839 if (r)
1840 return r;
1841
1842 memset(&alu, 0, sizeof(struct r600_bc_alu));
1843 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1844 alu.is_op3 = 1;
1845
1846 alu.src[0].sel = ctx->temp_reg;
1847 alu.src[0].chan = 1;
1848 alu.src[1].sel = ctx->temp_reg;
1849 alu.src[1].chan = 2;
1850
1851 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1852 alu.src[2].chan = 0;
1853
1854 alu.dst.sel = ctx->temp_reg;
1855 alu.dst.chan = 1;
1856 alu.dst.write = 1;
1857
1858 alu.last = 1;
1859 r = r600_bc_add_alu(ctx->bc, &alu);
1860 if (r)
1861 return r;
1862
1863 lit_vals[0] = fui(1.5f);
1864
1865 r = r600_bc_add_literal(ctx->bc, lit_vals);
1866 if (r)
1867 return r;
1868 src_not_temp = FALSE;
1869 src_gpr = ctx->temp_reg;
1870 }
1871
1872 if (src_not_temp) {
1873 for (i = 0; i < 4; i++) {
1874 memset(&alu, 0, sizeof(struct r600_bc_alu));
1875 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1876 alu.src[0].sel = src_gpr;
1877 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1878 alu.dst.sel = ctx->temp_reg;
1879 alu.dst.chan = i;
1880 if (i == 3)
1881 alu.last = 1;
1882 alu.dst.write = 1;
1883 r = r600_bc_add_alu(ctx->bc, &alu);
1884 if (r)
1885 return r;
1886 }
1887 src_gpr = ctx->temp_reg;
1888 }
1889
1890 opcode = ctx->inst_info->r600_opcode;
1891 if (opcode == SQ_TEX_INST_SAMPLE &&
1892 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1893 opcode = SQ_TEX_INST_SAMPLE_C;
1894
1895 memset(&tex, 0, sizeof(struct r600_bc_tex));
1896 tex.inst = opcode;
1897 tex.sampler_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1898 tex.resource_id = tex.sampler_id;
1899 tex.src_gpr = src_gpr;
1900 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1901 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
1902 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
1903 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
1904 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
1905 tex.src_sel_x = 0;
1906 tex.src_sel_y = 1;
1907 tex.src_sel_z = 2;
1908 tex.src_sel_w = 3;
1909
1910 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1911 tex.src_sel_x = 1;
1912 tex.src_sel_y = 0;
1913 tex.src_sel_z = 3;
1914 tex.src_sel_w = 1;
1915 }
1916
1917 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1918 tex.coord_type_x = 1;
1919 tex.coord_type_y = 1;
1920 tex.coord_type_z = 1;
1921 tex.coord_type_w = 1;
1922 }
1923
1924 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1925 tex.src_sel_w = 2;
1926
1927 r = r600_bc_add_tex(ctx->bc, &tex);
1928 if (r)
1929 return r;
1930
1931 /* add shadow ambient support - gallium doesn't do it yet */
1932 return 0;
1933 }
1934
1935 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1936 {
1937 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1938 struct r600_bc_alu_src r600_src[3];
1939 struct r600_bc_alu alu;
1940 unsigned i;
1941 int r;
1942
1943 r = tgsi_split_constant(ctx, r600_src);
1944 if (r)
1945 return r;
1946 r = tgsi_split_literal_constant(ctx, r600_src);
1947 if (r)
1948 return r;
1949 /* 1 - src0 */
1950 for (i = 0; i < 4; i++) {
1951 memset(&alu, 0, sizeof(struct r600_bc_alu));
1952 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1953 alu.src[0].sel = V_SQ_ALU_SRC_1;
1954 alu.src[0].chan = 0;
1955 alu.src[1] = r600_src[0];
1956 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1957 alu.src[1].neg = 1;
1958 alu.dst.sel = ctx->temp_reg;
1959 alu.dst.chan = i;
1960 if (i == 3) {
1961 alu.last = 1;
1962 }
1963 alu.dst.write = 1;
1964 r = r600_bc_add_alu(ctx->bc, &alu);
1965 if (r)
1966 return r;
1967 }
1968 r = r600_bc_add_literal(ctx->bc, ctx->value);
1969 if (r)
1970 return r;
1971
1972 /* (1 - src0) * src2 */
1973 for (i = 0; i < 4; i++) {
1974 memset(&alu, 0, sizeof(struct r600_bc_alu));
1975 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1976 alu.src[0].sel = ctx->temp_reg;
1977 alu.src[0].chan = i;
1978 alu.src[1] = r600_src[2];
1979 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1980 alu.dst.sel = ctx->temp_reg;
1981 alu.dst.chan = i;
1982 if (i == 3) {
1983 alu.last = 1;
1984 }
1985 alu.dst.write = 1;
1986 r = r600_bc_add_alu(ctx->bc, &alu);
1987 if (r)
1988 return r;
1989 }
1990 r = r600_bc_add_literal(ctx->bc, ctx->value);
1991 if (r)
1992 return r;
1993
1994 /* src0 * src1 + (1 - src0) * src2 */
1995 for (i = 0; i < 4; i++) {
1996 memset(&alu, 0, sizeof(struct r600_bc_alu));
1997 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1998 alu.is_op3 = 1;
1999 alu.src[0] = r600_src[0];
2000 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2001 alu.src[1] = r600_src[1];
2002 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2003 alu.src[2].sel = ctx->temp_reg;
2004 alu.src[2].chan = i;
2005 alu.dst.sel = ctx->temp_reg;
2006 alu.dst.chan = i;
2007 if (i == 3) {
2008 alu.last = 1;
2009 }
2010 r = r600_bc_add_alu(ctx->bc, &alu);
2011 if (r)
2012 return r;
2013 }
2014 return tgsi_helper_copy(ctx, inst);
2015 }
2016
2017 static int tgsi_cmp(struct r600_shader_ctx *ctx)
2018 {
2019 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2020 struct r600_bc_alu_src r600_src[3];
2021 struct r600_bc_alu alu;
2022 int i, r;
2023 int lasti = 0;
2024
2025 for (i = 0; i < 4; i++) {
2026 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
2027 lasti = i;
2028 }
2029 }
2030
2031 r = tgsi_split_constant(ctx, r600_src);
2032 if (r)
2033 return r;
2034 r = tgsi_split_literal_constant(ctx, r600_src);
2035 if (r)
2036 return r;
2037
2038 for (i = 0; i < lasti + 1; i++) {
2039 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2040 continue;
2041
2042 memset(&alu, 0, sizeof(struct r600_bc_alu));
2043 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
2044 alu.src[0] = r600_src[0];
2045 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2046
2047 alu.src[1] = r600_src[2];
2048 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
2049
2050 alu.src[2] = r600_src[1];
2051 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
2052
2053 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2054 if (r)
2055 return r;
2056
2057 alu.dst.chan = i;
2058 alu.dst.write = 1;
2059 alu.is_op3 = 1;
2060 if (i == lasti)
2061 alu.last = 1;
2062 r = r600_bc_add_alu(ctx->bc, &alu);
2063 if (r)
2064 return r;
2065 }
2066 return 0;
2067 }
2068
2069 static int tgsi_xpd(struct r600_shader_ctx *ctx)
2070 {
2071 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2072 struct r600_bc_alu_src r600_src[3];
2073 struct r600_bc_alu alu;
2074 uint32_t use_temp = 0;
2075 int i, r;
2076
2077 if (inst->Dst[0].Register.WriteMask != 0xf)
2078 use_temp = 1;
2079
2080 r = tgsi_split_constant(ctx, r600_src);
2081 if (r)
2082 return r;
2083 r = tgsi_split_literal_constant(ctx, r600_src);
2084 if (r)
2085 return r;
2086
2087 for (i = 0; i < 4; i++) {
2088 memset(&alu, 0, sizeof(struct r600_bc_alu));
2089 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2090
2091 alu.src[0] = r600_src[0];
2092 switch (i) {
2093 case 0:
2094 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2095 break;
2096 case 1:
2097 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2098 break;
2099 case 2:
2100 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2101 break;
2102 case 3:
2103 alu.src[0].sel = V_SQ_ALU_SRC_0;
2104 alu.src[0].chan = i;
2105 }
2106
2107 alu.src[1] = r600_src[1];
2108 switch (i) {
2109 case 0:
2110 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2111 break;
2112 case 1:
2113 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2114 break;
2115 case 2:
2116 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2117 break;
2118 case 3:
2119 alu.src[1].sel = V_SQ_ALU_SRC_0;
2120 alu.src[1].chan = i;
2121 }
2122
2123 alu.dst.sel = ctx->temp_reg;
2124 alu.dst.chan = i;
2125 alu.dst.write = 1;
2126
2127 if (i == 3)
2128 alu.last = 1;
2129 r = r600_bc_add_alu(ctx->bc, &alu);
2130 if (r)
2131 return r;
2132
2133 r = r600_bc_add_literal(ctx->bc, ctx->value);
2134 if (r)
2135 return r;
2136 }
2137
2138 for (i = 0; i < 4; i++) {
2139 memset(&alu, 0, sizeof(struct r600_bc_alu));
2140 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2141
2142 alu.src[0] = r600_src[0];
2143 switch (i) {
2144 case 0:
2145 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2146 break;
2147 case 1:
2148 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2149 break;
2150 case 2:
2151 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2152 break;
2153 case 3:
2154 alu.src[0].sel = V_SQ_ALU_SRC_0;
2155 alu.src[0].chan = i;
2156 }
2157
2158 alu.src[1] = r600_src[1];
2159 switch (i) {
2160 case 0:
2161 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2162 break;
2163 case 1:
2164 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2165 break;
2166 case 2:
2167 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2168 break;
2169 case 3:
2170 alu.src[1].sel = V_SQ_ALU_SRC_0;
2171 alu.src[1].chan = i;
2172 }
2173
2174 alu.src[2].sel = ctx->temp_reg;
2175 alu.src[2].neg = 1;
2176 alu.src[2].chan = i;
2177
2178 if (use_temp)
2179 alu.dst.sel = ctx->temp_reg;
2180 else {
2181 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2182 if (r)
2183 return r;
2184 }
2185 alu.dst.chan = i;
2186 alu.dst.write = 1;
2187 alu.is_op3 = 1;
2188 if (i == 3)
2189 alu.last = 1;
2190 r = r600_bc_add_alu(ctx->bc, &alu);
2191 if (r)
2192 return r;
2193
2194 r = r600_bc_add_literal(ctx->bc, ctx->value);
2195 if (r)
2196 return r;
2197 }
2198 if (use_temp)
2199 return tgsi_helper_copy(ctx, inst);
2200 return 0;
2201 }
2202
2203 static int tgsi_exp(struct r600_shader_ctx *ctx)
2204 {
2205 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2206 struct r600_bc_alu_src r600_src[3] = { { 0 } };
2207 struct r600_bc_alu alu;
2208 int r;
2209
2210 /* result.x = 2^floor(src); */
2211 if (inst->Dst[0].Register.WriteMask & 1) {
2212 memset(&alu, 0, sizeof(struct r600_bc_alu));
2213
2214 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2215 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2216 if (r)
2217 return r;
2218
2219 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2220
2221 alu.dst.sel = ctx->temp_reg;
2222 alu.dst.chan = 0;
2223 alu.dst.write = 1;
2224 alu.last = 1;
2225 r = r600_bc_add_alu(ctx->bc, &alu);
2226 if (r)
2227 return r;
2228
2229 r = r600_bc_add_literal(ctx->bc, ctx->value);
2230 if (r)
2231 return r;
2232
2233 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2234 alu.src[0].sel = ctx->temp_reg;
2235 alu.src[0].chan = 0;
2236
2237 alu.dst.sel = ctx->temp_reg;
2238 alu.dst.chan = 0;
2239 alu.dst.write = 1;
2240 alu.last = 1;
2241 r = r600_bc_add_alu(ctx->bc, &alu);
2242 if (r)
2243 return r;
2244
2245 r = r600_bc_add_literal(ctx->bc, ctx->value);
2246 if (r)
2247 return r;
2248 }
2249
2250 /* result.y = tmp - floor(tmp); */
2251 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2252 memset(&alu, 0, sizeof(struct r600_bc_alu));
2253
2254 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2255 alu.src[0] = r600_src[0];
2256 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2257 if (r)
2258 return r;
2259 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2260
2261 alu.dst.sel = ctx->temp_reg;
2262 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2263 // if (r)
2264 // return r;
2265 alu.dst.write = 1;
2266 alu.dst.chan = 1;
2267
2268 alu.last = 1;
2269
2270 r = r600_bc_add_alu(ctx->bc, &alu);
2271 if (r)
2272 return r;
2273 r = r600_bc_add_literal(ctx->bc, ctx->value);
2274 if (r)
2275 return r;
2276 }
2277
2278 /* result.z = RoughApprox2ToX(tmp);*/
2279 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2280 memset(&alu, 0, sizeof(struct r600_bc_alu));
2281 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2282 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2283 if (r)
2284 return r;
2285 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2286
2287 alu.dst.sel = ctx->temp_reg;
2288 alu.dst.write = 1;
2289 alu.dst.chan = 2;
2290
2291 alu.last = 1;
2292
2293 r = r600_bc_add_alu(ctx->bc, &alu);
2294 if (r)
2295 return r;
2296 r = r600_bc_add_literal(ctx->bc, ctx->value);
2297 if (r)
2298 return r;
2299 }
2300
2301 /* result.w = 1.0;*/
2302 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2303 memset(&alu, 0, sizeof(struct r600_bc_alu));
2304
2305 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2306 alu.src[0].sel = V_SQ_ALU_SRC_1;
2307 alu.src[0].chan = 0;
2308
2309 alu.dst.sel = ctx->temp_reg;
2310 alu.dst.chan = 3;
2311 alu.dst.write = 1;
2312 alu.last = 1;
2313 r = r600_bc_add_alu(ctx->bc, &alu);
2314 if (r)
2315 return r;
2316 r = r600_bc_add_literal(ctx->bc, ctx->value);
2317 if (r)
2318 return r;
2319 }
2320 return tgsi_helper_copy(ctx, inst);
2321 }
2322
2323 static int tgsi_log(struct r600_shader_ctx *ctx)
2324 {
2325 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2326 struct r600_bc_alu alu;
2327 int r;
2328
2329 /* result.x = floor(log2(src)); */
2330 if (inst->Dst[0].Register.WriteMask & 1) {
2331 memset(&alu, 0, sizeof(struct r600_bc_alu));
2332
2333 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2334 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2335 if (r)
2336 return r;
2337
2338 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2339
2340 alu.dst.sel = ctx->temp_reg;
2341 alu.dst.chan = 0;
2342 alu.dst.write = 1;
2343 alu.last = 1;
2344 r = r600_bc_add_alu(ctx->bc, &alu);
2345 if (r)
2346 return r;
2347
2348 r = r600_bc_add_literal(ctx->bc, ctx->value);
2349 if (r)
2350 return r;
2351
2352 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2353 alu.src[0].sel = ctx->temp_reg;
2354 alu.src[0].chan = 0;
2355
2356 alu.dst.sel = ctx->temp_reg;
2357 alu.dst.chan = 0;
2358 alu.dst.write = 1;
2359 alu.last = 1;
2360
2361 r = r600_bc_add_alu(ctx->bc, &alu);
2362 if (r)
2363 return r;
2364
2365 r = r600_bc_add_literal(ctx->bc, ctx->value);
2366 if (r)
2367 return r;
2368 }
2369
2370 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2371 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2372 memset(&alu, 0, sizeof(struct r600_bc_alu));
2373
2374 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2375 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2376 if (r)
2377 return r;
2378
2379 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2380
2381 alu.dst.sel = ctx->temp_reg;
2382 alu.dst.chan = 1;
2383 alu.dst.write = 1;
2384 alu.last = 1;
2385
2386 r = r600_bc_add_alu(ctx->bc, &alu);
2387 if (r)
2388 return r;
2389
2390 r = r600_bc_add_literal(ctx->bc, ctx->value);
2391 if (r)
2392 return r;
2393
2394 memset(&alu, 0, sizeof(struct r600_bc_alu));
2395
2396 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2397 alu.src[0].sel = ctx->temp_reg;
2398 alu.src[0].chan = 1;
2399
2400 alu.dst.sel = ctx->temp_reg;
2401 alu.dst.chan = 1;
2402 alu.dst.write = 1;
2403 alu.last = 1;
2404
2405 r = r600_bc_add_alu(ctx->bc, &alu);
2406 if (r)
2407 return r;
2408
2409 r = r600_bc_add_literal(ctx->bc, ctx->value);
2410 if (r)
2411 return r;
2412
2413 memset(&alu, 0, sizeof(struct r600_bc_alu));
2414
2415 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2416 alu.src[0].sel = ctx->temp_reg;
2417 alu.src[0].chan = 1;
2418
2419 alu.dst.sel = ctx->temp_reg;
2420 alu.dst.chan = 1;
2421 alu.dst.write = 1;
2422 alu.last = 1;
2423
2424 r = r600_bc_add_alu(ctx->bc, &alu);
2425 if (r)
2426 return r;
2427
2428 r = r600_bc_add_literal(ctx->bc, ctx->value);
2429 if (r)
2430 return r;
2431
2432 memset(&alu, 0, sizeof(struct r600_bc_alu));
2433
2434 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2435 alu.src[0].sel = ctx->temp_reg;
2436 alu.src[0].chan = 1;
2437
2438 alu.dst.sel = ctx->temp_reg;
2439 alu.dst.chan = 1;
2440 alu.dst.write = 1;
2441 alu.last = 1;
2442
2443 r = r600_bc_add_alu(ctx->bc, &alu);
2444 if (r)
2445 return r;
2446
2447 r = r600_bc_add_literal(ctx->bc, ctx->value);
2448 if (r)
2449 return r;
2450
2451 memset(&alu, 0, sizeof(struct r600_bc_alu));
2452
2453 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2454
2455 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2456 if (r)
2457 return r;
2458
2459 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2460
2461 alu.src[1].sel = ctx->temp_reg;
2462 alu.src[1].chan = 1;
2463
2464 alu.dst.sel = ctx->temp_reg;
2465 alu.dst.chan = 1;
2466 alu.dst.write = 1;
2467 alu.last = 1;
2468
2469 r = r600_bc_add_alu(ctx->bc, &alu);
2470 if (r)
2471 return r;
2472
2473 r = r600_bc_add_literal(ctx->bc, ctx->value);
2474 if (r)
2475 return r;
2476 }
2477
2478 /* result.z = log2(src);*/
2479 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2480 memset(&alu, 0, sizeof(struct r600_bc_alu));
2481
2482 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2483 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2484 if (r)
2485 return r;
2486
2487 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2488
2489 alu.dst.sel = ctx->temp_reg;
2490 alu.dst.write = 1;
2491 alu.dst.chan = 2;
2492 alu.last = 1;
2493
2494 r = r600_bc_add_alu(ctx->bc, &alu);
2495 if (r)
2496 return r;
2497
2498 r = r600_bc_add_literal(ctx->bc, ctx->value);
2499 if (r)
2500 return r;
2501 }
2502
2503 /* result.w = 1.0; */
2504 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2505 memset(&alu, 0, sizeof(struct r600_bc_alu));
2506
2507 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2508 alu.src[0].sel = V_SQ_ALU_SRC_1;
2509 alu.src[0].chan = 0;
2510
2511 alu.dst.sel = ctx->temp_reg;
2512 alu.dst.chan = 3;
2513 alu.dst.write = 1;
2514 alu.last = 1;
2515
2516 r = r600_bc_add_alu(ctx->bc, &alu);
2517 if (r)
2518 return r;
2519
2520 r = r600_bc_add_literal(ctx->bc, ctx->value);
2521 if (r)
2522 return r;
2523 }
2524
2525 return tgsi_helper_copy(ctx, inst);
2526 }
2527
2528 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
2529 {
2530 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2531 struct r600_bc_alu alu;
2532 int r;
2533 memset(&alu, 0, sizeof(struct r600_bc_alu));
2534
2535 switch (inst->Instruction.Opcode) {
2536 case TGSI_OPCODE_ARL:
2537 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
2538 break;
2539 case TGSI_OPCODE_ARR:
2540 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
2541 break;
2542 default:
2543 assert(0);
2544 return -1;
2545 }
2546
2547 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2548 if (r)
2549 return r;
2550 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2551 alu.last = 1;
2552 alu.dst.chan = 0;
2553 alu.dst.sel = ctx->temp_reg;
2554 alu.dst.write = 1;
2555 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2556 if (r)
2557 return r;
2558 memset(&alu, 0, sizeof(struct r600_bc_alu));
2559 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT;
2560 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2561 if (r)
2562 return r;
2563 alu.src[0].sel = ctx->temp_reg;
2564 alu.src[0].chan = 0;
2565 alu.last = 1;
2566 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2567 if (r)
2568 return r;
2569 return 0;
2570 }
2571 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
2572 {
2573 /* TODO from r600c, ar values don't persist between clauses */
2574 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2575 struct r600_bc_alu alu;
2576 int r;
2577 memset(&alu, 0, sizeof(struct r600_bc_alu));
2578
2579 switch (inst->Instruction.Opcode) {
2580 case TGSI_OPCODE_ARL:
2581 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2582 break;
2583 case TGSI_OPCODE_ARR:
2584 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA;
2585 break;
2586 default:
2587 assert(0);
2588 return -1;
2589 }
2590
2591
2592 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2593 if (r)
2594 return r;
2595 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2596
2597 alu.last = 1;
2598
2599 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2600 if (r)
2601 return r;
2602 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2603 return 0;
2604 }
2605
2606 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2607 {
2608 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2609 struct r600_bc_alu alu;
2610 int i, r = 0;
2611
2612 for (i = 0; i < 4; i++) {
2613 memset(&alu, 0, sizeof(struct r600_bc_alu));
2614
2615 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2616 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2617 if (r)
2618 return r;
2619
2620 if (i == 0 || i == 3) {
2621 alu.src[0].sel = V_SQ_ALU_SRC_1;
2622 } else {
2623 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2624 if (r)
2625 return r;
2626 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2627 }
2628
2629 if (i == 0 || i == 2) {
2630 alu.src[1].sel = V_SQ_ALU_SRC_1;
2631 } else {
2632 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2633 if (r)
2634 return r;
2635 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2636 }
2637 if (i == 3)
2638 alu.last = 1;
2639 r = r600_bc_add_alu(ctx->bc, &alu);
2640 if (r)
2641 return r;
2642 }
2643 return 0;
2644 }
2645
2646 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2647 {
2648 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2649 struct r600_bc_alu alu;
2650 int r;
2651
2652 memset(&alu, 0, sizeof(struct r600_bc_alu));
2653 alu.inst = opcode;
2654 alu.predicate = 1;
2655
2656 alu.dst.sel = ctx->temp_reg;
2657 alu.dst.write = 1;
2658 alu.dst.chan = 0;
2659
2660 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2661 if (r)
2662 return r;
2663 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2664 alu.src[1].sel = V_SQ_ALU_SRC_0;
2665 alu.src[1].chan = 0;
2666
2667 alu.last = 1;
2668
2669 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2670 if (r)
2671 return r;
2672 return 0;
2673 }
2674
2675 static int pops(struct r600_shader_ctx *ctx, int pops)
2676 {
2677 int alu_pop = 3;
2678 if (ctx->bc->cf_last) {
2679 if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) << 3)
2680 alu_pop = 0;
2681 else if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER) << 3)
2682 alu_pop = 1;
2683 }
2684 alu_pop += pops;
2685 if (alu_pop == 1) {
2686 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER) << 3;
2687 ctx->bc->force_add_cf = 1;
2688 } else if (alu_pop == 2) {
2689 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER) << 3;
2690 ctx->bc->force_add_cf = 1;
2691 } else {
2692 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2693 ctx->bc->cf_last->pop_count = pops;
2694 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
2695 }
2696 return 0;
2697 }
2698
2699 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2700 {
2701 switch(reason) {
2702 case FC_PUSH_VPM:
2703 ctx->bc->callstack[ctx->bc->call_sp].current--;
2704 break;
2705 case FC_PUSH_WQM:
2706 case FC_LOOP:
2707 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2708 break;
2709 case FC_REP:
2710 /* TOODO : for 16 vp asic should -= 2; */
2711 ctx->bc->callstack[ctx->bc->call_sp].current --;
2712 break;
2713 }
2714 }
2715
2716 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2717 {
2718 if (check_max_only) {
2719 int diff;
2720 switch (reason) {
2721 case FC_PUSH_VPM:
2722 diff = 1;
2723 break;
2724 case FC_PUSH_WQM:
2725 diff = 4;
2726 break;
2727 default:
2728 assert(0);
2729 diff = 0;
2730 }
2731 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2732 ctx->bc->callstack[ctx->bc->call_sp].max) {
2733 ctx->bc->callstack[ctx->bc->call_sp].max =
2734 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2735 }
2736 return;
2737 }
2738 switch (reason) {
2739 case FC_PUSH_VPM:
2740 ctx->bc->callstack[ctx->bc->call_sp].current++;
2741 break;
2742 case FC_PUSH_WQM:
2743 case FC_LOOP:
2744 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2745 break;
2746 case FC_REP:
2747 ctx->bc->callstack[ctx->bc->call_sp].current++;
2748 break;
2749 }
2750
2751 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2752 ctx->bc->callstack[ctx->bc->call_sp].max) {
2753 ctx->bc->callstack[ctx->bc->call_sp].max =
2754 ctx->bc->callstack[ctx->bc->call_sp].current;
2755 }
2756 }
2757
2758 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2759 {
2760 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2761
2762 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2763 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2764 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2765 sp->num_mid++;
2766 }
2767
2768 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2769 {
2770 ctx->bc->fc_sp++;
2771 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2772 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2773 }
2774
2775 static void fc_poplevel(struct r600_shader_ctx *ctx)
2776 {
2777 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2778 if (sp->mid) {
2779 free(sp->mid);
2780 sp->mid = NULL;
2781 }
2782 sp->num_mid = 0;
2783 sp->start = NULL;
2784 sp->type = 0;
2785 ctx->bc->fc_sp--;
2786 }
2787
2788 #if 0
2789 static int emit_return(struct r600_shader_ctx *ctx)
2790 {
2791 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2792 return 0;
2793 }
2794
2795 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2796 {
2797
2798 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2799 ctx->bc->cf_last->pop_count = pops;
2800 /* TODO work out offset */
2801 return 0;
2802 }
2803
2804 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2805 {
2806 return 0;
2807 }
2808
2809 static void emit_testflag(struct r600_shader_ctx *ctx)
2810 {
2811
2812 }
2813
2814 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2815 {
2816 emit_testflag(ctx);
2817 emit_jump_to_offset(ctx, 1, 4);
2818 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2819 pops(ctx, ifidx + 1);
2820 emit_return(ctx);
2821 }
2822
2823 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2824 {
2825 emit_testflag(ctx);
2826
2827 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2828 ctx->bc->cf_last->pop_count = 1;
2829
2830 fc_set_mid(ctx, fc_sp);
2831
2832 pops(ctx, 1);
2833 }
2834 #endif
2835
2836 static int tgsi_if(struct r600_shader_ctx *ctx)
2837 {
2838 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2839
2840 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2841
2842 fc_pushlevel(ctx, FC_IF);
2843
2844 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2845 return 0;
2846 }
2847
2848 static int tgsi_else(struct r600_shader_ctx *ctx)
2849 {
2850 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2851 ctx->bc->cf_last->pop_count = 1;
2852
2853 fc_set_mid(ctx, ctx->bc->fc_sp);
2854 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2855 return 0;
2856 }
2857
2858 static int tgsi_endif(struct r600_shader_ctx *ctx)
2859 {
2860 pops(ctx, 1);
2861 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2862 R600_ERR("if/endif unbalanced in shader\n");
2863 return -1;
2864 }
2865
2866 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2867 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2868 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2869 } else {
2870 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2871 }
2872 fc_poplevel(ctx);
2873
2874 callstack_decrease_current(ctx, FC_PUSH_VPM);
2875 return 0;
2876 }
2877
2878 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2879 {
2880 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2881
2882 fc_pushlevel(ctx, FC_LOOP);
2883
2884 /* check stack depth */
2885 callstack_check_depth(ctx, FC_LOOP, 0);
2886 return 0;
2887 }
2888
2889 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2890 {
2891 int i;
2892
2893 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2894
2895 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2896 R600_ERR("loop/endloop in shader code are not paired.\n");
2897 return -EINVAL;
2898 }
2899
2900 /* fixup loop pointers - from r600isa
2901 LOOP END points to CF after LOOP START,
2902 LOOP START point to CF after LOOP END
2903 BRK/CONT point to LOOP END CF
2904 */
2905 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2906
2907 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2908
2909 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2910 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2911 }
2912 /* TODO add LOOPRET support */
2913 fc_poplevel(ctx);
2914 callstack_decrease_current(ctx, FC_LOOP);
2915 return 0;
2916 }
2917
2918 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2919 {
2920 unsigned int fscp;
2921
2922 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2923 {
2924 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2925 break;
2926 }
2927
2928 if (fscp == 0) {
2929 R600_ERR("Break not inside loop/endloop pair\n");
2930 return -EINVAL;
2931 }
2932
2933 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2934 ctx->bc->cf_last->pop_count = 1;
2935
2936 fc_set_mid(ctx, fscp);
2937
2938 pops(ctx, 1);
2939 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2940 return 0;
2941 }
2942
2943 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2944 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2945 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2946 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2947
2948 /* FIXME:
2949 * For state trackers other than OpenGL, we'll want to use
2950 * _RECIP_IEEE instead.
2951 */
2952 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2953
2954 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2955 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2956 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2957 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2958 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2959 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2960 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2961 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2962 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2963 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2964 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2965 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2966 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2967 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2968 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2969 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2970 /* gap */
2971 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2972 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2973 /* gap */
2974 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2975 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2976 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2977 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2978 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2979 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2980 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2981 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2982 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2983 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2984 /* gap */
2985 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2986 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2987 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2988 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2989 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2990 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2991 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2992 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2993 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2994 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2995 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2996 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2997 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2998 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2999 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3000 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3001 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3002 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3003 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3004 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3005 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3006 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3007 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3008 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3009 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3010 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3011 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3012 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3013 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3014 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
3015 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3016 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3017 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3018 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3019 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3020 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3021 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3022 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3023 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3024 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3025 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3026 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3027 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3028 /* gap */
3029 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3030 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3031 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3032 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3033 /* gap */
3034 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3035 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3036 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3037 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3038 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3039 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3040 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3041 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3042 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3043 /* gap */
3044 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3045 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3046 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3047 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3048 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3049 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3050 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3051 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3052 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3053 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3054 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3055 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3056 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3057 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3058 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3059 /* gap */
3060 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3061 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3062 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3063 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3064 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3065 /* gap */
3066 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3067 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3068 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3069 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3070 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3071 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3072 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3073 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3074 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3075 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3076 /* gap */
3077 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3078 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3079 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3080 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3081 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3082 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3083 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3084 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3085 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3086 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3087 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3088 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3089 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3090 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3091 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3092 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3093 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3094 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3095 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3096 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3097 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3098 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3099 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3100 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3101 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3102 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3103 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3104 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3105 };
3106
3107 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
3108 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3109 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3110 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
3111 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
3112 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
3113 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
3114 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3115 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
3116 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3117 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3118 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3119 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
3120 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
3121 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
3122 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
3123 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
3124 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
3125 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3126 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
3127 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3128 /* gap */
3129 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3130 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3131 /* gap */
3132 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3133 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3134 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3135 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3136 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3137 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3138 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3139 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3140 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3141 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3142 /* gap */
3143 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3144 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3145 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3146 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3147 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3148 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3149 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3150 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3151 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3152 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3153 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3154 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3155 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3156 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3157 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3158 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3159 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3160 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3161 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3162 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3163 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3164 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3165 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3166 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3167 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3168 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3169 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3170 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3171 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3172 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3173 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3174 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3175 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3176 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3177 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3178 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3179 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3180 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3181 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3182 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3183 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3184 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3185 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3186 /* gap */
3187 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3188 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3189 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3190 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3191 /* gap */
3192 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3193 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3194 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3195 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3196 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3197 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3198 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3199 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3200 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3201 /* gap */
3202 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3203 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3204 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3205 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3206 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3207 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3208 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3209 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3210 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3211 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3212 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3213 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3214 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3215 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3216 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3217 /* gap */
3218 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3219 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3220 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3221 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3222 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3223 /* gap */
3224 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3225 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3226 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3227 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3228 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3229 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3230 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3231 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3232 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3233 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3234 /* gap */
3235 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3236 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3237 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3238 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3239 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3240 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3241 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3242 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3243 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3244 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3245 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3246 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3247 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3248 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3249 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3250 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3251 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3252 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3253 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3254 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3255 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3256 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3257 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3258 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3259 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3260 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3261 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3262 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3263 };