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r600g/llvm: fix txq for texture buffer
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
64 struct r600_pipe_shader *pipeshader,
65 struct r600_shader_key key);
66
67 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
68 int size, unsigned comp_mask) {
69
70 if (!size)
71 return;
72
73 if (ps->num_arrays == ps->max_arrays) {
74 ps->max_arrays += 64;
75 ps->arrays = realloc(ps->arrays, ps->max_arrays *
76 sizeof(struct r600_shader_array));
77 }
78
79 int n = ps->num_arrays;
80 ++ps->num_arrays;
81
82 ps->arrays[n].comp_mask = comp_mask;
83 ps->arrays[n].gpr_start = start_gpr;
84 ps->arrays[n].gpr_count = size;
85 }
86
87 static void r600_dump_streamout(struct pipe_stream_output_info *so)
88 {
89 unsigned i;
90
91 fprintf(stderr, "STREAMOUT\n");
92 for (i = 0; i < so->num_outputs; i++) {
93 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
94 so->output[i].start_component;
95 fprintf(stderr, " %i: MEM_STREAM0_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
96 i, so->output[i].output_buffer,
97 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
98 so->output[i].register_index,
99 mask & 1 ? "x" : "",
100 mask & 2 ? "y" : "",
101 mask & 4 ? "z" : "",
102 mask & 8 ? "w" : "",
103 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
104 }
105 }
106
107 int r600_pipe_shader_create(struct pipe_context *ctx,
108 struct r600_pipe_shader *shader,
109 struct r600_shader_key key)
110 {
111 struct r600_context *rctx = (struct r600_context *)ctx;
112 struct r600_pipe_shader_selector *sel = shader->selector;
113 int r, i;
114 uint32_t *ptr;
115 bool dump = r600_can_dump_shader(&rctx->screen->b, sel->tokens);
116 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
117 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
118
119 shader->shader.bc.isa = rctx->isa;
120
121 if (dump) {
122 fprintf(stderr, "--------------------------------------------------------------\n");
123 tgsi_dump(sel->tokens, 0);
124
125 if (sel->so.num_outputs) {
126 r600_dump_streamout(&sel->so);
127 }
128 }
129 r = r600_shader_from_tgsi(rctx->screen, shader, key);
130 if (r) {
131 R600_ERR("translation from TGSI failed !\n");
132 return r;
133 }
134
135 /* Check if the bytecode has already been built. When using the llvm
136 * backend, r600_shader_from_tgsi() will take care of building the
137 * bytecode.
138 */
139 if (!shader->shader.bc.bytecode) {
140 r = r600_bytecode_build(&shader->shader.bc);
141 if (r) {
142 R600_ERR("building bytecode failed !\n");
143 return r;
144 }
145 }
146
147 if (dump && !sb_disasm) {
148 fprintf(stderr, "--------------------------------------------------------------\n");
149 r600_bytecode_disasm(&shader->shader.bc);
150 fprintf(stderr, "______________________________________________________________\n");
151 } else if ((dump && sb_disasm) || use_sb) {
152 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
153 dump, use_sb);
154 if (r) {
155 R600_ERR("r600_sb_bytecode_process failed !\n");
156 return r;
157 }
158 }
159
160 /* Store the shader in a buffer. */
161 if (shader->bo == NULL) {
162 shader->bo = (struct r600_resource*)
163 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
164 if (shader->bo == NULL) {
165 return -ENOMEM;
166 }
167 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
168 if (R600_BIG_ENDIAN) {
169 for (i = 0; i < shader->shader.bc.ndw; ++i) {
170 ptr[i] = util_bswap32(shader->shader.bc.bytecode[i]);
171 }
172 } else {
173 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
174 }
175 rctx->b.ws->buffer_unmap(shader->bo->cs_buf);
176 }
177
178 /* Build state. */
179 switch (shader->shader.processor_type) {
180 case TGSI_PROCESSOR_VERTEX:
181 if (rctx->b.chip_class >= EVERGREEN) {
182 evergreen_update_vs_state(ctx, shader);
183 } else {
184 r600_update_vs_state(ctx, shader);
185 }
186 break;
187 case TGSI_PROCESSOR_FRAGMENT:
188 if (rctx->b.chip_class >= EVERGREEN) {
189 evergreen_update_ps_state(ctx, shader);
190 } else {
191 r600_update_ps_state(ctx, shader);
192 }
193 break;
194 default:
195 return -EINVAL;
196 }
197 return 0;
198 }
199
200 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
201 {
202 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
203 r600_bytecode_clear(&shader->shader.bc);
204 r600_release_command_buffer(&shader->command_buffer);
205 }
206
207 /*
208 * tgsi -> r600 shader
209 */
210 struct r600_shader_tgsi_instruction;
211
212 struct r600_shader_src {
213 unsigned sel;
214 unsigned swizzle[4];
215 unsigned neg;
216 unsigned abs;
217 unsigned rel;
218 unsigned kc_bank;
219 uint32_t value[4];
220 };
221
222 struct r600_shader_ctx {
223 struct tgsi_shader_info info;
224 struct tgsi_parse_context parse;
225 const struct tgsi_token *tokens;
226 unsigned type;
227 unsigned file_offset[TGSI_FILE_COUNT];
228 unsigned temp_reg;
229 struct r600_shader_tgsi_instruction *inst_info;
230 struct r600_bytecode *bc;
231 struct r600_shader *shader;
232 struct r600_shader_src src[4];
233 uint32_t *literals;
234 uint32_t nliterals;
235 uint32_t max_driver_temp_used;
236 boolean use_llvm;
237 /* needed for evergreen interpolation */
238 boolean input_centroid;
239 boolean input_linear;
240 boolean input_perspective;
241 int num_interp_gpr;
242 int face_gpr;
243 int colors_used;
244 boolean clip_vertex_write;
245 unsigned cv_output;
246 int fragcoord_input;
247 int native_integers;
248 };
249
250 struct r600_shader_tgsi_instruction {
251 unsigned tgsi_opcode;
252 unsigned is_op3;
253 unsigned op;
254 int (*process)(struct r600_shader_ctx *ctx);
255 };
256
257 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
258 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
259 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
260 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
261 static int tgsi_else(struct r600_shader_ctx *ctx);
262 static int tgsi_endif(struct r600_shader_ctx *ctx);
263 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
264 static int tgsi_endloop(struct r600_shader_ctx *ctx);
265 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
266
267 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
268 {
269 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
270 int j;
271
272 if (i->Instruction.NumDstRegs > 1) {
273 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
274 return -EINVAL;
275 }
276 if (i->Instruction.Predicate) {
277 R600_ERR("predicate unsupported\n");
278 return -EINVAL;
279 }
280 #if 0
281 if (i->Instruction.Label) {
282 R600_ERR("label unsupported\n");
283 return -EINVAL;
284 }
285 #endif
286 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
287 if (i->Src[j].Register.Dimension) {
288 if (i->Src[j].Register.File != TGSI_FILE_CONSTANT) {
289 R600_ERR("unsupported src %d (dimension %d)\n", j,
290 i->Src[j].Register.Dimension);
291 return -EINVAL;
292 }
293 }
294 }
295 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
296 if (i->Dst[j].Register.Dimension) {
297 R600_ERR("unsupported dst (dimension)\n");
298 return -EINVAL;
299 }
300 }
301 return 0;
302 }
303
304 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
305 int input)
306 {
307 int ij_index = 0;
308
309 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
310 if (ctx->shader->input[input].centroid)
311 ij_index++;
312 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
313 /* if we have perspective add one */
314 if (ctx->input_perspective) {
315 ij_index++;
316 /* if we have perspective centroid */
317 if (ctx->input_centroid)
318 ij_index++;
319 }
320 if (ctx->shader->input[input].centroid)
321 ij_index++;
322 }
323
324 ctx->shader->input[input].ij_index = ij_index;
325 }
326
327 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
328 {
329 int i, r;
330 struct r600_bytecode_alu alu;
331 int gpr = 0, base_chan = 0;
332 int ij_index = ctx->shader->input[input].ij_index;
333
334 /* work out gpr and base_chan from index */
335 gpr = ij_index / 2;
336 base_chan = (2 * (ij_index % 2)) + 1;
337
338 for (i = 0; i < 8; i++) {
339 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
340
341 if (i < 4)
342 alu.op = ALU_OP2_INTERP_ZW;
343 else
344 alu.op = ALU_OP2_INTERP_XY;
345
346 if ((i > 1) && (i < 6)) {
347 alu.dst.sel = ctx->shader->input[input].gpr;
348 alu.dst.write = 1;
349 }
350
351 alu.dst.chan = i % 4;
352
353 alu.src[0].sel = gpr;
354 alu.src[0].chan = (base_chan - (i % 2));
355
356 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
357
358 alu.bank_swizzle_force = SQ_ALU_VEC_210;
359 if ((i % 4) == 3)
360 alu.last = 1;
361 r = r600_bytecode_add_alu(ctx->bc, &alu);
362 if (r)
363 return r;
364 }
365 return 0;
366 }
367
368 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
369 {
370 int i, r;
371 struct r600_bytecode_alu alu;
372
373 for (i = 0; i < 4; i++) {
374 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
375
376 alu.op = ALU_OP1_INTERP_LOAD_P0;
377
378 alu.dst.sel = ctx->shader->input[input].gpr;
379 alu.dst.write = 1;
380
381 alu.dst.chan = i;
382
383 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
384 alu.src[0].chan = i;
385
386 if (i == 3)
387 alu.last = 1;
388 r = r600_bytecode_add_alu(ctx->bc, &alu);
389 if (r)
390 return r;
391 }
392 return 0;
393 }
394
395 /*
396 * Special export handling in shaders
397 *
398 * shader export ARRAY_BASE for EXPORT_POS:
399 * 60 is position
400 * 61 is misc vector
401 * 62, 63 are clip distance vectors
402 *
403 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
404 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
405 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
406 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
407 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
408 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
409 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
410 * exclusive from render target index)
411 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
412 *
413 *
414 * shader export ARRAY_BASE for EXPORT_PIXEL:
415 * 0-7 CB targets
416 * 61 computed Z vector
417 *
418 * The use of the values exported in the computed Z vector are controlled
419 * by DB_SHADER_CONTROL:
420 * Z_EXPORT_ENABLE - Z as a float in RED
421 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
422 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
423 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
424 * DB_SOURCE_FORMAT - export control restrictions
425 *
426 */
427
428
429 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
430 static int r600_spi_sid(struct r600_shader_io * io)
431 {
432 int index, name = io->name;
433
434 /* These params are handled differently, they don't need
435 * semantic indices, so we'll use 0 for them.
436 */
437 if (name == TGSI_SEMANTIC_POSITION ||
438 name == TGSI_SEMANTIC_PSIZE ||
439 name == TGSI_SEMANTIC_FACE)
440 index = 0;
441 else {
442 if (name == TGSI_SEMANTIC_GENERIC) {
443 /* For generic params simply use sid from tgsi */
444 index = io->sid;
445 } else {
446 /* For non-generic params - pack name and sid into 8 bits */
447 index = 0x80 | (name<<3) | (io->sid);
448 }
449
450 /* Make sure that all really used indices have nonzero value, so
451 * we can just compare it to 0 later instead of comparing the name
452 * with different values to detect special cases. */
453 index++;
454 }
455
456 return index;
457 };
458
459 /* turn input into interpolate on EG */
460 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
461 {
462 int r = 0;
463
464 if (ctx->shader->input[index].spi_sid) {
465 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
466 if (ctx->shader->input[index].interpolate > 0) {
467 evergreen_interp_assign_ij_index(ctx, index);
468 if (!ctx->use_llvm)
469 r = evergreen_interp_alu(ctx, index);
470 } else {
471 if (!ctx->use_llvm)
472 r = evergreen_interp_flat(ctx, index);
473 }
474 }
475 return r;
476 }
477
478 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
479 {
480 struct r600_bytecode_alu alu;
481 int i, r;
482 int gpr_front = ctx->shader->input[front].gpr;
483 int gpr_back = ctx->shader->input[back].gpr;
484
485 for (i = 0; i < 4; i++) {
486 memset(&alu, 0, sizeof(alu));
487 alu.op = ALU_OP3_CNDGT;
488 alu.is_op3 = 1;
489 alu.dst.write = 1;
490 alu.dst.sel = gpr_front;
491 alu.src[0].sel = ctx->face_gpr;
492 alu.src[1].sel = gpr_front;
493 alu.src[2].sel = gpr_back;
494
495 alu.dst.chan = i;
496 alu.src[1].chan = i;
497 alu.src[2].chan = i;
498 alu.last = (i==3);
499
500 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
501 return r;
502 }
503
504 return 0;
505 }
506
507 static int tgsi_declaration(struct r600_shader_ctx *ctx)
508 {
509 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
510 int r, i, j, count = d->Range.Last - d->Range.First + 1;
511
512 switch (d->Declaration.File) {
513 case TGSI_FILE_INPUT:
514 i = ctx->shader->ninput;
515 assert(i < Elements(ctx->shader->input));
516 ctx->shader->ninput += count;
517 ctx->shader->input[i].name = d->Semantic.Name;
518 ctx->shader->input[i].sid = d->Semantic.Index;
519 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
520 ctx->shader->input[i].centroid = d->Interp.Centroid;
521 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
522 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
523 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
524 switch (ctx->shader->input[i].name) {
525 case TGSI_SEMANTIC_FACE:
526 ctx->face_gpr = ctx->shader->input[i].gpr;
527 break;
528 case TGSI_SEMANTIC_COLOR:
529 ctx->colors_used++;
530 break;
531 case TGSI_SEMANTIC_POSITION:
532 ctx->fragcoord_input = i;
533 break;
534 }
535 if (ctx->bc->chip_class >= EVERGREEN) {
536 if ((r = evergreen_interp_input(ctx, i)))
537 return r;
538 }
539 }
540 for (j = 1; j < count; ++j) {
541 ctx->shader->input[i + j] = ctx->shader->input[i];
542 ctx->shader->input[i + j].gpr += j;
543 }
544 break;
545 case TGSI_FILE_OUTPUT:
546 i = ctx->shader->noutput++;
547 assert(i < Elements(ctx->shader->output));
548 ctx->shader->output[i].name = d->Semantic.Name;
549 ctx->shader->output[i].sid = d->Semantic.Index;
550 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
551 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
552 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
553 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
554 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
555 switch (d->Semantic.Name) {
556 case TGSI_SEMANTIC_CLIPDIST:
557 ctx->shader->clip_dist_write |= d->Declaration.UsageMask << (d->Semantic.Index << 2);
558 break;
559 case TGSI_SEMANTIC_PSIZE:
560 ctx->shader->vs_out_misc_write = 1;
561 ctx->shader->vs_out_point_size = 1;
562 break;
563 case TGSI_SEMANTIC_CLIPVERTEX:
564 ctx->clip_vertex_write = TRUE;
565 ctx->cv_output = i;
566 break;
567 }
568 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
569 switch (d->Semantic.Name) {
570 case TGSI_SEMANTIC_COLOR:
571 ctx->shader->nr_ps_max_color_exports++;
572 break;
573 }
574 }
575 break;
576 case TGSI_FILE_TEMPORARY:
577 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
578 if (d->Array.ArrayID) {
579 r600_add_gpr_array(ctx->shader,
580 ctx->file_offset[TGSI_FILE_TEMPORARY] +
581 d->Range.First,
582 d->Range.Last - d->Range.First + 1, 0x0F);
583 }
584 }
585 break;
586
587 case TGSI_FILE_CONSTANT:
588 case TGSI_FILE_SAMPLER:
589 case TGSI_FILE_ADDRESS:
590 break;
591
592 case TGSI_FILE_SYSTEM_VALUE:
593 if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
594 if (!ctx->native_integers) {
595 struct r600_bytecode_alu alu;
596 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
597
598 alu.op = ALU_OP1_INT_TO_FLT;
599 alu.src[0].sel = 0;
600 alu.src[0].chan = 3;
601
602 alu.dst.sel = 0;
603 alu.dst.chan = 3;
604 alu.dst.write = 1;
605 alu.last = 1;
606
607 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
608 return r;
609 }
610 break;
611 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
612 break;
613 default:
614 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
615 return -EINVAL;
616 }
617 return 0;
618 }
619
620 static int r600_get_temp(struct r600_shader_ctx *ctx)
621 {
622 return ctx->temp_reg + ctx->max_driver_temp_used++;
623 }
624
625 /*
626 * for evergreen we need to scan the shader to find the number of GPRs we need to
627 * reserve for interpolation.
628 *
629 * we need to know if we are going to emit
630 * any centroid inputs
631 * if perspective and linear are required
632 */
633 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
634 {
635 int i;
636 int num_baryc;
637
638 ctx->input_linear = FALSE;
639 ctx->input_perspective = FALSE;
640 ctx->input_centroid = FALSE;
641 ctx->num_interp_gpr = 1;
642
643 /* any centroid inputs */
644 for (i = 0; i < ctx->info.num_inputs; i++) {
645 /* skip position/face */
646 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
647 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
648 continue;
649 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
650 ctx->input_linear = TRUE;
651 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
652 ctx->input_perspective = TRUE;
653 if (ctx->info.input_centroid[i])
654 ctx->input_centroid = TRUE;
655 }
656
657 num_baryc = 0;
658 /* ignoring sample for now */
659 if (ctx->input_perspective)
660 num_baryc++;
661 if (ctx->input_linear)
662 num_baryc++;
663 if (ctx->input_centroid)
664 num_baryc *= 2;
665
666 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
667
668 /* XXX PULL MODEL and LINE STIPPLE, FIXED PT POS */
669 return ctx->num_interp_gpr;
670 }
671
672 static void tgsi_src(struct r600_shader_ctx *ctx,
673 const struct tgsi_full_src_register *tgsi_src,
674 struct r600_shader_src *r600_src)
675 {
676 memset(r600_src, 0, sizeof(*r600_src));
677 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
678 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
679 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
680 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
681 r600_src->neg = tgsi_src->Register.Negate;
682 r600_src->abs = tgsi_src->Register.Absolute;
683
684 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
685 int index;
686 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
687 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
688 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
689
690 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
691 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
692 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
693 return;
694 }
695 index = tgsi_src->Register.Index;
696 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
697 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
698 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
699 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
700 r600_src->swizzle[0] = 3;
701 r600_src->swizzle[1] = 3;
702 r600_src->swizzle[2] = 3;
703 r600_src->swizzle[3] = 3;
704 r600_src->sel = 0;
705 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
706 r600_src->swizzle[0] = 0;
707 r600_src->swizzle[1] = 0;
708 r600_src->swizzle[2] = 0;
709 r600_src->swizzle[3] = 0;
710 r600_src->sel = 0;
711 }
712 } else {
713 if (tgsi_src->Register.Indirect)
714 r600_src->rel = V_SQ_REL_RELATIVE;
715 r600_src->sel = tgsi_src->Register.Index;
716 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
717 }
718 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
719 if (tgsi_src->Register.Dimension) {
720 r600_src->kc_bank = tgsi_src->Dimension.Index;
721 }
722 }
723 }
724
725 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int cb_idx, unsigned int offset, unsigned int dst_reg)
726 {
727 struct r600_bytecode_vtx vtx;
728 unsigned int ar_reg;
729 int r;
730
731 if (offset) {
732 struct r600_bytecode_alu alu;
733
734 memset(&alu, 0, sizeof(alu));
735
736 alu.op = ALU_OP2_ADD_INT;
737 alu.src[0].sel = ctx->bc->ar_reg;
738
739 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
740 alu.src[1].value = offset;
741
742 alu.dst.sel = dst_reg;
743 alu.dst.write = 1;
744 alu.last = 1;
745
746 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
747 return r;
748
749 ar_reg = dst_reg;
750 } else {
751 ar_reg = ctx->bc->ar_reg;
752 }
753
754 memset(&vtx, 0, sizeof(vtx));
755 vtx.buffer_id = cb_idx;
756 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
757 vtx.src_gpr = ar_reg;
758 vtx.mega_fetch_count = 16;
759 vtx.dst_gpr = dst_reg;
760 vtx.dst_sel_x = 0; /* SEL_X */
761 vtx.dst_sel_y = 1; /* SEL_Y */
762 vtx.dst_sel_z = 2; /* SEL_Z */
763 vtx.dst_sel_w = 3; /* SEL_W */
764 vtx.data_format = FMT_32_32_32_32_FLOAT;
765 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
766 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
767 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
768 vtx.endian = r600_endian_swap(32);
769
770 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
771 return r;
772
773 return 0;
774 }
775
776 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
777 {
778 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
779 struct r600_bytecode_alu alu;
780 int i, j, k, nconst, r;
781
782 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
783 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
784 nconst++;
785 }
786 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
787 }
788 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
789 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
790 continue;
791 }
792
793 if (ctx->src[i].rel) {
794 int treg = r600_get_temp(ctx);
795 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].sel - 512, treg)))
796 return r;
797
798 ctx->src[i].kc_bank = 0;
799 ctx->src[i].sel = treg;
800 ctx->src[i].rel = 0;
801 j--;
802 } else if (j > 0) {
803 int treg = r600_get_temp(ctx);
804 for (k = 0; k < 4; k++) {
805 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
806 alu.op = ALU_OP1_MOV;
807 alu.src[0].sel = ctx->src[i].sel;
808 alu.src[0].chan = k;
809 alu.src[0].rel = ctx->src[i].rel;
810 alu.dst.sel = treg;
811 alu.dst.chan = k;
812 alu.dst.write = 1;
813 if (k == 3)
814 alu.last = 1;
815 r = r600_bytecode_add_alu(ctx->bc, &alu);
816 if (r)
817 return r;
818 }
819 ctx->src[i].sel = treg;
820 ctx->src[i].rel =0;
821 j--;
822 }
823 }
824 return 0;
825 }
826
827 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
828 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
829 {
830 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
831 struct r600_bytecode_alu alu;
832 int i, j, k, nliteral, r;
833
834 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
835 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
836 nliteral++;
837 }
838 }
839 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
840 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
841 int treg = r600_get_temp(ctx);
842 for (k = 0; k < 4; k++) {
843 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
844 alu.op = ALU_OP1_MOV;
845 alu.src[0].sel = ctx->src[i].sel;
846 alu.src[0].chan = k;
847 alu.src[0].value = ctx->src[i].value[k];
848 alu.dst.sel = treg;
849 alu.dst.chan = k;
850 alu.dst.write = 1;
851 if (k == 3)
852 alu.last = 1;
853 r = r600_bytecode_add_alu(ctx->bc, &alu);
854 if (r)
855 return r;
856 }
857 ctx->src[i].sel = treg;
858 j--;
859 }
860 }
861 return 0;
862 }
863
864 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
865 {
866 int i, r, count = ctx->shader->ninput;
867
868 for (i = 0; i < count; i++) {
869 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
870 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
871 if (r)
872 return r;
873 }
874 }
875 return 0;
876 }
877
878
879 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
880 struct r600_pipe_shader *pipeshader,
881 struct r600_shader_key key)
882 {
883 struct r600_shader *shader = &pipeshader->shader;
884 struct tgsi_token *tokens = pipeshader->selector->tokens;
885 struct pipe_stream_output_info so = pipeshader->selector->so;
886 struct tgsi_full_immediate *immediate;
887 struct tgsi_full_property *property;
888 struct r600_shader_ctx ctx;
889 struct r600_bytecode_output output[32];
890 unsigned output_done, noutput;
891 unsigned opcode;
892 int i, j, k, r = 0;
893 int next_pos_base = 60, next_param_base = 0;
894 int max_color_exports = MAX2(key.nr_cbufs, 1);
895 /* Declarations used by llvm code */
896 bool use_llvm = false;
897 bool indirect_gprs;
898
899 #ifdef R600_USE_LLVM
900 use_llvm = !(rscreen->b.debug_flags & DBG_NO_LLVM);
901 #endif
902 ctx.bc = &shader->bc;
903 ctx.shader = shader;
904 ctx.native_integers = true;
905
906 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
907 rscreen->has_compressed_msaa_texturing);
908 ctx.tokens = tokens;
909 tgsi_scan_shader(tokens, &ctx.info);
910 shader->indirect_files = ctx.info.indirect_files;
911 indirect_gprs = ctx.info.indirect_files & ~(1 << TGSI_FILE_CONSTANT);
912 tgsi_parse_init(&ctx.parse, tokens);
913 ctx.type = ctx.parse.FullHeader.Processor.Processor;
914 shader->processor_type = ctx.type;
915 ctx.bc->type = shader->processor_type;
916
917 ctx.face_gpr = -1;
918 ctx.fragcoord_input = -1;
919 ctx.colors_used = 0;
920 ctx.clip_vertex_write = 0;
921
922 shader->nr_ps_color_exports = 0;
923 shader->nr_ps_max_color_exports = 0;
924
925 shader->two_side = key.color_two_side;
926
927 /* register allocations */
928 /* Values [0,127] correspond to GPR[0..127].
929 * Values [128,159] correspond to constant buffer bank 0
930 * Values [160,191] correspond to constant buffer bank 1
931 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
932 * Values [256,287] correspond to constant buffer bank 2 (EG)
933 * Values [288,319] correspond to constant buffer bank 3 (EG)
934 * Other special values are shown in the list below.
935 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
936 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
937 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
938 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
939 * 248 SQ_ALU_SRC_0: special constant 0.0.
940 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
941 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
942 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
943 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
944 * 253 SQ_ALU_SRC_LITERAL: literal constant.
945 * 254 SQ_ALU_SRC_PV: previous vector result.
946 * 255 SQ_ALU_SRC_PS: previous scalar result.
947 */
948 for (i = 0; i < TGSI_FILE_COUNT; i++) {
949 ctx.file_offset[i] = 0;
950 }
951
952 #ifdef R600_USE_LLVM
953 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
954 fprintf(stderr, "Warning: R600 LLVM backend does not support "
955 "indirect adressing. Falling back to TGSI "
956 "backend.\n");
957 use_llvm = 0;
958 }
959 #endif
960 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
961 ctx.file_offset[TGSI_FILE_INPUT] = 1;
962 if (!use_llvm) {
963 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
964 }
965 }
966 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
967 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
968 }
969 ctx.use_llvm = use_llvm;
970
971 if (use_llvm) {
972 ctx.file_offset[TGSI_FILE_OUTPUT] =
973 ctx.file_offset[TGSI_FILE_INPUT];
974 } else {
975 ctx.file_offset[TGSI_FILE_OUTPUT] =
976 ctx.file_offset[TGSI_FILE_INPUT] +
977 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
978 }
979 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
980 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
981
982 /* Outside the GPR range. This will be translated to one of the
983 * kcache banks later. */
984 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
985
986 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
987 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
988 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
989 ctx.temp_reg = ctx.bc->ar_reg + 1;
990
991 if (indirect_gprs) {
992 shader->max_arrays = 0;
993 shader->num_arrays = 0;
994
995 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
996 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
997 ctx.file_offset[TGSI_FILE_OUTPUT] -
998 ctx.file_offset[TGSI_FILE_INPUT],
999 0x0F);
1000 }
1001 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
1002 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
1003 ctx.file_offset[TGSI_FILE_TEMPORARY] -
1004 ctx.file_offset[TGSI_FILE_OUTPUT],
1005 0x0F);
1006 }
1007 }
1008
1009 ctx.nliterals = 0;
1010 ctx.literals = NULL;
1011 shader->fs_write_all = FALSE;
1012 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1013 tgsi_parse_token(&ctx.parse);
1014 switch (ctx.parse.FullToken.Token.Type) {
1015 case TGSI_TOKEN_TYPE_IMMEDIATE:
1016 immediate = &ctx.parse.FullToken.FullImmediate;
1017 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
1018 if(ctx.literals == NULL) {
1019 r = -ENOMEM;
1020 goto out_err;
1021 }
1022 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
1023 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
1024 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
1025 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
1026 ctx.nliterals++;
1027 break;
1028 case TGSI_TOKEN_TYPE_DECLARATION:
1029 r = tgsi_declaration(&ctx);
1030 if (r)
1031 goto out_err;
1032 break;
1033 case TGSI_TOKEN_TYPE_INSTRUCTION:
1034 break;
1035 case TGSI_TOKEN_TYPE_PROPERTY:
1036 property = &ctx.parse.FullToken.FullProperty;
1037 switch (property->Property.PropertyName) {
1038 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1039 if (property->u[0].Data == 1)
1040 shader->fs_write_all = TRUE;
1041 break;
1042 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1043 /* we don't need this one */
1044 break;
1045 }
1046 break;
1047 default:
1048 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
1049 r = -EINVAL;
1050 goto out_err;
1051 }
1052 }
1053
1054 /* Process two side if needed */
1055 if (shader->two_side && ctx.colors_used) {
1056 int i, count = ctx.shader->ninput;
1057 unsigned next_lds_loc = ctx.shader->nlds;
1058
1059 /* additional inputs will be allocated right after the existing inputs,
1060 * we won't need them after the color selection, so we don't need to
1061 * reserve these gprs for the rest of the shader code and to adjust
1062 * output offsets etc. */
1063 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
1064 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1065
1066 if (ctx.face_gpr == -1) {
1067 i = ctx.shader->ninput++;
1068 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
1069 ctx.shader->input[i].spi_sid = 0;
1070 ctx.shader->input[i].gpr = gpr++;
1071 ctx.face_gpr = ctx.shader->input[i].gpr;
1072 }
1073
1074 for (i = 0; i < count; i++) {
1075 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1076 int ni = ctx.shader->ninput++;
1077 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
1078 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
1079 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
1080 ctx.shader->input[ni].gpr = gpr++;
1081 // TGSI to LLVM needs to know the lds position of inputs.
1082 // Non LLVM path computes it later (in process_twoside_color)
1083 ctx.shader->input[ni].lds_pos = next_lds_loc++;
1084 ctx.shader->input[i].back_color_input = ni;
1085 if (ctx.bc->chip_class >= EVERGREEN) {
1086 if ((r = evergreen_interp_input(&ctx, ni)))
1087 return r;
1088 }
1089 }
1090 }
1091 }
1092
1093 /* LLVM backend setup */
1094 #ifdef R600_USE_LLVM
1095 if (use_llvm) {
1096 struct radeon_llvm_context radeon_llvm_ctx;
1097 LLVMModuleRef mod;
1098 bool dump = r600_can_dump_shader(&rscreen->b, tokens);
1099 boolean use_kill = false;
1100
1101 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
1102 radeon_llvm_ctx.type = ctx.type;
1103 radeon_llvm_ctx.two_side = shader->two_side;
1104 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
1105 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
1106 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
1107 radeon_llvm_ctx.color_buffer_count = max_color_exports;
1108 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
1109 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN);
1110 radeon_llvm_ctx.stream_outputs = &so;
1111 radeon_llvm_ctx.clip_vertex = ctx.cv_output;
1112 radeon_llvm_ctx.alpha_to_one = key.alpha_to_one;
1113 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
1114 ctx.shader->has_txq_cube_array_z_comp = radeon_llvm_ctx.has_txq_cube_array_z_comp;
1115 ctx.shader->uses_tex_buffers = radeon_llvm_ctx.uses_tex_buffers;
1116
1117 if (r600_llvm_compile(mod, rscreen->b.family, ctx.bc, &use_kill, dump)) {
1118 radeon_llvm_dispose(&radeon_llvm_ctx);
1119 use_llvm = 0;
1120 fprintf(stderr, "R600 LLVM backend failed to compile "
1121 "shader. Falling back to TGSI\n");
1122 } else {
1123 ctx.file_offset[TGSI_FILE_OUTPUT] =
1124 ctx.file_offset[TGSI_FILE_INPUT];
1125 }
1126 if (use_kill)
1127 ctx.shader->uses_kill = use_kill;
1128 radeon_llvm_dispose(&radeon_llvm_ctx);
1129 }
1130 #endif
1131 /* End of LLVM backend setup */
1132
1133 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
1134 shader->nr_ps_max_color_exports = 8;
1135
1136 if (!use_llvm) {
1137 if (ctx.fragcoord_input >= 0) {
1138 if (ctx.bc->chip_class == CAYMAN) {
1139 for (j = 0 ; j < 4; j++) {
1140 struct r600_bytecode_alu alu;
1141 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1142 alu.op = ALU_OP1_RECIP_IEEE;
1143 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1144 alu.src[0].chan = 3;
1145
1146 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1147 alu.dst.chan = j;
1148 alu.dst.write = (j == 3);
1149 alu.last = 1;
1150 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1151 return r;
1152 }
1153 } else {
1154 struct r600_bytecode_alu alu;
1155 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1156 alu.op = ALU_OP1_RECIP_IEEE;
1157 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1158 alu.src[0].chan = 3;
1159
1160 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1161 alu.dst.chan = 3;
1162 alu.dst.write = 1;
1163 alu.last = 1;
1164 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1165 return r;
1166 }
1167 }
1168
1169 if (shader->two_side && ctx.colors_used) {
1170 if ((r = process_twoside_color_inputs(&ctx)))
1171 return r;
1172 }
1173
1174 tgsi_parse_init(&ctx.parse, tokens);
1175 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1176 tgsi_parse_token(&ctx.parse);
1177 switch (ctx.parse.FullToken.Token.Type) {
1178 case TGSI_TOKEN_TYPE_INSTRUCTION:
1179 r = tgsi_is_supported(&ctx);
1180 if (r)
1181 goto out_err;
1182 ctx.max_driver_temp_used = 0;
1183 /* reserve first tmp for everyone */
1184 r600_get_temp(&ctx);
1185
1186 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
1187 if ((r = tgsi_split_constant(&ctx)))
1188 goto out_err;
1189 if ((r = tgsi_split_literal_constant(&ctx)))
1190 goto out_err;
1191 if (ctx.bc->chip_class == CAYMAN)
1192 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
1193 else if (ctx.bc->chip_class >= EVERGREEN)
1194 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
1195 else
1196 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
1197 r = ctx.inst_info->process(&ctx);
1198 if (r)
1199 goto out_err;
1200 break;
1201 default:
1202 break;
1203 }
1204 }
1205 }
1206
1207 /* Reset the temporary register counter. */
1208 ctx.max_driver_temp_used = 0;
1209
1210 noutput = shader->noutput;
1211
1212 if (ctx.clip_vertex_write) {
1213 unsigned clipdist_temp[2];
1214
1215 clipdist_temp[0] = r600_get_temp(&ctx);
1216 clipdist_temp[1] = r600_get_temp(&ctx);
1217
1218 /* need to convert a clipvertex write into clipdistance writes and not export
1219 the clip vertex anymore */
1220
1221 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
1222 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1223 shader->output[noutput].gpr = clipdist_temp[0];
1224 noutput++;
1225 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1226 shader->output[noutput].gpr = clipdist_temp[1];
1227 noutput++;
1228
1229 /* reset spi_sid for clipvertex output to avoid confusing spi */
1230 shader->output[ctx.cv_output].spi_sid = 0;
1231
1232 shader->clip_dist_write = 0xFF;
1233
1234 for (i = 0; i < 8; i++) {
1235 int oreg = i >> 2;
1236 int ochan = i & 3;
1237
1238 for (j = 0; j < 4; j++) {
1239 struct r600_bytecode_alu alu;
1240 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1241 alu.op = ALU_OP2_DOT4;
1242 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
1243 alu.src[0].chan = j;
1244
1245 alu.src[1].sel = 512 + i;
1246 alu.src[1].kc_bank = R600_UCP_CONST_BUFFER;
1247 alu.src[1].chan = j;
1248
1249 alu.dst.sel = clipdist_temp[oreg];
1250 alu.dst.chan = j;
1251 alu.dst.write = (j == ochan);
1252 if (j == 3)
1253 alu.last = 1;
1254 if (!use_llvm)
1255 r = r600_bytecode_add_alu(ctx.bc, &alu);
1256 if (r)
1257 return r;
1258 }
1259 }
1260 }
1261
1262 /* Add stream outputs. */
1263 if (ctx.type == TGSI_PROCESSOR_VERTEX && so.num_outputs && !use_llvm) {
1264 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1265
1266 /* Sanity checking. */
1267 if (so.num_outputs > PIPE_MAX_SHADER_OUTPUTS) {
1268 R600_ERR("Too many stream outputs: %d\n", so.num_outputs);
1269 r = -EINVAL;
1270 goto out_err;
1271 }
1272 for (i = 0; i < so.num_outputs; i++) {
1273 if (so.output[i].output_buffer >= 4) {
1274 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1275 so.output[i].output_buffer);
1276 r = -EINVAL;
1277 goto out_err;
1278 }
1279 }
1280
1281 /* Initialize locations where the outputs are stored. */
1282 for (i = 0; i < so.num_outputs; i++) {
1283 so_gpr[i] = shader->output[so.output[i].register_index].gpr;
1284
1285 /* Lower outputs with dst_offset < start_component.
1286 *
1287 * We can only output 4D vectors with a write mask, e.g. we can
1288 * only output the W component at offset 3, etc. If we want
1289 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1290 * to move it to X and output X. */
1291 if (so.output[i].dst_offset < so.output[i].start_component) {
1292 unsigned tmp = r600_get_temp(&ctx);
1293
1294 for (j = 0; j < so.output[i].num_components; j++) {
1295 struct r600_bytecode_alu alu;
1296 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1297 alu.op = ALU_OP1_MOV;
1298 alu.src[0].sel = so_gpr[i];
1299 alu.src[0].chan = so.output[i].start_component + j;
1300
1301 alu.dst.sel = tmp;
1302 alu.dst.chan = j;
1303 alu.dst.write = 1;
1304 if (j == so.output[i].num_components - 1)
1305 alu.last = 1;
1306 r = r600_bytecode_add_alu(ctx.bc, &alu);
1307 if (r)
1308 return r;
1309 }
1310 so.output[i].start_component = 0;
1311 so_gpr[i] = tmp;
1312 }
1313 }
1314
1315 /* Write outputs to buffers. */
1316 for (i = 0; i < so.num_outputs; i++) {
1317 struct r600_bytecode_output output;
1318
1319 memset(&output, 0, sizeof(struct r600_bytecode_output));
1320 output.gpr = so_gpr[i];
1321 output.elem_size = so.output[i].num_components;
1322 output.array_base = so.output[i].dst_offset - so.output[i].start_component;
1323 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1324 output.burst_count = 1;
1325 output.barrier = 1;
1326 /* array_size is an upper limit for the burst_count
1327 * with MEM_STREAM instructions */
1328 output.array_size = 0xFFF;
1329 output.comp_mask = ((1 << so.output[i].num_components) - 1) << so.output[i].start_component;
1330 if (ctx.bc->chip_class >= EVERGREEN) {
1331 switch (so.output[i].output_buffer) {
1332 case 0:
1333 output.op = CF_OP_MEM_STREAM0_BUF0;
1334 break;
1335 case 1:
1336 output.op = CF_OP_MEM_STREAM0_BUF1;
1337 break;
1338 case 2:
1339 output.op = CF_OP_MEM_STREAM0_BUF2;
1340 break;
1341 case 3:
1342 output.op = CF_OP_MEM_STREAM0_BUF3;
1343 break;
1344 }
1345 } else {
1346 switch (so.output[i].output_buffer) {
1347 case 0:
1348 output.op = CF_OP_MEM_STREAM0;
1349 break;
1350 case 1:
1351 output.op = CF_OP_MEM_STREAM1;
1352 break;
1353 case 2:
1354 output.op = CF_OP_MEM_STREAM2;
1355 break;
1356 case 3:
1357 output.op = CF_OP_MEM_STREAM3;
1358 break;
1359 }
1360 }
1361 r = r600_bytecode_add_output(ctx.bc, &output);
1362 if (r)
1363 goto out_err;
1364 }
1365 }
1366
1367 /* export output */
1368 for (i = 0, j = 0; i < noutput; i++, j++) {
1369 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1370 output[j].gpr = shader->output[i].gpr;
1371 output[j].elem_size = 3;
1372 output[j].swizzle_x = 0;
1373 output[j].swizzle_y = 1;
1374 output[j].swizzle_z = 2;
1375 output[j].swizzle_w = 3;
1376 output[j].burst_count = 1;
1377 output[j].barrier = 1;
1378 output[j].type = -1;
1379 output[j].op = CF_OP_EXPORT;
1380 switch (ctx.type) {
1381 case TGSI_PROCESSOR_VERTEX:
1382 switch (shader->output[i].name) {
1383 case TGSI_SEMANTIC_POSITION:
1384 output[j].array_base = next_pos_base++;
1385 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1386 break;
1387
1388 case TGSI_SEMANTIC_PSIZE:
1389 output[j].array_base = next_pos_base++;
1390 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1391 break;
1392 case TGSI_SEMANTIC_CLIPVERTEX:
1393 j--;
1394 break;
1395 case TGSI_SEMANTIC_CLIPDIST:
1396 output[j].array_base = next_pos_base++;
1397 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1398 /* spi_sid is 0 for clipdistance outputs that were generated
1399 * for clipvertex - we don't need to pass them to PS */
1400 if (shader->output[i].spi_sid) {
1401 j++;
1402 /* duplicate it as PARAM to pass to the pixel shader */
1403 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
1404 output[j].array_base = next_param_base++;
1405 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1406 }
1407 break;
1408 case TGSI_SEMANTIC_FOG:
1409 output[j].swizzle_y = 4; /* 0 */
1410 output[j].swizzle_z = 4; /* 0 */
1411 output[j].swizzle_w = 5; /* 1 */
1412 break;
1413 }
1414 break;
1415 case TGSI_PROCESSOR_FRAGMENT:
1416 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
1417 /* never export more colors than the number of CBs */
1418 if (shader->output[i].sid >= max_color_exports) {
1419 /* skip export */
1420 j--;
1421 continue;
1422 }
1423 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1424 output[j].array_base = shader->output[i].sid;
1425 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1426 shader->nr_ps_color_exports++;
1427 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
1428 for (k = 1; k < max_color_exports; k++) {
1429 j++;
1430 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1431 output[j].gpr = shader->output[i].gpr;
1432 output[j].elem_size = 3;
1433 output[j].swizzle_x = 0;
1434 output[j].swizzle_y = 1;
1435 output[j].swizzle_z = 2;
1436 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1437 output[j].burst_count = 1;
1438 output[j].barrier = 1;
1439 output[j].array_base = k;
1440 output[j].op = CF_OP_EXPORT;
1441 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1442 shader->nr_ps_color_exports++;
1443 }
1444 }
1445 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
1446 output[j].array_base = 61;
1447 output[j].swizzle_x = 2;
1448 output[j].swizzle_y = 7;
1449 output[j].swizzle_z = output[j].swizzle_w = 7;
1450 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1451 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
1452 output[j].array_base = 61;
1453 output[j].swizzle_x = 7;
1454 output[j].swizzle_y = 1;
1455 output[j].swizzle_z = output[j].swizzle_w = 7;
1456 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1457 } else {
1458 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
1459 r = -EINVAL;
1460 goto out_err;
1461 }
1462 break;
1463 default:
1464 R600_ERR("unsupported processor type %d\n", ctx.type);
1465 r = -EINVAL;
1466 goto out_err;
1467 }
1468
1469 if (output[j].type==-1) {
1470 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1471 output[j].array_base = next_param_base++;
1472 }
1473 }
1474
1475 /* add fake position export */
1476 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_pos_base == 60) {
1477 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1478 output[j].gpr = 0;
1479 output[j].elem_size = 3;
1480 output[j].swizzle_x = 7;
1481 output[j].swizzle_y = 7;
1482 output[j].swizzle_z = 7;
1483 output[j].swizzle_w = 7;
1484 output[j].burst_count = 1;
1485 output[j].barrier = 1;
1486 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1487 output[j].array_base = next_pos_base;
1488 output[j].op = CF_OP_EXPORT;
1489 j++;
1490 }
1491
1492 /* add fake param output for vertex shader if no param is exported */
1493 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
1494 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1495 output[j].gpr = 0;
1496 output[j].elem_size = 3;
1497 output[j].swizzle_x = 7;
1498 output[j].swizzle_y = 7;
1499 output[j].swizzle_z = 7;
1500 output[j].swizzle_w = 7;
1501 output[j].burst_count = 1;
1502 output[j].barrier = 1;
1503 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1504 output[j].array_base = 0;
1505 output[j].op = CF_OP_EXPORT;
1506 j++;
1507 }
1508
1509 /* add fake pixel export */
1510 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && shader->nr_ps_color_exports == 0) {
1511 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1512 output[j].gpr = 0;
1513 output[j].elem_size = 3;
1514 output[j].swizzle_x = 7;
1515 output[j].swizzle_y = 7;
1516 output[j].swizzle_z = 7;
1517 output[j].swizzle_w = 7;
1518 output[j].burst_count = 1;
1519 output[j].barrier = 1;
1520 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1521 output[j].array_base = 0;
1522 output[j].op = CF_OP_EXPORT;
1523 j++;
1524 }
1525
1526 noutput = j;
1527
1528 /* set export done on last export of each type */
1529 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
1530 if (ctx.bc->chip_class < CAYMAN) {
1531 if (i == (noutput - 1)) {
1532 output[i].end_of_program = 1;
1533 }
1534 }
1535 if (!(output_done & (1 << output[i].type))) {
1536 output_done |= (1 << output[i].type);
1537 output[i].op = CF_OP_EXPORT_DONE;
1538 }
1539 }
1540 /* add output to bytecode */
1541 if (!use_llvm) {
1542 for (i = 0; i < noutput; i++) {
1543 r = r600_bytecode_add_output(ctx.bc, &output[i]);
1544 if (r)
1545 goto out_err;
1546 }
1547 }
1548 /* add program end */
1549 if (!use_llvm && ctx.bc->chip_class == CAYMAN)
1550 cm_bytecode_add_cf_end(ctx.bc);
1551
1552 /* check GPR limit - we have 124 = 128 - 4
1553 * (4 are reserved as alu clause temporary registers) */
1554 if (ctx.bc->ngpr > 124) {
1555 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
1556 r = -ENOMEM;
1557 goto out_err;
1558 }
1559
1560 free(ctx.literals);
1561 tgsi_parse_free(&ctx.parse);
1562 return 0;
1563 out_err:
1564 free(ctx.literals);
1565 tgsi_parse_free(&ctx.parse);
1566 return r;
1567 }
1568
1569 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
1570 {
1571 R600_ERR("%s tgsi opcode unsupported\n",
1572 tgsi_get_opcode_name(ctx->inst_info->tgsi_opcode));
1573 return -EINVAL;
1574 }
1575
1576 static int tgsi_end(struct r600_shader_ctx *ctx)
1577 {
1578 return 0;
1579 }
1580
1581 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
1582 const struct r600_shader_src *shader_src,
1583 unsigned chan)
1584 {
1585 bc_src->sel = shader_src->sel;
1586 bc_src->chan = shader_src->swizzle[chan];
1587 bc_src->neg = shader_src->neg;
1588 bc_src->abs = shader_src->abs;
1589 bc_src->rel = shader_src->rel;
1590 bc_src->value = shader_src->value[bc_src->chan];
1591 bc_src->kc_bank = shader_src->kc_bank;
1592 }
1593
1594 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
1595 {
1596 bc_src->abs = 1;
1597 bc_src->neg = 0;
1598 }
1599
1600 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
1601 {
1602 bc_src->neg = !bc_src->neg;
1603 }
1604
1605 static void tgsi_dst(struct r600_shader_ctx *ctx,
1606 const struct tgsi_full_dst_register *tgsi_dst,
1607 unsigned swizzle,
1608 struct r600_bytecode_alu_dst *r600_dst)
1609 {
1610 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1611
1612 r600_dst->sel = tgsi_dst->Register.Index;
1613 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
1614 r600_dst->chan = swizzle;
1615 r600_dst->write = 1;
1616 if (tgsi_dst->Register.Indirect)
1617 r600_dst->rel = V_SQ_REL_RELATIVE;
1618 if (inst->Instruction.Saturate) {
1619 r600_dst->clamp = 1;
1620 }
1621 }
1622
1623 static int tgsi_last_instruction(unsigned writemask)
1624 {
1625 int i, lasti = 0;
1626
1627 for (i = 0; i < 4; i++) {
1628 if (writemask & (1 << i)) {
1629 lasti = i;
1630 }
1631 }
1632 return lasti;
1633 }
1634
1635 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
1636 {
1637 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1638 struct r600_bytecode_alu alu;
1639 int i, j, r;
1640 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1641
1642 for (i = 0; i < lasti + 1; i++) {
1643 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1644 continue;
1645
1646 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1647 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1648
1649 alu.op = ctx->inst_info->op;
1650 if (!swap) {
1651 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1652 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
1653 }
1654 } else {
1655 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
1656 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1657 }
1658 /* handle some special cases */
1659 switch (ctx->inst_info->tgsi_opcode) {
1660 case TGSI_OPCODE_SUB:
1661 r600_bytecode_src_toggle_neg(&alu.src[1]);
1662 break;
1663 case TGSI_OPCODE_ABS:
1664 r600_bytecode_src_set_abs(&alu.src[0]);
1665 break;
1666 default:
1667 break;
1668 }
1669 if (i == lasti || trans_only) {
1670 alu.last = 1;
1671 }
1672 r = r600_bytecode_add_alu(ctx->bc, &alu);
1673 if (r)
1674 return r;
1675 }
1676 return 0;
1677 }
1678
1679 static int tgsi_op2(struct r600_shader_ctx *ctx)
1680 {
1681 return tgsi_op2_s(ctx, 0, 0);
1682 }
1683
1684 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
1685 {
1686 return tgsi_op2_s(ctx, 1, 0);
1687 }
1688
1689 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
1690 {
1691 return tgsi_op2_s(ctx, 0, 1);
1692 }
1693
1694 static int tgsi_ineg(struct r600_shader_ctx *ctx)
1695 {
1696 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1697 struct r600_bytecode_alu alu;
1698 int i, r;
1699 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1700
1701 for (i = 0; i < lasti + 1; i++) {
1702
1703 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1704 continue;
1705 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1706 alu.op = ctx->inst_info->op;
1707
1708 alu.src[0].sel = V_SQ_ALU_SRC_0;
1709
1710 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1711
1712 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1713
1714 if (i == lasti) {
1715 alu.last = 1;
1716 }
1717 r = r600_bytecode_add_alu(ctx->bc, &alu);
1718 if (r)
1719 return r;
1720 }
1721 return 0;
1722
1723 }
1724
1725 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
1726 {
1727 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1728 int i, j, r;
1729 struct r600_bytecode_alu alu;
1730 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1731
1732 for (i = 0 ; i < last_slot; i++) {
1733 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1734 alu.op = ctx->inst_info->op;
1735 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1736 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
1737
1738 /* RSQ should take the absolute value of src */
1739 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_RSQ) {
1740 r600_bytecode_src_set_abs(&alu.src[j]);
1741 }
1742 }
1743 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1744 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1745
1746 if (i == last_slot - 1)
1747 alu.last = 1;
1748 r = r600_bytecode_add_alu(ctx->bc, &alu);
1749 if (r)
1750 return r;
1751 }
1752 return 0;
1753 }
1754
1755 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
1756 {
1757 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1758 int i, j, k, r;
1759 struct r600_bytecode_alu alu;
1760 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1761 for (k = 0; k < last_slot; k++) {
1762 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
1763 continue;
1764
1765 for (i = 0 ; i < 4; i++) {
1766 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1767 alu.op = ctx->inst_info->op;
1768 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1769 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
1770 }
1771 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1772 alu.dst.write = (i == k);
1773 if (i == 3)
1774 alu.last = 1;
1775 r = r600_bytecode_add_alu(ctx->bc, &alu);
1776 if (r)
1777 return r;
1778 }
1779 }
1780 return 0;
1781 }
1782
1783 /*
1784 * r600 - trunc to -PI..PI range
1785 * r700 - normalize by dividing by 2PI
1786 * see fdo bug 27901
1787 */
1788 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
1789 {
1790 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
1791 static float double_pi = 3.1415926535 * 2;
1792 static float neg_pi = -3.1415926535;
1793
1794 int r;
1795 struct r600_bytecode_alu alu;
1796
1797 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1798 alu.op = ALU_OP3_MULADD;
1799 alu.is_op3 = 1;
1800
1801 alu.dst.chan = 0;
1802 alu.dst.sel = ctx->temp_reg;
1803 alu.dst.write = 1;
1804
1805 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
1806
1807 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1808 alu.src[1].chan = 0;
1809 alu.src[1].value = *(uint32_t *)&half_inv_pi;
1810 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1811 alu.src[2].chan = 0;
1812 alu.last = 1;
1813 r = r600_bytecode_add_alu(ctx->bc, &alu);
1814 if (r)
1815 return r;
1816
1817 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1818 alu.op = ALU_OP1_FRACT;
1819
1820 alu.dst.chan = 0;
1821 alu.dst.sel = ctx->temp_reg;
1822 alu.dst.write = 1;
1823
1824 alu.src[0].sel = ctx->temp_reg;
1825 alu.src[0].chan = 0;
1826 alu.last = 1;
1827 r = r600_bytecode_add_alu(ctx->bc, &alu);
1828 if (r)
1829 return r;
1830
1831 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1832 alu.op = ALU_OP3_MULADD;
1833 alu.is_op3 = 1;
1834
1835 alu.dst.chan = 0;
1836 alu.dst.sel = ctx->temp_reg;
1837 alu.dst.write = 1;
1838
1839 alu.src[0].sel = ctx->temp_reg;
1840 alu.src[0].chan = 0;
1841
1842 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1843 alu.src[1].chan = 0;
1844 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1845 alu.src[2].chan = 0;
1846
1847 if (ctx->bc->chip_class == R600) {
1848 alu.src[1].value = *(uint32_t *)&double_pi;
1849 alu.src[2].value = *(uint32_t *)&neg_pi;
1850 } else {
1851 alu.src[1].sel = V_SQ_ALU_SRC_1;
1852 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1853 alu.src[2].neg = 1;
1854 }
1855
1856 alu.last = 1;
1857 r = r600_bytecode_add_alu(ctx->bc, &alu);
1858 if (r)
1859 return r;
1860 return 0;
1861 }
1862
1863 static int cayman_trig(struct r600_shader_ctx *ctx)
1864 {
1865 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1866 struct r600_bytecode_alu alu;
1867 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1868 int i, r;
1869
1870 r = tgsi_setup_trig(ctx);
1871 if (r)
1872 return r;
1873
1874
1875 for (i = 0; i < last_slot; i++) {
1876 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1877 alu.op = ctx->inst_info->op;
1878 alu.dst.chan = i;
1879
1880 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1881 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1882
1883 alu.src[0].sel = ctx->temp_reg;
1884 alu.src[0].chan = 0;
1885 if (i == last_slot - 1)
1886 alu.last = 1;
1887 r = r600_bytecode_add_alu(ctx->bc, &alu);
1888 if (r)
1889 return r;
1890 }
1891 return 0;
1892 }
1893
1894 static int tgsi_trig(struct r600_shader_ctx *ctx)
1895 {
1896 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1897 struct r600_bytecode_alu alu;
1898 int i, r;
1899 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1900
1901 r = tgsi_setup_trig(ctx);
1902 if (r)
1903 return r;
1904
1905 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1906 alu.op = ctx->inst_info->op;
1907 alu.dst.chan = 0;
1908 alu.dst.sel = ctx->temp_reg;
1909 alu.dst.write = 1;
1910
1911 alu.src[0].sel = ctx->temp_reg;
1912 alu.src[0].chan = 0;
1913 alu.last = 1;
1914 r = r600_bytecode_add_alu(ctx->bc, &alu);
1915 if (r)
1916 return r;
1917
1918 /* replicate result */
1919 for (i = 0; i < lasti + 1; i++) {
1920 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1921 continue;
1922
1923 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1924 alu.op = ALU_OP1_MOV;
1925
1926 alu.src[0].sel = ctx->temp_reg;
1927 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1928 if (i == lasti)
1929 alu.last = 1;
1930 r = r600_bytecode_add_alu(ctx->bc, &alu);
1931 if (r)
1932 return r;
1933 }
1934 return 0;
1935 }
1936
1937 static int tgsi_scs(struct r600_shader_ctx *ctx)
1938 {
1939 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1940 struct r600_bytecode_alu alu;
1941 int i, r;
1942
1943 /* We'll only need the trig stuff if we are going to write to the
1944 * X or Y components of the destination vector.
1945 */
1946 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1947 r = tgsi_setup_trig(ctx);
1948 if (r)
1949 return r;
1950 }
1951
1952 /* dst.x = COS */
1953 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1954 if (ctx->bc->chip_class == CAYMAN) {
1955 for (i = 0 ; i < 3; i++) {
1956 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1957 alu.op = ALU_OP1_COS;
1958 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1959
1960 if (i == 0)
1961 alu.dst.write = 1;
1962 else
1963 alu.dst.write = 0;
1964 alu.src[0].sel = ctx->temp_reg;
1965 alu.src[0].chan = 0;
1966 if (i == 2)
1967 alu.last = 1;
1968 r = r600_bytecode_add_alu(ctx->bc, &alu);
1969 if (r)
1970 return r;
1971 }
1972 } else {
1973 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1974 alu.op = ALU_OP1_COS;
1975 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1976
1977 alu.src[0].sel = ctx->temp_reg;
1978 alu.src[0].chan = 0;
1979 alu.last = 1;
1980 r = r600_bytecode_add_alu(ctx->bc, &alu);
1981 if (r)
1982 return r;
1983 }
1984 }
1985
1986 /* dst.y = SIN */
1987 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1988 if (ctx->bc->chip_class == CAYMAN) {
1989 for (i = 0 ; i < 3; i++) {
1990 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1991 alu.op = ALU_OP1_SIN;
1992 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1993 if (i == 1)
1994 alu.dst.write = 1;
1995 else
1996 alu.dst.write = 0;
1997 alu.src[0].sel = ctx->temp_reg;
1998 alu.src[0].chan = 0;
1999 if (i == 2)
2000 alu.last = 1;
2001 r = r600_bytecode_add_alu(ctx->bc, &alu);
2002 if (r)
2003 return r;
2004 }
2005 } else {
2006 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2007 alu.op = ALU_OP1_SIN;
2008 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2009
2010 alu.src[0].sel = ctx->temp_reg;
2011 alu.src[0].chan = 0;
2012 alu.last = 1;
2013 r = r600_bytecode_add_alu(ctx->bc, &alu);
2014 if (r)
2015 return r;
2016 }
2017 }
2018
2019 /* dst.z = 0.0; */
2020 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2021 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2022
2023 alu.op = ALU_OP1_MOV;
2024
2025 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2026
2027 alu.src[0].sel = V_SQ_ALU_SRC_0;
2028 alu.src[0].chan = 0;
2029
2030 alu.last = 1;
2031
2032 r = r600_bytecode_add_alu(ctx->bc, &alu);
2033 if (r)
2034 return r;
2035 }
2036
2037 /* dst.w = 1.0; */
2038 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2039 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2040
2041 alu.op = ALU_OP1_MOV;
2042
2043 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2044
2045 alu.src[0].sel = V_SQ_ALU_SRC_1;
2046 alu.src[0].chan = 0;
2047
2048 alu.last = 1;
2049
2050 r = r600_bytecode_add_alu(ctx->bc, &alu);
2051 if (r)
2052 return r;
2053 }
2054
2055 return 0;
2056 }
2057
2058 static int tgsi_kill(struct r600_shader_ctx *ctx)
2059 {
2060 struct r600_bytecode_alu alu;
2061 int i, r;
2062
2063 for (i = 0; i < 4; i++) {
2064 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2065 alu.op = ctx->inst_info->op;
2066
2067 alu.dst.chan = i;
2068
2069 alu.src[0].sel = V_SQ_ALU_SRC_0;
2070
2071 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILL) {
2072 alu.src[1].sel = V_SQ_ALU_SRC_1;
2073 alu.src[1].neg = 1;
2074 } else {
2075 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2076 }
2077 if (i == 3) {
2078 alu.last = 1;
2079 }
2080 r = r600_bytecode_add_alu(ctx->bc, &alu);
2081 if (r)
2082 return r;
2083 }
2084
2085 /* kill must be last in ALU */
2086 ctx->bc->force_add_cf = 1;
2087 ctx->shader->uses_kill = TRUE;
2088 return 0;
2089 }
2090
2091 static int tgsi_lit(struct r600_shader_ctx *ctx)
2092 {
2093 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2094 struct r600_bytecode_alu alu;
2095 int r;
2096
2097 /* tmp.x = max(src.y, 0.0) */
2098 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2099 alu.op = ALU_OP2_MAX;
2100 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
2101 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2102 alu.src[1].chan = 1;
2103
2104 alu.dst.sel = ctx->temp_reg;
2105 alu.dst.chan = 0;
2106 alu.dst.write = 1;
2107
2108 alu.last = 1;
2109 r = r600_bytecode_add_alu(ctx->bc, &alu);
2110 if (r)
2111 return r;
2112
2113 if (inst->Dst[0].Register.WriteMask & (1 << 2))
2114 {
2115 int chan;
2116 int sel;
2117 int i;
2118
2119 if (ctx->bc->chip_class == CAYMAN) {
2120 for (i = 0; i < 3; i++) {
2121 /* tmp.z = log(tmp.x) */
2122 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2123 alu.op = ALU_OP1_LOG_CLAMPED;
2124 alu.src[0].sel = ctx->temp_reg;
2125 alu.src[0].chan = 0;
2126 alu.dst.sel = ctx->temp_reg;
2127 alu.dst.chan = i;
2128 if (i == 2) {
2129 alu.dst.write = 1;
2130 alu.last = 1;
2131 } else
2132 alu.dst.write = 0;
2133
2134 r = r600_bytecode_add_alu(ctx->bc, &alu);
2135 if (r)
2136 return r;
2137 }
2138 } else {
2139 /* tmp.z = log(tmp.x) */
2140 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2141 alu.op = ALU_OP1_LOG_CLAMPED;
2142 alu.src[0].sel = ctx->temp_reg;
2143 alu.src[0].chan = 0;
2144 alu.dst.sel = ctx->temp_reg;
2145 alu.dst.chan = 2;
2146 alu.dst.write = 1;
2147 alu.last = 1;
2148 r = r600_bytecode_add_alu(ctx->bc, &alu);
2149 if (r)
2150 return r;
2151 }
2152
2153 chan = alu.dst.chan;
2154 sel = alu.dst.sel;
2155
2156 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
2157 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2158 alu.op = ALU_OP3_MUL_LIT;
2159 alu.src[0].sel = sel;
2160 alu.src[0].chan = chan;
2161 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
2162 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
2163 alu.dst.sel = ctx->temp_reg;
2164 alu.dst.chan = 0;
2165 alu.dst.write = 1;
2166 alu.is_op3 = 1;
2167 alu.last = 1;
2168 r = r600_bytecode_add_alu(ctx->bc, &alu);
2169 if (r)
2170 return r;
2171
2172 if (ctx->bc->chip_class == CAYMAN) {
2173 for (i = 0; i < 3; i++) {
2174 /* dst.z = exp(tmp.x) */
2175 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2176 alu.op = ALU_OP1_EXP_IEEE;
2177 alu.src[0].sel = ctx->temp_reg;
2178 alu.src[0].chan = 0;
2179 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2180 if (i == 2) {
2181 alu.dst.write = 1;
2182 alu.last = 1;
2183 } else
2184 alu.dst.write = 0;
2185 r = r600_bytecode_add_alu(ctx->bc, &alu);
2186 if (r)
2187 return r;
2188 }
2189 } else {
2190 /* dst.z = exp(tmp.x) */
2191 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2192 alu.op = ALU_OP1_EXP_IEEE;
2193 alu.src[0].sel = ctx->temp_reg;
2194 alu.src[0].chan = 0;
2195 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2196 alu.last = 1;
2197 r = r600_bytecode_add_alu(ctx->bc, &alu);
2198 if (r)
2199 return r;
2200 }
2201 }
2202
2203 /* dst.x, <- 1.0 */
2204 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2205 alu.op = ALU_OP1_MOV;
2206 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
2207 alu.src[0].chan = 0;
2208 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2209 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
2210 r = r600_bytecode_add_alu(ctx->bc, &alu);
2211 if (r)
2212 return r;
2213
2214 /* dst.y = max(src.x, 0.0) */
2215 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2216 alu.op = ALU_OP2_MAX;
2217 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2218 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2219 alu.src[1].chan = 0;
2220 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2221 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
2222 r = r600_bytecode_add_alu(ctx->bc, &alu);
2223 if (r)
2224 return r;
2225
2226 /* dst.w, <- 1.0 */
2227 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2228 alu.op = ALU_OP1_MOV;
2229 alu.src[0].sel = V_SQ_ALU_SRC_1;
2230 alu.src[0].chan = 0;
2231 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2232 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
2233 alu.last = 1;
2234 r = r600_bytecode_add_alu(ctx->bc, &alu);
2235 if (r)
2236 return r;
2237
2238 return 0;
2239 }
2240
2241 static int tgsi_rsq(struct r600_shader_ctx *ctx)
2242 {
2243 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2244 struct r600_bytecode_alu alu;
2245 int i, r;
2246
2247 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2248
2249 /* XXX:
2250 * For state trackers other than OpenGL, we'll want to use
2251 * _RECIPSQRT_IEEE instead.
2252 */
2253 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
2254
2255 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2256 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2257 r600_bytecode_src_set_abs(&alu.src[i]);
2258 }
2259 alu.dst.sel = ctx->temp_reg;
2260 alu.dst.write = 1;
2261 alu.last = 1;
2262 r = r600_bytecode_add_alu(ctx->bc, &alu);
2263 if (r)
2264 return r;
2265 /* replicate result */
2266 return tgsi_helper_tempx_replicate(ctx);
2267 }
2268
2269 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
2270 {
2271 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2272 struct r600_bytecode_alu alu;
2273 int i, r;
2274
2275 for (i = 0; i < 4; i++) {
2276 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2277 alu.src[0].sel = ctx->temp_reg;
2278 alu.op = ALU_OP1_MOV;
2279 alu.dst.chan = i;
2280 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2281 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2282 if (i == 3)
2283 alu.last = 1;
2284 r = r600_bytecode_add_alu(ctx->bc, &alu);
2285 if (r)
2286 return r;
2287 }
2288 return 0;
2289 }
2290
2291 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
2292 {
2293 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2294 struct r600_bytecode_alu alu;
2295 int i, r;
2296
2297 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2298 alu.op = ctx->inst_info->op;
2299 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2300 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2301 }
2302 alu.dst.sel = ctx->temp_reg;
2303 alu.dst.write = 1;
2304 alu.last = 1;
2305 r = r600_bytecode_add_alu(ctx->bc, &alu);
2306 if (r)
2307 return r;
2308 /* replicate result */
2309 return tgsi_helper_tempx_replicate(ctx);
2310 }
2311
2312 static int cayman_pow(struct r600_shader_ctx *ctx)
2313 {
2314 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2315 int i, r;
2316 struct r600_bytecode_alu alu;
2317 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2318
2319 for (i = 0; i < 3; i++) {
2320 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2321 alu.op = ALU_OP1_LOG_IEEE;
2322 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2323 alu.dst.sel = ctx->temp_reg;
2324 alu.dst.chan = i;
2325 alu.dst.write = 1;
2326 if (i == 2)
2327 alu.last = 1;
2328 r = r600_bytecode_add_alu(ctx->bc, &alu);
2329 if (r)
2330 return r;
2331 }
2332
2333 /* b * LOG2(a) */
2334 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2335 alu.op = ALU_OP2_MUL;
2336 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2337 alu.src[1].sel = ctx->temp_reg;
2338 alu.dst.sel = ctx->temp_reg;
2339 alu.dst.write = 1;
2340 alu.last = 1;
2341 r = r600_bytecode_add_alu(ctx->bc, &alu);
2342 if (r)
2343 return r;
2344
2345 for (i = 0; i < last_slot; i++) {
2346 /* POW(a,b) = EXP2(b * LOG2(a))*/
2347 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2348 alu.op = ALU_OP1_EXP_IEEE;
2349 alu.src[0].sel = ctx->temp_reg;
2350
2351 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2352 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2353 if (i == last_slot - 1)
2354 alu.last = 1;
2355 r = r600_bytecode_add_alu(ctx->bc, &alu);
2356 if (r)
2357 return r;
2358 }
2359 return 0;
2360 }
2361
2362 static int tgsi_pow(struct r600_shader_ctx *ctx)
2363 {
2364 struct r600_bytecode_alu alu;
2365 int r;
2366
2367 /* LOG2(a) */
2368 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2369 alu.op = ALU_OP1_LOG_IEEE;
2370 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2371 alu.dst.sel = ctx->temp_reg;
2372 alu.dst.write = 1;
2373 alu.last = 1;
2374 r = r600_bytecode_add_alu(ctx->bc, &alu);
2375 if (r)
2376 return r;
2377 /* b * LOG2(a) */
2378 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2379 alu.op = ALU_OP2_MUL;
2380 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2381 alu.src[1].sel = ctx->temp_reg;
2382 alu.dst.sel = ctx->temp_reg;
2383 alu.dst.write = 1;
2384 alu.last = 1;
2385 r = r600_bytecode_add_alu(ctx->bc, &alu);
2386 if (r)
2387 return r;
2388 /* POW(a,b) = EXP2(b * LOG2(a))*/
2389 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2390 alu.op = ALU_OP1_EXP_IEEE;
2391 alu.src[0].sel = ctx->temp_reg;
2392 alu.dst.sel = ctx->temp_reg;
2393 alu.dst.write = 1;
2394 alu.last = 1;
2395 r = r600_bytecode_add_alu(ctx->bc, &alu);
2396 if (r)
2397 return r;
2398 return tgsi_helper_tempx_replicate(ctx);
2399 }
2400
2401 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
2402 {
2403 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2404 struct r600_bytecode_alu alu;
2405 int i, r, j;
2406 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2407 int tmp0 = ctx->temp_reg;
2408 int tmp1 = r600_get_temp(ctx);
2409 int tmp2 = r600_get_temp(ctx);
2410 int tmp3 = r600_get_temp(ctx);
2411 /* Unsigned path:
2412 *
2413 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
2414 *
2415 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
2416 * 2. tmp0.z = lo (tmp0.x * src2)
2417 * 3. tmp0.w = -tmp0.z
2418 * 4. tmp0.y = hi (tmp0.x * src2)
2419 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
2420 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
2421 * 7. tmp1.x = tmp0.x - tmp0.w
2422 * 8. tmp1.y = tmp0.x + tmp0.w
2423 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
2424 * 10. tmp0.z = hi(tmp0.x * src1) = q
2425 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
2426 *
2427 * 12. tmp0.w = src1 - tmp0.y = r
2428 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
2429 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
2430 *
2431 * if DIV
2432 *
2433 * 15. tmp1.z = tmp0.z + 1 = q + 1
2434 * 16. tmp1.w = tmp0.z - 1 = q - 1
2435 *
2436 * else MOD
2437 *
2438 * 15. tmp1.z = tmp0.w - src2 = r - src2
2439 * 16. tmp1.w = tmp0.w + src2 = r + src2
2440 *
2441 * endif
2442 *
2443 * 17. tmp1.x = tmp1.x & tmp1.y
2444 *
2445 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
2446 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
2447 *
2448 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
2449 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
2450 *
2451 * Signed path:
2452 *
2453 * Same as unsigned, using abs values of the operands,
2454 * and fixing the sign of the result in the end.
2455 */
2456
2457 for (i = 0; i < 4; i++) {
2458 if (!(write_mask & (1<<i)))
2459 continue;
2460
2461 if (signed_op) {
2462
2463 /* tmp2.x = -src0 */
2464 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2465 alu.op = ALU_OP2_SUB_INT;
2466
2467 alu.dst.sel = tmp2;
2468 alu.dst.chan = 0;
2469 alu.dst.write = 1;
2470
2471 alu.src[0].sel = V_SQ_ALU_SRC_0;
2472
2473 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2474
2475 alu.last = 1;
2476 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2477 return r;
2478
2479 /* tmp2.y = -src1 */
2480 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2481 alu.op = ALU_OP2_SUB_INT;
2482
2483 alu.dst.sel = tmp2;
2484 alu.dst.chan = 1;
2485 alu.dst.write = 1;
2486
2487 alu.src[0].sel = V_SQ_ALU_SRC_0;
2488
2489 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2490
2491 alu.last = 1;
2492 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2493 return r;
2494
2495 /* tmp2.z sign bit is set if src0 and src2 signs are different */
2496 /* it will be a sign of the quotient */
2497 if (!mod) {
2498
2499 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2500 alu.op = ALU_OP2_XOR_INT;
2501
2502 alu.dst.sel = tmp2;
2503 alu.dst.chan = 2;
2504 alu.dst.write = 1;
2505
2506 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2507 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2508
2509 alu.last = 1;
2510 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2511 return r;
2512 }
2513
2514 /* tmp2.x = |src0| */
2515 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2516 alu.op = ALU_OP3_CNDGE_INT;
2517 alu.is_op3 = 1;
2518
2519 alu.dst.sel = tmp2;
2520 alu.dst.chan = 0;
2521 alu.dst.write = 1;
2522
2523 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2524 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2525 alu.src[2].sel = tmp2;
2526 alu.src[2].chan = 0;
2527
2528 alu.last = 1;
2529 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2530 return r;
2531
2532 /* tmp2.y = |src1| */
2533 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2534 alu.op = ALU_OP3_CNDGE_INT;
2535 alu.is_op3 = 1;
2536
2537 alu.dst.sel = tmp2;
2538 alu.dst.chan = 1;
2539 alu.dst.write = 1;
2540
2541 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2542 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2543 alu.src[2].sel = tmp2;
2544 alu.src[2].chan = 1;
2545
2546 alu.last = 1;
2547 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2548 return r;
2549
2550 }
2551
2552 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
2553 if (ctx->bc->chip_class == CAYMAN) {
2554 /* tmp3.x = u2f(src2) */
2555 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2556 alu.op = ALU_OP1_UINT_TO_FLT;
2557
2558 alu.dst.sel = tmp3;
2559 alu.dst.chan = 0;
2560 alu.dst.write = 1;
2561
2562 if (signed_op) {
2563 alu.src[0].sel = tmp2;
2564 alu.src[0].chan = 1;
2565 } else {
2566 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2567 }
2568
2569 alu.last = 1;
2570 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2571 return r;
2572
2573 /* tmp0.x = recip(tmp3.x) */
2574 for (j = 0 ; j < 3; j++) {
2575 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2576 alu.op = ALU_OP1_RECIP_IEEE;
2577
2578 alu.dst.sel = tmp0;
2579 alu.dst.chan = j;
2580 alu.dst.write = (j == 0);
2581
2582 alu.src[0].sel = tmp3;
2583 alu.src[0].chan = 0;
2584
2585 if (j == 2)
2586 alu.last = 1;
2587 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2588 return r;
2589 }
2590
2591 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2592 alu.op = ALU_OP2_MUL;
2593
2594 alu.src[0].sel = tmp0;
2595 alu.src[0].chan = 0;
2596
2597 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2598 alu.src[1].value = 0x4f800000;
2599
2600 alu.dst.sel = tmp3;
2601 alu.dst.write = 1;
2602 alu.last = 1;
2603 r = r600_bytecode_add_alu(ctx->bc, &alu);
2604 if (r)
2605 return r;
2606
2607 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2608 alu.op = ALU_OP1_FLT_TO_UINT;
2609
2610 alu.dst.sel = tmp0;
2611 alu.dst.chan = 0;
2612 alu.dst.write = 1;
2613
2614 alu.src[0].sel = tmp3;
2615 alu.src[0].chan = 0;
2616
2617 alu.last = 1;
2618 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2619 return r;
2620
2621 } else {
2622 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2623 alu.op = ALU_OP1_RECIP_UINT;
2624
2625 alu.dst.sel = tmp0;
2626 alu.dst.chan = 0;
2627 alu.dst.write = 1;
2628
2629 if (signed_op) {
2630 alu.src[0].sel = tmp2;
2631 alu.src[0].chan = 1;
2632 } else {
2633 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2634 }
2635
2636 alu.last = 1;
2637 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2638 return r;
2639 }
2640
2641 /* 2. tmp0.z = lo (tmp0.x * src2) */
2642 if (ctx->bc->chip_class == CAYMAN) {
2643 for (j = 0 ; j < 4; j++) {
2644 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2645 alu.op = ALU_OP2_MULLO_UINT;
2646
2647 alu.dst.sel = tmp0;
2648 alu.dst.chan = j;
2649 alu.dst.write = (j == 2);
2650
2651 alu.src[0].sel = tmp0;
2652 alu.src[0].chan = 0;
2653 if (signed_op) {
2654 alu.src[1].sel = tmp2;
2655 alu.src[1].chan = 1;
2656 } else {
2657 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2658 }
2659
2660 alu.last = (j == 3);
2661 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2662 return r;
2663 }
2664 } else {
2665 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2666 alu.op = ALU_OP2_MULLO_UINT;
2667
2668 alu.dst.sel = tmp0;
2669 alu.dst.chan = 2;
2670 alu.dst.write = 1;
2671
2672 alu.src[0].sel = tmp0;
2673 alu.src[0].chan = 0;
2674 if (signed_op) {
2675 alu.src[1].sel = tmp2;
2676 alu.src[1].chan = 1;
2677 } else {
2678 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2679 }
2680
2681 alu.last = 1;
2682 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2683 return r;
2684 }
2685
2686 /* 3. tmp0.w = -tmp0.z */
2687 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2688 alu.op = ALU_OP2_SUB_INT;
2689
2690 alu.dst.sel = tmp0;
2691 alu.dst.chan = 3;
2692 alu.dst.write = 1;
2693
2694 alu.src[0].sel = V_SQ_ALU_SRC_0;
2695 alu.src[1].sel = tmp0;
2696 alu.src[1].chan = 2;
2697
2698 alu.last = 1;
2699 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2700 return r;
2701
2702 /* 4. tmp0.y = hi (tmp0.x * src2) */
2703 if (ctx->bc->chip_class == CAYMAN) {
2704 for (j = 0 ; j < 4; j++) {
2705 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2706 alu.op = ALU_OP2_MULHI_UINT;
2707
2708 alu.dst.sel = tmp0;
2709 alu.dst.chan = j;
2710 alu.dst.write = (j == 1);
2711
2712 alu.src[0].sel = tmp0;
2713 alu.src[0].chan = 0;
2714
2715 if (signed_op) {
2716 alu.src[1].sel = tmp2;
2717 alu.src[1].chan = 1;
2718 } else {
2719 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2720 }
2721 alu.last = (j == 3);
2722 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2723 return r;
2724 }
2725 } else {
2726 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2727 alu.op = ALU_OP2_MULHI_UINT;
2728
2729 alu.dst.sel = tmp0;
2730 alu.dst.chan = 1;
2731 alu.dst.write = 1;
2732
2733 alu.src[0].sel = tmp0;
2734 alu.src[0].chan = 0;
2735
2736 if (signed_op) {
2737 alu.src[1].sel = tmp2;
2738 alu.src[1].chan = 1;
2739 } else {
2740 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2741 }
2742
2743 alu.last = 1;
2744 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2745 return r;
2746 }
2747
2748 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
2749 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2750 alu.op = ALU_OP3_CNDE_INT;
2751 alu.is_op3 = 1;
2752
2753 alu.dst.sel = tmp0;
2754 alu.dst.chan = 2;
2755 alu.dst.write = 1;
2756
2757 alu.src[0].sel = tmp0;
2758 alu.src[0].chan = 1;
2759 alu.src[1].sel = tmp0;
2760 alu.src[1].chan = 3;
2761 alu.src[2].sel = tmp0;
2762 alu.src[2].chan = 2;
2763
2764 alu.last = 1;
2765 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2766 return r;
2767
2768 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
2769 if (ctx->bc->chip_class == CAYMAN) {
2770 for (j = 0 ; j < 4; j++) {
2771 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2772 alu.op = ALU_OP2_MULHI_UINT;
2773
2774 alu.dst.sel = tmp0;
2775 alu.dst.chan = j;
2776 alu.dst.write = (j == 3);
2777
2778 alu.src[0].sel = tmp0;
2779 alu.src[0].chan = 2;
2780
2781 alu.src[1].sel = tmp0;
2782 alu.src[1].chan = 0;
2783
2784 alu.last = (j == 3);
2785 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2786 return r;
2787 }
2788 } else {
2789 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2790 alu.op = ALU_OP2_MULHI_UINT;
2791
2792 alu.dst.sel = tmp0;
2793 alu.dst.chan = 3;
2794 alu.dst.write = 1;
2795
2796 alu.src[0].sel = tmp0;
2797 alu.src[0].chan = 2;
2798
2799 alu.src[1].sel = tmp0;
2800 alu.src[1].chan = 0;
2801
2802 alu.last = 1;
2803 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2804 return r;
2805 }
2806
2807 /* 7. tmp1.x = tmp0.x - tmp0.w */
2808 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2809 alu.op = ALU_OP2_SUB_INT;
2810
2811 alu.dst.sel = tmp1;
2812 alu.dst.chan = 0;
2813 alu.dst.write = 1;
2814
2815 alu.src[0].sel = tmp0;
2816 alu.src[0].chan = 0;
2817 alu.src[1].sel = tmp0;
2818 alu.src[1].chan = 3;
2819
2820 alu.last = 1;
2821 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2822 return r;
2823
2824 /* 8. tmp1.y = tmp0.x + tmp0.w */
2825 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2826 alu.op = ALU_OP2_ADD_INT;
2827
2828 alu.dst.sel = tmp1;
2829 alu.dst.chan = 1;
2830 alu.dst.write = 1;
2831
2832 alu.src[0].sel = tmp0;
2833 alu.src[0].chan = 0;
2834 alu.src[1].sel = tmp0;
2835 alu.src[1].chan = 3;
2836
2837 alu.last = 1;
2838 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2839 return r;
2840
2841 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
2842 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2843 alu.op = ALU_OP3_CNDE_INT;
2844 alu.is_op3 = 1;
2845
2846 alu.dst.sel = tmp0;
2847 alu.dst.chan = 0;
2848 alu.dst.write = 1;
2849
2850 alu.src[0].sel = tmp0;
2851 alu.src[0].chan = 1;
2852 alu.src[1].sel = tmp1;
2853 alu.src[1].chan = 1;
2854 alu.src[2].sel = tmp1;
2855 alu.src[2].chan = 0;
2856
2857 alu.last = 1;
2858 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2859 return r;
2860
2861 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
2862 if (ctx->bc->chip_class == CAYMAN) {
2863 for (j = 0 ; j < 4; j++) {
2864 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2865 alu.op = ALU_OP2_MULHI_UINT;
2866
2867 alu.dst.sel = tmp0;
2868 alu.dst.chan = j;
2869 alu.dst.write = (j == 2);
2870
2871 alu.src[0].sel = tmp0;
2872 alu.src[0].chan = 0;
2873
2874 if (signed_op) {
2875 alu.src[1].sel = tmp2;
2876 alu.src[1].chan = 0;
2877 } else {
2878 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2879 }
2880
2881 alu.last = (j == 3);
2882 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2883 return r;
2884 }
2885 } else {
2886 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2887 alu.op = ALU_OP2_MULHI_UINT;
2888
2889 alu.dst.sel = tmp0;
2890 alu.dst.chan = 2;
2891 alu.dst.write = 1;
2892
2893 alu.src[0].sel = tmp0;
2894 alu.src[0].chan = 0;
2895
2896 if (signed_op) {
2897 alu.src[1].sel = tmp2;
2898 alu.src[1].chan = 0;
2899 } else {
2900 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2901 }
2902
2903 alu.last = 1;
2904 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2905 return r;
2906 }
2907
2908 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
2909 if (ctx->bc->chip_class == CAYMAN) {
2910 for (j = 0 ; j < 4; j++) {
2911 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2912 alu.op = ALU_OP2_MULLO_UINT;
2913
2914 alu.dst.sel = tmp0;
2915 alu.dst.chan = j;
2916 alu.dst.write = (j == 1);
2917
2918 if (signed_op) {
2919 alu.src[0].sel = tmp2;
2920 alu.src[0].chan = 1;
2921 } else {
2922 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2923 }
2924
2925 alu.src[1].sel = tmp0;
2926 alu.src[1].chan = 2;
2927
2928 alu.last = (j == 3);
2929 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2930 return r;
2931 }
2932 } else {
2933 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2934 alu.op = ALU_OP2_MULLO_UINT;
2935
2936 alu.dst.sel = tmp0;
2937 alu.dst.chan = 1;
2938 alu.dst.write = 1;
2939
2940 if (signed_op) {
2941 alu.src[0].sel = tmp2;
2942 alu.src[0].chan = 1;
2943 } else {
2944 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2945 }
2946
2947 alu.src[1].sel = tmp0;
2948 alu.src[1].chan = 2;
2949
2950 alu.last = 1;
2951 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2952 return r;
2953 }
2954
2955 /* 12. tmp0.w = src1 - tmp0.y = r */
2956 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2957 alu.op = ALU_OP2_SUB_INT;
2958
2959 alu.dst.sel = tmp0;
2960 alu.dst.chan = 3;
2961 alu.dst.write = 1;
2962
2963 if (signed_op) {
2964 alu.src[0].sel = tmp2;
2965 alu.src[0].chan = 0;
2966 } else {
2967 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2968 }
2969
2970 alu.src[1].sel = tmp0;
2971 alu.src[1].chan = 1;
2972
2973 alu.last = 1;
2974 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2975 return r;
2976
2977 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
2978 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2979 alu.op = ALU_OP2_SETGE_UINT;
2980
2981 alu.dst.sel = tmp1;
2982 alu.dst.chan = 0;
2983 alu.dst.write = 1;
2984
2985 alu.src[0].sel = tmp0;
2986 alu.src[0].chan = 3;
2987 if (signed_op) {
2988 alu.src[1].sel = tmp2;
2989 alu.src[1].chan = 1;
2990 } else {
2991 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2992 }
2993
2994 alu.last = 1;
2995 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2996 return r;
2997
2998 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
2999 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3000 alu.op = ALU_OP2_SETGE_UINT;
3001
3002 alu.dst.sel = tmp1;
3003 alu.dst.chan = 1;
3004 alu.dst.write = 1;
3005
3006 if (signed_op) {
3007 alu.src[0].sel = tmp2;
3008 alu.src[0].chan = 0;
3009 } else {
3010 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3011 }
3012
3013 alu.src[1].sel = tmp0;
3014 alu.src[1].chan = 1;
3015
3016 alu.last = 1;
3017 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3018 return r;
3019
3020 if (mod) { /* UMOD */
3021
3022 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
3023 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3024 alu.op = ALU_OP2_SUB_INT;
3025
3026 alu.dst.sel = tmp1;
3027 alu.dst.chan = 2;
3028 alu.dst.write = 1;
3029
3030 alu.src[0].sel = tmp0;
3031 alu.src[0].chan = 3;
3032
3033 if (signed_op) {
3034 alu.src[1].sel = tmp2;
3035 alu.src[1].chan = 1;
3036 } else {
3037 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3038 }
3039
3040 alu.last = 1;
3041 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3042 return r;
3043
3044 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
3045 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3046 alu.op = ALU_OP2_ADD_INT;
3047
3048 alu.dst.sel = tmp1;
3049 alu.dst.chan = 3;
3050 alu.dst.write = 1;
3051
3052 alu.src[0].sel = tmp0;
3053 alu.src[0].chan = 3;
3054 if (signed_op) {
3055 alu.src[1].sel = tmp2;
3056 alu.src[1].chan = 1;
3057 } else {
3058 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3059 }
3060
3061 alu.last = 1;
3062 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3063 return r;
3064
3065 } else { /* UDIV */
3066
3067 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
3068 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3069 alu.op = ALU_OP2_ADD_INT;
3070
3071 alu.dst.sel = tmp1;
3072 alu.dst.chan = 2;
3073 alu.dst.write = 1;
3074
3075 alu.src[0].sel = tmp0;
3076 alu.src[0].chan = 2;
3077 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3078
3079 alu.last = 1;
3080 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3081 return r;
3082
3083 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
3084 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3085 alu.op = ALU_OP2_ADD_INT;
3086
3087 alu.dst.sel = tmp1;
3088 alu.dst.chan = 3;
3089 alu.dst.write = 1;
3090
3091 alu.src[0].sel = tmp0;
3092 alu.src[0].chan = 2;
3093 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
3094
3095 alu.last = 1;
3096 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3097 return r;
3098
3099 }
3100
3101 /* 17. tmp1.x = tmp1.x & tmp1.y */
3102 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3103 alu.op = ALU_OP2_AND_INT;
3104
3105 alu.dst.sel = tmp1;
3106 alu.dst.chan = 0;
3107 alu.dst.write = 1;
3108
3109 alu.src[0].sel = tmp1;
3110 alu.src[0].chan = 0;
3111 alu.src[1].sel = tmp1;
3112 alu.src[1].chan = 1;
3113
3114 alu.last = 1;
3115 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3116 return r;
3117
3118 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
3119 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
3120 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3121 alu.op = ALU_OP3_CNDE_INT;
3122 alu.is_op3 = 1;
3123
3124 alu.dst.sel = tmp0;
3125 alu.dst.chan = 2;
3126 alu.dst.write = 1;
3127
3128 alu.src[0].sel = tmp1;
3129 alu.src[0].chan = 0;
3130 alu.src[1].sel = tmp0;
3131 alu.src[1].chan = mod ? 3 : 2;
3132 alu.src[2].sel = tmp1;
3133 alu.src[2].chan = 2;
3134
3135 alu.last = 1;
3136 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3137 return r;
3138
3139 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
3140 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3141 alu.op = ALU_OP3_CNDE_INT;
3142 alu.is_op3 = 1;
3143
3144 if (signed_op) {
3145 alu.dst.sel = tmp0;
3146 alu.dst.chan = 2;
3147 alu.dst.write = 1;
3148 } else {
3149 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3150 }
3151
3152 alu.src[0].sel = tmp1;
3153 alu.src[0].chan = 1;
3154 alu.src[1].sel = tmp1;
3155 alu.src[1].chan = 3;
3156 alu.src[2].sel = tmp0;
3157 alu.src[2].chan = 2;
3158
3159 alu.last = 1;
3160 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3161 return r;
3162
3163 if (signed_op) {
3164
3165 /* fix the sign of the result */
3166
3167 if (mod) {
3168
3169 /* tmp0.x = -tmp0.z */
3170 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3171 alu.op = ALU_OP2_SUB_INT;
3172
3173 alu.dst.sel = tmp0;
3174 alu.dst.chan = 0;
3175 alu.dst.write = 1;
3176
3177 alu.src[0].sel = V_SQ_ALU_SRC_0;
3178 alu.src[1].sel = tmp0;
3179 alu.src[1].chan = 2;
3180
3181 alu.last = 1;
3182 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3183 return r;
3184
3185 /* sign of the remainder is the same as the sign of src0 */
3186 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
3187 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3188 alu.op = ALU_OP3_CNDGE_INT;
3189 alu.is_op3 = 1;
3190
3191 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3192
3193 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3194 alu.src[1].sel = tmp0;
3195 alu.src[1].chan = 2;
3196 alu.src[2].sel = tmp0;
3197 alu.src[2].chan = 0;
3198
3199 alu.last = 1;
3200 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3201 return r;
3202
3203 } else {
3204
3205 /* tmp0.x = -tmp0.z */
3206 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3207 alu.op = ALU_OP2_SUB_INT;
3208
3209 alu.dst.sel = tmp0;
3210 alu.dst.chan = 0;
3211 alu.dst.write = 1;
3212
3213 alu.src[0].sel = V_SQ_ALU_SRC_0;
3214 alu.src[1].sel = tmp0;
3215 alu.src[1].chan = 2;
3216
3217 alu.last = 1;
3218 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3219 return r;
3220
3221 /* fix the quotient sign (same as the sign of src0*src1) */
3222 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
3223 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3224 alu.op = ALU_OP3_CNDGE_INT;
3225 alu.is_op3 = 1;
3226
3227 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3228
3229 alu.src[0].sel = tmp2;
3230 alu.src[0].chan = 2;
3231 alu.src[1].sel = tmp0;
3232 alu.src[1].chan = 2;
3233 alu.src[2].sel = tmp0;
3234 alu.src[2].chan = 0;
3235
3236 alu.last = 1;
3237 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3238 return r;
3239 }
3240 }
3241 }
3242 return 0;
3243 }
3244
3245 static int tgsi_udiv(struct r600_shader_ctx *ctx)
3246 {
3247 return tgsi_divmod(ctx, 0, 0);
3248 }
3249
3250 static int tgsi_umod(struct r600_shader_ctx *ctx)
3251 {
3252 return tgsi_divmod(ctx, 1, 0);
3253 }
3254
3255 static int tgsi_idiv(struct r600_shader_ctx *ctx)
3256 {
3257 return tgsi_divmod(ctx, 0, 1);
3258 }
3259
3260 static int tgsi_imod(struct r600_shader_ctx *ctx)
3261 {
3262 return tgsi_divmod(ctx, 1, 1);
3263 }
3264
3265
3266 static int tgsi_f2i(struct r600_shader_ctx *ctx)
3267 {
3268 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3269 struct r600_bytecode_alu alu;
3270 int i, r;
3271 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3272 int last_inst = tgsi_last_instruction(write_mask);
3273
3274 for (i = 0; i < 4; i++) {
3275 if (!(write_mask & (1<<i)))
3276 continue;
3277
3278 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3279 alu.op = ALU_OP1_TRUNC;
3280
3281 alu.dst.sel = ctx->temp_reg;
3282 alu.dst.chan = i;
3283 alu.dst.write = 1;
3284
3285 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3286 if (i == last_inst)
3287 alu.last = 1;
3288 r = r600_bytecode_add_alu(ctx->bc, &alu);
3289 if (r)
3290 return r;
3291 }
3292
3293 for (i = 0; i < 4; i++) {
3294 if (!(write_mask & (1<<i)))
3295 continue;
3296
3297 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3298 alu.op = ctx->inst_info->op;
3299
3300 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3301
3302 alu.src[0].sel = ctx->temp_reg;
3303 alu.src[0].chan = i;
3304
3305 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
3306 alu.last = 1;
3307 r = r600_bytecode_add_alu(ctx->bc, &alu);
3308 if (r)
3309 return r;
3310 }
3311
3312 return 0;
3313 }
3314
3315 static int tgsi_iabs(struct r600_shader_ctx *ctx)
3316 {
3317 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3318 struct r600_bytecode_alu alu;
3319 int i, r;
3320 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3321 int last_inst = tgsi_last_instruction(write_mask);
3322
3323 /* tmp = -src */
3324 for (i = 0; i < 4; i++) {
3325 if (!(write_mask & (1<<i)))
3326 continue;
3327
3328 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3329 alu.op = ALU_OP2_SUB_INT;
3330
3331 alu.dst.sel = ctx->temp_reg;
3332 alu.dst.chan = i;
3333 alu.dst.write = 1;
3334
3335 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3336 alu.src[0].sel = V_SQ_ALU_SRC_0;
3337
3338 if (i == last_inst)
3339 alu.last = 1;
3340 r = r600_bytecode_add_alu(ctx->bc, &alu);
3341 if (r)
3342 return r;
3343 }
3344
3345 /* dst = (src >= 0 ? src : tmp) */
3346 for (i = 0; i < 4; i++) {
3347 if (!(write_mask & (1<<i)))
3348 continue;
3349
3350 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3351 alu.op = ALU_OP3_CNDGE_INT;
3352 alu.is_op3 = 1;
3353 alu.dst.write = 1;
3354
3355 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3356
3357 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3358 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3359 alu.src[2].sel = ctx->temp_reg;
3360 alu.src[2].chan = i;
3361
3362 if (i == last_inst)
3363 alu.last = 1;
3364 r = r600_bytecode_add_alu(ctx->bc, &alu);
3365 if (r)
3366 return r;
3367 }
3368 return 0;
3369 }
3370
3371 static int tgsi_issg(struct r600_shader_ctx *ctx)
3372 {
3373 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3374 struct r600_bytecode_alu alu;
3375 int i, r;
3376 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3377 int last_inst = tgsi_last_instruction(write_mask);
3378
3379 /* tmp = (src >= 0 ? src : -1) */
3380 for (i = 0; i < 4; i++) {
3381 if (!(write_mask & (1<<i)))
3382 continue;
3383
3384 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3385 alu.op = ALU_OP3_CNDGE_INT;
3386 alu.is_op3 = 1;
3387
3388 alu.dst.sel = ctx->temp_reg;
3389 alu.dst.chan = i;
3390 alu.dst.write = 1;
3391
3392 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3393 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3394 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
3395
3396 if (i == last_inst)
3397 alu.last = 1;
3398 r = r600_bytecode_add_alu(ctx->bc, &alu);
3399 if (r)
3400 return r;
3401 }
3402
3403 /* dst = (tmp > 0 ? 1 : tmp) */
3404 for (i = 0; i < 4; i++) {
3405 if (!(write_mask & (1<<i)))
3406 continue;
3407
3408 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3409 alu.op = ALU_OP3_CNDGT_INT;
3410 alu.is_op3 = 1;
3411 alu.dst.write = 1;
3412
3413 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3414
3415 alu.src[0].sel = ctx->temp_reg;
3416 alu.src[0].chan = i;
3417
3418 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3419
3420 alu.src[2].sel = ctx->temp_reg;
3421 alu.src[2].chan = i;
3422
3423 if (i == last_inst)
3424 alu.last = 1;
3425 r = r600_bytecode_add_alu(ctx->bc, &alu);
3426 if (r)
3427 return r;
3428 }
3429 return 0;
3430 }
3431
3432
3433
3434 static int tgsi_ssg(struct r600_shader_ctx *ctx)
3435 {
3436 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3437 struct r600_bytecode_alu alu;
3438 int i, r;
3439
3440 /* tmp = (src > 0 ? 1 : src) */
3441 for (i = 0; i < 4; i++) {
3442 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3443 alu.op = ALU_OP3_CNDGT;
3444 alu.is_op3 = 1;
3445
3446 alu.dst.sel = ctx->temp_reg;
3447 alu.dst.chan = i;
3448
3449 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3450 alu.src[1].sel = V_SQ_ALU_SRC_1;
3451 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
3452
3453 if (i == 3)
3454 alu.last = 1;
3455 r = r600_bytecode_add_alu(ctx->bc, &alu);
3456 if (r)
3457 return r;
3458 }
3459
3460 /* dst = (-tmp > 0 ? -1 : tmp) */
3461 for (i = 0; i < 4; i++) {
3462 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3463 alu.op = ALU_OP3_CNDGT;
3464 alu.is_op3 = 1;
3465 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3466
3467 alu.src[0].sel = ctx->temp_reg;
3468 alu.src[0].chan = i;
3469 alu.src[0].neg = 1;
3470
3471 alu.src[1].sel = V_SQ_ALU_SRC_1;
3472 alu.src[1].neg = 1;
3473
3474 alu.src[2].sel = ctx->temp_reg;
3475 alu.src[2].chan = i;
3476
3477 if (i == 3)
3478 alu.last = 1;
3479 r = r600_bytecode_add_alu(ctx->bc, &alu);
3480 if (r)
3481 return r;
3482 }
3483 return 0;
3484 }
3485
3486 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
3487 {
3488 struct r600_bytecode_alu alu;
3489 int i, r;
3490
3491 for (i = 0; i < 4; i++) {
3492 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3493 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
3494 alu.op = ALU_OP0_NOP;
3495 alu.dst.chan = i;
3496 } else {
3497 alu.op = ALU_OP1_MOV;
3498 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3499 alu.src[0].sel = ctx->temp_reg;
3500 alu.src[0].chan = i;
3501 }
3502 if (i == 3) {
3503 alu.last = 1;
3504 }
3505 r = r600_bytecode_add_alu(ctx->bc, &alu);
3506 if (r)
3507 return r;
3508 }
3509 return 0;
3510 }
3511
3512 static int tgsi_op3(struct r600_shader_ctx *ctx)
3513 {
3514 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3515 struct r600_bytecode_alu alu;
3516 int i, j, r;
3517 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3518
3519 for (i = 0; i < lasti + 1; i++) {
3520 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3521 continue;
3522
3523 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3524 alu.op = ctx->inst_info->op;
3525 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3526 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3527 }
3528
3529 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3530 alu.dst.chan = i;
3531 alu.dst.write = 1;
3532 alu.is_op3 = 1;
3533 if (i == lasti) {
3534 alu.last = 1;
3535 }
3536 r = r600_bytecode_add_alu(ctx->bc, &alu);
3537 if (r)
3538 return r;
3539 }
3540 return 0;
3541 }
3542
3543 static int tgsi_dp(struct r600_shader_ctx *ctx)
3544 {
3545 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3546 struct r600_bytecode_alu alu;
3547 int i, j, r;
3548
3549 for (i = 0; i < 4; i++) {
3550 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3551 alu.op = ctx->inst_info->op;
3552 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3553 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3554 }
3555
3556 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3557 alu.dst.chan = i;
3558 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3559 /* handle some special cases */
3560 switch (ctx->inst_info->tgsi_opcode) {
3561 case TGSI_OPCODE_DP2:
3562 if (i > 1) {
3563 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3564 alu.src[0].chan = alu.src[1].chan = 0;
3565 }
3566 break;
3567 case TGSI_OPCODE_DP3:
3568 if (i > 2) {
3569 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3570 alu.src[0].chan = alu.src[1].chan = 0;
3571 }
3572 break;
3573 case TGSI_OPCODE_DPH:
3574 if (i == 3) {
3575 alu.src[0].sel = V_SQ_ALU_SRC_1;
3576 alu.src[0].chan = 0;
3577 alu.src[0].neg = 0;
3578 }
3579 break;
3580 default:
3581 break;
3582 }
3583 if (i == 3) {
3584 alu.last = 1;
3585 }
3586 r = r600_bytecode_add_alu(ctx->bc, &alu);
3587 if (r)
3588 return r;
3589 }
3590 return 0;
3591 }
3592
3593 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
3594 unsigned index)
3595 {
3596 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3597 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
3598 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
3599 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
3600 ctx->src[index].neg || ctx->src[index].abs;
3601 }
3602
3603 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
3604 unsigned index)
3605 {
3606 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3607 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
3608 }
3609
3610 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
3611 {
3612 struct r600_bytecode_vtx vtx;
3613 struct r600_bytecode_alu alu;
3614 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3615 int src_gpr, r, i;
3616 int id = tgsi_tex_get_src_gpr(ctx, 1);
3617
3618 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
3619 if (src_requires_loading) {
3620 for (i = 0; i < 4; i++) {
3621 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3622 alu.op = ALU_OP1_MOV;
3623 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3624 alu.dst.sel = ctx->temp_reg;
3625 alu.dst.chan = i;
3626 if (i == 3)
3627 alu.last = 1;
3628 alu.dst.write = 1;
3629 r = r600_bytecode_add_alu(ctx->bc, &alu);
3630 if (r)
3631 return r;
3632 }
3633 src_gpr = ctx->temp_reg;
3634 }
3635
3636 memset(&vtx, 0, sizeof(vtx));
3637 vtx.op = FETCH_OP_VFETCH;
3638 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
3639 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
3640 vtx.src_gpr = src_gpr;
3641 vtx.mega_fetch_count = 16;
3642 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
3643 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
3644 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
3645 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
3646 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
3647 vtx.use_const_fields = 1;
3648 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
3649
3650 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
3651 return r;
3652
3653 if (ctx->bc->chip_class >= EVERGREEN)
3654 return 0;
3655
3656 for (i = 0; i < 4; i++) {
3657 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3658 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3659 continue;
3660
3661 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3662 alu.op = ALU_OP2_AND_INT;
3663
3664 alu.dst.chan = i;
3665 alu.dst.sel = vtx.dst_gpr;
3666 alu.dst.write = 1;
3667
3668 alu.src[0].sel = vtx.dst_gpr;
3669 alu.src[0].chan = i;
3670
3671 alu.src[1].sel = 512 + (id * 2);
3672 alu.src[1].chan = i % 4;
3673 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3674
3675 if (i == lasti)
3676 alu.last = 1;
3677 r = r600_bytecode_add_alu(ctx->bc, &alu);
3678 if (r)
3679 return r;
3680 }
3681
3682 if (inst->Dst[0].Register.WriteMask & 3) {
3683 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3684 alu.op = ALU_OP2_OR_INT;
3685
3686 alu.dst.chan = 3;
3687 alu.dst.sel = vtx.dst_gpr;
3688 alu.dst.write = 1;
3689
3690 alu.src[0].sel = vtx.dst_gpr;
3691 alu.src[0].chan = 3;
3692
3693 alu.src[1].sel = 512 + (id * 2) + 1;
3694 alu.src[1].chan = 0;
3695 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3696
3697 alu.last = 1;
3698 r = r600_bytecode_add_alu(ctx->bc, &alu);
3699 if (r)
3700 return r;
3701 }
3702 return 0;
3703 }
3704
3705 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
3706 {
3707 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3708 struct r600_bytecode_alu alu;
3709 int r;
3710 int id = tgsi_tex_get_src_gpr(ctx, 1);
3711
3712 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3713 alu.op = ALU_OP1_MOV;
3714
3715 if (ctx->bc->chip_class >= EVERGREEN) {
3716 alu.src[0].sel = 512 + (id / 4);
3717 alu.src[0].chan = id % 4;
3718 } else {
3719 /* r600 we have them at channel 2 of the second dword */
3720 alu.src[0].sel = 512 + (id * 2) + 1;
3721 alu.src[0].chan = 1;
3722 }
3723 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3724 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3725 alu.last = 1;
3726 r = r600_bytecode_add_alu(ctx->bc, &alu);
3727 if (r)
3728 return r;
3729 return 0;
3730 }
3731
3732 static int tgsi_tex(struct r600_shader_ctx *ctx)
3733 {
3734 static float one_point_five = 1.5f;
3735 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3736 struct r600_bytecode_tex tex;
3737 struct r600_bytecode_alu alu;
3738 unsigned src_gpr;
3739 int r, i, j;
3740 int opcode;
3741 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
3742 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
3743 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
3744 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
3745
3746 /* Texture fetch instructions can only use gprs as source.
3747 * Also they cannot negate the source or take the absolute value */
3748 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
3749 tgsi_tex_src_requires_loading(ctx, 0)) ||
3750 read_compressed_msaa;
3751 boolean src_loaded = FALSE;
3752 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
3753 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
3754 boolean has_txq_cube_array_z = false;
3755
3756 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
3757 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
3758 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
3759 if (inst->Dst[0].Register.WriteMask & 4) {
3760 ctx->shader->has_txq_cube_array_z_comp = true;
3761 has_txq_cube_array_z = true;
3762 }
3763
3764 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
3765 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
3766 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
3767 sampler_src_reg = 2;
3768
3769 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
3770
3771 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
3772 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
3773 ctx->shader->uses_tex_buffers = true;
3774 return r600_do_buffer_txq(ctx);
3775 }
3776 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
3777 if (ctx->bc->chip_class < EVERGREEN)
3778 ctx->shader->uses_tex_buffers = true;
3779 return do_vtx_fetch_inst(ctx, src_requires_loading);
3780 }
3781 }
3782
3783 if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
3784 /* get offset values */
3785 if (inst->Texture.NumOffsets) {
3786 assert(inst->Texture.NumOffsets == 1);
3787
3788 offset_x = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
3789 offset_y = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
3790 offset_z = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
3791 }
3792 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
3793 /* TGSI moves the sampler to src reg 3 for TXD */
3794 sampler_src_reg = 3;
3795
3796 for (i = 1; i < 3; i++) {
3797 /* set gradients h/v */
3798 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
3799 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
3800 FETCH_OP_SET_GRADIENTS_V;
3801 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
3802 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
3803
3804 if (tgsi_tex_src_requires_loading(ctx, i)) {
3805 tex.src_gpr = r600_get_temp(ctx);
3806 tex.src_sel_x = 0;
3807 tex.src_sel_y = 1;
3808 tex.src_sel_z = 2;
3809 tex.src_sel_w = 3;
3810
3811 for (j = 0; j < 4; j++) {
3812 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3813 alu.op = ALU_OP1_MOV;
3814 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
3815 alu.dst.sel = tex.src_gpr;
3816 alu.dst.chan = j;
3817 if (j == 3)
3818 alu.last = 1;
3819 alu.dst.write = 1;
3820 r = r600_bytecode_add_alu(ctx->bc, &alu);
3821 if (r)
3822 return r;
3823 }
3824
3825 } else {
3826 tex.src_gpr = tgsi_tex_get_src_gpr(ctx, i);
3827 tex.src_sel_x = ctx->src[i].swizzle[0];
3828 tex.src_sel_y = ctx->src[i].swizzle[1];
3829 tex.src_sel_z = ctx->src[i].swizzle[2];
3830 tex.src_sel_w = ctx->src[i].swizzle[3];
3831 tex.src_rel = ctx->src[i].rel;
3832 }
3833 tex.dst_gpr = ctx->temp_reg; /* just to avoid confusing the asm scheduler */
3834 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
3835 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
3836 tex.coord_type_x = 1;
3837 tex.coord_type_y = 1;
3838 tex.coord_type_z = 1;
3839 tex.coord_type_w = 1;
3840 }
3841 r = r600_bytecode_add_tex(ctx->bc, &tex);
3842 if (r)
3843 return r;
3844 }
3845 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
3846 int out_chan;
3847 /* Add perspective divide */
3848 if (ctx->bc->chip_class == CAYMAN) {
3849 out_chan = 2;
3850 for (i = 0; i < 3; i++) {
3851 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3852 alu.op = ALU_OP1_RECIP_IEEE;
3853 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3854
3855 alu.dst.sel = ctx->temp_reg;
3856 alu.dst.chan = i;
3857 if (i == 2)
3858 alu.last = 1;
3859 if (out_chan == i)
3860 alu.dst.write = 1;
3861 r = r600_bytecode_add_alu(ctx->bc, &alu);
3862 if (r)
3863 return r;
3864 }
3865
3866 } else {
3867 out_chan = 3;
3868 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3869 alu.op = ALU_OP1_RECIP_IEEE;
3870 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3871
3872 alu.dst.sel = ctx->temp_reg;
3873 alu.dst.chan = out_chan;
3874 alu.last = 1;
3875 alu.dst.write = 1;
3876 r = r600_bytecode_add_alu(ctx->bc, &alu);
3877 if (r)
3878 return r;
3879 }
3880
3881 for (i = 0; i < 3; i++) {
3882 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3883 alu.op = ALU_OP2_MUL;
3884 alu.src[0].sel = ctx->temp_reg;
3885 alu.src[0].chan = out_chan;
3886 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3887 alu.dst.sel = ctx->temp_reg;
3888 alu.dst.chan = i;
3889 alu.dst.write = 1;
3890 r = r600_bytecode_add_alu(ctx->bc, &alu);
3891 if (r)
3892 return r;
3893 }
3894 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3895 alu.op = ALU_OP1_MOV;
3896 alu.src[0].sel = V_SQ_ALU_SRC_1;
3897 alu.src[0].chan = 0;
3898 alu.dst.sel = ctx->temp_reg;
3899 alu.dst.chan = 3;
3900 alu.last = 1;
3901 alu.dst.write = 1;
3902 r = r600_bytecode_add_alu(ctx->bc, &alu);
3903 if (r)
3904 return r;
3905 src_loaded = TRUE;
3906 src_gpr = ctx->temp_reg;
3907 }
3908
3909 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
3910 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
3911 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
3912 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
3913 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
3914 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
3915
3916 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
3917 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
3918
3919 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
3920 for (i = 0; i < 4; i++) {
3921 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3922 alu.op = ALU_OP2_CUBE;
3923 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
3924 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
3925 alu.dst.sel = ctx->temp_reg;
3926 alu.dst.chan = i;
3927 if (i == 3)
3928 alu.last = 1;
3929 alu.dst.write = 1;
3930 r = r600_bytecode_add_alu(ctx->bc, &alu);
3931 if (r)
3932 return r;
3933 }
3934
3935 /* tmp1.z = RCP_e(|tmp1.z|) */
3936 if (ctx->bc->chip_class == CAYMAN) {
3937 for (i = 0; i < 3; i++) {
3938 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3939 alu.op = ALU_OP1_RECIP_IEEE;
3940 alu.src[0].sel = ctx->temp_reg;
3941 alu.src[0].chan = 2;
3942 alu.src[0].abs = 1;
3943 alu.dst.sel = ctx->temp_reg;
3944 alu.dst.chan = i;
3945 if (i == 2)
3946 alu.dst.write = 1;
3947 if (i == 2)
3948 alu.last = 1;
3949 r = r600_bytecode_add_alu(ctx->bc, &alu);
3950 if (r)
3951 return r;
3952 }
3953 } else {
3954 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3955 alu.op = ALU_OP1_RECIP_IEEE;
3956 alu.src[0].sel = ctx->temp_reg;
3957 alu.src[0].chan = 2;
3958 alu.src[0].abs = 1;
3959 alu.dst.sel = ctx->temp_reg;
3960 alu.dst.chan = 2;
3961 alu.dst.write = 1;
3962 alu.last = 1;
3963 r = r600_bytecode_add_alu(ctx->bc, &alu);
3964 if (r)
3965 return r;
3966 }
3967
3968 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
3969 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
3970 * muladd has no writemask, have to use another temp
3971 */
3972 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3973 alu.op = ALU_OP3_MULADD;
3974 alu.is_op3 = 1;
3975
3976 alu.src[0].sel = ctx->temp_reg;
3977 alu.src[0].chan = 0;
3978 alu.src[1].sel = ctx->temp_reg;
3979 alu.src[1].chan = 2;
3980
3981 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
3982 alu.src[2].chan = 0;
3983 alu.src[2].value = *(uint32_t *)&one_point_five;
3984
3985 alu.dst.sel = ctx->temp_reg;
3986 alu.dst.chan = 0;
3987 alu.dst.write = 1;
3988
3989 r = r600_bytecode_add_alu(ctx->bc, &alu);
3990 if (r)
3991 return r;
3992
3993 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3994 alu.op = ALU_OP3_MULADD;
3995 alu.is_op3 = 1;
3996
3997 alu.src[0].sel = ctx->temp_reg;
3998 alu.src[0].chan = 1;
3999 alu.src[1].sel = ctx->temp_reg;
4000 alu.src[1].chan = 2;
4001
4002 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4003 alu.src[2].chan = 0;
4004 alu.src[2].value = *(uint32_t *)&one_point_five;
4005
4006 alu.dst.sel = ctx->temp_reg;
4007 alu.dst.chan = 1;
4008 alu.dst.write = 1;
4009
4010 alu.last = 1;
4011 r = r600_bytecode_add_alu(ctx->bc, &alu);
4012 if (r)
4013 return r;
4014 /* write initial compare value into Z component
4015 - W src 0 for shadow cube
4016 - X src 1 for shadow cube array */
4017 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4018 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4019 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4020 alu.op = ALU_OP1_MOV;
4021 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4022 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4023 else
4024 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4025 alu.dst.sel = ctx->temp_reg;
4026 alu.dst.chan = 2;
4027 alu.dst.write = 1;
4028 alu.last = 1;
4029 r = r600_bytecode_add_alu(ctx->bc, &alu);
4030 if (r)
4031 return r;
4032 }
4033
4034 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4035 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4036 if (ctx->bc->chip_class >= EVERGREEN) {
4037 int mytmp = r600_get_temp(ctx);
4038 static const float eight = 8.0f;
4039 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4040 alu.op = ALU_OP1_MOV;
4041 alu.src[0].sel = ctx->temp_reg;
4042 alu.src[0].chan = 3;
4043 alu.dst.sel = mytmp;
4044 alu.dst.chan = 0;
4045 alu.dst.write = 1;
4046 alu.last = 1;
4047 r = r600_bytecode_add_alu(ctx->bc, &alu);
4048 if (r)
4049 return r;
4050
4051 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
4052 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4053 alu.op = ALU_OP3_MULADD;
4054 alu.is_op3 = 1;
4055 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4056 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4057 alu.src[1].chan = 0;
4058 alu.src[1].value = *(uint32_t *)&eight;
4059 alu.src[2].sel = mytmp;
4060 alu.src[2].chan = 0;
4061 alu.dst.sel = ctx->temp_reg;
4062 alu.dst.chan = 3;
4063 alu.dst.write = 1;
4064 alu.last = 1;
4065 r = r600_bytecode_add_alu(ctx->bc, &alu);
4066 if (r)
4067 return r;
4068 } else if (ctx->bc->chip_class < EVERGREEN) {
4069 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4070 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
4071 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4072 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4073 tex.src_gpr = r600_get_temp(ctx);
4074 tex.src_sel_x = 0;
4075 tex.src_sel_y = 0;
4076 tex.src_sel_z = 0;
4077 tex.src_sel_w = 0;
4078 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4079 tex.coord_type_x = 1;
4080 tex.coord_type_y = 1;
4081 tex.coord_type_z = 1;
4082 tex.coord_type_w = 1;
4083 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4084 alu.op = ALU_OP1_MOV;
4085 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4086 alu.dst.sel = tex.src_gpr;
4087 alu.dst.chan = 0;
4088 alu.last = 1;
4089 alu.dst.write = 1;
4090 r = r600_bytecode_add_alu(ctx->bc, &alu);
4091 if (r)
4092 return r;
4093
4094 r = r600_bytecode_add_tex(ctx->bc, &tex);
4095 if (r)
4096 return r;
4097 }
4098
4099 }
4100
4101 /* for cube forms of lod and bias we need to route things */
4102 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
4103 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
4104 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4105 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
4106 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4107 alu.op = ALU_OP1_MOV;
4108 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4109 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4110 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4111 else
4112 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4113 alu.dst.sel = ctx->temp_reg;
4114 alu.dst.chan = 2;
4115 alu.last = 1;
4116 alu.dst.write = 1;
4117 r = r600_bytecode_add_alu(ctx->bc, &alu);
4118 if (r)
4119 return r;
4120 }
4121
4122 src_loaded = TRUE;
4123 src_gpr = ctx->temp_reg;
4124 }
4125
4126 if (src_requires_loading && !src_loaded) {
4127 for (i = 0; i < 4; i++) {
4128 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4129 alu.op = ALU_OP1_MOV;
4130 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4131 alu.dst.sel = ctx->temp_reg;
4132 alu.dst.chan = i;
4133 if (i == 3)
4134 alu.last = 1;
4135 alu.dst.write = 1;
4136 r = r600_bytecode_add_alu(ctx->bc, &alu);
4137 if (r)
4138 return r;
4139 }
4140 src_loaded = TRUE;
4141 src_gpr = ctx->temp_reg;
4142 }
4143
4144 /* Obtain the sample index for reading a compressed MSAA color texture.
4145 * To read the FMASK, we use the ldfptr instruction, which tells us
4146 * where the samples are stored.
4147 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
4148 * which is the identity mapping. Each nibble says which physical sample
4149 * should be fetched to get that sample.
4150 *
4151 * Assume src.z contains the sample index. It should be modified like this:
4152 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
4153 * Then fetch the texel with src.
4154 */
4155 if (read_compressed_msaa) {
4156 unsigned sample_chan = 3;
4157 unsigned temp = r600_get_temp(ctx);
4158 assert(src_loaded);
4159
4160 /* temp.w = ldfptr() */
4161 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4162 tex.op = FETCH_OP_LD;
4163 tex.inst_mod = 1; /* to indicate this is ldfptr */
4164 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4165 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4166 tex.src_gpr = src_gpr;
4167 tex.dst_gpr = temp;
4168 tex.dst_sel_x = 7; /* mask out these components */
4169 tex.dst_sel_y = 7;
4170 tex.dst_sel_z = 7;
4171 tex.dst_sel_w = 0; /* store X */
4172 tex.src_sel_x = 0;
4173 tex.src_sel_y = 1;
4174 tex.src_sel_z = 2;
4175 tex.src_sel_w = 3;
4176 tex.offset_x = offset_x;
4177 tex.offset_y = offset_y;
4178 tex.offset_z = offset_z;
4179 r = r600_bytecode_add_tex(ctx->bc, &tex);
4180 if (r)
4181 return r;
4182
4183 /* temp.x = sample_index*4 */
4184 if (ctx->bc->chip_class == CAYMAN) {
4185 for (i = 0 ; i < 4; i++) {
4186 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4187 alu.op = ALU_OP2_MULLO_INT;
4188 alu.src[0].sel = src_gpr;
4189 alu.src[0].chan = sample_chan;
4190 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4191 alu.src[1].value = 4;
4192 alu.dst.sel = temp;
4193 alu.dst.chan = i;
4194 alu.dst.write = i == 0;
4195 if (i == 3)
4196 alu.last = 1;
4197 r = r600_bytecode_add_alu(ctx->bc, &alu);
4198 if (r)
4199 return r;
4200 }
4201 } else {
4202 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4203 alu.op = ALU_OP2_MULLO_INT;
4204 alu.src[0].sel = src_gpr;
4205 alu.src[0].chan = sample_chan;
4206 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4207 alu.src[1].value = 4;
4208 alu.dst.sel = temp;
4209 alu.dst.chan = 0;
4210 alu.dst.write = 1;
4211 alu.last = 1;
4212 r = r600_bytecode_add_alu(ctx->bc, &alu);
4213 if (r)
4214 return r;
4215 }
4216
4217 /* sample_index = temp.w >> temp.x */
4218 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4219 alu.op = ALU_OP2_LSHR_INT;
4220 alu.src[0].sel = temp;
4221 alu.src[0].chan = 3;
4222 alu.src[1].sel = temp;
4223 alu.src[1].chan = 0;
4224 alu.dst.sel = src_gpr;
4225 alu.dst.chan = sample_chan;
4226 alu.dst.write = 1;
4227 alu.last = 1;
4228 r = r600_bytecode_add_alu(ctx->bc, &alu);
4229 if (r)
4230 return r;
4231
4232 /* sample_index & 0xF */
4233 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4234 alu.op = ALU_OP2_AND_INT;
4235 alu.src[0].sel = src_gpr;
4236 alu.src[0].chan = sample_chan;
4237 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4238 alu.src[1].value = 0xF;
4239 alu.dst.sel = src_gpr;
4240 alu.dst.chan = sample_chan;
4241 alu.dst.write = 1;
4242 alu.last = 1;
4243 r = r600_bytecode_add_alu(ctx->bc, &alu);
4244 if (r)
4245 return r;
4246 #if 0
4247 /* visualize the FMASK */
4248 for (i = 0; i < 4; i++) {
4249 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4250 alu.op = ALU_OP1_INT_TO_FLT;
4251 alu.src[0].sel = src_gpr;
4252 alu.src[0].chan = sample_chan;
4253 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4254 alu.dst.chan = i;
4255 alu.dst.write = 1;
4256 alu.last = 1;
4257 r = r600_bytecode_add_alu(ctx->bc, &alu);
4258 if (r)
4259 return r;
4260 }
4261 return 0;
4262 #endif
4263 }
4264
4265 /* does this shader want a num layers from TXQ for a cube array? */
4266 if (has_txq_cube_array_z) {
4267 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4268
4269 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4270 alu.op = ALU_OP1_MOV;
4271
4272 alu.src[0].sel = 512 + (id / 4);
4273 alu.src[0].kc_bank = R600_TXQ_CONST_BUFFER;
4274 alu.src[0].chan = id % 4;
4275 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4276 alu.last = 1;
4277 r = r600_bytecode_add_alu(ctx->bc, &alu);
4278 if (r)
4279 return r;
4280 /* disable writemask from texture instruction */
4281 inst->Dst[0].Register.WriteMask &= ~4;
4282 }
4283
4284 opcode = ctx->inst_info->op;
4285 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4286 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4287 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4288 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4289 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
4290 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4291 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4292 switch (opcode) {
4293 case FETCH_OP_SAMPLE:
4294 opcode = FETCH_OP_SAMPLE_C;
4295 break;
4296 case FETCH_OP_SAMPLE_L:
4297 opcode = FETCH_OP_SAMPLE_C_L;
4298 break;
4299 case FETCH_OP_SAMPLE_LB:
4300 opcode = FETCH_OP_SAMPLE_C_LB;
4301 break;
4302 case FETCH_OP_SAMPLE_G:
4303 opcode = FETCH_OP_SAMPLE_C_G;
4304 break;
4305 }
4306 }
4307
4308 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4309 tex.op = opcode;
4310
4311 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4312 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4313 tex.src_gpr = src_gpr;
4314 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4315 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
4316 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
4317 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
4318 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
4319
4320 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
4321 tex.src_sel_x = 4;
4322 tex.src_sel_y = 4;
4323 tex.src_sel_z = 4;
4324 tex.src_sel_w = 4;
4325 } else if (src_loaded) {
4326 tex.src_sel_x = 0;
4327 tex.src_sel_y = 1;
4328 tex.src_sel_z = 2;
4329 tex.src_sel_w = 3;
4330 } else {
4331 tex.src_sel_x = ctx->src[0].swizzle[0];
4332 tex.src_sel_y = ctx->src[0].swizzle[1];
4333 tex.src_sel_z = ctx->src[0].swizzle[2];
4334 tex.src_sel_w = ctx->src[0].swizzle[3];
4335 tex.src_rel = ctx->src[0].rel;
4336 }
4337
4338 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4339 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4340 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4341 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4342 tex.src_sel_x = 1;
4343 tex.src_sel_y = 0;
4344 tex.src_sel_z = 3;
4345 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
4346 }
4347
4348 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
4349 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
4350 tex.coord_type_x = 1;
4351 tex.coord_type_y = 1;
4352 }
4353 tex.coord_type_z = 1;
4354 tex.coord_type_w = 1;
4355
4356 tex.offset_x = offset_x;
4357 tex.offset_y = offset_y;
4358 tex.offset_z = offset_z;
4359
4360 /* Put the depth for comparison in W.
4361 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
4362 * Some instructions expect the depth in Z. */
4363 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4364 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4365 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4366 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
4367 opcode != FETCH_OP_SAMPLE_C_L &&
4368 opcode != FETCH_OP_SAMPLE_C_LB) {
4369 tex.src_sel_w = tex.src_sel_z;
4370 }
4371
4372 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
4373 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
4374 if (opcode == FETCH_OP_SAMPLE_C_L ||
4375 opcode == FETCH_OP_SAMPLE_C_LB) {
4376 /* the array index is read from Y */
4377 tex.coord_type_y = 0;
4378 } else {
4379 /* the array index is read from Z */
4380 tex.coord_type_z = 0;
4381 tex.src_sel_z = tex.src_sel_y;
4382 }
4383 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
4384 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4385 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4386 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4387 (ctx->bc->chip_class >= EVERGREEN)))
4388 /* the array index is read from Z */
4389 tex.coord_type_z = 0;
4390
4391 /* mask unused source components */
4392 if (opcode == FETCH_OP_SAMPLE) {
4393 switch (inst->Texture.Texture) {
4394 case TGSI_TEXTURE_2D:
4395 case TGSI_TEXTURE_RECT:
4396 tex.src_sel_z = 7;
4397 tex.src_sel_w = 7;
4398 break;
4399 case TGSI_TEXTURE_1D_ARRAY:
4400 tex.src_sel_y = 7;
4401 tex.src_sel_w = 7;
4402 break;
4403 case TGSI_TEXTURE_1D:
4404 tex.src_sel_y = 7;
4405 tex.src_sel_z = 7;
4406 tex.src_sel_w = 7;
4407 break;
4408 }
4409 }
4410
4411 r = r600_bytecode_add_tex(ctx->bc, &tex);
4412 if (r)
4413 return r;
4414
4415 /* add shadow ambient support - gallium doesn't do it yet */
4416 return 0;
4417 }
4418
4419 static int tgsi_lrp(struct r600_shader_ctx *ctx)
4420 {
4421 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4422 struct r600_bytecode_alu alu;
4423 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4424 unsigned i;
4425 int r;
4426
4427 /* optimize if it's just an equal balance */
4428 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
4429 for (i = 0; i < lasti + 1; i++) {
4430 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4431 continue;
4432
4433 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4434 alu.op = ALU_OP2_ADD;
4435 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4436 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4437 alu.omod = 3;
4438 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4439 alu.dst.chan = i;
4440 if (i == lasti) {
4441 alu.last = 1;
4442 }
4443 r = r600_bytecode_add_alu(ctx->bc, &alu);
4444 if (r)
4445 return r;
4446 }
4447 return 0;
4448 }
4449
4450 /* 1 - src0 */
4451 for (i = 0; i < lasti + 1; i++) {
4452 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4453 continue;
4454
4455 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4456 alu.op = ALU_OP2_ADD;
4457 alu.src[0].sel = V_SQ_ALU_SRC_1;
4458 alu.src[0].chan = 0;
4459 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4460 r600_bytecode_src_toggle_neg(&alu.src[1]);
4461 alu.dst.sel = ctx->temp_reg;
4462 alu.dst.chan = i;
4463 if (i == lasti) {
4464 alu.last = 1;
4465 }
4466 alu.dst.write = 1;
4467 r = r600_bytecode_add_alu(ctx->bc, &alu);
4468 if (r)
4469 return r;
4470 }
4471
4472 /* (1 - src0) * src2 */
4473 for (i = 0; i < lasti + 1; i++) {
4474 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4475 continue;
4476
4477 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4478 alu.op = ALU_OP2_MUL;
4479 alu.src[0].sel = ctx->temp_reg;
4480 alu.src[0].chan = i;
4481 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4482 alu.dst.sel = ctx->temp_reg;
4483 alu.dst.chan = i;
4484 if (i == lasti) {
4485 alu.last = 1;
4486 }
4487 alu.dst.write = 1;
4488 r = r600_bytecode_add_alu(ctx->bc, &alu);
4489 if (r)
4490 return r;
4491 }
4492
4493 /* src0 * src1 + (1 - src0) * src2 */
4494 for (i = 0; i < lasti + 1; i++) {
4495 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4496 continue;
4497
4498 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4499 alu.op = ALU_OP3_MULADD;
4500 alu.is_op3 = 1;
4501 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4502 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4503 alu.src[2].sel = ctx->temp_reg;
4504 alu.src[2].chan = i;
4505
4506 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4507 alu.dst.chan = i;
4508 if (i == lasti) {
4509 alu.last = 1;
4510 }
4511 r = r600_bytecode_add_alu(ctx->bc, &alu);
4512 if (r)
4513 return r;
4514 }
4515 return 0;
4516 }
4517
4518 static int tgsi_cmp(struct r600_shader_ctx *ctx)
4519 {
4520 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4521 struct r600_bytecode_alu alu;
4522 int i, r;
4523 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4524
4525 for (i = 0; i < lasti + 1; i++) {
4526 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4527 continue;
4528
4529 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4530 alu.op = ALU_OP3_CNDGE;
4531 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4532 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4533 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4534 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4535 alu.dst.chan = i;
4536 alu.dst.write = 1;
4537 alu.is_op3 = 1;
4538 if (i == lasti)
4539 alu.last = 1;
4540 r = r600_bytecode_add_alu(ctx->bc, &alu);
4541 if (r)
4542 return r;
4543 }
4544 return 0;
4545 }
4546
4547 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
4548 {
4549 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4550 struct r600_bytecode_alu alu;
4551 int i, r;
4552 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4553
4554 for (i = 0; i < lasti + 1; i++) {
4555 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4556 continue;
4557
4558 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4559 alu.op = ALU_OP3_CNDGE_INT;
4560 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4561 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4562 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4563 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4564 alu.dst.chan = i;
4565 alu.dst.write = 1;
4566 alu.is_op3 = 1;
4567 if (i == lasti)
4568 alu.last = 1;
4569 r = r600_bytecode_add_alu(ctx->bc, &alu);
4570 if (r)
4571 return r;
4572 }
4573 return 0;
4574 }
4575
4576 static int tgsi_xpd(struct r600_shader_ctx *ctx)
4577 {
4578 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4579 static const unsigned int src0_swizzle[] = {2, 0, 1};
4580 static const unsigned int src1_swizzle[] = {1, 2, 0};
4581 struct r600_bytecode_alu alu;
4582 uint32_t use_temp = 0;
4583 int i, r;
4584
4585 if (inst->Dst[0].Register.WriteMask != 0xf)
4586 use_temp = 1;
4587
4588 for (i = 0; i < 4; i++) {
4589 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4590 alu.op = ALU_OP2_MUL;
4591 if (i < 3) {
4592 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4593 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
4594 } else {
4595 alu.src[0].sel = V_SQ_ALU_SRC_0;
4596 alu.src[0].chan = i;
4597 alu.src[1].sel = V_SQ_ALU_SRC_0;
4598 alu.src[1].chan = i;
4599 }
4600
4601 alu.dst.sel = ctx->temp_reg;
4602 alu.dst.chan = i;
4603 alu.dst.write = 1;
4604
4605 if (i == 3)
4606 alu.last = 1;
4607 r = r600_bytecode_add_alu(ctx->bc, &alu);
4608 if (r)
4609 return r;
4610 }
4611
4612 for (i = 0; i < 4; i++) {
4613 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4614 alu.op = ALU_OP3_MULADD;
4615
4616 if (i < 3) {
4617 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
4618 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
4619 } else {
4620 alu.src[0].sel = V_SQ_ALU_SRC_0;
4621 alu.src[0].chan = i;
4622 alu.src[1].sel = V_SQ_ALU_SRC_0;
4623 alu.src[1].chan = i;
4624 }
4625
4626 alu.src[2].sel = ctx->temp_reg;
4627 alu.src[2].neg = 1;
4628 alu.src[2].chan = i;
4629
4630 if (use_temp)
4631 alu.dst.sel = ctx->temp_reg;
4632 else
4633 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4634 alu.dst.chan = i;
4635 alu.dst.write = 1;
4636 alu.is_op3 = 1;
4637 if (i == 3)
4638 alu.last = 1;
4639 r = r600_bytecode_add_alu(ctx->bc, &alu);
4640 if (r)
4641 return r;
4642 }
4643 if (use_temp)
4644 return tgsi_helper_copy(ctx, inst);
4645 return 0;
4646 }
4647
4648 static int tgsi_exp(struct r600_shader_ctx *ctx)
4649 {
4650 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4651 struct r600_bytecode_alu alu;
4652 int r;
4653 int i;
4654
4655 /* result.x = 2^floor(src); */
4656 if (inst->Dst[0].Register.WriteMask & 1) {
4657 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4658
4659 alu.op = ALU_OP1_FLOOR;
4660 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4661
4662 alu.dst.sel = ctx->temp_reg;
4663 alu.dst.chan = 0;
4664 alu.dst.write = 1;
4665 alu.last = 1;
4666 r = r600_bytecode_add_alu(ctx->bc, &alu);
4667 if (r)
4668 return r;
4669
4670 if (ctx->bc->chip_class == CAYMAN) {
4671 for (i = 0; i < 3; i++) {
4672 alu.op = ALU_OP1_EXP_IEEE;
4673 alu.src[0].sel = ctx->temp_reg;
4674 alu.src[0].chan = 0;
4675
4676 alu.dst.sel = ctx->temp_reg;
4677 alu.dst.chan = i;
4678 alu.dst.write = i == 0;
4679 alu.last = i == 2;
4680 r = r600_bytecode_add_alu(ctx->bc, &alu);
4681 if (r)
4682 return r;
4683 }
4684 } else {
4685 alu.op = ALU_OP1_EXP_IEEE;
4686 alu.src[0].sel = ctx->temp_reg;
4687 alu.src[0].chan = 0;
4688
4689 alu.dst.sel = ctx->temp_reg;
4690 alu.dst.chan = 0;
4691 alu.dst.write = 1;
4692 alu.last = 1;
4693 r = r600_bytecode_add_alu(ctx->bc, &alu);
4694 if (r)
4695 return r;
4696 }
4697 }
4698
4699 /* result.y = tmp - floor(tmp); */
4700 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
4701 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4702
4703 alu.op = ALU_OP1_FRACT;
4704 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4705
4706 alu.dst.sel = ctx->temp_reg;
4707 #if 0
4708 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4709 if (r)
4710 return r;
4711 #endif
4712 alu.dst.write = 1;
4713 alu.dst.chan = 1;
4714
4715 alu.last = 1;
4716
4717 r = r600_bytecode_add_alu(ctx->bc, &alu);
4718 if (r)
4719 return r;
4720 }
4721
4722 /* result.z = RoughApprox2ToX(tmp);*/
4723 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
4724 if (ctx->bc->chip_class == CAYMAN) {
4725 for (i = 0; i < 3; i++) {
4726 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4727 alu.op = ALU_OP1_EXP_IEEE;
4728 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4729
4730 alu.dst.sel = ctx->temp_reg;
4731 alu.dst.chan = i;
4732 if (i == 2) {
4733 alu.dst.write = 1;
4734 alu.last = 1;
4735 }
4736
4737 r = r600_bytecode_add_alu(ctx->bc, &alu);
4738 if (r)
4739 return r;
4740 }
4741 } else {
4742 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4743 alu.op = ALU_OP1_EXP_IEEE;
4744 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4745
4746 alu.dst.sel = ctx->temp_reg;
4747 alu.dst.write = 1;
4748 alu.dst.chan = 2;
4749
4750 alu.last = 1;
4751
4752 r = r600_bytecode_add_alu(ctx->bc, &alu);
4753 if (r)
4754 return r;
4755 }
4756 }
4757
4758 /* result.w = 1.0;*/
4759 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
4760 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4761
4762 alu.op = ALU_OP1_MOV;
4763 alu.src[0].sel = V_SQ_ALU_SRC_1;
4764 alu.src[0].chan = 0;
4765
4766 alu.dst.sel = ctx->temp_reg;
4767 alu.dst.chan = 3;
4768 alu.dst.write = 1;
4769 alu.last = 1;
4770 r = r600_bytecode_add_alu(ctx->bc, &alu);
4771 if (r)
4772 return r;
4773 }
4774 return tgsi_helper_copy(ctx, inst);
4775 }
4776
4777 static int tgsi_log(struct r600_shader_ctx *ctx)
4778 {
4779 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4780 struct r600_bytecode_alu alu;
4781 int r;
4782 int i;
4783
4784 /* result.x = floor(log2(|src|)); */
4785 if (inst->Dst[0].Register.WriteMask & 1) {
4786 if (ctx->bc->chip_class == CAYMAN) {
4787 for (i = 0; i < 3; i++) {
4788 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4789
4790 alu.op = ALU_OP1_LOG_IEEE;
4791 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4792 r600_bytecode_src_set_abs(&alu.src[0]);
4793
4794 alu.dst.sel = ctx->temp_reg;
4795 alu.dst.chan = i;
4796 if (i == 0)
4797 alu.dst.write = 1;
4798 if (i == 2)
4799 alu.last = 1;
4800 r = r600_bytecode_add_alu(ctx->bc, &alu);
4801 if (r)
4802 return r;
4803 }
4804
4805 } else {
4806 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4807
4808 alu.op = ALU_OP1_LOG_IEEE;
4809 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4810 r600_bytecode_src_set_abs(&alu.src[0]);
4811
4812 alu.dst.sel = ctx->temp_reg;
4813 alu.dst.chan = 0;
4814 alu.dst.write = 1;
4815 alu.last = 1;
4816 r = r600_bytecode_add_alu(ctx->bc, &alu);
4817 if (r)
4818 return r;
4819 }
4820
4821 alu.op = ALU_OP1_FLOOR;
4822 alu.src[0].sel = ctx->temp_reg;
4823 alu.src[0].chan = 0;
4824
4825 alu.dst.sel = ctx->temp_reg;
4826 alu.dst.chan = 0;
4827 alu.dst.write = 1;
4828 alu.last = 1;
4829
4830 r = r600_bytecode_add_alu(ctx->bc, &alu);
4831 if (r)
4832 return r;
4833 }
4834
4835 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
4836 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
4837
4838 if (ctx->bc->chip_class == CAYMAN) {
4839 for (i = 0; i < 3; i++) {
4840 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4841
4842 alu.op = ALU_OP1_LOG_IEEE;
4843 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4844 r600_bytecode_src_set_abs(&alu.src[0]);
4845
4846 alu.dst.sel = ctx->temp_reg;
4847 alu.dst.chan = i;
4848 if (i == 1)
4849 alu.dst.write = 1;
4850 if (i == 2)
4851 alu.last = 1;
4852
4853 r = r600_bytecode_add_alu(ctx->bc, &alu);
4854 if (r)
4855 return r;
4856 }
4857 } else {
4858 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4859
4860 alu.op = ALU_OP1_LOG_IEEE;
4861 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4862 r600_bytecode_src_set_abs(&alu.src[0]);
4863
4864 alu.dst.sel = ctx->temp_reg;
4865 alu.dst.chan = 1;
4866 alu.dst.write = 1;
4867 alu.last = 1;
4868
4869 r = r600_bytecode_add_alu(ctx->bc, &alu);
4870 if (r)
4871 return r;
4872 }
4873
4874 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4875
4876 alu.op = ALU_OP1_FLOOR;
4877 alu.src[0].sel = ctx->temp_reg;
4878 alu.src[0].chan = 1;
4879
4880 alu.dst.sel = ctx->temp_reg;
4881 alu.dst.chan = 1;
4882 alu.dst.write = 1;
4883 alu.last = 1;
4884
4885 r = r600_bytecode_add_alu(ctx->bc, &alu);
4886 if (r)
4887 return r;
4888
4889 if (ctx->bc->chip_class == CAYMAN) {
4890 for (i = 0; i < 3; i++) {
4891 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4892 alu.op = ALU_OP1_EXP_IEEE;
4893 alu.src[0].sel = ctx->temp_reg;
4894 alu.src[0].chan = 1;
4895
4896 alu.dst.sel = ctx->temp_reg;
4897 alu.dst.chan = i;
4898 if (i == 1)
4899 alu.dst.write = 1;
4900 if (i == 2)
4901 alu.last = 1;
4902
4903 r = r600_bytecode_add_alu(ctx->bc, &alu);
4904 if (r)
4905 return r;
4906 }
4907 } else {
4908 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4909 alu.op = ALU_OP1_EXP_IEEE;
4910 alu.src[0].sel = ctx->temp_reg;
4911 alu.src[0].chan = 1;
4912
4913 alu.dst.sel = ctx->temp_reg;
4914 alu.dst.chan = 1;
4915 alu.dst.write = 1;
4916 alu.last = 1;
4917
4918 r = r600_bytecode_add_alu(ctx->bc, &alu);
4919 if (r)
4920 return r;
4921 }
4922
4923 if (ctx->bc->chip_class == CAYMAN) {
4924 for (i = 0; i < 3; i++) {
4925 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4926 alu.op = ALU_OP1_RECIP_IEEE;
4927 alu.src[0].sel = ctx->temp_reg;
4928 alu.src[0].chan = 1;
4929
4930 alu.dst.sel = ctx->temp_reg;
4931 alu.dst.chan = i;
4932 if (i == 1)
4933 alu.dst.write = 1;
4934 if (i == 2)
4935 alu.last = 1;
4936
4937 r = r600_bytecode_add_alu(ctx->bc, &alu);
4938 if (r)
4939 return r;
4940 }
4941 } else {
4942 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4943 alu.op = ALU_OP1_RECIP_IEEE;
4944 alu.src[0].sel = ctx->temp_reg;
4945 alu.src[0].chan = 1;
4946
4947 alu.dst.sel = ctx->temp_reg;
4948 alu.dst.chan = 1;
4949 alu.dst.write = 1;
4950 alu.last = 1;
4951
4952 r = r600_bytecode_add_alu(ctx->bc, &alu);
4953 if (r)
4954 return r;
4955 }
4956
4957 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4958
4959 alu.op = ALU_OP2_MUL;
4960
4961 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4962 r600_bytecode_src_set_abs(&alu.src[0]);
4963
4964 alu.src[1].sel = ctx->temp_reg;
4965 alu.src[1].chan = 1;
4966
4967 alu.dst.sel = ctx->temp_reg;
4968 alu.dst.chan = 1;
4969 alu.dst.write = 1;
4970 alu.last = 1;
4971
4972 r = r600_bytecode_add_alu(ctx->bc, &alu);
4973 if (r)
4974 return r;
4975 }
4976
4977 /* result.z = log2(|src|);*/
4978 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
4979 if (ctx->bc->chip_class == CAYMAN) {
4980 for (i = 0; i < 3; i++) {
4981 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4982
4983 alu.op = ALU_OP1_LOG_IEEE;
4984 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4985 r600_bytecode_src_set_abs(&alu.src[0]);
4986
4987 alu.dst.sel = ctx->temp_reg;
4988 if (i == 2)
4989 alu.dst.write = 1;
4990 alu.dst.chan = i;
4991 if (i == 2)
4992 alu.last = 1;
4993
4994 r = r600_bytecode_add_alu(ctx->bc, &alu);
4995 if (r)
4996 return r;
4997 }
4998 } else {
4999 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5000
5001 alu.op = ALU_OP1_LOG_IEEE;
5002 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5003 r600_bytecode_src_set_abs(&alu.src[0]);
5004
5005 alu.dst.sel = ctx->temp_reg;
5006 alu.dst.write = 1;
5007 alu.dst.chan = 2;
5008 alu.last = 1;
5009
5010 r = r600_bytecode_add_alu(ctx->bc, &alu);
5011 if (r)
5012 return r;
5013 }
5014 }
5015
5016 /* result.w = 1.0; */
5017 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
5018 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5019
5020 alu.op = ALU_OP1_MOV;
5021 alu.src[0].sel = V_SQ_ALU_SRC_1;
5022 alu.src[0].chan = 0;
5023
5024 alu.dst.sel = ctx->temp_reg;
5025 alu.dst.chan = 3;
5026 alu.dst.write = 1;
5027 alu.last = 1;
5028
5029 r = r600_bytecode_add_alu(ctx->bc, &alu);
5030 if (r)
5031 return r;
5032 }
5033
5034 return tgsi_helper_copy(ctx, inst);
5035 }
5036
5037 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
5038 {
5039 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5040 struct r600_bytecode_alu alu;
5041 int r;
5042
5043 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5044
5045 switch (inst->Instruction.Opcode) {
5046 case TGSI_OPCODE_ARL:
5047 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
5048 break;
5049 case TGSI_OPCODE_ARR:
5050 alu.op = ALU_OP1_FLT_TO_INT;
5051 break;
5052 case TGSI_OPCODE_UARL:
5053 alu.op = ALU_OP1_MOV;
5054 break;
5055 default:
5056 assert(0);
5057 return -1;
5058 }
5059
5060 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5061 alu.last = 1;
5062 alu.dst.sel = ctx->bc->ar_reg;
5063 alu.dst.write = 1;
5064 r = r600_bytecode_add_alu(ctx->bc, &alu);
5065 if (r)
5066 return r;
5067
5068 ctx->bc->ar_loaded = 0;
5069 return 0;
5070 }
5071 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
5072 {
5073 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5074 struct r600_bytecode_alu alu;
5075 int r;
5076
5077 switch (inst->Instruction.Opcode) {
5078 case TGSI_OPCODE_ARL:
5079 memset(&alu, 0, sizeof(alu));
5080 alu.op = ALU_OP1_FLOOR;
5081 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5082 alu.dst.sel = ctx->bc->ar_reg;
5083 alu.dst.write = 1;
5084 alu.last = 1;
5085
5086 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5087 return r;
5088
5089 memset(&alu, 0, sizeof(alu));
5090 alu.op = ALU_OP1_FLT_TO_INT;
5091 alu.src[0].sel = ctx->bc->ar_reg;
5092 alu.dst.sel = ctx->bc->ar_reg;
5093 alu.dst.write = 1;
5094 alu.last = 1;
5095
5096 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5097 return r;
5098 break;
5099 case TGSI_OPCODE_ARR:
5100 memset(&alu, 0, sizeof(alu));
5101 alu.op = ALU_OP1_FLT_TO_INT;
5102 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5103 alu.dst.sel = ctx->bc->ar_reg;
5104 alu.dst.write = 1;
5105 alu.last = 1;
5106
5107 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5108 return r;
5109 break;
5110 case TGSI_OPCODE_UARL:
5111 memset(&alu, 0, sizeof(alu));
5112 alu.op = ALU_OP1_MOV;
5113 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5114 alu.dst.sel = ctx->bc->ar_reg;
5115 alu.dst.write = 1;
5116 alu.last = 1;
5117
5118 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5119 return r;
5120 break;
5121 default:
5122 assert(0);
5123 return -1;
5124 }
5125
5126 ctx->bc->ar_loaded = 0;
5127 return 0;
5128 }
5129
5130 static int tgsi_opdst(struct r600_shader_ctx *ctx)
5131 {
5132 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5133 struct r600_bytecode_alu alu;
5134 int i, r = 0;
5135
5136 for (i = 0; i < 4; i++) {
5137 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5138
5139 alu.op = ALU_OP2_MUL;
5140 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5141
5142 if (i == 0 || i == 3) {
5143 alu.src[0].sel = V_SQ_ALU_SRC_1;
5144 } else {
5145 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5146 }
5147
5148 if (i == 0 || i == 2) {
5149 alu.src[1].sel = V_SQ_ALU_SRC_1;
5150 } else {
5151 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5152 }
5153 if (i == 3)
5154 alu.last = 1;
5155 r = r600_bytecode_add_alu(ctx->bc, &alu);
5156 if (r)
5157 return r;
5158 }
5159 return 0;
5160 }
5161
5162 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
5163 {
5164 struct r600_bytecode_alu alu;
5165 int r;
5166
5167 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5168 alu.op = opcode;
5169 alu.execute_mask = 1;
5170 alu.update_pred = 1;
5171
5172 alu.dst.sel = ctx->temp_reg;
5173 alu.dst.write = 1;
5174 alu.dst.chan = 0;
5175
5176 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5177 alu.src[1].sel = V_SQ_ALU_SRC_0;
5178 alu.src[1].chan = 0;
5179
5180 alu.last = 1;
5181
5182 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
5183 if (r)
5184 return r;
5185 return 0;
5186 }
5187
5188 static int pops(struct r600_shader_ctx *ctx, int pops)
5189 {
5190 unsigned force_pop = ctx->bc->force_add_cf;
5191
5192 if (!force_pop) {
5193 int alu_pop = 3;
5194 if (ctx->bc->cf_last) {
5195 if (ctx->bc->cf_last->op == CF_OP_ALU)
5196 alu_pop = 0;
5197 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
5198 alu_pop = 1;
5199 }
5200 alu_pop += pops;
5201 if (alu_pop == 1) {
5202 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
5203 ctx->bc->force_add_cf = 1;
5204 } else if (alu_pop == 2) {
5205 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
5206 ctx->bc->force_add_cf = 1;
5207 } else {
5208 force_pop = 1;
5209 }
5210 }
5211
5212 if (force_pop) {
5213 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
5214 ctx->bc->cf_last->pop_count = pops;
5215 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5216 }
5217
5218 return 0;
5219 }
5220
5221 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
5222 unsigned reason)
5223 {
5224 struct r600_stack_info *stack = &ctx->bc->stack;
5225 unsigned elements, entries;
5226
5227 unsigned entry_size = stack->entry_size;
5228
5229 elements = (stack->loop + stack->push_wqm ) * entry_size;
5230 elements += stack->push;
5231
5232 switch (ctx->bc->chip_class) {
5233 case R600:
5234 case R700:
5235 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
5236 * the stack must be reserved to hold the current active/continue
5237 * masks */
5238 if (reason == FC_PUSH_VPM) {
5239 elements += 2;
5240 }
5241 break;
5242
5243 case CAYMAN:
5244 /* r9xx: any stack operation on empty stack consumes 2 additional
5245 * elements */
5246 elements += 2;
5247
5248 /* fallthrough */
5249 /* FIXME: do the two elements added above cover the cases for the
5250 * r8xx+ below? */
5251
5252 case EVERGREEN:
5253 /* r8xx+: 2 extra elements are not always required, but one extra
5254 * element must be added for each of the following cases:
5255 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
5256 * stack usage.
5257 * (Currently we don't use ALU_ELSE_AFTER.)
5258 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
5259 * PUSH instruction executed.
5260 *
5261 * NOTE: it seems we also need to reserve additional element in some
5262 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
5263 * then STACK_SIZE should be 2 instead of 1 */
5264 if (reason == FC_PUSH_VPM) {
5265 elements += 1;
5266 }
5267 break;
5268
5269 default:
5270 assert(0);
5271 break;
5272 }
5273
5274 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
5275 * for all chips, so we use 4 in the final formula, not the real entry_size
5276 * for the chip */
5277 entry_size = 4;
5278
5279 entries = (elements + (entry_size - 1)) / entry_size;
5280
5281 if (entries > stack->max_entries)
5282 stack->max_entries = entries;
5283 }
5284
5285 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
5286 {
5287 switch(reason) {
5288 case FC_PUSH_VPM:
5289 --ctx->bc->stack.push;
5290 assert(ctx->bc->stack.push >= 0);
5291 break;
5292 case FC_PUSH_WQM:
5293 --ctx->bc->stack.push_wqm;
5294 assert(ctx->bc->stack.push_wqm >= 0);
5295 break;
5296 case FC_LOOP:
5297 --ctx->bc->stack.loop;
5298 assert(ctx->bc->stack.loop >= 0);
5299 break;
5300 default:
5301 assert(0);
5302 break;
5303 }
5304 }
5305
5306 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
5307 {
5308 switch (reason) {
5309 case FC_PUSH_VPM:
5310 ++ctx->bc->stack.push;
5311 break;
5312 case FC_PUSH_WQM:
5313 ++ctx->bc->stack.push_wqm;
5314 case FC_LOOP:
5315 ++ctx->bc->stack.loop;
5316 break;
5317 default:
5318 assert(0);
5319 }
5320
5321 callstack_update_max_depth(ctx, reason);
5322 }
5323
5324 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
5325 {
5326 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
5327
5328 sp->mid = realloc((void *)sp->mid,
5329 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
5330 sp->mid[sp->num_mid] = ctx->bc->cf_last;
5331 sp->num_mid++;
5332 }
5333
5334 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
5335 {
5336 ctx->bc->fc_sp++;
5337 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
5338 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
5339 }
5340
5341 static void fc_poplevel(struct r600_shader_ctx *ctx)
5342 {
5343 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
5344 free(sp->mid);
5345 sp->mid = NULL;
5346 sp->num_mid = 0;
5347 sp->start = NULL;
5348 sp->type = 0;
5349 ctx->bc->fc_sp--;
5350 }
5351
5352 #if 0
5353 static int emit_return(struct r600_shader_ctx *ctx)
5354 {
5355 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
5356 return 0;
5357 }
5358
5359 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
5360 {
5361
5362 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
5363 ctx->bc->cf_last->pop_count = pops;
5364 /* XXX work out offset */
5365 return 0;
5366 }
5367
5368 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
5369 {
5370 return 0;
5371 }
5372
5373 static void emit_testflag(struct r600_shader_ctx *ctx)
5374 {
5375
5376 }
5377
5378 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
5379 {
5380 emit_testflag(ctx);
5381 emit_jump_to_offset(ctx, 1, 4);
5382 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
5383 pops(ctx, ifidx + 1);
5384 emit_return(ctx);
5385 }
5386
5387 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
5388 {
5389 emit_testflag(ctx);
5390
5391 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5392 ctx->bc->cf_last->pop_count = 1;
5393
5394 fc_set_mid(ctx, fc_sp);
5395
5396 pops(ctx, 1);
5397 }
5398 #endif
5399
5400 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
5401 {
5402 int alu_type = CF_OP_ALU_PUSH_BEFORE;
5403
5404 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
5405 * LOOP_STARTxxx for nested loops may put the branch stack into a state
5406 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
5407 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
5408 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
5409 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
5410 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5411 alu_type = CF_OP_ALU;
5412 }
5413
5414 emit_logic_pred(ctx, opcode, alu_type);
5415
5416 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
5417
5418 fc_pushlevel(ctx, FC_IF);
5419
5420 callstack_push(ctx, FC_PUSH_VPM);
5421 return 0;
5422 }
5423
5424 static int tgsi_if(struct r600_shader_ctx *ctx)
5425 {
5426 return emit_if(ctx, ALU_OP2_PRED_SETNE);
5427 }
5428
5429 static int tgsi_uif(struct r600_shader_ctx *ctx)
5430 {
5431 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
5432 }
5433
5434 static int tgsi_else(struct r600_shader_ctx *ctx)
5435 {
5436 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
5437 ctx->bc->cf_last->pop_count = 1;
5438
5439 fc_set_mid(ctx, ctx->bc->fc_sp);
5440 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
5441 return 0;
5442 }
5443
5444 static int tgsi_endif(struct r600_shader_ctx *ctx)
5445 {
5446 pops(ctx, 1);
5447 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
5448 R600_ERR("if/endif unbalanced in shader\n");
5449 return -1;
5450 }
5451
5452 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
5453 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5454 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
5455 } else {
5456 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
5457 }
5458 fc_poplevel(ctx);
5459
5460 callstack_pop(ctx, FC_PUSH_VPM);
5461 return 0;
5462 }
5463
5464 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
5465 {
5466 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
5467 * limited to 4096 iterations, like the other LOOP_* instructions. */
5468 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
5469
5470 fc_pushlevel(ctx, FC_LOOP);
5471
5472 /* check stack depth */
5473 callstack_push(ctx, FC_LOOP);
5474 return 0;
5475 }
5476
5477 static int tgsi_endloop(struct r600_shader_ctx *ctx)
5478 {
5479 int i;
5480
5481 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
5482
5483 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
5484 R600_ERR("loop/endloop in shader code are not paired.\n");
5485 return -EINVAL;
5486 }
5487
5488 /* fixup loop pointers - from r600isa
5489 LOOP END points to CF after LOOP START,
5490 LOOP START point to CF after LOOP END
5491 BRK/CONT point to LOOP END CF
5492 */
5493 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
5494
5495 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5496
5497 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
5498 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
5499 }
5500 /* XXX add LOOPRET support */
5501 fc_poplevel(ctx);
5502 callstack_pop(ctx, FC_LOOP);
5503 return 0;
5504 }
5505
5506 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
5507 {
5508 unsigned int fscp;
5509
5510 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
5511 {
5512 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
5513 break;
5514 }
5515
5516 if (fscp == 0) {
5517 R600_ERR("Break not inside loop/endloop pair\n");
5518 return -EINVAL;
5519 }
5520
5521 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5522
5523 fc_set_mid(ctx, fscp);
5524
5525 return 0;
5526 }
5527
5528 static int tgsi_umad(struct r600_shader_ctx *ctx)
5529 {
5530 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5531 struct r600_bytecode_alu alu;
5532 int i, j, k, r;
5533 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5534
5535 /* src0 * src1 */
5536 for (i = 0; i < lasti + 1; i++) {
5537 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5538 continue;
5539
5540 if (ctx->bc->chip_class == CAYMAN) {
5541 for (j = 0 ; j < 4; j++) {
5542 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5543
5544 alu.op = ALU_OP2_MULLO_UINT;
5545 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
5546 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
5547 }
5548 tgsi_dst(ctx, &inst->Dst[0], j, &alu.dst);
5549 alu.dst.sel = ctx->temp_reg;
5550 alu.dst.write = (j == i);
5551 if (j == 3)
5552 alu.last = 1;
5553 r = r600_bytecode_add_alu(ctx->bc, &alu);
5554 if (r)
5555 return r;
5556 }
5557 } else {
5558 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5559
5560 alu.dst.chan = i;
5561 alu.dst.sel = ctx->temp_reg;
5562 alu.dst.write = 1;
5563
5564 alu.op = ALU_OP2_MULLO_UINT;
5565 for (j = 0; j < 2; j++) {
5566 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
5567 }
5568
5569 alu.last = 1;
5570 r = r600_bytecode_add_alu(ctx->bc, &alu);
5571 if (r)
5572 return r;
5573 }
5574 }
5575
5576
5577 for (i = 0; i < lasti + 1; i++) {
5578 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5579 continue;
5580
5581 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5582 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5583
5584 alu.op = ALU_OP2_ADD_INT;
5585
5586 alu.src[0].sel = ctx->temp_reg;
5587 alu.src[0].chan = i;
5588
5589 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5590 if (i == lasti) {
5591 alu.last = 1;
5592 }
5593 r = r600_bytecode_add_alu(ctx->bc, &alu);
5594 if (r)
5595 return r;
5596 }
5597 return 0;
5598 }
5599
5600 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
5601 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_r600_arl},
5602 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
5603 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
5604
5605 /* XXX:
5606 * For state trackers other than OpenGL, we'll want to use
5607 * _RECIP_IEEE instead.
5608 */
5609 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
5610
5611 {TGSI_OPCODE_RSQ, 0, ALU_OP0_NOP, tgsi_rsq},
5612 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
5613 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
5614 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
5615 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
5616 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
5617 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
5618 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
5619 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
5620 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
5621 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
5622 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
5623 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
5624 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
5625 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
5626 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
5627 /* gap */
5628 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
5629 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
5630 /* gap */
5631 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
5632 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
5633 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
5634 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
5635 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
5636 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
5637 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
5638 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
5639 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
5640 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
5641 /* gap */
5642 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
5643 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
5644 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
5645 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
5646 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
5647 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
5648 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
5649 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
5650 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5651 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5652 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5653 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5654 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5655 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
5656 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5657 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
5658 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
5659 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
5660 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
5661 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
5662 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
5663 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
5664 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
5665 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5666 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5667 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5668 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5669 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
5670 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
5671 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_r600_arl},
5672 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
5673 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
5674 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
5675 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
5676 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
5677 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
5678 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5679 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
5680 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
5681 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
5682 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5683 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
5684 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
5685 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
5686 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
5687 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
5688 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
5689 /* gap */
5690 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
5691 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
5692 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
5693 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
5694 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
5695 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
5696 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
5697 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
5698 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2_trans},
5699 /* gap */
5700 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
5701 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
5702 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
5703 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
5704 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
5705 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5706 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
5707 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5708 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
5709 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
5710 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
5711 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
5712 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5713 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
5714 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5715 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5716 /* gap */
5717 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
5718 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
5719 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
5720 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
5721 {TGSI_OPCODE_FSEQ, 0, ALU_OP2_SETE_DX10, tgsi_op2},
5722 {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2},
5723 {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap},
5724 {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap},
5725 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
5726 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
5727 /* gap */
5728 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
5729 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
5730 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
5731 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
5732 /* gap */
5733 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
5734 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
5735 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
5736 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
5737 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
5738 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
5739 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
5740 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2_trans},
5741 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
5742 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
5743 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
5744 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
5745 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
5746 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
5747 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
5748 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
5749 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
5750 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
5751 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
5752 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
5753 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2_trans},
5754 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
5755 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2_swap},
5756 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
5757 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
5758 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
5759 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
5760 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
5761 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
5762 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
5763 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
5764 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
5765 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
5766 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
5767 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
5768 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
5769 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
5770 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
5771 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
5772 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_r600_arl},
5773 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
5774 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
5775 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
5776 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5777 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
5778 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5779 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5780 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5781 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
5782 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
5783 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
5784 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
5785 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
5786 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
5787 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
5788 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
5789 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
5790 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
5791 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
5792 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
5793 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5794 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5795 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
5796 };
5797
5798 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
5799 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
5800 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
5801 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
5802 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
5803 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
5804 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
5805 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
5806 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
5807 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
5808 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
5809 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
5810 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
5811 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
5812 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
5813 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
5814 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
5815 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
5816 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
5817 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
5818 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
5819 /* gap */
5820 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
5821 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
5822 /* gap */
5823 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
5824 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
5825 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
5826 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
5827 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
5828 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
5829 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
5830 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
5831 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
5832 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
5833 /* gap */
5834 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
5835 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
5836 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
5837 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
5838 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
5839 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
5840 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
5841 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
5842 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5843 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5844 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5845 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5846 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5847 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
5848 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5849 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
5850 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
5851 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
5852 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
5853 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
5854 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
5855 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
5856 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
5857 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5858 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5859 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5860 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5861 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
5862 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
5863 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
5864 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
5865 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
5866 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
5867 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
5868 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
5869 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
5870 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5871 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
5872 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
5873 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
5874 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5875 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
5876 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
5877 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
5878 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
5879 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
5880 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
5881 /* gap */
5882 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
5883 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
5884 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
5885 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
5886 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
5887 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
5888 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
5889 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
5890 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
5891 /* gap */
5892 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
5893 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
5894 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
5895 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
5896 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
5897 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5898 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
5899 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5900 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
5901 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
5902 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
5903 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
5904 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5905 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
5906 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5907 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5908 /* gap */
5909 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
5910 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
5911 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
5912 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
5913 {TGSI_OPCODE_FSEQ, 0, ALU_OP2_SETE_DX10, tgsi_op2},
5914 {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2},
5915 {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap},
5916 {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap},
5917 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
5918 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
5919 /* gap */
5920 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
5921 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
5922 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
5923 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
5924 /* gap */
5925 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
5926 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_f2i},
5927 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
5928 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
5929 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
5930 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
5931 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
5932 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
5933 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
5934 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_f2i},
5935 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
5936 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
5937 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
5938 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
5939 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
5940 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
5941 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
5942 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
5943 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
5944 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
5945 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
5946 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
5947 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
5948 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
5949 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
5950 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
5951 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
5952 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
5953 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
5954 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
5955 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
5956 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
5957 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
5958 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
5959 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
5960 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
5961 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
5962 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
5963 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
5964 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
5965 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
5966 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
5967 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
5968 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5969 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
5970 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5971 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5972 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5973 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
5974 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
5975 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
5976 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
5977 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
5978 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
5979 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
5980 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
5981 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
5982 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
5983 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
5984 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
5985 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5986 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5987 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
5988 };
5989
5990 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
5991 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
5992 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
5993 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
5994 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
5995 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
5996 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
5997 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
5998 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
5999 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6000 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6001 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6002 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6003 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6004 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6005 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6006 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6007 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6008 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6009 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6010 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6011 /* gap */
6012 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
6013 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6014 /* gap */
6015 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6016 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6017 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6018 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6019 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6020 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6021 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
6022 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
6023 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, cayman_pow},
6024 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6025 /* gap */
6026 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6027 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6028 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6029 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6030 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, cayman_trig},
6031 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6032 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6033 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
6034 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6035 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6036 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6037 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6038 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6039 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6040 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6041 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6042 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, cayman_trig},
6043 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6044 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6045 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6046 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6047 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6048 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6049 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6050 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6051 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6052 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6053 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6054 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6055 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6056 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6057 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6058 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6059 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6060 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6061 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6062 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6063 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6064 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6065 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6066 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6067 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6068 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6069 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6070 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6071 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6072 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6073 /* gap */
6074 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6075 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6076 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6077 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6078 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6079 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2},
6080 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6081 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6082 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6083 /* gap */
6084 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6085 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6086 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6087 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6088 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6089 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6090 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6091 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6092 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6093 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
6094 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
6095 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6096 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6097 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6098 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6099 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6100 /* gap */
6101 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6102 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6103 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6104 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6105 /* gap */
6106 {TGSI_OPCODE_FSEQ, 0, ALU_OP2_SETE_DX10, tgsi_op2},
6107 {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2},
6108 {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap},
6109 {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap},
6110 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6111 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6112 /* gap */
6113 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6114 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6115 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6116 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6117 /* gap */
6118 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6119 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2},
6120 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6121 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6122 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6123 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6124 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6125 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
6126 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6127 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2},
6128 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2},
6129 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6130 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6131 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6132 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6133 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6134 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6135 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_INT, cayman_mul_int_instr},
6136 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6137 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6138 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6139 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6140 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6141 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6142 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6143 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6144 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6145 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6146 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6147 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6148 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6149 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6150 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6151 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6152 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6153 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6154 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6155 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6156 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6157 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6158 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6159 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6160 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6161 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6162 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6163 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6164 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6165 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6166 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6167 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6168 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6169 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6170 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6171 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6172 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6173 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6174 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6175 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6176 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6177 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6178 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6179 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6180 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6181 };