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r600: partly fix sampleMaskIn value
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
193 use_sb &= (shader->shader.processor_type != PIPE_SHADER_COMPUTE);
194
195 /* disable SB for shaders using doubles */
196 use_sb &= !shader->shader.uses_doubles;
197
198 use_sb &= !shader->shader.uses_atomics;
199 use_sb &= !shader->shader.uses_images;
200 use_sb &= !shader->shader.uses_helper_invocation;
201
202 /* Check if the bytecode has already been built. */
203 if (!shader->shader.bc.bytecode) {
204 r = r600_bytecode_build(&shader->shader.bc);
205 if (r) {
206 R600_ERR("building bytecode failed !\n");
207 goto error;
208 }
209 }
210
211 if (dump && !sb_disasm) {
212 fprintf(stderr, "--------------------------------------------------------------\n");
213 r600_bytecode_disasm(&shader->shader.bc);
214 fprintf(stderr, "______________________________________________________________\n");
215 } else if ((dump && sb_disasm) || use_sb) {
216 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
217 dump, use_sb);
218 if (r) {
219 R600_ERR("r600_sb_bytecode_process failed !\n");
220 goto error;
221 }
222 }
223
224 if (shader->gs_copy_shader) {
225 if (dump) {
226 // dump copy shader
227 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
228 &shader->gs_copy_shader->shader, dump, 0);
229 if (r)
230 goto error;
231 }
232
233 if ((r = store_shader(ctx, shader->gs_copy_shader)))
234 goto error;
235 }
236
237 /* Store the shader in a buffer. */
238 if ((r = store_shader(ctx, shader)))
239 goto error;
240
241 /* Build state. */
242 switch (shader->shader.processor_type) {
243 case PIPE_SHADER_TESS_CTRL:
244 evergreen_update_hs_state(ctx, shader);
245 break;
246 case PIPE_SHADER_TESS_EVAL:
247 if (key.tes.as_es)
248 evergreen_update_es_state(ctx, shader);
249 else
250 evergreen_update_vs_state(ctx, shader);
251 break;
252 case PIPE_SHADER_GEOMETRY:
253 if (rctx->b.chip_class >= EVERGREEN) {
254 evergreen_update_gs_state(ctx, shader);
255 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
256 } else {
257 r600_update_gs_state(ctx, shader);
258 r600_update_vs_state(ctx, shader->gs_copy_shader);
259 }
260 break;
261 case PIPE_SHADER_VERTEX:
262 export_shader = key.vs.as_es;
263 if (rctx->b.chip_class >= EVERGREEN) {
264 if (key.vs.as_ls)
265 evergreen_update_ls_state(ctx, shader);
266 else if (key.vs.as_es)
267 evergreen_update_es_state(ctx, shader);
268 else
269 evergreen_update_vs_state(ctx, shader);
270 } else {
271 if (export_shader)
272 r600_update_es_state(ctx, shader);
273 else
274 r600_update_vs_state(ctx, shader);
275 }
276 break;
277 case PIPE_SHADER_FRAGMENT:
278 if (rctx->b.chip_class >= EVERGREEN) {
279 evergreen_update_ps_state(ctx, shader);
280 } else {
281 r600_update_ps_state(ctx, shader);
282 }
283 break;
284 case PIPE_SHADER_COMPUTE:
285 evergreen_update_ls_state(ctx, shader);
286 break;
287 default:
288 r = -EINVAL;
289 goto error;
290 }
291 return 0;
292
293 error:
294 r600_pipe_shader_destroy(ctx, shader);
295 return r;
296 }
297
298 void r600_pipe_shader_destroy(struct pipe_context *ctx UNUSED, struct r600_pipe_shader *shader)
299 {
300 r600_resource_reference(&shader->bo, NULL);
301 r600_bytecode_clear(&shader->shader.bc);
302 r600_release_command_buffer(&shader->command_buffer);
303 }
304
305 /*
306 * tgsi -> r600 shader
307 */
308 struct r600_shader_tgsi_instruction;
309
310 struct r600_shader_src {
311 unsigned sel;
312 unsigned swizzle[4];
313 unsigned neg;
314 unsigned abs;
315 unsigned rel;
316 unsigned kc_bank;
317 boolean kc_rel; /* true if cache bank is indexed */
318 uint32_t value[4];
319 };
320
321 struct eg_interp {
322 boolean enabled;
323 unsigned ij_index;
324 };
325
326 struct r600_shader_ctx {
327 struct tgsi_shader_info info;
328 struct tgsi_parse_context parse;
329 const struct tgsi_token *tokens;
330 unsigned type;
331 unsigned file_offset[TGSI_FILE_COUNT];
332 unsigned temp_reg;
333 const struct r600_shader_tgsi_instruction *inst_info;
334 struct r600_bytecode *bc;
335 struct r600_shader *shader;
336 struct r600_shader_src src[4];
337 uint32_t *literals;
338 uint32_t nliterals;
339 uint32_t max_driver_temp_used;
340 /* needed for evergreen interpolation */
341 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
342 /* evergreen/cayman also store sample mask in face register */
343 int face_gpr;
344 /* sample id is .w component stored in fixed point position register */
345 int fixed_pt_position_gpr;
346 int colors_used;
347 boolean clip_vertex_write;
348 unsigned cv_output;
349 unsigned edgeflag_output;
350 int helper_invoc_reg;
351 int cs_block_size_reg;
352 int cs_grid_size_reg;
353 bool cs_block_size_loaded, cs_grid_size_loaded;
354 int fragcoord_input;
355 int next_ring_offset;
356 int gs_out_ring_offset;
357 int gs_next_vertex;
358 struct r600_shader *gs_for_vs;
359 int gs_export_gpr_tregs[4];
360 int gs_rotated_input[2];
361 const struct pipe_stream_output_info *gs_stream_output_info;
362 unsigned enabled_stream_buffers_mask;
363 unsigned tess_input_info; /* temp with tess input offsets */
364 unsigned tess_output_info; /* temp with tess input offsets */
365 unsigned thread_id_gpr; /* temp with thread id calculated for images */
366 bool thread_id_gpr_loaded;
367 };
368
369 struct r600_shader_tgsi_instruction {
370 unsigned op;
371 int (*process)(struct r600_shader_ctx *ctx);
372 };
373
374 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
375 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
376 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
377 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
378 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
379 static int tgsi_else(struct r600_shader_ctx *ctx);
380 static int tgsi_endif(struct r600_shader_ctx *ctx);
381 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
382 static int tgsi_endloop(struct r600_shader_ctx *ctx);
383 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
384 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
385 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
386 unsigned int dst_reg);
387 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
388 const struct r600_shader_src *shader_src,
389 unsigned chan);
390 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
391 unsigned dst_reg, unsigned mask);
392
393 static int tgsi_last_instruction(unsigned writemask)
394 {
395 int i, lasti = 0;
396
397 for (i = 0; i < 4; i++) {
398 if (writemask & (1 << i)) {
399 lasti = i;
400 }
401 }
402 return lasti;
403 }
404
405 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
406 {
407 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
408 unsigned j;
409
410 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
411 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
412 return -EINVAL;
413 }
414 #if 0
415 if (i->Instruction.Label) {
416 R600_ERR("label unsupported\n");
417 return -EINVAL;
418 }
419 #endif
420 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
421 if (i->Src[j].Register.Dimension) {
422 switch (i->Src[j].Register.File) {
423 case TGSI_FILE_CONSTANT:
424 case TGSI_FILE_HW_ATOMIC:
425 break;
426 case TGSI_FILE_INPUT:
427 if (ctx->type == PIPE_SHADER_GEOMETRY ||
428 ctx->type == PIPE_SHADER_TESS_CTRL ||
429 ctx->type == PIPE_SHADER_TESS_EVAL)
430 break;
431 case TGSI_FILE_OUTPUT:
432 if (ctx->type == PIPE_SHADER_TESS_CTRL)
433 break;
434 default:
435 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
436 i->Src[j].Register.File,
437 i->Src[j].Register.Dimension);
438 return -EINVAL;
439 }
440 }
441 }
442 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
443 if (i->Dst[j].Register.Dimension) {
444 if (ctx->type == PIPE_SHADER_TESS_CTRL)
445 continue;
446 R600_ERR("unsupported dst (dimension)\n");
447 return -EINVAL;
448 }
449 }
450 return 0;
451 }
452
453 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
454 {
455 if (interpolate == TGSI_INTERPOLATE_COLOR ||
456 interpolate == TGSI_INTERPOLATE_LINEAR ||
457 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
458 {
459 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
460 int loc;
461
462 switch(location) {
463 case TGSI_INTERPOLATE_LOC_CENTER:
464 loc = 1;
465 break;
466 case TGSI_INTERPOLATE_LOC_CENTROID:
467 loc = 2;
468 break;
469 case TGSI_INTERPOLATE_LOC_SAMPLE:
470 default:
471 loc = 0; break;
472 }
473
474 return is_linear * 3 + loc;
475 }
476
477 return -1;
478 }
479
480 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
481 int input)
482 {
483 int i = eg_get_interpolator_index(
484 ctx->shader->input[input].interpolate,
485 ctx->shader->input[input].interpolate_location);
486 assert(i >= 0);
487 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
488 }
489
490 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
491 {
492 int i, r;
493 struct r600_bytecode_alu alu;
494 int gpr = 0, base_chan = 0;
495 int ij_index = ctx->shader->input[input].ij_index;
496
497 /* work out gpr and base_chan from index */
498 gpr = ij_index / 2;
499 base_chan = (2 * (ij_index % 2)) + 1;
500
501 for (i = 0; i < 8; i++) {
502 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
503
504 if (i < 4)
505 alu.op = ALU_OP2_INTERP_ZW;
506 else
507 alu.op = ALU_OP2_INTERP_XY;
508
509 if ((i > 1) && (i < 6)) {
510 alu.dst.sel = ctx->shader->input[input].gpr;
511 alu.dst.write = 1;
512 }
513
514 alu.dst.chan = i % 4;
515
516 alu.src[0].sel = gpr;
517 alu.src[0].chan = (base_chan - (i % 2));
518
519 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
520
521 alu.bank_swizzle_force = SQ_ALU_VEC_210;
522 if ((i % 4) == 3)
523 alu.last = 1;
524 r = r600_bytecode_add_alu(ctx->bc, &alu);
525 if (r)
526 return r;
527 }
528 return 0;
529 }
530
531 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
532 {
533 int i, r;
534 struct r600_bytecode_alu alu;
535
536 for (i = 0; i < 4; i++) {
537 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
538
539 alu.op = ALU_OP1_INTERP_LOAD_P0;
540
541 alu.dst.sel = ctx->shader->input[input].gpr;
542 alu.dst.write = 1;
543
544 alu.dst.chan = i;
545
546 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
547 alu.src[0].chan = i;
548
549 if (i == 3)
550 alu.last = 1;
551 r = r600_bytecode_add_alu(ctx->bc, &alu);
552 if (r)
553 return r;
554 }
555 return 0;
556 }
557
558 /*
559 * Special export handling in shaders
560 *
561 * shader export ARRAY_BASE for EXPORT_POS:
562 * 60 is position
563 * 61 is misc vector
564 * 62, 63 are clip distance vectors
565 *
566 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
567 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
568 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
569 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
570 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
571 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
572 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
573 * exclusive from render target index)
574 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
575 *
576 *
577 * shader export ARRAY_BASE for EXPORT_PIXEL:
578 * 0-7 CB targets
579 * 61 computed Z vector
580 *
581 * The use of the values exported in the computed Z vector are controlled
582 * by DB_SHADER_CONTROL:
583 * Z_EXPORT_ENABLE - Z as a float in RED
584 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
585 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
586 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
587 * DB_SOURCE_FORMAT - export control restrictions
588 *
589 */
590
591
592 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
593 static int r600_spi_sid(struct r600_shader_io * io)
594 {
595 int index, name = io->name;
596
597 /* These params are handled differently, they don't need
598 * semantic indices, so we'll use 0 for them.
599 */
600 if (name == TGSI_SEMANTIC_POSITION ||
601 name == TGSI_SEMANTIC_PSIZE ||
602 name == TGSI_SEMANTIC_EDGEFLAG ||
603 name == TGSI_SEMANTIC_FACE ||
604 name == TGSI_SEMANTIC_SAMPLEMASK)
605 index = 0;
606 else {
607 if (name == TGSI_SEMANTIC_GENERIC) {
608 /* For generic params simply use sid from tgsi */
609 index = io->sid;
610 } else {
611 /* For non-generic params - pack name and sid into 8 bits */
612 index = 0x80 | (name<<3) | (io->sid);
613 }
614
615 /* Make sure that all really used indices have nonzero value, so
616 * we can just compare it to 0 later instead of comparing the name
617 * with different values to detect special cases. */
618 index++;
619 }
620
621 return index;
622 };
623
624 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
625 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
626 {
627 switch (semantic_name) {
628 case TGSI_SEMANTIC_POSITION:
629 return 0;
630 case TGSI_SEMANTIC_PSIZE:
631 return 1;
632 case TGSI_SEMANTIC_CLIPDIST:
633 assert(index <= 1);
634 return 2 + index;
635 case TGSI_SEMANTIC_GENERIC:
636 if (index <= 63-4)
637 return 4 + index - 9;
638 else
639 /* same explanation as in the default statement,
640 * the only user hitting this is st/nine.
641 */
642 return 0;
643
644 /* patch indices are completely separate and thus start from 0 */
645 case TGSI_SEMANTIC_TESSOUTER:
646 return 0;
647 case TGSI_SEMANTIC_TESSINNER:
648 return 1;
649 case TGSI_SEMANTIC_PATCH:
650 return 2 + index;
651
652 default:
653 /* Don't fail here. The result of this function is only used
654 * for LS, TCS, TES, and GS, where legacy GL semantics can't
655 * occur, but this function is called for all vertex shaders
656 * before it's known whether LS will be compiled or not.
657 */
658 return 0;
659 }
660 }
661
662 /* turn input into interpolate on EG */
663 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
664 {
665 int r = 0;
666
667 if (ctx->shader->input[index].spi_sid) {
668 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
669 if (ctx->shader->input[index].interpolate > 0) {
670 evergreen_interp_assign_ij_index(ctx, index);
671 r = evergreen_interp_alu(ctx, index);
672 } else {
673 r = evergreen_interp_flat(ctx, index);
674 }
675 }
676 return r;
677 }
678
679 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
680 {
681 struct r600_bytecode_alu alu;
682 int i, r;
683 int gpr_front = ctx->shader->input[front].gpr;
684 int gpr_back = ctx->shader->input[back].gpr;
685
686 for (i = 0; i < 4; i++) {
687 memset(&alu, 0, sizeof(alu));
688 alu.op = ALU_OP3_CNDGT;
689 alu.is_op3 = 1;
690 alu.dst.write = 1;
691 alu.dst.sel = gpr_front;
692 alu.src[0].sel = ctx->face_gpr;
693 alu.src[1].sel = gpr_front;
694 alu.src[2].sel = gpr_back;
695
696 alu.dst.chan = i;
697 alu.src[1].chan = i;
698 alu.src[2].chan = i;
699 alu.last = (i==3);
700
701 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
702 return r;
703 }
704
705 return 0;
706 }
707
708 /* execute a single slot ALU calculation */
709 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
710 int dst_sel, int dst_chan,
711 int src0_sel, unsigned src0_chan_val,
712 int src1_sel, unsigned src1_chan_val)
713 {
714 struct r600_bytecode_alu alu;
715 int r, i;
716
717 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
718 for (i = 0; i < 4; i++) {
719 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
720 alu.op = op;
721 alu.src[0].sel = src0_sel;
722 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
723 alu.src[0].value = src0_chan_val;
724 else
725 alu.src[0].chan = src0_chan_val;
726 alu.src[1].sel = src1_sel;
727 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
728 alu.src[1].value = src1_chan_val;
729 else
730 alu.src[1].chan = src1_chan_val;
731 alu.dst.sel = dst_sel;
732 alu.dst.chan = i;
733 alu.dst.write = i == dst_chan;
734 alu.last = (i == 3);
735 r = r600_bytecode_add_alu(ctx->bc, &alu);
736 if (r)
737 return r;
738 }
739 return 0;
740 }
741
742 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
743 alu.op = op;
744 alu.src[0].sel = src0_sel;
745 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
746 alu.src[0].value = src0_chan_val;
747 else
748 alu.src[0].chan = src0_chan_val;
749 alu.src[1].sel = src1_sel;
750 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
751 alu.src[1].value = src1_chan_val;
752 else
753 alu.src[1].chan = src1_chan_val;
754 alu.dst.sel = dst_sel;
755 alu.dst.chan = dst_chan;
756 alu.dst.write = 1;
757 alu.last = 1;
758 r = r600_bytecode_add_alu(ctx->bc, &alu);
759 if (r)
760 return r;
761 return 0;
762 }
763
764 /* execute a single slot ALU calculation */
765 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
766 int dst_sel, int dst_chan,
767 int src0_sel, unsigned src0_chan_val,
768 int src1_sel, unsigned src1_chan_val,
769 int src2_sel, unsigned src2_chan_val)
770 {
771 struct r600_bytecode_alu alu;
772 int r;
773
774 /* validate this for other ops */
775 assert(op == ALU_OP3_MULADD_UINT24 || op == ALU_OP3_CNDE_INT || op == ALU_OP3_BFE_UINT);
776 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
777 alu.op = op;
778 alu.src[0].sel = src0_sel;
779 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
780 alu.src[0].value = src0_chan_val;
781 else
782 alu.src[0].chan = src0_chan_val;
783 alu.src[1].sel = src1_sel;
784 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
785 alu.src[1].value = src1_chan_val;
786 else
787 alu.src[1].chan = src1_chan_val;
788 alu.src[2].sel = src2_sel;
789 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
790 alu.src[2].value = src2_chan_val;
791 else
792 alu.src[2].chan = src2_chan_val;
793 alu.dst.sel = dst_sel;
794 alu.dst.chan = dst_chan;
795 alu.is_op3 = 1;
796 alu.last = 1;
797 r = r600_bytecode_add_alu(ctx->bc, &alu);
798 if (r)
799 return r;
800 return 0;
801 }
802
803 /* put it in temp_reg.x */
804 static int get_lds_offset0(struct r600_shader_ctx *ctx,
805 int rel_patch_chan,
806 int temp_reg, bool is_patch_var)
807 {
808 int r;
809
810 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
811 /* ADD
812 Dimension - patch0_offset (input_vals.z),
813 Non-dim - patch0_data_offset (input_vals.w)
814 */
815 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
816 temp_reg, 0,
817 ctx->tess_output_info, 0,
818 0, rel_patch_chan,
819 ctx->tess_output_info, is_patch_var ? 3 : 2);
820 if (r)
821 return r;
822 return 0;
823 }
824
825 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
826 {
827 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
828 }
829
830 static int r600_get_temp(struct r600_shader_ctx *ctx)
831 {
832 return ctx->temp_reg + ctx->max_driver_temp_used++;
833 }
834
835 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
836 {
837 int i;
838 i = ctx->shader->noutput++;
839 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
840 ctx->shader->output[i].sid = 0;
841 ctx->shader->output[i].gpr = 0;
842 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
843 ctx->shader->output[i].write_mask = 0x4;
844 ctx->shader->output[i].spi_sid = prim_id_sid;
845
846 return 0;
847 }
848
849 static int tgsi_barrier(struct r600_shader_ctx *ctx)
850 {
851 struct r600_bytecode_alu alu;
852 int r;
853
854 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
855 alu.op = ctx->inst_info->op;
856 alu.last = 1;
857
858 r = r600_bytecode_add_alu(ctx->bc, &alu);
859 if (r)
860 return r;
861 return 0;
862 }
863
864 static int tgsi_declaration(struct r600_shader_ctx *ctx)
865 {
866 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
867 int r, i, j, count = d->Range.Last - d->Range.First + 1;
868
869 switch (d->Declaration.File) {
870 case TGSI_FILE_INPUT:
871 for (j = 0; j < count; j++) {
872 i = ctx->shader->ninput + j;
873 assert(i < ARRAY_SIZE(ctx->shader->input));
874 ctx->shader->input[i].name = d->Semantic.Name;
875 ctx->shader->input[i].sid = d->Semantic.Index + j;
876 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
877 ctx->shader->input[i].interpolate_location = d->Interp.Location;
878 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
879 if (ctx->type == PIPE_SHADER_FRAGMENT) {
880 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
881 switch (ctx->shader->input[i].name) {
882 case TGSI_SEMANTIC_FACE:
883 if (ctx->face_gpr != -1)
884 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
885 else
886 ctx->face_gpr = ctx->shader->input[i].gpr;
887 break;
888 case TGSI_SEMANTIC_COLOR:
889 ctx->colors_used++;
890 break;
891 case TGSI_SEMANTIC_POSITION:
892 ctx->fragcoord_input = i;
893 break;
894 case TGSI_SEMANTIC_PRIMID:
895 /* set this for now */
896 ctx->shader->gs_prim_id_input = true;
897 ctx->shader->ps_prim_id_input = i;
898 break;
899 }
900 if (ctx->bc->chip_class >= EVERGREEN) {
901 if ((r = evergreen_interp_input(ctx, i)))
902 return r;
903 }
904 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
905 /* FIXME probably skip inputs if they aren't passed in the ring */
906 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
907 ctx->next_ring_offset += 16;
908 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
909 ctx->shader->gs_prim_id_input = true;
910 }
911 }
912 ctx->shader->ninput += count;
913 break;
914 case TGSI_FILE_OUTPUT:
915 for (j = 0; j < count; j++) {
916 i = ctx->shader->noutput + j;
917 assert(i < ARRAY_SIZE(ctx->shader->output));
918 ctx->shader->output[i].name = d->Semantic.Name;
919 ctx->shader->output[i].sid = d->Semantic.Index + j;
920 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
921 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
922 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
923 if (ctx->type == PIPE_SHADER_VERTEX ||
924 ctx->type == PIPE_SHADER_GEOMETRY ||
925 ctx->type == PIPE_SHADER_TESS_EVAL) {
926 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
927 switch (d->Semantic.Name) {
928 case TGSI_SEMANTIC_CLIPDIST:
929 break;
930 case TGSI_SEMANTIC_PSIZE:
931 ctx->shader->vs_out_misc_write = 1;
932 ctx->shader->vs_out_point_size = 1;
933 break;
934 case TGSI_SEMANTIC_EDGEFLAG:
935 ctx->shader->vs_out_misc_write = 1;
936 ctx->shader->vs_out_edgeflag = 1;
937 ctx->edgeflag_output = i;
938 break;
939 case TGSI_SEMANTIC_VIEWPORT_INDEX:
940 ctx->shader->vs_out_misc_write = 1;
941 ctx->shader->vs_out_viewport = 1;
942 break;
943 case TGSI_SEMANTIC_LAYER:
944 ctx->shader->vs_out_misc_write = 1;
945 ctx->shader->vs_out_layer = 1;
946 break;
947 case TGSI_SEMANTIC_CLIPVERTEX:
948 ctx->clip_vertex_write = TRUE;
949 ctx->cv_output = i;
950 break;
951 }
952 if (ctx->type == PIPE_SHADER_GEOMETRY) {
953 ctx->gs_out_ring_offset += 16;
954 }
955 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
956 switch (d->Semantic.Name) {
957 case TGSI_SEMANTIC_COLOR:
958 ctx->shader->nr_ps_max_color_exports++;
959 break;
960 }
961 }
962 }
963 ctx->shader->noutput += count;
964 break;
965 case TGSI_FILE_TEMPORARY:
966 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
967 if (d->Array.ArrayID) {
968 r600_add_gpr_array(ctx->shader,
969 ctx->file_offset[TGSI_FILE_TEMPORARY] +
970 d->Range.First,
971 d->Range.Last - d->Range.First + 1, 0x0F);
972 }
973 }
974 break;
975
976 case TGSI_FILE_CONSTANT:
977 case TGSI_FILE_SAMPLER:
978 case TGSI_FILE_SAMPLER_VIEW:
979 case TGSI_FILE_ADDRESS:
980 case TGSI_FILE_BUFFER:
981 case TGSI_FILE_IMAGE:
982 case TGSI_FILE_MEMORY:
983 break;
984
985 case TGSI_FILE_HW_ATOMIC:
986 i = ctx->shader->nhwatomic_ranges;
987 ctx->shader->atomics[i].start = d->Range.First;
988 ctx->shader->atomics[i].end = d->Range.Last;
989 ctx->shader->atomics[i].hw_idx = ctx->shader->atomic_base + ctx->shader->nhwatomic;
990 ctx->shader->atomics[i].array_id = d->Array.ArrayID;
991 ctx->shader->atomics[i].buffer_id = d->Dim.Index2D;
992 ctx->shader->nhwatomic_ranges++;
993 ctx->shader->nhwatomic += count;
994 break;
995
996 case TGSI_FILE_SYSTEM_VALUE:
997 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
998 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
999 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
1000 break; /* Already handled from allocate_system_value_inputs */
1001 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
1002 break;
1003 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
1004 break;
1005 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
1006 break;
1007 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1008 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1009 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1010 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1011 unsigned temp_reg = r600_get_temp(ctx);
1012
1013 r = get_lds_offset0(ctx, 2, temp_reg, true);
1014 if (r)
1015 return r;
1016
1017 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1018 temp_reg, 0,
1019 temp_reg, 0,
1020 V_SQ_ALU_SRC_LITERAL, param * 16);
1021 if (r)
1022 return r;
1023
1024 do_lds_fetch_values(ctx, temp_reg, dreg, 0xf);
1025 }
1026 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1027 /* MOV r1.x, r0.x;
1028 MOV r1.y, r0.y;
1029 */
1030 for (i = 0; i < 2; i++) {
1031 struct r600_bytecode_alu alu;
1032 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1033 alu.op = ALU_OP1_MOV;
1034 alu.src[0].sel = 0;
1035 alu.src[0].chan = 0 + i;
1036 alu.dst.sel = 1;
1037 alu.dst.chan = 0 + i;
1038 alu.dst.write = 1;
1039 alu.last = (i == 1) ? 1 : 0;
1040 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1041 return r;
1042 }
1043 /* ADD r1.z, 1.0f, -r0.x */
1044 struct r600_bytecode_alu alu;
1045 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1046 alu.op = ALU_OP2_ADD;
1047 alu.src[0].sel = V_SQ_ALU_SRC_1;
1048 alu.src[1].sel = 1;
1049 alu.src[1].chan = 0;
1050 alu.src[1].neg = 1;
1051 alu.dst.sel = 1;
1052 alu.dst.chan = 2;
1053 alu.dst.write = 1;
1054 alu.last = 1;
1055 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1056 return r;
1057
1058 /* ADD r1.z, r1.z, -r1.y */
1059 alu.op = ALU_OP2_ADD;
1060 alu.src[0].sel = 1;
1061 alu.src[0].chan = 2;
1062 alu.src[1].sel = 1;
1063 alu.src[1].chan = 1;
1064 alu.src[1].neg = 1;
1065 alu.dst.sel = 1;
1066 alu.dst.chan = 2;
1067 alu.dst.write = 1;
1068 alu.last = 1;
1069 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1070 return r;
1071 break;
1072 }
1073 break;
1074 default:
1075 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1076 return -EINVAL;
1077 }
1078 return 0;
1079 }
1080
1081 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1082 {
1083 struct tgsi_parse_context parse;
1084 struct {
1085 boolean enabled;
1086 int *reg;
1087 unsigned name, alternate_name;
1088 } inputs[2] = {
1089 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1090
1091 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1092 };
1093 int num_regs = 0;
1094 unsigned k, i;
1095
1096 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1097 return 0;
1098 }
1099
1100 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1101 while (!tgsi_parse_end_of_tokens(&parse)) {
1102 tgsi_parse_token(&parse);
1103
1104 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1105 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1106 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1107 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1108 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1109 {
1110 int interpolate, location, k;
1111
1112 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1113 location = TGSI_INTERPOLATE_LOC_CENTER;
1114 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1115 location = TGSI_INTERPOLATE_LOC_CENTER;
1116 /* Needs sample positions, currently those are always available */
1117 } else {
1118 location = TGSI_INTERPOLATE_LOC_CENTROID;
1119 }
1120
1121 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1122 k = eg_get_interpolator_index(interpolate, location);
1123 if (k >= 0)
1124 ctx->eg_interpolators[k].enabled = true;
1125 }
1126 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1127 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1128 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1129 for (k = 0; k < ARRAY_SIZE(inputs); k++) {
1130 if (d->Semantic.Name == inputs[k].name ||
1131 d->Semantic.Name == inputs[k].alternate_name) {
1132 inputs[k].enabled = true;
1133 }
1134 }
1135 }
1136 }
1137 }
1138
1139 tgsi_parse_free(&parse);
1140
1141 if (ctx->info.reads_samplemask &&
1142 (ctx->info.uses_linear_sample || ctx->info.uses_linear_sample)) {
1143 inputs[1].enabled = true;
1144 }
1145
1146 if (ctx->bc->chip_class >= EVERGREEN) {
1147 int num_baryc = 0;
1148 /* assign gpr to each interpolator according to priority */
1149 for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
1150 if (ctx->eg_interpolators[i].enabled) {
1151 ctx->eg_interpolators[i].ij_index = num_baryc;
1152 num_baryc++;
1153 }
1154 }
1155 num_baryc = (num_baryc + 1) >> 1;
1156 gpr_offset += num_baryc;
1157 }
1158
1159 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
1160 boolean enabled = inputs[i].enabled;
1161 int *reg = inputs[i].reg;
1162 unsigned name = inputs[i].name;
1163
1164 if (enabled) {
1165 int gpr = gpr_offset + num_regs++;
1166 ctx->shader->nsys_inputs++;
1167
1168 // add to inputs, allocate a gpr
1169 k = ctx->shader->ninput++;
1170 ctx->shader->input[k].name = name;
1171 ctx->shader->input[k].sid = 0;
1172 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1173 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1174 *reg = ctx->shader->input[k].gpr = gpr;
1175 }
1176 }
1177
1178 return gpr_offset + num_regs;
1179 }
1180
1181 /*
1182 * for evergreen we need to scan the shader to find the number of GPRs we need to
1183 * reserve for interpolation and system values
1184 *
1185 * we need to know if we are going to emit any sample or centroid inputs
1186 * if perspective and linear are required
1187 */
1188 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1189 {
1190 unsigned i;
1191
1192 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1193
1194 /*
1195 * Could get this information from the shader info. But right now
1196 * we interpolate all declared inputs, whereas the shader info will
1197 * only contain the bits if the inputs are actually used, so it might
1198 * not be safe...
1199 */
1200 for (i = 0; i < ctx->info.num_inputs; i++) {
1201 int k;
1202 /* skip position/face/mask/sampleid */
1203 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1204 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1205 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1206 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1207 continue;
1208
1209 k = eg_get_interpolator_index(
1210 ctx->info.input_interpolate[i],
1211 ctx->info.input_interpolate_loc[i]);
1212 if (k >= 0)
1213 ctx->eg_interpolators[k].enabled = TRUE;
1214 }
1215
1216 /* XXX PULL MODEL and LINE STIPPLE */
1217
1218 return allocate_system_value_inputs(ctx, 0);
1219 }
1220
1221 /* sample_id_sel == NULL means fetch for current sample */
1222 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1223 {
1224 struct r600_bytecode_vtx vtx;
1225 int r, t1;
1226
1227 t1 = r600_get_temp(ctx);
1228
1229 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1230 vtx.op = FETCH_OP_VFETCH;
1231 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1232 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1233 if (sample_id == NULL) {
1234 assert(ctx->fixed_pt_position_gpr != -1);
1235
1236 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1237 vtx.src_sel_x = 3;
1238 }
1239 else {
1240 struct r600_bytecode_alu alu;
1241
1242 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1243 alu.op = ALU_OP1_MOV;
1244 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1245 alu.dst.sel = t1;
1246 alu.dst.write = 1;
1247 alu.last = 1;
1248 r = r600_bytecode_add_alu(ctx->bc, &alu);
1249 if (r)
1250 return r;
1251
1252 vtx.src_gpr = t1;
1253 vtx.src_sel_x = 0;
1254 }
1255 vtx.mega_fetch_count = 16;
1256 vtx.dst_gpr = t1;
1257 vtx.dst_sel_x = 0;
1258 vtx.dst_sel_y = 1;
1259 vtx.dst_sel_z = 2;
1260 vtx.dst_sel_w = 3;
1261 vtx.data_format = FMT_32_32_32_32_FLOAT;
1262 vtx.num_format_all = 2;
1263 vtx.format_comp_all = 1;
1264 vtx.use_const_fields = 0;
1265 vtx.offset = 0;
1266 vtx.endian = r600_endian_swap(32);
1267 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1268
1269 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1270 if (r)
1271 return r;
1272
1273 return t1;
1274 }
1275
1276 static int eg_load_helper_invocation(struct r600_shader_ctx *ctx)
1277 {
1278 int r;
1279 struct r600_bytecode_alu alu;
1280
1281 /* do a vtx fetch with wqm set on the vtx fetch */
1282 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1283 alu.op = ALU_OP1_MOV;
1284 alu.dst.sel = ctx->helper_invoc_reg;
1285 alu.dst.chan = 0;
1286 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
1287 alu.src[0].value = 0xffffffff;
1288 alu.dst.write = 1;
1289 alu.last = 1;
1290 r = r600_bytecode_add_alu(ctx->bc, &alu);
1291 if (r)
1292 return r;
1293
1294 /* do a vtx fetch in VPM mode */
1295 struct r600_bytecode_vtx vtx;
1296 memset(&vtx, 0, sizeof(vtx));
1297 vtx.op = FETCH_OP_GET_BUFFER_RESINFO;
1298 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1299 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1300 vtx.src_gpr = 0;
1301 vtx.mega_fetch_count = 16; /* no idea here really... */
1302 vtx.dst_gpr = ctx->helper_invoc_reg;
1303 vtx.dst_sel_x = 4;
1304 vtx.dst_sel_y = 7; /* SEL_Y */
1305 vtx.dst_sel_z = 7; /* SEL_Z */
1306 vtx.dst_sel_w = 7; /* SEL_W */
1307 vtx.data_format = FMT_32;
1308 if ((r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx)))
1309 return r;
1310 ctx->bc->cf_last->vpm = 1;
1311 return 0;
1312 }
1313
1314 static int cm_load_helper_invocation(struct r600_shader_ctx *ctx)
1315 {
1316 int r;
1317 struct r600_bytecode_alu alu;
1318
1319 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1320 alu.op = ALU_OP1_MOV;
1321 alu.dst.sel = ctx->helper_invoc_reg;
1322 alu.dst.chan = 0;
1323 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
1324 alu.src[0].value = 0xffffffff;
1325 alu.dst.write = 1;
1326 alu.last = 1;
1327 r = r600_bytecode_add_alu(ctx->bc, &alu);
1328 if (r)
1329 return r;
1330
1331 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1332 alu.op = ALU_OP1_MOV;
1333 alu.dst.sel = ctx->helper_invoc_reg;
1334 alu.dst.chan = 0;
1335 alu.src[0].sel = V_SQ_ALU_SRC_0;
1336 alu.dst.write = 1;
1337 alu.last = 1;
1338 r = r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_VALID_PIXEL_MODE);
1339 if (r)
1340 return r;
1341
1342 return ctx->helper_invoc_reg;
1343 }
1344
1345 static int load_block_grid_size(struct r600_shader_ctx *ctx, bool load_block)
1346 {
1347 struct r600_bytecode_vtx vtx;
1348 int r, t1;
1349
1350 if (ctx->cs_block_size_loaded)
1351 return ctx->cs_block_size_reg;
1352 if (ctx->cs_grid_size_loaded)
1353 return ctx->cs_grid_size_reg;
1354
1355 t1 = load_block ? ctx->cs_block_size_reg : ctx->cs_grid_size_reg;
1356 struct r600_bytecode_alu alu;
1357 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1358 alu.op = ALU_OP1_MOV;
1359 alu.src[0].sel = V_SQ_ALU_SRC_0;
1360 alu.dst.sel = t1;
1361 alu.dst.write = 1;
1362 alu.last = 1;
1363 r = r600_bytecode_add_alu(ctx->bc, &alu);
1364 if (r)
1365 return r;
1366
1367 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1368 vtx.op = FETCH_OP_VFETCH;
1369 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1370 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1371 vtx.src_gpr = t1;
1372 vtx.src_sel_x = 0;
1373
1374 vtx.mega_fetch_count = 16;
1375 vtx.dst_gpr = t1;
1376 vtx.dst_sel_x = 0;
1377 vtx.dst_sel_y = 1;
1378 vtx.dst_sel_z = 2;
1379 vtx.dst_sel_w = 7;
1380 vtx.data_format = FMT_32_32_32_32;
1381 vtx.num_format_all = 1;
1382 vtx.format_comp_all = 0;
1383 vtx.use_const_fields = 0;
1384 vtx.offset = load_block ? 0 : 16; // first element is size of buffer
1385 vtx.endian = r600_endian_swap(32);
1386 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1387
1388 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1389 if (r)
1390 return r;
1391
1392 if (load_block)
1393 ctx->cs_block_size_loaded = true;
1394 else
1395 ctx->cs_grid_size_loaded = true;
1396 return t1;
1397 }
1398
1399 static void tgsi_src(struct r600_shader_ctx *ctx,
1400 const struct tgsi_full_src_register *tgsi_src,
1401 struct r600_shader_src *r600_src)
1402 {
1403 memset(r600_src, 0, sizeof(*r600_src));
1404 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1405 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1406 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1407 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1408 r600_src->neg = tgsi_src->Register.Negate;
1409 r600_src->abs = tgsi_src->Register.Absolute;
1410
1411 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1412 int index;
1413 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1414 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1415 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1416
1417 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1418 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1419 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1420 return;
1421 }
1422 index = tgsi_src->Register.Index;
1423 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1424 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1425 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1426 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1427 r600_src->swizzle[0] = 2; // Z value
1428 r600_src->swizzle[1] = 2;
1429 r600_src->swizzle[2] = 2;
1430 r600_src->swizzle[3] = 2;
1431 r600_src->sel = ctx->face_gpr;
1432 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1433 r600_src->swizzle[0] = 3; // W value
1434 r600_src->swizzle[1] = 3;
1435 r600_src->swizzle[2] = 3;
1436 r600_src->swizzle[3] = 3;
1437 r600_src->sel = ctx->fixed_pt_position_gpr;
1438 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1439 r600_src->swizzle[0] = 0;
1440 r600_src->swizzle[1] = 1;
1441 r600_src->swizzle[2] = 4;
1442 r600_src->swizzle[3] = 4;
1443 r600_src->sel = load_sample_position(ctx, NULL, -1);
1444 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1445 r600_src->swizzle[0] = 3;
1446 r600_src->swizzle[1] = 3;
1447 r600_src->swizzle[2] = 3;
1448 r600_src->swizzle[3] = 3;
1449 r600_src->sel = 0;
1450 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1451 r600_src->swizzle[0] = 0;
1452 r600_src->swizzle[1] = 0;
1453 r600_src->swizzle[2] = 0;
1454 r600_src->swizzle[3] = 0;
1455 r600_src->sel = 0;
1456 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_THREAD_ID) {
1457 r600_src->sel = 0;
1458 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_BLOCK_ID) {
1459 r600_src->sel = 1;
1460 } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1461 r600_src->swizzle[0] = 3;
1462 r600_src->swizzle[1] = 3;
1463 r600_src->swizzle[2] = 3;
1464 r600_src->swizzle[3] = 3;
1465 r600_src->sel = 1;
1466 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1467 r600_src->swizzle[0] = 2;
1468 r600_src->swizzle[1] = 2;
1469 r600_src->swizzle[2] = 2;
1470 r600_src->swizzle[3] = 2;
1471 r600_src->sel = 0;
1472 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1473 r600_src->sel = 1;
1474 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1475 r600_src->sel = 3;
1476 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1477 r600_src->sel = 2;
1478 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1479 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
1480 r600_src->sel = ctx->tess_input_info;
1481 r600_src->swizzle[0] = 2;
1482 r600_src->swizzle[1] = 2;
1483 r600_src->swizzle[2] = 2;
1484 r600_src->swizzle[3] = 2;
1485 } else {
1486 r600_src->sel = ctx->tess_input_info;
1487 r600_src->swizzle[0] = 3;
1488 r600_src->swizzle[1] = 3;
1489 r600_src->swizzle[2] = 3;
1490 r600_src->swizzle[3] = 3;
1491 }
1492 } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1493 r600_src->sel = 0;
1494 r600_src->swizzle[0] = 0;
1495 r600_src->swizzle[1] = 0;
1496 r600_src->swizzle[2] = 0;
1497 r600_src->swizzle[3] = 0;
1498 } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1499 r600_src->sel = 0;
1500 r600_src->swizzle[0] = 3;
1501 r600_src->swizzle[1] = 3;
1502 r600_src->swizzle[2] = 3;
1503 r600_src->swizzle[3] = 3;
1504 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_GRID_SIZE) {
1505 r600_src->sel = load_block_grid_size(ctx, false);
1506 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_BLOCK_SIZE) {
1507 r600_src->sel = load_block_grid_size(ctx, true);
1508 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_HELPER_INVOCATION) {
1509 r600_src->sel = ctx->helper_invoc_reg;
1510 r600_src->swizzle[0] = 0;
1511 r600_src->swizzle[1] = 0;
1512 r600_src->swizzle[2] = 0;
1513 r600_src->swizzle[3] = 0;
1514 }
1515 } else {
1516 if (tgsi_src->Register.Indirect)
1517 r600_src->rel = V_SQ_REL_RELATIVE;
1518 r600_src->sel = tgsi_src->Register.Index;
1519 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1520 }
1521 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1522 if (tgsi_src->Register.Dimension) {
1523 r600_src->kc_bank = tgsi_src->Dimension.Index;
1524 if (tgsi_src->Dimension.Indirect) {
1525 r600_src->kc_rel = 1;
1526 }
1527 }
1528 }
1529 }
1530
1531 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1532 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1533 unsigned int dst_reg)
1534 {
1535 struct r600_bytecode_vtx vtx;
1536 unsigned int ar_reg;
1537 int r;
1538
1539 if (offset) {
1540 struct r600_bytecode_alu alu;
1541
1542 memset(&alu, 0, sizeof(alu));
1543
1544 alu.op = ALU_OP2_ADD_INT;
1545 alu.src[0].sel = ctx->bc->ar_reg;
1546 alu.src[0].chan = ar_chan;
1547
1548 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1549 alu.src[1].value = offset;
1550
1551 alu.dst.sel = dst_reg;
1552 alu.dst.chan = ar_chan;
1553 alu.dst.write = 1;
1554 alu.last = 1;
1555
1556 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1557 return r;
1558
1559 ar_reg = dst_reg;
1560 } else {
1561 ar_reg = ctx->bc->ar_reg;
1562 }
1563
1564 memset(&vtx, 0, sizeof(vtx));
1565 vtx.buffer_id = cb_idx;
1566 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1567 vtx.src_gpr = ar_reg;
1568 vtx.src_sel_x = ar_chan;
1569 vtx.mega_fetch_count = 16;
1570 vtx.dst_gpr = dst_reg;
1571 vtx.dst_sel_x = 0; /* SEL_X */
1572 vtx.dst_sel_y = 1; /* SEL_Y */
1573 vtx.dst_sel_z = 2; /* SEL_Z */
1574 vtx.dst_sel_w = 3; /* SEL_W */
1575 vtx.data_format = FMT_32_32_32_32_FLOAT;
1576 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1577 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1578 vtx.endian = r600_endian_swap(32);
1579 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1580
1581 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1582 return r;
1583
1584 return 0;
1585 }
1586
1587 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1588 {
1589 struct r600_bytecode_vtx vtx;
1590 int r;
1591 unsigned index = src->Register.Index;
1592 unsigned vtx_id = src->Dimension.Index;
1593 int offset_reg = ctx->gs_rotated_input[vtx_id / 3];
1594 int offset_chan = vtx_id % 3;
1595 int t2 = 0;
1596
1597 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1598 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1599
1600 if (offset_reg == ctx->gs_rotated_input[0] && offset_chan == 2)
1601 offset_chan = 3;
1602
1603 if (src->Dimension.Indirect || src->Register.Indirect)
1604 t2 = r600_get_temp(ctx);
1605
1606 if (src->Dimension.Indirect) {
1607 int treg[3];
1608 struct r600_bytecode_alu alu;
1609 int r, i;
1610 unsigned addr_reg;
1611 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1612 if (src->DimIndirect.Index > 0) {
1613 r = single_alu_op2(ctx, ALU_OP1_MOV,
1614 ctx->bc->ar_reg, 0,
1615 addr_reg, 0,
1616 0, 0);
1617 if (r)
1618 return r;
1619 }
1620 /*
1621 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1622 at least this is what fglrx seems to do. */
1623 for (i = 0; i < 3; i++) {
1624 treg[i] = r600_get_temp(ctx);
1625 }
1626 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1627
1628 for (i = 0; i < 3; i++) {
1629 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1630 alu.op = ALU_OP1_MOV;
1631 alu.src[0].sel = ctx->gs_rotated_input[0];
1632 alu.src[0].chan = i == 2 ? 3 : i;
1633 alu.dst.sel = treg[i];
1634 alu.dst.chan = 0;
1635 alu.dst.write = 1;
1636 alu.last = 1;
1637 r = r600_bytecode_add_alu(ctx->bc, &alu);
1638 if (r)
1639 return r;
1640 }
1641 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1642 alu.op = ALU_OP1_MOV;
1643 alu.src[0].sel = treg[0];
1644 alu.src[0].rel = 1;
1645 alu.dst.sel = t2;
1646 alu.dst.write = 1;
1647 alu.last = 1;
1648 r = r600_bytecode_add_alu(ctx->bc, &alu);
1649 if (r)
1650 return r;
1651 offset_reg = t2;
1652 offset_chan = 0;
1653 }
1654
1655 if (src->Register.Indirect) {
1656 int addr_reg;
1657 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1658
1659 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1660
1661 /* pull the value from index_reg */
1662 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1663 t2, 1,
1664 addr_reg, 0,
1665 V_SQ_ALU_SRC_LITERAL, first);
1666 if (r)
1667 return r;
1668 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1669 t2, 0,
1670 t2, 1,
1671 V_SQ_ALU_SRC_LITERAL, 4,
1672 offset_reg, offset_chan);
1673 if (r)
1674 return r;
1675 offset_reg = t2;
1676 offset_chan = 0;
1677 index = src->Register.Index - first;
1678 }
1679
1680 memset(&vtx, 0, sizeof(vtx));
1681 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1682 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1683 vtx.src_gpr = offset_reg;
1684 vtx.src_sel_x = offset_chan;
1685 vtx.offset = index * 16; /*bytes*/
1686 vtx.mega_fetch_count = 16;
1687 vtx.dst_gpr = dst_reg;
1688 vtx.dst_sel_x = 0; /* SEL_X */
1689 vtx.dst_sel_y = 1; /* SEL_Y */
1690 vtx.dst_sel_z = 2; /* SEL_Z */
1691 vtx.dst_sel_w = 3; /* SEL_W */
1692 if (ctx->bc->chip_class >= EVERGREEN) {
1693 vtx.use_const_fields = 1;
1694 } else {
1695 vtx.data_format = FMT_32_32_32_32_FLOAT;
1696 }
1697
1698 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1699 return r;
1700
1701 return 0;
1702 }
1703
1704 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1705 {
1706 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1707 unsigned i;
1708
1709 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1710 struct tgsi_full_src_register *src = &inst->Src[i];
1711
1712 if (src->Register.File == TGSI_FILE_INPUT) {
1713 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1714 /* primitive id is in R0.z */
1715 ctx->src[i].sel = 0;
1716 ctx->src[i].swizzle[0] = 2;
1717 }
1718 }
1719 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1720 int treg = r600_get_temp(ctx);
1721
1722 fetch_gs_input(ctx, src, treg);
1723 ctx->src[i].sel = treg;
1724 ctx->src[i].rel = 0;
1725 }
1726 }
1727 return 0;
1728 }
1729
1730
1731 /* Tessellation shaders pass outputs to the next shader using LDS.
1732 *
1733 * LS outputs = TCS(HS) inputs
1734 * TCS(HS) outputs = TES(DS) inputs
1735 *
1736 * The LDS layout is:
1737 * - TCS inputs for patch 0
1738 * - TCS inputs for patch 1
1739 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1740 * - ...
1741 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1742 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1743 * - TCS outputs for patch 1
1744 * - Per-patch TCS outputs for patch 1
1745 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1746 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1747 * - ...
1748 *
1749 * All three shaders VS(LS), TCS, TES share the same LDS space.
1750 */
1751 /* this will return with the dw address in temp_reg.x */
1752 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1753 const struct tgsi_full_dst_register *dst,
1754 const struct tgsi_full_src_register *src,
1755 int stride_bytes_reg, int stride_bytes_chan)
1756 {
1757 struct tgsi_full_dst_register reg;
1758 ubyte *name, *index, *array_first;
1759 int r;
1760 int param;
1761 struct tgsi_shader_info *info = &ctx->info;
1762 /* Set the register description. The address computation is the same
1763 * for sources and destinations. */
1764 if (src) {
1765 reg.Register.File = src->Register.File;
1766 reg.Register.Index = src->Register.Index;
1767 reg.Register.Indirect = src->Register.Indirect;
1768 reg.Register.Dimension = src->Register.Dimension;
1769 reg.Indirect = src->Indirect;
1770 reg.Dimension = src->Dimension;
1771 reg.DimIndirect = src->DimIndirect;
1772 } else
1773 reg = *dst;
1774
1775 /* If the register is 2-dimensional (e.g. an array of vertices
1776 * in a primitive), calculate the base address of the vertex. */
1777 if (reg.Register.Dimension) {
1778 int sel, chan;
1779 if (reg.Dimension.Indirect) {
1780 unsigned addr_reg;
1781 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1782
1783 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1784 /* pull the value from index_reg */
1785 sel = addr_reg;
1786 chan = 0;
1787 } else {
1788 sel = V_SQ_ALU_SRC_LITERAL;
1789 chan = reg.Dimension.Index;
1790 }
1791
1792 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1793 temp_reg, 0,
1794 stride_bytes_reg, stride_bytes_chan,
1795 sel, chan,
1796 temp_reg, 0);
1797 if (r)
1798 return r;
1799 }
1800
1801 if (reg.Register.File == TGSI_FILE_INPUT) {
1802 name = info->input_semantic_name;
1803 index = info->input_semantic_index;
1804 array_first = info->input_array_first;
1805 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1806 name = info->output_semantic_name;
1807 index = info->output_semantic_index;
1808 array_first = info->output_array_first;
1809 } else {
1810 assert(0);
1811 return -1;
1812 }
1813 if (reg.Register.Indirect) {
1814 int addr_reg;
1815 int first;
1816 /* Add the relative address of the element. */
1817 if (reg.Indirect.ArrayID)
1818 first = array_first[reg.Indirect.ArrayID];
1819 else
1820 first = reg.Register.Index;
1821
1822 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
1823
1824 /* pull the value from index_reg */
1825 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1826 temp_reg, 0,
1827 V_SQ_ALU_SRC_LITERAL, 16,
1828 addr_reg, 0,
1829 temp_reg, 0);
1830 if (r)
1831 return r;
1832
1833 param = r600_get_lds_unique_index(name[first],
1834 index[first]);
1835
1836 } else {
1837 param = r600_get_lds_unique_index(name[reg.Register.Index],
1838 index[reg.Register.Index]);
1839 }
1840
1841 /* add to base_addr - passed in temp_reg.x */
1842 if (param) {
1843 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1844 temp_reg, 0,
1845 temp_reg, 0,
1846 V_SQ_ALU_SRC_LITERAL, param * 16);
1847 if (r)
1848 return r;
1849
1850 }
1851 return 0;
1852 }
1853
1854 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
1855 unsigned dst_reg, unsigned mask)
1856 {
1857 struct r600_bytecode_alu alu;
1858 int r, i, lasti;
1859
1860 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
1861 ctx->bc->force_add_cf = 1;
1862
1863 lasti = tgsi_last_instruction(mask);
1864 for (i = 1; i <= lasti; i++) {
1865 if (!(mask & (1 << i)))
1866 continue;
1867
1868 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1869 temp_reg, i,
1870 temp_reg, 0,
1871 V_SQ_ALU_SRC_LITERAL, 4 * i);
1872 if (r)
1873 return r;
1874 }
1875 for (i = 0; i <= lasti; i++) {
1876 if (!(mask & (1 << i)))
1877 continue;
1878
1879 /* emit an LDS_READ_RET */
1880 memset(&alu, 0, sizeof(alu));
1881 alu.op = LDS_OP1_LDS_READ_RET;
1882 alu.src[0].sel = temp_reg;
1883 alu.src[0].chan = i;
1884 alu.src[1].sel = V_SQ_ALU_SRC_0;
1885 alu.src[2].sel = V_SQ_ALU_SRC_0;
1886 alu.dst.chan = 0;
1887 alu.is_lds_idx_op = true;
1888 alu.last = 1;
1889 r = r600_bytecode_add_alu(ctx->bc, &alu);
1890 if (r)
1891 return r;
1892 }
1893 for (i = 0; i <= lasti; i++) {
1894 if (!(mask & (1 << i)))
1895 continue;
1896
1897 /* then read from LDS_OQ_A_POP */
1898 memset(&alu, 0, sizeof(alu));
1899
1900 alu.op = ALU_OP1_MOV;
1901 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
1902 alu.src[0].chan = 0;
1903 alu.dst.sel = dst_reg;
1904 alu.dst.chan = i;
1905 alu.dst.write = 1;
1906 alu.last = 1;
1907 r = r600_bytecode_add_alu(ctx->bc, &alu);
1908 if (r)
1909 return r;
1910 }
1911 return 0;
1912 }
1913
1914 static int fetch_mask(struct tgsi_src_register *reg)
1915 {
1916 int mask = 0;
1917 mask |= 1 << reg->SwizzleX;
1918 mask |= 1 << reg->SwizzleY;
1919 mask |= 1 << reg->SwizzleZ;
1920 mask |= 1 << reg->SwizzleW;
1921 return mask;
1922 }
1923
1924 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1925 {
1926 int r;
1927 unsigned temp_reg = r600_get_temp(ctx);
1928
1929 r = get_lds_offset0(ctx, 2, temp_reg,
1930 src->Register.Dimension ? false : true);
1931 if (r)
1932 return r;
1933
1934 /* the base address is now in temp.x */
1935 r = r600_get_byte_address(ctx, temp_reg,
1936 NULL, src, ctx->tess_output_info, 1);
1937 if (r)
1938 return r;
1939
1940 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
1941 if (r)
1942 return r;
1943 return 0;
1944 }
1945
1946 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1947 {
1948 int r;
1949 unsigned temp_reg = r600_get_temp(ctx);
1950
1951 /* t.x = ips * r0.y */
1952 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
1953 temp_reg, 0,
1954 ctx->tess_input_info, 0,
1955 0, 1);
1956
1957 if (r)
1958 return r;
1959
1960 /* the base address is now in temp.x */
1961 r = r600_get_byte_address(ctx, temp_reg,
1962 NULL, src, ctx->tess_input_info, 1);
1963 if (r)
1964 return r;
1965
1966 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
1967 if (r)
1968 return r;
1969 return 0;
1970 }
1971
1972 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1973 {
1974 int r;
1975 unsigned temp_reg = r600_get_temp(ctx);
1976
1977 r = get_lds_offset0(ctx, 1, temp_reg,
1978 src->Register.Dimension ? false : true);
1979 if (r)
1980 return r;
1981 /* the base address is now in temp.x */
1982 r = r600_get_byte_address(ctx, temp_reg,
1983 NULL, src,
1984 ctx->tess_output_info, 1);
1985 if (r)
1986 return r;
1987
1988 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
1989 if (r)
1990 return r;
1991 return 0;
1992 }
1993
1994 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
1995 {
1996 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1997 unsigned i;
1998
1999 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2000 struct tgsi_full_src_register *src = &inst->Src[i];
2001
2002 if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
2003 int treg = r600_get_temp(ctx);
2004 fetch_tes_input(ctx, src, treg);
2005 ctx->src[i].sel = treg;
2006 ctx->src[i].rel = 0;
2007 }
2008 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
2009 int treg = r600_get_temp(ctx);
2010 fetch_tcs_input(ctx, src, treg);
2011 ctx->src[i].sel = treg;
2012 ctx->src[i].rel = 0;
2013 }
2014 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
2015 int treg = r600_get_temp(ctx);
2016 fetch_tcs_output(ctx, src, treg);
2017 ctx->src[i].sel = treg;
2018 ctx->src[i].rel = 0;
2019 }
2020 }
2021 return 0;
2022 }
2023
2024 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
2025 {
2026 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2027 struct r600_bytecode_alu alu;
2028 int i, j, k, nconst, r;
2029
2030 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
2031 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
2032 nconst++;
2033 }
2034 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
2035 }
2036 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
2037 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
2038 continue;
2039 }
2040
2041 if (ctx->src[i].rel) {
2042 int chan = inst->Src[i].Indirect.Swizzle;
2043 int treg = r600_get_temp(ctx);
2044 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
2045 return r;
2046
2047 ctx->src[i].kc_bank = 0;
2048 ctx->src[i].kc_rel = 0;
2049 ctx->src[i].sel = treg;
2050 ctx->src[i].rel = 0;
2051 j--;
2052 } else if (j > 0) {
2053 int treg = r600_get_temp(ctx);
2054 for (k = 0; k < 4; k++) {
2055 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2056 alu.op = ALU_OP1_MOV;
2057 alu.src[0].sel = ctx->src[i].sel;
2058 alu.src[0].chan = k;
2059 alu.src[0].rel = ctx->src[i].rel;
2060 alu.src[0].kc_bank = ctx->src[i].kc_bank;
2061 alu.src[0].kc_rel = ctx->src[i].kc_rel;
2062 alu.dst.sel = treg;
2063 alu.dst.chan = k;
2064 alu.dst.write = 1;
2065 if (k == 3)
2066 alu.last = 1;
2067 r = r600_bytecode_add_alu(ctx->bc, &alu);
2068 if (r)
2069 return r;
2070 }
2071 ctx->src[i].sel = treg;
2072 ctx->src[i].rel =0;
2073 j--;
2074 }
2075 }
2076 return 0;
2077 }
2078
2079 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
2080 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
2081 {
2082 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2083 struct r600_bytecode_alu alu;
2084 int i, j, k, nliteral, r;
2085
2086 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
2087 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
2088 nliteral++;
2089 }
2090 }
2091 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
2092 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
2093 int treg = r600_get_temp(ctx);
2094 for (k = 0; k < 4; k++) {
2095 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2096 alu.op = ALU_OP1_MOV;
2097 alu.src[0].sel = ctx->src[i].sel;
2098 alu.src[0].chan = k;
2099 alu.src[0].value = ctx->src[i].value[k];
2100 alu.dst.sel = treg;
2101 alu.dst.chan = k;
2102 alu.dst.write = 1;
2103 if (k == 3)
2104 alu.last = 1;
2105 r = r600_bytecode_add_alu(ctx->bc, &alu);
2106 if (r)
2107 return r;
2108 }
2109 ctx->src[i].sel = treg;
2110 j--;
2111 }
2112 }
2113 return 0;
2114 }
2115
2116 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
2117 {
2118 int i, r, count = ctx->shader->ninput;
2119
2120 for (i = 0; i < count; i++) {
2121 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
2122 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
2123 if (r)
2124 return r;
2125 }
2126 }
2127 return 0;
2128 }
2129
2130 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
2131 int stream, unsigned *stream_item_size UNUSED)
2132 {
2133 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
2134 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
2135 int j, r;
2136 unsigned i;
2137
2138 /* Sanity checking. */
2139 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
2140 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
2141 r = -EINVAL;
2142 goto out_err;
2143 }
2144 for (i = 0; i < so->num_outputs; i++) {
2145 if (so->output[i].output_buffer >= 4) {
2146 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2147 so->output[i].output_buffer);
2148 r = -EINVAL;
2149 goto out_err;
2150 }
2151 }
2152
2153 /* Initialize locations where the outputs are stored. */
2154 for (i = 0; i < so->num_outputs; i++) {
2155
2156 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2157 start_comp[i] = so->output[i].start_component;
2158 /* Lower outputs with dst_offset < start_component.
2159 *
2160 * We can only output 4D vectors with a write mask, e.g. we can
2161 * only output the W component at offset 3, etc. If we want
2162 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2163 * to move it to X and output X. */
2164 if (so->output[i].dst_offset < so->output[i].start_component) {
2165 unsigned tmp = r600_get_temp(ctx);
2166
2167 for (j = 0; j < so->output[i].num_components; j++) {
2168 struct r600_bytecode_alu alu;
2169 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2170 alu.op = ALU_OP1_MOV;
2171 alu.src[0].sel = so_gpr[i];
2172 alu.src[0].chan = so->output[i].start_component + j;
2173
2174 alu.dst.sel = tmp;
2175 alu.dst.chan = j;
2176 alu.dst.write = 1;
2177 if (j == so->output[i].num_components - 1)
2178 alu.last = 1;
2179 r = r600_bytecode_add_alu(ctx->bc, &alu);
2180 if (r)
2181 return r;
2182 }
2183 start_comp[i] = 0;
2184 so_gpr[i] = tmp;
2185 }
2186 }
2187
2188 /* Write outputs to buffers. */
2189 for (i = 0; i < so->num_outputs; i++) {
2190 struct r600_bytecode_output output;
2191
2192 if (stream != -1 && stream != so->output[i].stream)
2193 continue;
2194
2195 memset(&output, 0, sizeof(struct r600_bytecode_output));
2196 output.gpr = so_gpr[i];
2197 output.elem_size = so->output[i].num_components - 1;
2198 if (output.elem_size == 2)
2199 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2200 output.array_base = so->output[i].dst_offset - start_comp[i];
2201 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2202 output.burst_count = 1;
2203 /* array_size is an upper limit for the burst_count
2204 * with MEM_STREAM instructions */
2205 output.array_size = 0xFFF;
2206 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2207
2208 if (ctx->bc->chip_class >= EVERGREEN) {
2209 switch (so->output[i].output_buffer) {
2210 case 0:
2211 output.op = CF_OP_MEM_STREAM0_BUF0;
2212 break;
2213 case 1:
2214 output.op = CF_OP_MEM_STREAM0_BUF1;
2215 break;
2216 case 2:
2217 output.op = CF_OP_MEM_STREAM0_BUF2;
2218 break;
2219 case 3:
2220 output.op = CF_OP_MEM_STREAM0_BUF3;
2221 break;
2222 }
2223 output.op += so->output[i].stream * 4;
2224 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2225 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2226 } else {
2227 switch (so->output[i].output_buffer) {
2228 case 0:
2229 output.op = CF_OP_MEM_STREAM0;
2230 break;
2231 case 1:
2232 output.op = CF_OP_MEM_STREAM1;
2233 break;
2234 case 2:
2235 output.op = CF_OP_MEM_STREAM2;
2236 break;
2237 case 3:
2238 output.op = CF_OP_MEM_STREAM3;
2239 break;
2240 }
2241 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2242 }
2243 r = r600_bytecode_add_output(ctx->bc, &output);
2244 if (r)
2245 goto out_err;
2246 }
2247 return 0;
2248 out_err:
2249 return r;
2250 }
2251
2252 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2253 {
2254 struct r600_bytecode_alu alu;
2255 unsigned reg;
2256
2257 if (!ctx->shader->vs_out_edgeflag)
2258 return;
2259
2260 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2261
2262 /* clamp(x, 0, 1) */
2263 memset(&alu, 0, sizeof(alu));
2264 alu.op = ALU_OP1_MOV;
2265 alu.src[0].sel = reg;
2266 alu.dst.sel = reg;
2267 alu.dst.write = 1;
2268 alu.dst.clamp = 1;
2269 alu.last = 1;
2270 r600_bytecode_add_alu(ctx->bc, &alu);
2271
2272 memset(&alu, 0, sizeof(alu));
2273 alu.op = ALU_OP1_FLT_TO_INT;
2274 alu.src[0].sel = reg;
2275 alu.dst.sel = reg;
2276 alu.dst.write = 1;
2277 alu.last = 1;
2278 r600_bytecode_add_alu(ctx->bc, &alu);
2279 }
2280
2281 static int generate_gs_copy_shader(struct r600_context *rctx,
2282 struct r600_pipe_shader *gs,
2283 struct pipe_stream_output_info *so)
2284 {
2285 struct r600_shader_ctx ctx = {};
2286 struct r600_shader *gs_shader = &gs->shader;
2287 struct r600_pipe_shader *cshader;
2288 unsigned ocnt = gs_shader->noutput;
2289 struct r600_bytecode_alu alu;
2290 struct r600_bytecode_vtx vtx;
2291 struct r600_bytecode_output output;
2292 struct r600_bytecode_cf *cf_jump, *cf_pop,
2293 *last_exp_pos = NULL, *last_exp_param = NULL;
2294 int next_clip_pos = 61, next_param = 0;
2295 unsigned i, j;
2296 int ring;
2297 bool only_ring_0 = true;
2298 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2299 if (!cshader)
2300 return 0;
2301
2302 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2303 sizeof(struct r600_shader_io));
2304
2305 cshader->shader.noutput = ocnt;
2306
2307 ctx.shader = &cshader->shader;
2308 ctx.bc = &ctx.shader->bc;
2309 ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
2310
2311 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2312 rctx->screen->has_compressed_msaa_texturing);
2313
2314 ctx.bc->isa = rctx->isa;
2315
2316 cf_jump = NULL;
2317 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2318
2319 /* R0.x = R0.x & 0x3fffffff */
2320 memset(&alu, 0, sizeof(alu));
2321 alu.op = ALU_OP2_AND_INT;
2322 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2323 alu.src[1].value = 0x3fffffff;
2324 alu.dst.write = 1;
2325 r600_bytecode_add_alu(ctx.bc, &alu);
2326
2327 /* R0.y = R0.x >> 30 */
2328 memset(&alu, 0, sizeof(alu));
2329 alu.op = ALU_OP2_LSHR_INT;
2330 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2331 alu.src[1].value = 0x1e;
2332 alu.dst.chan = 1;
2333 alu.dst.write = 1;
2334 alu.last = 1;
2335 r600_bytecode_add_alu(ctx.bc, &alu);
2336
2337 /* fetch vertex data from GSVS ring */
2338 for (i = 0; i < ocnt; ++i) {
2339 struct r600_shader_io *out = &ctx.shader->output[i];
2340
2341 out->gpr = i + 1;
2342 out->ring_offset = i * 16;
2343
2344 memset(&vtx, 0, sizeof(vtx));
2345 vtx.op = FETCH_OP_VFETCH;
2346 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2347 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2348 vtx.mega_fetch_count = 16;
2349 vtx.offset = out->ring_offset;
2350 vtx.dst_gpr = out->gpr;
2351 vtx.src_gpr = 0;
2352 vtx.dst_sel_x = 0;
2353 vtx.dst_sel_y = 1;
2354 vtx.dst_sel_z = 2;
2355 vtx.dst_sel_w = 3;
2356 if (rctx->b.chip_class >= EVERGREEN) {
2357 vtx.use_const_fields = 1;
2358 } else {
2359 vtx.data_format = FMT_32_32_32_32_FLOAT;
2360 }
2361
2362 r600_bytecode_add_vtx(ctx.bc, &vtx);
2363 }
2364 ctx.temp_reg = i + 1;
2365 for (ring = 3; ring >= 0; --ring) {
2366 bool enabled = false;
2367 for (i = 0; i < so->num_outputs; i++) {
2368 if (so->output[i].stream == ring) {
2369 enabled = true;
2370 if (ring > 0)
2371 only_ring_0 = false;
2372 break;
2373 }
2374 }
2375 if (ring != 0 && !enabled) {
2376 cshader->shader.ring_item_sizes[ring] = 0;
2377 continue;
2378 }
2379
2380 if (cf_jump) {
2381 // Patch up jump label
2382 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2383 cf_pop = ctx.bc->cf_last;
2384
2385 cf_jump->cf_addr = cf_pop->id + 2;
2386 cf_jump->pop_count = 1;
2387 cf_pop->cf_addr = cf_pop->id + 2;
2388 cf_pop->pop_count = 1;
2389 }
2390
2391 /* PRED_SETE_INT __, R0.y, ring */
2392 memset(&alu, 0, sizeof(alu));
2393 alu.op = ALU_OP2_PRED_SETE_INT;
2394 alu.src[0].chan = 1;
2395 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2396 alu.src[1].value = ring;
2397 alu.execute_mask = 1;
2398 alu.update_pred = 1;
2399 alu.last = 1;
2400 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2401
2402 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2403 cf_jump = ctx.bc->cf_last;
2404
2405 if (enabled)
2406 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2407 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2408 }
2409
2410 /* bc adds nops - copy it */
2411 if (ctx.bc->chip_class == R600) {
2412 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2413 alu.op = ALU_OP0_NOP;
2414 alu.last = 1;
2415 r600_bytecode_add_alu(ctx.bc, &alu);
2416
2417 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2418 }
2419
2420 /* export vertex data */
2421 /* XXX factor out common code with r600_shader_from_tgsi ? */
2422 for (i = 0; i < ocnt; ++i) {
2423 struct r600_shader_io *out = &ctx.shader->output[i];
2424 bool instream0 = true;
2425 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2426 continue;
2427
2428 for (j = 0; j < so->num_outputs; j++) {
2429 if (so->output[j].register_index == i) {
2430 if (so->output[j].stream == 0)
2431 break;
2432 if (so->output[j].stream > 0)
2433 instream0 = false;
2434 }
2435 }
2436 if (!instream0)
2437 continue;
2438 memset(&output, 0, sizeof(output));
2439 output.gpr = out->gpr;
2440 output.elem_size = 3;
2441 output.swizzle_x = 0;
2442 output.swizzle_y = 1;
2443 output.swizzle_z = 2;
2444 output.swizzle_w = 3;
2445 output.burst_count = 1;
2446 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2447 output.op = CF_OP_EXPORT;
2448 switch (out->name) {
2449 case TGSI_SEMANTIC_POSITION:
2450 output.array_base = 60;
2451 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2452 break;
2453
2454 case TGSI_SEMANTIC_PSIZE:
2455 output.array_base = 61;
2456 if (next_clip_pos == 61)
2457 next_clip_pos = 62;
2458 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2459 output.swizzle_y = 7;
2460 output.swizzle_z = 7;
2461 output.swizzle_w = 7;
2462 ctx.shader->vs_out_misc_write = 1;
2463 ctx.shader->vs_out_point_size = 1;
2464 break;
2465 case TGSI_SEMANTIC_LAYER:
2466 if (out->spi_sid) {
2467 /* duplicate it as PARAM to pass to the pixel shader */
2468 output.array_base = next_param++;
2469 r600_bytecode_add_output(ctx.bc, &output);
2470 last_exp_param = ctx.bc->cf_last;
2471 }
2472 output.array_base = 61;
2473 if (next_clip_pos == 61)
2474 next_clip_pos = 62;
2475 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2476 output.swizzle_x = 7;
2477 output.swizzle_y = 7;
2478 output.swizzle_z = 0;
2479 output.swizzle_w = 7;
2480 ctx.shader->vs_out_misc_write = 1;
2481 ctx.shader->vs_out_layer = 1;
2482 break;
2483 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2484 if (out->spi_sid) {
2485 /* duplicate it as PARAM to pass to the pixel shader */
2486 output.array_base = next_param++;
2487 r600_bytecode_add_output(ctx.bc, &output);
2488 last_exp_param = ctx.bc->cf_last;
2489 }
2490 output.array_base = 61;
2491 if (next_clip_pos == 61)
2492 next_clip_pos = 62;
2493 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2494 ctx.shader->vs_out_misc_write = 1;
2495 ctx.shader->vs_out_viewport = 1;
2496 output.swizzle_x = 7;
2497 output.swizzle_y = 7;
2498 output.swizzle_z = 7;
2499 output.swizzle_w = 0;
2500 break;
2501 case TGSI_SEMANTIC_CLIPDIST:
2502 /* spi_sid is 0 for clipdistance outputs that were generated
2503 * for clipvertex - we don't need to pass them to PS */
2504 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2505 ctx.shader->cull_dist_write = gs->shader.cull_dist_write;
2506 ctx.shader->cc_dist_mask = gs->shader.cc_dist_mask;
2507 if (out->spi_sid) {
2508 /* duplicate it as PARAM to pass to the pixel shader */
2509 output.array_base = next_param++;
2510 r600_bytecode_add_output(ctx.bc, &output);
2511 last_exp_param = ctx.bc->cf_last;
2512 }
2513 output.array_base = next_clip_pos++;
2514 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2515 break;
2516 case TGSI_SEMANTIC_FOG:
2517 output.swizzle_y = 4; /* 0 */
2518 output.swizzle_z = 4; /* 0 */
2519 output.swizzle_w = 5; /* 1 */
2520 break;
2521 default:
2522 output.array_base = next_param++;
2523 break;
2524 }
2525 r600_bytecode_add_output(ctx.bc, &output);
2526 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2527 last_exp_param = ctx.bc->cf_last;
2528 else
2529 last_exp_pos = ctx.bc->cf_last;
2530 }
2531
2532 if (!last_exp_pos) {
2533 memset(&output, 0, sizeof(output));
2534 output.gpr = 0;
2535 output.elem_size = 3;
2536 output.swizzle_x = 7;
2537 output.swizzle_y = 7;
2538 output.swizzle_z = 7;
2539 output.swizzle_w = 7;
2540 output.burst_count = 1;
2541 output.type = 2;
2542 output.op = CF_OP_EXPORT;
2543 output.array_base = 60;
2544 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2545 r600_bytecode_add_output(ctx.bc, &output);
2546 last_exp_pos = ctx.bc->cf_last;
2547 }
2548
2549 if (!last_exp_param) {
2550 memset(&output, 0, sizeof(output));
2551 output.gpr = 0;
2552 output.elem_size = 3;
2553 output.swizzle_x = 7;
2554 output.swizzle_y = 7;
2555 output.swizzle_z = 7;
2556 output.swizzle_w = 7;
2557 output.burst_count = 1;
2558 output.type = 2;
2559 output.op = CF_OP_EXPORT;
2560 output.array_base = next_param++;
2561 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2562 r600_bytecode_add_output(ctx.bc, &output);
2563 last_exp_param = ctx.bc->cf_last;
2564 }
2565
2566 last_exp_pos->op = CF_OP_EXPORT_DONE;
2567 last_exp_param->op = CF_OP_EXPORT_DONE;
2568
2569 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2570 cf_pop = ctx.bc->cf_last;
2571
2572 cf_jump->cf_addr = cf_pop->id + 2;
2573 cf_jump->pop_count = 1;
2574 cf_pop->cf_addr = cf_pop->id + 2;
2575 cf_pop->pop_count = 1;
2576
2577 if (ctx.bc->chip_class == CAYMAN)
2578 cm_bytecode_add_cf_end(ctx.bc);
2579 else {
2580 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2581 ctx.bc->cf_last->end_of_program = 1;
2582 }
2583
2584 gs->gs_copy_shader = cshader;
2585 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2586
2587 ctx.bc->nstack = 1;
2588
2589 return r600_bytecode_build(ctx.bc);
2590 }
2591
2592 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2593 {
2594 if (ind) {
2595 struct r600_bytecode_alu alu;
2596 int r;
2597
2598 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2599 alu.op = ALU_OP2_ADD_INT;
2600 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2601 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2602 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2603 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2604 alu.dst.write = 1;
2605 alu.last = 1;
2606 r = r600_bytecode_add_alu(ctx->bc, &alu);
2607 if (r)
2608 return r;
2609 }
2610 return 0;
2611 }
2612
2613 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so UNUSED, int stream, bool ind)
2614 {
2615 struct r600_bytecode_output output;
2616 int ring_offset;
2617 unsigned i, k;
2618 int effective_stream = stream == -1 ? 0 : stream;
2619 int idx = 0;
2620
2621 for (i = 0; i < ctx->shader->noutput; i++) {
2622 if (ctx->gs_for_vs) {
2623 /* for ES we need to lookup corresponding ring offset expected by GS
2624 * (map this output to GS input by name and sid) */
2625 /* FIXME precompute offsets */
2626 ring_offset = -1;
2627 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2628 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2629 struct r600_shader_io *out = &ctx->shader->output[i];
2630 if (in->name == out->name && in->sid == out->sid)
2631 ring_offset = in->ring_offset;
2632 }
2633
2634 if (ring_offset == -1)
2635 continue;
2636 } else {
2637 ring_offset = idx * 16;
2638 idx++;
2639 }
2640
2641 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2642 continue;
2643 /* next_ring_offset after parsing input decls contains total size of
2644 * single vertex data, gs_next_vertex - current vertex index */
2645 if (!ind)
2646 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2647
2648 memset(&output, 0, sizeof(struct r600_bytecode_output));
2649 output.gpr = ctx->shader->output[i].gpr;
2650 output.elem_size = 3;
2651 output.comp_mask = 0xF;
2652 output.burst_count = 1;
2653
2654 if (ind)
2655 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2656 else
2657 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2658
2659 switch (stream) {
2660 default:
2661 case 0:
2662 output.op = CF_OP_MEM_RING; break;
2663 case 1:
2664 output.op = CF_OP_MEM_RING1; break;
2665 case 2:
2666 output.op = CF_OP_MEM_RING2; break;
2667 case 3:
2668 output.op = CF_OP_MEM_RING3; break;
2669 }
2670
2671 if (ind) {
2672 output.array_base = ring_offset >> 2; /* in dwords */
2673 output.array_size = 0xfff;
2674 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2675 } else
2676 output.array_base = ring_offset >> 2; /* in dwords */
2677 r600_bytecode_add_output(ctx->bc, &output);
2678 }
2679
2680 ++ctx->gs_next_vertex;
2681 return 0;
2682 }
2683
2684
2685 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2686 {
2687 int r;
2688 struct r600_bytecode_vtx vtx;
2689 int temp_val = ctx->temp_reg;
2690 /* need to store the TCS output somewhere */
2691 r = single_alu_op2(ctx, ALU_OP1_MOV,
2692 temp_val, 0,
2693 V_SQ_ALU_SRC_LITERAL, 0,
2694 0, 0);
2695 if (r)
2696 return r;
2697
2698 /* used by VS/TCS */
2699 if (ctx->tess_input_info) {
2700 /* fetch tcs input values into resv space */
2701 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2702 vtx.op = FETCH_OP_VFETCH;
2703 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2704 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2705 vtx.mega_fetch_count = 16;
2706 vtx.data_format = FMT_32_32_32_32;
2707 vtx.num_format_all = 2;
2708 vtx.format_comp_all = 1;
2709 vtx.use_const_fields = 0;
2710 vtx.endian = r600_endian_swap(32);
2711 vtx.srf_mode_all = 1;
2712 vtx.offset = 0;
2713 vtx.dst_gpr = ctx->tess_input_info;
2714 vtx.dst_sel_x = 0;
2715 vtx.dst_sel_y = 1;
2716 vtx.dst_sel_z = 2;
2717 vtx.dst_sel_w = 3;
2718 vtx.src_gpr = temp_val;
2719 vtx.src_sel_x = 0;
2720
2721 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2722 if (r)
2723 return r;
2724 }
2725
2726 /* used by TCS/TES */
2727 if (ctx->tess_output_info) {
2728 /* fetch tcs output values into resv space */
2729 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2730 vtx.op = FETCH_OP_VFETCH;
2731 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2732 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2733 vtx.mega_fetch_count = 16;
2734 vtx.data_format = FMT_32_32_32_32;
2735 vtx.num_format_all = 2;
2736 vtx.format_comp_all = 1;
2737 vtx.use_const_fields = 0;
2738 vtx.endian = r600_endian_swap(32);
2739 vtx.srf_mode_all = 1;
2740 vtx.offset = 16;
2741 vtx.dst_gpr = ctx->tess_output_info;
2742 vtx.dst_sel_x = 0;
2743 vtx.dst_sel_y = 1;
2744 vtx.dst_sel_z = 2;
2745 vtx.dst_sel_w = 3;
2746 vtx.src_gpr = temp_val;
2747 vtx.src_sel_x = 0;
2748
2749 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2750 if (r)
2751 return r;
2752 }
2753 return 0;
2754 }
2755
2756 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2757 {
2758 int j, r;
2759 int temp_reg;
2760 unsigned i;
2761
2762 /* fetch tcs input values into input_vals */
2763 ctx->tess_input_info = r600_get_temp(ctx);
2764 ctx->tess_output_info = 0;
2765 r = r600_fetch_tess_io_info(ctx);
2766 if (r)
2767 return r;
2768
2769 temp_reg = r600_get_temp(ctx);
2770 /* dst reg contains LDS address stride * idx */
2771 /* MUL vertexID, vertex_dw_stride */
2772 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2773 temp_reg, 0,
2774 ctx->tess_input_info, 1,
2775 0, 1); /* rel id in r0.y? */
2776 if (r)
2777 return r;
2778
2779 for (i = 0; i < ctx->shader->noutput; i++) {
2780 struct r600_bytecode_alu alu;
2781 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2782
2783 if (param) {
2784 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2785 temp_reg, 1,
2786 temp_reg, 0,
2787 V_SQ_ALU_SRC_LITERAL, param * 16);
2788 if (r)
2789 return r;
2790 }
2791
2792 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2793 temp_reg, 2,
2794 temp_reg, param ? 1 : 0,
2795 V_SQ_ALU_SRC_LITERAL, 8);
2796 if (r)
2797 return r;
2798
2799
2800 for (j = 0; j < 2; j++) {
2801 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2802 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2803 alu.op = LDS_OP3_LDS_WRITE_REL;
2804 alu.src[0].sel = temp_reg;
2805 alu.src[0].chan = chan;
2806 alu.src[1].sel = ctx->shader->output[i].gpr;
2807 alu.src[1].chan = j * 2;
2808 alu.src[2].sel = ctx->shader->output[i].gpr;
2809 alu.src[2].chan = (j * 2) + 1;
2810 alu.last = 1;
2811 alu.dst.chan = 0;
2812 alu.lds_idx = 1;
2813 alu.is_lds_idx_op = true;
2814 r = r600_bytecode_add_alu(ctx->bc, &alu);
2815 if (r)
2816 return r;
2817 }
2818 }
2819 return 0;
2820 }
2821
2822 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
2823 {
2824 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2825 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
2826 int i, r, lasti;
2827 int temp_reg = r600_get_temp(ctx);
2828 struct r600_bytecode_alu alu;
2829 unsigned write_mask = dst->Register.WriteMask;
2830
2831 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
2832 return 0;
2833
2834 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
2835 if (r)
2836 return r;
2837
2838 /* the base address is now in temp.x */
2839 r = r600_get_byte_address(ctx, temp_reg,
2840 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
2841 if (r)
2842 return r;
2843
2844 /* LDS write */
2845 lasti = tgsi_last_instruction(write_mask);
2846 for (i = 1; i <= lasti; i++) {
2847
2848 if (!(write_mask & (1 << i)))
2849 continue;
2850 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2851 temp_reg, i,
2852 temp_reg, 0,
2853 V_SQ_ALU_SRC_LITERAL, 4 * i);
2854 if (r)
2855 return r;
2856 }
2857
2858 for (i = 0; i <= lasti; i++) {
2859 if (!(write_mask & (1 << i)))
2860 continue;
2861
2862 if ((i == 0 && ((write_mask & 3) == 3)) ||
2863 (i == 2 && ((write_mask & 0xc) == 0xc))) {
2864 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2865 alu.op = LDS_OP3_LDS_WRITE_REL;
2866 alu.src[0].sel = temp_reg;
2867 alu.src[0].chan = i;
2868
2869 alu.src[1].sel = dst->Register.Index;
2870 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2871 alu.src[1].chan = i;
2872
2873 alu.src[2].sel = dst->Register.Index;
2874 alu.src[2].sel += ctx->file_offset[dst->Register.File];
2875 alu.src[2].chan = i + 1;
2876 alu.lds_idx = 1;
2877 alu.dst.chan = 0;
2878 alu.last = 1;
2879 alu.is_lds_idx_op = true;
2880 r = r600_bytecode_add_alu(ctx->bc, &alu);
2881 if (r)
2882 return r;
2883 i += 1;
2884 continue;
2885 }
2886 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2887 alu.op = LDS_OP2_LDS_WRITE;
2888 alu.src[0].sel = temp_reg;
2889 alu.src[0].chan = i;
2890
2891 alu.src[1].sel = dst->Register.Index;
2892 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2893 alu.src[1].chan = i;
2894
2895 alu.src[2].sel = V_SQ_ALU_SRC_0;
2896 alu.dst.chan = 0;
2897 alu.last = 1;
2898 alu.is_lds_idx_op = true;
2899 r = r600_bytecode_add_alu(ctx->bc, &alu);
2900 if (r)
2901 return r;
2902 }
2903 return 0;
2904 }
2905
2906 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
2907 int output_idx, int nc)
2908 {
2909 int param;
2910 unsigned temp_reg = r600_get_temp(ctx);
2911 unsigned name = ctx->shader->output[output_idx].name;
2912 int dreg = ctx->shader->output[output_idx].gpr;
2913 int r;
2914
2915 param = r600_get_lds_unique_index(name, 0);
2916 r = get_lds_offset0(ctx, 1, temp_reg, true);
2917 if (r)
2918 return r;
2919
2920 if (param) {
2921 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2922 temp_reg, 0,
2923 temp_reg, 0,
2924 V_SQ_ALU_SRC_LITERAL, param * 16);
2925 if (r)
2926 return r;
2927 }
2928
2929 do_lds_fetch_values(ctx, temp_reg, dreg, ((1u << nc) - 1));
2930 return 0;
2931 }
2932
2933 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
2934 {
2935 int stride, outer_comps, inner_comps;
2936 int tessinner_idx = -1, tessouter_idx = -1;
2937 int i, r;
2938 unsigned j;
2939 int temp_reg = r600_get_temp(ctx);
2940 int treg[3] = {-1, -1, -1};
2941 struct r600_bytecode_alu alu;
2942 struct r600_bytecode_cf *cf_jump, *cf_pop;
2943
2944 /* only execute factor emission for invocation 0 */
2945 /* PRED_SETE_INT __, R0.x, 0 */
2946 memset(&alu, 0, sizeof(alu));
2947 alu.op = ALU_OP2_PRED_SETE_INT;
2948 alu.src[0].chan = 2;
2949 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2950 alu.execute_mask = 1;
2951 alu.update_pred = 1;
2952 alu.last = 1;
2953 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2954
2955 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
2956 cf_jump = ctx->bc->cf_last;
2957
2958 treg[0] = r600_get_temp(ctx);
2959 switch (ctx->shader->tcs_prim_mode) {
2960 case PIPE_PRIM_LINES:
2961 stride = 8; /* 2 dwords, 1 vec2 store */
2962 outer_comps = 2;
2963 inner_comps = 0;
2964 break;
2965 case PIPE_PRIM_TRIANGLES:
2966 stride = 16; /* 4 dwords, 1 vec4 store */
2967 outer_comps = 3;
2968 inner_comps = 1;
2969 treg[1] = r600_get_temp(ctx);
2970 break;
2971 case PIPE_PRIM_QUADS:
2972 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2973 outer_comps = 4;
2974 inner_comps = 2;
2975 treg[1] = r600_get_temp(ctx);
2976 treg[2] = r600_get_temp(ctx);
2977 break;
2978 default:
2979 assert(0);
2980 return -1;
2981 }
2982
2983 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2984 /* TF_WRITE takes index in R.x, value in R.y */
2985 for (j = 0; j < ctx->shader->noutput; j++) {
2986 if (ctx->shader->output[j].name == TGSI_SEMANTIC_TESSINNER)
2987 tessinner_idx = j;
2988 if (ctx->shader->output[j].name == TGSI_SEMANTIC_TESSOUTER)
2989 tessouter_idx = j;
2990 }
2991
2992 if (tessouter_idx == -1)
2993 return -1;
2994
2995 if (tessinner_idx == -1 && inner_comps)
2996 return -1;
2997
2998 if (tessouter_idx != -1) {
2999 r = r600_tess_factor_read(ctx, tessouter_idx, outer_comps);
3000 if (r)
3001 return r;
3002 }
3003
3004 if (tessinner_idx != -1) {
3005 r = r600_tess_factor_read(ctx, tessinner_idx, inner_comps);
3006 if (r)
3007 return r;
3008 }
3009
3010 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
3011 /* r.x = relpatchid(r0.y) * tf_stride */
3012
3013 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
3014 /* add incoming r0.w to it: t.x = t.x + r0.w */
3015 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
3016 temp_reg, 0,
3017 0, 1,
3018 V_SQ_ALU_SRC_LITERAL, stride,
3019 0, 3);
3020 if (r)
3021 return r;
3022
3023 for (i = 0; i < outer_comps + inner_comps; i++) {
3024 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
3025 int out_comp = i >= outer_comps ? i - outer_comps : i;
3026
3027 if (ctx->shader->tcs_prim_mode == PIPE_PRIM_LINES) {
3028 if (out_comp == 1)
3029 out_comp = 0;
3030 else if (out_comp == 0)
3031 out_comp = 1;
3032 }
3033
3034 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
3035 treg[i / 2], (2 * (i % 2)),
3036 temp_reg, 0,
3037 V_SQ_ALU_SRC_LITERAL, 4 * i);
3038 if (r)
3039 return r;
3040 r = single_alu_op2(ctx, ALU_OP1_MOV,
3041 treg[i / 2], 1 + (2 * (i%2)),
3042 ctx->shader->output[out_idx].gpr, out_comp,
3043 0, 0);
3044 if (r)
3045 return r;
3046 }
3047 for (i = 0; i < outer_comps + inner_comps; i++) {
3048 struct r600_bytecode_gds gds;
3049
3050 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
3051 gds.src_gpr = treg[i / 2];
3052 gds.src_sel_x = 2 * (i % 2);
3053 gds.src_sel_y = 1 + (2 * (i % 2));
3054 gds.src_sel_z = 4;
3055 gds.dst_sel_x = 7;
3056 gds.dst_sel_y = 7;
3057 gds.dst_sel_z = 7;
3058 gds.dst_sel_w = 7;
3059 gds.op = FETCH_OP_TF_WRITE;
3060 r = r600_bytecode_add_gds(ctx->bc, &gds);
3061 if (r)
3062 return r;
3063 }
3064
3065 // Patch up jump label
3066 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
3067 cf_pop = ctx->bc->cf_last;
3068
3069 cf_jump->cf_addr = cf_pop->id + 2;
3070 cf_jump->pop_count = 1;
3071 cf_pop->cf_addr = cf_pop->id + 2;
3072 cf_pop->pop_count = 1;
3073
3074 return 0;
3075 }
3076
3077 /*
3078 * We have to work out the thread ID for load and atomic
3079 * operations, which store the returned value to an index
3080 * in an intermediate buffer.
3081 * The index is calculated by taking the thread id,
3082 * calculated from the MBCNT instructions.
3083 * Then the shader engine ID is multiplied by 256,
3084 * and the wave id is added.
3085 * Then the result is multipled by 64 and thread id is
3086 * added.
3087 */
3088 static int load_thread_id_gpr(struct r600_shader_ctx *ctx)
3089 {
3090 struct r600_bytecode_alu alu;
3091 int r;
3092
3093 if (ctx->thread_id_gpr_loaded)
3094 return 0;
3095
3096 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3097 alu.op = ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT;
3098 alu.dst.sel = ctx->temp_reg;
3099 alu.dst.chan = 0;
3100 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3101 alu.src[0].value = 0xffffffff;
3102 alu.dst.write = 1;
3103 r = r600_bytecode_add_alu(ctx->bc, &alu);
3104 if (r)
3105 return r;
3106
3107 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3108 alu.op = ALU_OP1_MBCNT_32HI_INT;
3109 alu.dst.sel = ctx->temp_reg;
3110 alu.dst.chan = 1;
3111 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3112 alu.src[0].value = 0xffffffff;
3113 alu.dst.write = 1;
3114 r = r600_bytecode_add_alu(ctx->bc, &alu);
3115 if (r)
3116 return r;
3117
3118 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3119 alu.op = ALU_OP3_MULADD_UINT24;
3120 alu.dst.sel = ctx->temp_reg;
3121 alu.dst.chan = 2;
3122 alu.src[0].sel = EG_V_SQ_ALU_SRC_SE_ID;
3123 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3124 alu.src[1].value = 256;
3125 alu.src[2].sel = EG_V_SQ_ALU_SRC_HW_WAVE_ID;
3126 alu.dst.write = 1;
3127 alu.is_op3 = 1;
3128 alu.last = 1;
3129 r = r600_bytecode_add_alu(ctx->bc, &alu);
3130 if (r)
3131 return r;
3132
3133 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
3134 ctx->thread_id_gpr, 1,
3135 ctx->temp_reg, 2,
3136 V_SQ_ALU_SRC_LITERAL, 0x40,
3137 ctx->temp_reg, 0);
3138 if (r)
3139 return r;
3140 ctx->thread_id_gpr_loaded = true;
3141 return 0;
3142 }
3143
3144 static int r600_shader_from_tgsi(struct r600_context *rctx,
3145 struct r600_pipe_shader *pipeshader,
3146 union r600_shader_key key)
3147 {
3148 struct r600_screen *rscreen = rctx->screen;
3149 struct r600_shader *shader = &pipeshader->shader;
3150 struct tgsi_token *tokens = pipeshader->selector->tokens;
3151 struct pipe_stream_output_info so = pipeshader->selector->so;
3152 struct tgsi_full_immediate *immediate;
3153 struct r600_shader_ctx ctx;
3154 struct r600_bytecode_output output[ARRAY_SIZE(shader->output)];
3155 unsigned output_done, noutput;
3156 unsigned opcode;
3157 int j, k, r = 0;
3158 unsigned i;
3159 int next_param_base = 0, next_clip_base;
3160 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
3161 bool indirect_gprs;
3162 bool ring_outputs = false;
3163 bool lds_outputs = false;
3164 bool lds_inputs = false;
3165 bool pos_emitted = false;
3166
3167 ctx.bc = &shader->bc;
3168 ctx.shader = shader;
3169
3170 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
3171 rscreen->has_compressed_msaa_texturing);
3172 ctx.tokens = tokens;
3173 tgsi_scan_shader(tokens, &ctx.info);
3174 shader->indirect_files = ctx.info.indirect_files;
3175
3176 shader->uses_helper_invocation = false;
3177 shader->uses_doubles = ctx.info.uses_doubles;
3178 shader->uses_atomics = ctx.info.file_mask[TGSI_FILE_HW_ATOMIC];
3179 shader->nsys_inputs = 0;
3180
3181 shader->uses_images = ctx.info.file_count[TGSI_FILE_IMAGE] > 0 ||
3182 ctx.info.file_count[TGSI_FILE_BUFFER] > 0;
3183 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
3184 tgsi_parse_init(&ctx.parse, tokens);
3185 ctx.type = ctx.info.processor;
3186 shader->processor_type = ctx.type;
3187 ctx.bc->type = shader->processor_type;
3188
3189 switch (ctx.type) {
3190 case PIPE_SHADER_VERTEX:
3191 shader->vs_as_gs_a = key.vs.as_gs_a;
3192 shader->vs_as_es = key.vs.as_es;
3193 shader->vs_as_ls = key.vs.as_ls;
3194 shader->atomic_base = key.vs.first_atomic_counter;
3195 if (shader->vs_as_es)
3196 ring_outputs = true;
3197 if (shader->vs_as_ls)
3198 lds_outputs = true;
3199 break;
3200 case PIPE_SHADER_GEOMETRY:
3201 ring_outputs = true;
3202 shader->atomic_base = key.gs.first_atomic_counter;
3203 shader->gs_tri_strip_adj_fix = key.gs.tri_strip_adj_fix;
3204 break;
3205 case PIPE_SHADER_TESS_CTRL:
3206 shader->tcs_prim_mode = key.tcs.prim_mode;
3207 shader->atomic_base = key.tcs.first_atomic_counter;
3208 lds_outputs = true;
3209 lds_inputs = true;
3210 break;
3211 case PIPE_SHADER_TESS_EVAL:
3212 shader->tes_as_es = key.tes.as_es;
3213 shader->atomic_base = key.tes.first_atomic_counter;
3214 lds_inputs = true;
3215 if (shader->tes_as_es)
3216 ring_outputs = true;
3217 break;
3218 case PIPE_SHADER_FRAGMENT:
3219 shader->two_side = key.ps.color_two_side;
3220 shader->atomic_base = key.ps.first_atomic_counter;
3221 shader->rat_base = key.ps.nr_cbufs;
3222 shader->image_size_const_offset = key.ps.image_size_const_offset;
3223 break;
3224 case PIPE_SHADER_COMPUTE:
3225 shader->rat_base = 0;
3226 shader->image_size_const_offset = ctx.info.file_count[TGSI_FILE_SAMPLER];
3227 break;
3228 default:
3229 break;
3230 }
3231
3232 if (shader->vs_as_es || shader->tes_as_es) {
3233 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
3234 } else {
3235 ctx.gs_for_vs = NULL;
3236 }
3237
3238 ctx.next_ring_offset = 0;
3239 ctx.gs_out_ring_offset = 0;
3240 ctx.gs_next_vertex = 0;
3241 ctx.gs_stream_output_info = &so;
3242
3243 ctx.face_gpr = -1;
3244 ctx.fixed_pt_position_gpr = -1;
3245 ctx.fragcoord_input = -1;
3246 ctx.colors_used = 0;
3247 ctx.clip_vertex_write = 0;
3248 ctx.thread_id_gpr_loaded = false;
3249
3250 ctx.helper_invoc_reg = -1;
3251 ctx.cs_block_size_reg = -1;
3252 ctx.cs_grid_size_reg = -1;
3253 ctx.cs_block_size_loaded = false;
3254 ctx.cs_grid_size_loaded = false;
3255
3256 shader->nr_ps_color_exports = 0;
3257 shader->nr_ps_max_color_exports = 0;
3258
3259
3260 /* register allocations */
3261 /* Values [0,127] correspond to GPR[0..127].
3262 * Values [128,159] correspond to constant buffer bank 0
3263 * Values [160,191] correspond to constant buffer bank 1
3264 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3265 * Values [256,287] correspond to constant buffer bank 2 (EG)
3266 * Values [288,319] correspond to constant buffer bank 3 (EG)
3267 * Other special values are shown in the list below.
3268 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3269 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3270 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3271 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3272 * 248 SQ_ALU_SRC_0: special constant 0.0.
3273 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3274 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3275 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3276 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3277 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3278 * 254 SQ_ALU_SRC_PV: previous vector result.
3279 * 255 SQ_ALU_SRC_PS: previous scalar result.
3280 */
3281 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3282 ctx.file_offset[i] = 0;
3283 }
3284
3285 if (ctx.type == PIPE_SHADER_VERTEX) {
3286
3287 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3288 if (ctx.info.num_inputs)
3289 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3290 }
3291 if (ctx.type == PIPE_SHADER_FRAGMENT) {
3292 if (ctx.bc->chip_class >= EVERGREEN)
3293 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3294 else
3295 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3296
3297 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3298 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_HELPER_INVOCATION) {
3299 ctx.helper_invoc_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3300 shader->uses_helper_invocation = true;
3301 }
3302 }
3303 }
3304 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3305 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3306 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3307 }
3308 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3309 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3310 if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3311 bool add_tesscoord = false, add_tess_inout = false;
3312 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3313 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3314 /* if we have tesscoord save one reg */
3315 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3316 add_tesscoord = true;
3317 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3318 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3319 add_tess_inout = true;
3320 }
3321 if (add_tesscoord || add_tess_inout)
3322 ctx.file_offset[TGSI_FILE_INPUT]++;
3323 if (add_tess_inout)
3324 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3325 }
3326 if (ctx.type == PIPE_SHADER_COMPUTE) {
3327 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3328 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3329 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_GRID_SIZE)
3330 ctx.cs_grid_size_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3331 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_BLOCK_SIZE)
3332 ctx.cs_block_size_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3333 }
3334 }
3335
3336 ctx.file_offset[TGSI_FILE_OUTPUT] =
3337 ctx.file_offset[TGSI_FILE_INPUT] +
3338 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3339 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3340 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3341
3342 /* Outside the GPR range. This will be translated to one of the
3343 * kcache banks later. */
3344 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3345
3346 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3347 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3348 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
3349 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
3350 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
3351
3352 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3353 ctx.tess_input_info = ctx.bc->ar_reg + 3;
3354 ctx.tess_output_info = ctx.bc->ar_reg + 4;
3355 ctx.temp_reg = ctx.bc->ar_reg + 5;
3356 } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3357 ctx.tess_input_info = 0;
3358 ctx.tess_output_info = ctx.bc->ar_reg + 3;
3359 ctx.temp_reg = ctx.bc->ar_reg + 4;
3360 } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
3361 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
3362 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
3363 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
3364 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
3365 ctx.temp_reg = ctx.bc->ar_reg + 7;
3366 if (ctx.shader->gs_tri_strip_adj_fix) {
3367 ctx.gs_rotated_input[0] = ctx.bc->ar_reg + 7;
3368 ctx.gs_rotated_input[1] = ctx.bc->ar_reg + 8;
3369 ctx.temp_reg += 2;
3370 } else {
3371 ctx.gs_rotated_input[0] = 0;
3372 ctx.gs_rotated_input[1] = 1;
3373 }
3374 } else {
3375 ctx.temp_reg = ctx.bc->ar_reg + 3;
3376 }
3377
3378 if (shader->uses_images) {
3379 ctx.thread_id_gpr = ctx.temp_reg++;
3380 ctx.thread_id_gpr_loaded = false;
3381 }
3382
3383 shader->max_arrays = 0;
3384 shader->num_arrays = 0;
3385 if (indirect_gprs) {
3386
3387 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3388 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3389 ctx.file_offset[TGSI_FILE_OUTPUT] -
3390 ctx.file_offset[TGSI_FILE_INPUT],
3391 0x0F);
3392 }
3393 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3394 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3395 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3396 ctx.file_offset[TGSI_FILE_OUTPUT],
3397 0x0F);
3398 }
3399 }
3400
3401 ctx.nliterals = 0;
3402 ctx.literals = NULL;
3403 ctx.max_driver_temp_used = 0;
3404
3405 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3406 ctx.info.colors_written == 1;
3407 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3408 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3409
3410 if (ctx.type == PIPE_SHADER_VERTEX ||
3411 ctx.type == PIPE_SHADER_GEOMETRY ||
3412 ctx.type == PIPE_SHADER_TESS_EVAL) {
3413 shader->cc_dist_mask = (1 << (ctx.info.properties[TGSI_PROPERTY_NUM_CULLDIST_ENABLED] +
3414 ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED])) - 1;
3415 shader->clip_dist_write = (1 << ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED]) - 1;
3416 shader->cull_dist_write = ((1 << ctx.info.properties[TGSI_PROPERTY_NUM_CULLDIST_ENABLED]) - 1) << ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED];
3417 }
3418
3419 if (shader->vs_as_gs_a)
3420 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3421
3422 if (ctx.type == PIPE_SHADER_TESS_EVAL)
3423 r600_fetch_tess_io_info(&ctx);
3424
3425 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3426 tgsi_parse_token(&ctx.parse);
3427 switch (ctx.parse.FullToken.Token.Type) {
3428 case TGSI_TOKEN_TYPE_IMMEDIATE:
3429 immediate = &ctx.parse.FullToken.FullImmediate;
3430 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3431 if(ctx.literals == NULL) {
3432 r = -ENOMEM;
3433 goto out_err;
3434 }
3435 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3436 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3437 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3438 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3439 ctx.nliterals++;
3440 break;
3441 case TGSI_TOKEN_TYPE_DECLARATION:
3442 r = tgsi_declaration(&ctx);
3443 if (r)
3444 goto out_err;
3445 break;
3446 case TGSI_TOKEN_TYPE_INSTRUCTION:
3447 case TGSI_TOKEN_TYPE_PROPERTY:
3448 break;
3449 default:
3450 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3451 r = -EINVAL;
3452 goto out_err;
3453 }
3454 }
3455
3456 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3457 shader->ring_item_sizes[1] = 0;
3458 shader->ring_item_sizes[2] = 0;
3459 shader->ring_item_sizes[3] = 0;
3460
3461 /* Process two side if needed */
3462 if (shader->two_side && ctx.colors_used) {
3463 int i, count = ctx.shader->ninput;
3464 unsigned next_lds_loc = ctx.shader->nlds;
3465
3466 /* additional inputs will be allocated right after the existing inputs,
3467 * we won't need them after the color selection, so we don't need to
3468 * reserve these gprs for the rest of the shader code and to adjust
3469 * output offsets etc. */
3470 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3471 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3472
3473 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3474 if (ctx.face_gpr == -1) {
3475 i = ctx.shader->ninput++;
3476 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3477 ctx.shader->input[i].spi_sid = 0;
3478 ctx.shader->input[i].gpr = gpr++;
3479 ctx.face_gpr = ctx.shader->input[i].gpr;
3480 }
3481
3482 for (i = 0; i < count; i++) {
3483 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3484 int ni = ctx.shader->ninput++;
3485 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3486 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3487 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3488 ctx.shader->input[ni].gpr = gpr++;
3489 // TGSI to LLVM needs to know the lds position of inputs.
3490 // Non LLVM path computes it later (in process_twoside_color)
3491 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3492 ctx.shader->input[i].back_color_input = ni;
3493 if (ctx.bc->chip_class >= EVERGREEN) {
3494 if ((r = evergreen_interp_input(&ctx, ni)))
3495 return r;
3496 }
3497 }
3498 }
3499 }
3500
3501 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3502 shader->nr_ps_max_color_exports = 8;
3503
3504 if (ctx.shader->uses_helper_invocation) {
3505 if (ctx.bc->chip_class == CAYMAN)
3506 r = cm_load_helper_invocation(&ctx);
3507 else
3508 r = eg_load_helper_invocation(&ctx);
3509 if (r)
3510 return r;
3511 }
3512
3513 /*
3514 * XXX this relies on fixed_pt_position_gpr only being present when
3515 * this shader should be executed per sample. Should be the case for now...
3516 */
3517 if (ctx.fixed_pt_position_gpr != -1 && ctx.info.reads_samplemask) {
3518 /*
3519 * Fix up sample mask. The hw always gives us coverage mask for
3520 * the pixel. However, for per-sample shading, we need the
3521 * coverage for the shader invocation only.
3522 * Also, with disabled msaa, only the first bit should be set
3523 * (luckily the same fixup works for both problems).
3524 * For now, we can only do it if we know this shader is always
3525 * executed per sample (due to usage of bits in the shader
3526 * forcing per-sample execution).
3527 * If the fb is not multisampled, we'd do unnecessary work but
3528 * it should still be correct.
3529 * It will however do nothing for sample shading according
3530 * to MinSampleShading.
3531 */
3532 struct r600_bytecode_alu alu;
3533 int tmp = r600_get_temp(&ctx);
3534 assert(ctx.face_gpr != -1);
3535 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3536
3537 alu.op = ALU_OP2_LSHL_INT;
3538 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3539 alu.src[0].value = 0x1;
3540 alu.src[1].sel = ctx.fixed_pt_position_gpr;
3541 alu.src[1].chan = 3;
3542 alu.dst.sel = tmp;
3543 alu.dst.chan = 0;
3544 alu.dst.write = 1;
3545 alu.last = 1;
3546 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3547 return r;
3548
3549 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3550 alu.op = ALU_OP2_AND_INT;
3551 alu.src[0].sel = tmp;
3552 alu.src[1].sel = ctx.face_gpr;
3553 alu.src[1].chan = 2;
3554 alu.dst.sel = ctx.face_gpr;
3555 alu.dst.chan = 2;
3556 alu.dst.write = 1;
3557 alu.last = 1;
3558 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3559 return r;
3560 }
3561
3562 if (ctx.fragcoord_input >= 0) {
3563 if (ctx.bc->chip_class == CAYMAN) {
3564 for (j = 0 ; j < 4; j++) {
3565 struct r600_bytecode_alu alu;
3566 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3567 alu.op = ALU_OP1_RECIP_IEEE;
3568 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3569 alu.src[0].chan = 3;
3570
3571 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3572 alu.dst.chan = j;
3573 alu.dst.write = (j == 3);
3574 alu.last = 1;
3575 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3576 return r;
3577 }
3578 } else {
3579 struct r600_bytecode_alu alu;
3580 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3581 alu.op = ALU_OP1_RECIP_IEEE;
3582 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3583 alu.src[0].chan = 3;
3584
3585 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3586 alu.dst.chan = 3;
3587 alu.dst.write = 1;
3588 alu.last = 1;
3589 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3590 return r;
3591 }
3592 }
3593
3594 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3595 struct r600_bytecode_alu alu;
3596 int r;
3597
3598 /* GS thread with no output workaround - emit a cut at start of GS */
3599 if (ctx.bc->chip_class == R600)
3600 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3601
3602 for (j = 0; j < 4; j++) {
3603 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3604 alu.op = ALU_OP1_MOV;
3605 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3606 alu.src[0].value = 0;
3607 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3608 alu.dst.write = 1;
3609 alu.last = 1;
3610 r = r600_bytecode_add_alu(ctx.bc, &alu);
3611 if (r)
3612 return r;
3613 }
3614
3615 if (ctx.shader->gs_tri_strip_adj_fix) {
3616 r = single_alu_op2(&ctx, ALU_OP2_AND_INT,
3617 ctx.gs_rotated_input[0], 2,
3618 0, 2,
3619 V_SQ_ALU_SRC_LITERAL, 1);
3620 if (r)
3621 return r;
3622
3623 for (i = 0; i < 6; i++) {
3624 int rotated = (i + 4) % 6;
3625 int offset_reg = i / 3;
3626 int offset_chan = i % 3;
3627 int rotated_offset_reg = rotated / 3;
3628 int rotated_offset_chan = rotated % 3;
3629
3630 if (offset_reg == 0 && offset_chan == 2)
3631 offset_chan = 3;
3632 if (rotated_offset_reg == 0 && rotated_offset_chan == 2)
3633 rotated_offset_chan = 3;
3634
3635 r = single_alu_op3(&ctx, ALU_OP3_CNDE_INT,
3636 ctx.gs_rotated_input[offset_reg], offset_chan,
3637 ctx.gs_rotated_input[0], 2,
3638 offset_reg, offset_chan,
3639 rotated_offset_reg, rotated_offset_chan);
3640 if (r)
3641 return r;
3642 }
3643 }
3644 }
3645
3646 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3647 r600_fetch_tess_io_info(&ctx);
3648
3649 if (shader->two_side && ctx.colors_used) {
3650 if ((r = process_twoside_color_inputs(&ctx)))
3651 return r;
3652 }
3653
3654 tgsi_parse_init(&ctx.parse, tokens);
3655 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3656 tgsi_parse_token(&ctx.parse);
3657 switch (ctx.parse.FullToken.Token.Type) {
3658 case TGSI_TOKEN_TYPE_INSTRUCTION:
3659 r = tgsi_is_supported(&ctx);
3660 if (r)
3661 goto out_err;
3662 ctx.max_driver_temp_used = 0;
3663 /* reserve first tmp for everyone */
3664 r600_get_temp(&ctx);
3665
3666 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3667 if ((r = tgsi_split_constant(&ctx)))
3668 goto out_err;
3669 if ((r = tgsi_split_literal_constant(&ctx)))
3670 goto out_err;
3671 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3672 if ((r = tgsi_split_gs_inputs(&ctx)))
3673 goto out_err;
3674 } else if (lds_inputs) {
3675 if ((r = tgsi_split_lds_inputs(&ctx)))
3676 goto out_err;
3677 }
3678 if (ctx.bc->chip_class == CAYMAN)
3679 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3680 else if (ctx.bc->chip_class >= EVERGREEN)
3681 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3682 else
3683 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3684 r = ctx.inst_info->process(&ctx);
3685 if (r)
3686 goto out_err;
3687
3688 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3689 r = r600_store_tcs_output(&ctx);
3690 if (r)
3691 goto out_err;
3692 }
3693 break;
3694 default:
3695 break;
3696 }
3697 }
3698
3699 /* Reset the temporary register counter. */
3700 ctx.max_driver_temp_used = 0;
3701
3702 noutput = shader->noutput;
3703
3704 if (!ring_outputs && ctx.clip_vertex_write) {
3705 unsigned clipdist_temp[2];
3706
3707 clipdist_temp[0] = r600_get_temp(&ctx);
3708 clipdist_temp[1] = r600_get_temp(&ctx);
3709
3710 /* need to convert a clipvertex write into clipdistance writes and not export
3711 the clip vertex anymore */
3712
3713 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3714 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3715 shader->output[noutput].gpr = clipdist_temp[0];
3716 noutput++;
3717 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3718 shader->output[noutput].gpr = clipdist_temp[1];
3719 noutput++;
3720
3721 /* reset spi_sid for clipvertex output to avoid confusing spi */
3722 shader->output[ctx.cv_output].spi_sid = 0;
3723
3724 shader->clip_dist_write = 0xFF;
3725 shader->cc_dist_mask = 0xFF;
3726
3727 for (i = 0; i < 8; i++) {
3728 int oreg = i >> 2;
3729 int ochan = i & 3;
3730
3731 for (j = 0; j < 4; j++) {
3732 struct r600_bytecode_alu alu;
3733 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3734 alu.op = ALU_OP2_DOT4;
3735 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3736 alu.src[0].chan = j;
3737
3738 alu.src[1].sel = 512 + i;
3739 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3740 alu.src[1].chan = j;
3741
3742 alu.dst.sel = clipdist_temp[oreg];
3743 alu.dst.chan = j;
3744 alu.dst.write = (j == ochan);
3745 if (j == 3)
3746 alu.last = 1;
3747 r = r600_bytecode_add_alu(ctx.bc, &alu);
3748 if (r)
3749 return r;
3750 }
3751 }
3752 }
3753
3754 /* Add stream outputs. */
3755 if (so.num_outputs) {
3756 bool emit = false;
3757 if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
3758 emit = true;
3759 if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
3760 emit = true;
3761 if (emit)
3762 emit_streamout(&ctx, &so, -1, NULL);
3763 }
3764 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3765 convert_edgeflag_to_int(&ctx);
3766
3767 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3768 r600_emit_tess_factor(&ctx);
3769
3770 if (lds_outputs) {
3771 if (ctx.type == PIPE_SHADER_VERTEX) {
3772 if (ctx.shader->noutput)
3773 emit_lds_vs_writes(&ctx);
3774 }
3775 } else if (ring_outputs) {
3776 if (shader->vs_as_es || shader->tes_as_es) {
3777 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3778 ctx.gs_export_gpr_tregs[1] = -1;
3779 ctx.gs_export_gpr_tregs[2] = -1;
3780 ctx.gs_export_gpr_tregs[3] = -1;
3781
3782 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3783 }
3784 } else {
3785 /* Export output */
3786 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3787
3788 for (i = 0, j = 0; i < noutput; i++, j++) {
3789 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3790 output[j].gpr = shader->output[i].gpr;
3791 output[j].elem_size = 3;
3792 output[j].swizzle_x = 0;
3793 output[j].swizzle_y = 1;
3794 output[j].swizzle_z = 2;
3795 output[j].swizzle_w = 3;
3796 output[j].burst_count = 1;
3797 output[j].type = 0xffffffff;
3798 output[j].op = CF_OP_EXPORT;
3799 switch (ctx.type) {
3800 case PIPE_SHADER_VERTEX:
3801 case PIPE_SHADER_TESS_EVAL:
3802 switch (shader->output[i].name) {
3803 case TGSI_SEMANTIC_POSITION:
3804 output[j].array_base = 60;
3805 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3806 pos_emitted = true;
3807 break;
3808
3809 case TGSI_SEMANTIC_PSIZE:
3810 output[j].array_base = 61;
3811 output[j].swizzle_y = 7;
3812 output[j].swizzle_z = 7;
3813 output[j].swizzle_w = 7;
3814 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3815 pos_emitted = true;
3816 break;
3817 case TGSI_SEMANTIC_EDGEFLAG:
3818 output[j].array_base = 61;
3819 output[j].swizzle_x = 7;
3820 output[j].swizzle_y = 0;
3821 output[j].swizzle_z = 7;
3822 output[j].swizzle_w = 7;
3823 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3824 pos_emitted = true;
3825 break;
3826 case TGSI_SEMANTIC_LAYER:
3827 /* spi_sid is 0 for outputs that are
3828 * not consumed by PS */
3829 if (shader->output[i].spi_sid) {
3830 output[j].array_base = next_param_base++;
3831 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3832 j++;
3833 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3834 }
3835 output[j].array_base = 61;
3836 output[j].swizzle_x = 7;
3837 output[j].swizzle_y = 7;
3838 output[j].swizzle_z = 0;
3839 output[j].swizzle_w = 7;
3840 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3841 pos_emitted = true;
3842 break;
3843 case TGSI_SEMANTIC_VIEWPORT_INDEX:
3844 /* spi_sid is 0 for outputs that are
3845 * not consumed by PS */
3846 if (shader->output[i].spi_sid) {
3847 output[j].array_base = next_param_base++;
3848 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3849 j++;
3850 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3851 }
3852 output[j].array_base = 61;
3853 output[j].swizzle_x = 7;
3854 output[j].swizzle_y = 7;
3855 output[j].swizzle_z = 7;
3856 output[j].swizzle_w = 0;
3857 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3858 pos_emitted = true;
3859 break;
3860 case TGSI_SEMANTIC_CLIPVERTEX:
3861 j--;
3862 break;
3863 case TGSI_SEMANTIC_CLIPDIST:
3864 output[j].array_base = next_clip_base++;
3865 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3866 pos_emitted = true;
3867 /* spi_sid is 0 for clipdistance outputs that were generated
3868 * for clipvertex - we don't need to pass them to PS */
3869 if (shader->output[i].spi_sid) {
3870 j++;
3871 /* duplicate it as PARAM to pass to the pixel shader */
3872 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3873 output[j].array_base = next_param_base++;
3874 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3875 }
3876 break;
3877 case TGSI_SEMANTIC_FOG:
3878 output[j].swizzle_y = 4; /* 0 */
3879 output[j].swizzle_z = 4; /* 0 */
3880 output[j].swizzle_w = 5; /* 1 */
3881 break;
3882 case TGSI_SEMANTIC_PRIMID:
3883 output[j].swizzle_x = 2;
3884 output[j].swizzle_y = 4; /* 0 */
3885 output[j].swizzle_z = 4; /* 0 */
3886 output[j].swizzle_w = 4; /* 0 */
3887 break;
3888 }
3889
3890 break;
3891 case PIPE_SHADER_FRAGMENT:
3892 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
3893 /* never export more colors than the number of CBs */
3894 if (shader->output[i].sid >= max_color_exports) {
3895 /* skip export */
3896 j--;
3897 continue;
3898 }
3899 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3900 output[j].array_base = shader->output[i].sid;
3901 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3902 shader->nr_ps_color_exports++;
3903 shader->ps_color_export_mask |= (0xf << (shader->output[i].sid * 4));
3904
3905 /* If the i-th target format is set, all previous target formats must
3906 * be non-zero to avoid hangs. - from radeonsi, seems to apply to eg as well.
3907 */
3908 if (shader->output[i].sid > 0)
3909 for (unsigned x = 0; x < shader->output[i].sid; x++)
3910 shader->ps_color_export_mask |= (1 << (x*4));
3911
3912 if (shader->output[i].sid > shader->ps_export_highest)
3913 shader->ps_export_highest = shader->output[i].sid;
3914 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
3915 for (k = 1; k < max_color_exports; k++) {
3916 j++;
3917 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3918 output[j].gpr = shader->output[i].gpr;
3919 output[j].elem_size = 3;
3920 output[j].swizzle_x = 0;
3921 output[j].swizzle_y = 1;
3922 output[j].swizzle_z = 2;
3923 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3924 output[j].burst_count = 1;
3925 output[j].array_base = k;
3926 output[j].op = CF_OP_EXPORT;
3927 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3928 shader->nr_ps_color_exports++;
3929 shader->ps_color_export_mask |= (0xf << (j * 4));
3930 }
3931 }
3932 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
3933 output[j].array_base = 61;
3934 output[j].swizzle_x = 2;
3935 output[j].swizzle_y = 7;
3936 output[j].swizzle_z = output[j].swizzle_w = 7;
3937 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3938 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
3939 output[j].array_base = 61;
3940 output[j].swizzle_x = 7;
3941 output[j].swizzle_y = 1;
3942 output[j].swizzle_z = output[j].swizzle_w = 7;
3943 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3944 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3945 output[j].array_base = 61;
3946 output[j].swizzle_x = 7;
3947 output[j].swizzle_y = 7;
3948 output[j].swizzle_z = 0;
3949 output[j].swizzle_w = 7;
3950 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3951 } else {
3952 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
3953 r = -EINVAL;
3954 goto out_err;
3955 }
3956 break;
3957 case PIPE_SHADER_TESS_CTRL:
3958 break;
3959 default:
3960 R600_ERR("unsupported processor type %d\n", ctx.type);
3961 r = -EINVAL;
3962 goto out_err;
3963 }
3964
3965 if (output[j].type == 0xffffffff) {
3966 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3967 output[j].array_base = next_param_base++;
3968 }
3969 }
3970
3971 /* add fake position export */
3972 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
3973 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3974 output[j].gpr = 0;
3975 output[j].elem_size = 3;
3976 output[j].swizzle_x = 7;
3977 output[j].swizzle_y = 7;
3978 output[j].swizzle_z = 7;
3979 output[j].swizzle_w = 7;
3980 output[j].burst_count = 1;
3981 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3982 output[j].array_base = 60;
3983 output[j].op = CF_OP_EXPORT;
3984 j++;
3985 }
3986
3987 /* add fake param output for vertex shader if no param is exported */
3988 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
3989 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3990 output[j].gpr = 0;
3991 output[j].elem_size = 3;
3992 output[j].swizzle_x = 7;
3993 output[j].swizzle_y = 7;
3994 output[j].swizzle_z = 7;
3995 output[j].swizzle_w = 7;
3996 output[j].burst_count = 1;
3997 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3998 output[j].array_base = 0;
3999 output[j].op = CF_OP_EXPORT;
4000 j++;
4001 }
4002
4003 /* add fake pixel export */
4004 if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
4005 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
4006 output[j].gpr = 0;
4007 output[j].elem_size = 3;
4008 output[j].swizzle_x = 7;
4009 output[j].swizzle_y = 7;
4010 output[j].swizzle_z = 7;
4011 output[j].swizzle_w = 7;
4012 output[j].burst_count = 1;
4013 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4014 output[j].array_base = 0;
4015 output[j].op = CF_OP_EXPORT;
4016 j++;
4017 shader->nr_ps_color_exports++;
4018 shader->ps_color_export_mask = 0xf;
4019 }
4020
4021 noutput = j;
4022
4023 /* set export done on last export of each type */
4024 for (k = noutput - 1, output_done = 0; k >= 0; k--) {
4025 if (!(output_done & (1 << output[k].type))) {
4026 output_done |= (1 << output[k].type);
4027 output[k].op = CF_OP_EXPORT_DONE;
4028 }
4029 }
4030 /* add output to bytecode */
4031 for (i = 0; i < noutput; i++) {
4032 r = r600_bytecode_add_output(ctx.bc, &output[i]);
4033 if (r)
4034 goto out_err;
4035 }
4036 }
4037
4038 /* add program end */
4039 if (ctx.bc->chip_class == CAYMAN)
4040 cm_bytecode_add_cf_end(ctx.bc);
4041 else {
4042 const struct cf_op_info *last = NULL;
4043
4044 if (ctx.bc->cf_last)
4045 last = r600_isa_cf(ctx.bc->cf_last->op);
4046
4047 /* alu clause instructions don't have EOP bit, so add NOP */
4048 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_POP)
4049 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
4050
4051 ctx.bc->cf_last->end_of_program = 1;
4052 }
4053
4054 /* check GPR limit - we have 124 = 128 - 4
4055 * (4 are reserved as alu clause temporary registers) */
4056 if (ctx.bc->ngpr > 124) {
4057 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
4058 r = -ENOMEM;
4059 goto out_err;
4060 }
4061
4062 if (ctx.type == PIPE_SHADER_GEOMETRY) {
4063 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
4064 return r;
4065 }
4066
4067 free(ctx.literals);
4068 tgsi_parse_free(&ctx.parse);
4069 return 0;
4070 out_err:
4071 free(ctx.literals);
4072 tgsi_parse_free(&ctx.parse);
4073 return r;
4074 }
4075
4076 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
4077 {
4078 const unsigned tgsi_opcode =
4079 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
4080 R600_ERR("%s tgsi opcode unsupported\n",
4081 tgsi_get_opcode_name(tgsi_opcode));
4082 return -EINVAL;
4083 }
4084
4085 static int tgsi_end(struct r600_shader_ctx *ctx UNUSED)
4086 {
4087 return 0;
4088 }
4089
4090 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
4091 const struct r600_shader_src *shader_src,
4092 unsigned chan)
4093 {
4094 bc_src->sel = shader_src->sel;
4095 bc_src->chan = shader_src->swizzle[chan];
4096 bc_src->neg = shader_src->neg;
4097 bc_src->abs = shader_src->abs;
4098 bc_src->rel = shader_src->rel;
4099 bc_src->value = shader_src->value[bc_src->chan];
4100 bc_src->kc_bank = shader_src->kc_bank;
4101 bc_src->kc_rel = shader_src->kc_rel;
4102 }
4103
4104 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
4105 {
4106 bc_src->abs = 1;
4107 bc_src->neg = 0;
4108 }
4109
4110 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
4111 {
4112 bc_src->neg = !bc_src->neg;
4113 }
4114
4115 static void tgsi_dst(struct r600_shader_ctx *ctx,
4116 const struct tgsi_full_dst_register *tgsi_dst,
4117 unsigned swizzle,
4118 struct r600_bytecode_alu_dst *r600_dst)
4119 {
4120 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4121
4122 r600_dst->sel = tgsi_dst->Register.Index;
4123 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
4124 r600_dst->chan = swizzle;
4125 r600_dst->write = 1;
4126 if (inst->Instruction.Saturate) {
4127 r600_dst->clamp = 1;
4128 }
4129 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
4130 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
4131 return;
4132 }
4133 }
4134 if (tgsi_dst->Register.Indirect)
4135 r600_dst->rel = V_SQ_REL_RELATIVE;
4136
4137 }
4138
4139 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap, int dest_temp, int op_override)
4140 {
4141 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4142 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4143 struct r600_bytecode_alu alu;
4144 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4145 int use_tmp = 0;
4146 int swizzle_x = inst->Src[0].Register.SwizzleX;
4147
4148 if (singledest) {
4149 switch (write_mask) {
4150 case 0x1:
4151 if (swizzle_x == 2) {
4152 write_mask = 0xc;
4153 use_tmp = 3;
4154 } else
4155 write_mask = 0x3;
4156 break;
4157 case 0x2:
4158 if (swizzle_x == 2) {
4159 write_mask = 0xc;
4160 use_tmp = 3;
4161 } else {
4162 write_mask = 0x3;
4163 use_tmp = 1;
4164 }
4165 break;
4166 case 0x4:
4167 if (swizzle_x == 0) {
4168 write_mask = 0x3;
4169 use_tmp = 1;
4170 } else
4171 write_mask = 0xc;
4172 break;
4173 case 0x8:
4174 if (swizzle_x == 0) {
4175 write_mask = 0x3;
4176 use_tmp = 1;
4177 } else {
4178 write_mask = 0xc;
4179 use_tmp = 3;
4180 }
4181 break;
4182 }
4183 }
4184
4185 lasti = tgsi_last_instruction(write_mask);
4186 for (i = 0; i <= lasti; i++) {
4187
4188 if (!(write_mask & (1 << i)))
4189 continue;
4190
4191 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4192
4193 if (singledest) {
4194 if (use_tmp || dest_temp) {
4195 alu.dst.sel = use_tmp ? ctx->temp_reg : dest_temp;
4196 alu.dst.chan = i;
4197 alu.dst.write = 1;
4198 } else {
4199 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4200 }
4201 if (i == 1 || i == 3)
4202 alu.dst.write = 0;
4203 } else
4204 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4205
4206 alu.op = op_override ? op_override : ctx->inst_info->op;
4207 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
4208 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4209 } else if (!swap) {
4210 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4211 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4212 }
4213 } else {
4214 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
4215 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
4216 }
4217
4218 /* handle some special cases */
4219 if (i == 1 || i == 3) {
4220 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
4221 case TGSI_OPCODE_DABS:
4222 r600_bytecode_src_set_abs(&alu.src[0]);
4223 break;
4224 default:
4225 break;
4226 }
4227 }
4228 if (i == lasti) {
4229 alu.last = 1;
4230 }
4231 r = r600_bytecode_add_alu(ctx->bc, &alu);
4232 if (r)
4233 return r;
4234 }
4235
4236 if (use_tmp) {
4237 write_mask = inst->Dst[0].Register.WriteMask;
4238
4239 lasti = tgsi_last_instruction(write_mask);
4240 /* move result from temp to dst */
4241 for (i = 0; i <= lasti; i++) {
4242 if (!(write_mask & (1 << i)))
4243 continue;
4244
4245 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4246 alu.op = ALU_OP1_MOV;
4247
4248 if (dest_temp) {
4249 alu.dst.sel = dest_temp;
4250 alu.dst.chan = i;
4251 alu.dst.write = 1;
4252 } else
4253 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4254 alu.src[0].sel = ctx->temp_reg;
4255 alu.src[0].chan = use_tmp - 1;
4256 alu.last = (i == lasti);
4257
4258 r = r600_bytecode_add_alu(ctx->bc, &alu);
4259 if (r)
4260 return r;
4261 }
4262 }
4263 return 0;
4264 }
4265
4266 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
4267 {
4268 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4269 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4270 /* confirm writemasking */
4271 if ((write_mask & 0x3) != 0x3 &&
4272 (write_mask & 0xc) != 0xc) {
4273 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
4274 return -1;
4275 }
4276 return tgsi_op2_64_params(ctx, false, false, 0, 0);
4277 }
4278
4279 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
4280 {
4281 return tgsi_op2_64_params(ctx, true, false, 0, 0);
4282 }
4283
4284 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
4285 {
4286 return tgsi_op2_64_params(ctx, true, true, 0, 0);
4287 }
4288
4289 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
4290 {
4291 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4292 struct r600_bytecode_alu alu;
4293 int i, j, r;
4294 int lasti = 3;
4295 int tmp = r600_get_temp(ctx);
4296
4297 for (i = 0; i < lasti + 1; i++) {
4298
4299 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4300 alu.op = ctx->inst_info->op;
4301 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4302 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
4303 }
4304
4305 if (inst->Dst[0].Register.WriteMask & (1 << i))
4306 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4307 else
4308 alu.dst.sel = tmp;
4309
4310 alu.dst.chan = i;
4311 alu.is_op3 = 1;
4312 if (i == lasti) {
4313 alu.last = 1;
4314 }
4315 r = r600_bytecode_add_alu(ctx->bc, &alu);
4316 if (r)
4317 return r;
4318 }
4319 return 0;
4320 }
4321
4322 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
4323 {
4324 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4325 struct r600_bytecode_alu alu;
4326 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4327 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4328 /* use temp register if trans_only and more than one dst component */
4329 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
4330 unsigned op = ctx->inst_info->op;
4331
4332 if (op == ALU_OP2_MUL_IEEE &&
4333 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
4334 op = ALU_OP2_MUL;
4335
4336 for (i = 0; i <= lasti; i++) {
4337 if (!(write_mask & (1 << i)))
4338 continue;
4339
4340 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4341 if (use_tmp) {
4342 alu.dst.sel = ctx->temp_reg;
4343 alu.dst.chan = i;
4344 alu.dst.write = 1;
4345 } else
4346 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4347
4348 alu.op = op;
4349 if (!swap) {
4350 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4351 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4352 }
4353 } else {
4354 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4355 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4356 }
4357 if (i == lasti || trans_only) {
4358 alu.last = 1;
4359 }
4360 r = r600_bytecode_add_alu(ctx->bc, &alu);
4361 if (r)
4362 return r;
4363 }
4364
4365 if (use_tmp) {
4366 /* move result from temp to dst */
4367 for (i = 0; i <= lasti; i++) {
4368 if (!(write_mask & (1 << i)))
4369 continue;
4370
4371 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4372 alu.op = ALU_OP1_MOV;
4373 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4374 alu.src[0].sel = ctx->temp_reg;
4375 alu.src[0].chan = i;
4376 alu.last = (i == lasti);
4377
4378 r = r600_bytecode_add_alu(ctx->bc, &alu);
4379 if (r)
4380 return r;
4381 }
4382 }
4383 return 0;
4384 }
4385
4386 static int tgsi_op2(struct r600_shader_ctx *ctx)
4387 {
4388 return tgsi_op2_s(ctx, 0, 0);
4389 }
4390
4391 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
4392 {
4393 return tgsi_op2_s(ctx, 1, 0);
4394 }
4395
4396 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
4397 {
4398 return tgsi_op2_s(ctx, 0, 1);
4399 }
4400
4401 static int tgsi_ineg(struct r600_shader_ctx *ctx)
4402 {
4403 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4404 struct r600_bytecode_alu alu;
4405 int i, r;
4406 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4407
4408 for (i = 0; i < lasti + 1; i++) {
4409
4410 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4411 continue;
4412 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4413 alu.op = ctx->inst_info->op;
4414
4415 alu.src[0].sel = V_SQ_ALU_SRC_0;
4416
4417 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4418
4419 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4420
4421 if (i == lasti) {
4422 alu.last = 1;
4423 }
4424 r = r600_bytecode_add_alu(ctx->bc, &alu);
4425 if (r)
4426 return r;
4427 }
4428 return 0;
4429
4430 }
4431
4432 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4433 {
4434 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4435 struct r600_bytecode_alu alu;
4436 int i, r;
4437 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4438
4439 for (i = 0; i < lasti + 1; i++) {
4440
4441 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4442 continue;
4443 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4444 alu.op = ALU_OP1_MOV;
4445
4446 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4447
4448 if (i == 1 || i == 3)
4449 r600_bytecode_src_toggle_neg(&alu.src[0]);
4450 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4451
4452 if (i == lasti) {
4453 alu.last = 1;
4454 }
4455 r = r600_bytecode_add_alu(ctx->bc, &alu);
4456 if (r)
4457 return r;
4458 }
4459 return 0;
4460
4461 }
4462
4463 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4464 {
4465 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4466 struct r600_bytecode_alu alu;
4467 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4468 int i, j, r;
4469
4470 for (i = 0; i <= 3; i++) {
4471 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4472 alu.op = ctx->inst_info->op;
4473
4474 alu.dst.sel = ctx->temp_reg;
4475 alu.dst.chan = i;
4476 alu.dst.write = 1;
4477 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4478 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4479 }
4480
4481 if (i == 3)
4482 alu.last = 1;
4483
4484 r = r600_bytecode_add_alu(ctx->bc, &alu);
4485 if (r)
4486 return r;
4487 }
4488
4489 /* Replicate significand result across channels. */
4490 for (i = 0; i <= 3; i++) {
4491 if (!(write_mask & (1 << i)))
4492 continue;
4493
4494 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4495 alu.op = ALU_OP1_MOV;
4496 alu.src[0].chan = (i & 1) + 2;
4497 alu.src[0].sel = ctx->temp_reg;
4498
4499 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4500 alu.dst.write = 1;
4501 alu.last = 1;
4502 r = r600_bytecode_add_alu(ctx->bc, &alu);
4503 if (r)
4504 return r;
4505 }
4506
4507 for (i = 0; i <= 3; i++) {
4508 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4509 /* MOV third channels to writemask dst1 */
4510 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4511 alu.op = ALU_OP1_MOV;
4512 alu.src[0].chan = 1;
4513 alu.src[0].sel = ctx->temp_reg;
4514
4515 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4516 alu.last = 1;
4517 r = r600_bytecode_add_alu(ctx->bc, &alu);
4518 if (r)
4519 return r;
4520 break;
4521 }
4522 }
4523 return 0;
4524 }
4525
4526
4527 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4528 {
4529 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4530 struct r600_bytecode_alu alu;
4531 int i, c, r;
4532 int write_mask = inst->Dst[0].Register.WriteMask;
4533 int temp_reg = r600_get_temp(ctx);
4534
4535 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4536 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4537
4538 for (c = 0; c < 2; c++) {
4539 int dchan = c * 2;
4540 if (write_mask & (0x3 << dchan)) {
4541 /* split into 24-bit int and 8-bit int */
4542 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4543 alu.op = ALU_OP2_AND_INT;
4544 alu.dst.sel = temp_reg;
4545 alu.dst.chan = dchan;
4546 r600_bytecode_src(&alu.src[0], &ctx->src[0], c);
4547 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4548 alu.src[1].value = 0xffffff00;
4549 alu.dst.write = 1;
4550 r = r600_bytecode_add_alu(ctx->bc, &alu);
4551 if (r)
4552 return r;
4553
4554 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4555 alu.op = ALU_OP2_AND_INT;
4556 alu.dst.sel = temp_reg;
4557 alu.dst.chan = dchan + 1;
4558 r600_bytecode_src(&alu.src[0], &ctx->src[0], c);
4559 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4560 alu.src[1].value = 0xff;
4561 alu.dst.write = 1;
4562 alu.last = 1;
4563 r = r600_bytecode_add_alu(ctx->bc, &alu);
4564 if (r)
4565 return r;
4566 }
4567 }
4568
4569 for (c = 0; c < 2; c++) {
4570 int dchan = c * 2;
4571 if (write_mask & (0x3 << dchan)) {
4572 for (i = dchan; i <= dchan + 1; i++) {
4573 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4574 alu.op = i == dchan ? ctx->inst_info->op : ALU_OP1_UINT_TO_FLT;
4575
4576 alu.src[0].sel = temp_reg;
4577 alu.src[0].chan = i;
4578 alu.dst.sel = temp_reg;
4579 alu.dst.chan = i;
4580 alu.dst.write = 1;
4581 if (ctx->bc->chip_class == CAYMAN)
4582 alu.last = i == dchan + 1;
4583 else
4584 alu.last = 1; /* trans only ops on evergreen */
4585
4586 r = r600_bytecode_add_alu(ctx->bc, &alu);
4587 if (r)
4588 return r;
4589 }
4590 }
4591 }
4592
4593 for (c = 0; c < 2; c++) {
4594 int dchan = c * 2;
4595 if (write_mask & (0x3 << dchan)) {
4596 for (i = 0; i < 4; i++) {
4597 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4598 alu.op = ALU_OP1_FLT32_TO_FLT64;
4599
4600 alu.src[0].chan = dchan + (i / 2);
4601 if (i == 0 || i == 2)
4602 alu.src[0].sel = temp_reg;
4603 else {
4604 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4605 alu.src[0].value = 0x0;
4606 }
4607 alu.dst.sel = ctx->temp_reg;
4608 alu.dst.chan = i;
4609 alu.last = i == 3;
4610 alu.dst.write = 1;
4611
4612 r = r600_bytecode_add_alu(ctx->bc, &alu);
4613 if (r)
4614 return r;
4615 }
4616
4617 for (i = 0; i <= 1; i++) {
4618 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4619 alu.op = ALU_OP2_ADD_64;
4620
4621 alu.src[0].chan = fp64_switch(i);
4622 alu.src[0].sel = ctx->temp_reg;
4623
4624 alu.src[1].chan = fp64_switch(i + 2);
4625 alu.src[1].sel = ctx->temp_reg;
4626 tgsi_dst(ctx, &inst->Dst[0], dchan + i, &alu.dst);
4627 alu.last = i == 1;
4628
4629 r = r600_bytecode_add_alu(ctx->bc, &alu);
4630 if (r)
4631 return r;
4632 }
4633 }
4634 }
4635
4636 return 0;
4637 }
4638
4639 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4640 {
4641 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4642 struct r600_bytecode_alu alu;
4643 int i, r;
4644 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4645 int treg = r600_get_temp(ctx);
4646 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4647 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4648
4649 /* do a 64->32 into a temp register */
4650 r = tgsi_op2_64_params(ctx, true, false, treg, ALU_OP1_FLT64_TO_FLT32);
4651 if (r)
4652 return r;
4653
4654 for (i = 0; i <= lasti; i++) {
4655 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4656 continue;
4657 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4658 alu.op = ctx->inst_info->op;
4659
4660 alu.src[0].chan = i;
4661 alu.src[0].sel = treg;
4662 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4663 alu.last = (i == lasti);
4664
4665 r = r600_bytecode_add_alu(ctx->bc, &alu);
4666 if (r)
4667 return r;
4668 }
4669
4670 return 0;
4671 }
4672
4673 static int cayman_emit_unary_double_raw(struct r600_bytecode *bc,
4674 unsigned op,
4675 int dst_reg,
4676 struct r600_shader_src *src,
4677 bool abs)
4678 {
4679 struct r600_bytecode_alu alu;
4680 const int last_slot = 3;
4681 int r;
4682
4683 /* these have to write the result to X/Y by the looks of it */
4684 for (int i = 0 ; i < last_slot; i++) {
4685 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4686 alu.op = op;
4687
4688 r600_bytecode_src(&alu.src[0], src, 1);
4689 r600_bytecode_src(&alu.src[1], src, 0);
4690
4691 if (abs)
4692 r600_bytecode_src_set_abs(&alu.src[1]);
4693
4694 alu.dst.sel = dst_reg;
4695 alu.dst.chan = i;
4696 alu.dst.write = (i == 0 || i == 1);
4697
4698 if (bc->chip_class != CAYMAN || i == last_slot - 1)
4699 alu.last = 1;
4700 r = r600_bytecode_add_alu(bc, &alu);
4701 if (r)
4702 return r;
4703 }
4704
4705 return 0;
4706 }
4707
4708 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4709 {
4710 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4711 int i, r;
4712 struct r600_bytecode_alu alu;
4713 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4714 int t1 = ctx->temp_reg;
4715
4716 /* should only be one src regs */
4717 assert(inst->Instruction.NumSrcRegs == 1);
4718
4719 /* only support one double at a time */
4720 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4721 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4722
4723 r = cayman_emit_unary_double_raw(
4724 ctx->bc, ctx->inst_info->op, t1,
4725 &ctx->src[0],
4726 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4727 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT);
4728 if (r)
4729 return r;
4730
4731 for (i = 0 ; i <= lasti; i++) {
4732 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4733 continue;
4734 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4735 alu.op = ALU_OP1_MOV;
4736 alu.src[0].sel = t1;
4737 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
4738 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4739 alu.dst.write = 1;
4740 if (i == lasti)
4741 alu.last = 1;
4742 r = r600_bytecode_add_alu(ctx->bc, &alu);
4743 if (r)
4744 return r;
4745 }
4746 return 0;
4747 }
4748
4749 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
4750 {
4751 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4752 int i, j, r;
4753 struct r600_bytecode_alu alu;
4754 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4755
4756 for (i = 0 ; i < last_slot; i++) {
4757 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4758 alu.op = ctx->inst_info->op;
4759 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4760 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
4761
4762 /* RSQ should take the absolute value of src */
4763 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
4764 r600_bytecode_src_set_abs(&alu.src[j]);
4765 }
4766 }
4767 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4768 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4769
4770 if (i == last_slot - 1)
4771 alu.last = 1;
4772 r = r600_bytecode_add_alu(ctx->bc, &alu);
4773 if (r)
4774 return r;
4775 }
4776 return 0;
4777 }
4778
4779 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
4780 {
4781 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4782 int i, j, k, r;
4783 struct r600_bytecode_alu alu;
4784 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4785 int t1 = ctx->temp_reg;
4786
4787 for (k = 0; k <= lasti; k++) {
4788 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
4789 continue;
4790
4791 for (i = 0 ; i < 4; i++) {
4792 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4793 alu.op = ctx->inst_info->op;
4794 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4795 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
4796 }
4797 alu.dst.sel = t1;
4798 alu.dst.chan = i;
4799 alu.dst.write = (i == k);
4800 if (i == 3)
4801 alu.last = 1;
4802 r = r600_bytecode_add_alu(ctx->bc, &alu);
4803 if (r)
4804 return r;
4805 }
4806 }
4807
4808 for (i = 0 ; i <= lasti; i++) {
4809 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4810 continue;
4811 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4812 alu.op = ALU_OP1_MOV;
4813 alu.src[0].sel = t1;
4814 alu.src[0].chan = i;
4815 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4816 alu.dst.write = 1;
4817 if (i == lasti)
4818 alu.last = 1;
4819 r = r600_bytecode_add_alu(ctx->bc, &alu);
4820 if (r)
4821 return r;
4822 }
4823
4824 return 0;
4825 }
4826
4827
4828 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
4829 {
4830 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4831 int i, j, k, r;
4832 struct r600_bytecode_alu alu;
4833 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4834 int t1 = ctx->temp_reg;
4835
4836 /* t1 would get overwritten below if we actually tried to
4837 * multiply two pairs of doubles at a time. */
4838 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4839 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4840
4841 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4842
4843 for (i = 0; i < 4; i++) {
4844 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4845 alu.op = ctx->inst_info->op;
4846 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4847 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));
4848 }
4849 alu.dst.sel = t1;
4850 alu.dst.chan = i;
4851 alu.dst.write = 1;
4852 if (i == 3)
4853 alu.last = 1;
4854 r = r600_bytecode_add_alu(ctx->bc, &alu);
4855 if (r)
4856 return r;
4857 }
4858
4859 for (i = 0; i <= lasti; i++) {
4860 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4861 continue;
4862 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4863 alu.op = ALU_OP1_MOV;
4864 alu.src[0].sel = t1;
4865 alu.src[0].chan = i;
4866 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4867 alu.dst.write = 1;
4868 if (i == lasti)
4869 alu.last = 1;
4870 r = r600_bytecode_add_alu(ctx->bc, &alu);
4871 if (r)
4872 return r;
4873 }
4874
4875 return 0;
4876 }
4877
4878 /*
4879 * Emit RECIP_64 + MUL_64 to implement division.
4880 */
4881 static int cayman_ddiv_instr(struct r600_shader_ctx *ctx)
4882 {
4883 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4884 int r;
4885 struct r600_bytecode_alu alu;
4886 int t1 = ctx->temp_reg;
4887 int k;
4888
4889 /* Only support one double at a time. This is the same constraint as
4890 * in DMUL lowering. */
4891 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4892 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4893
4894 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4895
4896 r = cayman_emit_unary_double_raw(ctx->bc, ALU_OP2_RECIP_64, t1, &ctx->src[1], false);
4897 if (r)
4898 return r;
4899
4900 for (int i = 0; i < 4; i++) {
4901 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4902 alu.op = ALU_OP2_MUL_64;
4903
4904 r600_bytecode_src(&alu.src[0], &ctx->src[0], k * 2 + ((i == 3) ? 0 : 1));
4905
4906 alu.src[1].sel = t1;
4907 alu.src[1].chan = (i == 3) ? 0 : 1;
4908
4909 alu.dst.sel = t1;
4910 alu.dst.chan = i;
4911 alu.dst.write = 1;
4912 if (i == 3)
4913 alu.last = 1;
4914 r = r600_bytecode_add_alu(ctx->bc, &alu);
4915 if (r)
4916 return r;
4917 }
4918
4919 for (int i = 0; i < 2; i++) {
4920 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4921 alu.op = ALU_OP1_MOV;
4922 alu.src[0].sel = t1;
4923 alu.src[0].chan = i;
4924 tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
4925 alu.dst.write = 1;
4926 if (i == 1)
4927 alu.last = 1;
4928 r = r600_bytecode_add_alu(ctx->bc, &alu);
4929 if (r)
4930 return r;
4931 }
4932 return 0;
4933 }
4934
4935 /*
4936 * r600 - trunc to -PI..PI range
4937 * r700 - normalize by dividing by 2PI
4938 * see fdo bug 27901
4939 */
4940 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
4941 {
4942 int r;
4943 struct r600_bytecode_alu alu;
4944
4945 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4946 alu.op = ALU_OP3_MULADD;
4947 alu.is_op3 = 1;
4948
4949 alu.dst.chan = 0;
4950 alu.dst.sel = ctx->temp_reg;
4951 alu.dst.write = 1;
4952
4953 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4954
4955 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4956 alu.src[1].chan = 0;
4957 alu.src[1].value = u_bitcast_f2u(0.5f * M_1_PI);
4958 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4959 alu.src[2].chan = 0;
4960 alu.last = 1;
4961 r = r600_bytecode_add_alu(ctx->bc, &alu);
4962 if (r)
4963 return r;
4964
4965 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4966 alu.op = ALU_OP1_FRACT;
4967
4968 alu.dst.chan = 0;
4969 alu.dst.sel = ctx->temp_reg;
4970 alu.dst.write = 1;
4971
4972 alu.src[0].sel = ctx->temp_reg;
4973 alu.src[0].chan = 0;
4974 alu.last = 1;
4975 r = r600_bytecode_add_alu(ctx->bc, &alu);
4976 if (r)
4977 return r;
4978
4979 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4980 alu.op = ALU_OP3_MULADD;
4981 alu.is_op3 = 1;
4982
4983 alu.dst.chan = 0;
4984 alu.dst.sel = ctx->temp_reg;
4985 alu.dst.write = 1;
4986
4987 alu.src[0].sel = ctx->temp_reg;
4988 alu.src[0].chan = 0;
4989
4990 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4991 alu.src[1].chan = 0;
4992 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4993 alu.src[2].chan = 0;
4994
4995 if (ctx->bc->chip_class == R600) {
4996 alu.src[1].value = u_bitcast_f2u(2.0f * M_PI);
4997 alu.src[2].value = u_bitcast_f2u(-M_PI);
4998 } else {
4999 alu.src[1].sel = V_SQ_ALU_SRC_1;
5000 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
5001 alu.src[2].neg = 1;
5002 }
5003
5004 alu.last = 1;
5005 r = r600_bytecode_add_alu(ctx->bc, &alu);
5006 if (r)
5007 return r;
5008 return 0;
5009 }
5010
5011 static int cayman_trig(struct r600_shader_ctx *ctx)
5012 {
5013 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5014 struct r600_bytecode_alu alu;
5015 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5016 int i, r;
5017
5018 r = tgsi_setup_trig(ctx);
5019 if (r)
5020 return r;
5021
5022
5023 for (i = 0; i < last_slot; i++) {
5024 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5025 alu.op = ctx->inst_info->op;
5026 alu.dst.chan = i;
5027
5028 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5029 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5030
5031 alu.src[0].sel = ctx->temp_reg;
5032 alu.src[0].chan = 0;
5033 if (i == last_slot - 1)
5034 alu.last = 1;
5035 r = r600_bytecode_add_alu(ctx->bc, &alu);
5036 if (r)
5037 return r;
5038 }
5039 return 0;
5040 }
5041
5042 static int tgsi_trig(struct r600_shader_ctx *ctx)
5043 {
5044 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5045 struct r600_bytecode_alu alu;
5046 int i, r;
5047 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5048
5049 r = tgsi_setup_trig(ctx);
5050 if (r)
5051 return r;
5052
5053 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5054 alu.op = ctx->inst_info->op;
5055 alu.dst.chan = 0;
5056 alu.dst.sel = ctx->temp_reg;
5057 alu.dst.write = 1;
5058
5059 alu.src[0].sel = ctx->temp_reg;
5060 alu.src[0].chan = 0;
5061 alu.last = 1;
5062 r = r600_bytecode_add_alu(ctx->bc, &alu);
5063 if (r)
5064 return r;
5065
5066 /* replicate result */
5067 for (i = 0; i < lasti + 1; i++) {
5068 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5069 continue;
5070
5071 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5072 alu.op = ALU_OP1_MOV;
5073
5074 alu.src[0].sel = ctx->temp_reg;
5075 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5076 if (i == lasti)
5077 alu.last = 1;
5078 r = r600_bytecode_add_alu(ctx->bc, &alu);
5079 if (r)
5080 return r;
5081 }
5082 return 0;
5083 }
5084
5085 static int tgsi_kill(struct r600_shader_ctx *ctx)
5086 {
5087 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5088 struct r600_bytecode_alu alu;
5089 int i, r;
5090
5091 for (i = 0; i < 4; i++) {
5092 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5093 alu.op = ctx->inst_info->op;
5094
5095 alu.dst.chan = i;
5096
5097 alu.src[0].sel = V_SQ_ALU_SRC_0;
5098
5099 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
5100 alu.src[1].sel = V_SQ_ALU_SRC_1;
5101 alu.src[1].neg = 1;
5102 } else {
5103 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5104 }
5105 if (i == 3) {
5106 alu.last = 1;
5107 }
5108 r = r600_bytecode_add_alu(ctx->bc, &alu);
5109 if (r)
5110 return r;
5111 }
5112
5113 /* kill must be last in ALU */
5114 ctx->bc->force_add_cf = 1;
5115 ctx->shader->uses_kill = TRUE;
5116 return 0;
5117 }
5118
5119 static int tgsi_lit(struct r600_shader_ctx *ctx)
5120 {
5121 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5122 struct r600_bytecode_alu alu;
5123 int r;
5124
5125 /* tmp.x = max(src.y, 0.0) */
5126 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5127 alu.op = ALU_OP2_MAX;
5128 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
5129 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
5130 alu.src[1].chan = 1;
5131
5132 alu.dst.sel = ctx->temp_reg;
5133 alu.dst.chan = 0;
5134 alu.dst.write = 1;
5135
5136 alu.last = 1;
5137 r = r600_bytecode_add_alu(ctx->bc, &alu);
5138 if (r)
5139 return r;
5140
5141 if (inst->Dst[0].Register.WriteMask & (1 << 2))
5142 {
5143 int chan;
5144 int sel;
5145 unsigned i;
5146
5147 if (ctx->bc->chip_class == CAYMAN) {
5148 for (i = 0; i < 3; i++) {
5149 /* tmp.z = log(tmp.x) */
5150 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5151 alu.op = ALU_OP1_LOG_CLAMPED;
5152 alu.src[0].sel = ctx->temp_reg;
5153 alu.src[0].chan = 0;
5154 alu.dst.sel = ctx->temp_reg;
5155 alu.dst.chan = i;
5156 if (i == 2) {
5157 alu.dst.write = 1;
5158 alu.last = 1;
5159 } else
5160 alu.dst.write = 0;
5161
5162 r = r600_bytecode_add_alu(ctx->bc, &alu);
5163 if (r)
5164 return r;
5165 }
5166 } else {
5167 /* tmp.z = log(tmp.x) */
5168 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5169 alu.op = ALU_OP1_LOG_CLAMPED;
5170 alu.src[0].sel = ctx->temp_reg;
5171 alu.src[0].chan = 0;
5172 alu.dst.sel = ctx->temp_reg;
5173 alu.dst.chan = 2;
5174 alu.dst.write = 1;
5175 alu.last = 1;
5176 r = r600_bytecode_add_alu(ctx->bc, &alu);
5177 if (r)
5178 return r;
5179 }
5180
5181 chan = alu.dst.chan;
5182 sel = alu.dst.sel;
5183
5184 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
5185 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5186 alu.op = ALU_OP3_MUL_LIT;
5187 alu.src[0].sel = sel;
5188 alu.src[0].chan = chan;
5189 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
5190 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
5191 alu.dst.sel = ctx->temp_reg;
5192 alu.dst.chan = 0;
5193 alu.dst.write = 1;
5194 alu.is_op3 = 1;
5195 alu.last = 1;
5196 r = r600_bytecode_add_alu(ctx->bc, &alu);
5197 if (r)
5198 return r;
5199
5200 if (ctx->bc->chip_class == CAYMAN) {
5201 for (i = 0; i < 3; i++) {
5202 /* dst.z = exp(tmp.x) */
5203 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5204 alu.op = ALU_OP1_EXP_IEEE;
5205 alu.src[0].sel = ctx->temp_reg;
5206 alu.src[0].chan = 0;
5207 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5208 if (i == 2) {
5209 alu.dst.write = 1;
5210 alu.last = 1;
5211 } else
5212 alu.dst.write = 0;
5213 r = r600_bytecode_add_alu(ctx->bc, &alu);
5214 if (r)
5215 return r;
5216 }
5217 } else {
5218 /* dst.z = exp(tmp.x) */
5219 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5220 alu.op = ALU_OP1_EXP_IEEE;
5221 alu.src[0].sel = ctx->temp_reg;
5222 alu.src[0].chan = 0;
5223 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
5224 alu.last = 1;
5225 r = r600_bytecode_add_alu(ctx->bc, &alu);
5226 if (r)
5227 return r;
5228 }
5229 }
5230
5231 /* dst.x, <- 1.0 */
5232 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5233 alu.op = ALU_OP1_MOV;
5234 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
5235 alu.src[0].chan = 0;
5236 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
5237 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
5238 r = r600_bytecode_add_alu(ctx->bc, &alu);
5239 if (r)
5240 return r;
5241
5242 /* dst.y = max(src.x, 0.0) */
5243 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5244 alu.op = ALU_OP2_MAX;
5245 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5246 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
5247 alu.src[1].chan = 0;
5248 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
5249 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
5250 r = r600_bytecode_add_alu(ctx->bc, &alu);
5251 if (r)
5252 return r;
5253
5254 /* dst.w, <- 1.0 */
5255 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5256 alu.op = ALU_OP1_MOV;
5257 alu.src[0].sel = V_SQ_ALU_SRC_1;
5258 alu.src[0].chan = 0;
5259 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
5260 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
5261 alu.last = 1;
5262 r = r600_bytecode_add_alu(ctx->bc, &alu);
5263 if (r)
5264 return r;
5265
5266 return 0;
5267 }
5268
5269 static int tgsi_rsq(struct r600_shader_ctx *ctx)
5270 {
5271 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5272 struct r600_bytecode_alu alu;
5273 int i, r;
5274
5275 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5276
5277 alu.op = ALU_OP1_RECIPSQRT_IEEE;
5278
5279 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5280 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
5281 r600_bytecode_src_set_abs(&alu.src[i]);
5282 }
5283 alu.dst.sel = ctx->temp_reg;
5284 alu.dst.write = 1;
5285 alu.last = 1;
5286 r = r600_bytecode_add_alu(ctx->bc, &alu);
5287 if (r)
5288 return r;
5289 /* replicate result */
5290 return tgsi_helper_tempx_replicate(ctx);
5291 }
5292
5293 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
5294 {
5295 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5296 struct r600_bytecode_alu alu;
5297 int i, r;
5298
5299 for (i = 0; i < 4; i++) {
5300 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5301 alu.src[0].sel = ctx->temp_reg;
5302 alu.op = ALU_OP1_MOV;
5303 alu.dst.chan = i;
5304 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5305 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5306 if (i == 3)
5307 alu.last = 1;
5308 r = r600_bytecode_add_alu(ctx->bc, &alu);
5309 if (r)
5310 return r;
5311 }
5312 return 0;
5313 }
5314
5315 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
5316 {
5317 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5318 struct r600_bytecode_alu alu;
5319 int i, r;
5320
5321 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5322 alu.op = ctx->inst_info->op;
5323 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5324 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
5325 }
5326 alu.dst.sel = ctx->temp_reg;
5327 alu.dst.write = 1;
5328 alu.last = 1;
5329 r = r600_bytecode_add_alu(ctx->bc, &alu);
5330 if (r)
5331 return r;
5332 /* replicate result */
5333 return tgsi_helper_tempx_replicate(ctx);
5334 }
5335
5336 static int cayman_pow(struct r600_shader_ctx *ctx)
5337 {
5338 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5339 int i, r;
5340 struct r600_bytecode_alu alu;
5341 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5342
5343 for (i = 0; i < 3; i++) {
5344 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5345 alu.op = ALU_OP1_LOG_IEEE;
5346 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5347 alu.dst.sel = ctx->temp_reg;
5348 alu.dst.chan = i;
5349 alu.dst.write = 1;
5350 if (i == 2)
5351 alu.last = 1;
5352 r = r600_bytecode_add_alu(ctx->bc, &alu);
5353 if (r)
5354 return r;
5355 }
5356
5357 /* b * LOG2(a) */
5358 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5359 alu.op = ALU_OP2_MUL;
5360 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5361 alu.src[1].sel = ctx->temp_reg;
5362 alu.dst.sel = ctx->temp_reg;
5363 alu.dst.write = 1;
5364 alu.last = 1;
5365 r = r600_bytecode_add_alu(ctx->bc, &alu);
5366 if (r)
5367 return r;
5368
5369 for (i = 0; i < last_slot; i++) {
5370 /* POW(a,b) = EXP2(b * LOG2(a))*/
5371 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5372 alu.op = ALU_OP1_EXP_IEEE;
5373 alu.src[0].sel = ctx->temp_reg;
5374
5375 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5376 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5377 if (i == last_slot - 1)
5378 alu.last = 1;
5379 r = r600_bytecode_add_alu(ctx->bc, &alu);
5380 if (r)
5381 return r;
5382 }
5383 return 0;
5384 }
5385
5386 static int tgsi_pow(struct r600_shader_ctx *ctx)
5387 {
5388 struct r600_bytecode_alu alu;
5389 int r;
5390
5391 /* LOG2(a) */
5392 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5393 alu.op = ALU_OP1_LOG_IEEE;
5394 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5395 alu.dst.sel = ctx->temp_reg;
5396 alu.dst.write = 1;
5397 alu.last = 1;
5398 r = r600_bytecode_add_alu(ctx->bc, &alu);
5399 if (r)
5400 return r;
5401 /* b * LOG2(a) */
5402 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5403 alu.op = ALU_OP2_MUL;
5404 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5405 alu.src[1].sel = ctx->temp_reg;
5406 alu.dst.sel = ctx->temp_reg;
5407 alu.dst.write = 1;
5408 alu.last = 1;
5409 r = r600_bytecode_add_alu(ctx->bc, &alu);
5410 if (r)
5411 return r;
5412 /* POW(a,b) = EXP2(b * LOG2(a))*/
5413 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5414 alu.op = ALU_OP1_EXP_IEEE;
5415 alu.src[0].sel = ctx->temp_reg;
5416 alu.dst.sel = ctx->temp_reg;
5417 alu.dst.write = 1;
5418 alu.last = 1;
5419 r = r600_bytecode_add_alu(ctx->bc, &alu);
5420 if (r)
5421 return r;
5422 return tgsi_helper_tempx_replicate(ctx);
5423 }
5424
5425 static int emit_mul_int_op(struct r600_bytecode *bc,
5426 struct r600_bytecode_alu *alu_src)
5427 {
5428 struct r600_bytecode_alu alu;
5429 int i, r;
5430 alu = *alu_src;
5431 if (bc->chip_class == CAYMAN) {
5432 for (i = 0; i < 4; i++) {
5433 alu.dst.chan = i;
5434 alu.dst.write = (i == alu_src->dst.chan);
5435 alu.last = (i == 3);
5436
5437 r = r600_bytecode_add_alu(bc, &alu);
5438 if (r)
5439 return r;
5440 }
5441 } else {
5442 alu.last = 1;
5443 r = r600_bytecode_add_alu(bc, &alu);
5444 if (r)
5445 return r;
5446 }
5447 return 0;
5448 }
5449
5450 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5451 {
5452 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5453 struct r600_bytecode_alu alu;
5454 int i, r, j;
5455 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5456 int tmp0 = ctx->temp_reg;
5457 int tmp1 = r600_get_temp(ctx);
5458 int tmp2 = r600_get_temp(ctx);
5459 int tmp3 = r600_get_temp(ctx);
5460 /* Unsigned path:
5461 *
5462 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5463 *
5464 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5465 * 2. tmp0.z = lo (tmp0.x * src2)
5466 * 3. tmp0.w = -tmp0.z
5467 * 4. tmp0.y = hi (tmp0.x * src2)
5468 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5469 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5470 * 7. tmp1.x = tmp0.x - tmp0.w
5471 * 8. tmp1.y = tmp0.x + tmp0.w
5472 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5473 * 10. tmp0.z = hi(tmp0.x * src1) = q
5474 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5475 *
5476 * 12. tmp0.w = src1 - tmp0.y = r
5477 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5478 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5479 *
5480 * if DIV
5481 *
5482 * 15. tmp1.z = tmp0.z + 1 = q + 1
5483 * 16. tmp1.w = tmp0.z - 1 = q - 1
5484 *
5485 * else MOD
5486 *
5487 * 15. tmp1.z = tmp0.w - src2 = r - src2
5488 * 16. tmp1.w = tmp0.w + src2 = r + src2
5489 *
5490 * endif
5491 *
5492 * 17. tmp1.x = tmp1.x & tmp1.y
5493 *
5494 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5495 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5496 *
5497 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5498 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5499 *
5500 * Signed path:
5501 *
5502 * Same as unsigned, using abs values of the operands,
5503 * and fixing the sign of the result in the end.
5504 */
5505
5506 for (i = 0; i < 4; i++) {
5507 if (!(write_mask & (1<<i)))
5508 continue;
5509
5510 if (signed_op) {
5511
5512 /* tmp2.x = -src0 */
5513 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5514 alu.op = ALU_OP2_SUB_INT;
5515
5516 alu.dst.sel = tmp2;
5517 alu.dst.chan = 0;
5518 alu.dst.write = 1;
5519
5520 alu.src[0].sel = V_SQ_ALU_SRC_0;
5521
5522 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5523
5524 alu.last = 1;
5525 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5526 return r;
5527
5528 /* tmp2.y = -src1 */
5529 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5530 alu.op = ALU_OP2_SUB_INT;
5531
5532 alu.dst.sel = tmp2;
5533 alu.dst.chan = 1;
5534 alu.dst.write = 1;
5535
5536 alu.src[0].sel = V_SQ_ALU_SRC_0;
5537
5538 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5539
5540 alu.last = 1;
5541 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5542 return r;
5543
5544 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5545 /* it will be a sign of the quotient */
5546 if (!mod) {
5547
5548 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5549 alu.op = ALU_OP2_XOR_INT;
5550
5551 alu.dst.sel = tmp2;
5552 alu.dst.chan = 2;
5553 alu.dst.write = 1;
5554
5555 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5556 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5557
5558 alu.last = 1;
5559 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5560 return r;
5561 }
5562
5563 /* tmp2.x = |src0| */
5564 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5565 alu.op = ALU_OP3_CNDGE_INT;
5566 alu.is_op3 = 1;
5567
5568 alu.dst.sel = tmp2;
5569 alu.dst.chan = 0;
5570 alu.dst.write = 1;
5571
5572 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5573 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5574 alu.src[2].sel = tmp2;
5575 alu.src[2].chan = 0;
5576
5577 alu.last = 1;
5578 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5579 return r;
5580
5581 /* tmp2.y = |src1| */
5582 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5583 alu.op = ALU_OP3_CNDGE_INT;
5584 alu.is_op3 = 1;
5585
5586 alu.dst.sel = tmp2;
5587 alu.dst.chan = 1;
5588 alu.dst.write = 1;
5589
5590 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5591 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5592 alu.src[2].sel = tmp2;
5593 alu.src[2].chan = 1;
5594
5595 alu.last = 1;
5596 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5597 return r;
5598
5599 }
5600
5601 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5602 if (ctx->bc->chip_class == CAYMAN) {
5603 /* tmp3.x = u2f(src2) */
5604 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5605 alu.op = ALU_OP1_UINT_TO_FLT;
5606
5607 alu.dst.sel = tmp3;
5608 alu.dst.chan = 0;
5609 alu.dst.write = 1;
5610
5611 if (signed_op) {
5612 alu.src[0].sel = tmp2;
5613 alu.src[0].chan = 1;
5614 } else {
5615 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5616 }
5617
5618 alu.last = 1;
5619 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5620 return r;
5621
5622 /* tmp0.x = recip(tmp3.x) */
5623 for (j = 0 ; j < 3; j++) {
5624 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5625 alu.op = ALU_OP1_RECIP_IEEE;
5626
5627 alu.dst.sel = tmp0;
5628 alu.dst.chan = j;
5629 alu.dst.write = (j == 0);
5630
5631 alu.src[0].sel = tmp3;
5632 alu.src[0].chan = 0;
5633
5634 if (j == 2)
5635 alu.last = 1;
5636 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5637 return r;
5638 }
5639
5640 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5641 alu.op = ALU_OP2_MUL;
5642
5643 alu.src[0].sel = tmp0;
5644 alu.src[0].chan = 0;
5645
5646 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5647 alu.src[1].value = 0x4f800000;
5648
5649 alu.dst.sel = tmp3;
5650 alu.dst.write = 1;
5651 alu.last = 1;
5652 r = r600_bytecode_add_alu(ctx->bc, &alu);
5653 if (r)
5654 return r;
5655
5656 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5657 alu.op = ALU_OP1_FLT_TO_UINT;
5658
5659 alu.dst.sel = tmp0;
5660 alu.dst.chan = 0;
5661 alu.dst.write = 1;
5662
5663 alu.src[0].sel = tmp3;
5664 alu.src[0].chan = 0;
5665
5666 alu.last = 1;
5667 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5668 return r;
5669
5670 } else {
5671 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5672 alu.op = ALU_OP1_RECIP_UINT;
5673
5674 alu.dst.sel = tmp0;
5675 alu.dst.chan = 0;
5676 alu.dst.write = 1;
5677
5678 if (signed_op) {
5679 alu.src[0].sel = tmp2;
5680 alu.src[0].chan = 1;
5681 } else {
5682 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5683 }
5684
5685 alu.last = 1;
5686 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5687 return r;
5688 }
5689
5690 /* 2. tmp0.z = lo (tmp0.x * src2) */
5691 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5692 alu.op = ALU_OP2_MULLO_UINT;
5693
5694 alu.dst.sel = tmp0;
5695 alu.dst.chan = 2;
5696 alu.dst.write = 1;
5697
5698 alu.src[0].sel = tmp0;
5699 alu.src[0].chan = 0;
5700 if (signed_op) {
5701 alu.src[1].sel = tmp2;
5702 alu.src[1].chan = 1;
5703 } else {
5704 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5705 }
5706
5707 if ((r = emit_mul_int_op(ctx->bc, &alu)))
5708 return r;
5709
5710 /* 3. tmp0.w = -tmp0.z */
5711 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5712 alu.op = ALU_OP2_SUB_INT;
5713
5714 alu.dst.sel = tmp0;
5715 alu.dst.chan = 3;
5716 alu.dst.write = 1;
5717
5718 alu.src[0].sel = V_SQ_ALU_SRC_0;
5719 alu.src[1].sel = tmp0;
5720 alu.src[1].chan = 2;
5721
5722 alu.last = 1;
5723 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5724 return r;
5725
5726 /* 4. tmp0.y = hi (tmp0.x * src2) */
5727 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5728 alu.op = ALU_OP2_MULHI_UINT;
5729
5730 alu.dst.sel = tmp0;
5731 alu.dst.chan = 1;
5732 alu.dst.write = 1;
5733
5734 alu.src[0].sel = tmp0;
5735 alu.src[0].chan = 0;
5736
5737 if (signed_op) {
5738 alu.src[1].sel = tmp2;
5739 alu.src[1].chan = 1;
5740 } else {
5741 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5742 }
5743
5744 if ((r = emit_mul_int_op(ctx->bc, &alu)))
5745 return r;
5746
5747 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5748 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5749 alu.op = ALU_OP3_CNDE_INT;
5750 alu.is_op3 = 1;
5751
5752 alu.dst.sel = tmp0;
5753 alu.dst.chan = 2;
5754 alu.dst.write = 1;
5755
5756 alu.src[0].sel = tmp0;
5757 alu.src[0].chan = 1;
5758 alu.src[1].sel = tmp0;
5759 alu.src[1].chan = 3;
5760 alu.src[2].sel = tmp0;
5761 alu.src[2].chan = 2;
5762
5763 alu.last = 1;
5764 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5765 return r;
5766
5767 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5768 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5769 alu.op = ALU_OP2_MULHI_UINT;
5770
5771 alu.dst.sel = tmp0;
5772 alu.dst.chan = 3;
5773 alu.dst.write = 1;
5774
5775 alu.src[0].sel = tmp0;
5776 alu.src[0].chan = 2;
5777
5778 alu.src[1].sel = tmp0;
5779 alu.src[1].chan = 0;
5780
5781 if ((r = emit_mul_int_op(ctx->bc, &alu)))
5782 return r;
5783
5784 /* 7. tmp1.x = tmp0.x - tmp0.w */
5785 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5786 alu.op = ALU_OP2_SUB_INT;
5787
5788 alu.dst.sel = tmp1;
5789 alu.dst.chan = 0;
5790 alu.dst.write = 1;
5791
5792 alu.src[0].sel = tmp0;
5793 alu.src[0].chan = 0;
5794 alu.src[1].sel = tmp0;
5795 alu.src[1].chan = 3;
5796
5797 alu.last = 1;
5798 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5799 return r;
5800
5801 /* 8. tmp1.y = tmp0.x + tmp0.w */
5802 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5803 alu.op = ALU_OP2_ADD_INT;
5804
5805 alu.dst.sel = tmp1;
5806 alu.dst.chan = 1;
5807 alu.dst.write = 1;
5808
5809 alu.src[0].sel = tmp0;
5810 alu.src[0].chan = 0;
5811 alu.src[1].sel = tmp0;
5812 alu.src[1].chan = 3;
5813
5814 alu.last = 1;
5815 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5816 return r;
5817
5818 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5819 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5820 alu.op = ALU_OP3_CNDE_INT;
5821 alu.is_op3 = 1;
5822
5823 alu.dst.sel = tmp0;
5824 alu.dst.chan = 0;
5825 alu.dst.write = 1;
5826
5827 alu.src[0].sel = tmp0;
5828 alu.src[0].chan = 1;
5829 alu.src[1].sel = tmp1;
5830 alu.src[1].chan = 1;
5831 alu.src[2].sel = tmp1;
5832 alu.src[2].chan = 0;
5833
5834 alu.last = 1;
5835 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5836 return r;
5837
5838 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5839 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5840 alu.op = ALU_OP2_MULHI_UINT;
5841
5842 alu.dst.sel = tmp0;
5843 alu.dst.chan = 2;
5844 alu.dst.write = 1;
5845
5846 alu.src[0].sel = tmp0;
5847 alu.src[0].chan = 0;
5848
5849 if (signed_op) {
5850 alu.src[1].sel = tmp2;
5851 alu.src[1].chan = 0;
5852 } else {
5853 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5854 }
5855
5856 if ((r = emit_mul_int_op(ctx->bc, &alu)))
5857 return r;
5858
5859 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5860 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5861 alu.op = ALU_OP2_MULLO_UINT;
5862
5863 alu.dst.sel = tmp0;
5864 alu.dst.chan = 1;
5865 alu.dst.write = 1;
5866
5867 if (signed_op) {
5868 alu.src[0].sel = tmp2;
5869 alu.src[0].chan = 1;
5870 } else {
5871 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5872 }
5873
5874 alu.src[1].sel = tmp0;
5875 alu.src[1].chan = 2;
5876
5877 if ((r = emit_mul_int_op(ctx->bc, &alu)))
5878 return r;
5879
5880 /* 12. tmp0.w = src1 - tmp0.y = r */
5881 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5882 alu.op = ALU_OP2_SUB_INT;
5883
5884 alu.dst.sel = tmp0;
5885 alu.dst.chan = 3;
5886 alu.dst.write = 1;
5887
5888 if (signed_op) {
5889 alu.src[0].sel = tmp2;
5890 alu.src[0].chan = 0;
5891 } else {
5892 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5893 }
5894
5895 alu.src[1].sel = tmp0;
5896 alu.src[1].chan = 1;
5897
5898 alu.last = 1;
5899 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5900 return r;
5901
5902 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5903 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5904 alu.op = ALU_OP2_SETGE_UINT;
5905
5906 alu.dst.sel = tmp1;
5907 alu.dst.chan = 0;
5908 alu.dst.write = 1;
5909
5910 alu.src[0].sel = tmp0;
5911 alu.src[0].chan = 3;
5912 if (signed_op) {
5913 alu.src[1].sel = tmp2;
5914 alu.src[1].chan = 1;
5915 } else {
5916 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5917 }
5918
5919 alu.last = 1;
5920 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5921 return r;
5922
5923 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5924 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5925 alu.op = ALU_OP2_SETGE_UINT;
5926
5927 alu.dst.sel = tmp1;
5928 alu.dst.chan = 1;
5929 alu.dst.write = 1;
5930
5931 if (signed_op) {
5932 alu.src[0].sel = tmp2;
5933 alu.src[0].chan = 0;
5934 } else {
5935 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5936 }
5937
5938 alu.src[1].sel = tmp0;
5939 alu.src[1].chan = 1;
5940
5941 alu.last = 1;
5942 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5943 return r;
5944
5945 if (mod) { /* UMOD */
5946
5947 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5948 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5949 alu.op = ALU_OP2_SUB_INT;
5950
5951 alu.dst.sel = tmp1;
5952 alu.dst.chan = 2;
5953 alu.dst.write = 1;
5954
5955 alu.src[0].sel = tmp0;
5956 alu.src[0].chan = 3;
5957
5958 if (signed_op) {
5959 alu.src[1].sel = tmp2;
5960 alu.src[1].chan = 1;
5961 } else {
5962 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5963 }
5964
5965 alu.last = 1;
5966 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5967 return r;
5968
5969 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5970 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5971 alu.op = ALU_OP2_ADD_INT;
5972
5973 alu.dst.sel = tmp1;
5974 alu.dst.chan = 3;
5975 alu.dst.write = 1;
5976
5977 alu.src[0].sel = tmp0;
5978 alu.src[0].chan = 3;
5979 if (signed_op) {
5980 alu.src[1].sel = tmp2;
5981 alu.src[1].chan = 1;
5982 } else {
5983 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5984 }
5985
5986 alu.last = 1;
5987 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5988 return r;
5989
5990 } else { /* UDIV */
5991
5992 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5993 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5994 alu.op = ALU_OP2_ADD_INT;
5995
5996 alu.dst.sel = tmp1;
5997 alu.dst.chan = 2;
5998 alu.dst.write = 1;
5999
6000 alu.src[0].sel = tmp0;
6001 alu.src[0].chan = 2;
6002 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6003
6004 alu.last = 1;
6005 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6006 return r;
6007
6008 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
6009 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6010 alu.op = ALU_OP2_ADD_INT;
6011
6012 alu.dst.sel = tmp1;
6013 alu.dst.chan = 3;
6014 alu.dst.write = 1;
6015
6016 alu.src[0].sel = tmp0;
6017 alu.src[0].chan = 2;
6018 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
6019
6020 alu.last = 1;
6021 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6022 return r;
6023
6024 }
6025
6026 /* 17. tmp1.x = tmp1.x & tmp1.y */
6027 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6028 alu.op = ALU_OP2_AND_INT;
6029
6030 alu.dst.sel = tmp1;
6031 alu.dst.chan = 0;
6032 alu.dst.write = 1;
6033
6034 alu.src[0].sel = tmp1;
6035 alu.src[0].chan = 0;
6036 alu.src[1].sel = tmp1;
6037 alu.src[1].chan = 1;
6038
6039 alu.last = 1;
6040 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6041 return r;
6042
6043 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
6044 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
6045 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6046 alu.op = ALU_OP3_CNDE_INT;
6047 alu.is_op3 = 1;
6048
6049 alu.dst.sel = tmp0;
6050 alu.dst.chan = 2;
6051 alu.dst.write = 1;
6052
6053 alu.src[0].sel = tmp1;
6054 alu.src[0].chan = 0;
6055 alu.src[1].sel = tmp0;
6056 alu.src[1].chan = mod ? 3 : 2;
6057 alu.src[2].sel = tmp1;
6058 alu.src[2].chan = 2;
6059
6060 alu.last = 1;
6061 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6062 return r;
6063
6064 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
6065 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6066 alu.op = ALU_OP3_CNDE_INT;
6067 alu.is_op3 = 1;
6068
6069 if (signed_op) {
6070 alu.dst.sel = tmp0;
6071 alu.dst.chan = 2;
6072 alu.dst.write = 1;
6073 } else {
6074 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6075 }
6076
6077 alu.src[0].sel = tmp1;
6078 alu.src[0].chan = 1;
6079 alu.src[1].sel = tmp1;
6080 alu.src[1].chan = 3;
6081 alu.src[2].sel = tmp0;
6082 alu.src[2].chan = 2;
6083
6084 alu.last = 1;
6085 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6086 return r;
6087
6088 if (signed_op) {
6089
6090 /* fix the sign of the result */
6091
6092 if (mod) {
6093
6094 /* tmp0.x = -tmp0.z */
6095 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6096 alu.op = ALU_OP2_SUB_INT;
6097
6098 alu.dst.sel = tmp0;
6099 alu.dst.chan = 0;
6100 alu.dst.write = 1;
6101
6102 alu.src[0].sel = V_SQ_ALU_SRC_0;
6103 alu.src[1].sel = tmp0;
6104 alu.src[1].chan = 2;
6105
6106 alu.last = 1;
6107 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6108 return r;
6109
6110 /* sign of the remainder is the same as the sign of src0 */
6111 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
6112 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6113 alu.op = ALU_OP3_CNDGE_INT;
6114 alu.is_op3 = 1;
6115
6116 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6117
6118 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6119 alu.src[1].sel = tmp0;
6120 alu.src[1].chan = 2;
6121 alu.src[2].sel = tmp0;
6122 alu.src[2].chan = 0;
6123
6124 alu.last = 1;
6125 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6126 return r;
6127
6128 } else {
6129
6130 /* tmp0.x = -tmp0.z */
6131 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6132 alu.op = ALU_OP2_SUB_INT;
6133
6134 alu.dst.sel = tmp0;
6135 alu.dst.chan = 0;
6136 alu.dst.write = 1;
6137
6138 alu.src[0].sel = V_SQ_ALU_SRC_0;
6139 alu.src[1].sel = tmp0;
6140 alu.src[1].chan = 2;
6141
6142 alu.last = 1;
6143 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6144 return r;
6145
6146 /* fix the quotient sign (same as the sign of src0*src1) */
6147 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
6148 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6149 alu.op = ALU_OP3_CNDGE_INT;
6150 alu.is_op3 = 1;
6151
6152 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6153
6154 alu.src[0].sel = tmp2;
6155 alu.src[0].chan = 2;
6156 alu.src[1].sel = tmp0;
6157 alu.src[1].chan = 2;
6158 alu.src[2].sel = tmp0;
6159 alu.src[2].chan = 0;
6160
6161 alu.last = 1;
6162 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6163 return r;
6164 }
6165 }
6166 }
6167 return 0;
6168 }
6169
6170 static int tgsi_udiv(struct r600_shader_ctx *ctx)
6171 {
6172 return tgsi_divmod(ctx, 0, 0);
6173 }
6174
6175 static int tgsi_umod(struct r600_shader_ctx *ctx)
6176 {
6177 return tgsi_divmod(ctx, 1, 0);
6178 }
6179
6180 static int tgsi_idiv(struct r600_shader_ctx *ctx)
6181 {
6182 return tgsi_divmod(ctx, 0, 1);
6183 }
6184
6185 static int tgsi_imod(struct r600_shader_ctx *ctx)
6186 {
6187 return tgsi_divmod(ctx, 1, 1);
6188 }
6189
6190
6191 static int tgsi_f2i(struct r600_shader_ctx *ctx)
6192 {
6193 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6194 struct r600_bytecode_alu alu;
6195 int i, r;
6196 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6197 int last_inst = tgsi_last_instruction(write_mask);
6198
6199 for (i = 0; i < 4; i++) {
6200 if (!(write_mask & (1<<i)))
6201 continue;
6202
6203 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6204 alu.op = ALU_OP1_TRUNC;
6205
6206 alu.dst.sel = ctx->temp_reg;
6207 alu.dst.chan = i;
6208 alu.dst.write = 1;
6209
6210 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6211 if (i == last_inst)
6212 alu.last = 1;
6213 r = r600_bytecode_add_alu(ctx->bc, &alu);
6214 if (r)
6215 return r;
6216 }
6217
6218 for (i = 0; i < 4; i++) {
6219 if (!(write_mask & (1<<i)))
6220 continue;
6221
6222 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6223 alu.op = ctx->inst_info->op;
6224
6225 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6226
6227 alu.src[0].sel = ctx->temp_reg;
6228 alu.src[0].chan = i;
6229
6230 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
6231 alu.last = 1;
6232 r = r600_bytecode_add_alu(ctx->bc, &alu);
6233 if (r)
6234 return r;
6235 }
6236
6237 return 0;
6238 }
6239
6240 static int tgsi_iabs(struct r600_shader_ctx *ctx)
6241 {
6242 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6243 struct r600_bytecode_alu alu;
6244 int i, r;
6245 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6246 int last_inst = tgsi_last_instruction(write_mask);
6247
6248 /* tmp = -src */
6249 for (i = 0; i < 4; i++) {
6250 if (!(write_mask & (1<<i)))
6251 continue;
6252
6253 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6254 alu.op = ALU_OP2_SUB_INT;
6255
6256 alu.dst.sel = ctx->temp_reg;
6257 alu.dst.chan = i;
6258 alu.dst.write = 1;
6259
6260 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6261 alu.src[0].sel = V_SQ_ALU_SRC_0;
6262
6263 if (i == last_inst)
6264 alu.last = 1;
6265 r = r600_bytecode_add_alu(ctx->bc, &alu);
6266 if (r)
6267 return r;
6268 }
6269
6270 /* dst = (src >= 0 ? src : tmp) */
6271 for (i = 0; i < 4; i++) {
6272 if (!(write_mask & (1<<i)))
6273 continue;
6274
6275 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6276 alu.op = ALU_OP3_CNDGE_INT;
6277 alu.is_op3 = 1;
6278 alu.dst.write = 1;
6279
6280 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6281
6282 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6283 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6284 alu.src[2].sel = ctx->temp_reg;
6285 alu.src[2].chan = i;
6286
6287 if (i == last_inst)
6288 alu.last = 1;
6289 r = r600_bytecode_add_alu(ctx->bc, &alu);
6290 if (r)
6291 return r;
6292 }
6293 return 0;
6294 }
6295
6296 static int tgsi_issg(struct r600_shader_ctx *ctx)
6297 {
6298 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6299 struct r600_bytecode_alu alu;
6300 int i, r;
6301 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6302 int last_inst = tgsi_last_instruction(write_mask);
6303
6304 /* tmp = (src >= 0 ? src : -1) */
6305 for (i = 0; i < 4; i++) {
6306 if (!(write_mask & (1<<i)))
6307 continue;
6308
6309 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6310 alu.op = ALU_OP3_CNDGE_INT;
6311 alu.is_op3 = 1;
6312
6313 alu.dst.sel = ctx->temp_reg;
6314 alu.dst.chan = i;
6315 alu.dst.write = 1;
6316
6317 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6318 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6319 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6320
6321 if (i == last_inst)
6322 alu.last = 1;
6323 r = r600_bytecode_add_alu(ctx->bc, &alu);
6324 if (r)
6325 return r;
6326 }
6327
6328 /* dst = (tmp > 0 ? 1 : tmp) */
6329 for (i = 0; i < 4; i++) {
6330 if (!(write_mask & (1<<i)))
6331 continue;
6332
6333 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6334 alu.op = ALU_OP3_CNDGT_INT;
6335 alu.is_op3 = 1;
6336 alu.dst.write = 1;
6337
6338 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6339
6340 alu.src[0].sel = ctx->temp_reg;
6341 alu.src[0].chan = i;
6342
6343 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6344
6345 alu.src[2].sel = ctx->temp_reg;
6346 alu.src[2].chan = i;
6347
6348 if (i == last_inst)
6349 alu.last = 1;
6350 r = r600_bytecode_add_alu(ctx->bc, &alu);
6351 if (r)
6352 return r;
6353 }
6354 return 0;
6355 }
6356
6357
6358
6359 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6360 {
6361 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6362 struct r600_bytecode_alu alu;
6363 int i, r;
6364
6365 /* tmp = (src > 0 ? 1 : src) */
6366 for (i = 0; i < 4; i++) {
6367 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6368 alu.op = ALU_OP3_CNDGT;
6369 alu.is_op3 = 1;
6370
6371 alu.dst.sel = ctx->temp_reg;
6372 alu.dst.chan = i;
6373
6374 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6375 alu.src[1].sel = V_SQ_ALU_SRC_1;
6376 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6377
6378 if (i == 3)
6379 alu.last = 1;
6380 r = r600_bytecode_add_alu(ctx->bc, &alu);
6381 if (r)
6382 return r;
6383 }
6384
6385 /* dst = (-tmp > 0 ? -1 : tmp) */
6386 for (i = 0; i < 4; i++) {
6387 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6388 alu.op = ALU_OP3_CNDGT;
6389 alu.is_op3 = 1;
6390 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6391
6392 alu.src[0].sel = ctx->temp_reg;
6393 alu.src[0].chan = i;
6394 alu.src[0].neg = 1;
6395
6396 alu.src[1].sel = V_SQ_ALU_SRC_1;
6397 alu.src[1].neg = 1;
6398
6399 alu.src[2].sel = ctx->temp_reg;
6400 alu.src[2].chan = i;
6401
6402 if (i == 3)
6403 alu.last = 1;
6404 r = r600_bytecode_add_alu(ctx->bc, &alu);
6405 if (r)
6406 return r;
6407 }
6408 return 0;
6409 }
6410
6411 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6412 {
6413 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6414 struct r600_bytecode_alu alu;
6415 int i, r, t1, t2;
6416
6417 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6418 int last_inst = tgsi_last_instruction(write_mask);
6419
6420 t1 = r600_get_temp(ctx);
6421
6422 for (i = 0; i < 4; i++) {
6423 if (!(write_mask & (1<<i)))
6424 continue;
6425
6426 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6427 alu.op = ALU_OP2_SETGE_INT;
6428 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6429 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6430 alu.src[1].value = 32;
6431 alu.dst.sel = ctx->temp_reg;
6432 alu.dst.chan = i;
6433 alu.dst.write = 1;
6434 alu.last = i == last_inst;
6435 r = r600_bytecode_add_alu(ctx->bc, &alu);
6436 if (r)
6437 return r;
6438 }
6439
6440 for (i = 0; i < 4; i++) {
6441 if (!(write_mask & (1<<i)))
6442 continue;
6443
6444 /* create mask tmp */
6445 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6446 alu.op = ALU_OP2_BFM_INT;
6447 alu.dst.sel = t1;
6448 alu.dst.chan = i;
6449 alu.dst.write = 1;
6450 alu.last = i == last_inst;
6451
6452 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6453 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6454
6455 r = r600_bytecode_add_alu(ctx->bc, &alu);
6456 if (r)
6457 return r;
6458 }
6459
6460 t2 = r600_get_temp(ctx);
6461
6462 for (i = 0; i < 4; i++) {
6463 if (!(write_mask & (1<<i)))
6464 continue;
6465
6466 /* shift insert left */
6467 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6468 alu.op = ALU_OP2_LSHL_INT;
6469 alu.dst.sel = t2;
6470 alu.dst.chan = i;
6471 alu.dst.write = 1;
6472 alu.last = i == last_inst;
6473
6474 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6475 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6476
6477 r = r600_bytecode_add_alu(ctx->bc, &alu);
6478 if (r)
6479 return r;
6480 }
6481
6482 for (i = 0; i < 4; i++) {
6483 if (!(write_mask & (1<<i)))
6484 continue;
6485
6486 /* actual bitfield insert */
6487 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6488 alu.op = ALU_OP3_BFI_INT;
6489 alu.is_op3 = 1;
6490 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6491 alu.dst.chan = i;
6492 alu.dst.write = 1;
6493 alu.last = i == last_inst;
6494
6495 alu.src[0].sel = t1;
6496 alu.src[0].chan = i;
6497 alu.src[1].sel = t2;
6498 alu.src[1].chan = i;
6499 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6500
6501 r = r600_bytecode_add_alu(ctx->bc, &alu);
6502 if (r)
6503 return r;
6504 }
6505
6506 for (i = 0; i < 4; i++) {
6507 if (!(write_mask & (1<<i)))
6508 continue;
6509 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6510 alu.op = ALU_OP3_CNDE_INT;
6511 alu.is_op3 = 1;
6512 alu.src[0].sel = ctx->temp_reg;
6513 alu.src[0].chan = i;
6514 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6515
6516 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6517
6518 alu.src[1].sel = alu.dst.sel;
6519 alu.src[1].chan = i;
6520
6521 alu.last = i == last_inst;
6522 r = r600_bytecode_add_alu(ctx->bc, &alu);
6523 if (r)
6524 return r;
6525 }
6526 return 0;
6527 }
6528
6529 static int tgsi_msb(struct r600_shader_ctx *ctx)
6530 {
6531 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6532 struct r600_bytecode_alu alu;
6533 int i, r, t1, t2;
6534
6535 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6536 int last_inst = tgsi_last_instruction(write_mask);
6537
6538 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6539 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6540
6541 t1 = ctx->temp_reg;
6542
6543 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6544 for (i = 0; i < 4; i++) {
6545 if (!(write_mask & (1<<i)))
6546 continue;
6547
6548 /* t1 = FFBH_INT / FFBH_UINT */
6549 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6550 alu.op = ctx->inst_info->op;
6551 alu.dst.sel = t1;
6552 alu.dst.chan = i;
6553 alu.dst.write = 1;
6554 alu.last = i == last_inst;
6555
6556 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6557
6558 r = r600_bytecode_add_alu(ctx->bc, &alu);
6559 if (r)
6560 return r;
6561 }
6562
6563 t2 = r600_get_temp(ctx);
6564
6565 for (i = 0; i < 4; i++) {
6566 if (!(write_mask & (1<<i)))
6567 continue;
6568
6569 /* t2 = 31 - t1 */
6570 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6571 alu.op = ALU_OP2_SUB_INT;
6572 alu.dst.sel = t2;
6573 alu.dst.chan = i;
6574 alu.dst.write = 1;
6575 alu.last = i == last_inst;
6576
6577 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6578 alu.src[0].value = 31;
6579 alu.src[1].sel = t1;
6580 alu.src[1].chan = i;
6581
6582 r = r600_bytecode_add_alu(ctx->bc, &alu);
6583 if (r)
6584 return r;
6585 }
6586
6587 for (i = 0; i < 4; i++) {
6588 if (!(write_mask & (1<<i)))
6589 continue;
6590
6591 /* result = t1 >= 0 ? t2 : t1 */
6592 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6593 alu.op = ALU_OP3_CNDGE_INT;
6594 alu.is_op3 = 1;
6595 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6596 alu.dst.chan = i;
6597 alu.dst.write = 1;
6598 alu.last = i == last_inst;
6599
6600 alu.src[0].sel = t1;
6601 alu.src[0].chan = i;
6602 alu.src[1].sel = t2;
6603 alu.src[1].chan = i;
6604 alu.src[2].sel = t1;
6605 alu.src[2].chan = i;
6606
6607 r = r600_bytecode_add_alu(ctx->bc, &alu);
6608 if (r)
6609 return r;
6610 }
6611
6612 return 0;
6613 }
6614
6615 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6616 {
6617 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6618 struct r600_bytecode_alu alu;
6619 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6620 unsigned location;
6621 const int input = inst->Src[0].Register.Index + ctx->shader->nsys_inputs;
6622
6623 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6624
6625 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6626 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6627 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6628 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6629 }
6630 else {
6631 location = TGSI_INTERPOLATE_LOC_CENTROID;
6632 }
6633
6634 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6635 if (k < 0)
6636 k = 0;
6637 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6638 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6639
6640 /* NOTE: currently offset is not perspective correct */
6641 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6642 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6643 int sample_gpr = -1;
6644 int gradientsH, gradientsV;
6645 struct r600_bytecode_tex tex;
6646
6647 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6648 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6649 }
6650
6651 gradientsH = r600_get_temp(ctx);
6652 gradientsV = r600_get_temp(ctx);
6653 for (i = 0; i < 2; i++) {
6654 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6655 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6656 tex.src_gpr = interp_gpr;
6657 tex.src_sel_x = interp_base_chan + 0;
6658 tex.src_sel_y = interp_base_chan + 1;
6659 tex.src_sel_z = 0;
6660 tex.src_sel_w = 0;
6661 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6662 tex.dst_sel_x = 0;
6663 tex.dst_sel_y = 1;
6664 tex.dst_sel_z = 7;
6665 tex.dst_sel_w = 7;
6666 tex.inst_mod = 1; // Use per pixel gradient calculation
6667 tex.sampler_id = 0;
6668 tex.resource_id = tex.sampler_id;
6669 r = r600_bytecode_add_tex(ctx->bc, &tex);
6670 if (r)
6671 return r;
6672 }
6673
6674 for (i = 0; i < 2; i++) {
6675 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6676 alu.op = ALU_OP3_MULADD;
6677 alu.is_op3 = 1;
6678 alu.src[0].sel = gradientsH;
6679 alu.src[0].chan = i;
6680 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6681 alu.src[1].sel = sample_gpr;
6682 alu.src[1].chan = 2;
6683 }
6684 else {
6685 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6686 }
6687 alu.src[2].sel = interp_gpr;
6688 alu.src[2].chan = interp_base_chan + i;
6689 alu.dst.sel = ctx->temp_reg;
6690 alu.dst.chan = i;
6691 alu.last = i == 1;
6692
6693 r = r600_bytecode_add_alu(ctx->bc, &alu);
6694 if (r)
6695 return r;
6696 }
6697
6698 for (i = 0; i < 2; i++) {
6699 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6700 alu.op = ALU_OP3_MULADD;
6701 alu.is_op3 = 1;
6702 alu.src[0].sel = gradientsV;
6703 alu.src[0].chan = i;
6704 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6705 alu.src[1].sel = sample_gpr;
6706 alu.src[1].chan = 3;
6707 }
6708 else {
6709 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6710 }
6711 alu.src[2].sel = ctx->temp_reg;
6712 alu.src[2].chan = i;
6713 alu.dst.sel = ctx->temp_reg;
6714 alu.dst.chan = i;
6715 alu.last = i == 1;
6716
6717 r = r600_bytecode_add_alu(ctx->bc, &alu);
6718 if (r)
6719 return r;
6720 }
6721 }
6722
6723 tmp = r600_get_temp(ctx);
6724 for (i = 0; i < 8; i++) {
6725 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6726 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6727
6728 alu.dst.sel = tmp;
6729 if ((i > 1 && i < 6)) {
6730 alu.dst.write = 1;
6731 }
6732 else {
6733 alu.dst.write = 0;
6734 }
6735 alu.dst.chan = i % 4;
6736
6737 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6738 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6739 alu.src[0].sel = ctx->temp_reg;
6740 alu.src[0].chan = 1 - (i % 2);
6741 } else {
6742 alu.src[0].sel = interp_gpr;
6743 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
6744 }
6745 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
6746 alu.src[1].chan = 0;
6747
6748 alu.last = i % 4 == 3;
6749 alu.bank_swizzle_force = SQ_ALU_VEC_210;
6750
6751 r = r600_bytecode_add_alu(ctx->bc, &alu);
6752 if (r)
6753 return r;
6754 }
6755
6756 // INTERP can't swizzle dst
6757 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6758 for (i = 0; i <= lasti; i++) {
6759 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6760 continue;
6761
6762 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6763 alu.op = ALU_OP1_MOV;
6764 alu.src[0].sel = tmp;
6765 alu.src[0].chan = ctx->src[0].swizzle[i];
6766 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6767 alu.dst.write = 1;
6768 alu.last = i == lasti;
6769 r = r600_bytecode_add_alu(ctx->bc, &alu);
6770 if (r)
6771 return r;
6772 }
6773
6774 return 0;
6775 }
6776
6777
6778 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
6779 {
6780 struct r600_bytecode_alu alu;
6781 int i, r;
6782
6783 for (i = 0; i < 4; i++) {
6784 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6785 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
6786 alu.op = ALU_OP0_NOP;
6787 alu.dst.chan = i;
6788 } else {
6789 alu.op = ALU_OP1_MOV;
6790 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6791 alu.src[0].sel = ctx->temp_reg;
6792 alu.src[0].chan = i;
6793 }
6794 if (i == 3) {
6795 alu.last = 1;
6796 }
6797 r = r600_bytecode_add_alu(ctx->bc, &alu);
6798 if (r)
6799 return r;
6800 }
6801 return 0;
6802 }
6803
6804 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
6805 unsigned temp, int chan,
6806 struct r600_bytecode_alu_src *bc_src,
6807 const struct r600_shader_src *shader_src)
6808 {
6809 struct r600_bytecode_alu alu;
6810 int r;
6811
6812 r600_bytecode_src(bc_src, shader_src, chan);
6813
6814 /* op3 operands don't support abs modifier */
6815 if (bc_src->abs) {
6816 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
6817 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6818 alu.op = ALU_OP1_MOV;
6819 alu.dst.sel = temp;
6820 alu.dst.chan = chan;
6821 alu.dst.write = 1;
6822
6823 alu.src[0] = *bc_src;
6824 alu.last = true; // sufficient?
6825 r = r600_bytecode_add_alu(ctx->bc, &alu);
6826 if (r)
6827 return r;
6828
6829 memset(bc_src, 0, sizeof(*bc_src));
6830 bc_src->sel = temp;
6831 bc_src->chan = chan;
6832 }
6833 return 0;
6834 }
6835
6836 static int tgsi_op3_dst(struct r600_shader_ctx *ctx, int dst)
6837 {
6838 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6839 struct r600_bytecode_alu alu;
6840 int i, j, r;
6841 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6842 int temp_regs[4];
6843 unsigned op = ctx->inst_info->op;
6844
6845 if (op == ALU_OP3_MULADD_IEEE &&
6846 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6847 op = ALU_OP3_MULADD;
6848
6849 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6850 temp_regs[j] = 0;
6851 if (ctx->src[j].abs)
6852 temp_regs[j] = r600_get_temp(ctx);
6853 }
6854 for (i = 0; i < lasti + 1; i++) {
6855 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6856 continue;
6857
6858 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6859 alu.op = op;
6860 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6861 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
6862 if (r)
6863 return r;
6864 }
6865
6866 if (dst == -1) {
6867 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6868 } else {
6869 alu.dst.sel = dst;
6870 }
6871 alu.dst.chan = i;
6872 alu.dst.write = 1;
6873 alu.is_op3 = 1;
6874 if (i == lasti) {
6875 alu.last = 1;
6876 }
6877 r = r600_bytecode_add_alu(ctx->bc, &alu);
6878 if (r)
6879 return r;
6880 }
6881 return 0;
6882 }
6883
6884 static int tgsi_op3(struct r600_shader_ctx *ctx)
6885 {
6886 return tgsi_op3_dst(ctx, -1);
6887 }
6888
6889 static int tgsi_dp(struct r600_shader_ctx *ctx)
6890 {
6891 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6892 struct r600_bytecode_alu alu;
6893 int i, j, r;
6894 unsigned op = ctx->inst_info->op;
6895 if (op == ALU_OP2_DOT4_IEEE &&
6896 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6897 op = ALU_OP2_DOT4;
6898
6899 for (i = 0; i < 4; i++) {
6900 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6901 alu.op = op;
6902 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6903 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6904 }
6905
6906 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6907 alu.dst.chan = i;
6908 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
6909 /* handle some special cases */
6910 switch (inst->Instruction.Opcode) {
6911 case TGSI_OPCODE_DP2:
6912 if (i > 1) {
6913 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6914 alu.src[0].chan = alu.src[1].chan = 0;
6915 }
6916 break;
6917 case TGSI_OPCODE_DP3:
6918 if (i > 2) {
6919 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6920 alu.src[0].chan = alu.src[1].chan = 0;
6921 }
6922 break;
6923 default:
6924 break;
6925 }
6926 if (i == 3) {
6927 alu.last = 1;
6928 }
6929 r = r600_bytecode_add_alu(ctx->bc, &alu);
6930 if (r)
6931 return r;
6932 }
6933 return 0;
6934 }
6935
6936 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
6937 unsigned index)
6938 {
6939 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6940 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
6941 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
6942 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
6943 ctx->src[index].neg || ctx->src[index].abs ||
6944 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
6945 }
6946
6947 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
6948 unsigned index)
6949 {
6950 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6951 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
6952 }
6953
6954 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
6955 {
6956 struct r600_bytecode_vtx vtx;
6957 struct r600_bytecode_alu alu;
6958 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6959 int src_gpr, r, i;
6960 int id = tgsi_tex_get_src_gpr(ctx, 1);
6961 int sampler_index_mode = inst->Src[1].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6962
6963 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6964 if (src_requires_loading) {
6965 for (i = 0; i < 4; i++) {
6966 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6967 alu.op = ALU_OP1_MOV;
6968 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6969 alu.dst.sel = ctx->temp_reg;
6970 alu.dst.chan = i;
6971 if (i == 3)
6972 alu.last = 1;
6973 alu.dst.write = 1;
6974 r = r600_bytecode_add_alu(ctx->bc, &alu);
6975 if (r)
6976 return r;
6977 }
6978 src_gpr = ctx->temp_reg;
6979 }
6980
6981 memset(&vtx, 0, sizeof(vtx));
6982 vtx.op = FETCH_OP_VFETCH;
6983 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6984 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6985 vtx.src_gpr = src_gpr;
6986 vtx.mega_fetch_count = 16;
6987 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6988 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6989 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
6990 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
6991 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
6992 vtx.use_const_fields = 1;
6993 vtx.buffer_index_mode = sampler_index_mode;
6994
6995 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
6996 return r;
6997
6998 if (ctx->bc->chip_class >= EVERGREEN)
6999 return 0;
7000
7001 for (i = 0; i < 4; i++) {
7002 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7003 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7004 continue;
7005
7006 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7007 alu.op = ALU_OP2_AND_INT;
7008
7009 alu.dst.chan = i;
7010 alu.dst.sel = vtx.dst_gpr;
7011 alu.dst.write = 1;
7012
7013 alu.src[0].sel = vtx.dst_gpr;
7014 alu.src[0].chan = i;
7015
7016 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
7017 alu.src[1].sel += (id * 2);
7018 alu.src[1].chan = i % 4;
7019 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7020
7021 if (i == lasti)
7022 alu.last = 1;
7023 r = r600_bytecode_add_alu(ctx->bc, &alu);
7024 if (r)
7025 return r;
7026 }
7027
7028 if (inst->Dst[0].Register.WriteMask & 3) {
7029 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7030 alu.op = ALU_OP2_OR_INT;
7031
7032 alu.dst.chan = 3;
7033 alu.dst.sel = vtx.dst_gpr;
7034 alu.dst.write = 1;
7035
7036 alu.src[0].sel = vtx.dst_gpr;
7037 alu.src[0].chan = 3;
7038
7039 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
7040 alu.src[1].chan = 0;
7041 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7042
7043 alu.last = 1;
7044 r = r600_bytecode_add_alu(ctx->bc, &alu);
7045 if (r)
7046 return r;
7047 }
7048 return 0;
7049 }
7050
7051 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx, int reg_idx, int offset, int eg_buffer_base)
7052 {
7053 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7054 int r;
7055 int id = tgsi_tex_get_src_gpr(ctx, reg_idx) + offset;
7056 int sampler_index_mode = inst->Src[reg_idx].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7057
7058 if (ctx->bc->chip_class < EVERGREEN) {
7059 struct r600_bytecode_alu alu;
7060 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7061 alu.op = ALU_OP1_MOV;
7062 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7063 /* r600 we have them at channel 2 of the second dword */
7064 alu.src[0].sel += (id * 2) + 1;
7065 alu.src[0].chan = 1;
7066 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7067 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
7068 alu.last = 1;
7069 r = r600_bytecode_add_alu(ctx->bc, &alu);
7070 if (r)
7071 return r;
7072 return 0;
7073 } else {
7074 struct r600_bytecode_vtx vtx;
7075 memset(&vtx, 0, sizeof(vtx));
7076 vtx.op = FETCH_OP_GET_BUFFER_RESINFO;
7077 vtx.buffer_id = id + eg_buffer_base;
7078 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
7079 vtx.src_gpr = 0;
7080 vtx.mega_fetch_count = 16; /* no idea here really... */
7081 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7082 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
7083 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 4 : 7; /* SEL_Y */
7084 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 4 : 7; /* SEL_Z */
7085 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 4 : 7; /* SEL_W */
7086 vtx.data_format = FMT_32_32_32_32;
7087 vtx.buffer_index_mode = sampler_index_mode;
7088
7089 if ((r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx)))
7090 return r;
7091 return 0;
7092 }
7093 }
7094
7095
7096 static int tgsi_tex(struct r600_shader_ctx *ctx)
7097 {
7098 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7099 struct r600_bytecode_tex tex;
7100 struct r600_bytecode_alu alu;
7101 unsigned src_gpr;
7102 int r, i, j;
7103 int opcode;
7104 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
7105 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
7106 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
7107 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
7108
7109 bool txf_add_offsets = inst->Texture.NumOffsets &&
7110 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
7111 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
7112
7113 /* Texture fetch instructions can only use gprs as source.
7114 * Also they cannot negate the source or take the absolute value */
7115 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
7116 tgsi_tex_src_requires_loading(ctx, 0)) ||
7117 read_compressed_msaa || txf_add_offsets;
7118
7119 boolean src_loaded = FALSE;
7120 unsigned sampler_src_reg = 1;
7121 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
7122 boolean has_txq_cube_array_z = false;
7123 unsigned sampler_index_mode;
7124
7125 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
7126 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7127 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
7128 if (inst->Dst[0].Register.WriteMask & 4) {
7129 ctx->shader->has_txq_cube_array_z_comp = true;
7130 has_txq_cube_array_z = true;
7131 }
7132
7133 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
7134 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7135 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
7136 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
7137 sampler_src_reg = 2;
7138
7139 /* TGSI moves the sampler to src reg 3 for TXD */
7140 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
7141 sampler_src_reg = 3;
7142
7143 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7144
7145 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
7146
7147 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
7148 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
7149 if (ctx->bc->chip_class < EVERGREEN)
7150 ctx->shader->uses_tex_buffers = true;
7151 return r600_do_buffer_txq(ctx, 1, 0, R600_MAX_CONST_BUFFERS);
7152 }
7153 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
7154 if (ctx->bc->chip_class < EVERGREEN)
7155 ctx->shader->uses_tex_buffers = true;
7156 return do_vtx_fetch_inst(ctx, src_requires_loading);
7157 }
7158 }
7159
7160 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
7161 int out_chan;
7162 /* Add perspective divide */
7163 if (ctx->bc->chip_class == CAYMAN) {
7164 out_chan = 2;
7165 for (i = 0; i < 3; i++) {
7166 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7167 alu.op = ALU_OP1_RECIP_IEEE;
7168 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7169
7170 alu.dst.sel = ctx->temp_reg;
7171 alu.dst.chan = i;
7172 if (i == 2)
7173 alu.last = 1;
7174 if (out_chan == i)
7175 alu.dst.write = 1;
7176 r = r600_bytecode_add_alu(ctx->bc, &alu);
7177 if (r)
7178 return r;
7179 }
7180
7181 } else {
7182 out_chan = 3;
7183 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7184 alu.op = ALU_OP1_RECIP_IEEE;
7185 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7186
7187 alu.dst.sel = ctx->temp_reg;
7188 alu.dst.chan = out_chan;
7189 alu.last = 1;
7190 alu.dst.write = 1;
7191 r = r600_bytecode_add_alu(ctx->bc, &alu);
7192 if (r)
7193 return r;
7194 }
7195
7196 for (i = 0; i < 3; i++) {
7197 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7198 alu.op = ALU_OP2_MUL;
7199 alu.src[0].sel = ctx->temp_reg;
7200 alu.src[0].chan = out_chan;
7201 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
7202 alu.dst.sel = ctx->temp_reg;
7203 alu.dst.chan = i;
7204 alu.dst.write = 1;
7205 r = r600_bytecode_add_alu(ctx->bc, &alu);
7206 if (r)
7207 return r;
7208 }
7209 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7210 alu.op = ALU_OP1_MOV;
7211 alu.src[0].sel = V_SQ_ALU_SRC_1;
7212 alu.src[0].chan = 0;
7213 alu.dst.sel = ctx->temp_reg;
7214 alu.dst.chan = 3;
7215 alu.last = 1;
7216 alu.dst.write = 1;
7217 r = r600_bytecode_add_alu(ctx->bc, &alu);
7218 if (r)
7219 return r;
7220 src_loaded = TRUE;
7221 src_gpr = ctx->temp_reg;
7222 }
7223
7224
7225 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7226 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7227 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7228 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7229 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
7230
7231 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
7232 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
7233
7234 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
7235 for (i = 0; i < 4; i++) {
7236 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7237 alu.op = ALU_OP2_CUBE;
7238 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
7239 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
7240 alu.dst.sel = ctx->temp_reg;
7241 alu.dst.chan = i;
7242 if (i == 3)
7243 alu.last = 1;
7244 alu.dst.write = 1;
7245 r = r600_bytecode_add_alu(ctx->bc, &alu);
7246 if (r)
7247 return r;
7248 }
7249
7250 /* tmp1.z = RCP_e(|tmp1.z|) */
7251 if (ctx->bc->chip_class == CAYMAN) {
7252 for (i = 0; i < 3; i++) {
7253 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7254 alu.op = ALU_OP1_RECIP_IEEE;
7255 alu.src[0].sel = ctx->temp_reg;
7256 alu.src[0].chan = 2;
7257 alu.src[0].abs = 1;
7258 alu.dst.sel = ctx->temp_reg;
7259 alu.dst.chan = i;
7260 if (i == 2)
7261 alu.dst.write = 1;
7262 if (i == 2)
7263 alu.last = 1;
7264 r = r600_bytecode_add_alu(ctx->bc, &alu);
7265 if (r)
7266 return r;
7267 }
7268 } else {
7269 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7270 alu.op = ALU_OP1_RECIP_IEEE;
7271 alu.src[0].sel = ctx->temp_reg;
7272 alu.src[0].chan = 2;
7273 alu.src[0].abs = 1;
7274 alu.dst.sel = ctx->temp_reg;
7275 alu.dst.chan = 2;
7276 alu.dst.write = 1;
7277 alu.last = 1;
7278 r = r600_bytecode_add_alu(ctx->bc, &alu);
7279 if (r)
7280 return r;
7281 }
7282
7283 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
7284 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
7285 * muladd has no writemask, have to use another temp
7286 */
7287 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7288 alu.op = ALU_OP3_MULADD;
7289 alu.is_op3 = 1;
7290
7291 alu.src[0].sel = ctx->temp_reg;
7292 alu.src[0].chan = 0;
7293 alu.src[1].sel = ctx->temp_reg;
7294 alu.src[1].chan = 2;
7295
7296 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7297 alu.src[2].chan = 0;
7298 alu.src[2].value = u_bitcast_f2u(1.5f);
7299
7300 alu.dst.sel = ctx->temp_reg;
7301 alu.dst.chan = 0;
7302 alu.dst.write = 1;
7303
7304 r = r600_bytecode_add_alu(ctx->bc, &alu);
7305 if (r)
7306 return r;
7307
7308 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7309 alu.op = ALU_OP3_MULADD;
7310 alu.is_op3 = 1;
7311
7312 alu.src[0].sel = ctx->temp_reg;
7313 alu.src[0].chan = 1;
7314 alu.src[1].sel = ctx->temp_reg;
7315 alu.src[1].chan = 2;
7316
7317 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7318 alu.src[2].chan = 0;
7319 alu.src[2].value = u_bitcast_f2u(1.5f);
7320
7321 alu.dst.sel = ctx->temp_reg;
7322 alu.dst.chan = 1;
7323 alu.dst.write = 1;
7324
7325 alu.last = 1;
7326 r = r600_bytecode_add_alu(ctx->bc, &alu);
7327 if (r)
7328 return r;
7329 /* write initial compare value into Z component
7330 - W src 0 for shadow cube
7331 - X src 1 for shadow cube array */
7332 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7333 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7334 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7335 alu.op = ALU_OP1_MOV;
7336 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
7337 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7338 else
7339 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7340 alu.dst.sel = ctx->temp_reg;
7341 alu.dst.chan = 2;
7342 alu.dst.write = 1;
7343 alu.last = 1;
7344 r = r600_bytecode_add_alu(ctx->bc, &alu);
7345 if (r)
7346 return r;
7347 }
7348
7349 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7350 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7351 if (ctx->bc->chip_class >= EVERGREEN) {
7352 int mytmp = r600_get_temp(ctx);
7353 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7354 alu.op = ALU_OP1_MOV;
7355 alu.src[0].sel = ctx->temp_reg;
7356 alu.src[0].chan = 3;
7357 alu.dst.sel = mytmp;
7358 alu.dst.chan = 0;
7359 alu.dst.write = 1;
7360 alu.last = 1;
7361 r = r600_bytecode_add_alu(ctx->bc, &alu);
7362 if (r)
7363 return r;
7364
7365 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7366 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7367 alu.op = ALU_OP3_MULADD;
7368 alu.is_op3 = 1;
7369 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7370 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7371 alu.src[1].chan = 0;
7372 alu.src[1].value = u_bitcast_f2u(8.0f);
7373 alu.src[2].sel = mytmp;
7374 alu.src[2].chan = 0;
7375 alu.dst.sel = ctx->temp_reg;
7376 alu.dst.chan = 3;
7377 alu.dst.write = 1;
7378 alu.last = 1;
7379 r = r600_bytecode_add_alu(ctx->bc, &alu);
7380 if (r)
7381 return r;
7382 } else if (ctx->bc->chip_class < EVERGREEN) {
7383 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7384 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7385 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7386 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7387 tex.src_gpr = r600_get_temp(ctx);
7388 tex.src_sel_x = 0;
7389 tex.src_sel_y = 0;
7390 tex.src_sel_z = 0;
7391 tex.src_sel_w = 0;
7392 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7393 tex.coord_type_x = 1;
7394 tex.coord_type_y = 1;
7395 tex.coord_type_z = 1;
7396 tex.coord_type_w = 1;
7397 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7398 alu.op = ALU_OP1_MOV;
7399 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7400 alu.dst.sel = tex.src_gpr;
7401 alu.dst.chan = 0;
7402 alu.last = 1;
7403 alu.dst.write = 1;
7404 r = r600_bytecode_add_alu(ctx->bc, &alu);
7405 if (r)
7406 return r;
7407
7408 r = r600_bytecode_add_tex(ctx->bc, &tex);
7409 if (r)
7410 return r;
7411 }
7412
7413 }
7414
7415 /* for cube forms of lod and bias we need to route things */
7416 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7417 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7418 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7419 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7420 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7421 alu.op = ALU_OP1_MOV;
7422 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7423 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7424 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7425 else
7426 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7427 alu.dst.sel = ctx->temp_reg;
7428 alu.dst.chan = 2;
7429 alu.last = 1;
7430 alu.dst.write = 1;
7431 r = r600_bytecode_add_alu(ctx->bc, &alu);
7432 if (r)
7433 return r;
7434 }
7435
7436 src_loaded = TRUE;
7437 src_gpr = ctx->temp_reg;
7438 }
7439
7440 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7441 int temp_h = 0, temp_v = 0;
7442 int start_val = 0;
7443
7444 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7445 if (src_loaded == TRUE)
7446 start_val = 1;
7447 else
7448 src_loaded = TRUE;
7449 for (i = start_val; i < 3; i++) {
7450 int treg = r600_get_temp(ctx);
7451
7452 if (i == 0)
7453 src_gpr = treg;
7454 else if (i == 1)
7455 temp_h = treg;
7456 else
7457 temp_v = treg;
7458
7459 for (j = 0; j < 4; j++) {
7460 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7461 alu.op = ALU_OP1_MOV;
7462 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7463 alu.dst.sel = treg;
7464 alu.dst.chan = j;
7465 if (j == 3)
7466 alu.last = 1;
7467 alu.dst.write = 1;
7468 r = r600_bytecode_add_alu(ctx->bc, &alu);
7469 if (r)
7470 return r;
7471 }
7472 }
7473 for (i = 1; i < 3; i++) {
7474 /* set gradients h/v */
7475 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7476 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7477 FETCH_OP_SET_GRADIENTS_V;
7478 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7479 tex.sampler_index_mode = sampler_index_mode;
7480 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7481 tex.resource_index_mode = sampler_index_mode;
7482
7483 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7484 tex.src_sel_x = 0;
7485 tex.src_sel_y = 1;
7486 tex.src_sel_z = 2;
7487 tex.src_sel_w = 3;
7488
7489 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7490 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7491 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7492 tex.coord_type_x = 1;
7493 tex.coord_type_y = 1;
7494 tex.coord_type_z = 1;
7495 tex.coord_type_w = 1;
7496 }
7497 r = r600_bytecode_add_tex(ctx->bc, &tex);
7498 if (r)
7499 return r;
7500 }
7501 }
7502
7503 if (src_requires_loading && !src_loaded) {
7504 for (i = 0; i < 4; i++) {
7505 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7506 alu.op = ALU_OP1_MOV;
7507 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7508 alu.dst.sel = ctx->temp_reg;
7509 alu.dst.chan = i;
7510 if (i == 3)
7511 alu.last = 1;
7512 alu.dst.write = 1;
7513 r = r600_bytecode_add_alu(ctx->bc, &alu);
7514 if (r)
7515 return r;
7516 }
7517 src_loaded = TRUE;
7518 src_gpr = ctx->temp_reg;
7519 }
7520
7521 /* get offset values */
7522 if (inst->Texture.NumOffsets) {
7523 assert(inst->Texture.NumOffsets == 1);
7524
7525 /* The texture offset feature doesn't work with the TXF instruction
7526 * and must be emulated by adding the offset to the texture coordinates. */
7527 if (txf_add_offsets) {
7528 const struct tgsi_texture_offset *off = inst->TexOffsets;
7529
7530 switch (inst->Texture.Texture) {
7531 case TGSI_TEXTURE_3D:
7532 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7533 alu.op = ALU_OP2_ADD_INT;
7534 alu.src[0].sel = src_gpr;
7535 alu.src[0].chan = 2;
7536 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7537 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7538 alu.dst.sel = src_gpr;
7539 alu.dst.chan = 2;
7540 alu.dst.write = 1;
7541 alu.last = 1;
7542 r = r600_bytecode_add_alu(ctx->bc, &alu);
7543 if (r)
7544 return r;
7545 /* fall through */
7546
7547 case TGSI_TEXTURE_2D:
7548 case TGSI_TEXTURE_SHADOW2D:
7549 case TGSI_TEXTURE_RECT:
7550 case TGSI_TEXTURE_SHADOWRECT:
7551 case TGSI_TEXTURE_2D_ARRAY:
7552 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7553 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7554 alu.op = ALU_OP2_ADD_INT;
7555 alu.src[0].sel = src_gpr;
7556 alu.src[0].chan = 1;
7557 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7558 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7559 alu.dst.sel = src_gpr;
7560 alu.dst.chan = 1;
7561 alu.dst.write = 1;
7562 alu.last = 1;
7563 r = r600_bytecode_add_alu(ctx->bc, &alu);
7564 if (r)
7565 return r;
7566 /* fall through */
7567
7568 case TGSI_TEXTURE_1D:
7569 case TGSI_TEXTURE_SHADOW1D:
7570 case TGSI_TEXTURE_1D_ARRAY:
7571 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7572 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7573 alu.op = ALU_OP2_ADD_INT;
7574 alu.src[0].sel = src_gpr;
7575 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7576 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
7577 alu.dst.sel = src_gpr;
7578 alu.dst.write = 1;
7579 alu.last = 1;
7580 r = r600_bytecode_add_alu(ctx->bc, &alu);
7581 if (r)
7582 return r;
7583 break;
7584 /* texture offsets do not apply to other texture targets */
7585 }
7586 } else {
7587 switch (inst->Texture.Texture) {
7588 case TGSI_TEXTURE_3D:
7589 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
7590 /* fallthrough */
7591 case TGSI_TEXTURE_2D:
7592 case TGSI_TEXTURE_SHADOW2D:
7593 case TGSI_TEXTURE_RECT:
7594 case TGSI_TEXTURE_SHADOWRECT:
7595 case TGSI_TEXTURE_2D_ARRAY:
7596 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7597 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
7598 /* fallthrough */
7599 case TGSI_TEXTURE_1D:
7600 case TGSI_TEXTURE_SHADOW1D:
7601 case TGSI_TEXTURE_1D_ARRAY:
7602 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7603 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
7604 }
7605 }
7606 }
7607
7608 /* Obtain the sample index for reading a compressed MSAA color texture.
7609 * To read the FMASK, we use the ldfptr instruction, which tells us
7610 * where the samples are stored.
7611 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7612 * which is the identity mapping. Each nibble says which physical sample
7613 * should be fetched to get that sample.
7614 *
7615 * Assume src.z contains the sample index. It should be modified like this:
7616 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7617 * Then fetch the texel with src.
7618 */
7619 if (read_compressed_msaa) {
7620 unsigned sample_chan = 3;
7621 unsigned temp = r600_get_temp(ctx);
7622 assert(src_loaded);
7623
7624 /* temp.w = ldfptr() */
7625 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7626 tex.op = FETCH_OP_LD;
7627 tex.inst_mod = 1; /* to indicate this is ldfptr */
7628 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7629 tex.sampler_index_mode = sampler_index_mode;
7630 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7631 tex.resource_index_mode = sampler_index_mode;
7632 tex.src_gpr = src_gpr;
7633 tex.dst_gpr = temp;
7634 tex.dst_sel_x = 7; /* mask out these components */
7635 tex.dst_sel_y = 7;
7636 tex.dst_sel_z = 7;
7637 tex.dst_sel_w = 0; /* store X */
7638 tex.src_sel_x = 0;
7639 tex.src_sel_y = 1;
7640 tex.src_sel_z = 2;
7641 tex.src_sel_w = 3;
7642 tex.offset_x = offset_x;
7643 tex.offset_y = offset_y;
7644 tex.offset_z = offset_z;
7645 r = r600_bytecode_add_tex(ctx->bc, &tex);
7646 if (r)
7647 return r;
7648
7649 /* temp.x = sample_index*4 */
7650 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7651 alu.op = ALU_OP2_MULLO_INT;
7652 alu.src[0].sel = src_gpr;
7653 alu.src[0].chan = sample_chan;
7654 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7655 alu.src[1].value = 4;
7656 alu.dst.sel = temp;
7657 alu.dst.chan = 0;
7658 alu.dst.write = 1;
7659 r = emit_mul_int_op(ctx->bc, &alu);
7660 if (r)
7661 return r;
7662
7663 /* sample_index = temp.w >> temp.x */
7664 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7665 alu.op = ALU_OP2_LSHR_INT;
7666 alu.src[0].sel = temp;
7667 alu.src[0].chan = 3;
7668 alu.src[1].sel = temp;
7669 alu.src[1].chan = 0;
7670 alu.dst.sel = src_gpr;
7671 alu.dst.chan = sample_chan;
7672 alu.dst.write = 1;
7673 alu.last = 1;
7674 r = r600_bytecode_add_alu(ctx->bc, &alu);
7675 if (r)
7676 return r;
7677
7678 /* sample_index & 0xF */
7679 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7680 alu.op = ALU_OP2_AND_INT;
7681 alu.src[0].sel = src_gpr;
7682 alu.src[0].chan = sample_chan;
7683 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7684 alu.src[1].value = 0xF;
7685 alu.dst.sel = src_gpr;
7686 alu.dst.chan = sample_chan;
7687 alu.dst.write = 1;
7688 alu.last = 1;
7689 r = r600_bytecode_add_alu(ctx->bc, &alu);
7690 if (r)
7691 return r;
7692 #if 0
7693 /* visualize the FMASK */
7694 for (i = 0; i < 4; i++) {
7695 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7696 alu.op = ALU_OP1_INT_TO_FLT;
7697 alu.src[0].sel = src_gpr;
7698 alu.src[0].chan = sample_chan;
7699 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7700 alu.dst.chan = i;
7701 alu.dst.write = 1;
7702 alu.last = 1;
7703 r = r600_bytecode_add_alu(ctx->bc, &alu);
7704 if (r)
7705 return r;
7706 }
7707 return 0;
7708 #endif
7709 }
7710
7711 /* does this shader want a num layers from TXQ for a cube array? */
7712 if (has_txq_cube_array_z) {
7713 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7714
7715 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7716 alu.op = ALU_OP1_MOV;
7717
7718 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7719 if (ctx->bc->chip_class >= EVERGREEN) {
7720 /* with eg each dword is number of cubes */
7721 alu.src[0].sel += id / 4;
7722 alu.src[0].chan = id % 4;
7723 } else {
7724 /* r600 we have them at channel 2 of the second dword */
7725 alu.src[0].sel += (id * 2) + 1;
7726 alu.src[0].chan = 2;
7727 }
7728 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7729 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
7730 alu.last = 1;
7731 r = r600_bytecode_add_alu(ctx->bc, &alu);
7732 if (r)
7733 return r;
7734 /* disable writemask from texture instruction */
7735 inst->Dst[0].Register.WriteMask &= ~4;
7736 }
7737
7738 opcode = ctx->inst_info->op;
7739 if (opcode == FETCH_OP_GATHER4 &&
7740 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
7741 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
7742 opcode = FETCH_OP_GATHER4_O;
7743
7744 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7745 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7746 encoded in the instruction are ignored. */
7747 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7748 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
7749 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7750 tex.sampler_index_mode = sampler_index_mode;
7751 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7752 tex.resource_index_mode = sampler_index_mode;
7753
7754 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
7755 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
7756 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
7757 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
7758 tex.src_sel_w = 4;
7759
7760 tex.dst_sel_x = 7;
7761 tex.dst_sel_y = 7;
7762 tex.dst_sel_z = 7;
7763 tex.dst_sel_w = 7;
7764
7765 r = r600_bytecode_add_tex(ctx->bc, &tex);
7766 if (r)
7767 return r;
7768 }
7769
7770 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7771 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7772 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7773 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7774 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
7775 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7776 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7777 switch (opcode) {
7778 case FETCH_OP_SAMPLE:
7779 opcode = FETCH_OP_SAMPLE_C;
7780 break;
7781 case FETCH_OP_SAMPLE_L:
7782 opcode = FETCH_OP_SAMPLE_C_L;
7783 break;
7784 case FETCH_OP_SAMPLE_LB:
7785 opcode = FETCH_OP_SAMPLE_C_LB;
7786 break;
7787 case FETCH_OP_SAMPLE_G:
7788 opcode = FETCH_OP_SAMPLE_C_G;
7789 break;
7790 /* Texture gather variants */
7791 case FETCH_OP_GATHER4:
7792 opcode = FETCH_OP_GATHER4_C;
7793 break;
7794 case FETCH_OP_GATHER4_O:
7795 opcode = FETCH_OP_GATHER4_C_O;
7796 break;
7797 }
7798 }
7799
7800 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7801 tex.op = opcode;
7802
7803 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7804 tex.sampler_index_mode = sampler_index_mode;
7805 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7806 tex.resource_index_mode = sampler_index_mode;
7807 tex.src_gpr = src_gpr;
7808 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7809
7810 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
7811 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
7812 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
7813 }
7814
7815 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7816 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
7817 tex.inst_mod = texture_component_select;
7818
7819 if (ctx->bc->chip_class == CAYMAN) {
7820 /* GATHER4 result order is different from TGSI TG4 */
7821 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
7822 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
7823 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
7824 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7825 } else {
7826 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7827 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7828 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7829 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7830 }
7831 }
7832 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
7833 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7834 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7835 tex.dst_sel_z = 7;
7836 tex.dst_sel_w = 7;
7837 }
7838 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7839 tex.dst_sel_x = 3;
7840 tex.dst_sel_y = 7;
7841 tex.dst_sel_z = 7;
7842 tex.dst_sel_w = 7;
7843 }
7844 else {
7845 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7846 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7847 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7848 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7849 }
7850
7851
7852 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7853 tex.src_sel_x = 4;
7854 tex.src_sel_y = 4;
7855 tex.src_sel_z = 4;
7856 tex.src_sel_w = 4;
7857 } else if (src_loaded) {
7858 tex.src_sel_x = 0;
7859 tex.src_sel_y = 1;
7860 tex.src_sel_z = 2;
7861 tex.src_sel_w = 3;
7862 } else {
7863 tex.src_sel_x = ctx->src[0].swizzle[0];
7864 tex.src_sel_y = ctx->src[0].swizzle[1];
7865 tex.src_sel_z = ctx->src[0].swizzle[2];
7866 tex.src_sel_w = ctx->src[0].swizzle[3];
7867 tex.src_rel = ctx->src[0].rel;
7868 }
7869
7870 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7871 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7872 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7873 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7874 tex.src_sel_x = 1;
7875 tex.src_sel_y = 0;
7876 tex.src_sel_z = 3;
7877 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
7878 }
7879
7880 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
7881 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
7882 tex.coord_type_x = 1;
7883 tex.coord_type_y = 1;
7884 }
7885 tex.coord_type_z = 1;
7886 tex.coord_type_w = 1;
7887
7888 tex.offset_x = offset_x;
7889 tex.offset_y = offset_y;
7890 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
7891 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7892 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
7893 tex.offset_z = 0;
7894 }
7895 else {
7896 tex.offset_z = offset_z;
7897 }
7898
7899 /* Put the depth for comparison in W.
7900 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7901 * Some instructions expect the depth in Z. */
7902 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7903 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7904 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7905 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
7906 opcode != FETCH_OP_SAMPLE_C_L &&
7907 opcode != FETCH_OP_SAMPLE_C_LB) {
7908 tex.src_sel_w = tex.src_sel_z;
7909 }
7910
7911 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
7912 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
7913 if (opcode == FETCH_OP_SAMPLE_C_L ||
7914 opcode == FETCH_OP_SAMPLE_C_LB) {
7915 /* the array index is read from Y */
7916 tex.coord_type_y = 0;
7917 } else {
7918 /* the array index is read from Z */
7919 tex.coord_type_z = 0;
7920 tex.src_sel_z = tex.src_sel_y;
7921 }
7922 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7923 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7924 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7925 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7926 (ctx->bc->chip_class >= EVERGREEN)))
7927 /* the array index is read from Z */
7928 tex.coord_type_z = 0;
7929
7930 /* mask unused source components */
7931 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
7932 switch (inst->Texture.Texture) {
7933 case TGSI_TEXTURE_2D:
7934 case TGSI_TEXTURE_RECT:
7935 tex.src_sel_z = 7;
7936 tex.src_sel_w = 7;
7937 break;
7938 case TGSI_TEXTURE_1D_ARRAY:
7939 tex.src_sel_y = 7;
7940 tex.src_sel_w = 7;
7941 break;
7942 case TGSI_TEXTURE_1D:
7943 tex.src_sel_y = 7;
7944 tex.src_sel_z = 7;
7945 tex.src_sel_w = 7;
7946 break;
7947 }
7948 }
7949
7950 r = r600_bytecode_add_tex(ctx->bc, &tex);
7951 if (r)
7952 return r;
7953
7954 /* add shadow ambient support - gallium doesn't do it yet */
7955 return 0;
7956 }
7957
7958 static int find_hw_atomic_counter(struct r600_shader_ctx *ctx,
7959 struct tgsi_full_src_register *src)
7960 {
7961 unsigned i;
7962
7963 if (src->Register.Indirect) {
7964 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7965 if (src->Indirect.ArrayID == ctx->shader->atomics[i].array_id)
7966 return ctx->shader->atomics[i].hw_idx;
7967 }
7968 } else {
7969 uint32_t index = src->Register.Index;
7970 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7971 if (ctx->shader->atomics[i].buffer_id != (unsigned)src->Dimension.Index)
7972 continue;
7973 if (index > ctx->shader->atomics[i].end)
7974 continue;
7975 if (index < ctx->shader->atomics[i].start)
7976 continue;
7977 uint32_t offset = (index - ctx->shader->atomics[i].start);
7978 return ctx->shader->atomics[i].hw_idx + offset;
7979 }
7980 }
7981 assert(0);
7982 return -1;
7983 }
7984
7985 static int tgsi_set_gds_temp(struct r600_shader_ctx *ctx,
7986 int *uav_id_p, int *uav_index_mode_p)
7987 {
7988 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7989 int uav_id, uav_index_mode = 0;
7990 int r;
7991 bool is_cm = (ctx->bc->chip_class == CAYMAN);
7992
7993 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
7994
7995 if (inst->Src[0].Register.Indirect) {
7996 if (is_cm) {
7997 struct r600_bytecode_alu alu;
7998 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7999 alu.op = ALU_OP2_LSHL_INT;
8000 alu.src[0].sel = get_address_file_reg(ctx, inst->Src[0].Indirect.Index);
8001 alu.src[0].chan = 0;
8002 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8003 alu.src[1].value = 2;
8004 alu.dst.sel = ctx->temp_reg;
8005 alu.dst.chan = 0;
8006 alu.dst.write = 1;
8007 alu.last = 1;
8008 r = r600_bytecode_add_alu(ctx->bc, &alu);
8009 if (r)
8010 return r;
8011
8012 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8013 ctx->temp_reg, 0,
8014 ctx->temp_reg, 0,
8015 V_SQ_ALU_SRC_LITERAL, uav_id * 4);
8016 if (r)
8017 return r;
8018 } else
8019 uav_index_mode = 2;
8020 } else if (is_cm) {
8021 r = single_alu_op2(ctx, ALU_OP1_MOV,
8022 ctx->temp_reg, 0,
8023 V_SQ_ALU_SRC_LITERAL, uav_id * 4,
8024 0, 0);
8025 if (r)
8026 return r;
8027 }
8028 *uav_id_p = uav_id;
8029 *uav_index_mode_p = uav_index_mode;
8030 return 0;
8031 }
8032
8033 static int tgsi_load_gds(struct r600_shader_ctx *ctx)
8034 {
8035 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8036 int r;
8037 struct r600_bytecode_gds gds;
8038 int uav_id = 0;
8039 int uav_index_mode = 0;
8040 bool is_cm = (ctx->bc->chip_class == CAYMAN);
8041
8042 r = tgsi_set_gds_temp(ctx, &uav_id, &uav_index_mode);
8043 if (r)
8044 return r;
8045
8046 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
8047 gds.op = FETCH_OP_GDS_READ_RET;
8048 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8049 gds.uav_id = is_cm ? 0 : uav_id;
8050 gds.uav_index_mode = is_cm ? 0 : uav_index_mode;
8051 gds.src_gpr = ctx->temp_reg;
8052 gds.src_sel_x = (is_cm) ? 0 : 4;
8053 gds.src_sel_y = 4;
8054 gds.src_sel_z = 4;
8055 gds.dst_sel_x = 0;
8056 gds.dst_sel_y = 7;
8057 gds.dst_sel_z = 7;
8058 gds.dst_sel_w = 7;
8059 gds.src_gpr2 = 0;
8060 gds.alloc_consume = !is_cm;
8061 r = r600_bytecode_add_gds(ctx->bc, &gds);
8062 if (r)
8063 return r;
8064
8065 ctx->bc->cf_last->vpm = 1;
8066 return 0;
8067 }
8068
8069 /* this fixes up 1D arrays properly */
8070 static int load_index_src(struct r600_shader_ctx *ctx, int src_index, int *idx_gpr)
8071 {
8072 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8073 int r, i;
8074 struct r600_bytecode_alu alu;
8075 int temp_reg = r600_get_temp(ctx);
8076
8077 for (i = 0; i < 4; i++) {
8078 bool def_val = true, write_zero = false;
8079 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8080 alu.op = ALU_OP1_MOV;
8081 alu.dst.sel = temp_reg;
8082 alu.dst.chan = i;
8083
8084 switch (inst->Memory.Texture) {
8085 case TGSI_TEXTURE_BUFFER:
8086 case TGSI_TEXTURE_1D:
8087 if (i == 1 || i == 2 || i == 3) {
8088 write_zero = true;
8089 }
8090 break;
8091 case TGSI_TEXTURE_1D_ARRAY:
8092 if (i == 1 || i == 3)
8093 write_zero = true;
8094 else if (i == 2) {
8095 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], 1);
8096 def_val = false;
8097 }
8098 break;
8099 case TGSI_TEXTURE_2D:
8100 if (i == 2 || i == 3)
8101 write_zero = true;
8102 break;
8103 default:
8104 if (i == 3)
8105 write_zero = true;
8106 break;
8107 }
8108
8109 if (write_zero) {
8110 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
8111 alu.src[0].value = 0;
8112 } else if (def_val) {
8113 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], i);
8114 }
8115
8116 if (i == 3)
8117 alu.last = 1;
8118 alu.dst.write = 1;
8119 r = r600_bytecode_add_alu(ctx->bc, &alu);
8120 if (r)
8121 return r;
8122 }
8123 *idx_gpr = temp_reg;
8124 return 0;
8125 }
8126
8127 static int load_buffer_coord(struct r600_shader_ctx *ctx, int src_idx,
8128 int temp_reg)
8129 {
8130 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8131 int r;
8132 if (inst->Src[src_idx].Register.File == TGSI_FILE_IMMEDIATE) {
8133 int value = (ctx->literals[4 * inst->Src[src_idx].Register.Index + inst->Src[src_idx].Register.SwizzleX]);
8134 r = single_alu_op2(ctx, ALU_OP1_MOV,
8135 temp_reg, 0,
8136 V_SQ_ALU_SRC_LITERAL, value >> 2,
8137 0, 0);
8138 if (r)
8139 return r;
8140 } else {
8141 struct r600_bytecode_alu alu;
8142 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8143 alu.op = ALU_OP2_LSHR_INT;
8144 r600_bytecode_src(&alu.src[0], &ctx->src[src_idx], 0);
8145 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8146 alu.src[1].value = 2;
8147 alu.dst.sel = temp_reg;
8148 alu.dst.write = 1;
8149 alu.last = 1;
8150 r = r600_bytecode_add_alu(ctx->bc, &alu);
8151 if (r)
8152 return r;
8153 }
8154 return 0;
8155 }
8156
8157 static int tgsi_load_buffer(struct r600_shader_ctx *ctx)
8158 {
8159 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8160 /* have to work out the offset into the RAT immediate return buffer */
8161 struct r600_bytecode_vtx vtx;
8162 struct r600_bytecode_cf *cf;
8163 int r;
8164 int temp_reg = r600_get_temp(ctx);
8165 unsigned rat_index_mode;
8166 unsigned base;
8167
8168 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8169 base = R600_IMAGE_REAL_RESOURCE_OFFSET + ctx->info.file_count[TGSI_FILE_IMAGE];
8170
8171 r = load_buffer_coord(ctx, 1, temp_reg);
8172 if (r)
8173 return r;
8174 ctx->bc->cf_last->barrier = 1;
8175 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8176 vtx.op = FETCH_OP_VFETCH;
8177 vtx.buffer_id = inst->Src[0].Register.Index + base;
8178 vtx.buffer_index_mode = rat_index_mode;
8179 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8180 vtx.src_gpr = temp_reg;
8181 vtx.src_sel_x = 0;
8182 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8183 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
8184 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
8185 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
8186 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
8187 vtx.num_format_all = 1;
8188 vtx.format_comp_all = 1;
8189 vtx.srf_mode_all = 0;
8190
8191 if (inst->Dst[0].Register.WriteMask & 8) {
8192 vtx.data_format = FMT_32_32_32_32;
8193 vtx.use_const_fields = 0;
8194 } else if (inst->Dst[0].Register.WriteMask & 4) {
8195 vtx.data_format = FMT_32_32_32;
8196 vtx.use_const_fields = 0;
8197 } else if (inst->Dst[0].Register.WriteMask & 2) {
8198 vtx.data_format = FMT_32_32;
8199 vtx.use_const_fields = 0;
8200 } else {
8201 vtx.data_format = FMT_32;
8202 vtx.use_const_fields = 0;
8203 }
8204
8205 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8206 if (r)
8207 return r;
8208 cf = ctx->bc->cf_last;
8209 cf->barrier = 1;
8210 return 0;
8211 }
8212
8213 static int tgsi_load_rat(struct r600_shader_ctx *ctx)
8214 {
8215 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8216 /* have to work out the offset into the RAT immediate return buffer */
8217 struct r600_bytecode_vtx vtx;
8218 struct r600_bytecode_cf *cf;
8219 int r;
8220 int idx_gpr;
8221 unsigned format, num_format, format_comp, endian;
8222 const struct util_format_description *desc;
8223 unsigned rat_index_mode;
8224 unsigned immed_base;
8225
8226 r = load_thread_id_gpr(ctx);
8227 if (r)
8228 return r;
8229
8230 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8231
8232 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
8233 r = load_index_src(ctx, 1, &idx_gpr);
8234 if (r)
8235 return r;
8236
8237 if (rat_index_mode)
8238 egcm_load_index_reg(ctx->bc, 1, false);
8239
8240 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8241 cf = ctx->bc->cf_last;
8242
8243 cf->rat.id = ctx->shader->rat_base + inst->Src[0].Register.Index;
8244 cf->rat.inst = V_RAT_INST_NOP_RTN;
8245 cf->rat.index_mode = rat_index_mode;
8246 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
8247 cf->output.gpr = ctx->thread_id_gpr;
8248 cf->output.index_gpr = idx_gpr;
8249 cf->output.comp_mask = 0xf;
8250 cf->output.burst_count = 1;
8251 cf->vpm = 1;
8252 cf->barrier = 1;
8253 cf->mark = 1;
8254 cf->output.elem_size = 0;
8255
8256 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
8257 cf = ctx->bc->cf_last;
8258 cf->barrier = 1;
8259
8260 desc = util_format_description(inst->Memory.Format);
8261 r600_vertex_data_type(inst->Memory.Format,
8262 &format, &num_format, &format_comp, &endian);
8263 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8264 vtx.op = FETCH_OP_VFETCH;
8265 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
8266 vtx.buffer_index_mode = rat_index_mode;
8267 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8268 vtx.src_gpr = ctx->thread_id_gpr;
8269 vtx.src_sel_x = 1;
8270 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8271 vtx.dst_sel_x = desc->swizzle[0];
8272 vtx.dst_sel_y = desc->swizzle[1];
8273 vtx.dst_sel_z = desc->swizzle[2];
8274 vtx.dst_sel_w = desc->swizzle[3];
8275 vtx.srf_mode_all = 1;
8276 vtx.data_format = format;
8277 vtx.num_format_all = num_format;
8278 vtx.format_comp_all = format_comp;
8279 vtx.endian = endian;
8280 vtx.offset = 0;
8281 vtx.mega_fetch_count = 3;
8282 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8283 if (r)
8284 return r;
8285 cf = ctx->bc->cf_last;
8286 cf->barrier = 1;
8287 return 0;
8288 }
8289
8290 static int tgsi_load_lds(struct r600_shader_ctx *ctx)
8291 {
8292 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8293 struct r600_bytecode_alu alu;
8294 int r;
8295 int temp_reg = r600_get_temp(ctx);
8296
8297 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8298 alu.op = ALU_OP1_MOV;
8299 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
8300 alu.dst.sel = temp_reg;
8301 alu.dst.write = 1;
8302 alu.last = 1;
8303 r = r600_bytecode_add_alu(ctx->bc, &alu);
8304 if (r)
8305 return r;
8306
8307 r = do_lds_fetch_values(ctx, temp_reg,
8308 ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index, inst->Dst[0].Register.WriteMask);
8309 if (r)
8310 return r;
8311 return 0;
8312 }
8313
8314 static int tgsi_load(struct r600_shader_ctx *ctx)
8315 {
8316 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8317 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
8318 return tgsi_load_rat(ctx);
8319 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
8320 return tgsi_load_gds(ctx);
8321 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
8322 return tgsi_load_buffer(ctx);
8323 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
8324 return tgsi_load_lds(ctx);
8325 return 0;
8326 }
8327
8328 static int tgsi_store_buffer_rat(struct r600_shader_ctx *ctx)
8329 {
8330 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8331 struct r600_bytecode_cf *cf;
8332 int r, i;
8333 unsigned rat_index_mode;
8334 int lasti;
8335 int temp_reg = r600_get_temp(ctx), treg2 = r600_get_temp(ctx);
8336
8337 r = load_buffer_coord(ctx, 0, treg2);
8338 if (r)
8339 return r;
8340
8341 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8342 if (rat_index_mode)
8343 egcm_load_index_reg(ctx->bc, 1, false);
8344
8345 for (i = 0; i <= 3; i++) {
8346 struct r600_bytecode_alu alu;
8347 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8348 alu.op = ALU_OP1_MOV;
8349 alu.dst.sel = temp_reg;
8350 alu.dst.chan = i;
8351 alu.src[0].sel = V_SQ_ALU_SRC_0;
8352 alu.last = (i == 3);
8353 alu.dst.write = 1;
8354 r = r600_bytecode_add_alu(ctx->bc, &alu);
8355 if (r)
8356 return r;
8357 }
8358
8359 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8360 for (i = 0; i <= lasti; i++) {
8361 struct r600_bytecode_alu alu;
8362 if (!((1 << i) & inst->Dst[0].Register.WriteMask))
8363 continue;
8364
8365 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8366 temp_reg, 0,
8367 treg2, 0,
8368 V_SQ_ALU_SRC_LITERAL, i);
8369 if (r)
8370 return r;
8371
8372 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8373 alu.op = ALU_OP1_MOV;
8374 alu.dst.sel = ctx->temp_reg;
8375 alu.dst.chan = 0;
8376
8377 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8378 alu.last = 1;
8379 alu.dst.write = 1;
8380 r = r600_bytecode_add_alu(ctx->bc, &alu);
8381 if (r)
8382 return r;
8383
8384 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8385 cf = ctx->bc->cf_last;
8386
8387 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index + ctx->info.file_count[TGSI_FILE_IMAGE];
8388 cf->rat.inst = V_RAT_INST_STORE_TYPED;
8389 cf->rat.index_mode = rat_index_mode;
8390 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
8391 cf->output.gpr = ctx->temp_reg;
8392 cf->output.index_gpr = temp_reg;
8393 cf->output.comp_mask = 1;
8394 cf->output.burst_count = 1;
8395 cf->vpm = 1;
8396 cf->barrier = 1;
8397 cf->output.elem_size = 0;
8398 }
8399 return 0;
8400 }
8401
8402 static int tgsi_store_rat(struct r600_shader_ctx *ctx)
8403 {
8404 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8405 struct r600_bytecode_cf *cf;
8406 bool src_requires_loading = false;
8407 int val_gpr, idx_gpr;
8408 int r, i;
8409 unsigned rat_index_mode;
8410
8411 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8412
8413 r = load_index_src(ctx, 0, &idx_gpr);
8414 if (r)
8415 return r;
8416
8417 if (inst->Src[1].Register.File != TGSI_FILE_TEMPORARY)
8418 src_requires_loading = true;
8419
8420 if (src_requires_loading) {
8421 struct r600_bytecode_alu alu;
8422 for (i = 0; i < 4; i++) {
8423 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8424 alu.op = ALU_OP1_MOV;
8425 alu.dst.sel = ctx->temp_reg;
8426 alu.dst.chan = i;
8427
8428 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8429 if (i == 3)
8430 alu.last = 1;
8431 alu.dst.write = 1;
8432 r = r600_bytecode_add_alu(ctx->bc, &alu);
8433 if (r)
8434 return r;
8435 }
8436 val_gpr = ctx->temp_reg;
8437 } else
8438 val_gpr = tgsi_tex_get_src_gpr(ctx, 1);
8439 if (rat_index_mode)
8440 egcm_load_index_reg(ctx->bc, 1, false);
8441
8442 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8443 cf = ctx->bc->cf_last;
8444
8445 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index;
8446 cf->rat.inst = V_RAT_INST_STORE_TYPED;
8447 cf->rat.index_mode = rat_index_mode;
8448 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
8449 cf->output.gpr = val_gpr;
8450 cf->output.index_gpr = idx_gpr;
8451 cf->output.comp_mask = 0xf;
8452 cf->output.burst_count = 1;
8453 cf->vpm = 1;
8454 cf->barrier = 1;
8455 cf->output.elem_size = 0;
8456 return 0;
8457 }
8458
8459 static int tgsi_store_lds(struct r600_shader_ctx *ctx)
8460 {
8461 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8462 struct r600_bytecode_alu alu;
8463 int r, i, lasti;
8464 int write_mask = inst->Dst[0].Register.WriteMask;
8465 int temp_reg = r600_get_temp(ctx);
8466
8467 /* LDS write */
8468 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8469 alu.op = ALU_OP1_MOV;
8470 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8471 alu.dst.sel = temp_reg;
8472 alu.dst.write = 1;
8473 alu.last = 1;
8474 r = r600_bytecode_add_alu(ctx->bc, &alu);
8475 if (r)
8476 return r;
8477
8478 lasti = tgsi_last_instruction(write_mask);
8479 for (i = 1; i <= lasti; i++) {
8480 if (!(write_mask & (1 << i)))
8481 continue;
8482 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8483 temp_reg, i,
8484 temp_reg, 0,
8485 V_SQ_ALU_SRC_LITERAL, 4 * i);
8486 if (r)
8487 return r;
8488 }
8489 for (i = 0; i <= lasti; i++) {
8490 if (!(write_mask & (1 << i)))
8491 continue;
8492
8493 if ((i == 0 && ((write_mask & 3) == 3)) ||
8494 (i == 2 && ((write_mask & 0xc) == 0xc))) {
8495 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8496 alu.op = LDS_OP3_LDS_WRITE_REL;
8497
8498 alu.src[0].sel = temp_reg;
8499 alu.src[0].chan = i;
8500 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8501 r600_bytecode_src(&alu.src[2], &ctx->src[1], i + 1);
8502 alu.last = 1;
8503 alu.is_lds_idx_op = true;
8504 alu.lds_idx = 1;
8505 r = r600_bytecode_add_alu(ctx->bc, &alu);
8506 if (r)
8507 return r;
8508 i += 1;
8509 continue;
8510 }
8511 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8512 alu.op = LDS_OP2_LDS_WRITE;
8513
8514 alu.src[0].sel = temp_reg;
8515 alu.src[0].chan = i;
8516 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8517
8518 alu.last = 1;
8519 alu.is_lds_idx_op = true;
8520
8521 r = r600_bytecode_add_alu(ctx->bc, &alu);
8522 if (r)
8523 return r;
8524 }
8525 return 0;
8526 }
8527
8528 static int tgsi_store(struct r600_shader_ctx *ctx)
8529 {
8530 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8531 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER)
8532 return tgsi_store_buffer_rat(ctx);
8533 else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY)
8534 return tgsi_store_lds(ctx);
8535 else
8536 return tgsi_store_rat(ctx);
8537 }
8538
8539 static int tgsi_atomic_op_rat(struct r600_shader_ctx *ctx)
8540 {
8541 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8542 /* have to work out the offset into the RAT immediate return buffer */
8543 struct r600_bytecode_alu alu;
8544 struct r600_bytecode_vtx vtx;
8545 struct r600_bytecode_cf *cf;
8546 int r;
8547 int idx_gpr;
8548 unsigned format, num_format, format_comp, endian;
8549 const struct util_format_description *desc;
8550 unsigned rat_index_mode;
8551 unsigned immed_base;
8552 unsigned rat_base;
8553
8554 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
8555 rat_base = ctx->shader->rat_base;
8556
8557 r = load_thread_id_gpr(ctx);
8558 if (r)
8559 return r;
8560
8561 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
8562 immed_base += ctx->info.file_count[TGSI_FILE_IMAGE];
8563 rat_base += ctx->info.file_count[TGSI_FILE_IMAGE];
8564
8565 r = load_buffer_coord(ctx, 1, ctx->temp_reg);
8566 if (r)
8567 return r;
8568 idx_gpr = ctx->temp_reg;
8569 } else {
8570 r = load_index_src(ctx, 1, &idx_gpr);
8571 if (r)
8572 return r;
8573 }
8574
8575 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8576
8577 if (ctx->inst_info->op == V_RAT_INST_CMPXCHG_INT_RTN) {
8578 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8579 alu.op = ALU_OP1_MOV;
8580 alu.dst.sel = ctx->thread_id_gpr;
8581 alu.dst.chan = 0;
8582 alu.dst.write = 1;
8583 r600_bytecode_src(&alu.src[0], &ctx->src[3], 0);
8584 alu.last = 1;
8585 r = r600_bytecode_add_alu(ctx->bc, &alu);
8586 if (r)
8587 return r;
8588
8589 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8590 alu.op = ALU_OP1_MOV;
8591 alu.dst.sel = ctx->thread_id_gpr;
8592 if (ctx->bc->chip_class == CAYMAN)
8593 alu.dst.chan = 2;
8594 else
8595 alu.dst.chan = 3;
8596 alu.dst.write = 1;
8597 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8598 alu.last = 1;
8599 r = r600_bytecode_add_alu(ctx->bc, &alu);
8600 if (r)
8601 return r;
8602 } else {
8603 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8604 alu.op = ALU_OP1_MOV;
8605 alu.dst.sel = ctx->thread_id_gpr;
8606 alu.dst.chan = 0;
8607 alu.dst.write = 1;
8608 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8609 alu.last = 1;
8610 r = r600_bytecode_add_alu(ctx->bc, &alu);
8611 if (r)
8612 return r;
8613 }
8614
8615 if (rat_index_mode)
8616 egcm_load_index_reg(ctx->bc, 1, false);
8617 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8618 cf = ctx->bc->cf_last;
8619
8620 cf->rat.id = rat_base + inst->Src[0].Register.Index;
8621 cf->rat.inst = ctx->inst_info->op;
8622 cf->rat.index_mode = rat_index_mode;
8623 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
8624 cf->output.gpr = ctx->thread_id_gpr;
8625 cf->output.index_gpr = idx_gpr;
8626 cf->output.comp_mask = 0xf;
8627 cf->output.burst_count = 1;
8628 cf->vpm = 1;
8629 cf->barrier = 1;
8630 cf->mark = 1;
8631 cf->output.elem_size = 0;
8632 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
8633 cf = ctx->bc->cf_last;
8634 cf->barrier = 1;
8635 cf->cf_addr = 1;
8636
8637 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8638 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
8639 desc = util_format_description(inst->Memory.Format);
8640 r600_vertex_data_type(inst->Memory.Format,
8641 &format, &num_format, &format_comp, &endian);
8642 vtx.dst_sel_x = desc->swizzle[0];
8643 } else {
8644 format = FMT_32;
8645 num_format = 1;
8646 format_comp = 0;
8647 endian = 0;
8648 vtx.dst_sel_x = 0;
8649 }
8650 vtx.op = FETCH_OP_VFETCH;
8651 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
8652 vtx.buffer_index_mode = rat_index_mode;
8653 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8654 vtx.src_gpr = ctx->thread_id_gpr;
8655 vtx.src_sel_x = 1;
8656 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8657 vtx.dst_sel_y = 7;
8658 vtx.dst_sel_z = 7;
8659 vtx.dst_sel_w = 7;
8660 vtx.use_const_fields = 0;
8661 vtx.srf_mode_all = 1;
8662 vtx.data_format = format;
8663 vtx.num_format_all = num_format;
8664 vtx.format_comp_all = format_comp;
8665 vtx.endian = endian;
8666 vtx.offset = 0;
8667 vtx.mega_fetch_count = 0xf;
8668 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8669 if (r)
8670 return r;
8671 cf = ctx->bc->cf_last;
8672 cf->vpm = 1;
8673 cf->barrier = 1;
8674 return 0;
8675 }
8676
8677 static int get_gds_op(int opcode)
8678 {
8679 switch (opcode) {
8680 case TGSI_OPCODE_ATOMUADD:
8681 return FETCH_OP_GDS_ADD_RET;
8682 case TGSI_OPCODE_ATOMAND:
8683 return FETCH_OP_GDS_AND_RET;
8684 case TGSI_OPCODE_ATOMOR:
8685 return FETCH_OP_GDS_OR_RET;
8686 case TGSI_OPCODE_ATOMXOR:
8687 return FETCH_OP_GDS_XOR_RET;
8688 case TGSI_OPCODE_ATOMUMIN:
8689 return FETCH_OP_GDS_MIN_UINT_RET;
8690 case TGSI_OPCODE_ATOMUMAX:
8691 return FETCH_OP_GDS_MAX_UINT_RET;
8692 case TGSI_OPCODE_ATOMXCHG:
8693 return FETCH_OP_GDS_XCHG_RET;
8694 case TGSI_OPCODE_ATOMCAS:
8695 return FETCH_OP_GDS_CMP_XCHG_RET;
8696 default:
8697 return -1;
8698 }
8699 }
8700
8701 static int tgsi_atomic_op_gds(struct r600_shader_ctx *ctx)
8702 {
8703 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8704 struct r600_bytecode_gds gds;
8705 struct r600_bytecode_alu alu;
8706 int gds_op = get_gds_op(inst->Instruction.Opcode);
8707 int r;
8708 int uav_id = 0;
8709 int uav_index_mode = 0;
8710 bool is_cm = (ctx->bc->chip_class == CAYMAN);
8711
8712 if (gds_op == -1) {
8713 fprintf(stderr, "unknown GDS op for opcode %d\n", inst->Instruction.Opcode);
8714 return -1;
8715 }
8716
8717 r = tgsi_set_gds_temp(ctx, &uav_id, &uav_index_mode);
8718 if (r)
8719 return r;
8720
8721 if (gds_op == FETCH_OP_GDS_CMP_XCHG_RET) {
8722 if (inst->Src[3].Register.File == TGSI_FILE_IMMEDIATE) {
8723 int value = (ctx->literals[4 * inst->Src[3].Register.Index + inst->Src[3].Register.SwizzleX]);
8724 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8725 alu.op = ALU_OP1_MOV;
8726 alu.dst.sel = ctx->temp_reg;
8727 alu.dst.chan = is_cm ? 2 : 1;
8728 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
8729 alu.src[0].value = value;
8730 alu.last = 1;
8731 alu.dst.write = 1;
8732 r = r600_bytecode_add_alu(ctx->bc, &alu);
8733 if (r)
8734 return r;
8735 } else {
8736 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8737 alu.op = ALU_OP1_MOV;
8738 alu.dst.sel = ctx->temp_reg;
8739 alu.dst.chan = is_cm ? 2 : 1;
8740 r600_bytecode_src(&alu.src[0], &ctx->src[3], 0);
8741 alu.last = 1;
8742 alu.dst.write = 1;
8743 r = r600_bytecode_add_alu(ctx->bc, &alu);
8744 if (r)
8745 return r;
8746 }
8747 }
8748 if (inst->Src[2].Register.File == TGSI_FILE_IMMEDIATE) {
8749 int value = (ctx->literals[4 * inst->Src[2].Register.Index + inst->Src[2].Register.SwizzleX]);
8750 int abs_value = abs(value);
8751 if (abs_value != value && gds_op == FETCH_OP_GDS_ADD_RET)
8752 gds_op = FETCH_OP_GDS_SUB_RET;
8753 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8754 alu.op = ALU_OP1_MOV;
8755 alu.dst.sel = ctx->temp_reg;
8756 alu.dst.chan = is_cm ? 1 : 0;
8757 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
8758 alu.src[0].value = abs_value;
8759 alu.last = 1;
8760 alu.dst.write = 1;
8761 r = r600_bytecode_add_alu(ctx->bc, &alu);
8762 if (r)
8763 return r;
8764 } else {
8765 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8766 alu.op = ALU_OP1_MOV;
8767 alu.dst.sel = ctx->temp_reg;
8768 alu.dst.chan = is_cm ? 1 : 0;
8769 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8770 alu.last = 1;
8771 alu.dst.write = 1;
8772 r = r600_bytecode_add_alu(ctx->bc, &alu);
8773 if (r)
8774 return r;
8775 }
8776
8777
8778 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
8779 gds.op = gds_op;
8780 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8781 gds.uav_id = is_cm ? 0 : uav_id;
8782 gds.uav_index_mode = is_cm ? 0 : uav_index_mode;
8783 gds.src_gpr = ctx->temp_reg;
8784 gds.src_gpr2 = 0;
8785 gds.src_sel_x = is_cm ? 0 : 4;
8786 gds.src_sel_y = is_cm ? 1 : 0;
8787 if (gds_op == FETCH_OP_GDS_CMP_XCHG_RET)
8788 gds.src_sel_z = is_cm ? 2 : 1;
8789 else
8790 gds.src_sel_z = 7;
8791 gds.dst_sel_x = 0;
8792 gds.dst_sel_y = 7;
8793 gds.dst_sel_z = 7;
8794 gds.dst_sel_w = 7;
8795 gds.alloc_consume = !is_cm;
8796
8797 r = r600_bytecode_add_gds(ctx->bc, &gds);
8798 if (r)
8799 return r;
8800 ctx->bc->cf_last->vpm = 1;
8801 return 0;
8802 }
8803
8804 static int get_lds_op(int opcode)
8805 {
8806 switch (opcode) {
8807 case TGSI_OPCODE_ATOMUADD:
8808 return LDS_OP2_LDS_ADD_RET;
8809 case TGSI_OPCODE_ATOMAND:
8810 return LDS_OP2_LDS_AND_RET;
8811 case TGSI_OPCODE_ATOMOR:
8812 return LDS_OP2_LDS_OR_RET;
8813 case TGSI_OPCODE_ATOMXOR:
8814 return LDS_OP2_LDS_XOR_RET;
8815 case TGSI_OPCODE_ATOMUMIN:
8816 return LDS_OP2_LDS_MIN_UINT_RET;
8817 case TGSI_OPCODE_ATOMUMAX:
8818 return LDS_OP2_LDS_MAX_UINT_RET;
8819 case TGSI_OPCODE_ATOMIMIN:
8820 return LDS_OP2_LDS_MIN_INT_RET;
8821 case TGSI_OPCODE_ATOMIMAX:
8822 return LDS_OP2_LDS_MAX_INT_RET;
8823 case TGSI_OPCODE_ATOMXCHG:
8824 return LDS_OP2_LDS_XCHG_RET;
8825 case TGSI_OPCODE_ATOMCAS:
8826 return LDS_OP3_LDS_CMP_XCHG_RET;
8827 default:
8828 return -1;
8829 }
8830 }
8831
8832 static int tgsi_atomic_op_lds(struct r600_shader_ctx *ctx)
8833 {
8834 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8835 int lds_op = get_lds_op(inst->Instruction.Opcode);
8836 int r;
8837
8838 struct r600_bytecode_alu alu;
8839 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8840 alu.op = lds_op;
8841 alu.is_lds_idx_op = true;
8842 alu.last = 1;
8843 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
8844 r600_bytecode_src(&alu.src[1], &ctx->src[2], 0);
8845 if (lds_op == LDS_OP3_LDS_CMP_XCHG_RET)
8846 r600_bytecode_src(&alu.src[2], &ctx->src[3], 0);
8847 else
8848 alu.src[2].sel = V_SQ_ALU_SRC_0;
8849 r = r600_bytecode_add_alu(ctx->bc, &alu);
8850 if (r)
8851 return r;
8852
8853 /* then read from LDS_OQ_A_POP */
8854 memset(&alu, 0, sizeof(alu));
8855
8856 alu.op = ALU_OP1_MOV;
8857 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
8858 alu.src[0].chan = 0;
8859 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
8860 alu.dst.write = 1;
8861 alu.last = 1;
8862 r = r600_bytecode_add_alu(ctx->bc, &alu);
8863 if (r)
8864 return r;
8865
8866 return 0;
8867 }
8868
8869 static int tgsi_atomic_op(struct r600_shader_ctx *ctx)
8870 {
8871 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8872 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
8873 return tgsi_atomic_op_rat(ctx);
8874 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
8875 return tgsi_atomic_op_gds(ctx);
8876 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
8877 return tgsi_atomic_op_rat(ctx);
8878 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
8879 return tgsi_atomic_op_lds(ctx);
8880 return 0;
8881 }
8882
8883 static int tgsi_resq(struct r600_shader_ctx *ctx)
8884 {
8885 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8886 unsigned sampler_index_mode;
8887 struct r600_bytecode_tex tex;
8888 int r;
8889 boolean has_txq_cube_array_z = false;
8890
8891 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
8892 (inst->Src[0].Register.File == TGSI_FILE_IMAGE && inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
8893 if (ctx->bc->chip_class < EVERGREEN)
8894 ctx->shader->uses_tex_buffers = true;
8895 unsigned eg_buffer_base = 0;
8896 eg_buffer_base = R600_IMAGE_REAL_RESOURCE_OFFSET;
8897 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
8898 eg_buffer_base += ctx->info.file_count[TGSI_FILE_IMAGE];
8899 return r600_do_buffer_txq(ctx, 0, ctx->shader->image_size_const_offset, eg_buffer_base);
8900 }
8901
8902 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY &&
8903 inst->Dst[0].Register.WriteMask & 4) {
8904 ctx->shader->has_txq_cube_array_z_comp = true;
8905 has_txq_cube_array_z = true;
8906 }
8907
8908 sampler_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8909 if (sampler_index_mode)
8910 egcm_load_index_reg(ctx->bc, 1, false);
8911
8912
8913 /* does this shader want a num layers from TXQ for a cube array? */
8914 if (has_txq_cube_array_z) {
8915 int id = tgsi_tex_get_src_gpr(ctx, 0) + ctx->shader->image_size_const_offset;
8916 struct r600_bytecode_alu alu;
8917
8918 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8919 alu.op = ALU_OP1_MOV;
8920
8921 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
8922 /* with eg each dword is either number of cubes */
8923 alu.src[0].sel += id / 4;
8924 alu.src[0].chan = id % 4;
8925 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
8926 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
8927 alu.last = 1;
8928 r = r600_bytecode_add_alu(ctx->bc, &alu);
8929 if (r)
8930 return r;
8931 /* disable writemask from texture instruction */
8932 inst->Dst[0].Register.WriteMask &= ~4;
8933 }
8934 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
8935 tex.op = ctx->inst_info->op;
8936 tex.sampler_id = R600_IMAGE_REAL_RESOURCE_OFFSET + inst->Src[0].Register.Index;
8937 tex.sampler_index_mode = sampler_index_mode;
8938 tex.resource_id = tex.sampler_id;
8939 tex.resource_index_mode = sampler_index_mode;
8940 tex.src_sel_x = 4;
8941 tex.src_sel_y = 4;
8942 tex.src_sel_z = 4;
8943 tex.src_sel_w = 4;
8944 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8945 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8946 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
8947 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8948 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8949 r = r600_bytecode_add_tex(ctx->bc, &tex);
8950 if (r)
8951 return r;
8952
8953 return 0;
8954 }
8955
8956 static int tgsi_lrp(struct r600_shader_ctx *ctx)
8957 {
8958 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8959 struct r600_bytecode_alu alu;
8960 unsigned lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8961 unsigned i, temp_regs[2];
8962 int r;
8963
8964 /* optimize if it's just an equal balance */
8965 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
8966 for (i = 0; i < lasti + 1; i++) {
8967 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8968 continue;
8969
8970 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8971 alu.op = ALU_OP2_ADD;
8972 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8973 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8974 alu.omod = 3;
8975 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8976 alu.dst.chan = i;
8977 if (i == lasti) {
8978 alu.last = 1;
8979 }
8980 r = r600_bytecode_add_alu(ctx->bc, &alu);
8981 if (r)
8982 return r;
8983 }
8984 return 0;
8985 }
8986
8987 /* 1 - src0 */
8988 for (i = 0; i < lasti + 1; i++) {
8989 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8990 continue;
8991
8992 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8993 alu.op = ALU_OP2_ADD;
8994 alu.src[0].sel = V_SQ_ALU_SRC_1;
8995 alu.src[0].chan = 0;
8996 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
8997 r600_bytecode_src_toggle_neg(&alu.src[1]);
8998 alu.dst.sel = ctx->temp_reg;
8999 alu.dst.chan = i;
9000 if (i == lasti) {
9001 alu.last = 1;
9002 }
9003 alu.dst.write = 1;
9004 r = r600_bytecode_add_alu(ctx->bc, &alu);
9005 if (r)
9006 return r;
9007 }
9008
9009 /* (1 - src0) * src2 */
9010 for (i = 0; i < lasti + 1; i++) {
9011 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9012 continue;
9013
9014 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9015 alu.op = ALU_OP2_MUL;
9016 alu.src[0].sel = ctx->temp_reg;
9017 alu.src[0].chan = i;
9018 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9019 alu.dst.sel = ctx->temp_reg;
9020 alu.dst.chan = i;
9021 if (i == lasti) {
9022 alu.last = 1;
9023 }
9024 alu.dst.write = 1;
9025 r = r600_bytecode_add_alu(ctx->bc, &alu);
9026 if (r)
9027 return r;
9028 }
9029
9030 /* src0 * src1 + (1 - src0) * src2 */
9031 if (ctx->src[0].abs)
9032 temp_regs[0] = r600_get_temp(ctx);
9033 else
9034 temp_regs[0] = 0;
9035 if (ctx->src[1].abs)
9036 temp_regs[1] = r600_get_temp(ctx);
9037 else
9038 temp_regs[1] = 0;
9039
9040 for (i = 0; i < lasti + 1; i++) {
9041 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9042 continue;
9043
9044 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9045 alu.op = ALU_OP3_MULADD;
9046 alu.is_op3 = 1;
9047 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
9048 if (r)
9049 return r;
9050 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
9051 if (r)
9052 return r;
9053 alu.src[2].sel = ctx->temp_reg;
9054 alu.src[2].chan = i;
9055
9056 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9057 alu.dst.chan = i;
9058 if (i == lasti) {
9059 alu.last = 1;
9060 }
9061 r = r600_bytecode_add_alu(ctx->bc, &alu);
9062 if (r)
9063 return r;
9064 }
9065 return 0;
9066 }
9067
9068 static int tgsi_cmp(struct r600_shader_ctx *ctx)
9069 {
9070 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9071 struct r600_bytecode_alu alu;
9072 int i, r, j;
9073 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9074 int temp_regs[3];
9075 unsigned op;
9076
9077 if (ctx->src[0].abs && ctx->src[0].neg) {
9078 op = ALU_OP3_CNDE;
9079 ctx->src[0].abs = 0;
9080 ctx->src[0].neg = 0;
9081 } else {
9082 op = ALU_OP3_CNDGE;
9083 }
9084
9085 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
9086 temp_regs[j] = 0;
9087 if (ctx->src[j].abs)
9088 temp_regs[j] = r600_get_temp(ctx);
9089 }
9090
9091 for (i = 0; i < lasti + 1; i++) {
9092 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9093 continue;
9094
9095 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9096 alu.op = op;
9097 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
9098 if (r)
9099 return r;
9100 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
9101 if (r)
9102 return r;
9103 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
9104 if (r)
9105 return r;
9106 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9107 alu.dst.chan = i;
9108 alu.dst.write = 1;
9109 alu.is_op3 = 1;
9110 if (i == lasti)
9111 alu.last = 1;
9112 r = r600_bytecode_add_alu(ctx->bc, &alu);
9113 if (r)
9114 return r;
9115 }
9116 return 0;
9117 }
9118
9119 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
9120 {
9121 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9122 struct r600_bytecode_alu alu;
9123 int i, r;
9124 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9125
9126 for (i = 0; i < lasti + 1; i++) {
9127 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9128 continue;
9129
9130 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9131 alu.op = ALU_OP3_CNDE_INT;
9132 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9133 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9134 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
9135 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9136 alu.dst.chan = i;
9137 alu.dst.write = 1;
9138 alu.is_op3 = 1;
9139 if (i == lasti)
9140 alu.last = 1;
9141 r = r600_bytecode_add_alu(ctx->bc, &alu);
9142 if (r)
9143 return r;
9144 }
9145 return 0;
9146 }
9147
9148 static int tgsi_exp(struct r600_shader_ctx *ctx)
9149 {
9150 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9151 struct r600_bytecode_alu alu;
9152 int r;
9153 unsigned i;
9154
9155 /* result.x = 2^floor(src); */
9156 if (inst->Dst[0].Register.WriteMask & 1) {
9157 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9158
9159 alu.op = ALU_OP1_FLOOR;
9160 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9161
9162 alu.dst.sel = ctx->temp_reg;
9163 alu.dst.chan = 0;
9164 alu.dst.write = 1;
9165 alu.last = 1;
9166 r = r600_bytecode_add_alu(ctx->bc, &alu);
9167 if (r)
9168 return r;
9169
9170 if (ctx->bc->chip_class == CAYMAN) {
9171 for (i = 0; i < 3; i++) {
9172 alu.op = ALU_OP1_EXP_IEEE;
9173 alu.src[0].sel = ctx->temp_reg;
9174 alu.src[0].chan = 0;
9175
9176 alu.dst.sel = ctx->temp_reg;
9177 alu.dst.chan = i;
9178 alu.dst.write = i == 0;
9179 alu.last = i == 2;
9180 r = r600_bytecode_add_alu(ctx->bc, &alu);
9181 if (r)
9182 return r;
9183 }
9184 } else {
9185 alu.op = ALU_OP1_EXP_IEEE;
9186 alu.src[0].sel = ctx->temp_reg;
9187 alu.src[0].chan = 0;
9188
9189 alu.dst.sel = ctx->temp_reg;
9190 alu.dst.chan = 0;
9191 alu.dst.write = 1;
9192 alu.last = 1;
9193 r = r600_bytecode_add_alu(ctx->bc, &alu);
9194 if (r)
9195 return r;
9196 }
9197 }
9198
9199 /* result.y = tmp - floor(tmp); */
9200 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
9201 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9202
9203 alu.op = ALU_OP1_FRACT;
9204 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9205
9206 alu.dst.sel = ctx->temp_reg;
9207 #if 0
9208 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9209 if (r)
9210 return r;
9211 #endif
9212 alu.dst.write = 1;
9213 alu.dst.chan = 1;
9214
9215 alu.last = 1;
9216
9217 r = r600_bytecode_add_alu(ctx->bc, &alu);
9218 if (r)
9219 return r;
9220 }
9221
9222 /* result.z = RoughApprox2ToX(tmp);*/
9223 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
9224 if (ctx->bc->chip_class == CAYMAN) {
9225 for (i = 0; i < 3; i++) {
9226 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9227 alu.op = ALU_OP1_EXP_IEEE;
9228 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9229
9230 alu.dst.sel = ctx->temp_reg;
9231 alu.dst.chan = i;
9232 if (i == 2) {
9233 alu.dst.write = 1;
9234 alu.last = 1;
9235 }
9236
9237 r = r600_bytecode_add_alu(ctx->bc, &alu);
9238 if (r)
9239 return r;
9240 }
9241 } else {
9242 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9243 alu.op = ALU_OP1_EXP_IEEE;
9244 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9245
9246 alu.dst.sel = ctx->temp_reg;
9247 alu.dst.write = 1;
9248 alu.dst.chan = 2;
9249
9250 alu.last = 1;
9251
9252 r = r600_bytecode_add_alu(ctx->bc, &alu);
9253 if (r)
9254 return r;
9255 }
9256 }
9257
9258 /* result.w = 1.0;*/
9259 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
9260 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9261
9262 alu.op = ALU_OP1_MOV;
9263 alu.src[0].sel = V_SQ_ALU_SRC_1;
9264 alu.src[0].chan = 0;
9265
9266 alu.dst.sel = ctx->temp_reg;
9267 alu.dst.chan = 3;
9268 alu.dst.write = 1;
9269 alu.last = 1;
9270 r = r600_bytecode_add_alu(ctx->bc, &alu);
9271 if (r)
9272 return r;
9273 }
9274 return tgsi_helper_copy(ctx, inst);
9275 }
9276
9277 static int tgsi_log(struct r600_shader_ctx *ctx)
9278 {
9279 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9280 struct r600_bytecode_alu alu;
9281 int r;
9282 unsigned i;
9283
9284 /* result.x = floor(log2(|src|)); */
9285 if (inst->Dst[0].Register.WriteMask & 1) {
9286 if (ctx->bc->chip_class == CAYMAN) {
9287 for (i = 0; i < 3; i++) {
9288 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9289
9290 alu.op = ALU_OP1_LOG_IEEE;
9291 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9292 r600_bytecode_src_set_abs(&alu.src[0]);
9293
9294 alu.dst.sel = ctx->temp_reg;
9295 alu.dst.chan = i;
9296 if (i == 0)
9297 alu.dst.write = 1;
9298 if (i == 2)
9299 alu.last = 1;
9300 r = r600_bytecode_add_alu(ctx->bc, &alu);
9301 if (r)
9302 return r;
9303 }
9304
9305 } else {
9306 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9307
9308 alu.op = ALU_OP1_LOG_IEEE;
9309 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9310 r600_bytecode_src_set_abs(&alu.src[0]);
9311
9312 alu.dst.sel = ctx->temp_reg;
9313 alu.dst.chan = 0;
9314 alu.dst.write = 1;
9315 alu.last = 1;
9316 r = r600_bytecode_add_alu(ctx->bc, &alu);
9317 if (r)
9318 return r;
9319 }
9320
9321 alu.op = ALU_OP1_FLOOR;
9322 alu.src[0].sel = ctx->temp_reg;
9323 alu.src[0].chan = 0;
9324
9325 alu.dst.sel = ctx->temp_reg;
9326 alu.dst.chan = 0;
9327 alu.dst.write = 1;
9328 alu.last = 1;
9329
9330 r = r600_bytecode_add_alu(ctx->bc, &alu);
9331 if (r)
9332 return r;
9333 }
9334
9335 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
9336 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
9337
9338 if (ctx->bc->chip_class == CAYMAN) {
9339 for (i = 0; i < 3; i++) {
9340 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9341
9342 alu.op = ALU_OP1_LOG_IEEE;
9343 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9344 r600_bytecode_src_set_abs(&alu.src[0]);
9345
9346 alu.dst.sel = ctx->temp_reg;
9347 alu.dst.chan = i;
9348 if (i == 1)
9349 alu.dst.write = 1;
9350 if (i == 2)
9351 alu.last = 1;
9352
9353 r = r600_bytecode_add_alu(ctx->bc, &alu);
9354 if (r)
9355 return r;
9356 }
9357 } else {
9358 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9359
9360 alu.op = ALU_OP1_LOG_IEEE;
9361 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9362 r600_bytecode_src_set_abs(&alu.src[0]);
9363
9364 alu.dst.sel = ctx->temp_reg;
9365 alu.dst.chan = 1;
9366 alu.dst.write = 1;
9367 alu.last = 1;
9368
9369 r = r600_bytecode_add_alu(ctx->bc, &alu);
9370 if (r)
9371 return r;
9372 }
9373
9374 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9375
9376 alu.op = ALU_OP1_FLOOR;
9377 alu.src[0].sel = ctx->temp_reg;
9378 alu.src[0].chan = 1;
9379
9380 alu.dst.sel = ctx->temp_reg;
9381 alu.dst.chan = 1;
9382 alu.dst.write = 1;
9383 alu.last = 1;
9384
9385 r = r600_bytecode_add_alu(ctx->bc, &alu);
9386 if (r)
9387 return r;
9388
9389 if (ctx->bc->chip_class == CAYMAN) {
9390 for (i = 0; i < 3; i++) {
9391 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9392 alu.op = ALU_OP1_EXP_IEEE;
9393 alu.src[0].sel = ctx->temp_reg;
9394 alu.src[0].chan = 1;
9395
9396 alu.dst.sel = ctx->temp_reg;
9397 alu.dst.chan = i;
9398 if (i == 1)
9399 alu.dst.write = 1;
9400 if (i == 2)
9401 alu.last = 1;
9402
9403 r = r600_bytecode_add_alu(ctx->bc, &alu);
9404 if (r)
9405 return r;
9406 }
9407 } else {
9408 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9409 alu.op = ALU_OP1_EXP_IEEE;
9410 alu.src[0].sel = ctx->temp_reg;
9411 alu.src[0].chan = 1;
9412
9413 alu.dst.sel = ctx->temp_reg;
9414 alu.dst.chan = 1;
9415 alu.dst.write = 1;
9416 alu.last = 1;
9417
9418 r = r600_bytecode_add_alu(ctx->bc, &alu);
9419 if (r)
9420 return r;
9421 }
9422
9423 if (ctx->bc->chip_class == CAYMAN) {
9424 for (i = 0; i < 3; i++) {
9425 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9426 alu.op = ALU_OP1_RECIP_IEEE;
9427 alu.src[0].sel = ctx->temp_reg;
9428 alu.src[0].chan = 1;
9429
9430 alu.dst.sel = ctx->temp_reg;
9431 alu.dst.chan = i;
9432 if (i == 1)
9433 alu.dst.write = 1;
9434 if (i == 2)
9435 alu.last = 1;
9436
9437 r = r600_bytecode_add_alu(ctx->bc, &alu);
9438 if (r)
9439 return r;
9440 }
9441 } else {
9442 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9443 alu.op = ALU_OP1_RECIP_IEEE;
9444 alu.src[0].sel = ctx->temp_reg;
9445 alu.src[0].chan = 1;
9446
9447 alu.dst.sel = ctx->temp_reg;
9448 alu.dst.chan = 1;
9449 alu.dst.write = 1;
9450 alu.last = 1;
9451
9452 r = r600_bytecode_add_alu(ctx->bc, &alu);
9453 if (r)
9454 return r;
9455 }
9456
9457 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9458
9459 alu.op = ALU_OP2_MUL;
9460
9461 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9462 r600_bytecode_src_set_abs(&alu.src[0]);
9463
9464 alu.src[1].sel = ctx->temp_reg;
9465 alu.src[1].chan = 1;
9466
9467 alu.dst.sel = ctx->temp_reg;
9468 alu.dst.chan = 1;
9469 alu.dst.write = 1;
9470 alu.last = 1;
9471
9472 r = r600_bytecode_add_alu(ctx->bc, &alu);
9473 if (r)
9474 return r;
9475 }
9476
9477 /* result.z = log2(|src|);*/
9478 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
9479 if (ctx->bc->chip_class == CAYMAN) {
9480 for (i = 0; i < 3; i++) {
9481 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9482
9483 alu.op = ALU_OP1_LOG_IEEE;
9484 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9485 r600_bytecode_src_set_abs(&alu.src[0]);
9486
9487 alu.dst.sel = ctx->temp_reg;
9488 if (i == 2)
9489 alu.dst.write = 1;
9490 alu.dst.chan = i;
9491 if (i == 2)
9492 alu.last = 1;
9493
9494 r = r600_bytecode_add_alu(ctx->bc, &alu);
9495 if (r)
9496 return r;
9497 }
9498 } else {
9499 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9500
9501 alu.op = ALU_OP1_LOG_IEEE;
9502 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9503 r600_bytecode_src_set_abs(&alu.src[0]);
9504
9505 alu.dst.sel = ctx->temp_reg;
9506 alu.dst.write = 1;
9507 alu.dst.chan = 2;
9508 alu.last = 1;
9509
9510 r = r600_bytecode_add_alu(ctx->bc, &alu);
9511 if (r)
9512 return r;
9513 }
9514 }
9515
9516 /* result.w = 1.0; */
9517 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
9518 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9519
9520 alu.op = ALU_OP1_MOV;
9521 alu.src[0].sel = V_SQ_ALU_SRC_1;
9522 alu.src[0].chan = 0;
9523
9524 alu.dst.sel = ctx->temp_reg;
9525 alu.dst.chan = 3;
9526 alu.dst.write = 1;
9527 alu.last = 1;
9528
9529 r = r600_bytecode_add_alu(ctx->bc, &alu);
9530 if (r)
9531 return r;
9532 }
9533
9534 return tgsi_helper_copy(ctx, inst);
9535 }
9536
9537 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
9538 {
9539 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9540 struct r600_bytecode_alu alu;
9541 int r;
9542 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9543 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
9544
9545 assert(inst->Dst[0].Register.Index < 3);
9546 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9547
9548 switch (inst->Instruction.Opcode) {
9549 case TGSI_OPCODE_ARL:
9550 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
9551 break;
9552 case TGSI_OPCODE_ARR:
9553 alu.op = ALU_OP1_FLT_TO_INT;
9554 break;
9555 case TGSI_OPCODE_UARL:
9556 alu.op = ALU_OP1_MOV;
9557 break;
9558 default:
9559 assert(0);
9560 return -1;
9561 }
9562
9563 for (i = 0; i <= lasti; ++i) {
9564 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9565 continue;
9566 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9567 alu.last = i == lasti;
9568 alu.dst.sel = reg;
9569 alu.dst.chan = i;
9570 alu.dst.write = 1;
9571 r = r600_bytecode_add_alu(ctx->bc, &alu);
9572 if (r)
9573 return r;
9574 }
9575
9576 if (inst->Dst[0].Register.Index > 0)
9577 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
9578 else
9579 ctx->bc->ar_loaded = 0;
9580
9581 return 0;
9582 }
9583 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
9584 {
9585 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9586 struct r600_bytecode_alu alu;
9587 int r;
9588 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9589
9590 switch (inst->Instruction.Opcode) {
9591 case TGSI_OPCODE_ARL:
9592 memset(&alu, 0, sizeof(alu));
9593 alu.op = ALU_OP1_FLOOR;
9594 alu.dst.sel = ctx->bc->ar_reg;
9595 alu.dst.write = 1;
9596 for (i = 0; i <= lasti; ++i) {
9597 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
9598 alu.dst.chan = i;
9599 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9600 alu.last = i == lasti;
9601 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9602 return r;
9603 }
9604 }
9605
9606 memset(&alu, 0, sizeof(alu));
9607 alu.op = ALU_OP1_FLT_TO_INT;
9608 alu.src[0].sel = ctx->bc->ar_reg;
9609 alu.dst.sel = ctx->bc->ar_reg;
9610 alu.dst.write = 1;
9611 /* FLT_TO_INT is trans-only on r600/r700 */
9612 alu.last = TRUE;
9613 for (i = 0; i <= lasti; ++i) {
9614 alu.dst.chan = i;
9615 alu.src[0].chan = i;
9616 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9617 return r;
9618 }
9619 break;
9620 case TGSI_OPCODE_ARR:
9621 memset(&alu, 0, sizeof(alu));
9622 alu.op = ALU_OP1_FLT_TO_INT;
9623 alu.dst.sel = ctx->bc->ar_reg;
9624 alu.dst.write = 1;
9625 /* FLT_TO_INT is trans-only on r600/r700 */
9626 alu.last = TRUE;
9627 for (i = 0; i <= lasti; ++i) {
9628 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
9629 alu.dst.chan = i;
9630 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9631 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9632 return r;
9633 }
9634 }
9635 break;
9636 case TGSI_OPCODE_UARL:
9637 memset(&alu, 0, sizeof(alu));
9638 alu.op = ALU_OP1_MOV;
9639 alu.dst.sel = ctx->bc->ar_reg;
9640 alu.dst.write = 1;
9641 for (i = 0; i <= lasti; ++i) {
9642 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
9643 alu.dst.chan = i;
9644 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9645 alu.last = i == lasti;
9646 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9647 return r;
9648 }
9649 }
9650 break;
9651 default:
9652 assert(0);
9653 return -1;
9654 }
9655
9656 ctx->bc->ar_loaded = 0;
9657 return 0;
9658 }
9659
9660 static int tgsi_opdst(struct r600_shader_ctx *ctx)
9661 {
9662 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9663 struct r600_bytecode_alu alu;
9664 int i, r = 0;
9665
9666 for (i = 0; i < 4; i++) {
9667 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9668
9669 alu.op = ALU_OP2_MUL;
9670 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9671
9672 if (i == 0 || i == 3) {
9673 alu.src[0].sel = V_SQ_ALU_SRC_1;
9674 } else {
9675 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9676 }
9677
9678 if (i == 0 || i == 2) {
9679 alu.src[1].sel = V_SQ_ALU_SRC_1;
9680 } else {
9681 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
9682 }
9683 if (i == 3)
9684 alu.last = 1;
9685 r = r600_bytecode_add_alu(ctx->bc, &alu);
9686 if (r)
9687 return r;
9688 }
9689 return 0;
9690 }
9691
9692 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type,
9693 struct r600_bytecode_alu_src *src)
9694 {
9695 struct r600_bytecode_alu alu;
9696 int r;
9697
9698 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9699 alu.op = opcode;
9700 alu.execute_mask = 1;
9701 alu.update_pred = 1;
9702
9703 alu.dst.sel = ctx->temp_reg;
9704 alu.dst.write = 1;
9705 alu.dst.chan = 0;
9706
9707 alu.src[0] = *src;
9708 alu.src[1].sel = V_SQ_ALU_SRC_0;
9709 alu.src[1].chan = 0;
9710
9711 alu.last = 1;
9712
9713 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
9714 if (r)
9715 return r;
9716 return 0;
9717 }
9718
9719 static int pops(struct r600_shader_ctx *ctx, int pops)
9720 {
9721 unsigned force_pop = ctx->bc->force_add_cf;
9722
9723 if (!force_pop) {
9724 int alu_pop = 3;
9725 if (ctx->bc->cf_last) {
9726 if (ctx->bc->cf_last->op == CF_OP_ALU)
9727 alu_pop = 0;
9728 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
9729 alu_pop = 1;
9730 }
9731 alu_pop += pops;
9732 if (alu_pop == 1) {
9733 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
9734 ctx->bc->force_add_cf = 1;
9735 } else if (alu_pop == 2) {
9736 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
9737 ctx->bc->force_add_cf = 1;
9738 } else {
9739 force_pop = 1;
9740 }
9741 }
9742
9743 if (force_pop) {
9744 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
9745 ctx->bc->cf_last->pop_count = pops;
9746 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
9747 }
9748
9749 return 0;
9750 }
9751
9752 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
9753 unsigned reason)
9754 {
9755 struct r600_stack_info *stack = &ctx->bc->stack;
9756 unsigned elements;
9757 int entries;
9758
9759 unsigned entry_size = stack->entry_size;
9760
9761 elements = (stack->loop + stack->push_wqm ) * entry_size;
9762 elements += stack->push;
9763
9764 switch (ctx->bc->chip_class) {
9765 case R600:
9766 case R700:
9767 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
9768 * the stack must be reserved to hold the current active/continue
9769 * masks */
9770 if (reason == FC_PUSH_VPM) {
9771 elements += 2;
9772 }
9773 break;
9774
9775 case CAYMAN:
9776 /* r9xx: any stack operation on empty stack consumes 2 additional
9777 * elements */
9778 elements += 2;
9779
9780 /* fallthrough */
9781 /* FIXME: do the two elements added above cover the cases for the
9782 * r8xx+ below? */
9783
9784 case EVERGREEN:
9785 /* r8xx+: 2 extra elements are not always required, but one extra
9786 * element must be added for each of the following cases:
9787 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
9788 * stack usage.
9789 * (Currently we don't use ALU_ELSE_AFTER.)
9790 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
9791 * PUSH instruction executed.
9792 *
9793 * NOTE: it seems we also need to reserve additional element in some
9794 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
9795 * then STACK_SIZE should be 2 instead of 1 */
9796 if (reason == FC_PUSH_VPM) {
9797 elements += 1;
9798 }
9799 break;
9800
9801 default:
9802 assert(0);
9803 break;
9804 }
9805
9806 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
9807 * for all chips, so we use 4 in the final formula, not the real entry_size
9808 * for the chip */
9809 entry_size = 4;
9810
9811 entries = (elements + (entry_size - 1)) / entry_size;
9812
9813 if (entries > stack->max_entries)
9814 stack->max_entries = entries;
9815 }
9816
9817 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
9818 {
9819 switch(reason) {
9820 case FC_PUSH_VPM:
9821 --ctx->bc->stack.push;
9822 assert(ctx->bc->stack.push >= 0);
9823 break;
9824 case FC_PUSH_WQM:
9825 --ctx->bc->stack.push_wqm;
9826 assert(ctx->bc->stack.push_wqm >= 0);
9827 break;
9828 case FC_LOOP:
9829 --ctx->bc->stack.loop;
9830 assert(ctx->bc->stack.loop >= 0);
9831 break;
9832 default:
9833 assert(0);
9834 break;
9835 }
9836 }
9837
9838 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
9839 {
9840 switch (reason) {
9841 case FC_PUSH_VPM:
9842 ++ctx->bc->stack.push;
9843 break;
9844 case FC_PUSH_WQM:
9845 ++ctx->bc->stack.push_wqm;
9846 case FC_LOOP:
9847 ++ctx->bc->stack.loop;
9848 break;
9849 default:
9850 assert(0);
9851 }
9852
9853 callstack_update_max_depth(ctx, reason);
9854 }
9855
9856 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
9857 {
9858 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
9859
9860 sp->mid = realloc((void *)sp->mid,
9861 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
9862 sp->mid[sp->num_mid] = ctx->bc->cf_last;
9863 sp->num_mid++;
9864 }
9865
9866 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
9867 {
9868 assert(ctx->bc->fc_sp < ARRAY_SIZE(ctx->bc->fc_stack));
9869 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
9870 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
9871 ctx->bc->fc_sp++;
9872 }
9873
9874 static void fc_poplevel(struct r600_shader_ctx *ctx)
9875 {
9876 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp - 1];
9877 free(sp->mid);
9878 sp->mid = NULL;
9879 sp->num_mid = 0;
9880 sp->start = NULL;
9881 sp->type = 0;
9882 ctx->bc->fc_sp--;
9883 }
9884
9885 #if 0
9886 static int emit_return(struct r600_shader_ctx *ctx)
9887 {
9888 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
9889 return 0;
9890 }
9891
9892 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
9893 {
9894
9895 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
9896 ctx->bc->cf_last->pop_count = pops;
9897 /* XXX work out offset */
9898 return 0;
9899 }
9900
9901 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
9902 {
9903 return 0;
9904 }
9905
9906 static void emit_testflag(struct r600_shader_ctx *ctx)
9907 {
9908
9909 }
9910
9911 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
9912 {
9913 emit_testflag(ctx);
9914 emit_jump_to_offset(ctx, 1, 4);
9915 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
9916 pops(ctx, ifidx + 1);
9917 emit_return(ctx);
9918 }
9919
9920 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
9921 {
9922 emit_testflag(ctx);
9923
9924 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9925 ctx->bc->cf_last->pop_count = 1;
9926
9927 fc_set_mid(ctx, fc_sp);
9928
9929 pops(ctx, 1);
9930 }
9931 #endif
9932
9933 static int emit_if(struct r600_shader_ctx *ctx, int opcode,
9934 struct r600_bytecode_alu_src *src)
9935 {
9936 int alu_type = CF_OP_ALU_PUSH_BEFORE;
9937
9938 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
9939 * LOOP_STARTxxx for nested loops may put the branch stack into a state
9940 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
9941 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
9942 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
9943 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
9944 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
9945 alu_type = CF_OP_ALU;
9946 }
9947
9948 emit_logic_pred(ctx, opcode, alu_type, src);
9949
9950 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
9951
9952 fc_pushlevel(ctx, FC_IF);
9953
9954 callstack_push(ctx, FC_PUSH_VPM);
9955 return 0;
9956 }
9957
9958 static int tgsi_if(struct r600_shader_ctx *ctx)
9959 {
9960 struct r600_bytecode_alu_src alu_src;
9961 r600_bytecode_src(&alu_src, &ctx->src[0], 0);
9962
9963 return emit_if(ctx, ALU_OP2_PRED_SETNE, &alu_src);
9964 }
9965
9966 static int tgsi_uif(struct r600_shader_ctx *ctx)
9967 {
9968 struct r600_bytecode_alu_src alu_src;
9969 r600_bytecode_src(&alu_src, &ctx->src[0], 0);
9970 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
9971 }
9972
9973 static int tgsi_else(struct r600_shader_ctx *ctx)
9974 {
9975 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
9976 ctx->bc->cf_last->pop_count = 1;
9977
9978 fc_set_mid(ctx, ctx->bc->fc_sp - 1);
9979 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id;
9980 return 0;
9981 }
9982
9983 static int tgsi_endif(struct r600_shader_ctx *ctx)
9984 {
9985 pops(ctx, 1);
9986 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_IF) {
9987 R600_ERR("if/endif unbalanced in shader\n");
9988 return -1;
9989 }
9990
9991 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid == NULL) {
9992 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
9993 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->pop_count = 1;
9994 } else {
9995 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
9996 }
9997 fc_poplevel(ctx);
9998
9999 callstack_pop(ctx, FC_PUSH_VPM);
10000 return 0;
10001 }
10002
10003 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
10004 {
10005 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
10006 * limited to 4096 iterations, like the other LOOP_* instructions. */
10007 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
10008
10009 fc_pushlevel(ctx, FC_LOOP);
10010
10011 /* check stack depth */
10012 callstack_push(ctx, FC_LOOP);
10013 return 0;
10014 }
10015
10016 static int tgsi_endloop(struct r600_shader_ctx *ctx)
10017 {
10018 int i;
10019
10020 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
10021
10022 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_LOOP) {
10023 R600_ERR("loop/endloop in shader code are not paired.\n");
10024 return -EINVAL;
10025 }
10026
10027 /* fixup loop pointers - from r600isa
10028 LOOP END points to CF after LOOP START,
10029 LOOP START point to CF after LOOP END
10030 BRK/CONT point to LOOP END CF
10031 */
10032 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->id + 2;
10033
10034 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
10035
10036 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp - 1].num_mid; i++) {
10037 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[i]->cf_addr = ctx->bc->cf_last->id;
10038 }
10039 /* XXX add LOOPRET support */
10040 fc_poplevel(ctx);
10041 callstack_pop(ctx, FC_LOOP);
10042 return 0;
10043 }
10044
10045 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
10046 {
10047 unsigned int fscp;
10048
10049 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
10050 {
10051 if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
10052 break;
10053 }
10054
10055 if (fscp == 0) {
10056 R600_ERR("Break not inside loop/endloop pair\n");
10057 return -EINVAL;
10058 }
10059
10060 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
10061
10062 fc_set_mid(ctx, fscp - 1);
10063
10064 return 0;
10065 }
10066
10067 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
10068 {
10069 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10070 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
10071 int r;
10072
10073 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
10074 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
10075
10076 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
10077 if (!r) {
10078 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
10079 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
10080 return emit_inc_ring_offset(ctx, stream, TRUE);
10081 }
10082 return r;
10083 }
10084
10085 static int tgsi_umad(struct r600_shader_ctx *ctx)
10086 {
10087 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10088 struct r600_bytecode_alu alu;
10089 int i, j, r;
10090 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10091
10092 /* src0 * src1 */
10093 for (i = 0; i < lasti + 1; i++) {
10094 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10095 continue;
10096
10097 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10098
10099 alu.dst.chan = i;
10100 alu.dst.sel = ctx->temp_reg;
10101 alu.dst.write = 1;
10102
10103 alu.op = ALU_OP2_MULLO_UINT;
10104 for (j = 0; j < 2; j++) {
10105 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
10106 }
10107
10108 alu.last = 1;
10109 r = emit_mul_int_op(ctx->bc, &alu);
10110 if (r)
10111 return r;
10112 }
10113
10114
10115 for (i = 0; i < lasti + 1; i++) {
10116 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10117 continue;
10118
10119 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10120 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10121
10122 alu.op = ALU_OP2_ADD_INT;
10123
10124 alu.src[0].sel = ctx->temp_reg;
10125 alu.src[0].chan = i;
10126
10127 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
10128 if (i == lasti) {
10129 alu.last = 1;
10130 }
10131 r = r600_bytecode_add_alu(ctx->bc, &alu);
10132 if (r)
10133 return r;
10134 }
10135 return 0;
10136 }
10137
10138 static int tgsi_pk2h(struct r600_shader_ctx *ctx)
10139 {
10140 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10141 struct r600_bytecode_alu alu;
10142 int r, i;
10143 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10144
10145 /* temp.xy = f32_to_f16(src) */
10146 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10147 alu.op = ALU_OP1_FLT32_TO_FLT16;
10148 alu.dst.chan = 0;
10149 alu.dst.sel = ctx->temp_reg;
10150 alu.dst.write = 1;
10151 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10152 r = r600_bytecode_add_alu(ctx->bc, &alu);
10153 if (r)
10154 return r;
10155 alu.dst.chan = 1;
10156 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
10157 alu.last = 1;
10158 r = r600_bytecode_add_alu(ctx->bc, &alu);
10159 if (r)
10160 return r;
10161
10162 /* dst.x = temp.y * 0x10000 + temp.x */
10163 for (i = 0; i < lasti + 1; i++) {
10164 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10165 continue;
10166
10167 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10168 alu.op = ALU_OP3_MULADD_UINT24;
10169 alu.is_op3 = 1;
10170 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10171 alu.last = i == lasti;
10172 alu.src[0].sel = ctx->temp_reg;
10173 alu.src[0].chan = 1;
10174 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10175 alu.src[1].value = 0x10000;
10176 alu.src[2].sel = ctx->temp_reg;
10177 alu.src[2].chan = 0;
10178 r = r600_bytecode_add_alu(ctx->bc, &alu);
10179 if (r)
10180 return r;
10181 }
10182
10183 return 0;
10184 }
10185
10186 static int tgsi_up2h(struct r600_shader_ctx *ctx)
10187 {
10188 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10189 struct r600_bytecode_alu alu;
10190 int r, i;
10191 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10192
10193 /* temp.x = src.x */
10194 /* note: no need to mask out the high bits */
10195 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10196 alu.op = ALU_OP1_MOV;
10197 alu.dst.chan = 0;
10198 alu.dst.sel = ctx->temp_reg;
10199 alu.dst.write = 1;
10200 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10201 r = r600_bytecode_add_alu(ctx->bc, &alu);
10202 if (r)
10203 return r;
10204
10205 /* temp.y = src.x >> 16 */
10206 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10207 alu.op = ALU_OP2_LSHR_INT;
10208 alu.dst.chan = 1;
10209 alu.dst.sel = ctx->temp_reg;
10210 alu.dst.write = 1;
10211 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10212 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10213 alu.src[1].value = 16;
10214 alu.last = 1;
10215 r = r600_bytecode_add_alu(ctx->bc, &alu);
10216 if (r)
10217 return r;
10218
10219 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
10220 for (i = 0; i < lasti + 1; i++) {
10221 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10222 continue;
10223 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10224 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10225 alu.op = ALU_OP1_FLT16_TO_FLT32;
10226 alu.src[0].sel = ctx->temp_reg;
10227 alu.src[0].chan = i % 2;
10228 alu.last = i == lasti;
10229 r = r600_bytecode_add_alu(ctx->bc, &alu);
10230 if (r)
10231 return r;
10232 }
10233
10234 return 0;
10235 }
10236
10237 static int tgsi_bfe(struct r600_shader_ctx *ctx)
10238 {
10239 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10240 struct r600_bytecode_alu alu;
10241 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10242 int r, i;
10243 int dst = -1;
10244
10245 if ((inst->Src[0].Register.File == inst->Dst[0].Register.File &&
10246 inst->Src[0].Register.Index == inst->Dst[0].Register.Index) ||
10247 (inst->Src[2].Register.File == inst->Dst[0].Register.File &&
10248 inst->Src[2].Register.Index == inst->Dst[0].Register.Index))
10249 dst = r600_get_temp(ctx);
10250
10251 r = tgsi_op3_dst(ctx, dst);
10252 if (r)
10253 return r;
10254
10255 for (i = 0; i < lasti + 1; i++) {
10256 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10257 alu.op = ALU_OP2_SETGE_INT;
10258 r600_bytecode_src(&alu.src[0], &ctx->src[2], i);
10259 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10260 alu.src[1].value = 32;
10261 alu.dst.sel = ctx->temp_reg;
10262 alu.dst.chan = i;
10263 alu.dst.write = 1;
10264 if (i == lasti)
10265 alu.last = 1;
10266 r = r600_bytecode_add_alu(ctx->bc, &alu);
10267 if (r)
10268 return r;
10269 }
10270
10271 for (i = 0; i < lasti + 1; i++) {
10272 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10273 alu.op = ALU_OP3_CNDE_INT;
10274 alu.is_op3 = 1;
10275 alu.src[0].sel = ctx->temp_reg;
10276 alu.src[0].chan = i;
10277
10278 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10279 if (dst != -1)
10280 alu.src[1].sel = dst;
10281 else
10282 alu.src[1].sel = alu.dst.sel;
10283 alu.src[1].chan = i;
10284 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
10285 alu.dst.write = 1;
10286 if (i == lasti)
10287 alu.last = 1;
10288 r = r600_bytecode_add_alu(ctx->bc, &alu);
10289 if (r)
10290 return r;
10291 }
10292
10293 return 0;
10294 }
10295
10296 static int tgsi_clock(struct r600_shader_ctx *ctx)
10297 {
10298 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10299 struct r600_bytecode_alu alu;
10300 int r;
10301
10302 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10303 alu.op = ALU_OP1_MOV;
10304 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
10305 alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_LO;
10306 r = r600_bytecode_add_alu(ctx->bc, &alu);
10307 if (r)
10308 return r;
10309 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10310 alu.op = ALU_OP1_MOV;
10311 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
10312 alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_HI;
10313 r = r600_bytecode_add_alu(ctx->bc, &alu);
10314 if (r)
10315 return r;
10316 return 0;
10317 }
10318
10319 static int emit_u64add(struct r600_shader_ctx *ctx, int op,
10320 int treg,
10321 int src0_sel, int src0_chan,
10322 int src1_sel, int src1_chan)
10323 {
10324 struct r600_bytecode_alu alu;
10325 int r;
10326 int opc;
10327
10328 if (op == ALU_OP2_ADD_INT)
10329 opc = ALU_OP2_ADDC_UINT;
10330 else
10331 opc = ALU_OP2_SUBB_UINT;
10332
10333 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10334 alu.op = op; ;
10335 alu.dst.sel = treg;
10336 alu.dst.chan = 0;
10337 alu.dst.write = 1;
10338 alu.src[0].sel = src0_sel;
10339 alu.src[0].chan = src0_chan + 0;
10340 alu.src[1].sel = src1_sel;
10341 alu.src[1].chan = src1_chan + 0;
10342 alu.src[1].neg = 0;
10343 r = r600_bytecode_add_alu(ctx->bc, &alu);
10344 if (r)
10345 return r;
10346
10347 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10348 alu.op = op;
10349 alu.dst.sel = treg;
10350 alu.dst.chan = 1;
10351 alu.dst.write = 1;
10352 alu.src[0].sel = src0_sel;
10353 alu.src[0].chan = src0_chan + 1;
10354 alu.src[1].sel = src1_sel;
10355 alu.src[1].chan = src1_chan + 1;
10356 alu.src[1].neg = 0;
10357 r = r600_bytecode_add_alu(ctx->bc, &alu);
10358 if (r)
10359 return r;
10360
10361 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10362 alu.op = opc;
10363 alu.dst.sel = treg;
10364 alu.dst.chan = 2;
10365 alu.dst.write = 1;
10366 alu.last = 1;
10367 alu.src[0].sel = src0_sel;
10368 alu.src[0].chan = src0_chan + 0;
10369 alu.src[1].sel = src1_sel;
10370 alu.src[1].chan = src1_chan + 0;
10371 alu.src[1].neg = 0;
10372 r = r600_bytecode_add_alu(ctx->bc, &alu);
10373 if (r)
10374 return r;
10375
10376 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10377 alu.op = op;
10378 alu.dst.sel = treg;
10379 alu.dst.chan = 1;
10380 alu.dst.write = 1;
10381 alu.src[0].sel = treg;
10382 alu.src[0].chan = 1;
10383 alu.src[1].sel = treg;
10384 alu.src[1].chan = 2;
10385 alu.last = 1;
10386 r = r600_bytecode_add_alu(ctx->bc, &alu);
10387 if (r)
10388 return r;
10389 return 0;
10390 }
10391
10392 static int egcm_u64add(struct r600_shader_ctx *ctx)
10393 {
10394 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10395 struct r600_bytecode_alu alu;
10396 int r;
10397 int treg = ctx->temp_reg;
10398 int op = ALU_OP2_ADD_INT, opc = ALU_OP2_ADDC_UINT;
10399
10400 if (ctx->src[1].neg) {
10401 op = ALU_OP2_SUB_INT;
10402 opc = ALU_OP2_SUBB_UINT;
10403 }
10404 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10405 alu.op = op; ;
10406 alu.dst.sel = treg;
10407 alu.dst.chan = 0;
10408 alu.dst.write = 1;
10409 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10410 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10411 alu.src[1].neg = 0;
10412 r = r600_bytecode_add_alu(ctx->bc, &alu);
10413 if (r)
10414 return r;
10415
10416 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10417 alu.op = op;
10418 alu.dst.sel = treg;
10419 alu.dst.chan = 1;
10420 alu.dst.write = 1;
10421 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
10422 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
10423 alu.src[1].neg = 0;
10424 r = r600_bytecode_add_alu(ctx->bc, &alu);
10425 if (r)
10426 return r;
10427
10428 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10429 alu.op = opc ;
10430 alu.dst.sel = treg;
10431 alu.dst.chan = 2;
10432 alu.dst.write = 1;
10433 alu.last = 1;
10434 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10435 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10436 alu.src[1].neg = 0;
10437 r = r600_bytecode_add_alu(ctx->bc, &alu);
10438 if (r)
10439 return r;
10440
10441 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10442 alu.op = op;
10443 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
10444 alu.src[0].sel = treg;
10445 alu.src[0].chan = 1;
10446 alu.src[1].sel = treg;
10447 alu.src[1].chan = 2;
10448 alu.last = 1;
10449 r = r600_bytecode_add_alu(ctx->bc, &alu);
10450 if (r)
10451 return r;
10452 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10453 alu.op = ALU_OP1_MOV;
10454 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
10455 alu.src[0].sel = treg;
10456 alu.src[0].chan = 0;
10457 alu.last = 1;
10458 r = r600_bytecode_add_alu(ctx->bc, &alu);
10459 if (r)
10460 return r;
10461 return 0;
10462 }
10463
10464 /* result.y = mul_high a, b
10465 result.x = mul a,b
10466 result.y += a.x * b.y + a.y * b.x;
10467 */
10468 static int egcm_u64mul(struct r600_shader_ctx *ctx)
10469 {
10470 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10471 struct r600_bytecode_alu alu;
10472 int r;
10473 int treg = ctx->temp_reg;
10474
10475 /* temp.x = mul_lo a.x, b.x */
10476 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10477 alu.op = ALU_OP2_MULLO_UINT;
10478 alu.dst.sel = treg;
10479 alu.dst.chan = 0;
10480 alu.dst.write = 1;
10481 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10482 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10483 r = emit_mul_int_op(ctx->bc, &alu);
10484 if (r)
10485 return r;
10486
10487 /* temp.y = mul_hi a.x, b.x */
10488 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10489 alu.op = ALU_OP2_MULHI_UINT;
10490 alu.dst.sel = treg;
10491 alu.dst.chan = 1;
10492 alu.dst.write = 1;
10493 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10494 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10495 r = emit_mul_int_op(ctx->bc, &alu);
10496 if (r)
10497 return r;
10498
10499 /* temp.z = mul a.x, b.y */
10500 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10501 alu.op = ALU_OP2_MULLO_UINT;
10502 alu.dst.sel = treg;
10503 alu.dst.chan = 2;
10504 alu.dst.write = 1;
10505 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10506 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
10507 r = emit_mul_int_op(ctx->bc, &alu);
10508 if (r)
10509 return r;
10510
10511 /* temp.w = mul a.y, b.x */
10512 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10513 alu.op = ALU_OP2_MULLO_UINT;
10514 alu.dst.sel = treg;
10515 alu.dst.chan = 3;
10516 alu.dst.write = 1;
10517 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
10518 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10519 r = emit_mul_int_op(ctx->bc, &alu);
10520 if (r)
10521 return r;
10522
10523 /* temp.z = temp.z + temp.w */
10524 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10525 alu.op = ALU_OP2_ADD_INT;
10526 alu.dst.sel = treg;
10527 alu.dst.chan = 2;
10528 alu.dst.write = 1;
10529 alu.src[0].sel = treg;
10530 alu.src[0].chan = 2;
10531 alu.src[1].sel = treg;
10532 alu.src[1].chan = 3;
10533 alu.last = 1;
10534 r = r600_bytecode_add_alu(ctx->bc, &alu);
10535 if (r)
10536 return r;
10537
10538 /* temp.y = temp.y + temp.z */
10539 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10540 alu.op = ALU_OP2_ADD_INT;
10541 alu.dst.sel = treg;
10542 alu.dst.chan = 1;
10543 alu.dst.write = 1;
10544 alu.src[0].sel = treg;
10545 alu.src[0].chan = 1;
10546 alu.src[1].sel = treg;
10547 alu.src[1].chan = 2;
10548 alu.last = 1;
10549 r = r600_bytecode_add_alu(ctx->bc, &alu);
10550 if (r)
10551 return r;
10552
10553 /* dst.x = temp.x */
10554 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10555 alu.op = ALU_OP1_MOV;
10556 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
10557 alu.src[0].sel = treg;
10558 alu.src[0].chan = 0;
10559 r = r600_bytecode_add_alu(ctx->bc, &alu);
10560 if (r)
10561 return r;
10562
10563 /* dst.y = temp.y */
10564 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10565 alu.op = ALU_OP1_MOV;
10566 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
10567 alu.src[0].sel = treg;
10568 alu.src[0].chan = 1;
10569 alu.last = 1;
10570 r = r600_bytecode_add_alu(ctx->bc, &alu);
10571 if (r)
10572 return r;
10573
10574 return 0;
10575 }
10576
10577 static int emit_u64sge(struct r600_shader_ctx *ctx,
10578 int treg,
10579 int src0_sel, int src0_base_chan,
10580 int src1_sel, int src1_base_chan)
10581 {
10582 int r;
10583 /* for 64-bit sge */
10584 /* result = (src0.y > src1.y) || ((src0.y == src1.y) && src0.x >= src1.x)) */
10585 r = single_alu_op2(ctx, ALU_OP2_SETGT_UINT,
10586 treg, 1,
10587 src0_sel, src0_base_chan + 1,
10588 src1_sel, src1_base_chan + 1);
10589 if (r)
10590 return r;
10591
10592 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
10593 treg, 0,
10594 src0_sel, src0_base_chan,
10595 src1_sel, src1_base_chan);
10596 if (r)
10597 return r;
10598
10599 r = single_alu_op2(ctx, ALU_OP2_SETE_INT,
10600 treg, 2,
10601 src0_sel, src0_base_chan + 1,
10602 src1_sel, src1_base_chan + 1);
10603 if (r)
10604 return r;
10605
10606 r = single_alu_op2(ctx, ALU_OP2_AND_INT,
10607 treg, 0,
10608 treg, 0,
10609 treg, 2);
10610 if (r)
10611 return r;
10612
10613 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
10614 treg, 0,
10615 treg, 0,
10616 treg, 1);
10617 if (r)
10618 return r;
10619 return 0;
10620 }
10621
10622 /* this isn't a complete div it's just enough for qbo shader to work */
10623 static int egcm_u64div(struct r600_shader_ctx *ctx)
10624 {
10625 struct r600_bytecode_alu alu;
10626 struct r600_bytecode_alu_src alu_num_hi, alu_num_lo, alu_denom_hi, alu_denom_lo, alu_src;
10627 int r, i;
10628 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10629
10630 /* make sure we are dividing my a const with 0 in the high bits */
10631 if (ctx->src[1].sel != V_SQ_ALU_SRC_LITERAL)
10632 return -1;
10633 if (ctx->src[1].value[ctx->src[1].swizzle[1]] != 0)
10634 return -1;
10635 /* make sure we are doing one division */
10636 if (inst->Dst[0].Register.WriteMask != 0x3)
10637 return -1;
10638
10639 /* emit_if uses ctx->temp_reg so we can't */
10640 int treg = r600_get_temp(ctx);
10641 int tmp_num = r600_get_temp(ctx);
10642 int sub_tmp = r600_get_temp(ctx);
10643
10644 /* tmp quot are tmp_num.zw */
10645 r600_bytecode_src(&alu_num_lo, &ctx->src[0], 0);
10646 r600_bytecode_src(&alu_num_hi, &ctx->src[0], 1);
10647 r600_bytecode_src(&alu_denom_lo, &ctx->src[1], 0);
10648 r600_bytecode_src(&alu_denom_hi, &ctx->src[1], 1);
10649
10650 /* MOV tmp_num.xy, numerator */
10651 r = single_alu_op2(ctx, ALU_OP1_MOV,
10652 tmp_num, 0,
10653 alu_num_lo.sel, alu_num_lo.chan,
10654 0, 0);
10655 if (r)
10656 return r;
10657 r = single_alu_op2(ctx, ALU_OP1_MOV,
10658 tmp_num, 1,
10659 alu_num_hi.sel, alu_num_hi.chan,
10660 0, 0);
10661 if (r)
10662 return r;
10663
10664 r = single_alu_op2(ctx, ALU_OP1_MOV,
10665 tmp_num, 2,
10666 V_SQ_ALU_SRC_LITERAL, 0,
10667 0, 0);
10668 if (r)
10669 return r;
10670
10671 r = single_alu_op2(ctx, ALU_OP1_MOV,
10672 tmp_num, 3,
10673 V_SQ_ALU_SRC_LITERAL, 0,
10674 0, 0);
10675 if (r)
10676 return r;
10677
10678 /* treg 0 is log2_denom */
10679 /* normally this gets the MSB for the denom high value
10680 - however we know this will always be 0 here. */
10681 r = single_alu_op2(ctx,
10682 ALU_OP1_MOV,
10683 treg, 0,
10684 V_SQ_ALU_SRC_LITERAL, 32,
10685 0, 0);
10686 if (r)
10687 return r;
10688
10689 /* normally check demon hi for 0, but we know it is already */
10690 /* t0.z = num_hi >= denom_lo */
10691 r = single_alu_op2(ctx,
10692 ALU_OP2_SETGE_UINT,
10693 treg, 1,
10694 alu_num_hi.sel, alu_num_hi.chan,
10695 V_SQ_ALU_SRC_LITERAL, alu_denom_lo.value);
10696 if (r)
10697 return r;
10698
10699 memset(&alu_src, 0, sizeof(alu_src));
10700 alu_src.sel = treg;
10701 alu_src.chan = 1;
10702 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
10703 if (r)
10704 return r;
10705
10706 /* for loops in here */
10707 /* get msb t0.x = msb(src[1].x) first */
10708 int msb_lo = util_last_bit(alu_denom_lo.value);
10709 r = single_alu_op2(ctx, ALU_OP1_MOV,
10710 treg, 0,
10711 V_SQ_ALU_SRC_LITERAL, msb_lo,
10712 0, 0);
10713 if (r)
10714 return r;
10715
10716 /* unroll the asm here */
10717 for (i = 0; i < 31; i++) {
10718 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
10719 treg, 2,
10720 V_SQ_ALU_SRC_LITERAL, i,
10721 treg, 0);
10722 if (r)
10723 return r;
10724
10725 /* we can do this on the CPU */
10726 uint32_t denom_lo_shl = alu_denom_lo.value << (31 - i);
10727 /* t0.z = tmp_num.y >= t0.z */
10728 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
10729 treg, 1,
10730 tmp_num, 1,
10731 V_SQ_ALU_SRC_LITERAL, denom_lo_shl);
10732 if (r)
10733 return r;
10734
10735 r = single_alu_op2(ctx, ALU_OP2_AND_INT,
10736 treg, 1,
10737 treg, 1,
10738 treg, 2);
10739 if (r)
10740 return r;
10741
10742 memset(&alu_src, 0, sizeof(alu_src));
10743 alu_src.sel = treg;
10744 alu_src.chan = 1;
10745 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
10746 if (r)
10747 return r;
10748
10749 r = single_alu_op2(ctx, ALU_OP2_SUB_INT,
10750 tmp_num, 1,
10751 tmp_num, 1,
10752 V_SQ_ALU_SRC_LITERAL, denom_lo_shl);
10753 if (r)
10754 return r;
10755
10756 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
10757 tmp_num, 3,
10758 tmp_num, 3,
10759 V_SQ_ALU_SRC_LITERAL, 1U << (31 - i));
10760 if (r)
10761 return r;
10762
10763 r = tgsi_endif(ctx);
10764 if (r)
10765 return r;
10766 }
10767
10768 /* log2_denom is always <= 31, so manually peel the last loop
10769 * iteration.
10770 */
10771 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
10772 treg, 1,
10773 tmp_num, 1,
10774 V_SQ_ALU_SRC_LITERAL, alu_denom_lo.value);
10775 if (r)
10776 return r;
10777
10778 memset(&alu_src, 0, sizeof(alu_src));
10779 alu_src.sel = treg;
10780 alu_src.chan = 1;
10781 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
10782 if (r)
10783 return r;
10784
10785 r = single_alu_op2(ctx, ALU_OP2_SUB_INT,
10786 tmp_num, 1,
10787 tmp_num, 1,
10788 V_SQ_ALU_SRC_LITERAL, alu_denom_lo.value);
10789 if (r)
10790 return r;
10791
10792 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
10793 tmp_num, 3,
10794 tmp_num, 3,
10795 V_SQ_ALU_SRC_LITERAL, 1U);
10796 if (r)
10797 return r;
10798 r = tgsi_endif(ctx);
10799 if (r)
10800 return r;
10801
10802 r = tgsi_endif(ctx);
10803 if (r)
10804 return r;
10805
10806 /* onto the second loop to unroll */
10807 for (i = 0; i < 31; i++) {
10808 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
10809 treg, 1,
10810 V_SQ_ALU_SRC_LITERAL, (63 - (31 - i)),
10811 treg, 0);
10812 if (r)
10813 return r;
10814
10815 uint64_t denom_shl = (uint64_t)alu_denom_lo.value << (31 - i);
10816 r = single_alu_op2(ctx, ALU_OP1_MOV,
10817 treg, 2,
10818 V_SQ_ALU_SRC_LITERAL, (denom_shl & 0xffffffff),
10819 0, 0);
10820 if (r)
10821 return r;
10822
10823 r = single_alu_op2(ctx, ALU_OP1_MOV,
10824 treg, 3,
10825 V_SQ_ALU_SRC_LITERAL, (denom_shl >> 32),
10826 0, 0);
10827 if (r)
10828 return r;
10829
10830 r = emit_u64sge(ctx, sub_tmp,
10831 tmp_num, 0,
10832 treg, 2);
10833 if (r)
10834 return r;
10835
10836 r = single_alu_op2(ctx, ALU_OP2_AND_INT,
10837 treg, 1,
10838 treg, 1,
10839 sub_tmp, 0);
10840 if (r)
10841 return r;
10842
10843 memset(&alu_src, 0, sizeof(alu_src));
10844 alu_src.sel = treg;
10845 alu_src.chan = 1;
10846 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
10847 if (r)
10848 return r;
10849
10850
10851 r = emit_u64add(ctx, ALU_OP2_SUB_INT,
10852 sub_tmp,
10853 tmp_num, 0,
10854 treg, 2);
10855 if (r)
10856 return r;
10857
10858 r = single_alu_op2(ctx, ALU_OP1_MOV,
10859 tmp_num, 0,
10860 sub_tmp, 0,
10861 0, 0);
10862 if (r)
10863 return r;
10864
10865 r = single_alu_op2(ctx, ALU_OP1_MOV,
10866 tmp_num, 1,
10867 sub_tmp, 1,
10868 0, 0);
10869 if (r)
10870 return r;
10871
10872 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
10873 tmp_num, 2,
10874 tmp_num, 2,
10875 V_SQ_ALU_SRC_LITERAL, 1U << (31 - i));
10876 if (r)
10877 return r;
10878
10879 r = tgsi_endif(ctx);
10880 if (r)
10881 return r;
10882 }
10883
10884 /* log2_denom is always <= 63, so manually peel the last loop
10885 * iteration.
10886 */
10887 uint64_t denom_shl = (uint64_t)alu_denom_lo.value;
10888 r = single_alu_op2(ctx, ALU_OP1_MOV,
10889 treg, 2,
10890 V_SQ_ALU_SRC_LITERAL, (denom_shl & 0xffffffff),
10891 0, 0);
10892 if (r)
10893 return r;
10894
10895 r = single_alu_op2(ctx, ALU_OP1_MOV,
10896 treg, 3,
10897 V_SQ_ALU_SRC_LITERAL, (denom_shl >> 32),
10898 0, 0);
10899 if (r)
10900 return r;
10901
10902 r = emit_u64sge(ctx, sub_tmp,
10903 tmp_num, 0,
10904 treg, 2);
10905 if (r)
10906 return r;
10907
10908 memset(&alu_src, 0, sizeof(alu_src));
10909 alu_src.sel = sub_tmp;
10910 alu_src.chan = 0;
10911 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
10912 if (r)
10913 return r;
10914
10915 r = emit_u64add(ctx, ALU_OP2_SUB_INT,
10916 sub_tmp,
10917 tmp_num, 0,
10918 treg, 2);
10919 if (r)
10920 return r;
10921
10922 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
10923 tmp_num, 2,
10924 tmp_num, 2,
10925 V_SQ_ALU_SRC_LITERAL, 1U);
10926 if (r)
10927 return r;
10928 r = tgsi_endif(ctx);
10929 if (r)
10930 return r;
10931
10932 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10933 alu.op = ALU_OP1_MOV;
10934 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
10935 alu.src[0].sel = tmp_num;
10936 alu.src[0].chan = 2;
10937 r = r600_bytecode_add_alu(ctx->bc, &alu);
10938 if (r)
10939 return r;
10940
10941 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10942 alu.op = ALU_OP1_MOV;
10943 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
10944 alu.src[0].sel = tmp_num;
10945 alu.src[0].chan = 3;
10946 alu.last = 1;
10947 r = r600_bytecode_add_alu(ctx->bc, &alu);
10948 if (r)
10949 return r;
10950 return 0;
10951 }
10952
10953 static int egcm_u64sne(struct r600_shader_ctx *ctx)
10954 {
10955 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10956 struct r600_bytecode_alu alu;
10957 int r;
10958 int treg = ctx->temp_reg;
10959
10960 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10961 alu.op = ALU_OP2_SETNE_INT;
10962 alu.dst.sel = treg;
10963 alu.dst.chan = 0;
10964 alu.dst.write = 1;
10965 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10966 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10967 r = r600_bytecode_add_alu(ctx->bc, &alu);
10968 if (r)
10969 return r;
10970
10971 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10972 alu.op = ALU_OP2_SETNE_INT;
10973 alu.dst.sel = treg;
10974 alu.dst.chan = 1;
10975 alu.dst.write = 1;
10976 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
10977 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
10978 alu.last = 1;
10979 r = r600_bytecode_add_alu(ctx->bc, &alu);
10980 if (r)
10981 return r;
10982
10983 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10984 alu.op = ALU_OP2_OR_INT;
10985 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
10986 alu.src[0].sel = treg;
10987 alu.src[0].chan = 0;
10988 alu.src[1].sel = treg;
10989 alu.src[1].chan = 1;
10990 alu.last = 1;
10991 r = r600_bytecode_add_alu(ctx->bc, &alu);
10992 if (r)
10993 return r;
10994 return 0;
10995 }
10996
10997 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
10998 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
10999 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
11000 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
11001
11002 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
11003
11004 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
11005 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
11006 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
11007 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
11008 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
11009 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11010 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11011 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
11012 /* MIN_DX10 returns non-nan result if one src is NaN, MIN returns NaN */
11013 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
11014 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
11015 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
11016 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
11017 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
11018 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
11019 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
11020 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
11021 [21] = { ALU_OP0_NOP, tgsi_unsupported},
11022 [22] = { ALU_OP0_NOP, tgsi_unsupported},
11023 [23] = { ALU_OP0_NOP, tgsi_unsupported},
11024 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
11025 [25] = { ALU_OP0_NOP, tgsi_unsupported},
11026 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
11027 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
11028 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
11029 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
11030 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
11031 [31] = { ALU_OP0_NOP, tgsi_unsupported},
11032 [32] = { ALU_OP0_NOP, tgsi_unsupported},
11033 [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_unsupported},
11034 [34] = { ALU_OP0_NOP, tgsi_unsupported},
11035 [35] = { ALU_OP0_NOP, tgsi_unsupported},
11036 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
11037 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11038 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11039 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
11040 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
11041 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
11042 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
11043 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11044 [44] = { ALU_OP0_NOP, tgsi_unsupported},
11045 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
11046 [46] = { ALU_OP0_NOP, tgsi_unsupported},
11047 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
11048 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
11049 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
11050 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
11051 [51] = { ALU_OP0_NOP, tgsi_unsupported},
11052 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
11053 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
11054 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
11055 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
11056 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
11057 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
11058 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11059 [59] = { ALU_OP0_NOP, tgsi_unsupported},
11060 [60] = { ALU_OP0_NOP, tgsi_unsupported},
11061 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
11062 [62] = { ALU_OP0_NOP, tgsi_unsupported},
11063 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
11064 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
11065 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
11066 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
11067 [67] = { ALU_OP0_NOP, tgsi_unsupported},
11068 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11069 [69] = { ALU_OP0_NOP, tgsi_unsupported},
11070 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
11071 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11072 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11073 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
11074 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
11075 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
11076 [76] = { ALU_OP0_NOP, tgsi_unsupported},
11077 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
11078 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
11079 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
11080 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
11081 [81] = { ALU_OP0_NOP, tgsi_unsupported},
11082 [82] = { ALU_OP0_NOP, tgsi_unsupported},
11083 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
11084 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
11085 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
11086 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
11087 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
11088 [88] = { ALU_OP0_NOP, tgsi_unsupported},
11089 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
11090 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
11091 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
11092 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
11093 [93] = { ALU_OP0_NOP, tgsi_unsupported},
11094 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
11095 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11096 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
11097 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
11098 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
11099 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
11100 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11101 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
11102 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11103 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11104 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
11105 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
11106 [106] = { ALU_OP0_NOP, tgsi_unsupported},
11107 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
11108 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
11109 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
11110 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
11111 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
11112 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
11113 [113] = { ALU_OP0_NOP, tgsi_unsupported},
11114 [114] = { ALU_OP0_NOP, tgsi_unsupported},
11115 [115] = { ALU_OP0_NOP, tgsi_unsupported},
11116 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
11117 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
11118 [TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
11119 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
11120 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
11121 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
11122 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
11123 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
11124 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
11125 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
11126 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
11127 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
11128 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
11129 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
11130 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
11131 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
11132 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
11133 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
11134 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
11135 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
11136 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
11137 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
11138 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
11139 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
11140 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
11141 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11142 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
11143 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
11144 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11145 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
11146 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
11147 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
11148 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
11149 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
11150 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
11151 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
11152 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
11153 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
11154 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
11155 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
11156 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
11157 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
11158 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
11159 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
11160 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
11161 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
11162 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
11163 [163] = { ALU_OP0_NOP, tgsi_unsupported},
11164 [164] = { ALU_OP0_NOP, tgsi_unsupported},
11165 [165] = { ALU_OP0_NOP, tgsi_unsupported},
11166 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
11167 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
11168 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
11169 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
11170 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
11171 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
11172 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
11173 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
11174 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
11175 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
11176 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
11177 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
11178 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11179 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11180 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
11181 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
11182 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
11183 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
11184 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
11185 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
11186 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
11187 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
11188 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
11189 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
11190 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
11191 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
11192 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
11193 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
11194 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
11195 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
11196 };
11197
11198 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
11199 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
11200 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
11201 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
11202 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
11203 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
11204 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
11205 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
11206 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
11207 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
11208 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11209 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11210 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
11211 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
11212 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
11213 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
11214 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
11215 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
11216 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
11217 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
11218 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
11219 [21] = { ALU_OP0_NOP, tgsi_unsupported},
11220 [22] = { ALU_OP0_NOP, tgsi_unsupported},
11221 [23] = { ALU_OP0_NOP, tgsi_unsupported},
11222 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
11223 [25] = { ALU_OP0_NOP, tgsi_unsupported},
11224 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
11225 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
11226 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
11227 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
11228 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
11229 [31] = { ALU_OP0_NOP, tgsi_unsupported},
11230 [32] = { ALU_OP0_NOP, tgsi_unsupported},
11231 [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_clock},
11232 [34] = { ALU_OP0_NOP, tgsi_unsupported},
11233 [35] = { ALU_OP0_NOP, tgsi_unsupported},
11234 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
11235 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11236 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11237 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
11238 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
11239 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
11240 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
11241 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11242 [44] = { ALU_OP0_NOP, tgsi_unsupported},
11243 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
11244 [46] = { ALU_OP0_NOP, tgsi_unsupported},
11245 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
11246 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
11247 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
11248 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
11249 [51] = { ALU_OP0_NOP, tgsi_unsupported},
11250 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
11251 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
11252 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
11253 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
11254 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
11255 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
11256 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11257 [59] = { ALU_OP0_NOP, tgsi_unsupported},
11258 [60] = { ALU_OP0_NOP, tgsi_unsupported},
11259 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
11260 [62] = { ALU_OP0_NOP, tgsi_unsupported},
11261 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
11262 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
11263 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
11264 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
11265 [67] = { ALU_OP0_NOP, tgsi_unsupported},
11266 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11267 [69] = { ALU_OP0_NOP, tgsi_unsupported},
11268 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
11269 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11270 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11271 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
11272 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
11273 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
11274 [76] = { ALU_OP0_NOP, tgsi_unsupported},
11275 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
11276 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
11277 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11278 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11279 [82] = { ALU_OP0_NOP, tgsi_unsupported},
11280 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
11281 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
11282 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
11283 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
11284 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
11285 [88] = { ALU_OP0_NOP, tgsi_unsupported},
11286 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
11287 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
11288 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
11289 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
11290 [93] = { ALU_OP0_NOP, tgsi_unsupported},
11291 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
11292 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11293 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
11294 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
11295 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
11296 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
11297 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11298 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
11299 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11300 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11301 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
11302 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
11303 [106] = { ALU_OP0_NOP, tgsi_unsupported},
11304 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
11305 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
11306 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
11307 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
11308 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
11309 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
11310 [113] = { ALU_OP0_NOP, tgsi_unsupported},
11311 [114] = { ALU_OP0_NOP, tgsi_unsupported},
11312 [115] = { ALU_OP0_NOP, tgsi_unsupported},
11313 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
11314 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
11315 /* Refer below for TGSI_OPCODE_DFMA */
11316 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
11317 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
11318 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
11319 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
11320 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
11321 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
11322 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
11323 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
11324 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
11325 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
11326 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
11327 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
11328 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
11329 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
11330 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
11331 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
11332 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
11333 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
11334 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
11335 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
11336 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
11337 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
11338 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11339 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
11340 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
11341 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11342 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
11343 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
11344 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
11345 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
11346 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
11347 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
11348 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
11349 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
11350 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
11351 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
11352 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
11353 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
11354 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
11355 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
11356 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
11357 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
11358 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
11359 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
11360 [163] = { ALU_OP0_NOP, tgsi_unsupported},
11361 [164] = { ALU_OP0_NOP, tgsi_unsupported},
11362 [165] = { ALU_OP0_NOP, tgsi_unsupported},
11363 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
11364 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
11365 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
11366 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
11367 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
11368 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
11369 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
11370 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
11371 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
11372 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
11373 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
11374 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
11375 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11376 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11377 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
11378 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
11379 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
11380 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
11381 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
11382 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
11383 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
11384 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
11385 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
11386 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
11387 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
11388 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
11389 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
11390 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
11391 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
11392 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
11393 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
11394 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
11395 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
11396 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
11397 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
11398 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
11399 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
11400 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
11401 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
11402 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
11403 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
11404 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
11405 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
11406 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
11407 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
11408 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
11409 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
11410 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
11411 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
11412 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
11413 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
11414 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
11415 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
11416 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
11417 [TGSI_OPCODE_U64SNE] = { ALU_OP0_NOP, egcm_u64sne },
11418 [TGSI_OPCODE_U64ADD] = { ALU_OP0_NOP, egcm_u64add },
11419 [TGSI_OPCODE_U64MUL] = { ALU_OP0_NOP, egcm_u64mul },
11420 [TGSI_OPCODE_U64DIV] = { ALU_OP0_NOP, egcm_u64div },
11421 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
11422 };
11423
11424 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
11425 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
11426 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
11427 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
11428 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
11429 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
11430 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
11431 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
11432 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
11433 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
11434 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11435 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11436 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
11437 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
11438 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
11439 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
11440 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
11441 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
11442 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
11443 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
11444 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
11445 [21] = { ALU_OP0_NOP, tgsi_unsupported},
11446 [22] = { ALU_OP0_NOP, tgsi_unsupported},
11447 [23] = { ALU_OP0_NOP, tgsi_unsupported},
11448 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
11449 [25] = { ALU_OP0_NOP, tgsi_unsupported},
11450 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
11451 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
11452 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
11453 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
11454 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
11455 [31] = { ALU_OP0_NOP, tgsi_unsupported},
11456 [32] = { ALU_OP0_NOP, tgsi_unsupported},
11457 [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_clock},
11458 [34] = { ALU_OP0_NOP, tgsi_unsupported},
11459 [35] = { ALU_OP0_NOP, tgsi_unsupported},
11460 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
11461 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11462 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11463 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
11464 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
11465 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
11466 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
11467 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11468 [44] = { ALU_OP0_NOP, tgsi_unsupported},
11469 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
11470 [46] = { ALU_OP0_NOP, tgsi_unsupported},
11471 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
11472 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
11473 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
11474 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
11475 [51] = { ALU_OP0_NOP, tgsi_unsupported},
11476 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
11477 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
11478 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
11479 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
11480 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
11481 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
11482 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11483 [59] = { ALU_OP0_NOP, tgsi_unsupported},
11484 [60] = { ALU_OP0_NOP, tgsi_unsupported},
11485 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
11486 [62] = { ALU_OP0_NOP, tgsi_unsupported},
11487 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
11488 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
11489 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
11490 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
11491 [67] = { ALU_OP0_NOP, tgsi_unsupported},
11492 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11493 [69] = { ALU_OP0_NOP, tgsi_unsupported},
11494 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
11495 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11496 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11497 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
11498 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
11499 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
11500 [76] = { ALU_OP0_NOP, tgsi_unsupported},
11501 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
11502 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
11503 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11504 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11505 [82] = { ALU_OP0_NOP, tgsi_unsupported},
11506 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
11507 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
11508 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
11509 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
11510 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
11511 [88] = { ALU_OP0_NOP, tgsi_unsupported},
11512 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
11513 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
11514 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
11515 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
11516 [93] = { ALU_OP0_NOP, tgsi_unsupported},
11517 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
11518 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11519 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
11520 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
11521 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
11522 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
11523 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11524 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
11525 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11526 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11527 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
11528 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
11529 [106] = { ALU_OP0_NOP, tgsi_unsupported},
11530 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
11531 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
11532 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
11533 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
11534 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
11535 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
11536 [113] = { ALU_OP0_NOP, tgsi_unsupported},
11537 [114] = { ALU_OP0_NOP, tgsi_unsupported},
11538 [115] = { ALU_OP0_NOP, tgsi_unsupported},
11539 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
11540 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
11541 /* Refer below for TGSI_OPCODE_DFMA */
11542 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
11543 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
11544 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
11545 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
11546 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
11547 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
11548 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
11549 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
11550 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
11551 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
11552 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
11553 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
11554 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
11555 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
11556 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
11557 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
11558 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
11559 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
11560 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
11561 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
11562 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
11563 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
11564 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11565 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
11566 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
11567 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11568 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
11569 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
11570 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
11571 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
11572 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
11573 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
11574 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
11575 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
11576 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
11577 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
11578 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
11579 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
11580 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
11581 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
11582 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
11583 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
11584 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
11585 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
11586 [163] = { ALU_OP0_NOP, tgsi_unsupported},
11587 [164] = { ALU_OP0_NOP, tgsi_unsupported},
11588 [165] = { ALU_OP0_NOP, tgsi_unsupported},
11589 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
11590 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
11591 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
11592 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
11593 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
11594 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
11595 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
11596 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
11597 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
11598 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
11599 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
11600 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
11601 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11602 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11603 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
11604 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
11605 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
11606 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
11607 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
11608 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
11609 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
11610 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
11611 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
11612 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
11613 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
11614 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
11615 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
11616 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
11617 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
11618 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
11619 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
11620 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
11621 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
11622 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
11623 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
11624 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
11625 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
11626 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
11627 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
11628 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
11629 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
11630 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
11631 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
11632 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
11633 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
11634 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
11635 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
11636 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
11637 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
11638 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
11639 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
11640 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
11641 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
11642 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
11643 [TGSI_OPCODE_U64SNE] = { ALU_OP0_NOP, egcm_u64sne },
11644 [TGSI_OPCODE_U64ADD] = { ALU_OP0_NOP, egcm_u64add },
11645 [TGSI_OPCODE_U64MUL] = { ALU_OP0_NOP, egcm_u64mul },
11646 [TGSI_OPCODE_U64DIV] = { ALU_OP0_NOP, egcm_u64div },
11647 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
11648 };