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r600g: add support for optionally using non-IEEE mul ops
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
193
194 /* disable SB for shaders using doubles */
195 use_sb &= !shader->shader.uses_doubles;
196
197 /* Check if the bytecode has already been built. */
198 if (!shader->shader.bc.bytecode) {
199 r = r600_bytecode_build(&shader->shader.bc);
200 if (r) {
201 R600_ERR("building bytecode failed !\n");
202 goto error;
203 }
204 }
205
206 if (dump && !sb_disasm) {
207 fprintf(stderr, "--------------------------------------------------------------\n");
208 r600_bytecode_disasm(&shader->shader.bc);
209 fprintf(stderr, "______________________________________________________________\n");
210 } else if ((dump && sb_disasm) || use_sb) {
211 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
212 dump, use_sb);
213 if (r) {
214 R600_ERR("r600_sb_bytecode_process failed !\n");
215 goto error;
216 }
217 }
218
219 if (shader->gs_copy_shader) {
220 if (dump) {
221 // dump copy shader
222 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
223 &shader->gs_copy_shader->shader, dump, 0);
224 if (r)
225 goto error;
226 }
227
228 if ((r = store_shader(ctx, shader->gs_copy_shader)))
229 goto error;
230 }
231
232 /* Store the shader in a buffer. */
233 if ((r = store_shader(ctx, shader)))
234 goto error;
235
236 /* Build state. */
237 switch (shader->shader.processor_type) {
238 case PIPE_SHADER_TESS_CTRL:
239 evergreen_update_hs_state(ctx, shader);
240 break;
241 case PIPE_SHADER_TESS_EVAL:
242 if (key.tes.as_es)
243 evergreen_update_es_state(ctx, shader);
244 else
245 evergreen_update_vs_state(ctx, shader);
246 break;
247 case PIPE_SHADER_GEOMETRY:
248 if (rctx->b.chip_class >= EVERGREEN) {
249 evergreen_update_gs_state(ctx, shader);
250 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
251 } else {
252 r600_update_gs_state(ctx, shader);
253 r600_update_vs_state(ctx, shader->gs_copy_shader);
254 }
255 break;
256 case PIPE_SHADER_VERTEX:
257 export_shader = key.vs.as_es;
258 if (rctx->b.chip_class >= EVERGREEN) {
259 if (key.vs.as_ls)
260 evergreen_update_ls_state(ctx, shader);
261 else if (key.vs.as_es)
262 evergreen_update_es_state(ctx, shader);
263 else
264 evergreen_update_vs_state(ctx, shader);
265 } else {
266 if (export_shader)
267 r600_update_es_state(ctx, shader);
268 else
269 r600_update_vs_state(ctx, shader);
270 }
271 break;
272 case PIPE_SHADER_FRAGMENT:
273 if (rctx->b.chip_class >= EVERGREEN) {
274 evergreen_update_ps_state(ctx, shader);
275 } else {
276 r600_update_ps_state(ctx, shader);
277 }
278 break;
279 default:
280 r = -EINVAL;
281 goto error;
282 }
283 return 0;
284
285 error:
286 r600_pipe_shader_destroy(ctx, shader);
287 return r;
288 }
289
290 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
291 {
292 r600_resource_reference(&shader->bo, NULL);
293 r600_bytecode_clear(&shader->shader.bc);
294 r600_release_command_buffer(&shader->command_buffer);
295 }
296
297 /*
298 * tgsi -> r600 shader
299 */
300 struct r600_shader_tgsi_instruction;
301
302 struct r600_shader_src {
303 unsigned sel;
304 unsigned swizzle[4];
305 unsigned neg;
306 unsigned abs;
307 unsigned rel;
308 unsigned kc_bank;
309 boolean kc_rel; /* true if cache bank is indexed */
310 uint32_t value[4];
311 };
312
313 struct eg_interp {
314 boolean enabled;
315 unsigned ij_index;
316 };
317
318 struct r600_shader_ctx {
319 struct tgsi_shader_info info;
320 struct tgsi_parse_context parse;
321 const struct tgsi_token *tokens;
322 unsigned type;
323 unsigned file_offset[TGSI_FILE_COUNT];
324 unsigned temp_reg;
325 const struct r600_shader_tgsi_instruction *inst_info;
326 struct r600_bytecode *bc;
327 struct r600_shader *shader;
328 struct r600_shader_src src[4];
329 uint32_t *literals;
330 uint32_t nliterals;
331 uint32_t max_driver_temp_used;
332 /* needed for evergreen interpolation */
333 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
334 /* evergreen/cayman also store sample mask in face register */
335 int face_gpr;
336 /* sample id is .w component stored in fixed point position register */
337 int fixed_pt_position_gpr;
338 int colors_used;
339 boolean clip_vertex_write;
340 unsigned cv_output;
341 unsigned edgeflag_output;
342 int fragcoord_input;
343 int native_integers;
344 int next_ring_offset;
345 int gs_out_ring_offset;
346 int gs_next_vertex;
347 struct r600_shader *gs_for_vs;
348 int gs_export_gpr_tregs[4];
349 const struct pipe_stream_output_info *gs_stream_output_info;
350 unsigned enabled_stream_buffers_mask;
351 unsigned tess_input_info; /* temp with tess input offsets */
352 unsigned tess_output_info; /* temp with tess input offsets */
353 };
354
355 struct r600_shader_tgsi_instruction {
356 unsigned op;
357 int (*process)(struct r600_shader_ctx *ctx);
358 };
359
360 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
361 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
362 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
363 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
364 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
365 static int tgsi_else(struct r600_shader_ctx *ctx);
366 static int tgsi_endif(struct r600_shader_ctx *ctx);
367 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
368 static int tgsi_endloop(struct r600_shader_ctx *ctx);
369 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
370 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
371 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
372 unsigned int dst_reg);
373 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
374 const struct r600_shader_src *shader_src,
375 unsigned chan);
376 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
377 unsigned dst_reg);
378
379 static int tgsi_last_instruction(unsigned writemask)
380 {
381 int i, lasti = 0;
382
383 for (i = 0; i < 4; i++) {
384 if (writemask & (1 << i)) {
385 lasti = i;
386 }
387 }
388 return lasti;
389 }
390
391 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
392 {
393 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
394 unsigned j;
395
396 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
397 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
398 return -EINVAL;
399 }
400 if (i->Instruction.Predicate) {
401 R600_ERR("predicate unsupported\n");
402 return -EINVAL;
403 }
404 #if 0
405 if (i->Instruction.Label) {
406 R600_ERR("label unsupported\n");
407 return -EINVAL;
408 }
409 #endif
410 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
411 if (i->Src[j].Register.Dimension) {
412 switch (i->Src[j].Register.File) {
413 case TGSI_FILE_CONSTANT:
414 break;
415 case TGSI_FILE_INPUT:
416 if (ctx->type == PIPE_SHADER_GEOMETRY ||
417 ctx->type == PIPE_SHADER_TESS_CTRL ||
418 ctx->type == PIPE_SHADER_TESS_EVAL)
419 break;
420 case TGSI_FILE_OUTPUT:
421 if (ctx->type == PIPE_SHADER_TESS_CTRL)
422 break;
423 default:
424 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
425 i->Src[j].Register.File,
426 i->Src[j].Register.Dimension);
427 return -EINVAL;
428 }
429 }
430 }
431 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
432 if (i->Dst[j].Register.Dimension) {
433 if (ctx->type == PIPE_SHADER_TESS_CTRL)
434 continue;
435 R600_ERR("unsupported dst (dimension)\n");
436 return -EINVAL;
437 }
438 }
439 return 0;
440 }
441
442 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
443 {
444 if (interpolate == TGSI_INTERPOLATE_COLOR ||
445 interpolate == TGSI_INTERPOLATE_LINEAR ||
446 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
447 {
448 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
449 int loc;
450
451 switch(location) {
452 case TGSI_INTERPOLATE_LOC_CENTER:
453 loc = 1;
454 break;
455 case TGSI_INTERPOLATE_LOC_CENTROID:
456 loc = 2;
457 break;
458 case TGSI_INTERPOLATE_LOC_SAMPLE:
459 default:
460 loc = 0; break;
461 }
462
463 return is_linear * 3 + loc;
464 }
465
466 return -1;
467 }
468
469 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
470 int input)
471 {
472 int i = eg_get_interpolator_index(
473 ctx->shader->input[input].interpolate,
474 ctx->shader->input[input].interpolate_location);
475 assert(i >= 0);
476 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
477 }
478
479 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
480 {
481 int i, r;
482 struct r600_bytecode_alu alu;
483 int gpr = 0, base_chan = 0;
484 int ij_index = ctx->shader->input[input].ij_index;
485
486 /* work out gpr and base_chan from index */
487 gpr = ij_index / 2;
488 base_chan = (2 * (ij_index % 2)) + 1;
489
490 for (i = 0; i < 8; i++) {
491 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
492
493 if (i < 4)
494 alu.op = ALU_OP2_INTERP_ZW;
495 else
496 alu.op = ALU_OP2_INTERP_XY;
497
498 if ((i > 1) && (i < 6)) {
499 alu.dst.sel = ctx->shader->input[input].gpr;
500 alu.dst.write = 1;
501 }
502
503 alu.dst.chan = i % 4;
504
505 alu.src[0].sel = gpr;
506 alu.src[0].chan = (base_chan - (i % 2));
507
508 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
509
510 alu.bank_swizzle_force = SQ_ALU_VEC_210;
511 if ((i % 4) == 3)
512 alu.last = 1;
513 r = r600_bytecode_add_alu(ctx->bc, &alu);
514 if (r)
515 return r;
516 }
517 return 0;
518 }
519
520 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
521 {
522 int i, r;
523 struct r600_bytecode_alu alu;
524
525 for (i = 0; i < 4; i++) {
526 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
527
528 alu.op = ALU_OP1_INTERP_LOAD_P0;
529
530 alu.dst.sel = ctx->shader->input[input].gpr;
531 alu.dst.write = 1;
532
533 alu.dst.chan = i;
534
535 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
536 alu.src[0].chan = i;
537
538 if (i == 3)
539 alu.last = 1;
540 r = r600_bytecode_add_alu(ctx->bc, &alu);
541 if (r)
542 return r;
543 }
544 return 0;
545 }
546
547 /*
548 * Special export handling in shaders
549 *
550 * shader export ARRAY_BASE for EXPORT_POS:
551 * 60 is position
552 * 61 is misc vector
553 * 62, 63 are clip distance vectors
554 *
555 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
556 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
557 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
558 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
559 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
560 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
561 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
562 * exclusive from render target index)
563 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
564 *
565 *
566 * shader export ARRAY_BASE for EXPORT_PIXEL:
567 * 0-7 CB targets
568 * 61 computed Z vector
569 *
570 * The use of the values exported in the computed Z vector are controlled
571 * by DB_SHADER_CONTROL:
572 * Z_EXPORT_ENABLE - Z as a float in RED
573 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
574 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
575 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
576 * DB_SOURCE_FORMAT - export control restrictions
577 *
578 */
579
580
581 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
582 static int r600_spi_sid(struct r600_shader_io * io)
583 {
584 int index, name = io->name;
585
586 /* These params are handled differently, they don't need
587 * semantic indices, so we'll use 0 for them.
588 */
589 if (name == TGSI_SEMANTIC_POSITION ||
590 name == TGSI_SEMANTIC_PSIZE ||
591 name == TGSI_SEMANTIC_EDGEFLAG ||
592 name == TGSI_SEMANTIC_FACE ||
593 name == TGSI_SEMANTIC_SAMPLEMASK)
594 index = 0;
595 else {
596 if (name == TGSI_SEMANTIC_GENERIC) {
597 /* For generic params simply use sid from tgsi */
598 index = io->sid;
599 } else {
600 /* For non-generic params - pack name and sid into 8 bits */
601 index = 0x80 | (name<<3) | (io->sid);
602 }
603
604 /* Make sure that all really used indices have nonzero value, so
605 * we can just compare it to 0 later instead of comparing the name
606 * with different values to detect special cases. */
607 index++;
608 }
609
610 return index;
611 };
612
613 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
614 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
615 {
616 switch (semantic_name) {
617 case TGSI_SEMANTIC_POSITION:
618 return 0;
619 case TGSI_SEMANTIC_PSIZE:
620 return 1;
621 case TGSI_SEMANTIC_CLIPDIST:
622 assert(index <= 1);
623 return 2 + index;
624 case TGSI_SEMANTIC_GENERIC:
625 if (index <= 63-4)
626 return 4 + index - 9;
627 else
628 /* same explanation as in the default statement,
629 * the only user hitting this is st/nine.
630 */
631 return 0;
632
633 /* patch indices are completely separate and thus start from 0 */
634 case TGSI_SEMANTIC_TESSOUTER:
635 return 0;
636 case TGSI_SEMANTIC_TESSINNER:
637 return 1;
638 case TGSI_SEMANTIC_PATCH:
639 return 2 + index;
640
641 default:
642 /* Don't fail here. The result of this function is only used
643 * for LS, TCS, TES, and GS, where legacy GL semantics can't
644 * occur, but this function is called for all vertex shaders
645 * before it's known whether LS will be compiled or not.
646 */
647 return 0;
648 }
649 }
650
651 /* turn input into interpolate on EG */
652 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
653 {
654 int r = 0;
655
656 if (ctx->shader->input[index].spi_sid) {
657 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
658 if (ctx->shader->input[index].interpolate > 0) {
659 evergreen_interp_assign_ij_index(ctx, index);
660 r = evergreen_interp_alu(ctx, index);
661 } else {
662 r = evergreen_interp_flat(ctx, index);
663 }
664 }
665 return r;
666 }
667
668 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
669 {
670 struct r600_bytecode_alu alu;
671 int i, r;
672 int gpr_front = ctx->shader->input[front].gpr;
673 int gpr_back = ctx->shader->input[back].gpr;
674
675 for (i = 0; i < 4; i++) {
676 memset(&alu, 0, sizeof(alu));
677 alu.op = ALU_OP3_CNDGT;
678 alu.is_op3 = 1;
679 alu.dst.write = 1;
680 alu.dst.sel = gpr_front;
681 alu.src[0].sel = ctx->face_gpr;
682 alu.src[1].sel = gpr_front;
683 alu.src[2].sel = gpr_back;
684
685 alu.dst.chan = i;
686 alu.src[1].chan = i;
687 alu.src[2].chan = i;
688 alu.last = (i==3);
689
690 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
691 return r;
692 }
693
694 return 0;
695 }
696
697 /* execute a single slot ALU calculation */
698 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
699 int dst_sel, int dst_chan,
700 int src0_sel, unsigned src0_chan_val,
701 int src1_sel, unsigned src1_chan_val)
702 {
703 struct r600_bytecode_alu alu;
704 int r, i;
705
706 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
707 for (i = 0; i < 4; i++) {
708 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
709 alu.op = op;
710 alu.src[0].sel = src0_sel;
711 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
712 alu.src[0].value = src0_chan_val;
713 else
714 alu.src[0].chan = src0_chan_val;
715 alu.src[1].sel = src1_sel;
716 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
717 alu.src[1].value = src1_chan_val;
718 else
719 alu.src[1].chan = src1_chan_val;
720 alu.dst.sel = dst_sel;
721 alu.dst.chan = i;
722 alu.dst.write = i == dst_chan;
723 alu.last = (i == 3);
724 r = r600_bytecode_add_alu(ctx->bc, &alu);
725 if (r)
726 return r;
727 }
728 return 0;
729 }
730
731 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
732 alu.op = op;
733 alu.src[0].sel = src0_sel;
734 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
735 alu.src[0].value = src0_chan_val;
736 else
737 alu.src[0].chan = src0_chan_val;
738 alu.src[1].sel = src1_sel;
739 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
740 alu.src[1].value = src1_chan_val;
741 else
742 alu.src[1].chan = src1_chan_val;
743 alu.dst.sel = dst_sel;
744 alu.dst.chan = dst_chan;
745 alu.dst.write = 1;
746 alu.last = 1;
747 r = r600_bytecode_add_alu(ctx->bc, &alu);
748 if (r)
749 return r;
750 return 0;
751 }
752
753 /* execute a single slot ALU calculation */
754 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
755 int dst_sel, int dst_chan,
756 int src0_sel, unsigned src0_chan_val,
757 int src1_sel, unsigned src1_chan_val,
758 int src2_sel, unsigned src2_chan_val)
759 {
760 struct r600_bytecode_alu alu;
761 int r;
762
763 /* validate this for other ops */
764 assert(op == ALU_OP3_MULADD_UINT24);
765 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
766 alu.op = op;
767 alu.src[0].sel = src0_sel;
768 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
769 alu.src[0].value = src0_chan_val;
770 else
771 alu.src[0].chan = src0_chan_val;
772 alu.src[1].sel = src1_sel;
773 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
774 alu.src[1].value = src1_chan_val;
775 else
776 alu.src[1].chan = src1_chan_val;
777 alu.src[2].sel = src2_sel;
778 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
779 alu.src[2].value = src2_chan_val;
780 else
781 alu.src[2].chan = src2_chan_val;
782 alu.dst.sel = dst_sel;
783 alu.dst.chan = dst_chan;
784 alu.is_op3 = 1;
785 alu.last = 1;
786 r = r600_bytecode_add_alu(ctx->bc, &alu);
787 if (r)
788 return r;
789 return 0;
790 }
791
792 /* put it in temp_reg.x */
793 static int get_lds_offset0(struct r600_shader_ctx *ctx,
794 int rel_patch_chan,
795 int temp_reg, bool is_patch_var)
796 {
797 int r;
798
799 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
800 /* ADD
801 Dimension - patch0_offset (input_vals.z),
802 Non-dim - patch0_data_offset (input_vals.w)
803 */
804 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
805 temp_reg, 0,
806 ctx->tess_output_info, 0,
807 0, rel_patch_chan,
808 ctx->tess_output_info, is_patch_var ? 3 : 2);
809 if (r)
810 return r;
811 return 0;
812 }
813
814 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
815 {
816 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
817 }
818
819 static int r600_get_temp(struct r600_shader_ctx *ctx)
820 {
821 return ctx->temp_reg + ctx->max_driver_temp_used++;
822 }
823
824 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
825 {
826 int i;
827 i = ctx->shader->noutput++;
828 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
829 ctx->shader->output[i].sid = 0;
830 ctx->shader->output[i].gpr = 0;
831 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
832 ctx->shader->output[i].write_mask = 0x4;
833 ctx->shader->output[i].spi_sid = prim_id_sid;
834
835 return 0;
836 }
837
838 static int tgsi_barrier(struct r600_shader_ctx *ctx)
839 {
840 struct r600_bytecode_alu alu;
841 int r;
842
843 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
844 alu.op = ctx->inst_info->op;
845 alu.last = 1;
846
847 r = r600_bytecode_add_alu(ctx->bc, &alu);
848 if (r)
849 return r;
850 return 0;
851 }
852
853 static int tgsi_declaration(struct r600_shader_ctx *ctx)
854 {
855 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
856 int r, i, j, count = d->Range.Last - d->Range.First + 1;
857
858 switch (d->Declaration.File) {
859 case TGSI_FILE_INPUT:
860 for (j = 0; j < count; j++) {
861 i = ctx->shader->ninput + j;
862 assert(i < ARRAY_SIZE(ctx->shader->input));
863 ctx->shader->input[i].name = d->Semantic.Name;
864 ctx->shader->input[i].sid = d->Semantic.Index + j;
865 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
866 ctx->shader->input[i].interpolate_location = d->Interp.Location;
867 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
868 if (ctx->type == PIPE_SHADER_FRAGMENT) {
869 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
870 switch (ctx->shader->input[i].name) {
871 case TGSI_SEMANTIC_FACE:
872 if (ctx->face_gpr != -1)
873 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
874 else
875 ctx->face_gpr = ctx->shader->input[i].gpr;
876 break;
877 case TGSI_SEMANTIC_COLOR:
878 ctx->colors_used++;
879 break;
880 case TGSI_SEMANTIC_POSITION:
881 ctx->fragcoord_input = i;
882 break;
883 case TGSI_SEMANTIC_PRIMID:
884 /* set this for now */
885 ctx->shader->gs_prim_id_input = true;
886 ctx->shader->ps_prim_id_input = i;
887 break;
888 }
889 if (ctx->bc->chip_class >= EVERGREEN) {
890 if ((r = evergreen_interp_input(ctx, i)))
891 return r;
892 }
893 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
894 /* FIXME probably skip inputs if they aren't passed in the ring */
895 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
896 ctx->next_ring_offset += 16;
897 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
898 ctx->shader->gs_prim_id_input = true;
899 }
900 }
901 ctx->shader->ninput += count;
902 break;
903 case TGSI_FILE_OUTPUT:
904 for (j = 0; j < count; j++) {
905 i = ctx->shader->noutput + j;
906 assert(i < ARRAY_SIZE(ctx->shader->output));
907 ctx->shader->output[i].name = d->Semantic.Name;
908 ctx->shader->output[i].sid = d->Semantic.Index + j;
909 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
910 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
911 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
912 if (ctx->type == PIPE_SHADER_VERTEX ||
913 ctx->type == PIPE_SHADER_GEOMETRY ||
914 ctx->type == PIPE_SHADER_TESS_EVAL) {
915 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
916 switch (d->Semantic.Name) {
917 case TGSI_SEMANTIC_CLIPDIST:
918 ctx->shader->clip_dist_write |= d->Declaration.UsageMask <<
919 ((d->Semantic.Index + j) << 2);
920 break;
921 case TGSI_SEMANTIC_PSIZE:
922 ctx->shader->vs_out_misc_write = 1;
923 ctx->shader->vs_out_point_size = 1;
924 break;
925 case TGSI_SEMANTIC_EDGEFLAG:
926 ctx->shader->vs_out_misc_write = 1;
927 ctx->shader->vs_out_edgeflag = 1;
928 ctx->edgeflag_output = i;
929 break;
930 case TGSI_SEMANTIC_VIEWPORT_INDEX:
931 ctx->shader->vs_out_misc_write = 1;
932 ctx->shader->vs_out_viewport = 1;
933 break;
934 case TGSI_SEMANTIC_LAYER:
935 ctx->shader->vs_out_misc_write = 1;
936 ctx->shader->vs_out_layer = 1;
937 break;
938 case TGSI_SEMANTIC_CLIPVERTEX:
939 ctx->clip_vertex_write = TRUE;
940 ctx->cv_output = i;
941 break;
942 }
943 if (ctx->type == PIPE_SHADER_GEOMETRY) {
944 ctx->gs_out_ring_offset += 16;
945 }
946 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
947 switch (d->Semantic.Name) {
948 case TGSI_SEMANTIC_COLOR:
949 ctx->shader->nr_ps_max_color_exports++;
950 break;
951 }
952 }
953 }
954 ctx->shader->noutput += count;
955 break;
956 case TGSI_FILE_TEMPORARY:
957 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
958 if (d->Array.ArrayID) {
959 r600_add_gpr_array(ctx->shader,
960 ctx->file_offset[TGSI_FILE_TEMPORARY] +
961 d->Range.First,
962 d->Range.Last - d->Range.First + 1, 0x0F);
963 }
964 }
965 break;
966
967 case TGSI_FILE_CONSTANT:
968 case TGSI_FILE_SAMPLER:
969 case TGSI_FILE_SAMPLER_VIEW:
970 case TGSI_FILE_ADDRESS:
971 break;
972
973 case TGSI_FILE_SYSTEM_VALUE:
974 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
975 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
976 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
977 break; /* Already handled from allocate_system_value_inputs */
978 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
979 if (!ctx->native_integers) {
980 struct r600_bytecode_alu alu;
981 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
982
983 alu.op = ALU_OP1_INT_TO_FLT;
984 alu.src[0].sel = 0;
985 alu.src[0].chan = 3;
986
987 alu.dst.sel = 0;
988 alu.dst.chan = 3;
989 alu.dst.write = 1;
990 alu.last = 1;
991
992 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
993 return r;
994 }
995 break;
996 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
997 break;
998 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
999 break;
1000 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1001 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1002 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1003 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1004 unsigned temp_reg = r600_get_temp(ctx);
1005
1006 r = get_lds_offset0(ctx, 2, temp_reg, true);
1007 if (r)
1008 return r;
1009
1010 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1011 temp_reg, 0,
1012 temp_reg, 0,
1013 V_SQ_ALU_SRC_LITERAL, param * 16);
1014 if (r)
1015 return r;
1016
1017 do_lds_fetch_values(ctx, temp_reg, dreg);
1018 }
1019 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1020 /* MOV r1.x, r0.x;
1021 MOV r1.y, r0.y;
1022 */
1023 for (i = 0; i < 2; i++) {
1024 struct r600_bytecode_alu alu;
1025 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1026 alu.op = ALU_OP1_MOV;
1027 alu.src[0].sel = 0;
1028 alu.src[0].chan = 0 + i;
1029 alu.dst.sel = 1;
1030 alu.dst.chan = 0 + i;
1031 alu.dst.write = 1;
1032 alu.last = (i == 1) ? 1 : 0;
1033 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1034 return r;
1035 }
1036 /* ADD r1.z, 1.0f, -r0.x */
1037 struct r600_bytecode_alu alu;
1038 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1039 alu.op = ALU_OP2_ADD;
1040 alu.src[0].sel = V_SQ_ALU_SRC_1;
1041 alu.src[1].sel = 1;
1042 alu.src[1].chan = 0;
1043 alu.src[1].neg = 1;
1044 alu.dst.sel = 1;
1045 alu.dst.chan = 2;
1046 alu.dst.write = 1;
1047 alu.last = 1;
1048 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1049 return r;
1050
1051 /* ADD r1.z, r1.z, -r1.y */
1052 alu.op = ALU_OP2_ADD;
1053 alu.src[0].sel = 1;
1054 alu.src[0].chan = 2;
1055 alu.src[1].sel = 1;
1056 alu.src[1].chan = 1;
1057 alu.src[1].neg = 1;
1058 alu.dst.sel = 1;
1059 alu.dst.chan = 2;
1060 alu.dst.write = 1;
1061 alu.last = 1;
1062 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1063 return r;
1064 break;
1065 }
1066 break;
1067 default:
1068 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1069 return -EINVAL;
1070 }
1071 return 0;
1072 }
1073
1074 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1075 {
1076 struct tgsi_parse_context parse;
1077 struct {
1078 boolean enabled;
1079 int *reg;
1080 unsigned name, alternate_name;
1081 } inputs[2] = {
1082 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1083
1084 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1085 };
1086 int i, k, num_regs = 0;
1087
1088 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1089 return 0;
1090 }
1091
1092 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1093 while (!tgsi_parse_end_of_tokens(&parse)) {
1094 tgsi_parse_token(&parse);
1095
1096 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1097 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1098 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1099 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1100 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1101 {
1102 int interpolate, location, k;
1103
1104 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1105 location = TGSI_INTERPOLATE_LOC_CENTER;
1106 inputs[1].enabled = true; /* needs SAMPLEID */
1107 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1108 location = TGSI_INTERPOLATE_LOC_CENTER;
1109 /* Needs sample positions, currently those are always available */
1110 } else {
1111 location = TGSI_INTERPOLATE_LOC_CENTROID;
1112 }
1113
1114 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1115 k = eg_get_interpolator_index(interpolate, location);
1116 ctx->eg_interpolators[k].enabled = true;
1117 }
1118 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1119 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1120 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1121 for (k = 0; k < ARRAY_SIZE(inputs); k++) {
1122 if (d->Semantic.Name == inputs[k].name ||
1123 d->Semantic.Name == inputs[k].alternate_name) {
1124 inputs[k].enabled = true;
1125 }
1126 }
1127 }
1128 }
1129 }
1130
1131 tgsi_parse_free(&parse);
1132
1133 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
1134 boolean enabled = inputs[i].enabled;
1135 int *reg = inputs[i].reg;
1136 unsigned name = inputs[i].name;
1137
1138 if (enabled) {
1139 int gpr = gpr_offset + num_regs++;
1140
1141 // add to inputs, allocate a gpr
1142 k = ctx->shader->ninput ++;
1143 ctx->shader->input[k].name = name;
1144 ctx->shader->input[k].sid = 0;
1145 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1146 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1147 *reg = ctx->shader->input[k].gpr = gpr;
1148 }
1149 }
1150
1151 return gpr_offset + num_regs;
1152 }
1153
1154 /*
1155 * for evergreen we need to scan the shader to find the number of GPRs we need to
1156 * reserve for interpolation and system values
1157 *
1158 * we need to know if we are going to emit
1159 * any sample or centroid inputs
1160 * if perspective and linear are required
1161 */
1162 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1163 {
1164 unsigned i;
1165 int num_baryc;
1166 struct tgsi_parse_context parse;
1167
1168 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1169
1170 for (i = 0; i < ctx->info.num_inputs; i++) {
1171 int k;
1172 /* skip position/face/mask/sampleid */
1173 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1174 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1175 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1176 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1177 continue;
1178
1179 k = eg_get_interpolator_index(
1180 ctx->info.input_interpolate[i],
1181 ctx->info.input_interpolate_loc[i]);
1182 if (k >= 0)
1183 ctx->eg_interpolators[k].enabled = TRUE;
1184 }
1185
1186 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1187 return 0;
1188 }
1189
1190 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1191 while (!tgsi_parse_end_of_tokens(&parse)) {
1192 tgsi_parse_token(&parse);
1193
1194 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1195 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1196 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1197 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1198 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1199 {
1200 int interpolate, location, k;
1201
1202 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1203 location = TGSI_INTERPOLATE_LOC_CENTER;
1204 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1205 location = TGSI_INTERPOLATE_LOC_CENTER;
1206 } else {
1207 location = TGSI_INTERPOLATE_LOC_CENTROID;
1208 }
1209
1210 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1211 k = eg_get_interpolator_index(interpolate, location);
1212 ctx->eg_interpolators[k].enabled = true;
1213 }
1214 }
1215 }
1216
1217 tgsi_parse_free(&parse);
1218
1219 /* assign gpr to each interpolator according to priority */
1220 num_baryc = 0;
1221 for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
1222 if (ctx->eg_interpolators[i].enabled) {
1223 ctx->eg_interpolators[i].ij_index = num_baryc;
1224 num_baryc ++;
1225 }
1226 }
1227
1228 /* XXX PULL MODEL and LINE STIPPLE */
1229
1230 num_baryc = (num_baryc + 1) >> 1;
1231 return allocate_system_value_inputs(ctx, num_baryc);
1232 }
1233
1234 /* sample_id_sel == NULL means fetch for current sample */
1235 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1236 {
1237 struct r600_bytecode_vtx vtx;
1238 int r, t1;
1239
1240 assert(ctx->fixed_pt_position_gpr != -1);
1241
1242 t1 = r600_get_temp(ctx);
1243
1244 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1245 vtx.op = FETCH_OP_VFETCH;
1246 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1247 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1248 if (sample_id == NULL) {
1249 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1250 vtx.src_sel_x = 3;
1251 }
1252 else {
1253 struct r600_bytecode_alu alu;
1254
1255 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1256 alu.op = ALU_OP1_MOV;
1257 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1258 alu.dst.sel = t1;
1259 alu.dst.write = 1;
1260 alu.last = 1;
1261 r = r600_bytecode_add_alu(ctx->bc, &alu);
1262 if (r)
1263 return r;
1264
1265 vtx.src_gpr = t1;
1266 vtx.src_sel_x = 0;
1267 }
1268 vtx.mega_fetch_count = 16;
1269 vtx.dst_gpr = t1;
1270 vtx.dst_sel_x = 0;
1271 vtx.dst_sel_y = 1;
1272 vtx.dst_sel_z = 2;
1273 vtx.dst_sel_w = 3;
1274 vtx.data_format = FMT_32_32_32_32_FLOAT;
1275 vtx.num_format_all = 2;
1276 vtx.format_comp_all = 1;
1277 vtx.use_const_fields = 0;
1278 vtx.offset = 1; // first element is size of buffer
1279 vtx.endian = r600_endian_swap(32);
1280 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1281
1282 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1283 if (r)
1284 return r;
1285
1286 return t1;
1287 }
1288
1289 static void tgsi_src(struct r600_shader_ctx *ctx,
1290 const struct tgsi_full_src_register *tgsi_src,
1291 struct r600_shader_src *r600_src)
1292 {
1293 memset(r600_src, 0, sizeof(*r600_src));
1294 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1295 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1296 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1297 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1298 r600_src->neg = tgsi_src->Register.Negate;
1299 r600_src->abs = tgsi_src->Register.Absolute;
1300
1301 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1302 int index;
1303 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1304 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1305 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1306
1307 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1308 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1309 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1310 return;
1311 }
1312 index = tgsi_src->Register.Index;
1313 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1314 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1315 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1316 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1317 r600_src->swizzle[0] = 2; // Z value
1318 r600_src->swizzle[1] = 2;
1319 r600_src->swizzle[2] = 2;
1320 r600_src->swizzle[3] = 2;
1321 r600_src->sel = ctx->face_gpr;
1322 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1323 r600_src->swizzle[0] = 3; // W value
1324 r600_src->swizzle[1] = 3;
1325 r600_src->swizzle[2] = 3;
1326 r600_src->swizzle[3] = 3;
1327 r600_src->sel = ctx->fixed_pt_position_gpr;
1328 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1329 r600_src->swizzle[0] = 0;
1330 r600_src->swizzle[1] = 1;
1331 r600_src->swizzle[2] = 4;
1332 r600_src->swizzle[3] = 4;
1333 r600_src->sel = load_sample_position(ctx, NULL, -1);
1334 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1335 r600_src->swizzle[0] = 3;
1336 r600_src->swizzle[1] = 3;
1337 r600_src->swizzle[2] = 3;
1338 r600_src->swizzle[3] = 3;
1339 r600_src->sel = 0;
1340 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1341 r600_src->swizzle[0] = 0;
1342 r600_src->swizzle[1] = 0;
1343 r600_src->swizzle[2] = 0;
1344 r600_src->swizzle[3] = 0;
1345 r600_src->sel = 0;
1346 } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1347 r600_src->swizzle[0] = 3;
1348 r600_src->swizzle[1] = 3;
1349 r600_src->swizzle[2] = 3;
1350 r600_src->swizzle[3] = 3;
1351 r600_src->sel = 1;
1352 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1353 r600_src->swizzle[0] = 2;
1354 r600_src->swizzle[1] = 2;
1355 r600_src->swizzle[2] = 2;
1356 r600_src->swizzle[3] = 2;
1357 r600_src->sel = 0;
1358 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1359 r600_src->sel = 1;
1360 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1361 r600_src->sel = 3;
1362 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1363 r600_src->sel = 2;
1364 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1365 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
1366 r600_src->sel = ctx->tess_input_info;
1367 r600_src->swizzle[0] = 2;
1368 r600_src->swizzle[1] = 2;
1369 r600_src->swizzle[2] = 2;
1370 r600_src->swizzle[3] = 2;
1371 } else {
1372 r600_src->sel = ctx->tess_input_info;
1373 r600_src->swizzle[0] = 3;
1374 r600_src->swizzle[1] = 3;
1375 r600_src->swizzle[2] = 3;
1376 r600_src->swizzle[3] = 3;
1377 }
1378 } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1379 r600_src->sel = 0;
1380 r600_src->swizzle[0] = 0;
1381 r600_src->swizzle[1] = 0;
1382 r600_src->swizzle[2] = 0;
1383 r600_src->swizzle[3] = 0;
1384 } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1385 r600_src->sel = 0;
1386 r600_src->swizzle[0] = 3;
1387 r600_src->swizzle[1] = 3;
1388 r600_src->swizzle[2] = 3;
1389 r600_src->swizzle[3] = 3;
1390 }
1391 } else {
1392 if (tgsi_src->Register.Indirect)
1393 r600_src->rel = V_SQ_REL_RELATIVE;
1394 r600_src->sel = tgsi_src->Register.Index;
1395 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1396 }
1397 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1398 if (tgsi_src->Register.Dimension) {
1399 r600_src->kc_bank = tgsi_src->Dimension.Index;
1400 if (tgsi_src->Dimension.Indirect) {
1401 r600_src->kc_rel = 1;
1402 }
1403 }
1404 }
1405 }
1406
1407 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1408 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1409 unsigned int dst_reg)
1410 {
1411 struct r600_bytecode_vtx vtx;
1412 unsigned int ar_reg;
1413 int r;
1414
1415 if (offset) {
1416 struct r600_bytecode_alu alu;
1417
1418 memset(&alu, 0, sizeof(alu));
1419
1420 alu.op = ALU_OP2_ADD_INT;
1421 alu.src[0].sel = ctx->bc->ar_reg;
1422 alu.src[0].chan = ar_chan;
1423
1424 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1425 alu.src[1].value = offset;
1426
1427 alu.dst.sel = dst_reg;
1428 alu.dst.chan = ar_chan;
1429 alu.dst.write = 1;
1430 alu.last = 1;
1431
1432 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1433 return r;
1434
1435 ar_reg = dst_reg;
1436 } else {
1437 ar_reg = ctx->bc->ar_reg;
1438 }
1439
1440 memset(&vtx, 0, sizeof(vtx));
1441 vtx.buffer_id = cb_idx;
1442 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1443 vtx.src_gpr = ar_reg;
1444 vtx.src_sel_x = ar_chan;
1445 vtx.mega_fetch_count = 16;
1446 vtx.dst_gpr = dst_reg;
1447 vtx.dst_sel_x = 0; /* SEL_X */
1448 vtx.dst_sel_y = 1; /* SEL_Y */
1449 vtx.dst_sel_z = 2; /* SEL_Z */
1450 vtx.dst_sel_w = 3; /* SEL_W */
1451 vtx.data_format = FMT_32_32_32_32_FLOAT;
1452 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1453 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1454 vtx.endian = r600_endian_swap(32);
1455 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1456
1457 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1458 return r;
1459
1460 return 0;
1461 }
1462
1463 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1464 {
1465 struct r600_bytecode_vtx vtx;
1466 int r;
1467 unsigned index = src->Register.Index;
1468 unsigned vtx_id = src->Dimension.Index;
1469 int offset_reg = vtx_id / 3;
1470 int offset_chan = vtx_id % 3;
1471 int t2 = 0;
1472
1473 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1474 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1475
1476 if (offset_reg == 0 && offset_chan == 2)
1477 offset_chan = 3;
1478
1479 if (src->Dimension.Indirect || src->Register.Indirect)
1480 t2 = r600_get_temp(ctx);
1481
1482 if (src->Dimension.Indirect) {
1483 int treg[3];
1484 struct r600_bytecode_alu alu;
1485 int r, i;
1486 unsigned addr_reg;
1487 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1488 if (src->DimIndirect.Index > 0) {
1489 r = single_alu_op2(ctx, ALU_OP1_MOV,
1490 ctx->bc->ar_reg, 0,
1491 addr_reg, 0,
1492 0, 0);
1493 if (r)
1494 return r;
1495 }
1496 /*
1497 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1498 at least this is what fglrx seems to do. */
1499 for (i = 0; i < 3; i++) {
1500 treg[i] = r600_get_temp(ctx);
1501 }
1502 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1503
1504 for (i = 0; i < 3; i++) {
1505 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1506 alu.op = ALU_OP1_MOV;
1507 alu.src[0].sel = 0;
1508 alu.src[0].chan = i == 2 ? 3 : i;
1509 alu.dst.sel = treg[i];
1510 alu.dst.chan = 0;
1511 alu.dst.write = 1;
1512 alu.last = 1;
1513 r = r600_bytecode_add_alu(ctx->bc, &alu);
1514 if (r)
1515 return r;
1516 }
1517 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1518 alu.op = ALU_OP1_MOV;
1519 alu.src[0].sel = treg[0];
1520 alu.src[0].rel = 1;
1521 alu.dst.sel = t2;
1522 alu.dst.write = 1;
1523 alu.last = 1;
1524 r = r600_bytecode_add_alu(ctx->bc, &alu);
1525 if (r)
1526 return r;
1527 offset_reg = t2;
1528 offset_chan = 0;
1529 }
1530
1531 if (src->Register.Indirect) {
1532 int addr_reg;
1533 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1534
1535 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1536
1537 /* pull the value from index_reg */
1538 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1539 t2, 1,
1540 addr_reg, 0,
1541 V_SQ_ALU_SRC_LITERAL, first);
1542 if (r)
1543 return r;
1544 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1545 t2, 0,
1546 t2, 1,
1547 V_SQ_ALU_SRC_LITERAL, 4,
1548 offset_reg, offset_chan);
1549 if (r)
1550 return r;
1551 offset_reg = t2;
1552 offset_chan = 0;
1553 index = src->Register.Index - first;
1554 }
1555
1556 memset(&vtx, 0, sizeof(vtx));
1557 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1558 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1559 vtx.src_gpr = offset_reg;
1560 vtx.src_sel_x = offset_chan;
1561 vtx.offset = index * 16; /*bytes*/
1562 vtx.mega_fetch_count = 16;
1563 vtx.dst_gpr = dst_reg;
1564 vtx.dst_sel_x = 0; /* SEL_X */
1565 vtx.dst_sel_y = 1; /* SEL_Y */
1566 vtx.dst_sel_z = 2; /* SEL_Z */
1567 vtx.dst_sel_w = 3; /* SEL_W */
1568 if (ctx->bc->chip_class >= EVERGREEN) {
1569 vtx.use_const_fields = 1;
1570 } else {
1571 vtx.data_format = FMT_32_32_32_32_FLOAT;
1572 }
1573
1574 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1575 return r;
1576
1577 return 0;
1578 }
1579
1580 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1581 {
1582 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1583 unsigned i;
1584
1585 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1586 struct tgsi_full_src_register *src = &inst->Src[i];
1587
1588 if (src->Register.File == TGSI_FILE_INPUT) {
1589 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1590 /* primitive id is in R0.z */
1591 ctx->src[i].sel = 0;
1592 ctx->src[i].swizzle[0] = 2;
1593 }
1594 }
1595 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1596 int treg = r600_get_temp(ctx);
1597
1598 fetch_gs_input(ctx, src, treg);
1599 ctx->src[i].sel = treg;
1600 ctx->src[i].rel = 0;
1601 }
1602 }
1603 return 0;
1604 }
1605
1606
1607 /* Tessellation shaders pass outputs to the next shader using LDS.
1608 *
1609 * LS outputs = TCS(HS) inputs
1610 * TCS(HS) outputs = TES(DS) inputs
1611 *
1612 * The LDS layout is:
1613 * - TCS inputs for patch 0
1614 * - TCS inputs for patch 1
1615 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1616 * - ...
1617 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1618 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1619 * - TCS outputs for patch 1
1620 * - Per-patch TCS outputs for patch 1
1621 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1622 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1623 * - ...
1624 *
1625 * All three shaders VS(LS), TCS, TES share the same LDS space.
1626 */
1627 /* this will return with the dw address in temp_reg.x */
1628 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1629 const struct tgsi_full_dst_register *dst,
1630 const struct tgsi_full_src_register *src,
1631 int stride_bytes_reg, int stride_bytes_chan)
1632 {
1633 struct tgsi_full_dst_register reg;
1634 ubyte *name, *index, *array_first;
1635 int r;
1636 int param;
1637 struct tgsi_shader_info *info = &ctx->info;
1638 /* Set the register description. The address computation is the same
1639 * for sources and destinations. */
1640 if (src) {
1641 reg.Register.File = src->Register.File;
1642 reg.Register.Index = src->Register.Index;
1643 reg.Register.Indirect = src->Register.Indirect;
1644 reg.Register.Dimension = src->Register.Dimension;
1645 reg.Indirect = src->Indirect;
1646 reg.Dimension = src->Dimension;
1647 reg.DimIndirect = src->DimIndirect;
1648 } else
1649 reg = *dst;
1650
1651 /* If the register is 2-dimensional (e.g. an array of vertices
1652 * in a primitive), calculate the base address of the vertex. */
1653 if (reg.Register.Dimension) {
1654 int sel, chan;
1655 if (reg.Dimension.Indirect) {
1656 unsigned addr_reg;
1657 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1658
1659 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1660 /* pull the value from index_reg */
1661 sel = addr_reg;
1662 chan = 0;
1663 } else {
1664 sel = V_SQ_ALU_SRC_LITERAL;
1665 chan = reg.Dimension.Index;
1666 }
1667
1668 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1669 temp_reg, 0,
1670 stride_bytes_reg, stride_bytes_chan,
1671 sel, chan,
1672 temp_reg, 0);
1673 if (r)
1674 return r;
1675 }
1676
1677 if (reg.Register.File == TGSI_FILE_INPUT) {
1678 name = info->input_semantic_name;
1679 index = info->input_semantic_index;
1680 array_first = info->input_array_first;
1681 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1682 name = info->output_semantic_name;
1683 index = info->output_semantic_index;
1684 array_first = info->output_array_first;
1685 } else {
1686 assert(0);
1687 return -1;
1688 }
1689 if (reg.Register.Indirect) {
1690 int addr_reg;
1691 int first;
1692 /* Add the relative address of the element. */
1693 if (reg.Indirect.ArrayID)
1694 first = array_first[reg.Indirect.ArrayID];
1695 else
1696 first = reg.Register.Index;
1697
1698 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
1699
1700 /* pull the value from index_reg */
1701 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1702 temp_reg, 0,
1703 V_SQ_ALU_SRC_LITERAL, 16,
1704 addr_reg, 0,
1705 temp_reg, 0);
1706 if (r)
1707 return r;
1708
1709 param = r600_get_lds_unique_index(name[first],
1710 index[first]);
1711
1712 } else {
1713 param = r600_get_lds_unique_index(name[reg.Register.Index],
1714 index[reg.Register.Index]);
1715 }
1716
1717 /* add to base_addr - passed in temp_reg.x */
1718 if (param) {
1719 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1720 temp_reg, 0,
1721 temp_reg, 0,
1722 V_SQ_ALU_SRC_LITERAL, param * 16);
1723 if (r)
1724 return r;
1725
1726 }
1727 return 0;
1728 }
1729
1730 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
1731 unsigned dst_reg)
1732 {
1733 struct r600_bytecode_alu alu;
1734 int r, i;
1735
1736 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
1737 ctx->bc->force_add_cf = 1;
1738 for (i = 1; i < 4; i++) {
1739 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1740 temp_reg, i,
1741 temp_reg, 0,
1742 V_SQ_ALU_SRC_LITERAL, 4 * i);
1743 if (r)
1744 return r;
1745 }
1746 for (i = 0; i < 4; i++) {
1747 /* emit an LDS_READ_RET */
1748 memset(&alu, 0, sizeof(alu));
1749 alu.op = LDS_OP1_LDS_READ_RET;
1750 alu.src[0].sel = temp_reg;
1751 alu.src[0].chan = i;
1752 alu.src[1].sel = V_SQ_ALU_SRC_0;
1753 alu.src[2].sel = V_SQ_ALU_SRC_0;
1754 alu.dst.chan = 0;
1755 alu.is_lds_idx_op = true;
1756 alu.last = 1;
1757 r = r600_bytecode_add_alu(ctx->bc, &alu);
1758 if (r)
1759 return r;
1760 }
1761 for (i = 0; i < 4; i++) {
1762 /* then read from LDS_OQ_A_POP */
1763 memset(&alu, 0, sizeof(alu));
1764
1765 alu.op = ALU_OP1_MOV;
1766 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
1767 alu.src[0].chan = 0;
1768 alu.dst.sel = dst_reg;
1769 alu.dst.chan = i;
1770 alu.dst.write = 1;
1771 alu.last = 1;
1772 r = r600_bytecode_add_alu(ctx->bc, &alu);
1773 if (r)
1774 return r;
1775 }
1776 return 0;
1777 }
1778
1779 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1780 {
1781 int r;
1782 unsigned temp_reg = r600_get_temp(ctx);
1783
1784 r = get_lds_offset0(ctx, 2, temp_reg,
1785 src->Register.Dimension ? false : true);
1786 if (r)
1787 return r;
1788
1789 /* the base address is now in temp.x */
1790 r = r600_get_byte_address(ctx, temp_reg,
1791 NULL, src, ctx->tess_output_info, 1);
1792 if (r)
1793 return r;
1794
1795 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1796 if (r)
1797 return r;
1798 return 0;
1799 }
1800
1801 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1802 {
1803 int r;
1804 unsigned temp_reg = r600_get_temp(ctx);
1805
1806 /* t.x = ips * r0.y */
1807 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
1808 temp_reg, 0,
1809 ctx->tess_input_info, 0,
1810 0, 1);
1811
1812 if (r)
1813 return r;
1814
1815 /* the base address is now in temp.x */
1816 r = r600_get_byte_address(ctx, temp_reg,
1817 NULL, src, ctx->tess_input_info, 1);
1818 if (r)
1819 return r;
1820
1821 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1822 if (r)
1823 return r;
1824 return 0;
1825 }
1826
1827 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1828 {
1829 int r;
1830 unsigned temp_reg = r600_get_temp(ctx);
1831
1832 r = get_lds_offset0(ctx, 1, temp_reg,
1833 src->Register.Dimension ? false : true);
1834 if (r)
1835 return r;
1836 /* the base address is now in temp.x */
1837 r = r600_get_byte_address(ctx, temp_reg,
1838 NULL, src,
1839 ctx->tess_output_info, 1);
1840 if (r)
1841 return r;
1842
1843 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1844 if (r)
1845 return r;
1846 return 0;
1847 }
1848
1849 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
1850 {
1851 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1852 unsigned i;
1853
1854 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1855 struct tgsi_full_src_register *src = &inst->Src[i];
1856
1857 if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
1858 int treg = r600_get_temp(ctx);
1859 fetch_tes_input(ctx, src, treg);
1860 ctx->src[i].sel = treg;
1861 ctx->src[i].rel = 0;
1862 }
1863 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
1864 int treg = r600_get_temp(ctx);
1865 fetch_tcs_input(ctx, src, treg);
1866 ctx->src[i].sel = treg;
1867 ctx->src[i].rel = 0;
1868 }
1869 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
1870 int treg = r600_get_temp(ctx);
1871 fetch_tcs_output(ctx, src, treg);
1872 ctx->src[i].sel = treg;
1873 ctx->src[i].rel = 0;
1874 }
1875 }
1876 return 0;
1877 }
1878
1879 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1880 {
1881 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1882 struct r600_bytecode_alu alu;
1883 int i, j, k, nconst, r;
1884
1885 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1886 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1887 nconst++;
1888 }
1889 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1890 }
1891 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1892 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1893 continue;
1894 }
1895
1896 if (ctx->src[i].rel) {
1897 int chan = inst->Src[i].Indirect.Swizzle;
1898 int treg = r600_get_temp(ctx);
1899 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1900 return r;
1901
1902 ctx->src[i].kc_bank = 0;
1903 ctx->src[i].kc_rel = 0;
1904 ctx->src[i].sel = treg;
1905 ctx->src[i].rel = 0;
1906 j--;
1907 } else if (j > 0) {
1908 int treg = r600_get_temp(ctx);
1909 for (k = 0; k < 4; k++) {
1910 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1911 alu.op = ALU_OP1_MOV;
1912 alu.src[0].sel = ctx->src[i].sel;
1913 alu.src[0].chan = k;
1914 alu.src[0].rel = ctx->src[i].rel;
1915 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1916 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1917 alu.dst.sel = treg;
1918 alu.dst.chan = k;
1919 alu.dst.write = 1;
1920 if (k == 3)
1921 alu.last = 1;
1922 r = r600_bytecode_add_alu(ctx->bc, &alu);
1923 if (r)
1924 return r;
1925 }
1926 ctx->src[i].sel = treg;
1927 ctx->src[i].rel =0;
1928 j--;
1929 }
1930 }
1931 return 0;
1932 }
1933
1934 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1935 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1936 {
1937 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1938 struct r600_bytecode_alu alu;
1939 int i, j, k, nliteral, r;
1940
1941 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1942 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1943 nliteral++;
1944 }
1945 }
1946 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1947 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1948 int treg = r600_get_temp(ctx);
1949 for (k = 0; k < 4; k++) {
1950 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1951 alu.op = ALU_OP1_MOV;
1952 alu.src[0].sel = ctx->src[i].sel;
1953 alu.src[0].chan = k;
1954 alu.src[0].value = ctx->src[i].value[k];
1955 alu.dst.sel = treg;
1956 alu.dst.chan = k;
1957 alu.dst.write = 1;
1958 if (k == 3)
1959 alu.last = 1;
1960 r = r600_bytecode_add_alu(ctx->bc, &alu);
1961 if (r)
1962 return r;
1963 }
1964 ctx->src[i].sel = treg;
1965 j--;
1966 }
1967 }
1968 return 0;
1969 }
1970
1971 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1972 {
1973 int i, r, count = ctx->shader->ninput;
1974
1975 for (i = 0; i < count; i++) {
1976 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1977 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1978 if (r)
1979 return r;
1980 }
1981 }
1982 return 0;
1983 }
1984
1985 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
1986 int stream, unsigned *stream_item_size)
1987 {
1988 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1989 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
1990 int i, j, r;
1991
1992 /* Sanity checking. */
1993 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
1994 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
1995 r = -EINVAL;
1996 goto out_err;
1997 }
1998 for (i = 0; i < so->num_outputs; i++) {
1999 if (so->output[i].output_buffer >= 4) {
2000 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2001 so->output[i].output_buffer);
2002 r = -EINVAL;
2003 goto out_err;
2004 }
2005 }
2006
2007 /* Initialize locations where the outputs are stored. */
2008 for (i = 0; i < so->num_outputs; i++) {
2009
2010 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2011 start_comp[i] = so->output[i].start_component;
2012 /* Lower outputs with dst_offset < start_component.
2013 *
2014 * We can only output 4D vectors with a write mask, e.g. we can
2015 * only output the W component at offset 3, etc. If we want
2016 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2017 * to move it to X and output X. */
2018 if (so->output[i].dst_offset < so->output[i].start_component) {
2019 unsigned tmp = r600_get_temp(ctx);
2020
2021 for (j = 0; j < so->output[i].num_components; j++) {
2022 struct r600_bytecode_alu alu;
2023 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2024 alu.op = ALU_OP1_MOV;
2025 alu.src[0].sel = so_gpr[i];
2026 alu.src[0].chan = so->output[i].start_component + j;
2027
2028 alu.dst.sel = tmp;
2029 alu.dst.chan = j;
2030 alu.dst.write = 1;
2031 if (j == so->output[i].num_components - 1)
2032 alu.last = 1;
2033 r = r600_bytecode_add_alu(ctx->bc, &alu);
2034 if (r)
2035 return r;
2036 }
2037 start_comp[i] = 0;
2038 so_gpr[i] = tmp;
2039 }
2040 }
2041
2042 /* Write outputs to buffers. */
2043 for (i = 0; i < so->num_outputs; i++) {
2044 struct r600_bytecode_output output;
2045
2046 if (stream != -1 && stream != so->output[i].output_buffer)
2047 continue;
2048
2049 memset(&output, 0, sizeof(struct r600_bytecode_output));
2050 output.gpr = so_gpr[i];
2051 output.elem_size = so->output[i].num_components - 1;
2052 if (output.elem_size == 2)
2053 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2054 output.array_base = so->output[i].dst_offset - start_comp[i];
2055 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2056 output.burst_count = 1;
2057 /* array_size is an upper limit for the burst_count
2058 * with MEM_STREAM instructions */
2059 output.array_size = 0xFFF;
2060 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2061
2062 if (ctx->bc->chip_class >= EVERGREEN) {
2063 switch (so->output[i].output_buffer) {
2064 case 0:
2065 output.op = CF_OP_MEM_STREAM0_BUF0;
2066 break;
2067 case 1:
2068 output.op = CF_OP_MEM_STREAM0_BUF1;
2069 break;
2070 case 2:
2071 output.op = CF_OP_MEM_STREAM0_BUF2;
2072 break;
2073 case 3:
2074 output.op = CF_OP_MEM_STREAM0_BUF3;
2075 break;
2076 }
2077 output.op += so->output[i].stream * 4;
2078 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2079 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2080 } else {
2081 switch (so->output[i].output_buffer) {
2082 case 0:
2083 output.op = CF_OP_MEM_STREAM0;
2084 break;
2085 case 1:
2086 output.op = CF_OP_MEM_STREAM1;
2087 break;
2088 case 2:
2089 output.op = CF_OP_MEM_STREAM2;
2090 break;
2091 case 3:
2092 output.op = CF_OP_MEM_STREAM3;
2093 break;
2094 }
2095 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2096 }
2097 r = r600_bytecode_add_output(ctx->bc, &output);
2098 if (r)
2099 goto out_err;
2100 }
2101 return 0;
2102 out_err:
2103 return r;
2104 }
2105
2106 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2107 {
2108 struct r600_bytecode_alu alu;
2109 unsigned reg;
2110
2111 if (!ctx->shader->vs_out_edgeflag)
2112 return;
2113
2114 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2115
2116 /* clamp(x, 0, 1) */
2117 memset(&alu, 0, sizeof(alu));
2118 alu.op = ALU_OP1_MOV;
2119 alu.src[0].sel = reg;
2120 alu.dst.sel = reg;
2121 alu.dst.write = 1;
2122 alu.dst.clamp = 1;
2123 alu.last = 1;
2124 r600_bytecode_add_alu(ctx->bc, &alu);
2125
2126 memset(&alu, 0, sizeof(alu));
2127 alu.op = ALU_OP1_FLT_TO_INT;
2128 alu.src[0].sel = reg;
2129 alu.dst.sel = reg;
2130 alu.dst.write = 1;
2131 alu.last = 1;
2132 r600_bytecode_add_alu(ctx->bc, &alu);
2133 }
2134
2135 static int generate_gs_copy_shader(struct r600_context *rctx,
2136 struct r600_pipe_shader *gs,
2137 struct pipe_stream_output_info *so)
2138 {
2139 struct r600_shader_ctx ctx = {};
2140 struct r600_shader *gs_shader = &gs->shader;
2141 struct r600_pipe_shader *cshader;
2142 int ocnt = gs_shader->noutput;
2143 struct r600_bytecode_alu alu;
2144 struct r600_bytecode_vtx vtx;
2145 struct r600_bytecode_output output;
2146 struct r600_bytecode_cf *cf_jump, *cf_pop,
2147 *last_exp_pos = NULL, *last_exp_param = NULL;
2148 int i, j, next_clip_pos = 61, next_param = 0;
2149 int ring;
2150 bool only_ring_0 = true;
2151 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2152 if (!cshader)
2153 return 0;
2154
2155 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2156 sizeof(struct r600_shader_io));
2157
2158 cshader->shader.noutput = ocnt;
2159
2160 ctx.shader = &cshader->shader;
2161 ctx.bc = &ctx.shader->bc;
2162 ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
2163
2164 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2165 rctx->screen->has_compressed_msaa_texturing);
2166
2167 ctx.bc->isa = rctx->isa;
2168
2169 cf_jump = NULL;
2170 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2171
2172 /* R0.x = R0.x & 0x3fffffff */
2173 memset(&alu, 0, sizeof(alu));
2174 alu.op = ALU_OP2_AND_INT;
2175 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2176 alu.src[1].value = 0x3fffffff;
2177 alu.dst.write = 1;
2178 r600_bytecode_add_alu(ctx.bc, &alu);
2179
2180 /* R0.y = R0.x >> 30 */
2181 memset(&alu, 0, sizeof(alu));
2182 alu.op = ALU_OP2_LSHR_INT;
2183 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2184 alu.src[1].value = 0x1e;
2185 alu.dst.chan = 1;
2186 alu.dst.write = 1;
2187 alu.last = 1;
2188 r600_bytecode_add_alu(ctx.bc, &alu);
2189
2190 /* fetch vertex data from GSVS ring */
2191 for (i = 0; i < ocnt; ++i) {
2192 struct r600_shader_io *out = &ctx.shader->output[i];
2193
2194 out->gpr = i + 1;
2195 out->ring_offset = i * 16;
2196
2197 memset(&vtx, 0, sizeof(vtx));
2198 vtx.op = FETCH_OP_VFETCH;
2199 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2200 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2201 vtx.mega_fetch_count = 16;
2202 vtx.offset = out->ring_offset;
2203 vtx.dst_gpr = out->gpr;
2204 vtx.src_gpr = 0;
2205 vtx.dst_sel_x = 0;
2206 vtx.dst_sel_y = 1;
2207 vtx.dst_sel_z = 2;
2208 vtx.dst_sel_w = 3;
2209 if (rctx->b.chip_class >= EVERGREEN) {
2210 vtx.use_const_fields = 1;
2211 } else {
2212 vtx.data_format = FMT_32_32_32_32_FLOAT;
2213 }
2214
2215 r600_bytecode_add_vtx(ctx.bc, &vtx);
2216 }
2217 ctx.temp_reg = i + 1;
2218 for (ring = 3; ring >= 0; --ring) {
2219 bool enabled = false;
2220 for (i = 0; i < so->num_outputs; i++) {
2221 if (so->output[i].stream == ring) {
2222 enabled = true;
2223 if (ring > 0)
2224 only_ring_0 = false;
2225 break;
2226 }
2227 }
2228 if (ring != 0 && !enabled) {
2229 cshader->shader.ring_item_sizes[ring] = 0;
2230 continue;
2231 }
2232
2233 if (cf_jump) {
2234 // Patch up jump label
2235 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2236 cf_pop = ctx.bc->cf_last;
2237
2238 cf_jump->cf_addr = cf_pop->id + 2;
2239 cf_jump->pop_count = 1;
2240 cf_pop->cf_addr = cf_pop->id + 2;
2241 cf_pop->pop_count = 1;
2242 }
2243
2244 /* PRED_SETE_INT __, R0.y, ring */
2245 memset(&alu, 0, sizeof(alu));
2246 alu.op = ALU_OP2_PRED_SETE_INT;
2247 alu.src[0].chan = 1;
2248 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2249 alu.src[1].value = ring;
2250 alu.execute_mask = 1;
2251 alu.update_pred = 1;
2252 alu.last = 1;
2253 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2254
2255 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2256 cf_jump = ctx.bc->cf_last;
2257
2258 if (enabled)
2259 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2260 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2261 }
2262
2263 /* bc adds nops - copy it */
2264 if (ctx.bc->chip_class == R600) {
2265 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2266 alu.op = ALU_OP0_NOP;
2267 alu.last = 1;
2268 r600_bytecode_add_alu(ctx.bc, &alu);
2269
2270 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2271 }
2272
2273 /* export vertex data */
2274 /* XXX factor out common code with r600_shader_from_tgsi ? */
2275 for (i = 0; i < ocnt; ++i) {
2276 struct r600_shader_io *out = &ctx.shader->output[i];
2277 bool instream0 = true;
2278 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2279 continue;
2280
2281 for (j = 0; j < so->num_outputs; j++) {
2282 if (so->output[j].register_index == i) {
2283 if (so->output[j].stream == 0)
2284 break;
2285 if (so->output[j].stream > 0)
2286 instream0 = false;
2287 }
2288 }
2289 if (!instream0)
2290 continue;
2291 memset(&output, 0, sizeof(output));
2292 output.gpr = out->gpr;
2293 output.elem_size = 3;
2294 output.swizzle_x = 0;
2295 output.swizzle_y = 1;
2296 output.swizzle_z = 2;
2297 output.swizzle_w = 3;
2298 output.burst_count = 1;
2299 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2300 output.op = CF_OP_EXPORT;
2301 switch (out->name) {
2302 case TGSI_SEMANTIC_POSITION:
2303 output.array_base = 60;
2304 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2305 break;
2306
2307 case TGSI_SEMANTIC_PSIZE:
2308 output.array_base = 61;
2309 if (next_clip_pos == 61)
2310 next_clip_pos = 62;
2311 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2312 output.swizzle_y = 7;
2313 output.swizzle_z = 7;
2314 output.swizzle_w = 7;
2315 ctx.shader->vs_out_misc_write = 1;
2316 ctx.shader->vs_out_point_size = 1;
2317 break;
2318 case TGSI_SEMANTIC_LAYER:
2319 if (out->spi_sid) {
2320 /* duplicate it as PARAM to pass to the pixel shader */
2321 output.array_base = next_param++;
2322 r600_bytecode_add_output(ctx.bc, &output);
2323 last_exp_param = ctx.bc->cf_last;
2324 }
2325 output.array_base = 61;
2326 if (next_clip_pos == 61)
2327 next_clip_pos = 62;
2328 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2329 output.swizzle_x = 7;
2330 output.swizzle_y = 7;
2331 output.swizzle_z = 0;
2332 output.swizzle_w = 7;
2333 ctx.shader->vs_out_misc_write = 1;
2334 ctx.shader->vs_out_layer = 1;
2335 break;
2336 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2337 if (out->spi_sid) {
2338 /* duplicate it as PARAM to pass to the pixel shader */
2339 output.array_base = next_param++;
2340 r600_bytecode_add_output(ctx.bc, &output);
2341 last_exp_param = ctx.bc->cf_last;
2342 }
2343 output.array_base = 61;
2344 if (next_clip_pos == 61)
2345 next_clip_pos = 62;
2346 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2347 ctx.shader->vs_out_misc_write = 1;
2348 ctx.shader->vs_out_viewport = 1;
2349 output.swizzle_x = 7;
2350 output.swizzle_y = 7;
2351 output.swizzle_z = 7;
2352 output.swizzle_w = 0;
2353 break;
2354 case TGSI_SEMANTIC_CLIPDIST:
2355 /* spi_sid is 0 for clipdistance outputs that were generated
2356 * for clipvertex - we don't need to pass them to PS */
2357 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2358 if (out->spi_sid) {
2359 /* duplicate it as PARAM to pass to the pixel shader */
2360 output.array_base = next_param++;
2361 r600_bytecode_add_output(ctx.bc, &output);
2362 last_exp_param = ctx.bc->cf_last;
2363 }
2364 output.array_base = next_clip_pos++;
2365 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2366 break;
2367 case TGSI_SEMANTIC_FOG:
2368 output.swizzle_y = 4; /* 0 */
2369 output.swizzle_z = 4; /* 0 */
2370 output.swizzle_w = 5; /* 1 */
2371 break;
2372 default:
2373 output.array_base = next_param++;
2374 break;
2375 }
2376 r600_bytecode_add_output(ctx.bc, &output);
2377 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2378 last_exp_param = ctx.bc->cf_last;
2379 else
2380 last_exp_pos = ctx.bc->cf_last;
2381 }
2382
2383 if (!last_exp_pos) {
2384 memset(&output, 0, sizeof(output));
2385 output.gpr = 0;
2386 output.elem_size = 3;
2387 output.swizzle_x = 7;
2388 output.swizzle_y = 7;
2389 output.swizzle_z = 7;
2390 output.swizzle_w = 7;
2391 output.burst_count = 1;
2392 output.type = 2;
2393 output.op = CF_OP_EXPORT;
2394 output.array_base = 60;
2395 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2396 r600_bytecode_add_output(ctx.bc, &output);
2397 last_exp_pos = ctx.bc->cf_last;
2398 }
2399
2400 if (!last_exp_param) {
2401 memset(&output, 0, sizeof(output));
2402 output.gpr = 0;
2403 output.elem_size = 3;
2404 output.swizzle_x = 7;
2405 output.swizzle_y = 7;
2406 output.swizzle_z = 7;
2407 output.swizzle_w = 7;
2408 output.burst_count = 1;
2409 output.type = 2;
2410 output.op = CF_OP_EXPORT;
2411 output.array_base = next_param++;
2412 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2413 r600_bytecode_add_output(ctx.bc, &output);
2414 last_exp_param = ctx.bc->cf_last;
2415 }
2416
2417 last_exp_pos->op = CF_OP_EXPORT_DONE;
2418 last_exp_param->op = CF_OP_EXPORT_DONE;
2419
2420 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2421 cf_pop = ctx.bc->cf_last;
2422
2423 cf_jump->cf_addr = cf_pop->id + 2;
2424 cf_jump->pop_count = 1;
2425 cf_pop->cf_addr = cf_pop->id + 2;
2426 cf_pop->pop_count = 1;
2427
2428 if (ctx.bc->chip_class == CAYMAN)
2429 cm_bytecode_add_cf_end(ctx.bc);
2430 else {
2431 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2432 ctx.bc->cf_last->end_of_program = 1;
2433 }
2434
2435 gs->gs_copy_shader = cshader;
2436 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2437
2438 ctx.bc->nstack = 1;
2439
2440 return r600_bytecode_build(ctx.bc);
2441 }
2442
2443 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2444 {
2445 if (ind) {
2446 struct r600_bytecode_alu alu;
2447 int r;
2448
2449 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2450 alu.op = ALU_OP2_ADD_INT;
2451 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2452 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2453 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2454 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2455 alu.dst.write = 1;
2456 alu.last = 1;
2457 r = r600_bytecode_add_alu(ctx->bc, &alu);
2458 if (r)
2459 return r;
2460 }
2461 return 0;
2462 }
2463
2464 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind)
2465 {
2466 struct r600_bytecode_output output;
2467 int i, k, ring_offset;
2468 int effective_stream = stream == -1 ? 0 : stream;
2469 int idx = 0;
2470
2471 for (i = 0; i < ctx->shader->noutput; i++) {
2472 if (ctx->gs_for_vs) {
2473 /* for ES we need to lookup corresponding ring offset expected by GS
2474 * (map this output to GS input by name and sid) */
2475 /* FIXME precompute offsets */
2476 ring_offset = -1;
2477 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2478 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2479 struct r600_shader_io *out = &ctx->shader->output[i];
2480 if (in->name == out->name && in->sid == out->sid)
2481 ring_offset = in->ring_offset;
2482 }
2483
2484 if (ring_offset == -1)
2485 continue;
2486 } else {
2487 ring_offset = idx * 16;
2488 idx++;
2489 }
2490
2491 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2492 continue;
2493 /* next_ring_offset after parsing input decls contains total size of
2494 * single vertex data, gs_next_vertex - current vertex index */
2495 if (!ind)
2496 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2497
2498 memset(&output, 0, sizeof(struct r600_bytecode_output));
2499 output.gpr = ctx->shader->output[i].gpr;
2500 output.elem_size = 3;
2501 output.comp_mask = 0xF;
2502 output.burst_count = 1;
2503
2504 if (ind)
2505 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2506 else
2507 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2508
2509 switch (stream) {
2510 default:
2511 case 0:
2512 output.op = CF_OP_MEM_RING; break;
2513 case 1:
2514 output.op = CF_OP_MEM_RING1; break;
2515 case 2:
2516 output.op = CF_OP_MEM_RING2; break;
2517 case 3:
2518 output.op = CF_OP_MEM_RING3; break;
2519 }
2520
2521 if (ind) {
2522 output.array_base = ring_offset >> 2; /* in dwords */
2523 output.array_size = 0xfff;
2524 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2525 } else
2526 output.array_base = ring_offset >> 2; /* in dwords */
2527 r600_bytecode_add_output(ctx->bc, &output);
2528 }
2529
2530 ++ctx->gs_next_vertex;
2531 return 0;
2532 }
2533
2534
2535 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2536 {
2537 int r;
2538 struct r600_bytecode_vtx vtx;
2539 int temp_val = ctx->temp_reg;
2540 /* need to store the TCS output somewhere */
2541 r = single_alu_op2(ctx, ALU_OP1_MOV,
2542 temp_val, 0,
2543 V_SQ_ALU_SRC_LITERAL, 0,
2544 0, 0);
2545 if (r)
2546 return r;
2547
2548 /* used by VS/TCS */
2549 if (ctx->tess_input_info) {
2550 /* fetch tcs input values into resv space */
2551 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2552 vtx.op = FETCH_OP_VFETCH;
2553 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2554 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2555 vtx.mega_fetch_count = 16;
2556 vtx.data_format = FMT_32_32_32_32;
2557 vtx.num_format_all = 2;
2558 vtx.format_comp_all = 1;
2559 vtx.use_const_fields = 0;
2560 vtx.endian = r600_endian_swap(32);
2561 vtx.srf_mode_all = 1;
2562 vtx.offset = 0;
2563 vtx.dst_gpr = ctx->tess_input_info;
2564 vtx.dst_sel_x = 0;
2565 vtx.dst_sel_y = 1;
2566 vtx.dst_sel_z = 2;
2567 vtx.dst_sel_w = 3;
2568 vtx.src_gpr = temp_val;
2569 vtx.src_sel_x = 0;
2570
2571 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2572 if (r)
2573 return r;
2574 }
2575
2576 /* used by TCS/TES */
2577 if (ctx->tess_output_info) {
2578 /* fetch tcs output values into resv space */
2579 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2580 vtx.op = FETCH_OP_VFETCH;
2581 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2582 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2583 vtx.mega_fetch_count = 16;
2584 vtx.data_format = FMT_32_32_32_32;
2585 vtx.num_format_all = 2;
2586 vtx.format_comp_all = 1;
2587 vtx.use_const_fields = 0;
2588 vtx.endian = r600_endian_swap(32);
2589 vtx.srf_mode_all = 1;
2590 vtx.offset = 16;
2591 vtx.dst_gpr = ctx->tess_output_info;
2592 vtx.dst_sel_x = 0;
2593 vtx.dst_sel_y = 1;
2594 vtx.dst_sel_z = 2;
2595 vtx.dst_sel_w = 3;
2596 vtx.src_gpr = temp_val;
2597 vtx.src_sel_x = 0;
2598
2599 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2600 if (r)
2601 return r;
2602 }
2603 return 0;
2604 }
2605
2606 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2607 {
2608 int i, j, r;
2609 int temp_reg;
2610
2611 /* fetch tcs input values into input_vals */
2612 ctx->tess_input_info = r600_get_temp(ctx);
2613 ctx->tess_output_info = 0;
2614 r = r600_fetch_tess_io_info(ctx);
2615 if (r)
2616 return r;
2617
2618 temp_reg = r600_get_temp(ctx);
2619 /* dst reg contains LDS address stride * idx */
2620 /* MUL vertexID, vertex_dw_stride */
2621 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2622 temp_reg, 0,
2623 ctx->tess_input_info, 1,
2624 0, 1); /* rel id in r0.y? */
2625 if (r)
2626 return r;
2627
2628 for (i = 0; i < ctx->shader->noutput; i++) {
2629 struct r600_bytecode_alu alu;
2630 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2631
2632 if (param) {
2633 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2634 temp_reg, 1,
2635 temp_reg, 0,
2636 V_SQ_ALU_SRC_LITERAL, param * 16);
2637 if (r)
2638 return r;
2639 }
2640
2641 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2642 temp_reg, 2,
2643 temp_reg, param ? 1 : 0,
2644 V_SQ_ALU_SRC_LITERAL, 8);
2645 if (r)
2646 return r;
2647
2648
2649 for (j = 0; j < 2; j++) {
2650 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2651 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2652 alu.op = LDS_OP3_LDS_WRITE_REL;
2653 alu.src[0].sel = temp_reg;
2654 alu.src[0].chan = chan;
2655 alu.src[1].sel = ctx->shader->output[i].gpr;
2656 alu.src[1].chan = j * 2;
2657 alu.src[2].sel = ctx->shader->output[i].gpr;
2658 alu.src[2].chan = (j * 2) + 1;
2659 alu.last = 1;
2660 alu.dst.chan = 0;
2661 alu.lds_idx = 1;
2662 alu.is_lds_idx_op = true;
2663 r = r600_bytecode_add_alu(ctx->bc, &alu);
2664 if (r)
2665 return r;
2666 }
2667 }
2668 return 0;
2669 }
2670
2671 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
2672 {
2673 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2674 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
2675 int i, r, lasti;
2676 int temp_reg = r600_get_temp(ctx);
2677 struct r600_bytecode_alu alu;
2678 unsigned write_mask = dst->Register.WriteMask;
2679
2680 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
2681 return 0;
2682
2683 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
2684 if (r)
2685 return r;
2686
2687 /* the base address is now in temp.x */
2688 r = r600_get_byte_address(ctx, temp_reg,
2689 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
2690 if (r)
2691 return r;
2692
2693 /* LDS write */
2694 lasti = tgsi_last_instruction(write_mask);
2695 for (i = 1; i <= lasti; i++) {
2696
2697 if (!(write_mask & (1 << i)))
2698 continue;
2699 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2700 temp_reg, i,
2701 temp_reg, 0,
2702 V_SQ_ALU_SRC_LITERAL, 4 * i);
2703 if (r)
2704 return r;
2705 }
2706
2707 for (i = 0; i <= lasti; i++) {
2708 if (!(write_mask & (1 << i)))
2709 continue;
2710
2711 if ((i == 0 && ((write_mask & 3) == 3)) ||
2712 (i == 2 && ((write_mask & 0xc) == 0xc))) {
2713 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2714 alu.op = LDS_OP3_LDS_WRITE_REL;
2715 alu.src[0].sel = temp_reg;
2716 alu.src[0].chan = i;
2717
2718 alu.src[1].sel = dst->Register.Index;
2719 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2720 alu.src[1].chan = i;
2721
2722 alu.src[2].sel = dst->Register.Index;
2723 alu.src[2].sel += ctx->file_offset[dst->Register.File];
2724 alu.src[2].chan = i + 1;
2725 alu.lds_idx = 1;
2726 alu.dst.chan = 0;
2727 alu.last = 1;
2728 alu.is_lds_idx_op = true;
2729 r = r600_bytecode_add_alu(ctx->bc, &alu);
2730 if (r)
2731 return r;
2732 i += 1;
2733 continue;
2734 }
2735 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2736 alu.op = LDS_OP2_LDS_WRITE;
2737 alu.src[0].sel = temp_reg;
2738 alu.src[0].chan = i;
2739
2740 alu.src[1].sel = dst->Register.Index;
2741 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2742 alu.src[1].chan = i;
2743
2744 alu.src[2].sel = V_SQ_ALU_SRC_0;
2745 alu.dst.chan = 0;
2746 alu.last = 1;
2747 alu.is_lds_idx_op = true;
2748 r = r600_bytecode_add_alu(ctx->bc, &alu);
2749 if (r)
2750 return r;
2751 }
2752 return 0;
2753 }
2754
2755 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
2756 int output_idx)
2757 {
2758 int param;
2759 unsigned temp_reg = r600_get_temp(ctx);
2760 unsigned name = ctx->shader->output[output_idx].name;
2761 int dreg = ctx->shader->output[output_idx].gpr;
2762 int r;
2763
2764 param = r600_get_lds_unique_index(name, 0);
2765 r = get_lds_offset0(ctx, 1, temp_reg, true);
2766 if (r)
2767 return r;
2768
2769 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2770 temp_reg, 0,
2771 temp_reg, 0,
2772 V_SQ_ALU_SRC_LITERAL, param * 16);
2773 if (r)
2774 return r;
2775
2776 do_lds_fetch_values(ctx, temp_reg, dreg);
2777 return 0;
2778 }
2779
2780 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
2781 {
2782 unsigned i;
2783 int stride, outer_comps, inner_comps;
2784 int tessinner_idx = -1, tessouter_idx = -1;
2785 int r;
2786 int temp_reg = r600_get_temp(ctx);
2787 int treg[3] = {-1, -1, -1};
2788 struct r600_bytecode_alu alu;
2789 struct r600_bytecode_cf *cf_jump, *cf_pop;
2790
2791 /* only execute factor emission for invocation 0 */
2792 /* PRED_SETE_INT __, R0.x, 0 */
2793 memset(&alu, 0, sizeof(alu));
2794 alu.op = ALU_OP2_PRED_SETE_INT;
2795 alu.src[0].chan = 2;
2796 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2797 alu.execute_mask = 1;
2798 alu.update_pred = 1;
2799 alu.last = 1;
2800 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2801
2802 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
2803 cf_jump = ctx->bc->cf_last;
2804
2805 treg[0] = r600_get_temp(ctx);
2806 switch (ctx->shader->tcs_prim_mode) {
2807 case PIPE_PRIM_LINES:
2808 stride = 8; /* 2 dwords, 1 vec2 store */
2809 outer_comps = 2;
2810 inner_comps = 0;
2811 break;
2812 case PIPE_PRIM_TRIANGLES:
2813 stride = 16; /* 4 dwords, 1 vec4 store */
2814 outer_comps = 3;
2815 inner_comps = 1;
2816 treg[1] = r600_get_temp(ctx);
2817 break;
2818 case PIPE_PRIM_QUADS:
2819 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2820 outer_comps = 4;
2821 inner_comps = 2;
2822 treg[1] = r600_get_temp(ctx);
2823 treg[2] = r600_get_temp(ctx);
2824 break;
2825 default:
2826 assert(0);
2827 return -1;
2828 }
2829
2830 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2831 /* TF_WRITE takes index in R.x, value in R.y */
2832 for (i = 0; i < ctx->shader->noutput; i++) {
2833 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSINNER)
2834 tessinner_idx = i;
2835 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSOUTER)
2836 tessouter_idx = i;
2837 }
2838
2839 if (tessouter_idx == -1)
2840 return -1;
2841
2842 if (tessinner_idx == -1 && inner_comps)
2843 return -1;
2844
2845 if (tessouter_idx != -1) {
2846 r = r600_tess_factor_read(ctx, tessouter_idx);
2847 if (r)
2848 return r;
2849 }
2850
2851 if (tessinner_idx != -1) {
2852 r = r600_tess_factor_read(ctx, tessinner_idx);
2853 if (r)
2854 return r;
2855 }
2856
2857 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2858 /* r.x = relpatchid(r0.y) * tf_stride */
2859
2860 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2861 /* add incoming r0.w to it: t.x = t.x + r0.w */
2862 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2863 temp_reg, 0,
2864 0, 1,
2865 V_SQ_ALU_SRC_LITERAL, stride,
2866 0, 3);
2867 if (r)
2868 return r;
2869
2870 for (i = 0; i < outer_comps + inner_comps; i++) {
2871 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
2872 int out_comp = i >= outer_comps ? i - outer_comps : i;
2873
2874 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2875 treg[i / 2], (2 * (i % 2)),
2876 temp_reg, 0,
2877 V_SQ_ALU_SRC_LITERAL, 4 * i);
2878 if (r)
2879 return r;
2880 r = single_alu_op2(ctx, ALU_OP1_MOV,
2881 treg[i / 2], 1 + (2 * (i%2)),
2882 ctx->shader->output[out_idx].gpr, out_comp,
2883 0, 0);
2884 if (r)
2885 return r;
2886 }
2887 for (i = 0; i < outer_comps + inner_comps; i++) {
2888 struct r600_bytecode_gds gds;
2889
2890 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
2891 gds.src_gpr = treg[i / 2];
2892 gds.src_sel_x = 2 * (i % 2);
2893 gds.src_sel_y = 1 + (2 * (i % 2));
2894 gds.src_sel_z = 4;
2895 gds.dst_sel_x = 7;
2896 gds.dst_sel_y = 7;
2897 gds.dst_sel_z = 7;
2898 gds.dst_sel_w = 7;
2899 gds.op = FETCH_OP_TF_WRITE;
2900 r = r600_bytecode_add_gds(ctx->bc, &gds);
2901 if (r)
2902 return r;
2903 }
2904
2905 // Patch up jump label
2906 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
2907 cf_pop = ctx->bc->cf_last;
2908
2909 cf_jump->cf_addr = cf_pop->id + 2;
2910 cf_jump->pop_count = 1;
2911 cf_pop->cf_addr = cf_pop->id + 2;
2912 cf_pop->pop_count = 1;
2913
2914 return 0;
2915 }
2916
2917 static int r600_shader_from_tgsi(struct r600_context *rctx,
2918 struct r600_pipe_shader *pipeshader,
2919 union r600_shader_key key)
2920 {
2921 struct r600_screen *rscreen = rctx->screen;
2922 struct r600_shader *shader = &pipeshader->shader;
2923 struct tgsi_token *tokens = pipeshader->selector->tokens;
2924 struct pipe_stream_output_info so = pipeshader->selector->so;
2925 struct tgsi_full_immediate *immediate;
2926 struct r600_shader_ctx ctx;
2927 struct r600_bytecode_output output[32];
2928 unsigned output_done, noutput;
2929 unsigned opcode;
2930 int i, j, k, r = 0;
2931 int next_param_base = 0, next_clip_base;
2932 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
2933 bool indirect_gprs;
2934 bool ring_outputs = false;
2935 bool lds_outputs = false;
2936 bool lds_inputs = false;
2937 bool pos_emitted = false;
2938
2939 ctx.bc = &shader->bc;
2940 ctx.shader = shader;
2941 ctx.native_integers = true;
2942
2943 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
2944 rscreen->has_compressed_msaa_texturing);
2945 ctx.tokens = tokens;
2946 tgsi_scan_shader(tokens, &ctx.info);
2947 shader->indirect_files = ctx.info.indirect_files;
2948
2949 shader->uses_doubles = ctx.info.uses_doubles;
2950
2951 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
2952 tgsi_parse_init(&ctx.parse, tokens);
2953 ctx.type = ctx.info.processor;
2954 shader->processor_type = ctx.type;
2955 ctx.bc->type = shader->processor_type;
2956
2957 switch (ctx.type) {
2958 case PIPE_SHADER_VERTEX:
2959 shader->vs_as_gs_a = key.vs.as_gs_a;
2960 shader->vs_as_es = key.vs.as_es;
2961 shader->vs_as_ls = key.vs.as_ls;
2962 if (shader->vs_as_es)
2963 ring_outputs = true;
2964 if (shader->vs_as_ls)
2965 lds_outputs = true;
2966 break;
2967 case PIPE_SHADER_GEOMETRY:
2968 ring_outputs = true;
2969 break;
2970 case PIPE_SHADER_TESS_CTRL:
2971 shader->tcs_prim_mode = key.tcs.prim_mode;
2972 lds_outputs = true;
2973 lds_inputs = true;
2974 break;
2975 case PIPE_SHADER_TESS_EVAL:
2976 shader->tes_as_es = key.tes.as_es;
2977 lds_inputs = true;
2978 if (shader->tes_as_es)
2979 ring_outputs = true;
2980 break;
2981 case PIPE_SHADER_FRAGMENT:
2982 shader->two_side = key.ps.color_two_side;
2983 break;
2984 default:
2985 break;
2986 }
2987
2988 if (shader->vs_as_es || shader->tes_as_es) {
2989 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
2990 } else {
2991 ctx.gs_for_vs = NULL;
2992 }
2993
2994 ctx.next_ring_offset = 0;
2995 ctx.gs_out_ring_offset = 0;
2996 ctx.gs_next_vertex = 0;
2997 ctx.gs_stream_output_info = &so;
2998
2999 ctx.face_gpr = -1;
3000 ctx.fixed_pt_position_gpr = -1;
3001 ctx.fragcoord_input = -1;
3002 ctx.colors_used = 0;
3003 ctx.clip_vertex_write = 0;
3004
3005 shader->nr_ps_color_exports = 0;
3006 shader->nr_ps_max_color_exports = 0;
3007
3008
3009 /* register allocations */
3010 /* Values [0,127] correspond to GPR[0..127].
3011 * Values [128,159] correspond to constant buffer bank 0
3012 * Values [160,191] correspond to constant buffer bank 1
3013 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3014 * Values [256,287] correspond to constant buffer bank 2 (EG)
3015 * Values [288,319] correspond to constant buffer bank 3 (EG)
3016 * Other special values are shown in the list below.
3017 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3018 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3019 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3020 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3021 * 248 SQ_ALU_SRC_0: special constant 0.0.
3022 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3023 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3024 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3025 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3026 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3027 * 254 SQ_ALU_SRC_PV: previous vector result.
3028 * 255 SQ_ALU_SRC_PS: previous scalar result.
3029 */
3030 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3031 ctx.file_offset[i] = 0;
3032 }
3033
3034 if (ctx.type == PIPE_SHADER_VERTEX) {
3035 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3036 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3037 }
3038 if (ctx.type == PIPE_SHADER_FRAGMENT) {
3039 if (ctx.bc->chip_class >= EVERGREEN)
3040 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3041 else
3042 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3043 }
3044 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3045 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3046 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3047 }
3048 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3049 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3050 if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3051 bool add_tesscoord = false, add_tess_inout = false;
3052 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3053 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3054 /* if we have tesscoord save one reg */
3055 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3056 add_tesscoord = true;
3057 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3058 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3059 add_tess_inout = true;
3060 }
3061 if (add_tesscoord || add_tess_inout)
3062 ctx.file_offset[TGSI_FILE_INPUT]++;
3063 if (add_tess_inout)
3064 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3065 }
3066
3067 ctx.file_offset[TGSI_FILE_OUTPUT] =
3068 ctx.file_offset[TGSI_FILE_INPUT] +
3069 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3070 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3071 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3072
3073 /* Outside the GPR range. This will be translated to one of the
3074 * kcache banks later. */
3075 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3076
3077 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3078 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3079 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
3080 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
3081 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
3082
3083 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3084 ctx.tess_input_info = ctx.bc->ar_reg + 3;
3085 ctx.tess_output_info = ctx.bc->ar_reg + 4;
3086 ctx.temp_reg = ctx.bc->ar_reg + 5;
3087 } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3088 ctx.tess_input_info = 0;
3089 ctx.tess_output_info = ctx.bc->ar_reg + 3;
3090 ctx.temp_reg = ctx.bc->ar_reg + 4;
3091 } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
3092 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
3093 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
3094 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
3095 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
3096 ctx.temp_reg = ctx.bc->ar_reg + 7;
3097 } else {
3098 ctx.temp_reg = ctx.bc->ar_reg + 3;
3099 }
3100
3101 shader->max_arrays = 0;
3102 shader->num_arrays = 0;
3103 if (indirect_gprs) {
3104
3105 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3106 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3107 ctx.file_offset[TGSI_FILE_OUTPUT] -
3108 ctx.file_offset[TGSI_FILE_INPUT],
3109 0x0F);
3110 }
3111 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3112 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3113 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3114 ctx.file_offset[TGSI_FILE_OUTPUT],
3115 0x0F);
3116 }
3117 }
3118
3119 ctx.nliterals = 0;
3120 ctx.literals = NULL;
3121
3122 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3123 ctx.info.colors_written == 1;
3124 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3125 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3126
3127 if (shader->vs_as_gs_a)
3128 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3129
3130 if (ctx.type == PIPE_SHADER_TESS_EVAL)
3131 r600_fetch_tess_io_info(&ctx);
3132
3133 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3134 tgsi_parse_token(&ctx.parse);
3135 switch (ctx.parse.FullToken.Token.Type) {
3136 case TGSI_TOKEN_TYPE_IMMEDIATE:
3137 immediate = &ctx.parse.FullToken.FullImmediate;
3138 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3139 if(ctx.literals == NULL) {
3140 r = -ENOMEM;
3141 goto out_err;
3142 }
3143 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3144 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3145 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3146 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3147 ctx.nliterals++;
3148 break;
3149 case TGSI_TOKEN_TYPE_DECLARATION:
3150 r = tgsi_declaration(&ctx);
3151 if (r)
3152 goto out_err;
3153 break;
3154 case TGSI_TOKEN_TYPE_INSTRUCTION:
3155 case TGSI_TOKEN_TYPE_PROPERTY:
3156 break;
3157 default:
3158 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3159 r = -EINVAL;
3160 goto out_err;
3161 }
3162 }
3163
3164 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3165 shader->ring_item_sizes[1] = 0;
3166 shader->ring_item_sizes[2] = 0;
3167 shader->ring_item_sizes[3] = 0;
3168
3169 /* Process two side if needed */
3170 if (shader->two_side && ctx.colors_used) {
3171 int i, count = ctx.shader->ninput;
3172 unsigned next_lds_loc = ctx.shader->nlds;
3173
3174 /* additional inputs will be allocated right after the existing inputs,
3175 * we won't need them after the color selection, so we don't need to
3176 * reserve these gprs for the rest of the shader code and to adjust
3177 * output offsets etc. */
3178 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3179 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3180
3181 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3182 if (ctx.face_gpr == -1) {
3183 i = ctx.shader->ninput++;
3184 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3185 ctx.shader->input[i].spi_sid = 0;
3186 ctx.shader->input[i].gpr = gpr++;
3187 ctx.face_gpr = ctx.shader->input[i].gpr;
3188 }
3189
3190 for (i = 0; i < count; i++) {
3191 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3192 int ni = ctx.shader->ninput++;
3193 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3194 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3195 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3196 ctx.shader->input[ni].gpr = gpr++;
3197 // TGSI to LLVM needs to know the lds position of inputs.
3198 // Non LLVM path computes it later (in process_twoside_color)
3199 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3200 ctx.shader->input[i].back_color_input = ni;
3201 if (ctx.bc->chip_class >= EVERGREEN) {
3202 if ((r = evergreen_interp_input(&ctx, ni)))
3203 return r;
3204 }
3205 }
3206 }
3207 }
3208
3209 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3210 shader->nr_ps_max_color_exports = 8;
3211
3212 if (ctx.fragcoord_input >= 0) {
3213 if (ctx.bc->chip_class == CAYMAN) {
3214 for (j = 0 ; j < 4; j++) {
3215 struct r600_bytecode_alu alu;
3216 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3217 alu.op = ALU_OP1_RECIP_IEEE;
3218 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3219 alu.src[0].chan = 3;
3220
3221 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3222 alu.dst.chan = j;
3223 alu.dst.write = (j == 3);
3224 alu.last = 1;
3225 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3226 return r;
3227 }
3228 } else {
3229 struct r600_bytecode_alu alu;
3230 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3231 alu.op = ALU_OP1_RECIP_IEEE;
3232 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3233 alu.src[0].chan = 3;
3234
3235 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3236 alu.dst.chan = 3;
3237 alu.dst.write = 1;
3238 alu.last = 1;
3239 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3240 return r;
3241 }
3242 }
3243
3244 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3245 struct r600_bytecode_alu alu;
3246 int r;
3247
3248 /* GS thread with no output workaround - emit a cut at start of GS */
3249 if (ctx.bc->chip_class == R600)
3250 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3251
3252 for (j = 0; j < 4; j++) {
3253 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3254 alu.op = ALU_OP1_MOV;
3255 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3256 alu.src[0].value = 0;
3257 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3258 alu.dst.write = 1;
3259 alu.last = 1;
3260 r = r600_bytecode_add_alu(ctx.bc, &alu);
3261 if (r)
3262 return r;
3263 }
3264 }
3265
3266 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3267 r600_fetch_tess_io_info(&ctx);
3268
3269 if (shader->two_side && ctx.colors_used) {
3270 if ((r = process_twoside_color_inputs(&ctx)))
3271 return r;
3272 }
3273
3274 tgsi_parse_init(&ctx.parse, tokens);
3275 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3276 tgsi_parse_token(&ctx.parse);
3277 switch (ctx.parse.FullToken.Token.Type) {
3278 case TGSI_TOKEN_TYPE_INSTRUCTION:
3279 r = tgsi_is_supported(&ctx);
3280 if (r)
3281 goto out_err;
3282 ctx.max_driver_temp_used = 0;
3283 /* reserve first tmp for everyone */
3284 r600_get_temp(&ctx);
3285
3286 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3287 if ((r = tgsi_split_constant(&ctx)))
3288 goto out_err;
3289 if ((r = tgsi_split_literal_constant(&ctx)))
3290 goto out_err;
3291 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3292 if ((r = tgsi_split_gs_inputs(&ctx)))
3293 goto out_err;
3294 } else if (lds_inputs) {
3295 if ((r = tgsi_split_lds_inputs(&ctx)))
3296 goto out_err;
3297 }
3298 if (ctx.bc->chip_class == CAYMAN)
3299 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3300 else if (ctx.bc->chip_class >= EVERGREEN)
3301 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3302 else
3303 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3304 r = ctx.inst_info->process(&ctx);
3305 if (r)
3306 goto out_err;
3307
3308 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3309 r = r600_store_tcs_output(&ctx);
3310 if (r)
3311 goto out_err;
3312 }
3313 break;
3314 default:
3315 break;
3316 }
3317 }
3318
3319 /* Reset the temporary register counter. */
3320 ctx.max_driver_temp_used = 0;
3321
3322 noutput = shader->noutput;
3323
3324 if (!ring_outputs && ctx.clip_vertex_write) {
3325 unsigned clipdist_temp[2];
3326
3327 clipdist_temp[0] = r600_get_temp(&ctx);
3328 clipdist_temp[1] = r600_get_temp(&ctx);
3329
3330 /* need to convert a clipvertex write into clipdistance writes and not export
3331 the clip vertex anymore */
3332
3333 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3334 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3335 shader->output[noutput].gpr = clipdist_temp[0];
3336 noutput++;
3337 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3338 shader->output[noutput].gpr = clipdist_temp[1];
3339 noutput++;
3340
3341 /* reset spi_sid for clipvertex output to avoid confusing spi */
3342 shader->output[ctx.cv_output].spi_sid = 0;
3343
3344 shader->clip_dist_write = 0xFF;
3345
3346 for (i = 0; i < 8; i++) {
3347 int oreg = i >> 2;
3348 int ochan = i & 3;
3349
3350 for (j = 0; j < 4; j++) {
3351 struct r600_bytecode_alu alu;
3352 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3353 alu.op = ALU_OP2_DOT4;
3354 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3355 alu.src[0].chan = j;
3356
3357 alu.src[1].sel = 512 + i;
3358 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3359 alu.src[1].chan = j;
3360
3361 alu.dst.sel = clipdist_temp[oreg];
3362 alu.dst.chan = j;
3363 alu.dst.write = (j == ochan);
3364 if (j == 3)
3365 alu.last = 1;
3366 r = r600_bytecode_add_alu(ctx.bc, &alu);
3367 if (r)
3368 return r;
3369 }
3370 }
3371 }
3372
3373 /* Add stream outputs. */
3374 if (so.num_outputs) {
3375 bool emit = false;
3376 if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
3377 emit = true;
3378 if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
3379 emit = true;
3380 if (emit)
3381 emit_streamout(&ctx, &so, -1, NULL);
3382 }
3383 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3384 convert_edgeflag_to_int(&ctx);
3385
3386 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3387 r600_emit_tess_factor(&ctx);
3388
3389 if (lds_outputs) {
3390 if (ctx.type == PIPE_SHADER_VERTEX) {
3391 if (ctx.shader->noutput)
3392 emit_lds_vs_writes(&ctx);
3393 }
3394 } else if (ring_outputs) {
3395 if (shader->vs_as_es || shader->tes_as_es) {
3396 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3397 ctx.gs_export_gpr_tregs[1] = -1;
3398 ctx.gs_export_gpr_tregs[2] = -1;
3399 ctx.gs_export_gpr_tregs[3] = -1;
3400
3401 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3402 }
3403 } else {
3404 /* Export output */
3405 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3406
3407 for (i = 0, j = 0; i < noutput; i++, j++) {
3408 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3409 output[j].gpr = shader->output[i].gpr;
3410 output[j].elem_size = 3;
3411 output[j].swizzle_x = 0;
3412 output[j].swizzle_y = 1;
3413 output[j].swizzle_z = 2;
3414 output[j].swizzle_w = 3;
3415 output[j].burst_count = 1;
3416 output[j].type = -1;
3417 output[j].op = CF_OP_EXPORT;
3418 switch (ctx.type) {
3419 case PIPE_SHADER_VERTEX:
3420 case PIPE_SHADER_TESS_EVAL:
3421 switch (shader->output[i].name) {
3422 case TGSI_SEMANTIC_POSITION:
3423 output[j].array_base = 60;
3424 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3425 pos_emitted = true;
3426 break;
3427
3428 case TGSI_SEMANTIC_PSIZE:
3429 output[j].array_base = 61;
3430 output[j].swizzle_y = 7;
3431 output[j].swizzle_z = 7;
3432 output[j].swizzle_w = 7;
3433 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3434 pos_emitted = true;
3435 break;
3436 case TGSI_SEMANTIC_EDGEFLAG:
3437 output[j].array_base = 61;
3438 output[j].swizzle_x = 7;
3439 output[j].swizzle_y = 0;
3440 output[j].swizzle_z = 7;
3441 output[j].swizzle_w = 7;
3442 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3443 pos_emitted = true;
3444 break;
3445 case TGSI_SEMANTIC_LAYER:
3446 /* spi_sid is 0 for outputs that are
3447 * not consumed by PS */
3448 if (shader->output[i].spi_sid) {
3449 output[j].array_base = next_param_base++;
3450 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3451 j++;
3452 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3453 }
3454 output[j].array_base = 61;
3455 output[j].swizzle_x = 7;
3456 output[j].swizzle_y = 7;
3457 output[j].swizzle_z = 0;
3458 output[j].swizzle_w = 7;
3459 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3460 pos_emitted = true;
3461 break;
3462 case TGSI_SEMANTIC_VIEWPORT_INDEX:
3463 /* spi_sid is 0 for outputs that are
3464 * not consumed by PS */
3465 if (shader->output[i].spi_sid) {
3466 output[j].array_base = next_param_base++;
3467 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3468 j++;
3469 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3470 }
3471 output[j].array_base = 61;
3472 output[j].swizzle_x = 7;
3473 output[j].swizzle_y = 7;
3474 output[j].swizzle_z = 7;
3475 output[j].swizzle_w = 0;
3476 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3477 pos_emitted = true;
3478 break;
3479 case TGSI_SEMANTIC_CLIPVERTEX:
3480 j--;
3481 break;
3482 case TGSI_SEMANTIC_CLIPDIST:
3483 output[j].array_base = next_clip_base++;
3484 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3485 pos_emitted = true;
3486 /* spi_sid is 0 for clipdistance outputs that were generated
3487 * for clipvertex - we don't need to pass them to PS */
3488 if (shader->output[i].spi_sid) {
3489 j++;
3490 /* duplicate it as PARAM to pass to the pixel shader */
3491 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3492 output[j].array_base = next_param_base++;
3493 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3494 }
3495 break;
3496 case TGSI_SEMANTIC_FOG:
3497 output[j].swizzle_y = 4; /* 0 */
3498 output[j].swizzle_z = 4; /* 0 */
3499 output[j].swizzle_w = 5; /* 1 */
3500 break;
3501 case TGSI_SEMANTIC_PRIMID:
3502 output[j].swizzle_x = 2;
3503 output[j].swizzle_y = 4; /* 0 */
3504 output[j].swizzle_z = 4; /* 0 */
3505 output[j].swizzle_w = 4; /* 0 */
3506 break;
3507 }
3508
3509 break;
3510 case PIPE_SHADER_FRAGMENT:
3511 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
3512 /* never export more colors than the number of CBs */
3513 if (shader->output[i].sid >= max_color_exports) {
3514 /* skip export */
3515 j--;
3516 continue;
3517 }
3518 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3519 output[j].array_base = shader->output[i].sid;
3520 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3521 shader->nr_ps_color_exports++;
3522 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
3523 for (k = 1; k < max_color_exports; k++) {
3524 j++;
3525 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3526 output[j].gpr = shader->output[i].gpr;
3527 output[j].elem_size = 3;
3528 output[j].swizzle_x = 0;
3529 output[j].swizzle_y = 1;
3530 output[j].swizzle_z = 2;
3531 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3532 output[j].burst_count = 1;
3533 output[j].array_base = k;
3534 output[j].op = CF_OP_EXPORT;
3535 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3536 shader->nr_ps_color_exports++;
3537 }
3538 }
3539 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
3540 output[j].array_base = 61;
3541 output[j].swizzle_x = 2;
3542 output[j].swizzle_y = 7;
3543 output[j].swizzle_z = output[j].swizzle_w = 7;
3544 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3545 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
3546 output[j].array_base = 61;
3547 output[j].swizzle_x = 7;
3548 output[j].swizzle_y = 1;
3549 output[j].swizzle_z = output[j].swizzle_w = 7;
3550 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3551 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3552 output[j].array_base = 61;
3553 output[j].swizzle_x = 7;
3554 output[j].swizzle_y = 7;
3555 output[j].swizzle_z = 0;
3556 output[j].swizzle_w = 7;
3557 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3558 } else {
3559 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
3560 r = -EINVAL;
3561 goto out_err;
3562 }
3563 break;
3564 case PIPE_SHADER_TESS_CTRL:
3565 break;
3566 default:
3567 R600_ERR("unsupported processor type %d\n", ctx.type);
3568 r = -EINVAL;
3569 goto out_err;
3570 }
3571
3572 if (output[j].type==-1) {
3573 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3574 output[j].array_base = next_param_base++;
3575 }
3576 }
3577
3578 /* add fake position export */
3579 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
3580 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3581 output[j].gpr = 0;
3582 output[j].elem_size = 3;
3583 output[j].swizzle_x = 7;
3584 output[j].swizzle_y = 7;
3585 output[j].swizzle_z = 7;
3586 output[j].swizzle_w = 7;
3587 output[j].burst_count = 1;
3588 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3589 output[j].array_base = 60;
3590 output[j].op = CF_OP_EXPORT;
3591 j++;
3592 }
3593
3594 /* add fake param output for vertex shader if no param is exported */
3595 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
3596 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3597 output[j].gpr = 0;
3598 output[j].elem_size = 3;
3599 output[j].swizzle_x = 7;
3600 output[j].swizzle_y = 7;
3601 output[j].swizzle_z = 7;
3602 output[j].swizzle_w = 7;
3603 output[j].burst_count = 1;
3604 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3605 output[j].array_base = 0;
3606 output[j].op = CF_OP_EXPORT;
3607 j++;
3608 }
3609
3610 /* add fake pixel export */
3611 if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
3612 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3613 output[j].gpr = 0;
3614 output[j].elem_size = 3;
3615 output[j].swizzle_x = 7;
3616 output[j].swizzle_y = 7;
3617 output[j].swizzle_z = 7;
3618 output[j].swizzle_w = 7;
3619 output[j].burst_count = 1;
3620 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3621 output[j].array_base = 0;
3622 output[j].op = CF_OP_EXPORT;
3623 j++;
3624 shader->nr_ps_color_exports++;
3625 }
3626
3627 noutput = j;
3628
3629 /* set export done on last export of each type */
3630 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
3631 if (!(output_done & (1 << output[i].type))) {
3632 output_done |= (1 << output[i].type);
3633 output[i].op = CF_OP_EXPORT_DONE;
3634 }
3635 }
3636 /* add output to bytecode */
3637 for (i = 0; i < noutput; i++) {
3638 r = r600_bytecode_add_output(ctx.bc, &output[i]);
3639 if (r)
3640 goto out_err;
3641 }
3642 }
3643
3644 /* add program end */
3645 if (ctx.bc->chip_class == CAYMAN)
3646 cm_bytecode_add_cf_end(ctx.bc);
3647 else {
3648 const struct cf_op_info *last = NULL;
3649
3650 if (ctx.bc->cf_last)
3651 last = r600_isa_cf(ctx.bc->cf_last->op);
3652
3653 /* alu clause instructions don't have EOP bit, so add NOP */
3654 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS || ctx.bc->cf_last->op == CF_OP_POP || ctx.bc->cf_last->op == CF_OP_GDS)
3655 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
3656
3657 ctx.bc->cf_last->end_of_program = 1;
3658 }
3659
3660 /* check GPR limit - we have 124 = 128 - 4
3661 * (4 are reserved as alu clause temporary registers) */
3662 if (ctx.bc->ngpr > 124) {
3663 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
3664 r = -ENOMEM;
3665 goto out_err;
3666 }
3667
3668 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3669 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
3670 return r;
3671 }
3672
3673 free(ctx.literals);
3674 tgsi_parse_free(&ctx.parse);
3675 return 0;
3676 out_err:
3677 free(ctx.literals);
3678 tgsi_parse_free(&ctx.parse);
3679 return r;
3680 }
3681
3682 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
3683 {
3684 const unsigned tgsi_opcode =
3685 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
3686 R600_ERR("%s tgsi opcode unsupported\n",
3687 tgsi_get_opcode_name(tgsi_opcode));
3688 return -EINVAL;
3689 }
3690
3691 static int tgsi_end(struct r600_shader_ctx *ctx)
3692 {
3693 return 0;
3694 }
3695
3696 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
3697 const struct r600_shader_src *shader_src,
3698 unsigned chan)
3699 {
3700 bc_src->sel = shader_src->sel;
3701 bc_src->chan = shader_src->swizzle[chan];
3702 bc_src->neg = shader_src->neg;
3703 bc_src->abs = shader_src->abs;
3704 bc_src->rel = shader_src->rel;
3705 bc_src->value = shader_src->value[bc_src->chan];
3706 bc_src->kc_bank = shader_src->kc_bank;
3707 bc_src->kc_rel = shader_src->kc_rel;
3708 }
3709
3710 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
3711 {
3712 bc_src->abs = 1;
3713 bc_src->neg = 0;
3714 }
3715
3716 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
3717 {
3718 bc_src->neg = !bc_src->neg;
3719 }
3720
3721 static void tgsi_dst(struct r600_shader_ctx *ctx,
3722 const struct tgsi_full_dst_register *tgsi_dst,
3723 unsigned swizzle,
3724 struct r600_bytecode_alu_dst *r600_dst)
3725 {
3726 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3727
3728 r600_dst->sel = tgsi_dst->Register.Index;
3729 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
3730 r600_dst->chan = swizzle;
3731 r600_dst->write = 1;
3732 if (inst->Instruction.Saturate) {
3733 r600_dst->clamp = 1;
3734 }
3735 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
3736 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
3737 return;
3738 }
3739 }
3740 if (tgsi_dst->Register.Indirect)
3741 r600_dst->rel = V_SQ_REL_RELATIVE;
3742
3743 }
3744
3745 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
3746 {
3747 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3748 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3749 struct r600_bytecode_alu alu;
3750 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3751 int use_tmp = 0;
3752
3753 if (singledest) {
3754 switch (write_mask) {
3755 case 0x1:
3756 write_mask = 0x3;
3757 break;
3758 case 0x2:
3759 use_tmp = 1;
3760 write_mask = 0x3;
3761 break;
3762 case 0x4:
3763 write_mask = 0xc;
3764 break;
3765 case 0x8:
3766 write_mask = 0xc;
3767 use_tmp = 3;
3768 break;
3769 }
3770 }
3771
3772 lasti = tgsi_last_instruction(write_mask);
3773 for (i = 0; i <= lasti; i++) {
3774
3775 if (!(write_mask & (1 << i)))
3776 continue;
3777
3778 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3779
3780 if (singledest) {
3781 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3782 if (use_tmp) {
3783 alu.dst.sel = ctx->temp_reg;
3784 alu.dst.chan = i;
3785 alu.dst.write = 1;
3786 }
3787 if (i == 1 || i == 3)
3788 alu.dst.write = 0;
3789 } else
3790 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3791
3792 alu.op = ctx->inst_info->op;
3793 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
3794 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3795 } else if (!swap) {
3796 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3797 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
3798 }
3799 } else {
3800 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
3801 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
3802 }
3803
3804 /* handle some special cases */
3805 if (i == 1 || i == 3) {
3806 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
3807 case TGSI_OPCODE_DABS:
3808 r600_bytecode_src_set_abs(&alu.src[0]);
3809 break;
3810 default:
3811 break;
3812 }
3813 }
3814 if (i == lasti) {
3815 alu.last = 1;
3816 }
3817 r = r600_bytecode_add_alu(ctx->bc, &alu);
3818 if (r)
3819 return r;
3820 }
3821
3822 if (use_tmp) {
3823 write_mask = inst->Dst[0].Register.WriteMask;
3824
3825 /* move result from temp to dst */
3826 for (i = 0; i <= lasti; i++) {
3827 if (!(write_mask & (1 << i)))
3828 continue;
3829
3830 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3831 alu.op = ALU_OP1_MOV;
3832 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3833 alu.src[0].sel = ctx->temp_reg;
3834 alu.src[0].chan = use_tmp - 1;
3835 alu.last = (i == lasti);
3836
3837 r = r600_bytecode_add_alu(ctx->bc, &alu);
3838 if (r)
3839 return r;
3840 }
3841 }
3842 return 0;
3843 }
3844
3845 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
3846 {
3847 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3848 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3849 /* confirm writemasking */
3850 if ((write_mask & 0x3) != 0x3 &&
3851 (write_mask & 0xc) != 0xc) {
3852 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
3853 return -1;
3854 }
3855 return tgsi_op2_64_params(ctx, false, false);
3856 }
3857
3858 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
3859 {
3860 return tgsi_op2_64_params(ctx, true, false);
3861 }
3862
3863 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
3864 {
3865 return tgsi_op2_64_params(ctx, true, true);
3866 }
3867
3868 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
3869 {
3870 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3871 struct r600_bytecode_alu alu;
3872 int i, j, r;
3873 int lasti = 3;
3874 int tmp = r600_get_temp(ctx);
3875
3876 for (i = 0; i < lasti + 1; i++) {
3877
3878 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3879 alu.op = ctx->inst_info->op;
3880 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3881 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
3882 }
3883
3884 if (inst->Dst[0].Register.WriteMask & (1 << i))
3885 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3886 else
3887 alu.dst.sel = tmp;
3888
3889 alu.dst.chan = i;
3890 alu.is_op3 = 1;
3891 if (i == lasti) {
3892 alu.last = 1;
3893 }
3894 r = r600_bytecode_add_alu(ctx->bc, &alu);
3895 if (r)
3896 return r;
3897 }
3898 return 0;
3899 }
3900
3901 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
3902 {
3903 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3904 struct r600_bytecode_alu alu;
3905 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3906 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3907 /* use temp register if trans_only and more than one dst component */
3908 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
3909 unsigned op = ctx->inst_info->op;
3910
3911 if (op == ALU_OP2_MUL_IEEE &&
3912 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
3913 op = ALU_OP2_MUL;
3914
3915 for (i = 0; i <= lasti; i++) {
3916 if (!(write_mask & (1 << i)))
3917 continue;
3918
3919 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3920 if (use_tmp) {
3921 alu.dst.sel = ctx->temp_reg;
3922 alu.dst.chan = i;
3923 alu.dst.write = 1;
3924 } else
3925 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3926
3927 alu.op = op;
3928 if (!swap) {
3929 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3930 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3931 }
3932 } else {
3933 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3934 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3935 }
3936 if (i == lasti || trans_only) {
3937 alu.last = 1;
3938 }
3939 r = r600_bytecode_add_alu(ctx->bc, &alu);
3940 if (r)
3941 return r;
3942 }
3943
3944 if (use_tmp) {
3945 /* move result from temp to dst */
3946 for (i = 0; i <= lasti; i++) {
3947 if (!(write_mask & (1 << i)))
3948 continue;
3949
3950 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3951 alu.op = ALU_OP1_MOV;
3952 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3953 alu.src[0].sel = ctx->temp_reg;
3954 alu.src[0].chan = i;
3955 alu.last = (i == lasti);
3956
3957 r = r600_bytecode_add_alu(ctx->bc, &alu);
3958 if (r)
3959 return r;
3960 }
3961 }
3962 return 0;
3963 }
3964
3965 static int tgsi_op2(struct r600_shader_ctx *ctx)
3966 {
3967 return tgsi_op2_s(ctx, 0, 0);
3968 }
3969
3970 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
3971 {
3972 return tgsi_op2_s(ctx, 1, 0);
3973 }
3974
3975 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
3976 {
3977 return tgsi_op2_s(ctx, 0, 1);
3978 }
3979
3980 static int tgsi_ineg(struct r600_shader_ctx *ctx)
3981 {
3982 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3983 struct r600_bytecode_alu alu;
3984 int i, r;
3985 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3986
3987 for (i = 0; i < lasti + 1; i++) {
3988
3989 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3990 continue;
3991 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3992 alu.op = ctx->inst_info->op;
3993
3994 alu.src[0].sel = V_SQ_ALU_SRC_0;
3995
3996 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3997
3998 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3999
4000 if (i == lasti) {
4001 alu.last = 1;
4002 }
4003 r = r600_bytecode_add_alu(ctx->bc, &alu);
4004 if (r)
4005 return r;
4006 }
4007 return 0;
4008
4009 }
4010
4011 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4012 {
4013 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4014 struct r600_bytecode_alu alu;
4015 int i, r;
4016 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4017
4018 for (i = 0; i < lasti + 1; i++) {
4019
4020 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4021 continue;
4022 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4023 alu.op = ALU_OP1_MOV;
4024
4025 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4026
4027 if (i == 1 || i == 3)
4028 r600_bytecode_src_toggle_neg(&alu.src[0]);
4029 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4030
4031 if (i == lasti) {
4032 alu.last = 1;
4033 }
4034 r = r600_bytecode_add_alu(ctx->bc, &alu);
4035 if (r)
4036 return r;
4037 }
4038 return 0;
4039
4040 }
4041
4042 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4043 {
4044 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4045 struct r600_bytecode_alu alu;
4046 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4047 int i, j, r;
4048 int firsti = write_mask == 0xc ? 2 : 0;
4049
4050 for (i = 0; i <= 3; i++) {
4051 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4052 alu.op = ctx->inst_info->op;
4053
4054 alu.dst.sel = ctx->temp_reg;
4055 alu.dst.chan = i;
4056 alu.dst.write = 1;
4057 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4058 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4059 }
4060
4061 if (i == 3)
4062 alu.last = 1;
4063
4064 r = r600_bytecode_add_alu(ctx->bc, &alu);
4065 if (r)
4066 return r;
4067 }
4068
4069 /* MOV first two channels to writemask dst0 */
4070 for (i = 0; i <= 1; i++) {
4071 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4072 alu.op = ALU_OP1_MOV;
4073 alu.src[0].chan = i + 2;
4074 alu.src[0].sel = ctx->temp_reg;
4075
4076 tgsi_dst(ctx, &inst->Dst[0], firsti + i, &alu.dst);
4077 alu.dst.write = (inst->Dst[0].Register.WriteMask >> (firsti + i)) & 1;
4078 alu.last = 1;
4079 r = r600_bytecode_add_alu(ctx->bc, &alu);
4080 if (r)
4081 return r;
4082 }
4083
4084 for (i = 0; i <= 3; i++) {
4085 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4086 /* MOV third channels to writemask dst1 */
4087 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4088 alu.op = ALU_OP1_MOV;
4089 alu.src[0].chan = 1;
4090 alu.src[0].sel = ctx->temp_reg;
4091
4092 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4093 alu.last = 1;
4094 r = r600_bytecode_add_alu(ctx->bc, &alu);
4095 if (r)
4096 return r;
4097 break;
4098 }
4099 }
4100 return 0;
4101 }
4102
4103
4104 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4105 {
4106 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4107 struct r600_bytecode_alu alu;
4108 int i, r;
4109 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4110
4111 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4112 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4113
4114 for (i = 0; i <= (lasti+1)/2; i++) {
4115 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4116 alu.op = ctx->inst_info->op;
4117
4118 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4119 alu.dst.sel = ctx->temp_reg;
4120 alu.dst.chan = i;
4121 alu.dst.write = 1;
4122 alu.last = 1;
4123
4124 r = r600_bytecode_add_alu(ctx->bc, &alu);
4125 if (r)
4126 return r;
4127 }
4128
4129 for (i = 0; i <= lasti; i++) {
4130 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4131 alu.op = ALU_OP1_FLT32_TO_FLT64;
4132
4133 alu.src[0].chan = i/2;
4134 if (i%2 == 0)
4135 alu.src[0].sel = ctx->temp_reg;
4136 else {
4137 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4138 alu.src[0].value = 0x0;
4139 }
4140 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4141 alu.last = i == lasti;
4142
4143 r = r600_bytecode_add_alu(ctx->bc, &alu);
4144 if (r)
4145 return r;
4146 }
4147
4148 return 0;
4149 }
4150
4151 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4152 {
4153 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4154 struct r600_bytecode_alu alu;
4155 int i, r;
4156 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4157
4158 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4159 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4160
4161 for (i = 0; i <= lasti; i++) {
4162 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4163 alu.op = ALU_OP1_FLT64_TO_FLT32;
4164
4165 r600_bytecode_src(&alu.src[0], &ctx->src[0], fp64_switch(i));
4166 alu.dst.chan = i;
4167 alu.dst.sel = ctx->temp_reg;
4168 alu.dst.write = i%2 == 0;
4169 alu.last = i == lasti;
4170
4171 r = r600_bytecode_add_alu(ctx->bc, &alu);
4172 if (r)
4173 return r;
4174 }
4175
4176 for (i = 0; i <= (lasti+1)/2; i++) {
4177 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4178 alu.op = ctx->inst_info->op;
4179
4180 alu.src[0].chan = i*2;
4181 alu.src[0].sel = ctx->temp_reg;
4182 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4183 alu.last = 1;
4184
4185 r = r600_bytecode_add_alu(ctx->bc, &alu);
4186 if (r)
4187 return r;
4188 }
4189
4190 return 0;
4191 }
4192
4193 static int cayman_emit_unary_double_raw(struct r600_bytecode *bc,
4194 unsigned op,
4195 int dst_reg,
4196 struct r600_shader_src *src,
4197 bool abs)
4198 {
4199 struct r600_bytecode_alu alu;
4200 const int last_slot = 3;
4201 int r;
4202
4203 /* these have to write the result to X/Y by the looks of it */
4204 for (int i = 0 ; i < last_slot; i++) {
4205 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4206 alu.op = op;
4207
4208 r600_bytecode_src(&alu.src[0], src, 1);
4209 r600_bytecode_src(&alu.src[1], src, 0);
4210
4211 if (abs)
4212 r600_bytecode_src_set_abs(&alu.src[1]);
4213
4214 alu.dst.sel = dst_reg;
4215 alu.dst.chan = i;
4216 alu.dst.write = (i == 0 || i == 1);
4217
4218 if (bc->chip_class != CAYMAN || i == last_slot - 1)
4219 alu.last = 1;
4220 r = r600_bytecode_add_alu(bc, &alu);
4221 if (r)
4222 return r;
4223 }
4224
4225 return 0;
4226 }
4227
4228 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4229 {
4230 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4231 int i, r;
4232 struct r600_bytecode_alu alu;
4233 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4234 int t1 = ctx->temp_reg;
4235
4236 /* should only be one src regs */
4237 assert(inst->Instruction.NumSrcRegs == 1);
4238
4239 /* only support one double at a time */
4240 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4241 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4242
4243 r = cayman_emit_unary_double_raw(
4244 ctx->bc, ctx->inst_info->op, t1,
4245 &ctx->src[0],
4246 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4247 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT);
4248 if (r)
4249 return r;
4250
4251 for (i = 0 ; i <= lasti; i++) {
4252 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4253 continue;
4254 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4255 alu.op = ALU_OP1_MOV;
4256 alu.src[0].sel = t1;
4257 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
4258 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4259 alu.dst.write = 1;
4260 if (i == lasti)
4261 alu.last = 1;
4262 r = r600_bytecode_add_alu(ctx->bc, &alu);
4263 if (r)
4264 return r;
4265 }
4266 return 0;
4267 }
4268
4269 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
4270 {
4271 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4272 int i, j, r;
4273 struct r600_bytecode_alu alu;
4274 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4275
4276 for (i = 0 ; i < last_slot; i++) {
4277 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4278 alu.op = ctx->inst_info->op;
4279 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4280 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
4281
4282 /* RSQ should take the absolute value of src */
4283 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
4284 r600_bytecode_src_set_abs(&alu.src[j]);
4285 }
4286 }
4287 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4288 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4289
4290 if (i == last_slot - 1)
4291 alu.last = 1;
4292 r = r600_bytecode_add_alu(ctx->bc, &alu);
4293 if (r)
4294 return r;
4295 }
4296 return 0;
4297 }
4298
4299 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
4300 {
4301 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4302 int i, j, k, r;
4303 struct r600_bytecode_alu alu;
4304 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4305 int t1 = ctx->temp_reg;
4306
4307 for (k = 0; k <= lasti; k++) {
4308 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
4309 continue;
4310
4311 for (i = 0 ; i < 4; i++) {
4312 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4313 alu.op = ctx->inst_info->op;
4314 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4315 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
4316 }
4317 alu.dst.sel = t1;
4318 alu.dst.chan = i;
4319 alu.dst.write = (i == k);
4320 if (i == 3)
4321 alu.last = 1;
4322 r = r600_bytecode_add_alu(ctx->bc, &alu);
4323 if (r)
4324 return r;
4325 }
4326 }
4327
4328 for (i = 0 ; i <= lasti; i++) {
4329 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4330 continue;
4331 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4332 alu.op = ALU_OP1_MOV;
4333 alu.src[0].sel = t1;
4334 alu.src[0].chan = i;
4335 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4336 alu.dst.write = 1;
4337 if (i == lasti)
4338 alu.last = 1;
4339 r = r600_bytecode_add_alu(ctx->bc, &alu);
4340 if (r)
4341 return r;
4342 }
4343
4344 return 0;
4345 }
4346
4347
4348 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
4349 {
4350 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4351 int i, j, k, r;
4352 struct r600_bytecode_alu alu;
4353 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4354 int t1 = ctx->temp_reg;
4355
4356 /* t1 would get overwritten below if we actually tried to
4357 * multiply two pairs of doubles at a time. */
4358 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4359 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4360
4361 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4362
4363 for (i = 0; i < 4; i++) {
4364 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4365 alu.op = ctx->inst_info->op;
4366 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4367 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));
4368 }
4369 alu.dst.sel = t1;
4370 alu.dst.chan = i;
4371 alu.dst.write = 1;
4372 if (i == 3)
4373 alu.last = 1;
4374 r = r600_bytecode_add_alu(ctx->bc, &alu);
4375 if (r)
4376 return r;
4377 }
4378
4379 for (i = 0; i <= lasti; i++) {
4380 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4381 continue;
4382 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4383 alu.op = ALU_OP1_MOV;
4384 alu.src[0].sel = t1;
4385 alu.src[0].chan = i;
4386 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4387 alu.dst.write = 1;
4388 if (i == lasti)
4389 alu.last = 1;
4390 r = r600_bytecode_add_alu(ctx->bc, &alu);
4391 if (r)
4392 return r;
4393 }
4394
4395 return 0;
4396 }
4397
4398 /*
4399 * Emit RECIP_64 + MUL_64 to implement division.
4400 */
4401 static int cayman_ddiv_instr(struct r600_shader_ctx *ctx)
4402 {
4403 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4404 int r;
4405 struct r600_bytecode_alu alu;
4406 int t1 = ctx->temp_reg;
4407 int k;
4408
4409 /* Only support one double at a time. This is the same constraint as
4410 * in DMUL lowering. */
4411 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4412 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4413
4414 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4415
4416 r = cayman_emit_unary_double_raw(ctx->bc, ALU_OP2_RECIP_64, t1, &ctx->src[1], false);
4417 if (r)
4418 return r;
4419
4420 for (int i = 0; i < 4; i++) {
4421 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4422 alu.op = ALU_OP2_MUL_64;
4423
4424 r600_bytecode_src(&alu.src[0], &ctx->src[0], k * 2 + ((i == 3) ? 0 : 1));
4425
4426 alu.src[1].sel = t1;
4427 alu.src[1].chan = (i == 3) ? 0 : 1;
4428
4429 alu.dst.sel = t1;
4430 alu.dst.chan = i;
4431 alu.dst.write = 1;
4432 if (i == 3)
4433 alu.last = 1;
4434 r = r600_bytecode_add_alu(ctx->bc, &alu);
4435 if (r)
4436 return r;
4437 }
4438
4439 for (int i = 0; i < 2; i++) {
4440 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4441 alu.op = ALU_OP1_MOV;
4442 alu.src[0].sel = t1;
4443 alu.src[0].chan = i;
4444 tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
4445 alu.dst.write = 1;
4446 if (i == 1)
4447 alu.last = 1;
4448 r = r600_bytecode_add_alu(ctx->bc, &alu);
4449 if (r)
4450 return r;
4451 }
4452 return 0;
4453 }
4454
4455 /*
4456 * r600 - trunc to -PI..PI range
4457 * r700 - normalize by dividing by 2PI
4458 * see fdo bug 27901
4459 */
4460 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
4461 {
4462 int r;
4463 struct r600_bytecode_alu alu;
4464
4465 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4466 alu.op = ALU_OP3_MULADD;
4467 alu.is_op3 = 1;
4468
4469 alu.dst.chan = 0;
4470 alu.dst.sel = ctx->temp_reg;
4471 alu.dst.write = 1;
4472
4473 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4474
4475 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4476 alu.src[1].chan = 0;
4477 alu.src[1].value = u_bitcast_f2u(0.5f * M_1_PI);
4478 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4479 alu.src[2].chan = 0;
4480 alu.last = 1;
4481 r = r600_bytecode_add_alu(ctx->bc, &alu);
4482 if (r)
4483 return r;
4484
4485 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4486 alu.op = ALU_OP1_FRACT;
4487
4488 alu.dst.chan = 0;
4489 alu.dst.sel = ctx->temp_reg;
4490 alu.dst.write = 1;
4491
4492 alu.src[0].sel = ctx->temp_reg;
4493 alu.src[0].chan = 0;
4494 alu.last = 1;
4495 r = r600_bytecode_add_alu(ctx->bc, &alu);
4496 if (r)
4497 return r;
4498
4499 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4500 alu.op = ALU_OP3_MULADD;
4501 alu.is_op3 = 1;
4502
4503 alu.dst.chan = 0;
4504 alu.dst.sel = ctx->temp_reg;
4505 alu.dst.write = 1;
4506
4507 alu.src[0].sel = ctx->temp_reg;
4508 alu.src[0].chan = 0;
4509
4510 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4511 alu.src[1].chan = 0;
4512 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4513 alu.src[2].chan = 0;
4514
4515 if (ctx->bc->chip_class == R600) {
4516 alu.src[1].value = u_bitcast_f2u(2.0f * M_PI);
4517 alu.src[2].value = u_bitcast_f2u(-M_PI);
4518 } else {
4519 alu.src[1].sel = V_SQ_ALU_SRC_1;
4520 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4521 alu.src[2].neg = 1;
4522 }
4523
4524 alu.last = 1;
4525 r = r600_bytecode_add_alu(ctx->bc, &alu);
4526 if (r)
4527 return r;
4528 return 0;
4529 }
4530
4531 static int cayman_trig(struct r600_shader_ctx *ctx)
4532 {
4533 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4534 struct r600_bytecode_alu alu;
4535 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4536 int i, r;
4537
4538 r = tgsi_setup_trig(ctx);
4539 if (r)
4540 return r;
4541
4542
4543 for (i = 0; i < last_slot; i++) {
4544 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4545 alu.op = ctx->inst_info->op;
4546 alu.dst.chan = i;
4547
4548 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4549 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4550
4551 alu.src[0].sel = ctx->temp_reg;
4552 alu.src[0].chan = 0;
4553 if (i == last_slot - 1)
4554 alu.last = 1;
4555 r = r600_bytecode_add_alu(ctx->bc, &alu);
4556 if (r)
4557 return r;
4558 }
4559 return 0;
4560 }
4561
4562 static int tgsi_trig(struct r600_shader_ctx *ctx)
4563 {
4564 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4565 struct r600_bytecode_alu alu;
4566 int i, r;
4567 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4568
4569 r = tgsi_setup_trig(ctx);
4570 if (r)
4571 return r;
4572
4573 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4574 alu.op = ctx->inst_info->op;
4575 alu.dst.chan = 0;
4576 alu.dst.sel = ctx->temp_reg;
4577 alu.dst.write = 1;
4578
4579 alu.src[0].sel = ctx->temp_reg;
4580 alu.src[0].chan = 0;
4581 alu.last = 1;
4582 r = r600_bytecode_add_alu(ctx->bc, &alu);
4583 if (r)
4584 return r;
4585
4586 /* replicate result */
4587 for (i = 0; i < lasti + 1; i++) {
4588 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4589 continue;
4590
4591 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4592 alu.op = ALU_OP1_MOV;
4593
4594 alu.src[0].sel = ctx->temp_reg;
4595 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4596 if (i == lasti)
4597 alu.last = 1;
4598 r = r600_bytecode_add_alu(ctx->bc, &alu);
4599 if (r)
4600 return r;
4601 }
4602 return 0;
4603 }
4604
4605 static int tgsi_scs(struct r600_shader_ctx *ctx)
4606 {
4607 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4608 struct r600_bytecode_alu alu;
4609 int i, r;
4610
4611 /* We'll only need the trig stuff if we are going to write to the
4612 * X or Y components of the destination vector.
4613 */
4614 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
4615 r = tgsi_setup_trig(ctx);
4616 if (r)
4617 return r;
4618 }
4619
4620 /* dst.x = COS */
4621 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
4622 if (ctx->bc->chip_class == CAYMAN) {
4623 for (i = 0 ; i < 3; i++) {
4624 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4625 alu.op = ALU_OP1_COS;
4626 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4627
4628 if (i == 0)
4629 alu.dst.write = 1;
4630 else
4631 alu.dst.write = 0;
4632 alu.src[0].sel = ctx->temp_reg;
4633 alu.src[0].chan = 0;
4634 if (i == 2)
4635 alu.last = 1;
4636 r = r600_bytecode_add_alu(ctx->bc, &alu);
4637 if (r)
4638 return r;
4639 }
4640 } else {
4641 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4642 alu.op = ALU_OP1_COS;
4643 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4644
4645 alu.src[0].sel = ctx->temp_reg;
4646 alu.src[0].chan = 0;
4647 alu.last = 1;
4648 r = r600_bytecode_add_alu(ctx->bc, &alu);
4649 if (r)
4650 return r;
4651 }
4652 }
4653
4654 /* dst.y = SIN */
4655 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
4656 if (ctx->bc->chip_class == CAYMAN) {
4657 for (i = 0 ; i < 3; i++) {
4658 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4659 alu.op = ALU_OP1_SIN;
4660 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4661 if (i == 1)
4662 alu.dst.write = 1;
4663 else
4664 alu.dst.write = 0;
4665 alu.src[0].sel = ctx->temp_reg;
4666 alu.src[0].chan = 0;
4667 if (i == 2)
4668 alu.last = 1;
4669 r = r600_bytecode_add_alu(ctx->bc, &alu);
4670 if (r)
4671 return r;
4672 }
4673 } else {
4674 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4675 alu.op = ALU_OP1_SIN;
4676 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4677
4678 alu.src[0].sel = ctx->temp_reg;
4679 alu.src[0].chan = 0;
4680 alu.last = 1;
4681 r = r600_bytecode_add_alu(ctx->bc, &alu);
4682 if (r)
4683 return r;
4684 }
4685 }
4686
4687 /* dst.z = 0.0; */
4688 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
4689 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4690
4691 alu.op = ALU_OP1_MOV;
4692
4693 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4694
4695 alu.src[0].sel = V_SQ_ALU_SRC_0;
4696 alu.src[0].chan = 0;
4697
4698 alu.last = 1;
4699
4700 r = r600_bytecode_add_alu(ctx->bc, &alu);
4701 if (r)
4702 return r;
4703 }
4704
4705 /* dst.w = 1.0; */
4706 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
4707 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4708
4709 alu.op = ALU_OP1_MOV;
4710
4711 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4712
4713 alu.src[0].sel = V_SQ_ALU_SRC_1;
4714 alu.src[0].chan = 0;
4715
4716 alu.last = 1;
4717
4718 r = r600_bytecode_add_alu(ctx->bc, &alu);
4719 if (r)
4720 return r;
4721 }
4722
4723 return 0;
4724 }
4725
4726 static int tgsi_kill(struct r600_shader_ctx *ctx)
4727 {
4728 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4729 struct r600_bytecode_alu alu;
4730 int i, r;
4731
4732 for (i = 0; i < 4; i++) {
4733 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4734 alu.op = ctx->inst_info->op;
4735
4736 alu.dst.chan = i;
4737
4738 alu.src[0].sel = V_SQ_ALU_SRC_0;
4739
4740 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
4741 alu.src[1].sel = V_SQ_ALU_SRC_1;
4742 alu.src[1].neg = 1;
4743 } else {
4744 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4745 }
4746 if (i == 3) {
4747 alu.last = 1;
4748 }
4749 r = r600_bytecode_add_alu(ctx->bc, &alu);
4750 if (r)
4751 return r;
4752 }
4753
4754 /* kill must be last in ALU */
4755 ctx->bc->force_add_cf = 1;
4756 ctx->shader->uses_kill = TRUE;
4757 return 0;
4758 }
4759
4760 static int tgsi_lit(struct r600_shader_ctx *ctx)
4761 {
4762 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4763 struct r600_bytecode_alu alu;
4764 int r;
4765
4766 /* tmp.x = max(src.y, 0.0) */
4767 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4768 alu.op = ALU_OP2_MAX;
4769 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4770 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4771 alu.src[1].chan = 1;
4772
4773 alu.dst.sel = ctx->temp_reg;
4774 alu.dst.chan = 0;
4775 alu.dst.write = 1;
4776
4777 alu.last = 1;
4778 r = r600_bytecode_add_alu(ctx->bc, &alu);
4779 if (r)
4780 return r;
4781
4782 if (inst->Dst[0].Register.WriteMask & (1 << 2))
4783 {
4784 int chan;
4785 int sel;
4786 unsigned i;
4787
4788 if (ctx->bc->chip_class == CAYMAN) {
4789 for (i = 0; i < 3; i++) {
4790 /* tmp.z = log(tmp.x) */
4791 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4792 alu.op = ALU_OP1_LOG_CLAMPED;
4793 alu.src[0].sel = ctx->temp_reg;
4794 alu.src[0].chan = 0;
4795 alu.dst.sel = ctx->temp_reg;
4796 alu.dst.chan = i;
4797 if (i == 2) {
4798 alu.dst.write = 1;
4799 alu.last = 1;
4800 } else
4801 alu.dst.write = 0;
4802
4803 r = r600_bytecode_add_alu(ctx->bc, &alu);
4804 if (r)
4805 return r;
4806 }
4807 } else {
4808 /* tmp.z = log(tmp.x) */
4809 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4810 alu.op = ALU_OP1_LOG_CLAMPED;
4811 alu.src[0].sel = ctx->temp_reg;
4812 alu.src[0].chan = 0;
4813 alu.dst.sel = ctx->temp_reg;
4814 alu.dst.chan = 2;
4815 alu.dst.write = 1;
4816 alu.last = 1;
4817 r = r600_bytecode_add_alu(ctx->bc, &alu);
4818 if (r)
4819 return r;
4820 }
4821
4822 chan = alu.dst.chan;
4823 sel = alu.dst.sel;
4824
4825 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4826 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4827 alu.op = ALU_OP3_MUL_LIT;
4828 alu.src[0].sel = sel;
4829 alu.src[0].chan = chan;
4830 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
4831 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
4832 alu.dst.sel = ctx->temp_reg;
4833 alu.dst.chan = 0;
4834 alu.dst.write = 1;
4835 alu.is_op3 = 1;
4836 alu.last = 1;
4837 r = r600_bytecode_add_alu(ctx->bc, &alu);
4838 if (r)
4839 return r;
4840
4841 if (ctx->bc->chip_class == CAYMAN) {
4842 for (i = 0; i < 3; i++) {
4843 /* dst.z = exp(tmp.x) */
4844 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4845 alu.op = ALU_OP1_EXP_IEEE;
4846 alu.src[0].sel = ctx->temp_reg;
4847 alu.src[0].chan = 0;
4848 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4849 if (i == 2) {
4850 alu.dst.write = 1;
4851 alu.last = 1;
4852 } else
4853 alu.dst.write = 0;
4854 r = r600_bytecode_add_alu(ctx->bc, &alu);
4855 if (r)
4856 return r;
4857 }
4858 } else {
4859 /* dst.z = exp(tmp.x) */
4860 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4861 alu.op = ALU_OP1_EXP_IEEE;
4862 alu.src[0].sel = ctx->temp_reg;
4863 alu.src[0].chan = 0;
4864 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4865 alu.last = 1;
4866 r = r600_bytecode_add_alu(ctx->bc, &alu);
4867 if (r)
4868 return r;
4869 }
4870 }
4871
4872 /* dst.x, <- 1.0 */
4873 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4874 alu.op = ALU_OP1_MOV;
4875 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
4876 alu.src[0].chan = 0;
4877 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4878 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
4879 r = r600_bytecode_add_alu(ctx->bc, &alu);
4880 if (r)
4881 return r;
4882
4883 /* dst.y = max(src.x, 0.0) */
4884 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4885 alu.op = ALU_OP2_MAX;
4886 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4887 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4888 alu.src[1].chan = 0;
4889 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4890 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
4891 r = r600_bytecode_add_alu(ctx->bc, &alu);
4892 if (r)
4893 return r;
4894
4895 /* dst.w, <- 1.0 */
4896 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4897 alu.op = ALU_OP1_MOV;
4898 alu.src[0].sel = V_SQ_ALU_SRC_1;
4899 alu.src[0].chan = 0;
4900 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4901 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
4902 alu.last = 1;
4903 r = r600_bytecode_add_alu(ctx->bc, &alu);
4904 if (r)
4905 return r;
4906
4907 return 0;
4908 }
4909
4910 static int tgsi_rsq(struct r600_shader_ctx *ctx)
4911 {
4912 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4913 struct r600_bytecode_alu alu;
4914 int i, r;
4915
4916 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4917
4918 /* XXX:
4919 * For state trackers other than OpenGL, we'll want to use
4920 * _RECIPSQRT_IEEE instead.
4921 */
4922 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
4923
4924 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4925 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4926 r600_bytecode_src_set_abs(&alu.src[i]);
4927 }
4928 alu.dst.sel = ctx->temp_reg;
4929 alu.dst.write = 1;
4930 alu.last = 1;
4931 r = r600_bytecode_add_alu(ctx->bc, &alu);
4932 if (r)
4933 return r;
4934 /* replicate result */
4935 return tgsi_helper_tempx_replicate(ctx);
4936 }
4937
4938 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
4939 {
4940 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4941 struct r600_bytecode_alu alu;
4942 int i, r;
4943
4944 for (i = 0; i < 4; i++) {
4945 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4946 alu.src[0].sel = ctx->temp_reg;
4947 alu.op = ALU_OP1_MOV;
4948 alu.dst.chan = i;
4949 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4950 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4951 if (i == 3)
4952 alu.last = 1;
4953 r = r600_bytecode_add_alu(ctx->bc, &alu);
4954 if (r)
4955 return r;
4956 }
4957 return 0;
4958 }
4959
4960 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
4961 {
4962 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4963 struct r600_bytecode_alu alu;
4964 int i, r;
4965
4966 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4967 alu.op = ctx->inst_info->op;
4968 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4969 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4970 }
4971 alu.dst.sel = ctx->temp_reg;
4972 alu.dst.write = 1;
4973 alu.last = 1;
4974 r = r600_bytecode_add_alu(ctx->bc, &alu);
4975 if (r)
4976 return r;
4977 /* replicate result */
4978 return tgsi_helper_tempx_replicate(ctx);
4979 }
4980
4981 static int cayman_pow(struct r600_shader_ctx *ctx)
4982 {
4983 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4984 int i, r;
4985 struct r600_bytecode_alu alu;
4986 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4987
4988 for (i = 0; i < 3; i++) {
4989 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4990 alu.op = ALU_OP1_LOG_IEEE;
4991 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4992 alu.dst.sel = ctx->temp_reg;
4993 alu.dst.chan = i;
4994 alu.dst.write = 1;
4995 if (i == 2)
4996 alu.last = 1;
4997 r = r600_bytecode_add_alu(ctx->bc, &alu);
4998 if (r)
4999 return r;
5000 }
5001
5002 /* b * LOG2(a) */
5003 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5004 alu.op = ALU_OP2_MUL;
5005 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5006 alu.src[1].sel = ctx->temp_reg;
5007 alu.dst.sel = ctx->temp_reg;
5008 alu.dst.write = 1;
5009 alu.last = 1;
5010 r = r600_bytecode_add_alu(ctx->bc, &alu);
5011 if (r)
5012 return r;
5013
5014 for (i = 0; i < last_slot; i++) {
5015 /* POW(a,b) = EXP2(b * LOG2(a))*/
5016 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5017 alu.op = ALU_OP1_EXP_IEEE;
5018 alu.src[0].sel = ctx->temp_reg;
5019
5020 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5021 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5022 if (i == last_slot - 1)
5023 alu.last = 1;
5024 r = r600_bytecode_add_alu(ctx->bc, &alu);
5025 if (r)
5026 return r;
5027 }
5028 return 0;
5029 }
5030
5031 static int tgsi_pow(struct r600_shader_ctx *ctx)
5032 {
5033 struct r600_bytecode_alu alu;
5034 int r;
5035
5036 /* LOG2(a) */
5037 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5038 alu.op = ALU_OP1_LOG_IEEE;
5039 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5040 alu.dst.sel = ctx->temp_reg;
5041 alu.dst.write = 1;
5042 alu.last = 1;
5043 r = r600_bytecode_add_alu(ctx->bc, &alu);
5044 if (r)
5045 return r;
5046 /* b * LOG2(a) */
5047 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5048 alu.op = ALU_OP2_MUL;
5049 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5050 alu.src[1].sel = ctx->temp_reg;
5051 alu.dst.sel = ctx->temp_reg;
5052 alu.dst.write = 1;
5053 alu.last = 1;
5054 r = r600_bytecode_add_alu(ctx->bc, &alu);
5055 if (r)
5056 return r;
5057 /* POW(a,b) = EXP2(b * LOG2(a))*/
5058 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5059 alu.op = ALU_OP1_EXP_IEEE;
5060 alu.src[0].sel = ctx->temp_reg;
5061 alu.dst.sel = ctx->temp_reg;
5062 alu.dst.write = 1;
5063 alu.last = 1;
5064 r = r600_bytecode_add_alu(ctx->bc, &alu);
5065 if (r)
5066 return r;
5067 return tgsi_helper_tempx_replicate(ctx);
5068 }
5069
5070 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5071 {
5072 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5073 struct r600_bytecode_alu alu;
5074 int i, r, j;
5075 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5076 int tmp0 = ctx->temp_reg;
5077 int tmp1 = r600_get_temp(ctx);
5078 int tmp2 = r600_get_temp(ctx);
5079 int tmp3 = r600_get_temp(ctx);
5080 /* Unsigned path:
5081 *
5082 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5083 *
5084 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5085 * 2. tmp0.z = lo (tmp0.x * src2)
5086 * 3. tmp0.w = -tmp0.z
5087 * 4. tmp0.y = hi (tmp0.x * src2)
5088 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5089 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5090 * 7. tmp1.x = tmp0.x - tmp0.w
5091 * 8. tmp1.y = tmp0.x + tmp0.w
5092 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5093 * 10. tmp0.z = hi(tmp0.x * src1) = q
5094 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5095 *
5096 * 12. tmp0.w = src1 - tmp0.y = r
5097 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5098 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5099 *
5100 * if DIV
5101 *
5102 * 15. tmp1.z = tmp0.z + 1 = q + 1
5103 * 16. tmp1.w = tmp0.z - 1 = q - 1
5104 *
5105 * else MOD
5106 *
5107 * 15. tmp1.z = tmp0.w - src2 = r - src2
5108 * 16. tmp1.w = tmp0.w + src2 = r + src2
5109 *
5110 * endif
5111 *
5112 * 17. tmp1.x = tmp1.x & tmp1.y
5113 *
5114 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5115 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5116 *
5117 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5118 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5119 *
5120 * Signed path:
5121 *
5122 * Same as unsigned, using abs values of the operands,
5123 * and fixing the sign of the result in the end.
5124 */
5125
5126 for (i = 0; i < 4; i++) {
5127 if (!(write_mask & (1<<i)))
5128 continue;
5129
5130 if (signed_op) {
5131
5132 /* tmp2.x = -src0 */
5133 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5134 alu.op = ALU_OP2_SUB_INT;
5135
5136 alu.dst.sel = tmp2;
5137 alu.dst.chan = 0;
5138 alu.dst.write = 1;
5139
5140 alu.src[0].sel = V_SQ_ALU_SRC_0;
5141
5142 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5143
5144 alu.last = 1;
5145 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5146 return r;
5147
5148 /* tmp2.y = -src1 */
5149 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5150 alu.op = ALU_OP2_SUB_INT;
5151
5152 alu.dst.sel = tmp2;
5153 alu.dst.chan = 1;
5154 alu.dst.write = 1;
5155
5156 alu.src[0].sel = V_SQ_ALU_SRC_0;
5157
5158 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5159
5160 alu.last = 1;
5161 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5162 return r;
5163
5164 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5165 /* it will be a sign of the quotient */
5166 if (!mod) {
5167
5168 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5169 alu.op = ALU_OP2_XOR_INT;
5170
5171 alu.dst.sel = tmp2;
5172 alu.dst.chan = 2;
5173 alu.dst.write = 1;
5174
5175 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5176 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5177
5178 alu.last = 1;
5179 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5180 return r;
5181 }
5182
5183 /* tmp2.x = |src0| */
5184 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5185 alu.op = ALU_OP3_CNDGE_INT;
5186 alu.is_op3 = 1;
5187
5188 alu.dst.sel = tmp2;
5189 alu.dst.chan = 0;
5190 alu.dst.write = 1;
5191
5192 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5193 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5194 alu.src[2].sel = tmp2;
5195 alu.src[2].chan = 0;
5196
5197 alu.last = 1;
5198 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5199 return r;
5200
5201 /* tmp2.y = |src1| */
5202 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5203 alu.op = ALU_OP3_CNDGE_INT;
5204 alu.is_op3 = 1;
5205
5206 alu.dst.sel = tmp2;
5207 alu.dst.chan = 1;
5208 alu.dst.write = 1;
5209
5210 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5211 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5212 alu.src[2].sel = tmp2;
5213 alu.src[2].chan = 1;
5214
5215 alu.last = 1;
5216 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5217 return r;
5218
5219 }
5220
5221 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5222 if (ctx->bc->chip_class == CAYMAN) {
5223 /* tmp3.x = u2f(src2) */
5224 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5225 alu.op = ALU_OP1_UINT_TO_FLT;
5226
5227 alu.dst.sel = tmp3;
5228 alu.dst.chan = 0;
5229 alu.dst.write = 1;
5230
5231 if (signed_op) {
5232 alu.src[0].sel = tmp2;
5233 alu.src[0].chan = 1;
5234 } else {
5235 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5236 }
5237
5238 alu.last = 1;
5239 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5240 return r;
5241
5242 /* tmp0.x = recip(tmp3.x) */
5243 for (j = 0 ; j < 3; j++) {
5244 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5245 alu.op = ALU_OP1_RECIP_IEEE;
5246
5247 alu.dst.sel = tmp0;
5248 alu.dst.chan = j;
5249 alu.dst.write = (j == 0);
5250
5251 alu.src[0].sel = tmp3;
5252 alu.src[0].chan = 0;
5253
5254 if (j == 2)
5255 alu.last = 1;
5256 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5257 return r;
5258 }
5259
5260 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5261 alu.op = ALU_OP2_MUL;
5262
5263 alu.src[0].sel = tmp0;
5264 alu.src[0].chan = 0;
5265
5266 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5267 alu.src[1].value = 0x4f800000;
5268
5269 alu.dst.sel = tmp3;
5270 alu.dst.write = 1;
5271 alu.last = 1;
5272 r = r600_bytecode_add_alu(ctx->bc, &alu);
5273 if (r)
5274 return r;
5275
5276 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5277 alu.op = ALU_OP1_FLT_TO_UINT;
5278
5279 alu.dst.sel = tmp0;
5280 alu.dst.chan = 0;
5281 alu.dst.write = 1;
5282
5283 alu.src[0].sel = tmp3;
5284 alu.src[0].chan = 0;
5285
5286 alu.last = 1;
5287 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5288 return r;
5289
5290 } else {
5291 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5292 alu.op = ALU_OP1_RECIP_UINT;
5293
5294 alu.dst.sel = tmp0;
5295 alu.dst.chan = 0;
5296 alu.dst.write = 1;
5297
5298 if (signed_op) {
5299 alu.src[0].sel = tmp2;
5300 alu.src[0].chan = 1;
5301 } else {
5302 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5303 }
5304
5305 alu.last = 1;
5306 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5307 return r;
5308 }
5309
5310 /* 2. tmp0.z = lo (tmp0.x * src2) */
5311 if (ctx->bc->chip_class == CAYMAN) {
5312 for (j = 0 ; j < 4; j++) {
5313 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5314 alu.op = ALU_OP2_MULLO_UINT;
5315
5316 alu.dst.sel = tmp0;
5317 alu.dst.chan = j;
5318 alu.dst.write = (j == 2);
5319
5320 alu.src[0].sel = tmp0;
5321 alu.src[0].chan = 0;
5322 if (signed_op) {
5323 alu.src[1].sel = tmp2;
5324 alu.src[1].chan = 1;
5325 } else {
5326 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5327 }
5328
5329 alu.last = (j == 3);
5330 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5331 return r;
5332 }
5333 } else {
5334 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5335 alu.op = ALU_OP2_MULLO_UINT;
5336
5337 alu.dst.sel = tmp0;
5338 alu.dst.chan = 2;
5339 alu.dst.write = 1;
5340
5341 alu.src[0].sel = tmp0;
5342 alu.src[0].chan = 0;
5343 if (signed_op) {
5344 alu.src[1].sel = tmp2;
5345 alu.src[1].chan = 1;
5346 } else {
5347 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5348 }
5349
5350 alu.last = 1;
5351 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5352 return r;
5353 }
5354
5355 /* 3. tmp0.w = -tmp0.z */
5356 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5357 alu.op = ALU_OP2_SUB_INT;
5358
5359 alu.dst.sel = tmp0;
5360 alu.dst.chan = 3;
5361 alu.dst.write = 1;
5362
5363 alu.src[0].sel = V_SQ_ALU_SRC_0;
5364 alu.src[1].sel = tmp0;
5365 alu.src[1].chan = 2;
5366
5367 alu.last = 1;
5368 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5369 return r;
5370
5371 /* 4. tmp0.y = hi (tmp0.x * src2) */
5372 if (ctx->bc->chip_class == CAYMAN) {
5373 for (j = 0 ; j < 4; j++) {
5374 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5375 alu.op = ALU_OP2_MULHI_UINT;
5376
5377 alu.dst.sel = tmp0;
5378 alu.dst.chan = j;
5379 alu.dst.write = (j == 1);
5380
5381 alu.src[0].sel = tmp0;
5382 alu.src[0].chan = 0;
5383
5384 if (signed_op) {
5385 alu.src[1].sel = tmp2;
5386 alu.src[1].chan = 1;
5387 } else {
5388 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5389 }
5390 alu.last = (j == 3);
5391 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5392 return r;
5393 }
5394 } else {
5395 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5396 alu.op = ALU_OP2_MULHI_UINT;
5397
5398 alu.dst.sel = tmp0;
5399 alu.dst.chan = 1;
5400 alu.dst.write = 1;
5401
5402 alu.src[0].sel = tmp0;
5403 alu.src[0].chan = 0;
5404
5405 if (signed_op) {
5406 alu.src[1].sel = tmp2;
5407 alu.src[1].chan = 1;
5408 } else {
5409 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5410 }
5411
5412 alu.last = 1;
5413 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5414 return r;
5415 }
5416
5417 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5418 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5419 alu.op = ALU_OP3_CNDE_INT;
5420 alu.is_op3 = 1;
5421
5422 alu.dst.sel = tmp0;
5423 alu.dst.chan = 2;
5424 alu.dst.write = 1;
5425
5426 alu.src[0].sel = tmp0;
5427 alu.src[0].chan = 1;
5428 alu.src[1].sel = tmp0;
5429 alu.src[1].chan = 3;
5430 alu.src[2].sel = tmp0;
5431 alu.src[2].chan = 2;
5432
5433 alu.last = 1;
5434 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5435 return r;
5436
5437 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5438 if (ctx->bc->chip_class == CAYMAN) {
5439 for (j = 0 ; j < 4; j++) {
5440 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5441 alu.op = ALU_OP2_MULHI_UINT;
5442
5443 alu.dst.sel = tmp0;
5444 alu.dst.chan = j;
5445 alu.dst.write = (j == 3);
5446
5447 alu.src[0].sel = tmp0;
5448 alu.src[0].chan = 2;
5449
5450 alu.src[1].sel = tmp0;
5451 alu.src[1].chan = 0;
5452
5453 alu.last = (j == 3);
5454 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5455 return r;
5456 }
5457 } else {
5458 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5459 alu.op = ALU_OP2_MULHI_UINT;
5460
5461 alu.dst.sel = tmp0;
5462 alu.dst.chan = 3;
5463 alu.dst.write = 1;
5464
5465 alu.src[0].sel = tmp0;
5466 alu.src[0].chan = 2;
5467
5468 alu.src[1].sel = tmp0;
5469 alu.src[1].chan = 0;
5470
5471 alu.last = 1;
5472 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5473 return r;
5474 }
5475
5476 /* 7. tmp1.x = tmp0.x - tmp0.w */
5477 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5478 alu.op = ALU_OP2_SUB_INT;
5479
5480 alu.dst.sel = tmp1;
5481 alu.dst.chan = 0;
5482 alu.dst.write = 1;
5483
5484 alu.src[0].sel = tmp0;
5485 alu.src[0].chan = 0;
5486 alu.src[1].sel = tmp0;
5487 alu.src[1].chan = 3;
5488
5489 alu.last = 1;
5490 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5491 return r;
5492
5493 /* 8. tmp1.y = tmp0.x + tmp0.w */
5494 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5495 alu.op = ALU_OP2_ADD_INT;
5496
5497 alu.dst.sel = tmp1;
5498 alu.dst.chan = 1;
5499 alu.dst.write = 1;
5500
5501 alu.src[0].sel = tmp0;
5502 alu.src[0].chan = 0;
5503 alu.src[1].sel = tmp0;
5504 alu.src[1].chan = 3;
5505
5506 alu.last = 1;
5507 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5508 return r;
5509
5510 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5511 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5512 alu.op = ALU_OP3_CNDE_INT;
5513 alu.is_op3 = 1;
5514
5515 alu.dst.sel = tmp0;
5516 alu.dst.chan = 0;
5517 alu.dst.write = 1;
5518
5519 alu.src[0].sel = tmp0;
5520 alu.src[0].chan = 1;
5521 alu.src[1].sel = tmp1;
5522 alu.src[1].chan = 1;
5523 alu.src[2].sel = tmp1;
5524 alu.src[2].chan = 0;
5525
5526 alu.last = 1;
5527 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5528 return r;
5529
5530 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5531 if (ctx->bc->chip_class == CAYMAN) {
5532 for (j = 0 ; j < 4; j++) {
5533 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5534 alu.op = ALU_OP2_MULHI_UINT;
5535
5536 alu.dst.sel = tmp0;
5537 alu.dst.chan = j;
5538 alu.dst.write = (j == 2);
5539
5540 alu.src[0].sel = tmp0;
5541 alu.src[0].chan = 0;
5542
5543 if (signed_op) {
5544 alu.src[1].sel = tmp2;
5545 alu.src[1].chan = 0;
5546 } else {
5547 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5548 }
5549
5550 alu.last = (j == 3);
5551 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5552 return r;
5553 }
5554 } else {
5555 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5556 alu.op = ALU_OP2_MULHI_UINT;
5557
5558 alu.dst.sel = tmp0;
5559 alu.dst.chan = 2;
5560 alu.dst.write = 1;
5561
5562 alu.src[0].sel = tmp0;
5563 alu.src[0].chan = 0;
5564
5565 if (signed_op) {
5566 alu.src[1].sel = tmp2;
5567 alu.src[1].chan = 0;
5568 } else {
5569 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5570 }
5571
5572 alu.last = 1;
5573 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5574 return r;
5575 }
5576
5577 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5578 if (ctx->bc->chip_class == CAYMAN) {
5579 for (j = 0 ; j < 4; j++) {
5580 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5581 alu.op = ALU_OP2_MULLO_UINT;
5582
5583 alu.dst.sel = tmp0;
5584 alu.dst.chan = j;
5585 alu.dst.write = (j == 1);
5586
5587 if (signed_op) {
5588 alu.src[0].sel = tmp2;
5589 alu.src[0].chan = 1;
5590 } else {
5591 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5592 }
5593
5594 alu.src[1].sel = tmp0;
5595 alu.src[1].chan = 2;
5596
5597 alu.last = (j == 3);
5598 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5599 return r;
5600 }
5601 } else {
5602 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5603 alu.op = ALU_OP2_MULLO_UINT;
5604
5605 alu.dst.sel = tmp0;
5606 alu.dst.chan = 1;
5607 alu.dst.write = 1;
5608
5609 if (signed_op) {
5610 alu.src[0].sel = tmp2;
5611 alu.src[0].chan = 1;
5612 } else {
5613 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5614 }
5615
5616 alu.src[1].sel = tmp0;
5617 alu.src[1].chan = 2;
5618
5619 alu.last = 1;
5620 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5621 return r;
5622 }
5623
5624 /* 12. tmp0.w = src1 - tmp0.y = r */
5625 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5626 alu.op = ALU_OP2_SUB_INT;
5627
5628 alu.dst.sel = tmp0;
5629 alu.dst.chan = 3;
5630 alu.dst.write = 1;
5631
5632 if (signed_op) {
5633 alu.src[0].sel = tmp2;
5634 alu.src[0].chan = 0;
5635 } else {
5636 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5637 }
5638
5639 alu.src[1].sel = tmp0;
5640 alu.src[1].chan = 1;
5641
5642 alu.last = 1;
5643 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5644 return r;
5645
5646 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5647 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5648 alu.op = ALU_OP2_SETGE_UINT;
5649
5650 alu.dst.sel = tmp1;
5651 alu.dst.chan = 0;
5652 alu.dst.write = 1;
5653
5654 alu.src[0].sel = tmp0;
5655 alu.src[0].chan = 3;
5656 if (signed_op) {
5657 alu.src[1].sel = tmp2;
5658 alu.src[1].chan = 1;
5659 } else {
5660 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5661 }
5662
5663 alu.last = 1;
5664 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5665 return r;
5666
5667 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5668 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5669 alu.op = ALU_OP2_SETGE_UINT;
5670
5671 alu.dst.sel = tmp1;
5672 alu.dst.chan = 1;
5673 alu.dst.write = 1;
5674
5675 if (signed_op) {
5676 alu.src[0].sel = tmp2;
5677 alu.src[0].chan = 0;
5678 } else {
5679 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5680 }
5681
5682 alu.src[1].sel = tmp0;
5683 alu.src[1].chan = 1;
5684
5685 alu.last = 1;
5686 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5687 return r;
5688
5689 if (mod) { /* UMOD */
5690
5691 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5692 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5693 alu.op = ALU_OP2_SUB_INT;
5694
5695 alu.dst.sel = tmp1;
5696 alu.dst.chan = 2;
5697 alu.dst.write = 1;
5698
5699 alu.src[0].sel = tmp0;
5700 alu.src[0].chan = 3;
5701
5702 if (signed_op) {
5703 alu.src[1].sel = tmp2;
5704 alu.src[1].chan = 1;
5705 } else {
5706 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5707 }
5708
5709 alu.last = 1;
5710 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5711 return r;
5712
5713 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5714 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5715 alu.op = ALU_OP2_ADD_INT;
5716
5717 alu.dst.sel = tmp1;
5718 alu.dst.chan = 3;
5719 alu.dst.write = 1;
5720
5721 alu.src[0].sel = tmp0;
5722 alu.src[0].chan = 3;
5723 if (signed_op) {
5724 alu.src[1].sel = tmp2;
5725 alu.src[1].chan = 1;
5726 } else {
5727 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5728 }
5729
5730 alu.last = 1;
5731 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5732 return r;
5733
5734 } else { /* UDIV */
5735
5736 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5737 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5738 alu.op = ALU_OP2_ADD_INT;
5739
5740 alu.dst.sel = tmp1;
5741 alu.dst.chan = 2;
5742 alu.dst.write = 1;
5743
5744 alu.src[0].sel = tmp0;
5745 alu.src[0].chan = 2;
5746 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5747
5748 alu.last = 1;
5749 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5750 return r;
5751
5752 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5753 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5754 alu.op = ALU_OP2_ADD_INT;
5755
5756 alu.dst.sel = tmp1;
5757 alu.dst.chan = 3;
5758 alu.dst.write = 1;
5759
5760 alu.src[0].sel = tmp0;
5761 alu.src[0].chan = 2;
5762 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
5763
5764 alu.last = 1;
5765 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5766 return r;
5767
5768 }
5769
5770 /* 17. tmp1.x = tmp1.x & tmp1.y */
5771 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5772 alu.op = ALU_OP2_AND_INT;
5773
5774 alu.dst.sel = tmp1;
5775 alu.dst.chan = 0;
5776 alu.dst.write = 1;
5777
5778 alu.src[0].sel = tmp1;
5779 alu.src[0].chan = 0;
5780 alu.src[1].sel = tmp1;
5781 alu.src[1].chan = 1;
5782
5783 alu.last = 1;
5784 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5785 return r;
5786
5787 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5788 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5789 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5790 alu.op = ALU_OP3_CNDE_INT;
5791 alu.is_op3 = 1;
5792
5793 alu.dst.sel = tmp0;
5794 alu.dst.chan = 2;
5795 alu.dst.write = 1;
5796
5797 alu.src[0].sel = tmp1;
5798 alu.src[0].chan = 0;
5799 alu.src[1].sel = tmp0;
5800 alu.src[1].chan = mod ? 3 : 2;
5801 alu.src[2].sel = tmp1;
5802 alu.src[2].chan = 2;
5803
5804 alu.last = 1;
5805 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5806 return r;
5807
5808 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5809 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5810 alu.op = ALU_OP3_CNDE_INT;
5811 alu.is_op3 = 1;
5812
5813 if (signed_op) {
5814 alu.dst.sel = tmp0;
5815 alu.dst.chan = 2;
5816 alu.dst.write = 1;
5817 } else {
5818 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5819 }
5820
5821 alu.src[0].sel = tmp1;
5822 alu.src[0].chan = 1;
5823 alu.src[1].sel = tmp1;
5824 alu.src[1].chan = 3;
5825 alu.src[2].sel = tmp0;
5826 alu.src[2].chan = 2;
5827
5828 alu.last = 1;
5829 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5830 return r;
5831
5832 if (signed_op) {
5833
5834 /* fix the sign of the result */
5835
5836 if (mod) {
5837
5838 /* tmp0.x = -tmp0.z */
5839 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5840 alu.op = ALU_OP2_SUB_INT;
5841
5842 alu.dst.sel = tmp0;
5843 alu.dst.chan = 0;
5844 alu.dst.write = 1;
5845
5846 alu.src[0].sel = V_SQ_ALU_SRC_0;
5847 alu.src[1].sel = tmp0;
5848 alu.src[1].chan = 2;
5849
5850 alu.last = 1;
5851 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5852 return r;
5853
5854 /* sign of the remainder is the same as the sign of src0 */
5855 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5856 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5857 alu.op = ALU_OP3_CNDGE_INT;
5858 alu.is_op3 = 1;
5859
5860 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5861
5862 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5863 alu.src[1].sel = tmp0;
5864 alu.src[1].chan = 2;
5865 alu.src[2].sel = tmp0;
5866 alu.src[2].chan = 0;
5867
5868 alu.last = 1;
5869 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5870 return r;
5871
5872 } else {
5873
5874 /* tmp0.x = -tmp0.z */
5875 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5876 alu.op = ALU_OP2_SUB_INT;
5877
5878 alu.dst.sel = tmp0;
5879 alu.dst.chan = 0;
5880 alu.dst.write = 1;
5881
5882 alu.src[0].sel = V_SQ_ALU_SRC_0;
5883 alu.src[1].sel = tmp0;
5884 alu.src[1].chan = 2;
5885
5886 alu.last = 1;
5887 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5888 return r;
5889
5890 /* fix the quotient sign (same as the sign of src0*src1) */
5891 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5892 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5893 alu.op = ALU_OP3_CNDGE_INT;
5894 alu.is_op3 = 1;
5895
5896 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5897
5898 alu.src[0].sel = tmp2;
5899 alu.src[0].chan = 2;
5900 alu.src[1].sel = tmp0;
5901 alu.src[1].chan = 2;
5902 alu.src[2].sel = tmp0;
5903 alu.src[2].chan = 0;
5904
5905 alu.last = 1;
5906 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5907 return r;
5908 }
5909 }
5910 }
5911 return 0;
5912 }
5913
5914 static int tgsi_udiv(struct r600_shader_ctx *ctx)
5915 {
5916 return tgsi_divmod(ctx, 0, 0);
5917 }
5918
5919 static int tgsi_umod(struct r600_shader_ctx *ctx)
5920 {
5921 return tgsi_divmod(ctx, 1, 0);
5922 }
5923
5924 static int tgsi_idiv(struct r600_shader_ctx *ctx)
5925 {
5926 return tgsi_divmod(ctx, 0, 1);
5927 }
5928
5929 static int tgsi_imod(struct r600_shader_ctx *ctx)
5930 {
5931 return tgsi_divmod(ctx, 1, 1);
5932 }
5933
5934
5935 static int tgsi_f2i(struct r600_shader_ctx *ctx)
5936 {
5937 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5938 struct r600_bytecode_alu alu;
5939 int i, r;
5940 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5941 int last_inst = tgsi_last_instruction(write_mask);
5942
5943 for (i = 0; i < 4; i++) {
5944 if (!(write_mask & (1<<i)))
5945 continue;
5946
5947 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5948 alu.op = ALU_OP1_TRUNC;
5949
5950 alu.dst.sel = ctx->temp_reg;
5951 alu.dst.chan = i;
5952 alu.dst.write = 1;
5953
5954 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5955 if (i == last_inst)
5956 alu.last = 1;
5957 r = r600_bytecode_add_alu(ctx->bc, &alu);
5958 if (r)
5959 return r;
5960 }
5961
5962 for (i = 0; i < 4; i++) {
5963 if (!(write_mask & (1<<i)))
5964 continue;
5965
5966 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5967 alu.op = ctx->inst_info->op;
5968
5969 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5970
5971 alu.src[0].sel = ctx->temp_reg;
5972 alu.src[0].chan = i;
5973
5974 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
5975 alu.last = 1;
5976 r = r600_bytecode_add_alu(ctx->bc, &alu);
5977 if (r)
5978 return r;
5979 }
5980
5981 return 0;
5982 }
5983
5984 static int tgsi_iabs(struct r600_shader_ctx *ctx)
5985 {
5986 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5987 struct r600_bytecode_alu alu;
5988 int i, r;
5989 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5990 int last_inst = tgsi_last_instruction(write_mask);
5991
5992 /* tmp = -src */
5993 for (i = 0; i < 4; i++) {
5994 if (!(write_mask & (1<<i)))
5995 continue;
5996
5997 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5998 alu.op = ALU_OP2_SUB_INT;
5999
6000 alu.dst.sel = ctx->temp_reg;
6001 alu.dst.chan = i;
6002 alu.dst.write = 1;
6003
6004 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6005 alu.src[0].sel = V_SQ_ALU_SRC_0;
6006
6007 if (i == last_inst)
6008 alu.last = 1;
6009 r = r600_bytecode_add_alu(ctx->bc, &alu);
6010 if (r)
6011 return r;
6012 }
6013
6014 /* dst = (src >= 0 ? src : tmp) */
6015 for (i = 0; i < 4; i++) {
6016 if (!(write_mask & (1<<i)))
6017 continue;
6018
6019 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6020 alu.op = ALU_OP3_CNDGE_INT;
6021 alu.is_op3 = 1;
6022 alu.dst.write = 1;
6023
6024 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6025
6026 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6027 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6028 alu.src[2].sel = ctx->temp_reg;
6029 alu.src[2].chan = i;
6030
6031 if (i == last_inst)
6032 alu.last = 1;
6033 r = r600_bytecode_add_alu(ctx->bc, &alu);
6034 if (r)
6035 return r;
6036 }
6037 return 0;
6038 }
6039
6040 static int tgsi_issg(struct r600_shader_ctx *ctx)
6041 {
6042 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6043 struct r600_bytecode_alu alu;
6044 int i, r;
6045 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6046 int last_inst = tgsi_last_instruction(write_mask);
6047
6048 /* tmp = (src >= 0 ? src : -1) */
6049 for (i = 0; i < 4; i++) {
6050 if (!(write_mask & (1<<i)))
6051 continue;
6052
6053 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6054 alu.op = ALU_OP3_CNDGE_INT;
6055 alu.is_op3 = 1;
6056
6057 alu.dst.sel = ctx->temp_reg;
6058 alu.dst.chan = i;
6059 alu.dst.write = 1;
6060
6061 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6062 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6063 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6064
6065 if (i == last_inst)
6066 alu.last = 1;
6067 r = r600_bytecode_add_alu(ctx->bc, &alu);
6068 if (r)
6069 return r;
6070 }
6071
6072 /* dst = (tmp > 0 ? 1 : tmp) */
6073 for (i = 0; i < 4; i++) {
6074 if (!(write_mask & (1<<i)))
6075 continue;
6076
6077 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6078 alu.op = ALU_OP3_CNDGT_INT;
6079 alu.is_op3 = 1;
6080 alu.dst.write = 1;
6081
6082 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6083
6084 alu.src[0].sel = ctx->temp_reg;
6085 alu.src[0].chan = i;
6086
6087 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6088
6089 alu.src[2].sel = ctx->temp_reg;
6090 alu.src[2].chan = i;
6091
6092 if (i == last_inst)
6093 alu.last = 1;
6094 r = r600_bytecode_add_alu(ctx->bc, &alu);
6095 if (r)
6096 return r;
6097 }
6098 return 0;
6099 }
6100
6101
6102
6103 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6104 {
6105 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6106 struct r600_bytecode_alu alu;
6107 int i, r;
6108
6109 /* tmp = (src > 0 ? 1 : src) */
6110 for (i = 0; i < 4; i++) {
6111 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6112 alu.op = ALU_OP3_CNDGT;
6113 alu.is_op3 = 1;
6114
6115 alu.dst.sel = ctx->temp_reg;
6116 alu.dst.chan = i;
6117
6118 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6119 alu.src[1].sel = V_SQ_ALU_SRC_1;
6120 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6121
6122 if (i == 3)
6123 alu.last = 1;
6124 r = r600_bytecode_add_alu(ctx->bc, &alu);
6125 if (r)
6126 return r;
6127 }
6128
6129 /* dst = (-tmp > 0 ? -1 : tmp) */
6130 for (i = 0; i < 4; i++) {
6131 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6132 alu.op = ALU_OP3_CNDGT;
6133 alu.is_op3 = 1;
6134 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6135
6136 alu.src[0].sel = ctx->temp_reg;
6137 alu.src[0].chan = i;
6138 alu.src[0].neg = 1;
6139
6140 alu.src[1].sel = V_SQ_ALU_SRC_1;
6141 alu.src[1].neg = 1;
6142
6143 alu.src[2].sel = ctx->temp_reg;
6144 alu.src[2].chan = i;
6145
6146 if (i == 3)
6147 alu.last = 1;
6148 r = r600_bytecode_add_alu(ctx->bc, &alu);
6149 if (r)
6150 return r;
6151 }
6152 return 0;
6153 }
6154
6155 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6156 {
6157 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6158 struct r600_bytecode_alu alu;
6159 int i, r, t1, t2;
6160
6161 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6162 int last_inst = tgsi_last_instruction(write_mask);
6163
6164 t1 = ctx->temp_reg;
6165
6166 for (i = 0; i < 4; i++) {
6167 if (!(write_mask & (1<<i)))
6168 continue;
6169
6170 /* create mask tmp */
6171 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6172 alu.op = ALU_OP2_BFM_INT;
6173 alu.dst.sel = t1;
6174 alu.dst.chan = i;
6175 alu.dst.write = 1;
6176 alu.last = i == last_inst;
6177
6178 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6179 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6180
6181 r = r600_bytecode_add_alu(ctx->bc, &alu);
6182 if (r)
6183 return r;
6184 }
6185
6186 t2 = r600_get_temp(ctx);
6187
6188 for (i = 0; i < 4; i++) {
6189 if (!(write_mask & (1<<i)))
6190 continue;
6191
6192 /* shift insert left */
6193 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6194 alu.op = ALU_OP2_LSHL_INT;
6195 alu.dst.sel = t2;
6196 alu.dst.chan = i;
6197 alu.dst.write = 1;
6198 alu.last = i == last_inst;
6199
6200 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6201 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6202
6203 r = r600_bytecode_add_alu(ctx->bc, &alu);
6204 if (r)
6205 return r;
6206 }
6207
6208 for (i = 0; i < 4; i++) {
6209 if (!(write_mask & (1<<i)))
6210 continue;
6211
6212 /* actual bitfield insert */
6213 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6214 alu.op = ALU_OP3_BFI_INT;
6215 alu.is_op3 = 1;
6216 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6217 alu.dst.chan = i;
6218 alu.dst.write = 1;
6219 alu.last = i == last_inst;
6220
6221 alu.src[0].sel = t1;
6222 alu.src[0].chan = i;
6223 alu.src[1].sel = t2;
6224 alu.src[1].chan = i;
6225 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6226
6227 r = r600_bytecode_add_alu(ctx->bc, &alu);
6228 if (r)
6229 return r;
6230 }
6231
6232 return 0;
6233 }
6234
6235 static int tgsi_msb(struct r600_shader_ctx *ctx)
6236 {
6237 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6238 struct r600_bytecode_alu alu;
6239 int i, r, t1, t2;
6240
6241 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6242 int last_inst = tgsi_last_instruction(write_mask);
6243
6244 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6245 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6246
6247 t1 = ctx->temp_reg;
6248
6249 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6250 for (i = 0; i < 4; i++) {
6251 if (!(write_mask & (1<<i)))
6252 continue;
6253
6254 /* t1 = FFBH_INT / FFBH_UINT */
6255 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6256 alu.op = ctx->inst_info->op;
6257 alu.dst.sel = t1;
6258 alu.dst.chan = i;
6259 alu.dst.write = 1;
6260 alu.last = i == last_inst;
6261
6262 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6263
6264 r = r600_bytecode_add_alu(ctx->bc, &alu);
6265 if (r)
6266 return r;
6267 }
6268
6269 t2 = r600_get_temp(ctx);
6270
6271 for (i = 0; i < 4; i++) {
6272 if (!(write_mask & (1<<i)))
6273 continue;
6274
6275 /* t2 = 31 - t1 */
6276 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6277 alu.op = ALU_OP2_SUB_INT;
6278 alu.dst.sel = t2;
6279 alu.dst.chan = i;
6280 alu.dst.write = 1;
6281 alu.last = i == last_inst;
6282
6283 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6284 alu.src[0].value = 31;
6285 alu.src[1].sel = t1;
6286 alu.src[1].chan = i;
6287
6288 r = r600_bytecode_add_alu(ctx->bc, &alu);
6289 if (r)
6290 return r;
6291 }
6292
6293 for (i = 0; i < 4; i++) {
6294 if (!(write_mask & (1<<i)))
6295 continue;
6296
6297 /* result = t1 >= 0 ? t2 : t1 */
6298 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6299 alu.op = ALU_OP3_CNDGE_INT;
6300 alu.is_op3 = 1;
6301 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6302 alu.dst.chan = i;
6303 alu.dst.write = 1;
6304 alu.last = i == last_inst;
6305
6306 alu.src[0].sel = t1;
6307 alu.src[0].chan = i;
6308 alu.src[1].sel = t2;
6309 alu.src[1].chan = i;
6310 alu.src[2].sel = t1;
6311 alu.src[2].chan = i;
6312
6313 r = r600_bytecode_add_alu(ctx->bc, &alu);
6314 if (r)
6315 return r;
6316 }
6317
6318 return 0;
6319 }
6320
6321 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6322 {
6323 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6324 struct r600_bytecode_alu alu;
6325 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6326 unsigned location;
6327 int input;
6328
6329 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6330
6331 input = inst->Src[0].Register.Index;
6332
6333 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6334 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6335 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6336 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6337 }
6338 else {
6339 location = TGSI_INTERPOLATE_LOC_CENTROID;
6340 }
6341
6342 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6343 if (k < 0)
6344 k = 0;
6345 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6346 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6347
6348 /* NOTE: currently offset is not perspective correct */
6349 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6350 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6351 int sample_gpr = -1;
6352 int gradientsH, gradientsV;
6353 struct r600_bytecode_tex tex;
6354
6355 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6356 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6357 }
6358
6359 gradientsH = r600_get_temp(ctx);
6360 gradientsV = r600_get_temp(ctx);
6361 for (i = 0; i < 2; i++) {
6362 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6363 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6364 tex.src_gpr = interp_gpr;
6365 tex.src_sel_x = interp_base_chan + 0;
6366 tex.src_sel_y = interp_base_chan + 1;
6367 tex.src_sel_z = 0;
6368 tex.src_sel_w = 0;
6369 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6370 tex.dst_sel_x = 0;
6371 tex.dst_sel_y = 1;
6372 tex.dst_sel_z = 7;
6373 tex.dst_sel_w = 7;
6374 tex.inst_mod = 1; // Use per pixel gradient calculation
6375 tex.sampler_id = 0;
6376 tex.resource_id = tex.sampler_id;
6377 r = r600_bytecode_add_tex(ctx->bc, &tex);
6378 if (r)
6379 return r;
6380 }
6381
6382 for (i = 0; i < 2; i++) {
6383 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6384 alu.op = ALU_OP3_MULADD;
6385 alu.is_op3 = 1;
6386 alu.src[0].sel = gradientsH;
6387 alu.src[0].chan = i;
6388 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6389 alu.src[1].sel = sample_gpr;
6390 alu.src[1].chan = 2;
6391 }
6392 else {
6393 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6394 }
6395 alu.src[2].sel = interp_gpr;
6396 alu.src[2].chan = interp_base_chan + i;
6397 alu.dst.sel = ctx->temp_reg;
6398 alu.dst.chan = i;
6399 alu.last = i == 1;
6400
6401 r = r600_bytecode_add_alu(ctx->bc, &alu);
6402 if (r)
6403 return r;
6404 }
6405
6406 for (i = 0; i < 2; i++) {
6407 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6408 alu.op = ALU_OP3_MULADD;
6409 alu.is_op3 = 1;
6410 alu.src[0].sel = gradientsV;
6411 alu.src[0].chan = i;
6412 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6413 alu.src[1].sel = sample_gpr;
6414 alu.src[1].chan = 3;
6415 }
6416 else {
6417 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6418 }
6419 alu.src[2].sel = ctx->temp_reg;
6420 alu.src[2].chan = i;
6421 alu.dst.sel = ctx->temp_reg;
6422 alu.dst.chan = i;
6423 alu.last = i == 1;
6424
6425 r = r600_bytecode_add_alu(ctx->bc, &alu);
6426 if (r)
6427 return r;
6428 }
6429 }
6430
6431 tmp = r600_get_temp(ctx);
6432 for (i = 0; i < 8; i++) {
6433 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6434 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6435
6436 alu.dst.sel = tmp;
6437 if ((i > 1 && i < 6)) {
6438 alu.dst.write = 1;
6439 }
6440 else {
6441 alu.dst.write = 0;
6442 }
6443 alu.dst.chan = i % 4;
6444
6445 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6446 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6447 alu.src[0].sel = ctx->temp_reg;
6448 alu.src[0].chan = 1 - (i % 2);
6449 } else {
6450 alu.src[0].sel = interp_gpr;
6451 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
6452 }
6453 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
6454 alu.src[1].chan = 0;
6455
6456 alu.last = i % 4 == 3;
6457 alu.bank_swizzle_force = SQ_ALU_VEC_210;
6458
6459 r = r600_bytecode_add_alu(ctx->bc, &alu);
6460 if (r)
6461 return r;
6462 }
6463
6464 // INTERP can't swizzle dst
6465 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6466 for (i = 0; i <= lasti; i++) {
6467 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6468 continue;
6469
6470 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6471 alu.op = ALU_OP1_MOV;
6472 alu.src[0].sel = tmp;
6473 alu.src[0].chan = ctx->src[0].swizzle[i];
6474 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6475 alu.dst.write = 1;
6476 alu.last = i == lasti;
6477 r = r600_bytecode_add_alu(ctx->bc, &alu);
6478 if (r)
6479 return r;
6480 }
6481
6482 return 0;
6483 }
6484
6485
6486 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
6487 {
6488 struct r600_bytecode_alu alu;
6489 int i, r;
6490
6491 for (i = 0; i < 4; i++) {
6492 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6493 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
6494 alu.op = ALU_OP0_NOP;
6495 alu.dst.chan = i;
6496 } else {
6497 alu.op = ALU_OP1_MOV;
6498 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6499 alu.src[0].sel = ctx->temp_reg;
6500 alu.src[0].chan = i;
6501 }
6502 if (i == 3) {
6503 alu.last = 1;
6504 }
6505 r = r600_bytecode_add_alu(ctx->bc, &alu);
6506 if (r)
6507 return r;
6508 }
6509 return 0;
6510 }
6511
6512 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
6513 unsigned temp, int chan,
6514 struct r600_bytecode_alu_src *bc_src,
6515 const struct r600_shader_src *shader_src)
6516 {
6517 struct r600_bytecode_alu alu;
6518 int r;
6519
6520 r600_bytecode_src(bc_src, shader_src, chan);
6521
6522 /* op3 operands don't support abs modifier */
6523 if (bc_src->abs) {
6524 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
6525 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6526 alu.op = ALU_OP1_MOV;
6527 alu.dst.sel = temp;
6528 alu.dst.chan = chan;
6529 alu.dst.write = 1;
6530
6531 alu.src[0] = *bc_src;
6532 alu.last = true; // sufficient?
6533 r = r600_bytecode_add_alu(ctx->bc, &alu);
6534 if (r)
6535 return r;
6536
6537 memset(bc_src, 0, sizeof(*bc_src));
6538 bc_src->sel = temp;
6539 bc_src->chan = chan;
6540 }
6541 return 0;
6542 }
6543
6544 static int tgsi_op3(struct r600_shader_ctx *ctx)
6545 {
6546 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6547 struct r600_bytecode_alu alu;
6548 int i, j, r;
6549 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6550 int temp_regs[4];
6551 unsigned op = ctx->inst_info->op;
6552
6553 if (op == ALU_OP3_MULADD_IEEE &&
6554 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6555 op = ALU_OP3_MULADD;
6556
6557 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6558 temp_regs[j] = 0;
6559 if (ctx->src[j].abs)
6560 temp_regs[j] = r600_get_temp(ctx);
6561 }
6562 for (i = 0; i < lasti + 1; i++) {
6563 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6564 continue;
6565
6566 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6567 alu.op = op;
6568 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6569 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
6570 if (r)
6571 return r;
6572 }
6573
6574 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6575 alu.dst.chan = i;
6576 alu.dst.write = 1;
6577 alu.is_op3 = 1;
6578 if (i == lasti) {
6579 alu.last = 1;
6580 }
6581 r = r600_bytecode_add_alu(ctx->bc, &alu);
6582 if (r)
6583 return r;
6584 }
6585 return 0;
6586 }
6587
6588 static int tgsi_dp(struct r600_shader_ctx *ctx)
6589 {
6590 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6591 struct r600_bytecode_alu alu;
6592 int i, j, r;
6593 unsigned op = ctx->inst_info->op;
6594 if (op == ALU_OP2_DOT4_IEEE &&
6595 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6596 op = ALU_OP2_DOT4;
6597
6598 for (i = 0; i < 4; i++) {
6599 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6600 alu.op = op;
6601 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6602 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6603 }
6604
6605 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6606 alu.dst.chan = i;
6607 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
6608 /* handle some special cases */
6609 switch (inst->Instruction.Opcode) {
6610 case TGSI_OPCODE_DP2:
6611 if (i > 1) {
6612 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6613 alu.src[0].chan = alu.src[1].chan = 0;
6614 }
6615 break;
6616 case TGSI_OPCODE_DP3:
6617 if (i > 2) {
6618 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6619 alu.src[0].chan = alu.src[1].chan = 0;
6620 }
6621 break;
6622 case TGSI_OPCODE_DPH:
6623 if (i == 3) {
6624 alu.src[0].sel = V_SQ_ALU_SRC_1;
6625 alu.src[0].chan = 0;
6626 alu.src[0].neg = 0;
6627 }
6628 break;
6629 default:
6630 break;
6631 }
6632 if (i == 3) {
6633 alu.last = 1;
6634 }
6635 r = r600_bytecode_add_alu(ctx->bc, &alu);
6636 if (r)
6637 return r;
6638 }
6639 return 0;
6640 }
6641
6642 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
6643 unsigned index)
6644 {
6645 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6646 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
6647 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
6648 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
6649 ctx->src[index].neg || ctx->src[index].abs ||
6650 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
6651 }
6652
6653 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
6654 unsigned index)
6655 {
6656 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6657 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
6658 }
6659
6660 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
6661 {
6662 struct r600_bytecode_vtx vtx;
6663 struct r600_bytecode_alu alu;
6664 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6665 int src_gpr, r, i;
6666 int id = tgsi_tex_get_src_gpr(ctx, 1);
6667
6668 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6669 if (src_requires_loading) {
6670 for (i = 0; i < 4; i++) {
6671 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6672 alu.op = ALU_OP1_MOV;
6673 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6674 alu.dst.sel = ctx->temp_reg;
6675 alu.dst.chan = i;
6676 if (i == 3)
6677 alu.last = 1;
6678 alu.dst.write = 1;
6679 r = r600_bytecode_add_alu(ctx->bc, &alu);
6680 if (r)
6681 return r;
6682 }
6683 src_gpr = ctx->temp_reg;
6684 }
6685
6686 memset(&vtx, 0, sizeof(vtx));
6687 vtx.op = FETCH_OP_VFETCH;
6688 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6689 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6690 vtx.src_gpr = src_gpr;
6691 vtx.mega_fetch_count = 16;
6692 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6693 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6694 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
6695 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
6696 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
6697 vtx.use_const_fields = 1;
6698
6699 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
6700 return r;
6701
6702 if (ctx->bc->chip_class >= EVERGREEN)
6703 return 0;
6704
6705 for (i = 0; i < 4; i++) {
6706 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6707 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6708 continue;
6709
6710 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6711 alu.op = ALU_OP2_AND_INT;
6712
6713 alu.dst.chan = i;
6714 alu.dst.sel = vtx.dst_gpr;
6715 alu.dst.write = 1;
6716
6717 alu.src[0].sel = vtx.dst_gpr;
6718 alu.src[0].chan = i;
6719
6720 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
6721 alu.src[1].sel += (id * 2);
6722 alu.src[1].chan = i % 4;
6723 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6724
6725 if (i == lasti)
6726 alu.last = 1;
6727 r = r600_bytecode_add_alu(ctx->bc, &alu);
6728 if (r)
6729 return r;
6730 }
6731
6732 if (inst->Dst[0].Register.WriteMask & 3) {
6733 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6734 alu.op = ALU_OP2_OR_INT;
6735
6736 alu.dst.chan = 3;
6737 alu.dst.sel = vtx.dst_gpr;
6738 alu.dst.write = 1;
6739
6740 alu.src[0].sel = vtx.dst_gpr;
6741 alu.src[0].chan = 3;
6742
6743 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
6744 alu.src[1].chan = 0;
6745 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6746
6747 alu.last = 1;
6748 r = r600_bytecode_add_alu(ctx->bc, &alu);
6749 if (r)
6750 return r;
6751 }
6752 return 0;
6753 }
6754
6755 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
6756 {
6757 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6758 struct r600_bytecode_alu alu;
6759 int r;
6760 int id = tgsi_tex_get_src_gpr(ctx, 1);
6761
6762 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6763 alu.op = ALU_OP1_MOV;
6764 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6765 if (ctx->bc->chip_class >= EVERGREEN) {
6766 /* channel 0 or 2 of each word */
6767 alu.src[0].sel += (id / 2);
6768 alu.src[0].chan = (id % 2) * 2;
6769 } else {
6770 /* r600 we have them at channel 2 of the second dword */
6771 alu.src[0].sel += (id * 2) + 1;
6772 alu.src[0].chan = 1;
6773 }
6774 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6775 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
6776 alu.last = 1;
6777 r = r600_bytecode_add_alu(ctx->bc, &alu);
6778 if (r)
6779 return r;
6780 return 0;
6781 }
6782
6783 static int tgsi_tex(struct r600_shader_ctx *ctx)
6784 {
6785 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6786 struct r600_bytecode_tex tex;
6787 struct r600_bytecode_alu alu;
6788 unsigned src_gpr;
6789 int r, i, j;
6790 int opcode;
6791 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
6792 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6793 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
6794 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
6795
6796 bool txf_add_offsets = inst->Texture.NumOffsets &&
6797 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6798 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
6799
6800 /* Texture fetch instructions can only use gprs as source.
6801 * Also they cannot negate the source or take the absolute value */
6802 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
6803 inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
6804 tgsi_tex_src_requires_loading(ctx, 0)) ||
6805 read_compressed_msaa || txf_add_offsets;
6806
6807 boolean src_loaded = FALSE;
6808 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
6809 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
6810 boolean has_txq_cube_array_z = false;
6811 unsigned sampler_index_mode;
6812
6813 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
6814 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6815 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
6816 if (inst->Dst[0].Register.WriteMask & 4) {
6817 ctx->shader->has_txq_cube_array_z_comp = true;
6818 has_txq_cube_array_z = true;
6819 }
6820
6821 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
6822 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
6823 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
6824 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
6825 sampler_src_reg = 2;
6826
6827 /* TGSI moves the sampler to src reg 3 for TXD */
6828 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
6829 sampler_src_reg = 3;
6830
6831 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6832
6833 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6834
6835 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
6836 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
6837 ctx->shader->uses_tex_buffers = true;
6838 return r600_do_buffer_txq(ctx);
6839 }
6840 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
6841 if (ctx->bc->chip_class < EVERGREEN)
6842 ctx->shader->uses_tex_buffers = true;
6843 return do_vtx_fetch_inst(ctx, src_requires_loading);
6844 }
6845 }
6846
6847 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
6848 int out_chan;
6849 /* Add perspective divide */
6850 if (ctx->bc->chip_class == CAYMAN) {
6851 out_chan = 2;
6852 for (i = 0; i < 3; i++) {
6853 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6854 alu.op = ALU_OP1_RECIP_IEEE;
6855 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6856
6857 alu.dst.sel = ctx->temp_reg;
6858 alu.dst.chan = i;
6859 if (i == 2)
6860 alu.last = 1;
6861 if (out_chan == i)
6862 alu.dst.write = 1;
6863 r = r600_bytecode_add_alu(ctx->bc, &alu);
6864 if (r)
6865 return r;
6866 }
6867
6868 } else {
6869 out_chan = 3;
6870 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6871 alu.op = ALU_OP1_RECIP_IEEE;
6872 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6873
6874 alu.dst.sel = ctx->temp_reg;
6875 alu.dst.chan = out_chan;
6876 alu.last = 1;
6877 alu.dst.write = 1;
6878 r = r600_bytecode_add_alu(ctx->bc, &alu);
6879 if (r)
6880 return r;
6881 }
6882
6883 for (i = 0; i < 3; i++) {
6884 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6885 alu.op = ALU_OP2_MUL;
6886 alu.src[0].sel = ctx->temp_reg;
6887 alu.src[0].chan = out_chan;
6888 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6889 alu.dst.sel = ctx->temp_reg;
6890 alu.dst.chan = i;
6891 alu.dst.write = 1;
6892 r = r600_bytecode_add_alu(ctx->bc, &alu);
6893 if (r)
6894 return r;
6895 }
6896 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6897 alu.op = ALU_OP1_MOV;
6898 alu.src[0].sel = V_SQ_ALU_SRC_1;
6899 alu.src[0].chan = 0;
6900 alu.dst.sel = ctx->temp_reg;
6901 alu.dst.chan = 3;
6902 alu.last = 1;
6903 alu.dst.write = 1;
6904 r = r600_bytecode_add_alu(ctx->bc, &alu);
6905 if (r)
6906 return r;
6907 src_loaded = TRUE;
6908 src_gpr = ctx->temp_reg;
6909 }
6910
6911
6912 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
6913 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6914 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6915 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
6916 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
6917 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
6918
6919 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
6920 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
6921
6922 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
6923 for (i = 0; i < 4; i++) {
6924 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6925 alu.op = ALU_OP2_CUBE;
6926 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6927 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
6928 alu.dst.sel = ctx->temp_reg;
6929 alu.dst.chan = i;
6930 if (i == 3)
6931 alu.last = 1;
6932 alu.dst.write = 1;
6933 r = r600_bytecode_add_alu(ctx->bc, &alu);
6934 if (r)
6935 return r;
6936 }
6937
6938 /* tmp1.z = RCP_e(|tmp1.z|) */
6939 if (ctx->bc->chip_class == CAYMAN) {
6940 for (i = 0; i < 3; i++) {
6941 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6942 alu.op = ALU_OP1_RECIP_IEEE;
6943 alu.src[0].sel = ctx->temp_reg;
6944 alu.src[0].chan = 2;
6945 alu.src[0].abs = 1;
6946 alu.dst.sel = ctx->temp_reg;
6947 alu.dst.chan = i;
6948 if (i == 2)
6949 alu.dst.write = 1;
6950 if (i == 2)
6951 alu.last = 1;
6952 r = r600_bytecode_add_alu(ctx->bc, &alu);
6953 if (r)
6954 return r;
6955 }
6956 } else {
6957 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6958 alu.op = ALU_OP1_RECIP_IEEE;
6959 alu.src[0].sel = ctx->temp_reg;
6960 alu.src[0].chan = 2;
6961 alu.src[0].abs = 1;
6962 alu.dst.sel = ctx->temp_reg;
6963 alu.dst.chan = 2;
6964 alu.dst.write = 1;
6965 alu.last = 1;
6966 r = r600_bytecode_add_alu(ctx->bc, &alu);
6967 if (r)
6968 return r;
6969 }
6970
6971 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
6972 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
6973 * muladd has no writemask, have to use another temp
6974 */
6975 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6976 alu.op = ALU_OP3_MULADD;
6977 alu.is_op3 = 1;
6978
6979 alu.src[0].sel = ctx->temp_reg;
6980 alu.src[0].chan = 0;
6981 alu.src[1].sel = ctx->temp_reg;
6982 alu.src[1].chan = 2;
6983
6984 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
6985 alu.src[2].chan = 0;
6986 alu.src[2].value = u_bitcast_f2u(1.5f);
6987
6988 alu.dst.sel = ctx->temp_reg;
6989 alu.dst.chan = 0;
6990 alu.dst.write = 1;
6991
6992 r = r600_bytecode_add_alu(ctx->bc, &alu);
6993 if (r)
6994 return r;
6995
6996 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6997 alu.op = ALU_OP3_MULADD;
6998 alu.is_op3 = 1;
6999
7000 alu.src[0].sel = ctx->temp_reg;
7001 alu.src[0].chan = 1;
7002 alu.src[1].sel = ctx->temp_reg;
7003 alu.src[1].chan = 2;
7004
7005 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7006 alu.src[2].chan = 0;
7007 alu.src[2].value = u_bitcast_f2u(1.5f);
7008
7009 alu.dst.sel = ctx->temp_reg;
7010 alu.dst.chan = 1;
7011 alu.dst.write = 1;
7012
7013 alu.last = 1;
7014 r = r600_bytecode_add_alu(ctx->bc, &alu);
7015 if (r)
7016 return r;
7017 /* write initial compare value into Z component
7018 - W src 0 for shadow cube
7019 - X src 1 for shadow cube array */
7020 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7021 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7022 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7023 alu.op = ALU_OP1_MOV;
7024 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
7025 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7026 else
7027 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7028 alu.dst.sel = ctx->temp_reg;
7029 alu.dst.chan = 2;
7030 alu.dst.write = 1;
7031 alu.last = 1;
7032 r = r600_bytecode_add_alu(ctx->bc, &alu);
7033 if (r)
7034 return r;
7035 }
7036
7037 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7038 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7039 if (ctx->bc->chip_class >= EVERGREEN) {
7040 int mytmp = r600_get_temp(ctx);
7041 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7042 alu.op = ALU_OP1_MOV;
7043 alu.src[0].sel = ctx->temp_reg;
7044 alu.src[0].chan = 3;
7045 alu.dst.sel = mytmp;
7046 alu.dst.chan = 0;
7047 alu.dst.write = 1;
7048 alu.last = 1;
7049 r = r600_bytecode_add_alu(ctx->bc, &alu);
7050 if (r)
7051 return r;
7052
7053 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7054 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7055 alu.op = ALU_OP3_MULADD;
7056 alu.is_op3 = 1;
7057 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7058 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7059 alu.src[1].chan = 0;
7060 alu.src[1].value = u_bitcast_f2u(8.0f);
7061 alu.src[2].sel = mytmp;
7062 alu.src[2].chan = 0;
7063 alu.dst.sel = ctx->temp_reg;
7064 alu.dst.chan = 3;
7065 alu.dst.write = 1;
7066 alu.last = 1;
7067 r = r600_bytecode_add_alu(ctx->bc, &alu);
7068 if (r)
7069 return r;
7070 } else if (ctx->bc->chip_class < EVERGREEN) {
7071 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7072 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7073 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7074 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7075 tex.src_gpr = r600_get_temp(ctx);
7076 tex.src_sel_x = 0;
7077 tex.src_sel_y = 0;
7078 tex.src_sel_z = 0;
7079 tex.src_sel_w = 0;
7080 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7081 tex.coord_type_x = 1;
7082 tex.coord_type_y = 1;
7083 tex.coord_type_z = 1;
7084 tex.coord_type_w = 1;
7085 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7086 alu.op = ALU_OP1_MOV;
7087 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7088 alu.dst.sel = tex.src_gpr;
7089 alu.dst.chan = 0;
7090 alu.last = 1;
7091 alu.dst.write = 1;
7092 r = r600_bytecode_add_alu(ctx->bc, &alu);
7093 if (r)
7094 return r;
7095
7096 r = r600_bytecode_add_tex(ctx->bc, &tex);
7097 if (r)
7098 return r;
7099 }
7100
7101 }
7102
7103 /* for cube forms of lod and bias we need to route things */
7104 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7105 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7106 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7107 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7108 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7109 alu.op = ALU_OP1_MOV;
7110 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7111 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7112 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7113 else
7114 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7115 alu.dst.sel = ctx->temp_reg;
7116 alu.dst.chan = 2;
7117 alu.last = 1;
7118 alu.dst.write = 1;
7119 r = r600_bytecode_add_alu(ctx->bc, &alu);
7120 if (r)
7121 return r;
7122 }
7123
7124 src_loaded = TRUE;
7125 src_gpr = ctx->temp_reg;
7126 }
7127
7128 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7129 int temp_h = 0, temp_v = 0;
7130 int start_val = 0;
7131
7132 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7133 if (src_loaded == TRUE)
7134 start_val = 1;
7135 else
7136 src_loaded = TRUE;
7137 for (i = start_val; i < 3; i++) {
7138 int treg = r600_get_temp(ctx);
7139
7140 if (i == 0)
7141 src_gpr = treg;
7142 else if (i == 1)
7143 temp_h = treg;
7144 else
7145 temp_v = treg;
7146
7147 for (j = 0; j < 4; j++) {
7148 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7149 alu.op = ALU_OP1_MOV;
7150 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7151 alu.dst.sel = treg;
7152 alu.dst.chan = j;
7153 if (j == 3)
7154 alu.last = 1;
7155 alu.dst.write = 1;
7156 r = r600_bytecode_add_alu(ctx->bc, &alu);
7157 if (r)
7158 return r;
7159 }
7160 }
7161 for (i = 1; i < 3; i++) {
7162 /* set gradients h/v */
7163 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7164 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7165 FETCH_OP_SET_GRADIENTS_V;
7166 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7167 tex.sampler_index_mode = sampler_index_mode;
7168 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7169 tex.resource_index_mode = sampler_index_mode;
7170
7171 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7172 tex.src_sel_x = 0;
7173 tex.src_sel_y = 1;
7174 tex.src_sel_z = 2;
7175 tex.src_sel_w = 3;
7176
7177 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7178 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7179 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7180 tex.coord_type_x = 1;
7181 tex.coord_type_y = 1;
7182 tex.coord_type_z = 1;
7183 tex.coord_type_w = 1;
7184 }
7185 r = r600_bytecode_add_tex(ctx->bc, &tex);
7186 if (r)
7187 return r;
7188 }
7189 }
7190
7191 if (src_requires_loading && !src_loaded) {
7192 for (i = 0; i < 4; i++) {
7193 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7194 alu.op = ALU_OP1_MOV;
7195 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7196 alu.dst.sel = ctx->temp_reg;
7197 alu.dst.chan = i;
7198 if (i == 3)
7199 alu.last = 1;
7200 alu.dst.write = 1;
7201 r = r600_bytecode_add_alu(ctx->bc, &alu);
7202 if (r)
7203 return r;
7204 }
7205 src_loaded = TRUE;
7206 src_gpr = ctx->temp_reg;
7207 }
7208
7209 /* get offset values */
7210 if (inst->Texture.NumOffsets) {
7211 assert(inst->Texture.NumOffsets == 1);
7212
7213 /* The texture offset feature doesn't work with the TXF instruction
7214 * and must be emulated by adding the offset to the texture coordinates. */
7215 if (txf_add_offsets) {
7216 const struct tgsi_texture_offset *off = inst->TexOffsets;
7217
7218 switch (inst->Texture.Texture) {
7219 case TGSI_TEXTURE_3D:
7220 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7221 alu.op = ALU_OP2_ADD_INT;
7222 alu.src[0].sel = src_gpr;
7223 alu.src[0].chan = 2;
7224 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7225 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7226 alu.dst.sel = src_gpr;
7227 alu.dst.chan = 2;
7228 alu.dst.write = 1;
7229 alu.last = 1;
7230 r = r600_bytecode_add_alu(ctx->bc, &alu);
7231 if (r)
7232 return r;
7233 /* fall through */
7234
7235 case TGSI_TEXTURE_2D:
7236 case TGSI_TEXTURE_SHADOW2D:
7237 case TGSI_TEXTURE_RECT:
7238 case TGSI_TEXTURE_SHADOWRECT:
7239 case TGSI_TEXTURE_2D_ARRAY:
7240 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7241 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7242 alu.op = ALU_OP2_ADD_INT;
7243 alu.src[0].sel = src_gpr;
7244 alu.src[0].chan = 1;
7245 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7246 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7247 alu.dst.sel = src_gpr;
7248 alu.dst.chan = 1;
7249 alu.dst.write = 1;
7250 alu.last = 1;
7251 r = r600_bytecode_add_alu(ctx->bc, &alu);
7252 if (r)
7253 return r;
7254 /* fall through */
7255
7256 case TGSI_TEXTURE_1D:
7257 case TGSI_TEXTURE_SHADOW1D:
7258 case TGSI_TEXTURE_1D_ARRAY:
7259 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7260 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7261 alu.op = ALU_OP2_ADD_INT;
7262 alu.src[0].sel = src_gpr;
7263 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7264 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
7265 alu.dst.sel = src_gpr;
7266 alu.dst.write = 1;
7267 alu.last = 1;
7268 r = r600_bytecode_add_alu(ctx->bc, &alu);
7269 if (r)
7270 return r;
7271 break;
7272 /* texture offsets do not apply to other texture targets */
7273 }
7274 } else {
7275 switch (inst->Texture.Texture) {
7276 case TGSI_TEXTURE_3D:
7277 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
7278 /* fallthrough */
7279 case TGSI_TEXTURE_2D:
7280 case TGSI_TEXTURE_SHADOW2D:
7281 case TGSI_TEXTURE_RECT:
7282 case TGSI_TEXTURE_SHADOWRECT:
7283 case TGSI_TEXTURE_2D_ARRAY:
7284 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7285 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
7286 /* fallthrough */
7287 case TGSI_TEXTURE_1D:
7288 case TGSI_TEXTURE_SHADOW1D:
7289 case TGSI_TEXTURE_1D_ARRAY:
7290 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7291 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
7292 }
7293 }
7294 }
7295
7296 /* Obtain the sample index for reading a compressed MSAA color texture.
7297 * To read the FMASK, we use the ldfptr instruction, which tells us
7298 * where the samples are stored.
7299 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7300 * which is the identity mapping. Each nibble says which physical sample
7301 * should be fetched to get that sample.
7302 *
7303 * Assume src.z contains the sample index. It should be modified like this:
7304 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7305 * Then fetch the texel with src.
7306 */
7307 if (read_compressed_msaa) {
7308 unsigned sample_chan = 3;
7309 unsigned temp = r600_get_temp(ctx);
7310 assert(src_loaded);
7311
7312 /* temp.w = ldfptr() */
7313 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7314 tex.op = FETCH_OP_LD;
7315 tex.inst_mod = 1; /* to indicate this is ldfptr */
7316 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7317 tex.sampler_index_mode = sampler_index_mode;
7318 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7319 tex.resource_index_mode = sampler_index_mode;
7320 tex.src_gpr = src_gpr;
7321 tex.dst_gpr = temp;
7322 tex.dst_sel_x = 7; /* mask out these components */
7323 tex.dst_sel_y = 7;
7324 tex.dst_sel_z = 7;
7325 tex.dst_sel_w = 0; /* store X */
7326 tex.src_sel_x = 0;
7327 tex.src_sel_y = 1;
7328 tex.src_sel_z = 2;
7329 tex.src_sel_w = 3;
7330 tex.offset_x = offset_x;
7331 tex.offset_y = offset_y;
7332 tex.offset_z = offset_z;
7333 r = r600_bytecode_add_tex(ctx->bc, &tex);
7334 if (r)
7335 return r;
7336
7337 /* temp.x = sample_index*4 */
7338 if (ctx->bc->chip_class == CAYMAN) {
7339 for (i = 0 ; i < 4; i++) {
7340 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7341 alu.op = ALU_OP2_MULLO_INT;
7342 alu.src[0].sel = src_gpr;
7343 alu.src[0].chan = sample_chan;
7344 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7345 alu.src[1].value = 4;
7346 alu.dst.sel = temp;
7347 alu.dst.chan = i;
7348 alu.dst.write = i == 0;
7349 if (i == 3)
7350 alu.last = 1;
7351 r = r600_bytecode_add_alu(ctx->bc, &alu);
7352 if (r)
7353 return r;
7354 }
7355 } else {
7356 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7357 alu.op = ALU_OP2_MULLO_INT;
7358 alu.src[0].sel = src_gpr;
7359 alu.src[0].chan = sample_chan;
7360 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7361 alu.src[1].value = 4;
7362 alu.dst.sel = temp;
7363 alu.dst.chan = 0;
7364 alu.dst.write = 1;
7365 alu.last = 1;
7366 r = r600_bytecode_add_alu(ctx->bc, &alu);
7367 if (r)
7368 return r;
7369 }
7370
7371 /* sample_index = temp.w >> temp.x */
7372 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7373 alu.op = ALU_OP2_LSHR_INT;
7374 alu.src[0].sel = temp;
7375 alu.src[0].chan = 3;
7376 alu.src[1].sel = temp;
7377 alu.src[1].chan = 0;
7378 alu.dst.sel = src_gpr;
7379 alu.dst.chan = sample_chan;
7380 alu.dst.write = 1;
7381 alu.last = 1;
7382 r = r600_bytecode_add_alu(ctx->bc, &alu);
7383 if (r)
7384 return r;
7385
7386 /* sample_index & 0xF */
7387 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7388 alu.op = ALU_OP2_AND_INT;
7389 alu.src[0].sel = src_gpr;
7390 alu.src[0].chan = sample_chan;
7391 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7392 alu.src[1].value = 0xF;
7393 alu.dst.sel = src_gpr;
7394 alu.dst.chan = sample_chan;
7395 alu.dst.write = 1;
7396 alu.last = 1;
7397 r = r600_bytecode_add_alu(ctx->bc, &alu);
7398 if (r)
7399 return r;
7400 #if 0
7401 /* visualize the FMASK */
7402 for (i = 0; i < 4; i++) {
7403 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7404 alu.op = ALU_OP1_INT_TO_FLT;
7405 alu.src[0].sel = src_gpr;
7406 alu.src[0].chan = sample_chan;
7407 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7408 alu.dst.chan = i;
7409 alu.dst.write = 1;
7410 alu.last = 1;
7411 r = r600_bytecode_add_alu(ctx->bc, &alu);
7412 if (r)
7413 return r;
7414 }
7415 return 0;
7416 #endif
7417 }
7418
7419 /* does this shader want a num layers from TXQ for a cube array? */
7420 if (has_txq_cube_array_z) {
7421 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7422
7423 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7424 alu.op = ALU_OP1_MOV;
7425
7426 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7427 if (ctx->bc->chip_class >= EVERGREEN) {
7428 /* channel 1 or 3 of each word */
7429 alu.src[0].sel += (id / 2);
7430 alu.src[0].chan = ((id % 2) * 2) + 1;
7431 } else {
7432 /* r600 we have them at channel 2 of the second dword */
7433 alu.src[0].sel += (id * 2) + 1;
7434 alu.src[0].chan = 2;
7435 }
7436 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7437 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
7438 alu.last = 1;
7439 r = r600_bytecode_add_alu(ctx->bc, &alu);
7440 if (r)
7441 return r;
7442 /* disable writemask from texture instruction */
7443 inst->Dst[0].Register.WriteMask &= ~4;
7444 }
7445
7446 opcode = ctx->inst_info->op;
7447 if (opcode == FETCH_OP_GATHER4 &&
7448 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
7449 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
7450 opcode = FETCH_OP_GATHER4_O;
7451
7452 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7453 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7454 encoded in the instruction are ignored. */
7455 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7456 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
7457 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7458 tex.sampler_index_mode = sampler_index_mode;
7459 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7460 tex.resource_index_mode = sampler_index_mode;
7461
7462 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
7463 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
7464 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
7465 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
7466 tex.src_sel_w = 4;
7467
7468 tex.dst_sel_x = 7;
7469 tex.dst_sel_y = 7;
7470 tex.dst_sel_z = 7;
7471 tex.dst_sel_w = 7;
7472
7473 r = r600_bytecode_add_tex(ctx->bc, &tex);
7474 if (r)
7475 return r;
7476 }
7477
7478 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7479 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7480 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7481 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7482 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
7483 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7484 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7485 switch (opcode) {
7486 case FETCH_OP_SAMPLE:
7487 opcode = FETCH_OP_SAMPLE_C;
7488 break;
7489 case FETCH_OP_SAMPLE_L:
7490 opcode = FETCH_OP_SAMPLE_C_L;
7491 break;
7492 case FETCH_OP_SAMPLE_LB:
7493 opcode = FETCH_OP_SAMPLE_C_LB;
7494 break;
7495 case FETCH_OP_SAMPLE_G:
7496 opcode = FETCH_OP_SAMPLE_C_G;
7497 break;
7498 /* Texture gather variants */
7499 case FETCH_OP_GATHER4:
7500 opcode = FETCH_OP_GATHER4_C;
7501 break;
7502 case FETCH_OP_GATHER4_O:
7503 opcode = FETCH_OP_GATHER4_C_O;
7504 break;
7505 }
7506 }
7507
7508 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7509 tex.op = opcode;
7510
7511 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7512 tex.sampler_index_mode = sampler_index_mode;
7513 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7514 tex.resource_index_mode = sampler_index_mode;
7515 tex.src_gpr = src_gpr;
7516 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7517
7518 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
7519 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
7520 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
7521 }
7522
7523 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7524 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
7525 tex.inst_mod = texture_component_select;
7526
7527 if (ctx->bc->chip_class == CAYMAN) {
7528 /* GATHER4 result order is different from TGSI TG4 */
7529 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
7530 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
7531 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
7532 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7533 } else {
7534 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7535 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7536 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7537 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7538 }
7539 }
7540 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
7541 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7542 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7543 tex.dst_sel_z = 7;
7544 tex.dst_sel_w = 7;
7545 }
7546 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7547 tex.dst_sel_x = 3;
7548 tex.dst_sel_y = 7;
7549 tex.dst_sel_z = 7;
7550 tex.dst_sel_w = 7;
7551 }
7552 else {
7553 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7554 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7555 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7556 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7557 }
7558
7559
7560 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ||
7561 inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7562 tex.src_sel_x = 4;
7563 tex.src_sel_y = 4;
7564 tex.src_sel_z = 4;
7565 tex.src_sel_w = 4;
7566 } else if (src_loaded) {
7567 tex.src_sel_x = 0;
7568 tex.src_sel_y = 1;
7569 tex.src_sel_z = 2;
7570 tex.src_sel_w = 3;
7571 } else {
7572 tex.src_sel_x = ctx->src[0].swizzle[0];
7573 tex.src_sel_y = ctx->src[0].swizzle[1];
7574 tex.src_sel_z = ctx->src[0].swizzle[2];
7575 tex.src_sel_w = ctx->src[0].swizzle[3];
7576 tex.src_rel = ctx->src[0].rel;
7577 }
7578
7579 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7580 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7581 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7582 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7583 tex.src_sel_x = 1;
7584 tex.src_sel_y = 0;
7585 tex.src_sel_z = 3;
7586 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
7587 }
7588
7589 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
7590 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
7591 tex.coord_type_x = 1;
7592 tex.coord_type_y = 1;
7593 }
7594 tex.coord_type_z = 1;
7595 tex.coord_type_w = 1;
7596
7597 tex.offset_x = offset_x;
7598 tex.offset_y = offset_y;
7599 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
7600 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7601 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
7602 tex.offset_z = 0;
7603 }
7604 else {
7605 tex.offset_z = offset_z;
7606 }
7607
7608 /* Put the depth for comparison in W.
7609 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7610 * Some instructions expect the depth in Z. */
7611 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7612 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7613 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7614 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
7615 opcode != FETCH_OP_SAMPLE_C_L &&
7616 opcode != FETCH_OP_SAMPLE_C_LB) {
7617 tex.src_sel_w = tex.src_sel_z;
7618 }
7619
7620 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
7621 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
7622 if (opcode == FETCH_OP_SAMPLE_C_L ||
7623 opcode == FETCH_OP_SAMPLE_C_LB) {
7624 /* the array index is read from Y */
7625 tex.coord_type_y = 0;
7626 } else {
7627 /* the array index is read from Z */
7628 tex.coord_type_z = 0;
7629 tex.src_sel_z = tex.src_sel_y;
7630 }
7631 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7632 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7633 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7634 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7635 (ctx->bc->chip_class >= EVERGREEN)))
7636 /* the array index is read from Z */
7637 tex.coord_type_z = 0;
7638
7639 /* mask unused source components */
7640 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
7641 switch (inst->Texture.Texture) {
7642 case TGSI_TEXTURE_2D:
7643 case TGSI_TEXTURE_RECT:
7644 tex.src_sel_z = 7;
7645 tex.src_sel_w = 7;
7646 break;
7647 case TGSI_TEXTURE_1D_ARRAY:
7648 tex.src_sel_y = 7;
7649 tex.src_sel_w = 7;
7650 break;
7651 case TGSI_TEXTURE_1D:
7652 tex.src_sel_y = 7;
7653 tex.src_sel_z = 7;
7654 tex.src_sel_w = 7;
7655 break;
7656 }
7657 }
7658
7659 r = r600_bytecode_add_tex(ctx->bc, &tex);
7660 if (r)
7661 return r;
7662
7663 /* add shadow ambient support - gallium doesn't do it yet */
7664 return 0;
7665 }
7666
7667 static int tgsi_lrp(struct r600_shader_ctx *ctx)
7668 {
7669 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7670 struct r600_bytecode_alu alu;
7671 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7672 unsigned i, temp_regs[2];
7673 int r;
7674
7675 /* optimize if it's just an equal balance */
7676 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
7677 for (i = 0; i < lasti + 1; i++) {
7678 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7679 continue;
7680
7681 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7682 alu.op = ALU_OP2_ADD;
7683 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
7684 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7685 alu.omod = 3;
7686 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7687 alu.dst.chan = i;
7688 if (i == lasti) {
7689 alu.last = 1;
7690 }
7691 r = r600_bytecode_add_alu(ctx->bc, &alu);
7692 if (r)
7693 return r;
7694 }
7695 return 0;
7696 }
7697
7698 /* 1 - src0 */
7699 for (i = 0; i < lasti + 1; i++) {
7700 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7701 continue;
7702
7703 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7704 alu.op = ALU_OP2_ADD;
7705 alu.src[0].sel = V_SQ_ALU_SRC_1;
7706 alu.src[0].chan = 0;
7707 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
7708 r600_bytecode_src_toggle_neg(&alu.src[1]);
7709 alu.dst.sel = ctx->temp_reg;
7710 alu.dst.chan = i;
7711 if (i == lasti) {
7712 alu.last = 1;
7713 }
7714 alu.dst.write = 1;
7715 r = r600_bytecode_add_alu(ctx->bc, &alu);
7716 if (r)
7717 return r;
7718 }
7719
7720 /* (1 - src0) * src2 */
7721 for (i = 0; i < lasti + 1; i++) {
7722 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7723 continue;
7724
7725 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7726 alu.op = ALU_OP2_MUL;
7727 alu.src[0].sel = ctx->temp_reg;
7728 alu.src[0].chan = i;
7729 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7730 alu.dst.sel = ctx->temp_reg;
7731 alu.dst.chan = i;
7732 if (i == lasti) {
7733 alu.last = 1;
7734 }
7735 alu.dst.write = 1;
7736 r = r600_bytecode_add_alu(ctx->bc, &alu);
7737 if (r)
7738 return r;
7739 }
7740
7741 /* src0 * src1 + (1 - src0) * src2 */
7742 if (ctx->src[0].abs)
7743 temp_regs[0] = r600_get_temp(ctx);
7744 else
7745 temp_regs[0] = 0;
7746 if (ctx->src[1].abs)
7747 temp_regs[1] = r600_get_temp(ctx);
7748 else
7749 temp_regs[1] = 0;
7750
7751 for (i = 0; i < lasti + 1; i++) {
7752 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7753 continue;
7754
7755 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7756 alu.op = ALU_OP3_MULADD;
7757 alu.is_op3 = 1;
7758 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7759 if (r)
7760 return r;
7761 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
7762 if (r)
7763 return r;
7764 alu.src[2].sel = ctx->temp_reg;
7765 alu.src[2].chan = i;
7766
7767 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7768 alu.dst.chan = i;
7769 if (i == lasti) {
7770 alu.last = 1;
7771 }
7772 r = r600_bytecode_add_alu(ctx->bc, &alu);
7773 if (r)
7774 return r;
7775 }
7776 return 0;
7777 }
7778
7779 static int tgsi_cmp(struct r600_shader_ctx *ctx)
7780 {
7781 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7782 struct r600_bytecode_alu alu;
7783 int i, r, j;
7784 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7785 int temp_regs[3];
7786 unsigned op;
7787
7788 if (ctx->src[0].abs && ctx->src[0].neg) {
7789 op = ALU_OP3_CNDE;
7790 ctx->src[0].abs = 0;
7791 ctx->src[0].neg = 0;
7792 } else {
7793 op = ALU_OP3_CNDGE;
7794 }
7795
7796 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7797 temp_regs[j] = 0;
7798 if (ctx->src[j].abs)
7799 temp_regs[j] = r600_get_temp(ctx);
7800 }
7801
7802 for (i = 0; i < lasti + 1; i++) {
7803 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7804 continue;
7805
7806 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7807 alu.op = op;
7808 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7809 if (r)
7810 return r;
7811 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
7812 if (r)
7813 return r;
7814 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
7815 if (r)
7816 return r;
7817 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7818 alu.dst.chan = i;
7819 alu.dst.write = 1;
7820 alu.is_op3 = 1;
7821 if (i == lasti)
7822 alu.last = 1;
7823 r = r600_bytecode_add_alu(ctx->bc, &alu);
7824 if (r)
7825 return r;
7826 }
7827 return 0;
7828 }
7829
7830 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
7831 {
7832 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7833 struct r600_bytecode_alu alu;
7834 int i, r;
7835 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7836
7837 for (i = 0; i < lasti + 1; i++) {
7838 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7839 continue;
7840
7841 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7842 alu.op = ALU_OP3_CNDE_INT;
7843 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7844 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7845 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
7846 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7847 alu.dst.chan = i;
7848 alu.dst.write = 1;
7849 alu.is_op3 = 1;
7850 if (i == lasti)
7851 alu.last = 1;
7852 r = r600_bytecode_add_alu(ctx->bc, &alu);
7853 if (r)
7854 return r;
7855 }
7856 return 0;
7857 }
7858
7859 static int tgsi_xpd(struct r600_shader_ctx *ctx)
7860 {
7861 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7862 static const unsigned int src0_swizzle[] = {2, 0, 1};
7863 static const unsigned int src1_swizzle[] = {1, 2, 0};
7864 struct r600_bytecode_alu alu;
7865 uint32_t use_temp = 0;
7866 int i, r;
7867
7868 if (inst->Dst[0].Register.WriteMask != 0xf)
7869 use_temp = 1;
7870
7871 for (i = 0; i < 4; i++) {
7872 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7873 alu.op = ALU_OP2_MUL;
7874 if (i < 3) {
7875 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
7876 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
7877 } else {
7878 alu.src[0].sel = V_SQ_ALU_SRC_0;
7879 alu.src[0].chan = i;
7880 alu.src[1].sel = V_SQ_ALU_SRC_0;
7881 alu.src[1].chan = i;
7882 }
7883
7884 alu.dst.sel = ctx->temp_reg;
7885 alu.dst.chan = i;
7886 alu.dst.write = 1;
7887
7888 if (i == 3)
7889 alu.last = 1;
7890 r = r600_bytecode_add_alu(ctx->bc, &alu);
7891 if (r)
7892 return r;
7893 }
7894
7895 for (i = 0; i < 4; i++) {
7896 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7897 alu.op = ALU_OP3_MULADD;
7898
7899 if (i < 3) {
7900 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
7901 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
7902 } else {
7903 alu.src[0].sel = V_SQ_ALU_SRC_0;
7904 alu.src[0].chan = i;
7905 alu.src[1].sel = V_SQ_ALU_SRC_0;
7906 alu.src[1].chan = i;
7907 }
7908
7909 alu.src[2].sel = ctx->temp_reg;
7910 alu.src[2].neg = 1;
7911 alu.src[2].chan = i;
7912
7913 if (use_temp)
7914 alu.dst.sel = ctx->temp_reg;
7915 else
7916 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7917 alu.dst.chan = i;
7918 alu.dst.write = 1;
7919 alu.is_op3 = 1;
7920 if (i == 3)
7921 alu.last = 1;
7922 r = r600_bytecode_add_alu(ctx->bc, &alu);
7923 if (r)
7924 return r;
7925 }
7926 if (use_temp)
7927 return tgsi_helper_copy(ctx, inst);
7928 return 0;
7929 }
7930
7931 static int tgsi_exp(struct r600_shader_ctx *ctx)
7932 {
7933 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7934 struct r600_bytecode_alu alu;
7935 int r;
7936 unsigned i;
7937
7938 /* result.x = 2^floor(src); */
7939 if (inst->Dst[0].Register.WriteMask & 1) {
7940 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7941
7942 alu.op = ALU_OP1_FLOOR;
7943 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7944
7945 alu.dst.sel = ctx->temp_reg;
7946 alu.dst.chan = 0;
7947 alu.dst.write = 1;
7948 alu.last = 1;
7949 r = r600_bytecode_add_alu(ctx->bc, &alu);
7950 if (r)
7951 return r;
7952
7953 if (ctx->bc->chip_class == CAYMAN) {
7954 for (i = 0; i < 3; i++) {
7955 alu.op = ALU_OP1_EXP_IEEE;
7956 alu.src[0].sel = ctx->temp_reg;
7957 alu.src[0].chan = 0;
7958
7959 alu.dst.sel = ctx->temp_reg;
7960 alu.dst.chan = i;
7961 alu.dst.write = i == 0;
7962 alu.last = i == 2;
7963 r = r600_bytecode_add_alu(ctx->bc, &alu);
7964 if (r)
7965 return r;
7966 }
7967 } else {
7968 alu.op = ALU_OP1_EXP_IEEE;
7969 alu.src[0].sel = ctx->temp_reg;
7970 alu.src[0].chan = 0;
7971
7972 alu.dst.sel = ctx->temp_reg;
7973 alu.dst.chan = 0;
7974 alu.dst.write = 1;
7975 alu.last = 1;
7976 r = r600_bytecode_add_alu(ctx->bc, &alu);
7977 if (r)
7978 return r;
7979 }
7980 }
7981
7982 /* result.y = tmp - floor(tmp); */
7983 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
7984 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7985
7986 alu.op = ALU_OP1_FRACT;
7987 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7988
7989 alu.dst.sel = ctx->temp_reg;
7990 #if 0
7991 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7992 if (r)
7993 return r;
7994 #endif
7995 alu.dst.write = 1;
7996 alu.dst.chan = 1;
7997
7998 alu.last = 1;
7999
8000 r = r600_bytecode_add_alu(ctx->bc, &alu);
8001 if (r)
8002 return r;
8003 }
8004
8005 /* result.z = RoughApprox2ToX(tmp);*/
8006 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
8007 if (ctx->bc->chip_class == CAYMAN) {
8008 for (i = 0; i < 3; i++) {
8009 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8010 alu.op = ALU_OP1_EXP_IEEE;
8011 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8012
8013 alu.dst.sel = ctx->temp_reg;
8014 alu.dst.chan = i;
8015 if (i == 2) {
8016 alu.dst.write = 1;
8017 alu.last = 1;
8018 }
8019
8020 r = r600_bytecode_add_alu(ctx->bc, &alu);
8021 if (r)
8022 return r;
8023 }
8024 } else {
8025 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8026 alu.op = ALU_OP1_EXP_IEEE;
8027 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8028
8029 alu.dst.sel = ctx->temp_reg;
8030 alu.dst.write = 1;
8031 alu.dst.chan = 2;
8032
8033 alu.last = 1;
8034
8035 r = r600_bytecode_add_alu(ctx->bc, &alu);
8036 if (r)
8037 return r;
8038 }
8039 }
8040
8041 /* result.w = 1.0;*/
8042 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
8043 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8044
8045 alu.op = ALU_OP1_MOV;
8046 alu.src[0].sel = V_SQ_ALU_SRC_1;
8047 alu.src[0].chan = 0;
8048
8049 alu.dst.sel = ctx->temp_reg;
8050 alu.dst.chan = 3;
8051 alu.dst.write = 1;
8052 alu.last = 1;
8053 r = r600_bytecode_add_alu(ctx->bc, &alu);
8054 if (r)
8055 return r;
8056 }
8057 return tgsi_helper_copy(ctx, inst);
8058 }
8059
8060 static int tgsi_log(struct r600_shader_ctx *ctx)
8061 {
8062 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8063 struct r600_bytecode_alu alu;
8064 int r;
8065 unsigned i;
8066
8067 /* result.x = floor(log2(|src|)); */
8068 if (inst->Dst[0].Register.WriteMask & 1) {
8069 if (ctx->bc->chip_class == CAYMAN) {
8070 for (i = 0; i < 3; i++) {
8071 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8072
8073 alu.op = ALU_OP1_LOG_IEEE;
8074 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8075 r600_bytecode_src_set_abs(&alu.src[0]);
8076
8077 alu.dst.sel = ctx->temp_reg;
8078 alu.dst.chan = i;
8079 if (i == 0)
8080 alu.dst.write = 1;
8081 if (i == 2)
8082 alu.last = 1;
8083 r = r600_bytecode_add_alu(ctx->bc, &alu);
8084 if (r)
8085 return r;
8086 }
8087
8088 } else {
8089 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8090
8091 alu.op = ALU_OP1_LOG_IEEE;
8092 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8093 r600_bytecode_src_set_abs(&alu.src[0]);
8094
8095 alu.dst.sel = ctx->temp_reg;
8096 alu.dst.chan = 0;
8097 alu.dst.write = 1;
8098 alu.last = 1;
8099 r = r600_bytecode_add_alu(ctx->bc, &alu);
8100 if (r)
8101 return r;
8102 }
8103
8104 alu.op = ALU_OP1_FLOOR;
8105 alu.src[0].sel = ctx->temp_reg;
8106 alu.src[0].chan = 0;
8107
8108 alu.dst.sel = ctx->temp_reg;
8109 alu.dst.chan = 0;
8110 alu.dst.write = 1;
8111 alu.last = 1;
8112
8113 r = r600_bytecode_add_alu(ctx->bc, &alu);
8114 if (r)
8115 return r;
8116 }
8117
8118 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
8119 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8120
8121 if (ctx->bc->chip_class == CAYMAN) {
8122 for (i = 0; i < 3; i++) {
8123 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8124
8125 alu.op = ALU_OP1_LOG_IEEE;
8126 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8127 r600_bytecode_src_set_abs(&alu.src[0]);
8128
8129 alu.dst.sel = ctx->temp_reg;
8130 alu.dst.chan = i;
8131 if (i == 1)
8132 alu.dst.write = 1;
8133 if (i == 2)
8134 alu.last = 1;
8135
8136 r = r600_bytecode_add_alu(ctx->bc, &alu);
8137 if (r)
8138 return r;
8139 }
8140 } else {
8141 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8142
8143 alu.op = ALU_OP1_LOG_IEEE;
8144 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8145 r600_bytecode_src_set_abs(&alu.src[0]);
8146
8147 alu.dst.sel = ctx->temp_reg;
8148 alu.dst.chan = 1;
8149 alu.dst.write = 1;
8150 alu.last = 1;
8151
8152 r = r600_bytecode_add_alu(ctx->bc, &alu);
8153 if (r)
8154 return r;
8155 }
8156
8157 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8158
8159 alu.op = ALU_OP1_FLOOR;
8160 alu.src[0].sel = ctx->temp_reg;
8161 alu.src[0].chan = 1;
8162
8163 alu.dst.sel = ctx->temp_reg;
8164 alu.dst.chan = 1;
8165 alu.dst.write = 1;
8166 alu.last = 1;
8167
8168 r = r600_bytecode_add_alu(ctx->bc, &alu);
8169 if (r)
8170 return r;
8171
8172 if (ctx->bc->chip_class == CAYMAN) {
8173 for (i = 0; i < 3; i++) {
8174 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8175 alu.op = ALU_OP1_EXP_IEEE;
8176 alu.src[0].sel = ctx->temp_reg;
8177 alu.src[0].chan = 1;
8178
8179 alu.dst.sel = ctx->temp_reg;
8180 alu.dst.chan = i;
8181 if (i == 1)
8182 alu.dst.write = 1;
8183 if (i == 2)
8184 alu.last = 1;
8185
8186 r = r600_bytecode_add_alu(ctx->bc, &alu);
8187 if (r)
8188 return r;
8189 }
8190 } else {
8191 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8192 alu.op = ALU_OP1_EXP_IEEE;
8193 alu.src[0].sel = ctx->temp_reg;
8194 alu.src[0].chan = 1;
8195
8196 alu.dst.sel = ctx->temp_reg;
8197 alu.dst.chan = 1;
8198 alu.dst.write = 1;
8199 alu.last = 1;
8200
8201 r = r600_bytecode_add_alu(ctx->bc, &alu);
8202 if (r)
8203 return r;
8204 }
8205
8206 if (ctx->bc->chip_class == CAYMAN) {
8207 for (i = 0; i < 3; i++) {
8208 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8209 alu.op = ALU_OP1_RECIP_IEEE;
8210 alu.src[0].sel = ctx->temp_reg;
8211 alu.src[0].chan = 1;
8212
8213 alu.dst.sel = ctx->temp_reg;
8214 alu.dst.chan = i;
8215 if (i == 1)
8216 alu.dst.write = 1;
8217 if (i == 2)
8218 alu.last = 1;
8219
8220 r = r600_bytecode_add_alu(ctx->bc, &alu);
8221 if (r)
8222 return r;
8223 }
8224 } else {
8225 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8226 alu.op = ALU_OP1_RECIP_IEEE;
8227 alu.src[0].sel = ctx->temp_reg;
8228 alu.src[0].chan = 1;
8229
8230 alu.dst.sel = ctx->temp_reg;
8231 alu.dst.chan = 1;
8232 alu.dst.write = 1;
8233 alu.last = 1;
8234
8235 r = r600_bytecode_add_alu(ctx->bc, &alu);
8236 if (r)
8237 return r;
8238 }
8239
8240 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8241
8242 alu.op = ALU_OP2_MUL;
8243
8244 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8245 r600_bytecode_src_set_abs(&alu.src[0]);
8246
8247 alu.src[1].sel = ctx->temp_reg;
8248 alu.src[1].chan = 1;
8249
8250 alu.dst.sel = ctx->temp_reg;
8251 alu.dst.chan = 1;
8252 alu.dst.write = 1;
8253 alu.last = 1;
8254
8255 r = r600_bytecode_add_alu(ctx->bc, &alu);
8256 if (r)
8257 return r;
8258 }
8259
8260 /* result.z = log2(|src|);*/
8261 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
8262 if (ctx->bc->chip_class == CAYMAN) {
8263 for (i = 0; i < 3; i++) {
8264 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8265
8266 alu.op = ALU_OP1_LOG_IEEE;
8267 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8268 r600_bytecode_src_set_abs(&alu.src[0]);
8269
8270 alu.dst.sel = ctx->temp_reg;
8271 if (i == 2)
8272 alu.dst.write = 1;
8273 alu.dst.chan = i;
8274 if (i == 2)
8275 alu.last = 1;
8276
8277 r = r600_bytecode_add_alu(ctx->bc, &alu);
8278 if (r)
8279 return r;
8280 }
8281 } else {
8282 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8283
8284 alu.op = ALU_OP1_LOG_IEEE;
8285 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8286 r600_bytecode_src_set_abs(&alu.src[0]);
8287
8288 alu.dst.sel = ctx->temp_reg;
8289 alu.dst.write = 1;
8290 alu.dst.chan = 2;
8291 alu.last = 1;
8292
8293 r = r600_bytecode_add_alu(ctx->bc, &alu);
8294 if (r)
8295 return r;
8296 }
8297 }
8298
8299 /* result.w = 1.0; */
8300 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
8301 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8302
8303 alu.op = ALU_OP1_MOV;
8304 alu.src[0].sel = V_SQ_ALU_SRC_1;
8305 alu.src[0].chan = 0;
8306
8307 alu.dst.sel = ctx->temp_reg;
8308 alu.dst.chan = 3;
8309 alu.dst.write = 1;
8310 alu.last = 1;
8311
8312 r = r600_bytecode_add_alu(ctx->bc, &alu);
8313 if (r)
8314 return r;
8315 }
8316
8317 return tgsi_helper_copy(ctx, inst);
8318 }
8319
8320 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
8321 {
8322 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8323 struct r600_bytecode_alu alu;
8324 int r;
8325 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8326 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
8327
8328 assert(inst->Dst[0].Register.Index < 3);
8329 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8330
8331 switch (inst->Instruction.Opcode) {
8332 case TGSI_OPCODE_ARL:
8333 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
8334 break;
8335 case TGSI_OPCODE_ARR:
8336 alu.op = ALU_OP1_FLT_TO_INT;
8337 break;
8338 case TGSI_OPCODE_UARL:
8339 alu.op = ALU_OP1_MOV;
8340 break;
8341 default:
8342 assert(0);
8343 return -1;
8344 }
8345
8346 for (i = 0; i <= lasti; ++i) {
8347 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8348 continue;
8349 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8350 alu.last = i == lasti;
8351 alu.dst.sel = reg;
8352 alu.dst.chan = i;
8353 alu.dst.write = 1;
8354 r = r600_bytecode_add_alu(ctx->bc, &alu);
8355 if (r)
8356 return r;
8357 }
8358
8359 if (inst->Dst[0].Register.Index > 0)
8360 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
8361 else
8362 ctx->bc->ar_loaded = 0;
8363
8364 return 0;
8365 }
8366 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
8367 {
8368 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8369 struct r600_bytecode_alu alu;
8370 int r;
8371 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8372
8373 switch (inst->Instruction.Opcode) {
8374 case TGSI_OPCODE_ARL:
8375 memset(&alu, 0, sizeof(alu));
8376 alu.op = ALU_OP1_FLOOR;
8377 alu.dst.sel = ctx->bc->ar_reg;
8378 alu.dst.write = 1;
8379 for (i = 0; i <= lasti; ++i) {
8380 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8381 alu.dst.chan = i;
8382 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8383 alu.last = i == lasti;
8384 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8385 return r;
8386 }
8387 }
8388
8389 memset(&alu, 0, sizeof(alu));
8390 alu.op = ALU_OP1_FLT_TO_INT;
8391 alu.src[0].sel = ctx->bc->ar_reg;
8392 alu.dst.sel = ctx->bc->ar_reg;
8393 alu.dst.write = 1;
8394 /* FLT_TO_INT is trans-only on r600/r700 */
8395 alu.last = TRUE;
8396 for (i = 0; i <= lasti; ++i) {
8397 alu.dst.chan = i;
8398 alu.src[0].chan = i;
8399 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8400 return r;
8401 }
8402 break;
8403 case TGSI_OPCODE_ARR:
8404 memset(&alu, 0, sizeof(alu));
8405 alu.op = ALU_OP1_FLT_TO_INT;
8406 alu.dst.sel = ctx->bc->ar_reg;
8407 alu.dst.write = 1;
8408 /* FLT_TO_INT is trans-only on r600/r700 */
8409 alu.last = TRUE;
8410 for (i = 0; i <= lasti; ++i) {
8411 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8412 alu.dst.chan = i;
8413 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8414 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8415 return r;
8416 }
8417 }
8418 break;
8419 case TGSI_OPCODE_UARL:
8420 memset(&alu, 0, sizeof(alu));
8421 alu.op = ALU_OP1_MOV;
8422 alu.dst.sel = ctx->bc->ar_reg;
8423 alu.dst.write = 1;
8424 for (i = 0; i <= lasti; ++i) {
8425 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8426 alu.dst.chan = i;
8427 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8428 alu.last = i == lasti;
8429 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8430 return r;
8431 }
8432 }
8433 break;
8434 default:
8435 assert(0);
8436 return -1;
8437 }
8438
8439 ctx->bc->ar_loaded = 0;
8440 return 0;
8441 }
8442
8443 static int tgsi_opdst(struct r600_shader_ctx *ctx)
8444 {
8445 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8446 struct r600_bytecode_alu alu;
8447 int i, r = 0;
8448
8449 for (i = 0; i < 4; i++) {
8450 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8451
8452 alu.op = ALU_OP2_MUL;
8453 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8454
8455 if (i == 0 || i == 3) {
8456 alu.src[0].sel = V_SQ_ALU_SRC_1;
8457 } else {
8458 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8459 }
8460
8461 if (i == 0 || i == 2) {
8462 alu.src[1].sel = V_SQ_ALU_SRC_1;
8463 } else {
8464 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8465 }
8466 if (i == 3)
8467 alu.last = 1;
8468 r = r600_bytecode_add_alu(ctx->bc, &alu);
8469 if (r)
8470 return r;
8471 }
8472 return 0;
8473 }
8474
8475 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
8476 {
8477 struct r600_bytecode_alu alu;
8478 int r;
8479
8480 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8481 alu.op = opcode;
8482 alu.execute_mask = 1;
8483 alu.update_pred = 1;
8484
8485 alu.dst.sel = ctx->temp_reg;
8486 alu.dst.write = 1;
8487 alu.dst.chan = 0;
8488
8489 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8490 alu.src[1].sel = V_SQ_ALU_SRC_0;
8491 alu.src[1].chan = 0;
8492
8493 alu.last = 1;
8494
8495 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
8496 if (r)
8497 return r;
8498 return 0;
8499 }
8500
8501 static int pops(struct r600_shader_ctx *ctx, int pops)
8502 {
8503 unsigned force_pop = ctx->bc->force_add_cf;
8504
8505 if (!force_pop) {
8506 int alu_pop = 3;
8507 if (ctx->bc->cf_last) {
8508 if (ctx->bc->cf_last->op == CF_OP_ALU)
8509 alu_pop = 0;
8510 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
8511 alu_pop = 1;
8512 }
8513 alu_pop += pops;
8514 if (alu_pop == 1) {
8515 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
8516 ctx->bc->force_add_cf = 1;
8517 } else if (alu_pop == 2) {
8518 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
8519 ctx->bc->force_add_cf = 1;
8520 } else {
8521 force_pop = 1;
8522 }
8523 }
8524
8525 if (force_pop) {
8526 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
8527 ctx->bc->cf_last->pop_count = pops;
8528 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8529 }
8530
8531 return 0;
8532 }
8533
8534 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
8535 unsigned reason)
8536 {
8537 struct r600_stack_info *stack = &ctx->bc->stack;
8538 unsigned elements, entries;
8539
8540 unsigned entry_size = stack->entry_size;
8541
8542 elements = (stack->loop + stack->push_wqm ) * entry_size;
8543 elements += stack->push;
8544
8545 switch (ctx->bc->chip_class) {
8546 case R600:
8547 case R700:
8548 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
8549 * the stack must be reserved to hold the current active/continue
8550 * masks */
8551 if (reason == FC_PUSH_VPM) {
8552 elements += 2;
8553 }
8554 break;
8555
8556 case CAYMAN:
8557 /* r9xx: any stack operation on empty stack consumes 2 additional
8558 * elements */
8559 elements += 2;
8560
8561 /* fallthrough */
8562 /* FIXME: do the two elements added above cover the cases for the
8563 * r8xx+ below? */
8564
8565 case EVERGREEN:
8566 /* r8xx+: 2 extra elements are not always required, but one extra
8567 * element must be added for each of the following cases:
8568 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
8569 * stack usage.
8570 * (Currently we don't use ALU_ELSE_AFTER.)
8571 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
8572 * PUSH instruction executed.
8573 *
8574 * NOTE: it seems we also need to reserve additional element in some
8575 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
8576 * then STACK_SIZE should be 2 instead of 1 */
8577 if (reason == FC_PUSH_VPM) {
8578 elements += 1;
8579 }
8580 break;
8581
8582 default:
8583 assert(0);
8584 break;
8585 }
8586
8587 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
8588 * for all chips, so we use 4 in the final formula, not the real entry_size
8589 * for the chip */
8590 entry_size = 4;
8591
8592 entries = (elements + (entry_size - 1)) / entry_size;
8593
8594 if (entries > stack->max_entries)
8595 stack->max_entries = entries;
8596 }
8597
8598 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
8599 {
8600 switch(reason) {
8601 case FC_PUSH_VPM:
8602 --ctx->bc->stack.push;
8603 assert(ctx->bc->stack.push >= 0);
8604 break;
8605 case FC_PUSH_WQM:
8606 --ctx->bc->stack.push_wqm;
8607 assert(ctx->bc->stack.push_wqm >= 0);
8608 break;
8609 case FC_LOOP:
8610 --ctx->bc->stack.loop;
8611 assert(ctx->bc->stack.loop >= 0);
8612 break;
8613 default:
8614 assert(0);
8615 break;
8616 }
8617 }
8618
8619 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
8620 {
8621 switch (reason) {
8622 case FC_PUSH_VPM:
8623 ++ctx->bc->stack.push;
8624 break;
8625 case FC_PUSH_WQM:
8626 ++ctx->bc->stack.push_wqm;
8627 case FC_LOOP:
8628 ++ctx->bc->stack.loop;
8629 break;
8630 default:
8631 assert(0);
8632 }
8633
8634 callstack_update_max_depth(ctx, reason);
8635 }
8636
8637 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
8638 {
8639 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
8640
8641 sp->mid = realloc((void *)sp->mid,
8642 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
8643 sp->mid[sp->num_mid] = ctx->bc->cf_last;
8644 sp->num_mid++;
8645 }
8646
8647 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
8648 {
8649 ctx->bc->fc_sp++;
8650 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
8651 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
8652 }
8653
8654 static void fc_poplevel(struct r600_shader_ctx *ctx)
8655 {
8656 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
8657 free(sp->mid);
8658 sp->mid = NULL;
8659 sp->num_mid = 0;
8660 sp->start = NULL;
8661 sp->type = 0;
8662 ctx->bc->fc_sp--;
8663 }
8664
8665 #if 0
8666 static int emit_return(struct r600_shader_ctx *ctx)
8667 {
8668 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
8669 return 0;
8670 }
8671
8672 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
8673 {
8674
8675 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
8676 ctx->bc->cf_last->pop_count = pops;
8677 /* XXX work out offset */
8678 return 0;
8679 }
8680
8681 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
8682 {
8683 return 0;
8684 }
8685
8686 static void emit_testflag(struct r600_shader_ctx *ctx)
8687 {
8688
8689 }
8690
8691 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
8692 {
8693 emit_testflag(ctx);
8694 emit_jump_to_offset(ctx, 1, 4);
8695 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
8696 pops(ctx, ifidx + 1);
8697 emit_return(ctx);
8698 }
8699
8700 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
8701 {
8702 emit_testflag(ctx);
8703
8704 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8705 ctx->bc->cf_last->pop_count = 1;
8706
8707 fc_set_mid(ctx, fc_sp);
8708
8709 pops(ctx, 1);
8710 }
8711 #endif
8712
8713 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
8714 {
8715 int alu_type = CF_OP_ALU_PUSH_BEFORE;
8716
8717 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
8718 * LOOP_STARTxxx for nested loops may put the branch stack into a state
8719 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
8720 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
8721 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
8722 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
8723 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8724 alu_type = CF_OP_ALU;
8725 }
8726
8727 emit_logic_pred(ctx, opcode, alu_type);
8728
8729 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
8730
8731 fc_pushlevel(ctx, FC_IF);
8732
8733 callstack_push(ctx, FC_PUSH_VPM);
8734 return 0;
8735 }
8736
8737 static int tgsi_if(struct r600_shader_ctx *ctx)
8738 {
8739 return emit_if(ctx, ALU_OP2_PRED_SETNE);
8740 }
8741
8742 static int tgsi_uif(struct r600_shader_ctx *ctx)
8743 {
8744 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
8745 }
8746
8747 static int tgsi_else(struct r600_shader_ctx *ctx)
8748 {
8749 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
8750 ctx->bc->cf_last->pop_count = 1;
8751
8752 fc_set_mid(ctx, ctx->bc->fc_sp);
8753 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
8754 return 0;
8755 }
8756
8757 static int tgsi_endif(struct r600_shader_ctx *ctx)
8758 {
8759 pops(ctx, 1);
8760 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
8761 R600_ERR("if/endif unbalanced in shader\n");
8762 return -1;
8763 }
8764
8765 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
8766 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
8767 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
8768 } else {
8769 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
8770 }
8771 fc_poplevel(ctx);
8772
8773 callstack_pop(ctx, FC_PUSH_VPM);
8774 return 0;
8775 }
8776
8777 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
8778 {
8779 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
8780 * limited to 4096 iterations, like the other LOOP_* instructions. */
8781 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
8782
8783 fc_pushlevel(ctx, FC_LOOP);
8784
8785 /* check stack depth */
8786 callstack_push(ctx, FC_LOOP);
8787 return 0;
8788 }
8789
8790 static int tgsi_endloop(struct r600_shader_ctx *ctx)
8791 {
8792 unsigned i;
8793
8794 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
8795
8796 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
8797 R600_ERR("loop/endloop in shader code are not paired.\n");
8798 return -EINVAL;
8799 }
8800
8801 /* fixup loop pointers - from r600isa
8802 LOOP END points to CF after LOOP START,
8803 LOOP START point to CF after LOOP END
8804 BRK/CONT point to LOOP END CF
8805 */
8806 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
8807
8808 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
8809
8810 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
8811 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
8812 }
8813 /* XXX add LOOPRET support */
8814 fc_poplevel(ctx);
8815 callstack_pop(ctx, FC_LOOP);
8816 return 0;
8817 }
8818
8819 static int tgsi_loop_breakc(struct r600_shader_ctx *ctx)
8820 {
8821 int r;
8822 unsigned int fscp;
8823
8824 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
8825 {
8826 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
8827 break;
8828 }
8829 if (fscp == 0) {
8830 R600_ERR("BREAKC not inside loop/endloop pair\n");
8831 return -EINVAL;
8832 }
8833
8834 if (ctx->bc->chip_class == EVERGREEN &&
8835 ctx->bc->family != CHIP_CYPRESS &&
8836 ctx->bc->family != CHIP_JUNIPER) {
8837 /* HW bug: ALU_BREAK does not save the active mask correctly */
8838 r = tgsi_uif(ctx);
8839 if (r)
8840 return r;
8841
8842 r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_BREAK);
8843 if (r)
8844 return r;
8845 fc_set_mid(ctx, fscp);
8846
8847 return tgsi_endif(ctx);
8848 } else {
8849 r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
8850 if (r)
8851 return r;
8852 fc_set_mid(ctx, fscp);
8853 }
8854
8855 return 0;
8856 }
8857
8858 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
8859 {
8860 unsigned int fscp;
8861
8862 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
8863 {
8864 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
8865 break;
8866 }
8867
8868 if (fscp == 0) {
8869 R600_ERR("Break not inside loop/endloop pair\n");
8870 return -EINVAL;
8871 }
8872
8873 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8874
8875 fc_set_mid(ctx, fscp);
8876
8877 return 0;
8878 }
8879
8880 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
8881 {
8882 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8883 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
8884 int r;
8885
8886 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8887 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
8888
8889 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8890 if (!r) {
8891 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
8892 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8893 return emit_inc_ring_offset(ctx, stream, TRUE);
8894 }
8895 return r;
8896 }
8897
8898 static int tgsi_umad(struct r600_shader_ctx *ctx)
8899 {
8900 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8901 struct r600_bytecode_alu alu;
8902 int i, j, k, r;
8903 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8904
8905 /* src0 * src1 */
8906 for (i = 0; i < lasti + 1; i++) {
8907 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8908 continue;
8909
8910 if (ctx->bc->chip_class == CAYMAN) {
8911 for (j = 0 ; j < 4; j++) {
8912 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8913
8914 alu.op = ALU_OP2_MULLO_UINT;
8915 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
8916 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
8917 }
8918 alu.dst.chan = j;
8919 alu.dst.sel = ctx->temp_reg;
8920 alu.dst.write = (j == i);
8921 if (j == 3)
8922 alu.last = 1;
8923 r = r600_bytecode_add_alu(ctx->bc, &alu);
8924 if (r)
8925 return r;
8926 }
8927 } else {
8928 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8929
8930 alu.dst.chan = i;
8931 alu.dst.sel = ctx->temp_reg;
8932 alu.dst.write = 1;
8933
8934 alu.op = ALU_OP2_MULLO_UINT;
8935 for (j = 0; j < 2; j++) {
8936 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
8937 }
8938
8939 alu.last = 1;
8940 r = r600_bytecode_add_alu(ctx->bc, &alu);
8941 if (r)
8942 return r;
8943 }
8944 }
8945
8946
8947 for (i = 0; i < lasti + 1; i++) {
8948 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8949 continue;
8950
8951 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8952 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8953
8954 alu.op = ALU_OP2_ADD_INT;
8955
8956 alu.src[0].sel = ctx->temp_reg;
8957 alu.src[0].chan = i;
8958
8959 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8960 if (i == lasti) {
8961 alu.last = 1;
8962 }
8963 r = r600_bytecode_add_alu(ctx->bc, &alu);
8964 if (r)
8965 return r;
8966 }
8967 return 0;
8968 }
8969
8970 static int tgsi_pk2h(struct r600_shader_ctx *ctx)
8971 {
8972 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8973 struct r600_bytecode_alu alu;
8974 int r, i;
8975 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8976
8977 /* temp.xy = f32_to_f16(src) */
8978 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8979 alu.op = ALU_OP1_FLT32_TO_FLT16;
8980 alu.dst.chan = 0;
8981 alu.dst.sel = ctx->temp_reg;
8982 alu.dst.write = 1;
8983 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8984 r = r600_bytecode_add_alu(ctx->bc, &alu);
8985 if (r)
8986 return r;
8987 alu.dst.chan = 1;
8988 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
8989 alu.last = 1;
8990 r = r600_bytecode_add_alu(ctx->bc, &alu);
8991 if (r)
8992 return r;
8993
8994 /* dst.x = temp.y * 0x10000 + temp.x */
8995 for (i = 0; i < lasti + 1; i++) {
8996 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8997 continue;
8998
8999 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9000 alu.op = ALU_OP3_MULADD_UINT24;
9001 alu.is_op3 = 1;
9002 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9003 alu.last = i == lasti;
9004 alu.src[0].sel = ctx->temp_reg;
9005 alu.src[0].chan = 1;
9006 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9007 alu.src[1].value = 0x10000;
9008 alu.src[2].sel = ctx->temp_reg;
9009 alu.src[2].chan = 0;
9010 r = r600_bytecode_add_alu(ctx->bc, &alu);
9011 if (r)
9012 return r;
9013 }
9014
9015 return 0;
9016 }
9017
9018 static int tgsi_up2h(struct r600_shader_ctx *ctx)
9019 {
9020 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9021 struct r600_bytecode_alu alu;
9022 int r, i;
9023 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9024
9025 /* temp.x = src.x */
9026 /* note: no need to mask out the high bits */
9027 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9028 alu.op = ALU_OP1_MOV;
9029 alu.dst.chan = 0;
9030 alu.dst.sel = ctx->temp_reg;
9031 alu.dst.write = 1;
9032 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9033 r = r600_bytecode_add_alu(ctx->bc, &alu);
9034 if (r)
9035 return r;
9036
9037 /* temp.y = src.x >> 16 */
9038 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9039 alu.op = ALU_OP2_LSHR_INT;
9040 alu.dst.chan = 1;
9041 alu.dst.sel = ctx->temp_reg;
9042 alu.dst.write = 1;
9043 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9044 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9045 alu.src[1].value = 16;
9046 alu.last = 1;
9047 r = r600_bytecode_add_alu(ctx->bc, &alu);
9048 if (r)
9049 return r;
9050
9051 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
9052 for (i = 0; i < lasti + 1; i++) {
9053 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9054 continue;
9055 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9056 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9057 alu.op = ALU_OP1_FLT16_TO_FLT32;
9058 alu.src[0].sel = ctx->temp_reg;
9059 alu.src[0].chan = i % 2;
9060 alu.last = i == lasti;
9061 r = r600_bytecode_add_alu(ctx->bc, &alu);
9062 if (r)
9063 return r;
9064 }
9065
9066 return 0;
9067 }
9068
9069 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
9070 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
9071 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9072 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9073
9074 /* XXX:
9075 * For state trackers other than OpenGL, we'll want to use
9076 * _RECIP_IEEE instead.
9077 */
9078 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
9079
9080 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
9081 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9082 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9083 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
9084 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9085 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
9086 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
9087 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9088 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9089 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9090 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9091 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9092 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
9093 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9094 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
9095 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9096 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
9097 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9098 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9099 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9100 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
9101 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9102 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9103 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9104 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9105 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9106 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
9107 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9108 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9109 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9110 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
9111 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9112 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9113 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9114 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9115 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
9116 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9117 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9118 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9119 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9120 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9121 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9122 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9123 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9124 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9125 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9126 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9127 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9128 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9129 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9130 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9131 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9132 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9133 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9134 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9135 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9136 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
9137 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9138 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9139 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9140 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9141 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9142 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
9143 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9144 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9145 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9146 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
9147 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9148 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9149 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9150 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9151 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9152 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9153 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9154 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9155 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9156 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
9157 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
9158 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9159 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9160 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9161 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9162 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
9163 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9164 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9165 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9166 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9167 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9168 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
9169 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9170 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9171 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9172 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9173 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9174 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9175 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9176 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9177 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9178 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9179 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9180 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9181 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9182 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9183 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9184 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9185 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9186 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9187 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9188 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
9189 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9190 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_loop_breakc},
9191 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9192 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9193 [TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
9194 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
9195 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9196 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9197 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9198 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9199 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9200 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
9201 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9202 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
9203 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9204 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9205 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9206 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9207 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9208 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9209 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9210 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9211 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9212 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9213 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
9214 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9215 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
9216 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9217 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9218 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9219 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9220 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9221 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9222 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9223 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9224 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9225 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9226 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9227 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9228 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9229 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9230 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9231 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9232 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
9233 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9234 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9235 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9236 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9237 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9238 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9239 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9240 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9241 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
9242 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9243 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9244 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9245 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9246 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9247 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9248 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9249 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9250 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9251 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9252 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9253 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9254 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9255 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9256 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9257 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
9258 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
9259 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
9260 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
9261 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
9262 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
9263 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
9264 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
9265 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
9266 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
9267 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
9268 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
9269 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
9270 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9271 };
9272
9273 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
9274 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9275 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9276 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9277 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
9278 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
9279 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9280 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9281 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
9282 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9283 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
9284 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
9285 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9286 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9287 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9288 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9289 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9290 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
9291 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9292 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
9293 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9294 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
9295 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9296 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9297 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9298 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
9299 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9300 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9301 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9302 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9303 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9304 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
9305 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9306 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9307 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9308 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
9309 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9310 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9311 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9312 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9313 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
9314 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9315 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9316 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9317 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9318 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9319 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9320 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9321 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9322 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9323 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9324 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9325 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9326 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9327 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9328 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
9329 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9330 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9331 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9332 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9333 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9334 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9335 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9336 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9337 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9338 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9339 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9340 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
9341 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9342 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9343 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9344 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
9345 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9346 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9347 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9348 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9349 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9350 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9351 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9352 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9353 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9354 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
9355 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
9356 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9357 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9358 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9359 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9360 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9361 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9362 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9363 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9364 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9365 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9366 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
9367 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9368 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9369 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9370 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9371 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9372 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9373 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9374 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9375 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9376 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9377 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9378 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9379 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9380 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9381 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9382 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9383 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9384 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9385 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9386 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
9387 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9388 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
9389 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9390 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9391 /* Refer below for TGSI_OPCODE_DFMA */
9392 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
9393 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9394 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9395 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9396 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9397 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9398 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9399 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9400 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
9401 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9402 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9403 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9404 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9405 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9406 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9407 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9408 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9409 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9410 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9411 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9412 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9413 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9414 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9415 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9416 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9417 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9418 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9419 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9420 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9421 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9422 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9423 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9424 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9425 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9426 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9427 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9428 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9429 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9430 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9431 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9432 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9433 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9434 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9435 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9436 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9437 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9438 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9439 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9440 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9441 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9442 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9443 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9444 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9445 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9446 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9447 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9448 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9449 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9450 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9451 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9452 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9453 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9454 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9455 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9456 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9457 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
9458 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
9459 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9460 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9461 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9462 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9463 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9464 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9465 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9466 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9467 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9468 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9469 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9470 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9471 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9472 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9473 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9474 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
9475 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9476 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9477 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9478 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9479 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9480 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9481 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9482 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9483 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9484 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
9485 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9486 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9487 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9488 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9489 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9490 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9491 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9492 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9493 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9494 };
9495
9496 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
9497 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9498 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9499 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9500 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
9501 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
9502 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9503 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9504 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
9505 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9506 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
9507 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
9508 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9509 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9510 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9511 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9512 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9513 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
9514 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9515 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
9516 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
9517 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
9518 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9519 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9520 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9521 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
9522 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9523 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9524 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
9525 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
9526 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
9527 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
9528 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9529 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9530 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9531 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
9532 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
9533 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9534 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9535 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9536 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
9537 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9538 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9539 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9540 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9541 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9542 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9543 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9544 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
9545 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9546 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9547 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9548 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9549 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9550 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9551 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
9552 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9553 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9554 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9555 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9556 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9557 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9558 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9559 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9560 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9561 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9562 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9563 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
9564 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9565 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9566 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9567 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
9568 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9569 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9570 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9571 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9572 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9573 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9574 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9575 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9576 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9577 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
9578 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
9579 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9580 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
9581 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9582 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9583 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9584 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9585 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9586 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9587 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9588 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9589 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
9590 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9591 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9592 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9593 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9594 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9595 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9596 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9597 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9598 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9599 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9600 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9601 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9602 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9603 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9604 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9605 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9606 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9607 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9608 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9609 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
9610 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9611 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
9612 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9613 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9614 /* Refer below for TGSI_OPCODE_DFMA */
9615 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
9616 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9617 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9618 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9619 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9620 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9621 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9622 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9623 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
9624 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
9625 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9626 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9627 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9628 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9629 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9630 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9631 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
9632 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9633 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9634 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9635 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9636 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9637 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9638 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9639 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9640 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9641 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9642 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9643 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9644 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9645 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9646 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9647 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9648 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9649 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9650 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9651 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9652 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9653 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9654 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9655 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9656 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9657 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9658 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9659 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9660 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9661 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9662 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9663 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9664 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9665 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9666 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9667 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9668 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9669 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9670 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9671 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9672 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9673 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9674 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9675 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9676 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
9677 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
9678 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9679 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9680 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
9681 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
9682 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9683 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9684 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9685 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9686 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9687 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9688 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9689 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9690 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9691 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9692 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9693 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9694 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9695 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9696 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9697 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
9698 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9699 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9700 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9701 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9702 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9703 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9704 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9705 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9706 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9707 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
9708 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9709 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9710 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9711 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9712 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9713 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9714 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9715 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9716 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9717 };