2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_screen.h"
29 #include "r600_context.h"
30 #include "r600_shader.h"
38 struct r600_shader_tgsi_instruction
;
40 struct r600_shader_ctx
{
41 struct tgsi_shader_info info
;
42 struct tgsi_parse_context parse
;
43 const struct tgsi_token
*tokens
;
45 unsigned file_offset
[TGSI_FILE_COUNT
];
47 struct r600_shader_tgsi_instruction
*inst_info
;
49 struct r600_shader
*shader
;
53 struct r600_shader_tgsi_instruction
{
57 int (*process
)(struct r600_shader_ctx
*ctx
);
60 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[];
61 static int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
);
63 static int r600_shader_update(struct pipe_context
*ctx
, struct r600_shader
*shader
)
65 struct r600_context
*rctx
= r600_context(ctx
);
66 const struct util_format_description
*desc
;
67 enum pipe_format resource_format
[160];
68 unsigned i
, nresources
= 0;
69 struct r600_bc
*bc
= &shader
->bc
;
70 struct r600_bc_cf
*cf
;
71 struct r600_bc_vtx
*vtx
;
73 if (shader
->processor_type
!= TGSI_PROCESSOR_VERTEX
)
75 for (i
= 0; i
< rctx
->vertex_elements
->count
; i
++) {
76 resource_format
[nresources
++] = rctx
->vertex_elements
->elements
[i
].src_format
;
78 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
80 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
81 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
82 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
83 desc
= util_format_description(resource_format
[vtx
->buffer_id
]);
85 R600_ERR("unknown format %d\n", resource_format
[vtx
->buffer_id
]);
88 vtx
->dst_sel_x
= desc
->swizzle
[0];
89 vtx
->dst_sel_y
= desc
->swizzle
[1];
90 vtx
->dst_sel_z
= desc
->swizzle
[2];
91 vtx
->dst_sel_w
= desc
->swizzle
[3];
98 return r600_bc_build(&shader
->bc
);
101 int r600_pipe_shader_create(struct pipe_context
*ctx
,
102 struct r600_context_state
*rpshader
,
103 const struct tgsi_token
*tokens
)
105 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
108 //fprintf(stderr, "--------------------------------------------------------------\n");
109 //tgsi_dump(tokens, 0);
110 if (rpshader
== NULL
)
112 rpshader
->shader
.family
= radeon_get_family(rscreen
->rw
);
113 r
= r600_shader_from_tgsi(tokens
, &rpshader
->shader
);
115 R600_ERR("translation from TGSI failed !\n");
118 r
= r600_bc_build(&rpshader
->shader
.bc
);
120 R600_ERR("building bytecode failed !\n");
123 //fprintf(stderr, "______________________________________________________________\n");
127 static int r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
129 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
130 struct r600_shader
*rshader
= &rpshader
->shader
;
131 struct radeon_state
*state
;
134 rpshader
->rstate
= radeon_state_decref(rpshader
->rstate
);
135 state
= radeon_state(rscreen
->rw
, R600_VS_SHADER_TYPE
, R600_VS_SHADER
);
138 for (i
= 0; i
< 10; i
++) {
139 state
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_0
+ i
] = 0;
141 /* so far never got proper semantic id from tgsi */
142 for (i
= 0; i
< 32; i
++) {
143 tmp
= i
<< ((i
& 3) * 8);
144 state
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_0
+ i
/ 4] |= tmp
;
146 state
->states
[R600_VS_SHADER__SPI_VS_OUT_CONFIG
] = S_0286C4_VS_EXPORT_COUNT(rshader
->noutput
- 2);
147 state
->states
[R600_VS_SHADER__SQ_PGM_RESOURCES_VS
] = S_028868_NUM_GPRS(rshader
->bc
.ngpr
);
148 rpshader
->rstate
= state
;
149 rpshader
->rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
150 rpshader
->rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
151 rpshader
->rstate
->nbo
= 2;
152 rpshader
->rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
153 rpshader
->rstate
->placement
[2] = RADEON_GEM_DOMAIN_GTT
;
154 return radeon_state_pm4(state
);
157 static int r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
159 const struct pipe_rasterizer_state
*rasterizer
;
160 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
161 struct r600_shader
*rshader
= &rpshader
->shader
;
162 struct r600_context
*rctx
= r600_context(ctx
);
163 struct radeon_state
*state
;
164 unsigned i
, tmp
, exports_ps
, num_cout
;
166 rasterizer
= &rctx
->rasterizer
->state
.rasterizer
;
167 rpshader
->rstate
= radeon_state_decref(rpshader
->rstate
);
168 state
= radeon_state(rscreen
->rw
, R600_PS_SHADER_TYPE
, R600_PS_SHADER
);
171 for (i
= 0; i
< rshader
->ninput
; i
++) {
172 tmp
= S_028644_SEMANTIC(i
);
173 tmp
|= S_028644_SEL_CENTROID(1);
174 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
||
175 rshader
->input
[i
].name
== TGSI_SEMANTIC_BCOLOR
) {
176 tmp
|= S_028644_FLAT_SHADE(rshader
->flat_shade
);
178 if (rasterizer
->sprite_coord_enable
& (1 << i
)) {
179 tmp
|= S_028644_PT_SPRITE_TEX(1);
181 state
->states
[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0
+ i
] = tmp
;
186 for (i
= 0; i
< rshader
->noutput
; i
++) {
187 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
189 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
190 exports_ps
|= (1 << (num_cout
+1));
195 /* always at least export 1 component per pixel */
198 state
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_0
] = S_0286CC_NUM_INTERP(rshader
->ninput
) |
199 S_0286CC_PERSP_GRADIENT_ENA(1);
200 state
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_1
] = 0x00000000;
201 state
->states
[R600_PS_SHADER__SQ_PGM_RESOURCES_PS
] = S_028868_NUM_GPRS(rshader
->bc
.ngpr
);
202 state
->states
[R600_PS_SHADER__SQ_PGM_EXPORTS_PS
] = exports_ps
;
203 rpshader
->rstate
= state
;
204 rpshader
->rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
205 rpshader
->rstate
->nbo
= 1;
206 rpshader
->rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
207 return radeon_state_pm4(state
);
210 static int r600_pipe_shader(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
212 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
213 struct r600_context
*rctx
= r600_context(ctx
);
214 struct r600_shader
*rshader
= &rpshader
->shader
;
217 /* copy new shader */
218 radeon_bo_decref(rscreen
->rw
, rpshader
->bo
);
220 rpshader
->bo
= radeon_bo(rscreen
->rw
, 0, rshader
->bc
.ndw
* 4,
222 if (rpshader
->bo
== NULL
) {
225 radeon_bo_map(rscreen
->rw
, rpshader
->bo
);
226 memcpy(rpshader
->bo
->data
, rshader
->bc
.bytecode
, rshader
->bc
.ndw
* 4);
227 radeon_bo_unmap(rscreen
->rw
, rpshader
->bo
);
229 rshader
->flat_shade
= rctx
->flat_shade
;
230 switch (rshader
->processor_type
) {
231 case TGSI_PROCESSOR_VERTEX
:
232 r
= r600_pipe_shader_vs(ctx
, rpshader
);
234 case TGSI_PROCESSOR_FRAGMENT
:
235 r
= r600_pipe_shader_ps(ctx
, rpshader
);
244 int r600_pipe_shader_update(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
246 struct r600_context
*rctx
= r600_context(ctx
);
249 if (rpshader
== NULL
)
251 /* there should be enough input */
252 if (rctx
->vertex_elements
->count
< rpshader
->shader
.bc
.nresource
) {
253 R600_ERR("%d resources provided, expecting %d\n",
254 rctx
->vertex_elements
->count
, rpshader
->shader
.bc
.nresource
);
257 r
= r600_shader_update(ctx
, &rpshader
->shader
);
260 return r600_pipe_shader(ctx
, rpshader
);
263 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
265 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
268 if (i
->Instruction
.NumDstRegs
> 1) {
269 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
272 if (i
->Instruction
.Predicate
) {
273 R600_ERR("predicate unsupported\n");
276 if (i
->Instruction
.Label
) {
277 R600_ERR("label unsupported\n");
280 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
281 if (i
->Src
[j
].Register
.Indirect
||
282 i
->Src
[j
].Register
.Dimension
||
283 i
->Src
[j
].Register
.Absolute
) {
284 R600_ERR("unsupported src (indirect|dimension|absolute)\n");
288 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
289 if (i
->Dst
[j
].Register
.Indirect
|| i
->Dst
[j
].Register
.Dimension
) {
290 R600_ERR("unsupported dst (indirect|dimension)\n");
297 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
299 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
300 struct r600_bc_vtx vtx
;
304 switch (d
->Declaration
.File
) {
305 case TGSI_FILE_INPUT
:
306 i
= ctx
->shader
->ninput
++;
307 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
308 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
;
309 ctx
->shader
->input
[i
].interpolate
= d
->Declaration
.Interpolate
;
310 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + i
;
311 if (ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
312 /* turn input into fetch */
313 memset(&vtx
, 0, sizeof(struct r600_bc_vtx
));
317 /* register containing the index into the buffer */
320 vtx
.mega_fetch_count
= 0x1F;
321 vtx
.dst_gpr
= ctx
->shader
->input
[i
].gpr
;
326 r
= r600_bc_add_vtx(ctx
->bc
, &vtx
);
331 case TGSI_FILE_OUTPUT
:
332 i
= ctx
->shader
->noutput
++;
333 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
334 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
;
335 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + i
;
336 ctx
->shader
->output
[i
].interpolate
= d
->Declaration
.Interpolate
;
338 case TGSI_FILE_CONSTANT
:
339 case TGSI_FILE_TEMPORARY
:
340 case TGSI_FILE_SAMPLER
:
343 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
349 int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
)
351 struct tgsi_full_immediate
*immediate
;
352 struct r600_shader_ctx ctx
;
353 struct r600_bc_output output
[32];
354 unsigned output_done
, noutput
;
358 ctx
.bc
= &shader
->bc
;
360 r
= r600_bc_init(ctx
.bc
, shader
->family
);
364 tgsi_scan_shader(tokens
, &ctx
.info
);
365 tgsi_parse_init(&ctx
.parse
, tokens
);
366 ctx
.type
= ctx
.parse
.FullHeader
.Processor
.Processor
;
367 shader
->processor_type
= ctx
.type
;
369 /* register allocations */
370 /* Values [0,127] correspond to GPR[0..127].
371 * Values [128,159] correspond to constant buffer bank 0
372 * Values [160,191] correspond to constant buffer bank 1
373 * Values [256,511] correspond to cfile constants c[0..255].
374 * Other special values are shown in the list below.
375 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
376 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
377 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
378 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
379 * 248 SQ_ALU_SRC_0: special constant 0.0.
380 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
381 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
382 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
383 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
384 * 253 SQ_ALU_SRC_LITERAL: literal constant.
385 * 254 SQ_ALU_SRC_PV: previous vector result.
386 * 255 SQ_ALU_SRC_PS: previous scalar result.
388 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
389 ctx
.file_offset
[i
] = 0;
391 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
392 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
394 ctx
.file_offset
[TGSI_FILE_OUTPUT
] = ctx
.file_offset
[TGSI_FILE_INPUT
] +
395 ctx
.info
.file_count
[TGSI_FILE_INPUT
];
396 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
397 ctx
.info
.file_count
[TGSI_FILE_OUTPUT
];
398 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 256;
399 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = 253;
400 ctx
.temp_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
401 ctx
.info
.file_count
[TGSI_FILE_TEMPORARY
];
403 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
404 tgsi_parse_token(&ctx
.parse
);
405 switch (ctx
.parse
.FullToken
.Token
.Type
) {
406 case TGSI_TOKEN_TYPE_IMMEDIATE
:
407 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
408 ctx
.value
[0] = immediate
->u
[0].Uint
;
409 ctx
.value
[1] = immediate
->u
[1].Uint
;
410 ctx
.value
[2] = immediate
->u
[2].Uint
;
411 ctx
.value
[3] = immediate
->u
[3].Uint
;
413 case TGSI_TOKEN_TYPE_DECLARATION
:
414 r
= tgsi_declaration(&ctx
);
418 case TGSI_TOKEN_TYPE_INSTRUCTION
:
419 r
= tgsi_is_supported(&ctx
);
422 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
423 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
424 r
= ctx
.inst_info
->process(&ctx
);
427 r
= r600_bc_add_literal(ctx
.bc
, ctx
.value
);
432 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
438 noutput
= shader
->noutput
;
439 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
440 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
441 output
[i
].gpr
= shader
->output
[i
].gpr
;
442 output
[i
].elem_size
= 3;
443 output
[i
].swizzle_x
= 0;
444 output
[i
].swizzle_y
= 1;
445 output
[i
].swizzle_z
= 2;
446 output
[i
].swizzle_w
= 3;
447 output
[i
].barrier
= 1;
448 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
449 output
[i
].array_base
= i
- pos0
;
450 output
[i
].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
;
452 case TGSI_PROCESSOR_VERTEX
:
453 if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
454 output
[i
].array_base
= 60;
455 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
456 /* position doesn't count in array_base */
459 if (shader
->output
[i
].name
== TGSI_SEMANTIC_PSIZE
) {
460 output
[i
].array_base
= 61;
461 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
462 /* position doesn't count in array_base */
466 case TGSI_PROCESSOR_FRAGMENT
:
467 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
468 output
[i
].array_base
= shader
->output
[i
].sid
;
469 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
470 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
471 output
[i
].array_base
= 61;
472 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
474 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
480 R600_ERR("unsupported processor type %d\n", ctx
.type
);
485 /* add fake param output for vertex shader if no param is exported */
486 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
487 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
488 if (output
[i
].type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
) {
494 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
496 output
[i
].elem_size
= 3;
497 output
[i
].swizzle_x
= 0;
498 output
[i
].swizzle_y
= 1;
499 output
[i
].swizzle_z
= 2;
500 output
[i
].swizzle_w
= 3;
501 output
[i
].barrier
= 1;
502 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
503 output
[i
].array_base
= 0;
504 output
[i
].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
;
508 /* add fake pixel export */
509 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& !noutput
) {
510 memset(&output
[0], 0, sizeof(struct r600_bc_output
));
512 output
[0].elem_size
= 3;
513 output
[0].swizzle_x
= 7;
514 output
[0].swizzle_y
= 7;
515 output
[0].swizzle_z
= 7;
516 output
[0].swizzle_w
= 7;
517 output
[0].barrier
= 1;
518 output
[0].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
519 output
[0].array_base
= 0;
520 output
[0].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
;
523 /* set export done on last export of each type */
524 for (i
= noutput
- 1, output_done
= 0; i
>= 0; i
--) {
525 if (i
== (noutput
- 1)) {
526 output
[i
].end_of_program
= 1;
528 if (!(output_done
& (1 << output
[i
].type
))) {
529 output_done
|= (1 << output
[i
].type
);
530 output
[i
].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
;
533 /* add output to bytecode */
534 for (i
= 0; i
< noutput
; i
++) {
535 r
= r600_bc_add_output(ctx
.bc
, &output
[i
]);
539 tgsi_parse_free(&ctx
.parse
);
542 tgsi_parse_free(&ctx
.parse
);
546 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
548 R600_ERR("%d tgsi opcode unsupported\n", ctx
->inst_info
->tgsi_opcode
);
552 static int tgsi_end(struct r600_shader_ctx
*ctx
)
557 static int tgsi_src(struct r600_shader_ctx
*ctx
,
558 const struct tgsi_full_src_register
*tgsi_src
,
559 struct r600_bc_alu_src
*r600_src
)
561 memset(r600_src
, 0, sizeof(struct r600_bc_alu_src
));
562 r600_src
->sel
= tgsi_src
->Register
.Index
;
563 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
566 r600_src
->neg
= tgsi_src
->Register
.Negate
;
567 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
571 static int tgsi_dst(struct r600_shader_ctx
*ctx
,
572 const struct tgsi_full_dst_register
*tgsi_dst
,
574 struct r600_bc_alu_dst
*r600_dst
)
576 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
578 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
579 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
580 r600_dst
->chan
= swizzle
;
582 if (inst
->Instruction
.Saturate
) {
588 static unsigned tgsi_chan(const struct tgsi_full_src_register
*tgsi_src
, unsigned swizzle
)
592 return tgsi_src
->Register
.SwizzleX
;
594 return tgsi_src
->Register
.SwizzleY
;
596 return tgsi_src
->Register
.SwizzleZ
;
598 return tgsi_src
->Register
.SwizzleW
;
604 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
, struct r600_bc_alu_src r600_src
[3])
606 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
607 struct r600_bc_alu alu
;
608 int i
, j
, k
, nconst
, r
;
610 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
611 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
614 r
= tgsi_src(ctx
, &inst
->Src
[i
], &r600_src
[i
]);
619 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
620 if (inst
->Src
[j
].Register
.File
== TGSI_FILE_CONSTANT
&& j
> 0) {
621 for (k
= 0; k
< 4; k
++) {
622 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
623 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
624 alu
.src
[0].sel
= r600_src
[0].sel
;
626 alu
.dst
.sel
= ctx
->temp_reg
+ j
;
631 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
635 r600_src
[0].sel
= ctx
->temp_reg
+ j
;
642 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
644 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
645 struct r600_bc_alu_src r600_src
[3];
646 struct r600_bc_alu alu
;
649 r
= tgsi_split_constant(ctx
, r600_src
);
652 for (i
= 0; i
< 4; i
++) {
653 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
654 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
655 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
658 alu
.inst
= ctx
->inst_info
->r600_opcode
;
659 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
660 alu
.src
[j
] = r600_src
[j
];
661 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
663 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
667 /* handle some special cases */
668 switch (ctx
->inst_info
->tgsi_opcode
) {
669 case TGSI_OPCODE_SUB
:
672 case TGSI_OPCODE_ABS
:
681 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
689 * r600 - trunc to -PI..PI range
690 * r700 - normalize by dividing by 2PI
693 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
695 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
696 struct r600_bc_alu_src r600_src
[3];
697 struct r600_bc_alu alu
;
699 uint32_t lit_vals
[4];
701 memset(lit_vals
, 0, 4*4);
702 r
= tgsi_split_constant(ctx
, r600_src
);
705 lit_vals
[0] = fui(1.0 /(3.1415926535 * 2));
706 lit_vals
[1] = fui(0.5f
);
708 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
709 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
713 alu
.dst
.sel
= ctx
->temp_reg
;
716 alu
.src
[0] = r600_src
[0];
717 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
719 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
721 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
724 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
727 r
= r600_bc_add_literal(ctx
->bc
, lit_vals
);
731 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
732 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
;
735 alu
.dst
.sel
= ctx
->temp_reg
;
738 alu
.src
[0].sel
= ctx
->temp_reg
;
741 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
745 if (ctx
->bc
->chiprev
== 0) {
746 lit_vals
[0] = fui(3.1415926535897f
* 2.0f
);
747 lit_vals
[1] = fui(-3.1415926535897f
);
749 lit_vals
[0] = fui(1.0f
);
750 lit_vals
[1] = fui(-0.5f
);
753 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
754 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
758 alu
.dst
.sel
= ctx
->temp_reg
;
761 alu
.src
[0].sel
= ctx
->temp_reg
;
764 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
766 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
769 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
772 r
= r600_bc_add_literal(ctx
->bc
, lit_vals
);
776 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
777 alu
.inst
= ctx
->inst_info
->r600_opcode
;
779 alu
.dst
.sel
= ctx
->temp_reg
;
782 alu
.src
[0].sel
= ctx
->temp_reg
;
785 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
789 /* replicate result */
790 for (i
= 0; i
< 4; i
++) {
791 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
792 alu
.src
[0].sel
= ctx
->temp_reg
;
793 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
795 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
798 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
801 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
808 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
810 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
811 struct r600_bc_alu alu
;
814 for (i
= 0; i
< 4; i
++) {
815 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
816 alu
.inst
= ctx
->inst_info
->r600_opcode
;
818 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
819 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[1]);
822 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
826 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
833 static int tgsi_slt(struct r600_shader_ctx
*ctx
)
835 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
836 struct r600_bc_alu_src r600_src
[3];
837 struct r600_bc_alu alu
;
840 r
= tgsi_split_constant(ctx
, r600_src
);
843 for (i
= 0; i
< 4; i
++) {
844 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
845 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
846 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
849 alu
.inst
= ctx
->inst_info
->r600_opcode
;
850 alu
.src
[1] = r600_src
[0];
851 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
852 alu
.src
[0] = r600_src
[1];
853 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[1], i
);
854 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
861 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
868 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
870 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
871 struct r600_bc_alu alu
;
875 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
876 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
877 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
; /*1.0*/
879 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
882 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
883 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
887 /* dst.y = max(src.x, 0.0) */
888 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
889 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
;
890 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
893 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
894 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], 0);
895 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
898 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
899 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
903 /* dst.z = NOP - fill Z slot */
904 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
905 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
907 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
912 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
913 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
914 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
916 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
919 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
921 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
925 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
930 /* dst.z = log(src.y) */
931 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
932 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
;
933 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
936 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
937 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
941 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
948 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
949 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
950 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
;
951 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
954 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 3);
955 alu
.src
[1].sel
= sel
;
956 alu
.src
[1].chan
= chan
;
957 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[2]);
960 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[0], 0);
961 alu
.dst
.sel
= ctx
->temp_reg
;
966 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
970 /* dst.z = exp(tmp.x) */
971 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
972 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
;
973 alu
.src
[0].sel
= ctx
->temp_reg
;
975 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
979 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
986 static int tgsi_trans(struct r600_shader_ctx
*ctx
)
988 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
989 struct r600_bc_alu alu
;
992 for (i
= 0; i
< 4; i
++) {
993 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
994 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
995 alu
.inst
= ctx
->inst_info
->r600_opcode
;
996 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
997 r
= tgsi_src(ctx
, &inst
->Src
[j
], &alu
.src
[j
]);
1000 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
1002 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1006 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1014 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
)
1016 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1017 struct r600_bc_alu alu
;
1020 for (i
= 0; i
< 4; i
++) {
1021 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1022 alu
.src
[0].sel
= ctx
->temp_reg
;
1023 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1025 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1028 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1031 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1038 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
1040 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1041 struct r600_bc_alu alu
;
1044 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1045 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1046 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1047 r
= tgsi_src(ctx
, &inst
->Src
[i
], &alu
.src
[i
]);
1050 alu
.src
[i
].chan
= tgsi_chan(&inst
->Src
[i
], 0);
1052 alu
.dst
.sel
= ctx
->temp_reg
;
1055 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1058 /* replicate result */
1059 return tgsi_helper_tempx_replicate(ctx
);
1062 static int tgsi_pow(struct r600_shader_ctx
*ctx
)
1064 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1065 struct r600_bc_alu alu
;
1069 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1070 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
;
1071 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1074 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
1075 alu
.dst
.sel
= ctx
->temp_reg
;
1078 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1082 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1083 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE
;
1084 r
= tgsi_src(ctx
, &inst
->Src
[1], &alu
.src
[0]);
1087 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[1], 0);
1088 alu
.src
[1].sel
= ctx
->temp_reg
;
1089 alu
.dst
.sel
= ctx
->temp_reg
;
1092 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1095 /* POW(a,b) = EXP2(b * LOG2(a))*/
1096 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1097 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
;
1098 alu
.src
[0].sel
= ctx
->temp_reg
;
1099 alu
.dst
.sel
= ctx
->temp_reg
;
1102 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1105 return tgsi_helper_tempx_replicate(ctx
);
1108 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
1110 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1111 struct r600_bc_alu alu
;
1112 struct r600_bc_alu_src r600_src
[3];
1115 r
= tgsi_split_constant(ctx
, r600_src
);
1119 /* tmp = (src > 0 ? 1 : src) */
1120 for (i
= 0; i
< 4; i
++) {
1121 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1122 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
;
1124 alu
.dst
.sel
= ctx
->temp_reg
;
1127 alu
.src
[0] = r600_src
[0];
1128 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1130 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1132 alu
.src
[2] = r600_src
[0];
1133 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[0], i
);
1136 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1141 /* dst = (-tmp > 0 ? -1 : tmp) */
1142 for (i
= 0; i
< 4; i
++) {
1143 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1144 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
;
1146 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1150 alu
.src
[0].sel
= ctx
->temp_reg
;
1153 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1156 alu
.src
[2].sel
= ctx
->temp_reg
;
1161 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1168 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
1170 struct r600_bc_alu alu
;
1173 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1176 for (i
= 0; i
< 4; i
++) {
1177 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1178 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
1179 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
1182 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1183 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1186 alu
.src
[0].sel
= ctx
->temp_reg
;
1187 alu
.src
[0].chan
= i
;
1192 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1199 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
1201 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1202 struct r600_bc_alu_src r600_src
[3];
1203 struct r600_bc_alu alu
;
1206 r
= tgsi_split_constant(ctx
, r600_src
);
1209 /* do it in 2 step as op3 doesn't support writemask */
1210 for (i
= 0; i
< 4; i
++) {
1211 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1212 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1213 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1214 alu
.src
[j
] = r600_src
[j
];
1215 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
1217 alu
.dst
.sel
= ctx
->temp_reg
;
1224 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1228 return tgsi_helper_copy(ctx
, inst
);
1231 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
1233 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1234 struct r600_bc_alu_src r600_src
[3];
1235 struct r600_bc_alu alu
;
1238 r
= tgsi_split_constant(ctx
, r600_src
);
1241 for (i
= 0; i
< 4; i
++) {
1242 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1243 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1244 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1245 alu
.src
[j
] = r600_src
[j
];
1246 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
1248 alu
.dst
.sel
= ctx
->temp_reg
;
1251 /* handle some special cases */
1252 switch (ctx
->inst_info
->tgsi_opcode
) {
1253 case TGSI_OPCODE_DP2
:
1255 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1256 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1259 case TGSI_OPCODE_DP3
:
1261 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1262 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1271 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1275 return tgsi_helper_copy(ctx
, inst
);
1278 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
1280 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1281 struct r600_bc_tex tex
;
1282 struct r600_bc_alu alu
;
1286 src_gpr
= ctx
->file_offset
[inst
->Src
[0].Register
.File
] + inst
->Src
[0].Register
.Index
;
1288 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
1289 /* Add perspective divide */
1290 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1291 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
;
1292 alu
.src
[0].sel
= src_gpr
;
1293 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 3);
1294 alu
.dst
.sel
= ctx
->temp_reg
;
1298 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1302 for (i
= 0; i
< 3; i
++) {
1303 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1304 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
1305 alu
.src
[0].sel
= ctx
->temp_reg
;
1306 alu
.src
[0].chan
= 3;
1307 alu
.src
[1].sel
= src_gpr
;
1308 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1309 alu
.dst
.sel
= ctx
->temp_reg
;
1312 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1316 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1317 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1318 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1319 alu
.src
[0].chan
= 0;
1320 alu
.dst
.sel
= ctx
->temp_reg
;
1324 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1327 src_gpr
= ctx
->temp_reg
;
1328 } else if (inst
->Src
[0].Register
.File
!= TGSI_FILE_TEMPORARY
) {
1329 for (i
= 0; i
< 4; i
++) {
1330 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1331 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1332 alu
.src
[0].sel
= src_gpr
;
1333 alu
.src
[0].chan
= i
;
1334 alu
.dst
.sel
= ctx
->temp_reg
;
1339 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1343 src_gpr
= ctx
->temp_reg
;
1346 memset(&tex
, 0, sizeof(struct r600_bc_tex
));
1347 tex
.inst
= ctx
->inst_info
->r600_opcode
;
1348 tex
.resource_id
= ctx
->file_offset
[inst
->Src
[1].Register
.File
] + inst
->Src
[1].Register
.Index
;
1349 tex
.sampler_id
= tex
.resource_id
;
1350 tex
.src_gpr
= src_gpr
;
1351 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
1361 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
1362 tex
.coord_type_x
= 1;
1363 tex
.coord_type_y
= 1;
1364 tex
.coord_type_z
= 1;
1365 tex
.coord_type_w
= 1;
1367 return r600_bc_add_tex(ctx
->bc
, &tex
);
1370 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
1372 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1373 struct r600_bc_alu_src r600_src
[3];
1374 struct r600_bc_alu alu
;
1378 r
= tgsi_split_constant(ctx
, r600_src
);
1382 for (i
= 0; i
< 4; i
++) {
1383 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1384 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
;
1385 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1386 alu
.src
[0].chan
= 0;
1387 alu
.src
[1] = r600_src
[0];
1388 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1390 alu
.dst
.sel
= ctx
->temp_reg
;
1396 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1400 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1404 /* (1 - src0) * src2 */
1405 for (i
= 0; i
< 4; i
++) {
1406 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1407 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
1408 alu
.src
[0].sel
= ctx
->temp_reg
;
1409 alu
.src
[0].chan
= i
;
1410 alu
.src
[1] = r600_src
[2];
1411 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[2], i
);
1412 alu
.dst
.sel
= ctx
->temp_reg
;
1418 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1422 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1426 /* src0 * src1 + (1 - src0) * src2 */
1427 for (i
= 0; i
< 4; i
++) {
1428 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1429 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
1431 alu
.src
[0] = r600_src
[0];
1432 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1433 alu
.src
[1] = r600_src
[1];
1434 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], i
);
1435 alu
.src
[2].sel
= ctx
->temp_reg
;
1436 alu
.src
[2].chan
= i
;
1437 alu
.dst
.sel
= ctx
->temp_reg
;
1442 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1446 return tgsi_helper_copy(ctx
, inst
);
1449 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
1450 {TGSI_OPCODE_ARL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1451 {TGSI_OPCODE_MOV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
1452 {TGSI_OPCODE_LIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
1453 {TGSI_OPCODE_RCP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
1454 {TGSI_OPCODE_RSQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
, tgsi_trans_srcx_replicate
},
1455 {TGSI_OPCODE_EXP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1456 {TGSI_OPCODE_LOG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1457 {TGSI_OPCODE_MUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
1458 {TGSI_OPCODE_ADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
1459 {TGSI_OPCODE_DP3
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1460 {TGSI_OPCODE_DP4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1461 {TGSI_OPCODE_DST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1462 {TGSI_OPCODE_MIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
1463 {TGSI_OPCODE_MAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
1464 {TGSI_OPCODE_SLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_slt
},
1465 {TGSI_OPCODE_SGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
1466 {TGSI_OPCODE_MAD
, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
1467 {TGSI_OPCODE_SUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
1468 {TGSI_OPCODE_LRP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
1469 {TGSI_OPCODE_CND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1471 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1472 {TGSI_OPCODE_DP2A
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1474 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1475 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1476 {TGSI_OPCODE_FRC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
1477 {TGSI_OPCODE_CLAMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1478 {TGSI_OPCODE_FLR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
1479 {TGSI_OPCODE_ROUND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1480 {TGSI_OPCODE_EX2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
1481 {TGSI_OPCODE_LG2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
1482 {TGSI_OPCODE_POW
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
1483 {TGSI_OPCODE_XPD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1485 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1486 {TGSI_OPCODE_ABS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
1487 {TGSI_OPCODE_RCC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1488 {TGSI_OPCODE_DPH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1489 {TGSI_OPCODE_COS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
1490 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
1491 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
1492 {TGSI_OPCODE_KILP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
}, /* predicated kill */
1493 {TGSI_OPCODE_PK2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1494 {TGSI_OPCODE_PK2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1495 {TGSI_OPCODE_PK4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1496 {TGSI_OPCODE_PK4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1497 {TGSI_OPCODE_RFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1498 {TGSI_OPCODE_SEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
1499 {TGSI_OPCODE_SFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1500 {TGSI_OPCODE_SGT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
1501 {TGSI_OPCODE_SIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
1502 {TGSI_OPCODE_SLE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_slt
},
1503 {TGSI_OPCODE_SNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
1504 {TGSI_OPCODE_STR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1505 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
1506 {TGSI_OPCODE_TXD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1507 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
1508 {TGSI_OPCODE_UP2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1509 {TGSI_OPCODE_UP2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1510 {TGSI_OPCODE_UP4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1511 {TGSI_OPCODE_UP4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1512 {TGSI_OPCODE_X2D
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1513 {TGSI_OPCODE_ARA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1514 {TGSI_OPCODE_ARR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1515 {TGSI_OPCODE_BRA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1516 {TGSI_OPCODE_CAL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1517 {TGSI_OPCODE_RET
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1518 {TGSI_OPCODE_SSG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
1519 {TGSI_OPCODE_CMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1520 {TGSI_OPCODE_SCS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1521 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
1522 {TGSI_OPCODE_NRM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1523 {TGSI_OPCODE_DIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1524 {TGSI_OPCODE_DP2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1525 {TGSI_OPCODE_TXL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1526 {TGSI_OPCODE_BRK
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1527 {TGSI_OPCODE_IF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1529 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1530 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1531 {TGSI_OPCODE_ELSE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1532 {TGSI_OPCODE_ENDIF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1534 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1535 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1536 {TGSI_OPCODE_PUSHA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1537 {TGSI_OPCODE_POPA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1538 {TGSI_OPCODE_CEIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1539 {TGSI_OPCODE_I2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1540 {TGSI_OPCODE_NOT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1541 {TGSI_OPCODE_TRUNC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_trans_srcx_replicate
},
1542 {TGSI_OPCODE_SHL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1544 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1545 {TGSI_OPCODE_AND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1546 {TGSI_OPCODE_OR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1547 {TGSI_OPCODE_MOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1548 {TGSI_OPCODE_XOR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1549 {TGSI_OPCODE_SAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1550 {TGSI_OPCODE_TXF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1551 {TGSI_OPCODE_TXQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1552 {TGSI_OPCODE_CONT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1553 {TGSI_OPCODE_EMIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1554 {TGSI_OPCODE_ENDPRIM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1555 {TGSI_OPCODE_BGNLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1556 {TGSI_OPCODE_BGNSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1557 {TGSI_OPCODE_ENDLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1558 {TGSI_OPCODE_ENDSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1560 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1561 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1562 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1563 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1564 {TGSI_OPCODE_NOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1566 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1567 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1568 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1569 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1570 {TGSI_OPCODE_NRM4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1571 {TGSI_OPCODE_CALLNZ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1572 {TGSI_OPCODE_IFC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1573 {TGSI_OPCODE_BREAKC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1574 {TGSI_OPCODE_KIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
1575 {TGSI_OPCODE_END
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
1577 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1578 {TGSI_OPCODE_F2I
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1579 {TGSI_OPCODE_IDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1580 {TGSI_OPCODE_IMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1581 {TGSI_OPCODE_IMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1582 {TGSI_OPCODE_INEG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1583 {TGSI_OPCODE_ISGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1584 {TGSI_OPCODE_ISHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1585 {TGSI_OPCODE_ISLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1586 {TGSI_OPCODE_F2U
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1587 {TGSI_OPCODE_U2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1588 {TGSI_OPCODE_UADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1589 {TGSI_OPCODE_UDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1590 {TGSI_OPCODE_UMAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1591 {TGSI_OPCODE_UMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1592 {TGSI_OPCODE_UMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1593 {TGSI_OPCODE_UMOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1594 {TGSI_OPCODE_UMUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1595 {TGSI_OPCODE_USEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1596 {TGSI_OPCODE_USGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1597 {TGSI_OPCODE_USHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1598 {TGSI_OPCODE_USLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1599 {TGSI_OPCODE_USNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1600 {TGSI_OPCODE_SWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1601 {TGSI_OPCODE_CASE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1602 {TGSI_OPCODE_DEFAULT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1603 {TGSI_OPCODE_ENDSWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1604 {TGSI_OPCODE_LAST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},