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r600/shader: add flag to denote if shader uses images
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
193
194 /* disable SB for shaders using doubles */
195 use_sb &= !shader->shader.uses_doubles;
196
197 use_sb &= !shader->shader.uses_atomics;
198
199 /* Check if the bytecode has already been built. */
200 if (!shader->shader.bc.bytecode) {
201 r = r600_bytecode_build(&shader->shader.bc);
202 if (r) {
203 R600_ERR("building bytecode failed !\n");
204 goto error;
205 }
206 }
207
208 if (dump && !sb_disasm) {
209 fprintf(stderr, "--------------------------------------------------------------\n");
210 r600_bytecode_disasm(&shader->shader.bc);
211 fprintf(stderr, "______________________________________________________________\n");
212 } else if ((dump && sb_disasm) || use_sb) {
213 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
214 dump, use_sb);
215 if (r) {
216 R600_ERR("r600_sb_bytecode_process failed !\n");
217 goto error;
218 }
219 }
220
221 if (shader->gs_copy_shader) {
222 if (dump) {
223 // dump copy shader
224 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
225 &shader->gs_copy_shader->shader, dump, 0);
226 if (r)
227 goto error;
228 }
229
230 if ((r = store_shader(ctx, shader->gs_copy_shader)))
231 goto error;
232 }
233
234 /* Store the shader in a buffer. */
235 if ((r = store_shader(ctx, shader)))
236 goto error;
237
238 /* Build state. */
239 switch (shader->shader.processor_type) {
240 case PIPE_SHADER_TESS_CTRL:
241 evergreen_update_hs_state(ctx, shader);
242 break;
243 case PIPE_SHADER_TESS_EVAL:
244 if (key.tes.as_es)
245 evergreen_update_es_state(ctx, shader);
246 else
247 evergreen_update_vs_state(ctx, shader);
248 break;
249 case PIPE_SHADER_GEOMETRY:
250 if (rctx->b.chip_class >= EVERGREEN) {
251 evergreen_update_gs_state(ctx, shader);
252 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
253 } else {
254 r600_update_gs_state(ctx, shader);
255 r600_update_vs_state(ctx, shader->gs_copy_shader);
256 }
257 break;
258 case PIPE_SHADER_VERTEX:
259 export_shader = key.vs.as_es;
260 if (rctx->b.chip_class >= EVERGREEN) {
261 if (key.vs.as_ls)
262 evergreen_update_ls_state(ctx, shader);
263 else if (key.vs.as_es)
264 evergreen_update_es_state(ctx, shader);
265 else
266 evergreen_update_vs_state(ctx, shader);
267 } else {
268 if (export_shader)
269 r600_update_es_state(ctx, shader);
270 else
271 r600_update_vs_state(ctx, shader);
272 }
273 break;
274 case PIPE_SHADER_FRAGMENT:
275 if (rctx->b.chip_class >= EVERGREEN) {
276 evergreen_update_ps_state(ctx, shader);
277 } else {
278 r600_update_ps_state(ctx, shader);
279 }
280 break;
281 default:
282 r = -EINVAL;
283 goto error;
284 }
285 return 0;
286
287 error:
288 r600_pipe_shader_destroy(ctx, shader);
289 return r;
290 }
291
292 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
293 {
294 r600_resource_reference(&shader->bo, NULL);
295 r600_bytecode_clear(&shader->shader.bc);
296 r600_release_command_buffer(&shader->command_buffer);
297 }
298
299 /*
300 * tgsi -> r600 shader
301 */
302 struct r600_shader_tgsi_instruction;
303
304 struct r600_shader_src {
305 unsigned sel;
306 unsigned swizzle[4];
307 unsigned neg;
308 unsigned abs;
309 unsigned rel;
310 unsigned kc_bank;
311 boolean kc_rel; /* true if cache bank is indexed */
312 uint32_t value[4];
313 };
314
315 struct eg_interp {
316 boolean enabled;
317 unsigned ij_index;
318 };
319
320 struct r600_shader_ctx {
321 struct tgsi_shader_info info;
322 struct tgsi_parse_context parse;
323 const struct tgsi_token *tokens;
324 unsigned type;
325 unsigned file_offset[TGSI_FILE_COUNT];
326 unsigned temp_reg;
327 const struct r600_shader_tgsi_instruction *inst_info;
328 struct r600_bytecode *bc;
329 struct r600_shader *shader;
330 struct r600_shader_src src[4];
331 uint32_t *literals;
332 uint32_t nliterals;
333 uint32_t max_driver_temp_used;
334 /* needed for evergreen interpolation */
335 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
336 /* evergreen/cayman also store sample mask in face register */
337 int face_gpr;
338 /* sample id is .w component stored in fixed point position register */
339 int fixed_pt_position_gpr;
340 int colors_used;
341 boolean clip_vertex_write;
342 unsigned cv_output;
343 unsigned edgeflag_output;
344 int fragcoord_input;
345 int native_integers;
346 int next_ring_offset;
347 int gs_out_ring_offset;
348 int gs_next_vertex;
349 struct r600_shader *gs_for_vs;
350 int gs_export_gpr_tregs[4];
351 int gs_rotated_input[2];
352 const struct pipe_stream_output_info *gs_stream_output_info;
353 unsigned enabled_stream_buffers_mask;
354 unsigned tess_input_info; /* temp with tess input offsets */
355 unsigned tess_output_info; /* temp with tess input offsets */
356 };
357
358 struct r600_shader_tgsi_instruction {
359 unsigned op;
360 int (*process)(struct r600_shader_ctx *ctx);
361 };
362
363 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
364 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
365 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
366 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
367 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
368 static int tgsi_else(struct r600_shader_ctx *ctx);
369 static int tgsi_endif(struct r600_shader_ctx *ctx);
370 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
371 static int tgsi_endloop(struct r600_shader_ctx *ctx);
372 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
373 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
374 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
375 unsigned int dst_reg);
376 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
377 const struct r600_shader_src *shader_src,
378 unsigned chan);
379 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
380 unsigned dst_reg);
381
382 static int tgsi_last_instruction(unsigned writemask)
383 {
384 int i, lasti = 0;
385
386 for (i = 0; i < 4; i++) {
387 if (writemask & (1 << i)) {
388 lasti = i;
389 }
390 }
391 return lasti;
392 }
393
394 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
395 {
396 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
397 unsigned j;
398
399 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
400 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
401 return -EINVAL;
402 }
403 #if 0
404 if (i->Instruction.Label) {
405 R600_ERR("label unsupported\n");
406 return -EINVAL;
407 }
408 #endif
409 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
410 if (i->Src[j].Register.Dimension) {
411 switch (i->Src[j].Register.File) {
412 case TGSI_FILE_CONSTANT:
413 case TGSI_FILE_HW_ATOMIC:
414 break;
415 case TGSI_FILE_INPUT:
416 if (ctx->type == PIPE_SHADER_GEOMETRY ||
417 ctx->type == PIPE_SHADER_TESS_CTRL ||
418 ctx->type == PIPE_SHADER_TESS_EVAL)
419 break;
420 case TGSI_FILE_OUTPUT:
421 if (ctx->type == PIPE_SHADER_TESS_CTRL)
422 break;
423 default:
424 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
425 i->Src[j].Register.File,
426 i->Src[j].Register.Dimension);
427 return -EINVAL;
428 }
429 }
430 }
431 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
432 if (i->Dst[j].Register.Dimension) {
433 if (ctx->type == PIPE_SHADER_TESS_CTRL)
434 continue;
435 R600_ERR("unsupported dst (dimension)\n");
436 return -EINVAL;
437 }
438 }
439 return 0;
440 }
441
442 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
443 {
444 if (interpolate == TGSI_INTERPOLATE_COLOR ||
445 interpolate == TGSI_INTERPOLATE_LINEAR ||
446 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
447 {
448 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
449 int loc;
450
451 switch(location) {
452 case TGSI_INTERPOLATE_LOC_CENTER:
453 loc = 1;
454 break;
455 case TGSI_INTERPOLATE_LOC_CENTROID:
456 loc = 2;
457 break;
458 case TGSI_INTERPOLATE_LOC_SAMPLE:
459 default:
460 loc = 0; break;
461 }
462
463 return is_linear * 3 + loc;
464 }
465
466 return -1;
467 }
468
469 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
470 int input)
471 {
472 int i = eg_get_interpolator_index(
473 ctx->shader->input[input].interpolate,
474 ctx->shader->input[input].interpolate_location);
475 assert(i >= 0);
476 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
477 }
478
479 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
480 {
481 int i, r;
482 struct r600_bytecode_alu alu;
483 int gpr = 0, base_chan = 0;
484 int ij_index = ctx->shader->input[input].ij_index;
485
486 /* work out gpr and base_chan from index */
487 gpr = ij_index / 2;
488 base_chan = (2 * (ij_index % 2)) + 1;
489
490 for (i = 0; i < 8; i++) {
491 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
492
493 if (i < 4)
494 alu.op = ALU_OP2_INTERP_ZW;
495 else
496 alu.op = ALU_OP2_INTERP_XY;
497
498 if ((i > 1) && (i < 6)) {
499 alu.dst.sel = ctx->shader->input[input].gpr;
500 alu.dst.write = 1;
501 }
502
503 alu.dst.chan = i % 4;
504
505 alu.src[0].sel = gpr;
506 alu.src[0].chan = (base_chan - (i % 2));
507
508 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
509
510 alu.bank_swizzle_force = SQ_ALU_VEC_210;
511 if ((i % 4) == 3)
512 alu.last = 1;
513 r = r600_bytecode_add_alu(ctx->bc, &alu);
514 if (r)
515 return r;
516 }
517 return 0;
518 }
519
520 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
521 {
522 int i, r;
523 struct r600_bytecode_alu alu;
524
525 for (i = 0; i < 4; i++) {
526 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
527
528 alu.op = ALU_OP1_INTERP_LOAD_P0;
529
530 alu.dst.sel = ctx->shader->input[input].gpr;
531 alu.dst.write = 1;
532
533 alu.dst.chan = i;
534
535 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
536 alu.src[0].chan = i;
537
538 if (i == 3)
539 alu.last = 1;
540 r = r600_bytecode_add_alu(ctx->bc, &alu);
541 if (r)
542 return r;
543 }
544 return 0;
545 }
546
547 /*
548 * Special export handling in shaders
549 *
550 * shader export ARRAY_BASE for EXPORT_POS:
551 * 60 is position
552 * 61 is misc vector
553 * 62, 63 are clip distance vectors
554 *
555 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
556 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
557 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
558 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
559 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
560 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
561 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
562 * exclusive from render target index)
563 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
564 *
565 *
566 * shader export ARRAY_BASE for EXPORT_PIXEL:
567 * 0-7 CB targets
568 * 61 computed Z vector
569 *
570 * The use of the values exported in the computed Z vector are controlled
571 * by DB_SHADER_CONTROL:
572 * Z_EXPORT_ENABLE - Z as a float in RED
573 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
574 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
575 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
576 * DB_SOURCE_FORMAT - export control restrictions
577 *
578 */
579
580
581 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
582 static int r600_spi_sid(struct r600_shader_io * io)
583 {
584 int index, name = io->name;
585
586 /* These params are handled differently, they don't need
587 * semantic indices, so we'll use 0 for them.
588 */
589 if (name == TGSI_SEMANTIC_POSITION ||
590 name == TGSI_SEMANTIC_PSIZE ||
591 name == TGSI_SEMANTIC_EDGEFLAG ||
592 name == TGSI_SEMANTIC_FACE ||
593 name == TGSI_SEMANTIC_SAMPLEMASK)
594 index = 0;
595 else {
596 if (name == TGSI_SEMANTIC_GENERIC) {
597 /* For generic params simply use sid from tgsi */
598 index = io->sid;
599 } else {
600 /* For non-generic params - pack name and sid into 8 bits */
601 index = 0x80 | (name<<3) | (io->sid);
602 }
603
604 /* Make sure that all really used indices have nonzero value, so
605 * we can just compare it to 0 later instead of comparing the name
606 * with different values to detect special cases. */
607 index++;
608 }
609
610 return index;
611 };
612
613 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
614 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
615 {
616 switch (semantic_name) {
617 case TGSI_SEMANTIC_POSITION:
618 return 0;
619 case TGSI_SEMANTIC_PSIZE:
620 return 1;
621 case TGSI_SEMANTIC_CLIPDIST:
622 assert(index <= 1);
623 return 2 + index;
624 case TGSI_SEMANTIC_GENERIC:
625 if (index <= 63-4)
626 return 4 + index - 9;
627 else
628 /* same explanation as in the default statement,
629 * the only user hitting this is st/nine.
630 */
631 return 0;
632
633 /* patch indices are completely separate and thus start from 0 */
634 case TGSI_SEMANTIC_TESSOUTER:
635 return 0;
636 case TGSI_SEMANTIC_TESSINNER:
637 return 1;
638 case TGSI_SEMANTIC_PATCH:
639 return 2 + index;
640
641 default:
642 /* Don't fail here. The result of this function is only used
643 * for LS, TCS, TES, and GS, where legacy GL semantics can't
644 * occur, but this function is called for all vertex shaders
645 * before it's known whether LS will be compiled or not.
646 */
647 return 0;
648 }
649 }
650
651 /* turn input into interpolate on EG */
652 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
653 {
654 int r = 0;
655
656 if (ctx->shader->input[index].spi_sid) {
657 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
658 if (ctx->shader->input[index].interpolate > 0) {
659 evergreen_interp_assign_ij_index(ctx, index);
660 r = evergreen_interp_alu(ctx, index);
661 } else {
662 r = evergreen_interp_flat(ctx, index);
663 }
664 }
665 return r;
666 }
667
668 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
669 {
670 struct r600_bytecode_alu alu;
671 int i, r;
672 int gpr_front = ctx->shader->input[front].gpr;
673 int gpr_back = ctx->shader->input[back].gpr;
674
675 for (i = 0; i < 4; i++) {
676 memset(&alu, 0, sizeof(alu));
677 alu.op = ALU_OP3_CNDGT;
678 alu.is_op3 = 1;
679 alu.dst.write = 1;
680 alu.dst.sel = gpr_front;
681 alu.src[0].sel = ctx->face_gpr;
682 alu.src[1].sel = gpr_front;
683 alu.src[2].sel = gpr_back;
684
685 alu.dst.chan = i;
686 alu.src[1].chan = i;
687 alu.src[2].chan = i;
688 alu.last = (i==3);
689
690 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
691 return r;
692 }
693
694 return 0;
695 }
696
697 /* execute a single slot ALU calculation */
698 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
699 int dst_sel, int dst_chan,
700 int src0_sel, unsigned src0_chan_val,
701 int src1_sel, unsigned src1_chan_val)
702 {
703 struct r600_bytecode_alu alu;
704 int r, i;
705
706 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
707 for (i = 0; i < 4; i++) {
708 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
709 alu.op = op;
710 alu.src[0].sel = src0_sel;
711 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
712 alu.src[0].value = src0_chan_val;
713 else
714 alu.src[0].chan = src0_chan_val;
715 alu.src[1].sel = src1_sel;
716 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
717 alu.src[1].value = src1_chan_val;
718 else
719 alu.src[1].chan = src1_chan_val;
720 alu.dst.sel = dst_sel;
721 alu.dst.chan = i;
722 alu.dst.write = i == dst_chan;
723 alu.last = (i == 3);
724 r = r600_bytecode_add_alu(ctx->bc, &alu);
725 if (r)
726 return r;
727 }
728 return 0;
729 }
730
731 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
732 alu.op = op;
733 alu.src[0].sel = src0_sel;
734 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
735 alu.src[0].value = src0_chan_val;
736 else
737 alu.src[0].chan = src0_chan_val;
738 alu.src[1].sel = src1_sel;
739 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
740 alu.src[1].value = src1_chan_val;
741 else
742 alu.src[1].chan = src1_chan_val;
743 alu.dst.sel = dst_sel;
744 alu.dst.chan = dst_chan;
745 alu.dst.write = 1;
746 alu.last = 1;
747 r = r600_bytecode_add_alu(ctx->bc, &alu);
748 if (r)
749 return r;
750 return 0;
751 }
752
753 /* execute a single slot ALU calculation */
754 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
755 int dst_sel, int dst_chan,
756 int src0_sel, unsigned src0_chan_val,
757 int src1_sel, unsigned src1_chan_val,
758 int src2_sel, unsigned src2_chan_val)
759 {
760 struct r600_bytecode_alu alu;
761 int r;
762
763 /* validate this for other ops */
764 assert(op == ALU_OP3_MULADD_UINT24 || op == ALU_OP3_CNDE_INT);
765 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
766 alu.op = op;
767 alu.src[0].sel = src0_sel;
768 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
769 alu.src[0].value = src0_chan_val;
770 else
771 alu.src[0].chan = src0_chan_val;
772 alu.src[1].sel = src1_sel;
773 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
774 alu.src[1].value = src1_chan_val;
775 else
776 alu.src[1].chan = src1_chan_val;
777 alu.src[2].sel = src2_sel;
778 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
779 alu.src[2].value = src2_chan_val;
780 else
781 alu.src[2].chan = src2_chan_val;
782 alu.dst.sel = dst_sel;
783 alu.dst.chan = dst_chan;
784 alu.is_op3 = 1;
785 alu.last = 1;
786 r = r600_bytecode_add_alu(ctx->bc, &alu);
787 if (r)
788 return r;
789 return 0;
790 }
791
792 /* put it in temp_reg.x */
793 static int get_lds_offset0(struct r600_shader_ctx *ctx,
794 int rel_patch_chan,
795 int temp_reg, bool is_patch_var)
796 {
797 int r;
798
799 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
800 /* ADD
801 Dimension - patch0_offset (input_vals.z),
802 Non-dim - patch0_data_offset (input_vals.w)
803 */
804 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
805 temp_reg, 0,
806 ctx->tess_output_info, 0,
807 0, rel_patch_chan,
808 ctx->tess_output_info, is_patch_var ? 3 : 2);
809 if (r)
810 return r;
811 return 0;
812 }
813
814 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
815 {
816 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
817 }
818
819 static int r600_get_temp(struct r600_shader_ctx *ctx)
820 {
821 return ctx->temp_reg + ctx->max_driver_temp_used++;
822 }
823
824 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
825 {
826 int i;
827 i = ctx->shader->noutput++;
828 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
829 ctx->shader->output[i].sid = 0;
830 ctx->shader->output[i].gpr = 0;
831 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
832 ctx->shader->output[i].write_mask = 0x4;
833 ctx->shader->output[i].spi_sid = prim_id_sid;
834
835 return 0;
836 }
837
838 static int tgsi_barrier(struct r600_shader_ctx *ctx)
839 {
840 struct r600_bytecode_alu alu;
841 int r;
842
843 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
844 alu.op = ctx->inst_info->op;
845 alu.last = 1;
846
847 r = r600_bytecode_add_alu(ctx->bc, &alu);
848 if (r)
849 return r;
850 return 0;
851 }
852
853 static int tgsi_declaration(struct r600_shader_ctx *ctx)
854 {
855 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
856 int r, i, j, count = d->Range.Last - d->Range.First + 1;
857
858 switch (d->Declaration.File) {
859 case TGSI_FILE_INPUT:
860 for (j = 0; j < count; j++) {
861 i = ctx->shader->ninput + j;
862 assert(i < ARRAY_SIZE(ctx->shader->input));
863 ctx->shader->input[i].name = d->Semantic.Name;
864 ctx->shader->input[i].sid = d->Semantic.Index + j;
865 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
866 ctx->shader->input[i].interpolate_location = d->Interp.Location;
867 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
868 if (ctx->type == PIPE_SHADER_FRAGMENT) {
869 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
870 switch (ctx->shader->input[i].name) {
871 case TGSI_SEMANTIC_FACE:
872 if (ctx->face_gpr != -1)
873 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
874 else
875 ctx->face_gpr = ctx->shader->input[i].gpr;
876 break;
877 case TGSI_SEMANTIC_COLOR:
878 ctx->colors_used++;
879 break;
880 case TGSI_SEMANTIC_POSITION:
881 ctx->fragcoord_input = i;
882 break;
883 case TGSI_SEMANTIC_PRIMID:
884 /* set this for now */
885 ctx->shader->gs_prim_id_input = true;
886 ctx->shader->ps_prim_id_input = i;
887 break;
888 }
889 if (ctx->bc->chip_class >= EVERGREEN) {
890 if ((r = evergreen_interp_input(ctx, i)))
891 return r;
892 }
893 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
894 /* FIXME probably skip inputs if they aren't passed in the ring */
895 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
896 ctx->next_ring_offset += 16;
897 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
898 ctx->shader->gs_prim_id_input = true;
899 }
900 }
901 ctx->shader->ninput += count;
902 break;
903 case TGSI_FILE_OUTPUT:
904 for (j = 0; j < count; j++) {
905 i = ctx->shader->noutput + j;
906 assert(i < ARRAY_SIZE(ctx->shader->output));
907 ctx->shader->output[i].name = d->Semantic.Name;
908 ctx->shader->output[i].sid = d->Semantic.Index + j;
909 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
910 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
911 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
912 if (ctx->type == PIPE_SHADER_VERTEX ||
913 ctx->type == PIPE_SHADER_GEOMETRY ||
914 ctx->type == PIPE_SHADER_TESS_EVAL) {
915 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
916 switch (d->Semantic.Name) {
917 case TGSI_SEMANTIC_CLIPDIST:
918 ctx->shader->clip_dist_write |= d->Declaration.UsageMask <<
919 ((d->Semantic.Index + j) << 2);
920 break;
921 case TGSI_SEMANTIC_PSIZE:
922 ctx->shader->vs_out_misc_write = 1;
923 ctx->shader->vs_out_point_size = 1;
924 break;
925 case TGSI_SEMANTIC_EDGEFLAG:
926 ctx->shader->vs_out_misc_write = 1;
927 ctx->shader->vs_out_edgeflag = 1;
928 ctx->edgeflag_output = i;
929 break;
930 case TGSI_SEMANTIC_VIEWPORT_INDEX:
931 ctx->shader->vs_out_misc_write = 1;
932 ctx->shader->vs_out_viewport = 1;
933 break;
934 case TGSI_SEMANTIC_LAYER:
935 ctx->shader->vs_out_misc_write = 1;
936 ctx->shader->vs_out_layer = 1;
937 break;
938 case TGSI_SEMANTIC_CLIPVERTEX:
939 ctx->clip_vertex_write = TRUE;
940 ctx->cv_output = i;
941 break;
942 }
943 if (ctx->type == PIPE_SHADER_GEOMETRY) {
944 ctx->gs_out_ring_offset += 16;
945 }
946 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
947 switch (d->Semantic.Name) {
948 case TGSI_SEMANTIC_COLOR:
949 ctx->shader->nr_ps_max_color_exports++;
950 break;
951 }
952 }
953 }
954 ctx->shader->noutput += count;
955 break;
956 case TGSI_FILE_TEMPORARY:
957 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
958 if (d->Array.ArrayID) {
959 r600_add_gpr_array(ctx->shader,
960 ctx->file_offset[TGSI_FILE_TEMPORARY] +
961 d->Range.First,
962 d->Range.Last - d->Range.First + 1, 0x0F);
963 }
964 }
965 break;
966
967 case TGSI_FILE_CONSTANT:
968 case TGSI_FILE_SAMPLER:
969 case TGSI_FILE_SAMPLER_VIEW:
970 case TGSI_FILE_ADDRESS:
971 break;
972
973 case TGSI_FILE_HW_ATOMIC:
974 i = ctx->shader->nhwatomic_ranges;
975 ctx->shader->atomics[i].start = d->Range.First;
976 ctx->shader->atomics[i].end = d->Range.Last;
977 ctx->shader->atomics[i].hw_idx = ctx->shader->atomic_base + ctx->shader->nhwatomic;
978 ctx->shader->atomics[i].array_id = d->Array.ArrayID;
979 ctx->shader->atomics[i].buffer_id = d->Dim.Index2D;
980 ctx->shader->nhwatomic_ranges++;
981 ctx->shader->nhwatomic += count;
982 break;
983
984 case TGSI_FILE_SYSTEM_VALUE:
985 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
986 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
987 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
988 break; /* Already handled from allocate_system_value_inputs */
989 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
990 if (!ctx->native_integers) {
991 struct r600_bytecode_alu alu;
992 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
993
994 alu.op = ALU_OP1_INT_TO_FLT;
995 alu.src[0].sel = 0;
996 alu.src[0].chan = 3;
997
998 alu.dst.sel = 0;
999 alu.dst.chan = 3;
1000 alu.dst.write = 1;
1001 alu.last = 1;
1002
1003 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1004 return r;
1005 }
1006 break;
1007 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
1008 break;
1009 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
1010 break;
1011 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1012 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1013 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1014 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1015 unsigned temp_reg = r600_get_temp(ctx);
1016
1017 r = get_lds_offset0(ctx, 2, temp_reg, true);
1018 if (r)
1019 return r;
1020
1021 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1022 temp_reg, 0,
1023 temp_reg, 0,
1024 V_SQ_ALU_SRC_LITERAL, param * 16);
1025 if (r)
1026 return r;
1027
1028 do_lds_fetch_values(ctx, temp_reg, dreg);
1029 }
1030 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1031 /* MOV r1.x, r0.x;
1032 MOV r1.y, r0.y;
1033 */
1034 for (i = 0; i < 2; i++) {
1035 struct r600_bytecode_alu alu;
1036 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1037 alu.op = ALU_OP1_MOV;
1038 alu.src[0].sel = 0;
1039 alu.src[0].chan = 0 + i;
1040 alu.dst.sel = 1;
1041 alu.dst.chan = 0 + i;
1042 alu.dst.write = 1;
1043 alu.last = (i == 1) ? 1 : 0;
1044 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1045 return r;
1046 }
1047 /* ADD r1.z, 1.0f, -r0.x */
1048 struct r600_bytecode_alu alu;
1049 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1050 alu.op = ALU_OP2_ADD;
1051 alu.src[0].sel = V_SQ_ALU_SRC_1;
1052 alu.src[1].sel = 1;
1053 alu.src[1].chan = 0;
1054 alu.src[1].neg = 1;
1055 alu.dst.sel = 1;
1056 alu.dst.chan = 2;
1057 alu.dst.write = 1;
1058 alu.last = 1;
1059 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1060 return r;
1061
1062 /* ADD r1.z, r1.z, -r1.y */
1063 alu.op = ALU_OP2_ADD;
1064 alu.src[0].sel = 1;
1065 alu.src[0].chan = 2;
1066 alu.src[1].sel = 1;
1067 alu.src[1].chan = 1;
1068 alu.src[1].neg = 1;
1069 alu.dst.sel = 1;
1070 alu.dst.chan = 2;
1071 alu.dst.write = 1;
1072 alu.last = 1;
1073 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1074 return r;
1075 break;
1076 }
1077 break;
1078 default:
1079 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1080 return -EINVAL;
1081 }
1082 return 0;
1083 }
1084
1085 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1086 {
1087 struct tgsi_parse_context parse;
1088 struct {
1089 boolean enabled;
1090 int *reg;
1091 unsigned name, alternate_name;
1092 } inputs[2] = {
1093 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1094
1095 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1096 };
1097 int i, k, num_regs = 0;
1098
1099 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1100 return 0;
1101 }
1102
1103 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1104 while (!tgsi_parse_end_of_tokens(&parse)) {
1105 tgsi_parse_token(&parse);
1106
1107 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1108 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1109 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1110 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1111 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1112 {
1113 int interpolate, location, k;
1114
1115 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1116 location = TGSI_INTERPOLATE_LOC_CENTER;
1117 inputs[1].enabled = true; /* needs SAMPLEID */
1118 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1119 location = TGSI_INTERPOLATE_LOC_CENTER;
1120 /* Needs sample positions, currently those are always available */
1121 } else {
1122 location = TGSI_INTERPOLATE_LOC_CENTROID;
1123 }
1124
1125 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1126 k = eg_get_interpolator_index(interpolate, location);
1127 if (k >= 0)
1128 ctx->eg_interpolators[k].enabled = true;
1129 }
1130 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1131 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1132 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1133 for (k = 0; k < ARRAY_SIZE(inputs); k++) {
1134 if (d->Semantic.Name == inputs[k].name ||
1135 d->Semantic.Name == inputs[k].alternate_name) {
1136 inputs[k].enabled = true;
1137 }
1138 }
1139 }
1140 }
1141 }
1142
1143 tgsi_parse_free(&parse);
1144
1145 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
1146 boolean enabled = inputs[i].enabled;
1147 int *reg = inputs[i].reg;
1148 unsigned name = inputs[i].name;
1149
1150 if (enabled) {
1151 int gpr = gpr_offset + num_regs++;
1152 ctx->shader->nsys_inputs++;
1153
1154 // add to inputs, allocate a gpr
1155 k = ctx->shader->ninput++;
1156 ctx->shader->input[k].name = name;
1157 ctx->shader->input[k].sid = 0;
1158 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1159 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1160 *reg = ctx->shader->input[k].gpr = gpr;
1161 }
1162 }
1163
1164 return gpr_offset + num_regs;
1165 }
1166
1167 /*
1168 * for evergreen we need to scan the shader to find the number of GPRs we need to
1169 * reserve for interpolation and system values
1170 *
1171 * we need to know if we are going to emit
1172 * any sample or centroid inputs
1173 * if perspective and linear are required
1174 */
1175 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1176 {
1177 unsigned i;
1178 int num_baryc;
1179 struct tgsi_parse_context parse;
1180
1181 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1182
1183 for (i = 0; i < ctx->info.num_inputs; i++) {
1184 int k;
1185 /* skip position/face/mask/sampleid */
1186 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1187 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1188 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1189 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1190 continue;
1191
1192 k = eg_get_interpolator_index(
1193 ctx->info.input_interpolate[i],
1194 ctx->info.input_interpolate_loc[i]);
1195 if (k >= 0)
1196 ctx->eg_interpolators[k].enabled = TRUE;
1197 }
1198
1199 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1200 return 0;
1201 }
1202
1203 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1204 while (!tgsi_parse_end_of_tokens(&parse)) {
1205 tgsi_parse_token(&parse);
1206
1207 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1208 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1209 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1210 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1211 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1212 {
1213 int interpolate, location, k;
1214
1215 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1216 location = TGSI_INTERPOLATE_LOC_CENTER;
1217 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1218 location = TGSI_INTERPOLATE_LOC_CENTER;
1219 } else {
1220 location = TGSI_INTERPOLATE_LOC_CENTROID;
1221 }
1222
1223 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1224 k = eg_get_interpolator_index(interpolate, location);
1225 if (k >= 0)
1226 ctx->eg_interpolators[k].enabled = true;
1227 }
1228 }
1229 }
1230
1231 tgsi_parse_free(&parse);
1232
1233 /* assign gpr to each interpolator according to priority */
1234 num_baryc = 0;
1235 for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
1236 if (ctx->eg_interpolators[i].enabled) {
1237 ctx->eg_interpolators[i].ij_index = num_baryc;
1238 num_baryc ++;
1239 }
1240 }
1241
1242 /* XXX PULL MODEL and LINE STIPPLE */
1243
1244 num_baryc = (num_baryc + 1) >> 1;
1245 return allocate_system_value_inputs(ctx, num_baryc);
1246 }
1247
1248 /* sample_id_sel == NULL means fetch for current sample */
1249 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1250 {
1251 struct r600_bytecode_vtx vtx;
1252 int r, t1;
1253
1254 assert(ctx->fixed_pt_position_gpr != -1);
1255
1256 t1 = r600_get_temp(ctx);
1257
1258 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1259 vtx.op = FETCH_OP_VFETCH;
1260 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1261 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1262 if (sample_id == NULL) {
1263 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1264 vtx.src_sel_x = 3;
1265 }
1266 else {
1267 struct r600_bytecode_alu alu;
1268
1269 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1270 alu.op = ALU_OP1_MOV;
1271 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1272 alu.dst.sel = t1;
1273 alu.dst.write = 1;
1274 alu.last = 1;
1275 r = r600_bytecode_add_alu(ctx->bc, &alu);
1276 if (r)
1277 return r;
1278
1279 vtx.src_gpr = t1;
1280 vtx.src_sel_x = 0;
1281 }
1282 vtx.mega_fetch_count = 16;
1283 vtx.dst_gpr = t1;
1284 vtx.dst_sel_x = 0;
1285 vtx.dst_sel_y = 1;
1286 vtx.dst_sel_z = 2;
1287 vtx.dst_sel_w = 3;
1288 vtx.data_format = FMT_32_32_32_32_FLOAT;
1289 vtx.num_format_all = 2;
1290 vtx.format_comp_all = 1;
1291 vtx.use_const_fields = 0;
1292 vtx.offset = 1; // first element is size of buffer
1293 vtx.endian = r600_endian_swap(32);
1294 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1295
1296 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1297 if (r)
1298 return r;
1299
1300 return t1;
1301 }
1302
1303 static void tgsi_src(struct r600_shader_ctx *ctx,
1304 const struct tgsi_full_src_register *tgsi_src,
1305 struct r600_shader_src *r600_src)
1306 {
1307 memset(r600_src, 0, sizeof(*r600_src));
1308 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1309 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1310 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1311 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1312 r600_src->neg = tgsi_src->Register.Negate;
1313 r600_src->abs = tgsi_src->Register.Absolute;
1314
1315 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1316 int index;
1317 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1318 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1319 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1320
1321 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1322 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1323 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1324 return;
1325 }
1326 index = tgsi_src->Register.Index;
1327 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1328 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1329 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1330 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1331 r600_src->swizzle[0] = 2; // Z value
1332 r600_src->swizzle[1] = 2;
1333 r600_src->swizzle[2] = 2;
1334 r600_src->swizzle[3] = 2;
1335 r600_src->sel = ctx->face_gpr;
1336 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1337 r600_src->swizzle[0] = 3; // W value
1338 r600_src->swizzle[1] = 3;
1339 r600_src->swizzle[2] = 3;
1340 r600_src->swizzle[3] = 3;
1341 r600_src->sel = ctx->fixed_pt_position_gpr;
1342 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1343 r600_src->swizzle[0] = 0;
1344 r600_src->swizzle[1] = 1;
1345 r600_src->swizzle[2] = 4;
1346 r600_src->swizzle[3] = 4;
1347 r600_src->sel = load_sample_position(ctx, NULL, -1);
1348 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1349 r600_src->swizzle[0] = 3;
1350 r600_src->swizzle[1] = 3;
1351 r600_src->swizzle[2] = 3;
1352 r600_src->swizzle[3] = 3;
1353 r600_src->sel = 0;
1354 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1355 r600_src->swizzle[0] = 0;
1356 r600_src->swizzle[1] = 0;
1357 r600_src->swizzle[2] = 0;
1358 r600_src->swizzle[3] = 0;
1359 r600_src->sel = 0;
1360 } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1361 r600_src->swizzle[0] = 3;
1362 r600_src->swizzle[1] = 3;
1363 r600_src->swizzle[2] = 3;
1364 r600_src->swizzle[3] = 3;
1365 r600_src->sel = 1;
1366 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1367 r600_src->swizzle[0] = 2;
1368 r600_src->swizzle[1] = 2;
1369 r600_src->swizzle[2] = 2;
1370 r600_src->swizzle[3] = 2;
1371 r600_src->sel = 0;
1372 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1373 r600_src->sel = 1;
1374 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1375 r600_src->sel = 3;
1376 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1377 r600_src->sel = 2;
1378 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1379 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
1380 r600_src->sel = ctx->tess_input_info;
1381 r600_src->swizzle[0] = 2;
1382 r600_src->swizzle[1] = 2;
1383 r600_src->swizzle[2] = 2;
1384 r600_src->swizzle[3] = 2;
1385 } else {
1386 r600_src->sel = ctx->tess_input_info;
1387 r600_src->swizzle[0] = 3;
1388 r600_src->swizzle[1] = 3;
1389 r600_src->swizzle[2] = 3;
1390 r600_src->swizzle[3] = 3;
1391 }
1392 } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1393 r600_src->sel = 0;
1394 r600_src->swizzle[0] = 0;
1395 r600_src->swizzle[1] = 0;
1396 r600_src->swizzle[2] = 0;
1397 r600_src->swizzle[3] = 0;
1398 } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1399 r600_src->sel = 0;
1400 r600_src->swizzle[0] = 3;
1401 r600_src->swizzle[1] = 3;
1402 r600_src->swizzle[2] = 3;
1403 r600_src->swizzle[3] = 3;
1404 }
1405 } else {
1406 if (tgsi_src->Register.Indirect)
1407 r600_src->rel = V_SQ_REL_RELATIVE;
1408 r600_src->sel = tgsi_src->Register.Index;
1409 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1410 }
1411 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1412 if (tgsi_src->Register.Dimension) {
1413 r600_src->kc_bank = tgsi_src->Dimension.Index;
1414 if (tgsi_src->Dimension.Indirect) {
1415 r600_src->kc_rel = 1;
1416 }
1417 }
1418 }
1419 }
1420
1421 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1422 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1423 unsigned int dst_reg)
1424 {
1425 struct r600_bytecode_vtx vtx;
1426 unsigned int ar_reg;
1427 int r;
1428
1429 if (offset) {
1430 struct r600_bytecode_alu alu;
1431
1432 memset(&alu, 0, sizeof(alu));
1433
1434 alu.op = ALU_OP2_ADD_INT;
1435 alu.src[0].sel = ctx->bc->ar_reg;
1436 alu.src[0].chan = ar_chan;
1437
1438 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1439 alu.src[1].value = offset;
1440
1441 alu.dst.sel = dst_reg;
1442 alu.dst.chan = ar_chan;
1443 alu.dst.write = 1;
1444 alu.last = 1;
1445
1446 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1447 return r;
1448
1449 ar_reg = dst_reg;
1450 } else {
1451 ar_reg = ctx->bc->ar_reg;
1452 }
1453
1454 memset(&vtx, 0, sizeof(vtx));
1455 vtx.buffer_id = cb_idx;
1456 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1457 vtx.src_gpr = ar_reg;
1458 vtx.src_sel_x = ar_chan;
1459 vtx.mega_fetch_count = 16;
1460 vtx.dst_gpr = dst_reg;
1461 vtx.dst_sel_x = 0; /* SEL_X */
1462 vtx.dst_sel_y = 1; /* SEL_Y */
1463 vtx.dst_sel_z = 2; /* SEL_Z */
1464 vtx.dst_sel_w = 3; /* SEL_W */
1465 vtx.data_format = FMT_32_32_32_32_FLOAT;
1466 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1467 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1468 vtx.endian = r600_endian_swap(32);
1469 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1470
1471 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1472 return r;
1473
1474 return 0;
1475 }
1476
1477 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1478 {
1479 struct r600_bytecode_vtx vtx;
1480 int r;
1481 unsigned index = src->Register.Index;
1482 unsigned vtx_id = src->Dimension.Index;
1483 int offset_reg = ctx->gs_rotated_input[vtx_id / 3];
1484 int offset_chan = vtx_id % 3;
1485 int t2 = 0;
1486
1487 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1488 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1489
1490 if (offset_reg == ctx->gs_rotated_input[0] && offset_chan == 2)
1491 offset_chan = 3;
1492
1493 if (src->Dimension.Indirect || src->Register.Indirect)
1494 t2 = r600_get_temp(ctx);
1495
1496 if (src->Dimension.Indirect) {
1497 int treg[3];
1498 struct r600_bytecode_alu alu;
1499 int r, i;
1500 unsigned addr_reg;
1501 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1502 if (src->DimIndirect.Index > 0) {
1503 r = single_alu_op2(ctx, ALU_OP1_MOV,
1504 ctx->bc->ar_reg, 0,
1505 addr_reg, 0,
1506 0, 0);
1507 if (r)
1508 return r;
1509 }
1510 /*
1511 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1512 at least this is what fglrx seems to do. */
1513 for (i = 0; i < 3; i++) {
1514 treg[i] = r600_get_temp(ctx);
1515 }
1516 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1517
1518 for (i = 0; i < 3; i++) {
1519 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1520 alu.op = ALU_OP1_MOV;
1521 alu.src[0].sel = ctx->gs_rotated_input[0];
1522 alu.src[0].chan = i == 2 ? 3 : i;
1523 alu.dst.sel = treg[i];
1524 alu.dst.chan = 0;
1525 alu.dst.write = 1;
1526 alu.last = 1;
1527 r = r600_bytecode_add_alu(ctx->bc, &alu);
1528 if (r)
1529 return r;
1530 }
1531 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1532 alu.op = ALU_OP1_MOV;
1533 alu.src[0].sel = treg[0];
1534 alu.src[0].rel = 1;
1535 alu.dst.sel = t2;
1536 alu.dst.write = 1;
1537 alu.last = 1;
1538 r = r600_bytecode_add_alu(ctx->bc, &alu);
1539 if (r)
1540 return r;
1541 offset_reg = t2;
1542 offset_chan = 0;
1543 }
1544
1545 if (src->Register.Indirect) {
1546 int addr_reg;
1547 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1548
1549 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1550
1551 /* pull the value from index_reg */
1552 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1553 t2, 1,
1554 addr_reg, 0,
1555 V_SQ_ALU_SRC_LITERAL, first);
1556 if (r)
1557 return r;
1558 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1559 t2, 0,
1560 t2, 1,
1561 V_SQ_ALU_SRC_LITERAL, 4,
1562 offset_reg, offset_chan);
1563 if (r)
1564 return r;
1565 offset_reg = t2;
1566 offset_chan = 0;
1567 index = src->Register.Index - first;
1568 }
1569
1570 memset(&vtx, 0, sizeof(vtx));
1571 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1572 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1573 vtx.src_gpr = offset_reg;
1574 vtx.src_sel_x = offset_chan;
1575 vtx.offset = index * 16; /*bytes*/
1576 vtx.mega_fetch_count = 16;
1577 vtx.dst_gpr = dst_reg;
1578 vtx.dst_sel_x = 0; /* SEL_X */
1579 vtx.dst_sel_y = 1; /* SEL_Y */
1580 vtx.dst_sel_z = 2; /* SEL_Z */
1581 vtx.dst_sel_w = 3; /* SEL_W */
1582 if (ctx->bc->chip_class >= EVERGREEN) {
1583 vtx.use_const_fields = 1;
1584 } else {
1585 vtx.data_format = FMT_32_32_32_32_FLOAT;
1586 }
1587
1588 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1589 return r;
1590
1591 return 0;
1592 }
1593
1594 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1595 {
1596 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1597 unsigned i;
1598
1599 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1600 struct tgsi_full_src_register *src = &inst->Src[i];
1601
1602 if (src->Register.File == TGSI_FILE_INPUT) {
1603 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1604 /* primitive id is in R0.z */
1605 ctx->src[i].sel = 0;
1606 ctx->src[i].swizzle[0] = 2;
1607 }
1608 }
1609 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1610 int treg = r600_get_temp(ctx);
1611
1612 fetch_gs_input(ctx, src, treg);
1613 ctx->src[i].sel = treg;
1614 ctx->src[i].rel = 0;
1615 }
1616 }
1617 return 0;
1618 }
1619
1620
1621 /* Tessellation shaders pass outputs to the next shader using LDS.
1622 *
1623 * LS outputs = TCS(HS) inputs
1624 * TCS(HS) outputs = TES(DS) inputs
1625 *
1626 * The LDS layout is:
1627 * - TCS inputs for patch 0
1628 * - TCS inputs for patch 1
1629 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1630 * - ...
1631 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1632 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1633 * - TCS outputs for patch 1
1634 * - Per-patch TCS outputs for patch 1
1635 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1636 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1637 * - ...
1638 *
1639 * All three shaders VS(LS), TCS, TES share the same LDS space.
1640 */
1641 /* this will return with the dw address in temp_reg.x */
1642 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1643 const struct tgsi_full_dst_register *dst,
1644 const struct tgsi_full_src_register *src,
1645 int stride_bytes_reg, int stride_bytes_chan)
1646 {
1647 struct tgsi_full_dst_register reg;
1648 ubyte *name, *index, *array_first;
1649 int r;
1650 int param;
1651 struct tgsi_shader_info *info = &ctx->info;
1652 /* Set the register description. The address computation is the same
1653 * for sources and destinations. */
1654 if (src) {
1655 reg.Register.File = src->Register.File;
1656 reg.Register.Index = src->Register.Index;
1657 reg.Register.Indirect = src->Register.Indirect;
1658 reg.Register.Dimension = src->Register.Dimension;
1659 reg.Indirect = src->Indirect;
1660 reg.Dimension = src->Dimension;
1661 reg.DimIndirect = src->DimIndirect;
1662 } else
1663 reg = *dst;
1664
1665 /* If the register is 2-dimensional (e.g. an array of vertices
1666 * in a primitive), calculate the base address of the vertex. */
1667 if (reg.Register.Dimension) {
1668 int sel, chan;
1669 if (reg.Dimension.Indirect) {
1670 unsigned addr_reg;
1671 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1672
1673 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1674 /* pull the value from index_reg */
1675 sel = addr_reg;
1676 chan = 0;
1677 } else {
1678 sel = V_SQ_ALU_SRC_LITERAL;
1679 chan = reg.Dimension.Index;
1680 }
1681
1682 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1683 temp_reg, 0,
1684 stride_bytes_reg, stride_bytes_chan,
1685 sel, chan,
1686 temp_reg, 0);
1687 if (r)
1688 return r;
1689 }
1690
1691 if (reg.Register.File == TGSI_FILE_INPUT) {
1692 name = info->input_semantic_name;
1693 index = info->input_semantic_index;
1694 array_first = info->input_array_first;
1695 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1696 name = info->output_semantic_name;
1697 index = info->output_semantic_index;
1698 array_first = info->output_array_first;
1699 } else {
1700 assert(0);
1701 return -1;
1702 }
1703 if (reg.Register.Indirect) {
1704 int addr_reg;
1705 int first;
1706 /* Add the relative address of the element. */
1707 if (reg.Indirect.ArrayID)
1708 first = array_first[reg.Indirect.ArrayID];
1709 else
1710 first = reg.Register.Index;
1711
1712 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
1713
1714 /* pull the value from index_reg */
1715 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1716 temp_reg, 0,
1717 V_SQ_ALU_SRC_LITERAL, 16,
1718 addr_reg, 0,
1719 temp_reg, 0);
1720 if (r)
1721 return r;
1722
1723 param = r600_get_lds_unique_index(name[first],
1724 index[first]);
1725
1726 } else {
1727 param = r600_get_lds_unique_index(name[reg.Register.Index],
1728 index[reg.Register.Index]);
1729 }
1730
1731 /* add to base_addr - passed in temp_reg.x */
1732 if (param) {
1733 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1734 temp_reg, 0,
1735 temp_reg, 0,
1736 V_SQ_ALU_SRC_LITERAL, param * 16);
1737 if (r)
1738 return r;
1739
1740 }
1741 return 0;
1742 }
1743
1744 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
1745 unsigned dst_reg)
1746 {
1747 struct r600_bytecode_alu alu;
1748 int r, i;
1749
1750 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
1751 ctx->bc->force_add_cf = 1;
1752 for (i = 1; i < 4; i++) {
1753 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1754 temp_reg, i,
1755 temp_reg, 0,
1756 V_SQ_ALU_SRC_LITERAL, 4 * i);
1757 if (r)
1758 return r;
1759 }
1760 for (i = 0; i < 4; i++) {
1761 /* emit an LDS_READ_RET */
1762 memset(&alu, 0, sizeof(alu));
1763 alu.op = LDS_OP1_LDS_READ_RET;
1764 alu.src[0].sel = temp_reg;
1765 alu.src[0].chan = i;
1766 alu.src[1].sel = V_SQ_ALU_SRC_0;
1767 alu.src[2].sel = V_SQ_ALU_SRC_0;
1768 alu.dst.chan = 0;
1769 alu.is_lds_idx_op = true;
1770 alu.last = 1;
1771 r = r600_bytecode_add_alu(ctx->bc, &alu);
1772 if (r)
1773 return r;
1774 }
1775 for (i = 0; i < 4; i++) {
1776 /* then read from LDS_OQ_A_POP */
1777 memset(&alu, 0, sizeof(alu));
1778
1779 alu.op = ALU_OP1_MOV;
1780 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
1781 alu.src[0].chan = 0;
1782 alu.dst.sel = dst_reg;
1783 alu.dst.chan = i;
1784 alu.dst.write = 1;
1785 alu.last = 1;
1786 r = r600_bytecode_add_alu(ctx->bc, &alu);
1787 if (r)
1788 return r;
1789 }
1790 return 0;
1791 }
1792
1793 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1794 {
1795 int r;
1796 unsigned temp_reg = r600_get_temp(ctx);
1797
1798 r = get_lds_offset0(ctx, 2, temp_reg,
1799 src->Register.Dimension ? false : true);
1800 if (r)
1801 return r;
1802
1803 /* the base address is now in temp.x */
1804 r = r600_get_byte_address(ctx, temp_reg,
1805 NULL, src, ctx->tess_output_info, 1);
1806 if (r)
1807 return r;
1808
1809 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1810 if (r)
1811 return r;
1812 return 0;
1813 }
1814
1815 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1816 {
1817 int r;
1818 unsigned temp_reg = r600_get_temp(ctx);
1819
1820 /* t.x = ips * r0.y */
1821 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
1822 temp_reg, 0,
1823 ctx->tess_input_info, 0,
1824 0, 1);
1825
1826 if (r)
1827 return r;
1828
1829 /* the base address is now in temp.x */
1830 r = r600_get_byte_address(ctx, temp_reg,
1831 NULL, src, ctx->tess_input_info, 1);
1832 if (r)
1833 return r;
1834
1835 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1836 if (r)
1837 return r;
1838 return 0;
1839 }
1840
1841 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1842 {
1843 int r;
1844 unsigned temp_reg = r600_get_temp(ctx);
1845
1846 r = get_lds_offset0(ctx, 1, temp_reg,
1847 src->Register.Dimension ? false : true);
1848 if (r)
1849 return r;
1850 /* the base address is now in temp.x */
1851 r = r600_get_byte_address(ctx, temp_reg,
1852 NULL, src,
1853 ctx->tess_output_info, 1);
1854 if (r)
1855 return r;
1856
1857 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1858 if (r)
1859 return r;
1860 return 0;
1861 }
1862
1863 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
1864 {
1865 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1866 unsigned i;
1867
1868 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1869 struct tgsi_full_src_register *src = &inst->Src[i];
1870
1871 if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
1872 int treg = r600_get_temp(ctx);
1873 fetch_tes_input(ctx, src, treg);
1874 ctx->src[i].sel = treg;
1875 ctx->src[i].rel = 0;
1876 }
1877 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
1878 int treg = r600_get_temp(ctx);
1879 fetch_tcs_input(ctx, src, treg);
1880 ctx->src[i].sel = treg;
1881 ctx->src[i].rel = 0;
1882 }
1883 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
1884 int treg = r600_get_temp(ctx);
1885 fetch_tcs_output(ctx, src, treg);
1886 ctx->src[i].sel = treg;
1887 ctx->src[i].rel = 0;
1888 }
1889 }
1890 return 0;
1891 }
1892
1893 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1894 {
1895 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1896 struct r600_bytecode_alu alu;
1897 int i, j, k, nconst, r;
1898
1899 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1900 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1901 nconst++;
1902 }
1903 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1904 }
1905 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1906 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1907 continue;
1908 }
1909
1910 if (ctx->src[i].rel) {
1911 int chan = inst->Src[i].Indirect.Swizzle;
1912 int treg = r600_get_temp(ctx);
1913 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1914 return r;
1915
1916 ctx->src[i].kc_bank = 0;
1917 ctx->src[i].kc_rel = 0;
1918 ctx->src[i].sel = treg;
1919 ctx->src[i].rel = 0;
1920 j--;
1921 } else if (j > 0) {
1922 int treg = r600_get_temp(ctx);
1923 for (k = 0; k < 4; k++) {
1924 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1925 alu.op = ALU_OP1_MOV;
1926 alu.src[0].sel = ctx->src[i].sel;
1927 alu.src[0].chan = k;
1928 alu.src[0].rel = ctx->src[i].rel;
1929 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1930 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1931 alu.dst.sel = treg;
1932 alu.dst.chan = k;
1933 alu.dst.write = 1;
1934 if (k == 3)
1935 alu.last = 1;
1936 r = r600_bytecode_add_alu(ctx->bc, &alu);
1937 if (r)
1938 return r;
1939 }
1940 ctx->src[i].sel = treg;
1941 ctx->src[i].rel =0;
1942 j--;
1943 }
1944 }
1945 return 0;
1946 }
1947
1948 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1949 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1950 {
1951 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1952 struct r600_bytecode_alu alu;
1953 int i, j, k, nliteral, r;
1954
1955 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1956 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1957 nliteral++;
1958 }
1959 }
1960 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1961 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1962 int treg = r600_get_temp(ctx);
1963 for (k = 0; k < 4; k++) {
1964 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1965 alu.op = ALU_OP1_MOV;
1966 alu.src[0].sel = ctx->src[i].sel;
1967 alu.src[0].chan = k;
1968 alu.src[0].value = ctx->src[i].value[k];
1969 alu.dst.sel = treg;
1970 alu.dst.chan = k;
1971 alu.dst.write = 1;
1972 if (k == 3)
1973 alu.last = 1;
1974 r = r600_bytecode_add_alu(ctx->bc, &alu);
1975 if (r)
1976 return r;
1977 }
1978 ctx->src[i].sel = treg;
1979 j--;
1980 }
1981 }
1982 return 0;
1983 }
1984
1985 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1986 {
1987 int i, r, count = ctx->shader->ninput;
1988
1989 for (i = 0; i < count; i++) {
1990 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1991 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1992 if (r)
1993 return r;
1994 }
1995 }
1996 return 0;
1997 }
1998
1999 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
2000 int stream, unsigned *stream_item_size)
2001 {
2002 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
2003 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
2004 int i, j, r;
2005
2006 /* Sanity checking. */
2007 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
2008 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
2009 r = -EINVAL;
2010 goto out_err;
2011 }
2012 for (i = 0; i < so->num_outputs; i++) {
2013 if (so->output[i].output_buffer >= 4) {
2014 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2015 so->output[i].output_buffer);
2016 r = -EINVAL;
2017 goto out_err;
2018 }
2019 }
2020
2021 /* Initialize locations where the outputs are stored. */
2022 for (i = 0; i < so->num_outputs; i++) {
2023
2024 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2025 start_comp[i] = so->output[i].start_component;
2026 /* Lower outputs with dst_offset < start_component.
2027 *
2028 * We can only output 4D vectors with a write mask, e.g. we can
2029 * only output the W component at offset 3, etc. If we want
2030 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2031 * to move it to X and output X. */
2032 if (so->output[i].dst_offset < so->output[i].start_component) {
2033 unsigned tmp = r600_get_temp(ctx);
2034
2035 for (j = 0; j < so->output[i].num_components; j++) {
2036 struct r600_bytecode_alu alu;
2037 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2038 alu.op = ALU_OP1_MOV;
2039 alu.src[0].sel = so_gpr[i];
2040 alu.src[0].chan = so->output[i].start_component + j;
2041
2042 alu.dst.sel = tmp;
2043 alu.dst.chan = j;
2044 alu.dst.write = 1;
2045 if (j == so->output[i].num_components - 1)
2046 alu.last = 1;
2047 r = r600_bytecode_add_alu(ctx->bc, &alu);
2048 if (r)
2049 return r;
2050 }
2051 start_comp[i] = 0;
2052 so_gpr[i] = tmp;
2053 }
2054 }
2055
2056 /* Write outputs to buffers. */
2057 for (i = 0; i < so->num_outputs; i++) {
2058 struct r600_bytecode_output output;
2059
2060 if (stream != -1 && stream != so->output[i].output_buffer)
2061 continue;
2062
2063 memset(&output, 0, sizeof(struct r600_bytecode_output));
2064 output.gpr = so_gpr[i];
2065 output.elem_size = so->output[i].num_components - 1;
2066 if (output.elem_size == 2)
2067 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2068 output.array_base = so->output[i].dst_offset - start_comp[i];
2069 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2070 output.burst_count = 1;
2071 /* array_size is an upper limit for the burst_count
2072 * with MEM_STREAM instructions */
2073 output.array_size = 0xFFF;
2074 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2075
2076 if (ctx->bc->chip_class >= EVERGREEN) {
2077 switch (so->output[i].output_buffer) {
2078 case 0:
2079 output.op = CF_OP_MEM_STREAM0_BUF0;
2080 break;
2081 case 1:
2082 output.op = CF_OP_MEM_STREAM0_BUF1;
2083 break;
2084 case 2:
2085 output.op = CF_OP_MEM_STREAM0_BUF2;
2086 break;
2087 case 3:
2088 output.op = CF_OP_MEM_STREAM0_BUF3;
2089 break;
2090 }
2091 output.op += so->output[i].stream * 4;
2092 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2093 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2094 } else {
2095 switch (so->output[i].output_buffer) {
2096 case 0:
2097 output.op = CF_OP_MEM_STREAM0;
2098 break;
2099 case 1:
2100 output.op = CF_OP_MEM_STREAM1;
2101 break;
2102 case 2:
2103 output.op = CF_OP_MEM_STREAM2;
2104 break;
2105 case 3:
2106 output.op = CF_OP_MEM_STREAM3;
2107 break;
2108 }
2109 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2110 }
2111 r = r600_bytecode_add_output(ctx->bc, &output);
2112 if (r)
2113 goto out_err;
2114 }
2115 return 0;
2116 out_err:
2117 return r;
2118 }
2119
2120 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2121 {
2122 struct r600_bytecode_alu alu;
2123 unsigned reg;
2124
2125 if (!ctx->shader->vs_out_edgeflag)
2126 return;
2127
2128 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2129
2130 /* clamp(x, 0, 1) */
2131 memset(&alu, 0, sizeof(alu));
2132 alu.op = ALU_OP1_MOV;
2133 alu.src[0].sel = reg;
2134 alu.dst.sel = reg;
2135 alu.dst.write = 1;
2136 alu.dst.clamp = 1;
2137 alu.last = 1;
2138 r600_bytecode_add_alu(ctx->bc, &alu);
2139
2140 memset(&alu, 0, sizeof(alu));
2141 alu.op = ALU_OP1_FLT_TO_INT;
2142 alu.src[0].sel = reg;
2143 alu.dst.sel = reg;
2144 alu.dst.write = 1;
2145 alu.last = 1;
2146 r600_bytecode_add_alu(ctx->bc, &alu);
2147 }
2148
2149 static int generate_gs_copy_shader(struct r600_context *rctx,
2150 struct r600_pipe_shader *gs,
2151 struct pipe_stream_output_info *so)
2152 {
2153 struct r600_shader_ctx ctx = {};
2154 struct r600_shader *gs_shader = &gs->shader;
2155 struct r600_pipe_shader *cshader;
2156 int ocnt = gs_shader->noutput;
2157 struct r600_bytecode_alu alu;
2158 struct r600_bytecode_vtx vtx;
2159 struct r600_bytecode_output output;
2160 struct r600_bytecode_cf *cf_jump, *cf_pop,
2161 *last_exp_pos = NULL, *last_exp_param = NULL;
2162 int i, j, next_clip_pos = 61, next_param = 0;
2163 int ring;
2164 bool only_ring_0 = true;
2165 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2166 if (!cshader)
2167 return 0;
2168
2169 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2170 sizeof(struct r600_shader_io));
2171
2172 cshader->shader.noutput = ocnt;
2173
2174 ctx.shader = &cshader->shader;
2175 ctx.bc = &ctx.shader->bc;
2176 ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
2177
2178 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2179 rctx->screen->has_compressed_msaa_texturing);
2180
2181 ctx.bc->isa = rctx->isa;
2182
2183 cf_jump = NULL;
2184 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2185
2186 /* R0.x = R0.x & 0x3fffffff */
2187 memset(&alu, 0, sizeof(alu));
2188 alu.op = ALU_OP2_AND_INT;
2189 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2190 alu.src[1].value = 0x3fffffff;
2191 alu.dst.write = 1;
2192 r600_bytecode_add_alu(ctx.bc, &alu);
2193
2194 /* R0.y = R0.x >> 30 */
2195 memset(&alu, 0, sizeof(alu));
2196 alu.op = ALU_OP2_LSHR_INT;
2197 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2198 alu.src[1].value = 0x1e;
2199 alu.dst.chan = 1;
2200 alu.dst.write = 1;
2201 alu.last = 1;
2202 r600_bytecode_add_alu(ctx.bc, &alu);
2203
2204 /* fetch vertex data from GSVS ring */
2205 for (i = 0; i < ocnt; ++i) {
2206 struct r600_shader_io *out = &ctx.shader->output[i];
2207
2208 out->gpr = i + 1;
2209 out->ring_offset = i * 16;
2210
2211 memset(&vtx, 0, sizeof(vtx));
2212 vtx.op = FETCH_OP_VFETCH;
2213 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2214 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2215 vtx.mega_fetch_count = 16;
2216 vtx.offset = out->ring_offset;
2217 vtx.dst_gpr = out->gpr;
2218 vtx.src_gpr = 0;
2219 vtx.dst_sel_x = 0;
2220 vtx.dst_sel_y = 1;
2221 vtx.dst_sel_z = 2;
2222 vtx.dst_sel_w = 3;
2223 if (rctx->b.chip_class >= EVERGREEN) {
2224 vtx.use_const_fields = 1;
2225 } else {
2226 vtx.data_format = FMT_32_32_32_32_FLOAT;
2227 }
2228
2229 r600_bytecode_add_vtx(ctx.bc, &vtx);
2230 }
2231 ctx.temp_reg = i + 1;
2232 for (ring = 3; ring >= 0; --ring) {
2233 bool enabled = false;
2234 for (i = 0; i < so->num_outputs; i++) {
2235 if (so->output[i].stream == ring) {
2236 enabled = true;
2237 if (ring > 0)
2238 only_ring_0 = false;
2239 break;
2240 }
2241 }
2242 if (ring != 0 && !enabled) {
2243 cshader->shader.ring_item_sizes[ring] = 0;
2244 continue;
2245 }
2246
2247 if (cf_jump) {
2248 // Patch up jump label
2249 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2250 cf_pop = ctx.bc->cf_last;
2251
2252 cf_jump->cf_addr = cf_pop->id + 2;
2253 cf_jump->pop_count = 1;
2254 cf_pop->cf_addr = cf_pop->id + 2;
2255 cf_pop->pop_count = 1;
2256 }
2257
2258 /* PRED_SETE_INT __, R0.y, ring */
2259 memset(&alu, 0, sizeof(alu));
2260 alu.op = ALU_OP2_PRED_SETE_INT;
2261 alu.src[0].chan = 1;
2262 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2263 alu.src[1].value = ring;
2264 alu.execute_mask = 1;
2265 alu.update_pred = 1;
2266 alu.last = 1;
2267 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2268
2269 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2270 cf_jump = ctx.bc->cf_last;
2271
2272 if (enabled)
2273 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2274 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2275 }
2276
2277 /* bc adds nops - copy it */
2278 if (ctx.bc->chip_class == R600) {
2279 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2280 alu.op = ALU_OP0_NOP;
2281 alu.last = 1;
2282 r600_bytecode_add_alu(ctx.bc, &alu);
2283
2284 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2285 }
2286
2287 /* export vertex data */
2288 /* XXX factor out common code with r600_shader_from_tgsi ? */
2289 for (i = 0; i < ocnt; ++i) {
2290 struct r600_shader_io *out = &ctx.shader->output[i];
2291 bool instream0 = true;
2292 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2293 continue;
2294
2295 for (j = 0; j < so->num_outputs; j++) {
2296 if (so->output[j].register_index == i) {
2297 if (so->output[j].stream == 0)
2298 break;
2299 if (so->output[j].stream > 0)
2300 instream0 = false;
2301 }
2302 }
2303 if (!instream0)
2304 continue;
2305 memset(&output, 0, sizeof(output));
2306 output.gpr = out->gpr;
2307 output.elem_size = 3;
2308 output.swizzle_x = 0;
2309 output.swizzle_y = 1;
2310 output.swizzle_z = 2;
2311 output.swizzle_w = 3;
2312 output.burst_count = 1;
2313 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2314 output.op = CF_OP_EXPORT;
2315 switch (out->name) {
2316 case TGSI_SEMANTIC_POSITION:
2317 output.array_base = 60;
2318 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2319 break;
2320
2321 case TGSI_SEMANTIC_PSIZE:
2322 output.array_base = 61;
2323 if (next_clip_pos == 61)
2324 next_clip_pos = 62;
2325 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2326 output.swizzle_y = 7;
2327 output.swizzle_z = 7;
2328 output.swizzle_w = 7;
2329 ctx.shader->vs_out_misc_write = 1;
2330 ctx.shader->vs_out_point_size = 1;
2331 break;
2332 case TGSI_SEMANTIC_LAYER:
2333 if (out->spi_sid) {
2334 /* duplicate it as PARAM to pass to the pixel shader */
2335 output.array_base = next_param++;
2336 r600_bytecode_add_output(ctx.bc, &output);
2337 last_exp_param = ctx.bc->cf_last;
2338 }
2339 output.array_base = 61;
2340 if (next_clip_pos == 61)
2341 next_clip_pos = 62;
2342 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2343 output.swizzle_x = 7;
2344 output.swizzle_y = 7;
2345 output.swizzle_z = 0;
2346 output.swizzle_w = 7;
2347 ctx.shader->vs_out_misc_write = 1;
2348 ctx.shader->vs_out_layer = 1;
2349 break;
2350 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2351 if (out->spi_sid) {
2352 /* duplicate it as PARAM to pass to the pixel shader */
2353 output.array_base = next_param++;
2354 r600_bytecode_add_output(ctx.bc, &output);
2355 last_exp_param = ctx.bc->cf_last;
2356 }
2357 output.array_base = 61;
2358 if (next_clip_pos == 61)
2359 next_clip_pos = 62;
2360 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2361 ctx.shader->vs_out_misc_write = 1;
2362 ctx.shader->vs_out_viewport = 1;
2363 output.swizzle_x = 7;
2364 output.swizzle_y = 7;
2365 output.swizzle_z = 7;
2366 output.swizzle_w = 0;
2367 break;
2368 case TGSI_SEMANTIC_CLIPDIST:
2369 /* spi_sid is 0 for clipdistance outputs that were generated
2370 * for clipvertex - we don't need to pass them to PS */
2371 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2372 if (out->spi_sid) {
2373 /* duplicate it as PARAM to pass to the pixel shader */
2374 output.array_base = next_param++;
2375 r600_bytecode_add_output(ctx.bc, &output);
2376 last_exp_param = ctx.bc->cf_last;
2377 }
2378 output.array_base = next_clip_pos++;
2379 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2380 break;
2381 case TGSI_SEMANTIC_FOG:
2382 output.swizzle_y = 4; /* 0 */
2383 output.swizzle_z = 4; /* 0 */
2384 output.swizzle_w = 5; /* 1 */
2385 break;
2386 default:
2387 output.array_base = next_param++;
2388 break;
2389 }
2390 r600_bytecode_add_output(ctx.bc, &output);
2391 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2392 last_exp_param = ctx.bc->cf_last;
2393 else
2394 last_exp_pos = ctx.bc->cf_last;
2395 }
2396
2397 if (!last_exp_pos) {
2398 memset(&output, 0, sizeof(output));
2399 output.gpr = 0;
2400 output.elem_size = 3;
2401 output.swizzle_x = 7;
2402 output.swizzle_y = 7;
2403 output.swizzle_z = 7;
2404 output.swizzle_w = 7;
2405 output.burst_count = 1;
2406 output.type = 2;
2407 output.op = CF_OP_EXPORT;
2408 output.array_base = 60;
2409 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2410 r600_bytecode_add_output(ctx.bc, &output);
2411 last_exp_pos = ctx.bc->cf_last;
2412 }
2413
2414 if (!last_exp_param) {
2415 memset(&output, 0, sizeof(output));
2416 output.gpr = 0;
2417 output.elem_size = 3;
2418 output.swizzle_x = 7;
2419 output.swizzle_y = 7;
2420 output.swizzle_z = 7;
2421 output.swizzle_w = 7;
2422 output.burst_count = 1;
2423 output.type = 2;
2424 output.op = CF_OP_EXPORT;
2425 output.array_base = next_param++;
2426 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2427 r600_bytecode_add_output(ctx.bc, &output);
2428 last_exp_param = ctx.bc->cf_last;
2429 }
2430
2431 last_exp_pos->op = CF_OP_EXPORT_DONE;
2432 last_exp_param->op = CF_OP_EXPORT_DONE;
2433
2434 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2435 cf_pop = ctx.bc->cf_last;
2436
2437 cf_jump->cf_addr = cf_pop->id + 2;
2438 cf_jump->pop_count = 1;
2439 cf_pop->cf_addr = cf_pop->id + 2;
2440 cf_pop->pop_count = 1;
2441
2442 if (ctx.bc->chip_class == CAYMAN)
2443 cm_bytecode_add_cf_end(ctx.bc);
2444 else {
2445 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2446 ctx.bc->cf_last->end_of_program = 1;
2447 }
2448
2449 gs->gs_copy_shader = cshader;
2450 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2451
2452 ctx.bc->nstack = 1;
2453
2454 return r600_bytecode_build(ctx.bc);
2455 }
2456
2457 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2458 {
2459 if (ind) {
2460 struct r600_bytecode_alu alu;
2461 int r;
2462
2463 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2464 alu.op = ALU_OP2_ADD_INT;
2465 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2466 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2467 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2468 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2469 alu.dst.write = 1;
2470 alu.last = 1;
2471 r = r600_bytecode_add_alu(ctx->bc, &alu);
2472 if (r)
2473 return r;
2474 }
2475 return 0;
2476 }
2477
2478 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind)
2479 {
2480 struct r600_bytecode_output output;
2481 int i, k, ring_offset;
2482 int effective_stream = stream == -1 ? 0 : stream;
2483 int idx = 0;
2484
2485 for (i = 0; i < ctx->shader->noutput; i++) {
2486 if (ctx->gs_for_vs) {
2487 /* for ES we need to lookup corresponding ring offset expected by GS
2488 * (map this output to GS input by name and sid) */
2489 /* FIXME precompute offsets */
2490 ring_offset = -1;
2491 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2492 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2493 struct r600_shader_io *out = &ctx->shader->output[i];
2494 if (in->name == out->name && in->sid == out->sid)
2495 ring_offset = in->ring_offset;
2496 }
2497
2498 if (ring_offset == -1)
2499 continue;
2500 } else {
2501 ring_offset = idx * 16;
2502 idx++;
2503 }
2504
2505 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2506 continue;
2507 /* next_ring_offset after parsing input decls contains total size of
2508 * single vertex data, gs_next_vertex - current vertex index */
2509 if (!ind)
2510 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2511
2512 memset(&output, 0, sizeof(struct r600_bytecode_output));
2513 output.gpr = ctx->shader->output[i].gpr;
2514 output.elem_size = 3;
2515 output.comp_mask = 0xF;
2516 output.burst_count = 1;
2517
2518 if (ind)
2519 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2520 else
2521 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2522
2523 switch (stream) {
2524 default:
2525 case 0:
2526 output.op = CF_OP_MEM_RING; break;
2527 case 1:
2528 output.op = CF_OP_MEM_RING1; break;
2529 case 2:
2530 output.op = CF_OP_MEM_RING2; break;
2531 case 3:
2532 output.op = CF_OP_MEM_RING3; break;
2533 }
2534
2535 if (ind) {
2536 output.array_base = ring_offset >> 2; /* in dwords */
2537 output.array_size = 0xfff;
2538 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2539 } else
2540 output.array_base = ring_offset >> 2; /* in dwords */
2541 r600_bytecode_add_output(ctx->bc, &output);
2542 }
2543
2544 ++ctx->gs_next_vertex;
2545 return 0;
2546 }
2547
2548
2549 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2550 {
2551 int r;
2552 struct r600_bytecode_vtx vtx;
2553 int temp_val = ctx->temp_reg;
2554 /* need to store the TCS output somewhere */
2555 r = single_alu_op2(ctx, ALU_OP1_MOV,
2556 temp_val, 0,
2557 V_SQ_ALU_SRC_LITERAL, 0,
2558 0, 0);
2559 if (r)
2560 return r;
2561
2562 /* used by VS/TCS */
2563 if (ctx->tess_input_info) {
2564 /* fetch tcs input values into resv space */
2565 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2566 vtx.op = FETCH_OP_VFETCH;
2567 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2568 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2569 vtx.mega_fetch_count = 16;
2570 vtx.data_format = FMT_32_32_32_32;
2571 vtx.num_format_all = 2;
2572 vtx.format_comp_all = 1;
2573 vtx.use_const_fields = 0;
2574 vtx.endian = r600_endian_swap(32);
2575 vtx.srf_mode_all = 1;
2576 vtx.offset = 0;
2577 vtx.dst_gpr = ctx->tess_input_info;
2578 vtx.dst_sel_x = 0;
2579 vtx.dst_sel_y = 1;
2580 vtx.dst_sel_z = 2;
2581 vtx.dst_sel_w = 3;
2582 vtx.src_gpr = temp_val;
2583 vtx.src_sel_x = 0;
2584
2585 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2586 if (r)
2587 return r;
2588 }
2589
2590 /* used by TCS/TES */
2591 if (ctx->tess_output_info) {
2592 /* fetch tcs output values into resv space */
2593 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2594 vtx.op = FETCH_OP_VFETCH;
2595 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2596 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2597 vtx.mega_fetch_count = 16;
2598 vtx.data_format = FMT_32_32_32_32;
2599 vtx.num_format_all = 2;
2600 vtx.format_comp_all = 1;
2601 vtx.use_const_fields = 0;
2602 vtx.endian = r600_endian_swap(32);
2603 vtx.srf_mode_all = 1;
2604 vtx.offset = 16;
2605 vtx.dst_gpr = ctx->tess_output_info;
2606 vtx.dst_sel_x = 0;
2607 vtx.dst_sel_y = 1;
2608 vtx.dst_sel_z = 2;
2609 vtx.dst_sel_w = 3;
2610 vtx.src_gpr = temp_val;
2611 vtx.src_sel_x = 0;
2612
2613 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2614 if (r)
2615 return r;
2616 }
2617 return 0;
2618 }
2619
2620 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2621 {
2622 int i, j, r;
2623 int temp_reg;
2624
2625 /* fetch tcs input values into input_vals */
2626 ctx->tess_input_info = r600_get_temp(ctx);
2627 ctx->tess_output_info = 0;
2628 r = r600_fetch_tess_io_info(ctx);
2629 if (r)
2630 return r;
2631
2632 temp_reg = r600_get_temp(ctx);
2633 /* dst reg contains LDS address stride * idx */
2634 /* MUL vertexID, vertex_dw_stride */
2635 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2636 temp_reg, 0,
2637 ctx->tess_input_info, 1,
2638 0, 1); /* rel id in r0.y? */
2639 if (r)
2640 return r;
2641
2642 for (i = 0; i < ctx->shader->noutput; i++) {
2643 struct r600_bytecode_alu alu;
2644 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2645
2646 if (param) {
2647 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2648 temp_reg, 1,
2649 temp_reg, 0,
2650 V_SQ_ALU_SRC_LITERAL, param * 16);
2651 if (r)
2652 return r;
2653 }
2654
2655 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2656 temp_reg, 2,
2657 temp_reg, param ? 1 : 0,
2658 V_SQ_ALU_SRC_LITERAL, 8);
2659 if (r)
2660 return r;
2661
2662
2663 for (j = 0; j < 2; j++) {
2664 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2665 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2666 alu.op = LDS_OP3_LDS_WRITE_REL;
2667 alu.src[0].sel = temp_reg;
2668 alu.src[0].chan = chan;
2669 alu.src[1].sel = ctx->shader->output[i].gpr;
2670 alu.src[1].chan = j * 2;
2671 alu.src[2].sel = ctx->shader->output[i].gpr;
2672 alu.src[2].chan = (j * 2) + 1;
2673 alu.last = 1;
2674 alu.dst.chan = 0;
2675 alu.lds_idx = 1;
2676 alu.is_lds_idx_op = true;
2677 r = r600_bytecode_add_alu(ctx->bc, &alu);
2678 if (r)
2679 return r;
2680 }
2681 }
2682 return 0;
2683 }
2684
2685 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
2686 {
2687 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2688 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
2689 int i, r, lasti;
2690 int temp_reg = r600_get_temp(ctx);
2691 struct r600_bytecode_alu alu;
2692 unsigned write_mask = dst->Register.WriteMask;
2693
2694 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
2695 return 0;
2696
2697 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
2698 if (r)
2699 return r;
2700
2701 /* the base address is now in temp.x */
2702 r = r600_get_byte_address(ctx, temp_reg,
2703 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
2704 if (r)
2705 return r;
2706
2707 /* LDS write */
2708 lasti = tgsi_last_instruction(write_mask);
2709 for (i = 1; i <= lasti; i++) {
2710
2711 if (!(write_mask & (1 << i)))
2712 continue;
2713 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2714 temp_reg, i,
2715 temp_reg, 0,
2716 V_SQ_ALU_SRC_LITERAL, 4 * i);
2717 if (r)
2718 return r;
2719 }
2720
2721 for (i = 0; i <= lasti; i++) {
2722 if (!(write_mask & (1 << i)))
2723 continue;
2724
2725 if ((i == 0 && ((write_mask & 3) == 3)) ||
2726 (i == 2 && ((write_mask & 0xc) == 0xc))) {
2727 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2728 alu.op = LDS_OP3_LDS_WRITE_REL;
2729 alu.src[0].sel = temp_reg;
2730 alu.src[0].chan = i;
2731
2732 alu.src[1].sel = dst->Register.Index;
2733 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2734 alu.src[1].chan = i;
2735
2736 alu.src[2].sel = dst->Register.Index;
2737 alu.src[2].sel += ctx->file_offset[dst->Register.File];
2738 alu.src[2].chan = i + 1;
2739 alu.lds_idx = 1;
2740 alu.dst.chan = 0;
2741 alu.last = 1;
2742 alu.is_lds_idx_op = true;
2743 r = r600_bytecode_add_alu(ctx->bc, &alu);
2744 if (r)
2745 return r;
2746 i += 1;
2747 continue;
2748 }
2749 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2750 alu.op = LDS_OP2_LDS_WRITE;
2751 alu.src[0].sel = temp_reg;
2752 alu.src[0].chan = i;
2753
2754 alu.src[1].sel = dst->Register.Index;
2755 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2756 alu.src[1].chan = i;
2757
2758 alu.src[2].sel = V_SQ_ALU_SRC_0;
2759 alu.dst.chan = 0;
2760 alu.last = 1;
2761 alu.is_lds_idx_op = true;
2762 r = r600_bytecode_add_alu(ctx->bc, &alu);
2763 if (r)
2764 return r;
2765 }
2766 return 0;
2767 }
2768
2769 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
2770 int output_idx)
2771 {
2772 int param;
2773 unsigned temp_reg = r600_get_temp(ctx);
2774 unsigned name = ctx->shader->output[output_idx].name;
2775 int dreg = ctx->shader->output[output_idx].gpr;
2776 int r;
2777
2778 param = r600_get_lds_unique_index(name, 0);
2779 r = get_lds_offset0(ctx, 1, temp_reg, true);
2780 if (r)
2781 return r;
2782
2783 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2784 temp_reg, 0,
2785 temp_reg, 0,
2786 V_SQ_ALU_SRC_LITERAL, param * 16);
2787 if (r)
2788 return r;
2789
2790 do_lds_fetch_values(ctx, temp_reg, dreg);
2791 return 0;
2792 }
2793
2794 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
2795 {
2796 unsigned i;
2797 int stride, outer_comps, inner_comps;
2798 int tessinner_idx = -1, tessouter_idx = -1;
2799 int r;
2800 int temp_reg = r600_get_temp(ctx);
2801 int treg[3] = {-1, -1, -1};
2802 struct r600_bytecode_alu alu;
2803 struct r600_bytecode_cf *cf_jump, *cf_pop;
2804
2805 /* only execute factor emission for invocation 0 */
2806 /* PRED_SETE_INT __, R0.x, 0 */
2807 memset(&alu, 0, sizeof(alu));
2808 alu.op = ALU_OP2_PRED_SETE_INT;
2809 alu.src[0].chan = 2;
2810 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2811 alu.execute_mask = 1;
2812 alu.update_pred = 1;
2813 alu.last = 1;
2814 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2815
2816 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
2817 cf_jump = ctx->bc->cf_last;
2818
2819 treg[0] = r600_get_temp(ctx);
2820 switch (ctx->shader->tcs_prim_mode) {
2821 case PIPE_PRIM_LINES:
2822 stride = 8; /* 2 dwords, 1 vec2 store */
2823 outer_comps = 2;
2824 inner_comps = 0;
2825 break;
2826 case PIPE_PRIM_TRIANGLES:
2827 stride = 16; /* 4 dwords, 1 vec4 store */
2828 outer_comps = 3;
2829 inner_comps = 1;
2830 treg[1] = r600_get_temp(ctx);
2831 break;
2832 case PIPE_PRIM_QUADS:
2833 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2834 outer_comps = 4;
2835 inner_comps = 2;
2836 treg[1] = r600_get_temp(ctx);
2837 treg[2] = r600_get_temp(ctx);
2838 break;
2839 default:
2840 assert(0);
2841 return -1;
2842 }
2843
2844 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2845 /* TF_WRITE takes index in R.x, value in R.y */
2846 for (i = 0; i < ctx->shader->noutput; i++) {
2847 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSINNER)
2848 tessinner_idx = i;
2849 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSOUTER)
2850 tessouter_idx = i;
2851 }
2852
2853 if (tessouter_idx == -1)
2854 return -1;
2855
2856 if (tessinner_idx == -1 && inner_comps)
2857 return -1;
2858
2859 if (tessouter_idx != -1) {
2860 r = r600_tess_factor_read(ctx, tessouter_idx);
2861 if (r)
2862 return r;
2863 }
2864
2865 if (tessinner_idx != -1) {
2866 r = r600_tess_factor_read(ctx, tessinner_idx);
2867 if (r)
2868 return r;
2869 }
2870
2871 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2872 /* r.x = relpatchid(r0.y) * tf_stride */
2873
2874 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2875 /* add incoming r0.w to it: t.x = t.x + r0.w */
2876 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2877 temp_reg, 0,
2878 0, 1,
2879 V_SQ_ALU_SRC_LITERAL, stride,
2880 0, 3);
2881 if (r)
2882 return r;
2883
2884 for (i = 0; i < outer_comps + inner_comps; i++) {
2885 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
2886 int out_comp = i >= outer_comps ? i - outer_comps : i;
2887
2888 if (ctx->shader->tcs_prim_mode == PIPE_PRIM_LINES) {
2889 if (out_comp == 1)
2890 out_comp = 0;
2891 else if (out_comp == 0)
2892 out_comp = 1;
2893 }
2894
2895 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2896 treg[i / 2], (2 * (i % 2)),
2897 temp_reg, 0,
2898 V_SQ_ALU_SRC_LITERAL, 4 * i);
2899 if (r)
2900 return r;
2901 r = single_alu_op2(ctx, ALU_OP1_MOV,
2902 treg[i / 2], 1 + (2 * (i%2)),
2903 ctx->shader->output[out_idx].gpr, out_comp,
2904 0, 0);
2905 if (r)
2906 return r;
2907 }
2908 for (i = 0; i < outer_comps + inner_comps; i++) {
2909 struct r600_bytecode_gds gds;
2910
2911 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
2912 gds.src_gpr = treg[i / 2];
2913 gds.src_sel_x = 2 * (i % 2);
2914 gds.src_sel_y = 1 + (2 * (i % 2));
2915 gds.src_sel_z = 4;
2916 gds.dst_sel_x = 7;
2917 gds.dst_sel_y = 7;
2918 gds.dst_sel_z = 7;
2919 gds.dst_sel_w = 7;
2920 gds.op = FETCH_OP_TF_WRITE;
2921 r = r600_bytecode_add_gds(ctx->bc, &gds);
2922 if (r)
2923 return r;
2924 }
2925
2926 // Patch up jump label
2927 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
2928 cf_pop = ctx->bc->cf_last;
2929
2930 cf_jump->cf_addr = cf_pop->id + 2;
2931 cf_jump->pop_count = 1;
2932 cf_pop->cf_addr = cf_pop->id + 2;
2933 cf_pop->pop_count = 1;
2934
2935 return 0;
2936 }
2937
2938 static int r600_shader_from_tgsi(struct r600_context *rctx,
2939 struct r600_pipe_shader *pipeshader,
2940 union r600_shader_key key)
2941 {
2942 struct r600_screen *rscreen = rctx->screen;
2943 struct r600_shader *shader = &pipeshader->shader;
2944 struct tgsi_token *tokens = pipeshader->selector->tokens;
2945 struct pipe_stream_output_info so = pipeshader->selector->so;
2946 struct tgsi_full_immediate *immediate;
2947 struct r600_shader_ctx ctx;
2948 struct r600_bytecode_output output[ARRAY_SIZE(shader->output)];
2949 unsigned output_done, noutput;
2950 unsigned opcode;
2951 int i, j, k, r = 0;
2952 int next_param_base = 0, next_clip_base;
2953 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
2954 bool indirect_gprs;
2955 bool ring_outputs = false;
2956 bool lds_outputs = false;
2957 bool lds_inputs = false;
2958 bool pos_emitted = false;
2959
2960 ctx.bc = &shader->bc;
2961 ctx.shader = shader;
2962 ctx.native_integers = true;
2963
2964 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
2965 rscreen->has_compressed_msaa_texturing);
2966 ctx.tokens = tokens;
2967 tgsi_scan_shader(tokens, &ctx.info);
2968 shader->indirect_files = ctx.info.indirect_files;
2969
2970 shader->uses_doubles = ctx.info.uses_doubles;
2971 shader->uses_atomics = ctx.info.file_mask[TGSI_FILE_HW_ATOMIC];
2972 shader->nsys_inputs = 0;
2973
2974 shader->uses_images = ctx.info.file_count[TGSI_FILE_IMAGE] > 0;
2975 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
2976 tgsi_parse_init(&ctx.parse, tokens);
2977 ctx.type = ctx.info.processor;
2978 shader->processor_type = ctx.type;
2979 ctx.bc->type = shader->processor_type;
2980
2981 switch (ctx.type) {
2982 case PIPE_SHADER_VERTEX:
2983 shader->vs_as_gs_a = key.vs.as_gs_a;
2984 shader->vs_as_es = key.vs.as_es;
2985 shader->vs_as_ls = key.vs.as_ls;
2986 shader->atomic_base = key.vs.first_atomic_counter;
2987 if (shader->vs_as_es)
2988 ring_outputs = true;
2989 if (shader->vs_as_ls)
2990 lds_outputs = true;
2991 break;
2992 case PIPE_SHADER_GEOMETRY:
2993 ring_outputs = true;
2994 shader->atomic_base = key.gs.first_atomic_counter;
2995 shader->gs_tri_strip_adj_fix = key.gs.tri_strip_adj_fix;
2996 break;
2997 case PIPE_SHADER_TESS_CTRL:
2998 shader->tcs_prim_mode = key.tcs.prim_mode;
2999 shader->atomic_base = key.tcs.first_atomic_counter;
3000 lds_outputs = true;
3001 lds_inputs = true;
3002 break;
3003 case PIPE_SHADER_TESS_EVAL:
3004 shader->tes_as_es = key.tes.as_es;
3005 shader->atomic_base = key.tes.first_atomic_counter;
3006 lds_inputs = true;
3007 if (shader->tes_as_es)
3008 ring_outputs = true;
3009 break;
3010 case PIPE_SHADER_FRAGMENT:
3011 shader->two_side = key.ps.color_two_side;
3012 shader->atomic_base = key.ps.first_atomic_counter;
3013 break;
3014 default:
3015 break;
3016 }
3017
3018 if (shader->vs_as_es || shader->tes_as_es) {
3019 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
3020 } else {
3021 ctx.gs_for_vs = NULL;
3022 }
3023
3024 ctx.next_ring_offset = 0;
3025 ctx.gs_out_ring_offset = 0;
3026 ctx.gs_next_vertex = 0;
3027 ctx.gs_stream_output_info = &so;
3028
3029 ctx.face_gpr = -1;
3030 ctx.fixed_pt_position_gpr = -1;
3031 ctx.fragcoord_input = -1;
3032 ctx.colors_used = 0;
3033 ctx.clip_vertex_write = 0;
3034
3035 shader->nr_ps_color_exports = 0;
3036 shader->nr_ps_max_color_exports = 0;
3037
3038
3039 /* register allocations */
3040 /* Values [0,127] correspond to GPR[0..127].
3041 * Values [128,159] correspond to constant buffer bank 0
3042 * Values [160,191] correspond to constant buffer bank 1
3043 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3044 * Values [256,287] correspond to constant buffer bank 2 (EG)
3045 * Values [288,319] correspond to constant buffer bank 3 (EG)
3046 * Other special values are shown in the list below.
3047 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3048 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3049 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3050 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3051 * 248 SQ_ALU_SRC_0: special constant 0.0.
3052 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3053 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3054 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3055 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3056 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3057 * 254 SQ_ALU_SRC_PV: previous vector result.
3058 * 255 SQ_ALU_SRC_PS: previous scalar result.
3059 */
3060 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3061 ctx.file_offset[i] = 0;
3062 }
3063
3064 if (ctx.type == PIPE_SHADER_VERTEX) {
3065
3066 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3067 if (ctx.info.num_inputs)
3068 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3069 }
3070 if (ctx.type == PIPE_SHADER_FRAGMENT) {
3071 if (ctx.bc->chip_class >= EVERGREEN)
3072 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3073 else
3074 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3075 }
3076 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3077 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3078 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3079 }
3080 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3081 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3082 if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3083 bool add_tesscoord = false, add_tess_inout = false;
3084 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3085 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3086 /* if we have tesscoord save one reg */
3087 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3088 add_tesscoord = true;
3089 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3090 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3091 add_tess_inout = true;
3092 }
3093 if (add_tesscoord || add_tess_inout)
3094 ctx.file_offset[TGSI_FILE_INPUT]++;
3095 if (add_tess_inout)
3096 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3097 }
3098
3099 ctx.file_offset[TGSI_FILE_OUTPUT] =
3100 ctx.file_offset[TGSI_FILE_INPUT] +
3101 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3102 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3103 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3104
3105 /* Outside the GPR range. This will be translated to one of the
3106 * kcache banks later. */
3107 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3108
3109 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3110 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3111 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
3112 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
3113 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
3114
3115 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3116 ctx.tess_input_info = ctx.bc->ar_reg + 3;
3117 ctx.tess_output_info = ctx.bc->ar_reg + 4;
3118 ctx.temp_reg = ctx.bc->ar_reg + 5;
3119 } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3120 ctx.tess_input_info = 0;
3121 ctx.tess_output_info = ctx.bc->ar_reg + 3;
3122 ctx.temp_reg = ctx.bc->ar_reg + 4;
3123 } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
3124 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
3125 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
3126 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
3127 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
3128 ctx.temp_reg = ctx.bc->ar_reg + 7;
3129 if (ctx.shader->gs_tri_strip_adj_fix) {
3130 ctx.gs_rotated_input[0] = ctx.bc->ar_reg + 7;
3131 ctx.gs_rotated_input[1] = ctx.bc->ar_reg + 8;
3132 ctx.temp_reg += 2;
3133 } else {
3134 ctx.gs_rotated_input[0] = 0;
3135 ctx.gs_rotated_input[1] = 1;
3136 }
3137 } else {
3138 ctx.temp_reg = ctx.bc->ar_reg + 3;
3139 }
3140
3141 shader->max_arrays = 0;
3142 shader->num_arrays = 0;
3143 if (indirect_gprs) {
3144
3145 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3146 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3147 ctx.file_offset[TGSI_FILE_OUTPUT] -
3148 ctx.file_offset[TGSI_FILE_INPUT],
3149 0x0F);
3150 }
3151 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3152 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3153 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3154 ctx.file_offset[TGSI_FILE_OUTPUT],
3155 0x0F);
3156 }
3157 }
3158
3159 ctx.nliterals = 0;
3160 ctx.literals = NULL;
3161
3162 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3163 ctx.info.colors_written == 1;
3164 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3165 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3166
3167 if (shader->vs_as_gs_a)
3168 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3169
3170 if (ctx.type == PIPE_SHADER_TESS_EVAL)
3171 r600_fetch_tess_io_info(&ctx);
3172
3173 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3174 tgsi_parse_token(&ctx.parse);
3175 switch (ctx.parse.FullToken.Token.Type) {
3176 case TGSI_TOKEN_TYPE_IMMEDIATE:
3177 immediate = &ctx.parse.FullToken.FullImmediate;
3178 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3179 if(ctx.literals == NULL) {
3180 r = -ENOMEM;
3181 goto out_err;
3182 }
3183 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3184 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3185 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3186 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3187 ctx.nliterals++;
3188 break;
3189 case TGSI_TOKEN_TYPE_DECLARATION:
3190 r = tgsi_declaration(&ctx);
3191 if (r)
3192 goto out_err;
3193 break;
3194 case TGSI_TOKEN_TYPE_INSTRUCTION:
3195 case TGSI_TOKEN_TYPE_PROPERTY:
3196 break;
3197 default:
3198 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3199 r = -EINVAL;
3200 goto out_err;
3201 }
3202 }
3203
3204 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3205 shader->ring_item_sizes[1] = 0;
3206 shader->ring_item_sizes[2] = 0;
3207 shader->ring_item_sizes[3] = 0;
3208
3209 /* Process two side if needed */
3210 if (shader->two_side && ctx.colors_used) {
3211 int i, count = ctx.shader->ninput;
3212 unsigned next_lds_loc = ctx.shader->nlds;
3213
3214 /* additional inputs will be allocated right after the existing inputs,
3215 * we won't need them after the color selection, so we don't need to
3216 * reserve these gprs for the rest of the shader code and to adjust
3217 * output offsets etc. */
3218 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3219 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3220
3221 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3222 if (ctx.face_gpr == -1) {
3223 i = ctx.shader->ninput++;
3224 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3225 ctx.shader->input[i].spi_sid = 0;
3226 ctx.shader->input[i].gpr = gpr++;
3227 ctx.face_gpr = ctx.shader->input[i].gpr;
3228 }
3229
3230 for (i = 0; i < count; i++) {
3231 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3232 int ni = ctx.shader->ninput++;
3233 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3234 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3235 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3236 ctx.shader->input[ni].gpr = gpr++;
3237 // TGSI to LLVM needs to know the lds position of inputs.
3238 // Non LLVM path computes it later (in process_twoside_color)
3239 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3240 ctx.shader->input[i].back_color_input = ni;
3241 if (ctx.bc->chip_class >= EVERGREEN) {
3242 if ((r = evergreen_interp_input(&ctx, ni)))
3243 return r;
3244 }
3245 }
3246 }
3247 }
3248
3249 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3250 shader->nr_ps_max_color_exports = 8;
3251
3252 if (ctx.fragcoord_input >= 0) {
3253 if (ctx.bc->chip_class == CAYMAN) {
3254 for (j = 0 ; j < 4; j++) {
3255 struct r600_bytecode_alu alu;
3256 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3257 alu.op = ALU_OP1_RECIP_IEEE;
3258 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3259 alu.src[0].chan = 3;
3260
3261 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3262 alu.dst.chan = j;
3263 alu.dst.write = (j == 3);
3264 alu.last = 1;
3265 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3266 return r;
3267 }
3268 } else {
3269 struct r600_bytecode_alu alu;
3270 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3271 alu.op = ALU_OP1_RECIP_IEEE;
3272 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3273 alu.src[0].chan = 3;
3274
3275 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3276 alu.dst.chan = 3;
3277 alu.dst.write = 1;
3278 alu.last = 1;
3279 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3280 return r;
3281 }
3282 }
3283
3284 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3285 struct r600_bytecode_alu alu;
3286 int r;
3287
3288 /* GS thread with no output workaround - emit a cut at start of GS */
3289 if (ctx.bc->chip_class == R600)
3290 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3291
3292 for (j = 0; j < 4; j++) {
3293 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3294 alu.op = ALU_OP1_MOV;
3295 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3296 alu.src[0].value = 0;
3297 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3298 alu.dst.write = 1;
3299 alu.last = 1;
3300 r = r600_bytecode_add_alu(ctx.bc, &alu);
3301 if (r)
3302 return r;
3303 }
3304
3305 if (ctx.shader->gs_tri_strip_adj_fix) {
3306 r = single_alu_op2(&ctx, ALU_OP2_AND_INT,
3307 ctx.gs_rotated_input[0], 2,
3308 0, 2,
3309 V_SQ_ALU_SRC_LITERAL, 1);
3310 if (r)
3311 return r;
3312
3313 for (i = 0; i < 6; i++) {
3314 int rotated = (i + 4) % 6;
3315 int offset_reg = i / 3;
3316 int offset_chan = i % 3;
3317 int rotated_offset_reg = rotated / 3;
3318 int rotated_offset_chan = rotated % 3;
3319
3320 if (offset_reg == 0 && offset_chan == 2)
3321 offset_chan = 3;
3322 if (rotated_offset_reg == 0 && rotated_offset_chan == 2)
3323 rotated_offset_chan = 3;
3324
3325 r = single_alu_op3(&ctx, ALU_OP3_CNDE_INT,
3326 ctx.gs_rotated_input[offset_reg], offset_chan,
3327 ctx.gs_rotated_input[0], 2,
3328 offset_reg, offset_chan,
3329 rotated_offset_reg, rotated_offset_chan);
3330 if (r)
3331 return r;
3332 }
3333 }
3334 }
3335
3336 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3337 r600_fetch_tess_io_info(&ctx);
3338
3339 if (shader->two_side && ctx.colors_used) {
3340 if ((r = process_twoside_color_inputs(&ctx)))
3341 return r;
3342 }
3343
3344 tgsi_parse_init(&ctx.parse, tokens);
3345 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3346 tgsi_parse_token(&ctx.parse);
3347 switch (ctx.parse.FullToken.Token.Type) {
3348 case TGSI_TOKEN_TYPE_INSTRUCTION:
3349 r = tgsi_is_supported(&ctx);
3350 if (r)
3351 goto out_err;
3352 ctx.max_driver_temp_used = 0;
3353 /* reserve first tmp for everyone */
3354 r600_get_temp(&ctx);
3355
3356 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3357 if ((r = tgsi_split_constant(&ctx)))
3358 goto out_err;
3359 if ((r = tgsi_split_literal_constant(&ctx)))
3360 goto out_err;
3361 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3362 if ((r = tgsi_split_gs_inputs(&ctx)))
3363 goto out_err;
3364 } else if (lds_inputs) {
3365 if ((r = tgsi_split_lds_inputs(&ctx)))
3366 goto out_err;
3367 }
3368 if (ctx.bc->chip_class == CAYMAN)
3369 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3370 else if (ctx.bc->chip_class >= EVERGREEN)
3371 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3372 else
3373 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3374 r = ctx.inst_info->process(&ctx);
3375 if (r)
3376 goto out_err;
3377
3378 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3379 r = r600_store_tcs_output(&ctx);
3380 if (r)
3381 goto out_err;
3382 }
3383 break;
3384 default:
3385 break;
3386 }
3387 }
3388
3389 /* Reset the temporary register counter. */
3390 ctx.max_driver_temp_used = 0;
3391
3392 noutput = shader->noutput;
3393
3394 if (!ring_outputs && ctx.clip_vertex_write) {
3395 unsigned clipdist_temp[2];
3396
3397 clipdist_temp[0] = r600_get_temp(&ctx);
3398 clipdist_temp[1] = r600_get_temp(&ctx);
3399
3400 /* need to convert a clipvertex write into clipdistance writes and not export
3401 the clip vertex anymore */
3402
3403 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3404 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3405 shader->output[noutput].gpr = clipdist_temp[0];
3406 noutput++;
3407 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3408 shader->output[noutput].gpr = clipdist_temp[1];
3409 noutput++;
3410
3411 /* reset spi_sid for clipvertex output to avoid confusing spi */
3412 shader->output[ctx.cv_output].spi_sid = 0;
3413
3414 shader->clip_dist_write = 0xFF;
3415
3416 for (i = 0; i < 8; i++) {
3417 int oreg = i >> 2;
3418 int ochan = i & 3;
3419
3420 for (j = 0; j < 4; j++) {
3421 struct r600_bytecode_alu alu;
3422 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3423 alu.op = ALU_OP2_DOT4;
3424 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3425 alu.src[0].chan = j;
3426
3427 alu.src[1].sel = 512 + i;
3428 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3429 alu.src[1].chan = j;
3430
3431 alu.dst.sel = clipdist_temp[oreg];
3432 alu.dst.chan = j;
3433 alu.dst.write = (j == ochan);
3434 if (j == 3)
3435 alu.last = 1;
3436 r = r600_bytecode_add_alu(ctx.bc, &alu);
3437 if (r)
3438 return r;
3439 }
3440 }
3441 }
3442
3443 /* Add stream outputs. */
3444 if (so.num_outputs) {
3445 bool emit = false;
3446 if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
3447 emit = true;
3448 if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
3449 emit = true;
3450 if (emit)
3451 emit_streamout(&ctx, &so, -1, NULL);
3452 }
3453 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3454 convert_edgeflag_to_int(&ctx);
3455
3456 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3457 r600_emit_tess_factor(&ctx);
3458
3459 if (lds_outputs) {
3460 if (ctx.type == PIPE_SHADER_VERTEX) {
3461 if (ctx.shader->noutput)
3462 emit_lds_vs_writes(&ctx);
3463 }
3464 } else if (ring_outputs) {
3465 if (shader->vs_as_es || shader->tes_as_es) {
3466 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3467 ctx.gs_export_gpr_tregs[1] = -1;
3468 ctx.gs_export_gpr_tregs[2] = -1;
3469 ctx.gs_export_gpr_tregs[3] = -1;
3470
3471 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3472 }
3473 } else {
3474 /* Export output */
3475 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3476
3477 for (i = 0, j = 0; i < noutput; i++, j++) {
3478 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3479 output[j].gpr = shader->output[i].gpr;
3480 output[j].elem_size = 3;
3481 output[j].swizzle_x = 0;
3482 output[j].swizzle_y = 1;
3483 output[j].swizzle_z = 2;
3484 output[j].swizzle_w = 3;
3485 output[j].burst_count = 1;
3486 output[j].type = -1;
3487 output[j].op = CF_OP_EXPORT;
3488 switch (ctx.type) {
3489 case PIPE_SHADER_VERTEX:
3490 case PIPE_SHADER_TESS_EVAL:
3491 switch (shader->output[i].name) {
3492 case TGSI_SEMANTIC_POSITION:
3493 output[j].array_base = 60;
3494 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3495 pos_emitted = true;
3496 break;
3497
3498 case TGSI_SEMANTIC_PSIZE:
3499 output[j].array_base = 61;
3500 output[j].swizzle_y = 7;
3501 output[j].swizzle_z = 7;
3502 output[j].swizzle_w = 7;
3503 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3504 pos_emitted = true;
3505 break;
3506 case TGSI_SEMANTIC_EDGEFLAG:
3507 output[j].array_base = 61;
3508 output[j].swizzle_x = 7;
3509 output[j].swizzle_y = 0;
3510 output[j].swizzle_z = 7;
3511 output[j].swizzle_w = 7;
3512 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3513 pos_emitted = true;
3514 break;
3515 case TGSI_SEMANTIC_LAYER:
3516 /* spi_sid is 0 for outputs that are
3517 * not consumed by PS */
3518 if (shader->output[i].spi_sid) {
3519 output[j].array_base = next_param_base++;
3520 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3521 j++;
3522 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3523 }
3524 output[j].array_base = 61;
3525 output[j].swizzle_x = 7;
3526 output[j].swizzle_y = 7;
3527 output[j].swizzle_z = 0;
3528 output[j].swizzle_w = 7;
3529 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3530 pos_emitted = true;
3531 break;
3532 case TGSI_SEMANTIC_VIEWPORT_INDEX:
3533 /* spi_sid is 0 for outputs that are
3534 * not consumed by PS */
3535 if (shader->output[i].spi_sid) {
3536 output[j].array_base = next_param_base++;
3537 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3538 j++;
3539 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3540 }
3541 output[j].array_base = 61;
3542 output[j].swizzle_x = 7;
3543 output[j].swizzle_y = 7;
3544 output[j].swizzle_z = 7;
3545 output[j].swizzle_w = 0;
3546 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3547 pos_emitted = true;
3548 break;
3549 case TGSI_SEMANTIC_CLIPVERTEX:
3550 j--;
3551 break;
3552 case TGSI_SEMANTIC_CLIPDIST:
3553 output[j].array_base = next_clip_base++;
3554 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3555 pos_emitted = true;
3556 /* spi_sid is 0 for clipdistance outputs that were generated
3557 * for clipvertex - we don't need to pass them to PS */
3558 if (shader->output[i].spi_sid) {
3559 j++;
3560 /* duplicate it as PARAM to pass to the pixel shader */
3561 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3562 output[j].array_base = next_param_base++;
3563 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3564 }
3565 break;
3566 case TGSI_SEMANTIC_FOG:
3567 output[j].swizzle_y = 4; /* 0 */
3568 output[j].swizzle_z = 4; /* 0 */
3569 output[j].swizzle_w = 5; /* 1 */
3570 break;
3571 case TGSI_SEMANTIC_PRIMID:
3572 output[j].swizzle_x = 2;
3573 output[j].swizzle_y = 4; /* 0 */
3574 output[j].swizzle_z = 4; /* 0 */
3575 output[j].swizzle_w = 4; /* 0 */
3576 break;
3577 }
3578
3579 break;
3580 case PIPE_SHADER_FRAGMENT:
3581 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
3582 /* never export more colors than the number of CBs */
3583 if (shader->output[i].sid >= max_color_exports) {
3584 /* skip export */
3585 j--;
3586 continue;
3587 }
3588 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3589 output[j].array_base = shader->output[i].sid;
3590 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3591 shader->nr_ps_color_exports++;
3592 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
3593 for (k = 1; k < max_color_exports; k++) {
3594 j++;
3595 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3596 output[j].gpr = shader->output[i].gpr;
3597 output[j].elem_size = 3;
3598 output[j].swizzle_x = 0;
3599 output[j].swizzle_y = 1;
3600 output[j].swizzle_z = 2;
3601 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3602 output[j].burst_count = 1;
3603 output[j].array_base = k;
3604 output[j].op = CF_OP_EXPORT;
3605 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3606 shader->nr_ps_color_exports++;
3607 }
3608 }
3609 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
3610 output[j].array_base = 61;
3611 output[j].swizzle_x = 2;
3612 output[j].swizzle_y = 7;
3613 output[j].swizzle_z = output[j].swizzle_w = 7;
3614 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3615 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
3616 output[j].array_base = 61;
3617 output[j].swizzle_x = 7;
3618 output[j].swizzle_y = 1;
3619 output[j].swizzle_z = output[j].swizzle_w = 7;
3620 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3621 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3622 output[j].array_base = 61;
3623 output[j].swizzle_x = 7;
3624 output[j].swizzle_y = 7;
3625 output[j].swizzle_z = 0;
3626 output[j].swizzle_w = 7;
3627 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3628 } else {
3629 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
3630 r = -EINVAL;
3631 goto out_err;
3632 }
3633 break;
3634 case PIPE_SHADER_TESS_CTRL:
3635 break;
3636 default:
3637 R600_ERR("unsupported processor type %d\n", ctx.type);
3638 r = -EINVAL;
3639 goto out_err;
3640 }
3641
3642 if (output[j].type==-1) {
3643 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3644 output[j].array_base = next_param_base++;
3645 }
3646 }
3647
3648 /* add fake position export */
3649 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
3650 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3651 output[j].gpr = 0;
3652 output[j].elem_size = 3;
3653 output[j].swizzle_x = 7;
3654 output[j].swizzle_y = 7;
3655 output[j].swizzle_z = 7;
3656 output[j].swizzle_w = 7;
3657 output[j].burst_count = 1;
3658 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3659 output[j].array_base = 60;
3660 output[j].op = CF_OP_EXPORT;
3661 j++;
3662 }
3663
3664 /* add fake param output for vertex shader if no param is exported */
3665 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
3666 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3667 output[j].gpr = 0;
3668 output[j].elem_size = 3;
3669 output[j].swizzle_x = 7;
3670 output[j].swizzle_y = 7;
3671 output[j].swizzle_z = 7;
3672 output[j].swizzle_w = 7;
3673 output[j].burst_count = 1;
3674 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3675 output[j].array_base = 0;
3676 output[j].op = CF_OP_EXPORT;
3677 j++;
3678 }
3679
3680 /* add fake pixel export */
3681 if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
3682 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3683 output[j].gpr = 0;
3684 output[j].elem_size = 3;
3685 output[j].swizzle_x = 7;
3686 output[j].swizzle_y = 7;
3687 output[j].swizzle_z = 7;
3688 output[j].swizzle_w = 7;
3689 output[j].burst_count = 1;
3690 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3691 output[j].array_base = 0;
3692 output[j].op = CF_OP_EXPORT;
3693 j++;
3694 shader->nr_ps_color_exports++;
3695 }
3696
3697 noutput = j;
3698
3699 /* set export done on last export of each type */
3700 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
3701 if (!(output_done & (1 << output[i].type))) {
3702 output_done |= (1 << output[i].type);
3703 output[i].op = CF_OP_EXPORT_DONE;
3704 }
3705 }
3706 /* add output to bytecode */
3707 for (i = 0; i < noutput; i++) {
3708 r = r600_bytecode_add_output(ctx.bc, &output[i]);
3709 if (r)
3710 goto out_err;
3711 }
3712 }
3713
3714 /* add program end */
3715 if (ctx.bc->chip_class == CAYMAN)
3716 cm_bytecode_add_cf_end(ctx.bc);
3717 else {
3718 const struct cf_op_info *last = NULL;
3719
3720 if (ctx.bc->cf_last)
3721 last = r600_isa_cf(ctx.bc->cf_last->op);
3722
3723 /* alu clause instructions don't have EOP bit, so add NOP */
3724 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS || ctx.bc->cf_last->op == CF_OP_POP || ctx.bc->cf_last->op == CF_OP_GDS)
3725 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
3726
3727 ctx.bc->cf_last->end_of_program = 1;
3728 }
3729
3730 /* check GPR limit - we have 124 = 128 - 4
3731 * (4 are reserved as alu clause temporary registers) */
3732 if (ctx.bc->ngpr > 124) {
3733 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
3734 r = -ENOMEM;
3735 goto out_err;
3736 }
3737
3738 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3739 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
3740 return r;
3741 }
3742
3743 free(ctx.literals);
3744 tgsi_parse_free(&ctx.parse);
3745 return 0;
3746 out_err:
3747 free(ctx.literals);
3748 tgsi_parse_free(&ctx.parse);
3749 return r;
3750 }
3751
3752 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
3753 {
3754 const unsigned tgsi_opcode =
3755 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
3756 R600_ERR("%s tgsi opcode unsupported\n",
3757 tgsi_get_opcode_name(tgsi_opcode));
3758 return -EINVAL;
3759 }
3760
3761 static int tgsi_end(struct r600_shader_ctx *ctx)
3762 {
3763 return 0;
3764 }
3765
3766 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
3767 const struct r600_shader_src *shader_src,
3768 unsigned chan)
3769 {
3770 bc_src->sel = shader_src->sel;
3771 bc_src->chan = shader_src->swizzle[chan];
3772 bc_src->neg = shader_src->neg;
3773 bc_src->abs = shader_src->abs;
3774 bc_src->rel = shader_src->rel;
3775 bc_src->value = shader_src->value[bc_src->chan];
3776 bc_src->kc_bank = shader_src->kc_bank;
3777 bc_src->kc_rel = shader_src->kc_rel;
3778 }
3779
3780 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
3781 {
3782 bc_src->abs = 1;
3783 bc_src->neg = 0;
3784 }
3785
3786 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
3787 {
3788 bc_src->neg = !bc_src->neg;
3789 }
3790
3791 static void tgsi_dst(struct r600_shader_ctx *ctx,
3792 const struct tgsi_full_dst_register *tgsi_dst,
3793 unsigned swizzle,
3794 struct r600_bytecode_alu_dst *r600_dst)
3795 {
3796 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3797
3798 r600_dst->sel = tgsi_dst->Register.Index;
3799 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
3800 r600_dst->chan = swizzle;
3801 r600_dst->write = 1;
3802 if (inst->Instruction.Saturate) {
3803 r600_dst->clamp = 1;
3804 }
3805 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
3806 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
3807 return;
3808 }
3809 }
3810 if (tgsi_dst->Register.Indirect)
3811 r600_dst->rel = V_SQ_REL_RELATIVE;
3812
3813 }
3814
3815 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
3816 {
3817 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3818 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3819 struct r600_bytecode_alu alu;
3820 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3821 int use_tmp = 0;
3822
3823 if (singledest) {
3824 switch (write_mask) {
3825 case 0x1:
3826 write_mask = 0x3;
3827 break;
3828 case 0x2:
3829 use_tmp = 1;
3830 write_mask = 0x3;
3831 break;
3832 case 0x4:
3833 write_mask = 0xc;
3834 break;
3835 case 0x8:
3836 write_mask = 0xc;
3837 use_tmp = 3;
3838 break;
3839 }
3840 }
3841
3842 lasti = tgsi_last_instruction(write_mask);
3843 for (i = 0; i <= lasti; i++) {
3844
3845 if (!(write_mask & (1 << i)))
3846 continue;
3847
3848 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3849
3850 if (singledest) {
3851 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3852 if (use_tmp) {
3853 alu.dst.sel = ctx->temp_reg;
3854 alu.dst.chan = i;
3855 alu.dst.write = 1;
3856 }
3857 if (i == 1 || i == 3)
3858 alu.dst.write = 0;
3859 } else
3860 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3861
3862 alu.op = ctx->inst_info->op;
3863 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
3864 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3865 } else if (!swap) {
3866 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3867 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
3868 }
3869 } else {
3870 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
3871 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
3872 }
3873
3874 /* handle some special cases */
3875 if (i == 1 || i == 3) {
3876 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
3877 case TGSI_OPCODE_DABS:
3878 r600_bytecode_src_set_abs(&alu.src[0]);
3879 break;
3880 default:
3881 break;
3882 }
3883 }
3884 if (i == lasti) {
3885 alu.last = 1;
3886 }
3887 r = r600_bytecode_add_alu(ctx->bc, &alu);
3888 if (r)
3889 return r;
3890 }
3891
3892 if (use_tmp) {
3893 write_mask = inst->Dst[0].Register.WriteMask;
3894
3895 /* move result from temp to dst */
3896 for (i = 0; i <= lasti; i++) {
3897 if (!(write_mask & (1 << i)))
3898 continue;
3899
3900 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3901 alu.op = ALU_OP1_MOV;
3902 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3903 alu.src[0].sel = ctx->temp_reg;
3904 alu.src[0].chan = use_tmp - 1;
3905 alu.last = (i == lasti);
3906
3907 r = r600_bytecode_add_alu(ctx->bc, &alu);
3908 if (r)
3909 return r;
3910 }
3911 }
3912 return 0;
3913 }
3914
3915 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
3916 {
3917 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3918 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3919 /* confirm writemasking */
3920 if ((write_mask & 0x3) != 0x3 &&
3921 (write_mask & 0xc) != 0xc) {
3922 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
3923 return -1;
3924 }
3925 return tgsi_op2_64_params(ctx, false, false);
3926 }
3927
3928 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
3929 {
3930 return tgsi_op2_64_params(ctx, true, false);
3931 }
3932
3933 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
3934 {
3935 return tgsi_op2_64_params(ctx, true, true);
3936 }
3937
3938 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
3939 {
3940 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3941 struct r600_bytecode_alu alu;
3942 int i, j, r;
3943 int lasti = 3;
3944 int tmp = r600_get_temp(ctx);
3945
3946 for (i = 0; i < lasti + 1; i++) {
3947
3948 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3949 alu.op = ctx->inst_info->op;
3950 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3951 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
3952 }
3953
3954 if (inst->Dst[0].Register.WriteMask & (1 << i))
3955 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3956 else
3957 alu.dst.sel = tmp;
3958
3959 alu.dst.chan = i;
3960 alu.is_op3 = 1;
3961 if (i == lasti) {
3962 alu.last = 1;
3963 }
3964 r = r600_bytecode_add_alu(ctx->bc, &alu);
3965 if (r)
3966 return r;
3967 }
3968 return 0;
3969 }
3970
3971 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
3972 {
3973 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3974 struct r600_bytecode_alu alu;
3975 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3976 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3977 /* use temp register if trans_only and more than one dst component */
3978 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
3979 unsigned op = ctx->inst_info->op;
3980
3981 if (op == ALU_OP2_MUL_IEEE &&
3982 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
3983 op = ALU_OP2_MUL;
3984
3985 for (i = 0; i <= lasti; i++) {
3986 if (!(write_mask & (1 << i)))
3987 continue;
3988
3989 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3990 if (use_tmp) {
3991 alu.dst.sel = ctx->temp_reg;
3992 alu.dst.chan = i;
3993 alu.dst.write = 1;
3994 } else
3995 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3996
3997 alu.op = op;
3998 if (!swap) {
3999 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4000 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4001 }
4002 } else {
4003 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4004 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4005 }
4006 if (i == lasti || trans_only) {
4007 alu.last = 1;
4008 }
4009 r = r600_bytecode_add_alu(ctx->bc, &alu);
4010 if (r)
4011 return r;
4012 }
4013
4014 if (use_tmp) {
4015 /* move result from temp to dst */
4016 for (i = 0; i <= lasti; i++) {
4017 if (!(write_mask & (1 << i)))
4018 continue;
4019
4020 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4021 alu.op = ALU_OP1_MOV;
4022 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4023 alu.src[0].sel = ctx->temp_reg;
4024 alu.src[0].chan = i;
4025 alu.last = (i == lasti);
4026
4027 r = r600_bytecode_add_alu(ctx->bc, &alu);
4028 if (r)
4029 return r;
4030 }
4031 }
4032 return 0;
4033 }
4034
4035 static int tgsi_op2(struct r600_shader_ctx *ctx)
4036 {
4037 return tgsi_op2_s(ctx, 0, 0);
4038 }
4039
4040 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
4041 {
4042 return tgsi_op2_s(ctx, 1, 0);
4043 }
4044
4045 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
4046 {
4047 return tgsi_op2_s(ctx, 0, 1);
4048 }
4049
4050 static int tgsi_ineg(struct r600_shader_ctx *ctx)
4051 {
4052 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4053 struct r600_bytecode_alu alu;
4054 int i, r;
4055 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4056
4057 for (i = 0; i < lasti + 1; i++) {
4058
4059 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4060 continue;
4061 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4062 alu.op = ctx->inst_info->op;
4063
4064 alu.src[0].sel = V_SQ_ALU_SRC_0;
4065
4066 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4067
4068 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4069
4070 if (i == lasti) {
4071 alu.last = 1;
4072 }
4073 r = r600_bytecode_add_alu(ctx->bc, &alu);
4074 if (r)
4075 return r;
4076 }
4077 return 0;
4078
4079 }
4080
4081 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4082 {
4083 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4084 struct r600_bytecode_alu alu;
4085 int i, r;
4086 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4087
4088 for (i = 0; i < lasti + 1; i++) {
4089
4090 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4091 continue;
4092 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4093 alu.op = ALU_OP1_MOV;
4094
4095 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4096
4097 if (i == 1 || i == 3)
4098 r600_bytecode_src_toggle_neg(&alu.src[0]);
4099 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4100
4101 if (i == lasti) {
4102 alu.last = 1;
4103 }
4104 r = r600_bytecode_add_alu(ctx->bc, &alu);
4105 if (r)
4106 return r;
4107 }
4108 return 0;
4109
4110 }
4111
4112 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4113 {
4114 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4115 struct r600_bytecode_alu alu;
4116 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4117 int i, j, r;
4118
4119 for (i = 0; i <= 3; i++) {
4120 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4121 alu.op = ctx->inst_info->op;
4122
4123 alu.dst.sel = ctx->temp_reg;
4124 alu.dst.chan = i;
4125 alu.dst.write = 1;
4126 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4127 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4128 }
4129
4130 if (i == 3)
4131 alu.last = 1;
4132
4133 r = r600_bytecode_add_alu(ctx->bc, &alu);
4134 if (r)
4135 return r;
4136 }
4137
4138 /* Replicate significand result across channels. */
4139 for (i = 0; i <= 3; i++) {
4140 if (!(write_mask & (1 << i)))
4141 continue;
4142
4143 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4144 alu.op = ALU_OP1_MOV;
4145 alu.src[0].chan = (i & 1) + 2;
4146 alu.src[0].sel = ctx->temp_reg;
4147
4148 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4149 alu.dst.write = 1;
4150 alu.last = 1;
4151 r = r600_bytecode_add_alu(ctx->bc, &alu);
4152 if (r)
4153 return r;
4154 }
4155
4156 for (i = 0; i <= 3; i++) {
4157 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4158 /* MOV third channels to writemask dst1 */
4159 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4160 alu.op = ALU_OP1_MOV;
4161 alu.src[0].chan = 1;
4162 alu.src[0].sel = ctx->temp_reg;
4163
4164 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4165 alu.last = 1;
4166 r = r600_bytecode_add_alu(ctx->bc, &alu);
4167 if (r)
4168 return r;
4169 break;
4170 }
4171 }
4172 return 0;
4173 }
4174
4175
4176 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4177 {
4178 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4179 struct r600_bytecode_alu alu;
4180 int i, r;
4181 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4182
4183 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4184 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4185
4186 for (i = 0; i <= (lasti+1)/2; i++) {
4187 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4188 alu.op = ctx->inst_info->op;
4189
4190 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4191 alu.dst.sel = ctx->temp_reg;
4192 alu.dst.chan = i;
4193 alu.dst.write = 1;
4194 alu.last = 1;
4195
4196 r = r600_bytecode_add_alu(ctx->bc, &alu);
4197 if (r)
4198 return r;
4199 }
4200
4201 for (i = 0; i <= lasti; i++) {
4202 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4203 alu.op = ALU_OP1_FLT32_TO_FLT64;
4204
4205 alu.src[0].chan = i/2;
4206 if (i%2 == 0)
4207 alu.src[0].sel = ctx->temp_reg;
4208 else {
4209 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4210 alu.src[0].value = 0x0;
4211 }
4212 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4213 alu.last = i == lasti;
4214
4215 r = r600_bytecode_add_alu(ctx->bc, &alu);
4216 if (r)
4217 return r;
4218 }
4219
4220 return 0;
4221 }
4222
4223 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4224 {
4225 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4226 struct r600_bytecode_alu alu;
4227 int i, r;
4228 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4229
4230 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4231 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4232
4233 for (i = 0; i <= lasti; i++) {
4234 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4235 alu.op = ALU_OP1_FLT64_TO_FLT32;
4236
4237 r600_bytecode_src(&alu.src[0], &ctx->src[0], fp64_switch(i));
4238 alu.dst.chan = i;
4239 alu.dst.sel = ctx->temp_reg;
4240 alu.dst.write = i%2 == 0;
4241 alu.last = i == lasti;
4242
4243 r = r600_bytecode_add_alu(ctx->bc, &alu);
4244 if (r)
4245 return r;
4246 }
4247
4248 for (i = 0; i <= (lasti+1)/2; i++) {
4249 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4250 alu.op = ctx->inst_info->op;
4251
4252 alu.src[0].chan = i*2;
4253 alu.src[0].sel = ctx->temp_reg;
4254 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4255 alu.last = 1;
4256
4257 r = r600_bytecode_add_alu(ctx->bc, &alu);
4258 if (r)
4259 return r;
4260 }
4261
4262 return 0;
4263 }
4264
4265 static int cayman_emit_unary_double_raw(struct r600_bytecode *bc,
4266 unsigned op,
4267 int dst_reg,
4268 struct r600_shader_src *src,
4269 bool abs)
4270 {
4271 struct r600_bytecode_alu alu;
4272 const int last_slot = 3;
4273 int r;
4274
4275 /* these have to write the result to X/Y by the looks of it */
4276 for (int i = 0 ; i < last_slot; i++) {
4277 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4278 alu.op = op;
4279
4280 r600_bytecode_src(&alu.src[0], src, 1);
4281 r600_bytecode_src(&alu.src[1], src, 0);
4282
4283 if (abs)
4284 r600_bytecode_src_set_abs(&alu.src[1]);
4285
4286 alu.dst.sel = dst_reg;
4287 alu.dst.chan = i;
4288 alu.dst.write = (i == 0 || i == 1);
4289
4290 if (bc->chip_class != CAYMAN || i == last_slot - 1)
4291 alu.last = 1;
4292 r = r600_bytecode_add_alu(bc, &alu);
4293 if (r)
4294 return r;
4295 }
4296
4297 return 0;
4298 }
4299
4300 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4301 {
4302 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4303 int i, r;
4304 struct r600_bytecode_alu alu;
4305 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4306 int t1 = ctx->temp_reg;
4307
4308 /* should only be one src regs */
4309 assert(inst->Instruction.NumSrcRegs == 1);
4310
4311 /* only support one double at a time */
4312 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4313 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4314
4315 r = cayman_emit_unary_double_raw(
4316 ctx->bc, ctx->inst_info->op, t1,
4317 &ctx->src[0],
4318 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4319 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT);
4320 if (r)
4321 return r;
4322
4323 for (i = 0 ; i <= lasti; i++) {
4324 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4325 continue;
4326 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4327 alu.op = ALU_OP1_MOV;
4328 alu.src[0].sel = t1;
4329 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
4330 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4331 alu.dst.write = 1;
4332 if (i == lasti)
4333 alu.last = 1;
4334 r = r600_bytecode_add_alu(ctx->bc, &alu);
4335 if (r)
4336 return r;
4337 }
4338 return 0;
4339 }
4340
4341 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
4342 {
4343 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4344 int i, j, r;
4345 struct r600_bytecode_alu alu;
4346 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4347
4348 for (i = 0 ; i < last_slot; i++) {
4349 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4350 alu.op = ctx->inst_info->op;
4351 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4352 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
4353
4354 /* RSQ should take the absolute value of src */
4355 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
4356 r600_bytecode_src_set_abs(&alu.src[j]);
4357 }
4358 }
4359 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4360 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4361
4362 if (i == last_slot - 1)
4363 alu.last = 1;
4364 r = r600_bytecode_add_alu(ctx->bc, &alu);
4365 if (r)
4366 return r;
4367 }
4368 return 0;
4369 }
4370
4371 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
4372 {
4373 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4374 int i, j, k, r;
4375 struct r600_bytecode_alu alu;
4376 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4377 int t1 = ctx->temp_reg;
4378
4379 for (k = 0; k <= lasti; k++) {
4380 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
4381 continue;
4382
4383 for (i = 0 ; i < 4; i++) {
4384 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4385 alu.op = ctx->inst_info->op;
4386 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4387 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
4388 }
4389 alu.dst.sel = t1;
4390 alu.dst.chan = i;
4391 alu.dst.write = (i == k);
4392 if (i == 3)
4393 alu.last = 1;
4394 r = r600_bytecode_add_alu(ctx->bc, &alu);
4395 if (r)
4396 return r;
4397 }
4398 }
4399
4400 for (i = 0 ; i <= lasti; i++) {
4401 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4402 continue;
4403 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4404 alu.op = ALU_OP1_MOV;
4405 alu.src[0].sel = t1;
4406 alu.src[0].chan = i;
4407 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4408 alu.dst.write = 1;
4409 if (i == lasti)
4410 alu.last = 1;
4411 r = r600_bytecode_add_alu(ctx->bc, &alu);
4412 if (r)
4413 return r;
4414 }
4415
4416 return 0;
4417 }
4418
4419
4420 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
4421 {
4422 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4423 int i, j, k, r;
4424 struct r600_bytecode_alu alu;
4425 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4426 int t1 = ctx->temp_reg;
4427
4428 /* t1 would get overwritten below if we actually tried to
4429 * multiply two pairs of doubles at a time. */
4430 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4431 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4432
4433 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4434
4435 for (i = 0; i < 4; i++) {
4436 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4437 alu.op = ctx->inst_info->op;
4438 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4439 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));
4440 }
4441 alu.dst.sel = t1;
4442 alu.dst.chan = i;
4443 alu.dst.write = 1;
4444 if (i == 3)
4445 alu.last = 1;
4446 r = r600_bytecode_add_alu(ctx->bc, &alu);
4447 if (r)
4448 return r;
4449 }
4450
4451 for (i = 0; i <= lasti; i++) {
4452 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4453 continue;
4454 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4455 alu.op = ALU_OP1_MOV;
4456 alu.src[0].sel = t1;
4457 alu.src[0].chan = i;
4458 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4459 alu.dst.write = 1;
4460 if (i == lasti)
4461 alu.last = 1;
4462 r = r600_bytecode_add_alu(ctx->bc, &alu);
4463 if (r)
4464 return r;
4465 }
4466
4467 return 0;
4468 }
4469
4470 /*
4471 * Emit RECIP_64 + MUL_64 to implement division.
4472 */
4473 static int cayman_ddiv_instr(struct r600_shader_ctx *ctx)
4474 {
4475 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4476 int r;
4477 struct r600_bytecode_alu alu;
4478 int t1 = ctx->temp_reg;
4479 int k;
4480
4481 /* Only support one double at a time. This is the same constraint as
4482 * in DMUL lowering. */
4483 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4484 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4485
4486 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4487
4488 r = cayman_emit_unary_double_raw(ctx->bc, ALU_OP2_RECIP_64, t1, &ctx->src[1], false);
4489 if (r)
4490 return r;
4491
4492 for (int i = 0; i < 4; i++) {
4493 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4494 alu.op = ALU_OP2_MUL_64;
4495
4496 r600_bytecode_src(&alu.src[0], &ctx->src[0], k * 2 + ((i == 3) ? 0 : 1));
4497
4498 alu.src[1].sel = t1;
4499 alu.src[1].chan = (i == 3) ? 0 : 1;
4500
4501 alu.dst.sel = t1;
4502 alu.dst.chan = i;
4503 alu.dst.write = 1;
4504 if (i == 3)
4505 alu.last = 1;
4506 r = r600_bytecode_add_alu(ctx->bc, &alu);
4507 if (r)
4508 return r;
4509 }
4510
4511 for (int i = 0; i < 2; i++) {
4512 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4513 alu.op = ALU_OP1_MOV;
4514 alu.src[0].sel = t1;
4515 alu.src[0].chan = i;
4516 tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
4517 alu.dst.write = 1;
4518 if (i == 1)
4519 alu.last = 1;
4520 r = r600_bytecode_add_alu(ctx->bc, &alu);
4521 if (r)
4522 return r;
4523 }
4524 return 0;
4525 }
4526
4527 /*
4528 * r600 - trunc to -PI..PI range
4529 * r700 - normalize by dividing by 2PI
4530 * see fdo bug 27901
4531 */
4532 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
4533 {
4534 int r;
4535 struct r600_bytecode_alu alu;
4536
4537 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4538 alu.op = ALU_OP3_MULADD;
4539 alu.is_op3 = 1;
4540
4541 alu.dst.chan = 0;
4542 alu.dst.sel = ctx->temp_reg;
4543 alu.dst.write = 1;
4544
4545 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4546
4547 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4548 alu.src[1].chan = 0;
4549 alu.src[1].value = u_bitcast_f2u(0.5f * M_1_PI);
4550 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4551 alu.src[2].chan = 0;
4552 alu.last = 1;
4553 r = r600_bytecode_add_alu(ctx->bc, &alu);
4554 if (r)
4555 return r;
4556
4557 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4558 alu.op = ALU_OP1_FRACT;
4559
4560 alu.dst.chan = 0;
4561 alu.dst.sel = ctx->temp_reg;
4562 alu.dst.write = 1;
4563
4564 alu.src[0].sel = ctx->temp_reg;
4565 alu.src[0].chan = 0;
4566 alu.last = 1;
4567 r = r600_bytecode_add_alu(ctx->bc, &alu);
4568 if (r)
4569 return r;
4570
4571 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4572 alu.op = ALU_OP3_MULADD;
4573 alu.is_op3 = 1;
4574
4575 alu.dst.chan = 0;
4576 alu.dst.sel = ctx->temp_reg;
4577 alu.dst.write = 1;
4578
4579 alu.src[0].sel = ctx->temp_reg;
4580 alu.src[0].chan = 0;
4581
4582 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4583 alu.src[1].chan = 0;
4584 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4585 alu.src[2].chan = 0;
4586
4587 if (ctx->bc->chip_class == R600) {
4588 alu.src[1].value = u_bitcast_f2u(2.0f * M_PI);
4589 alu.src[2].value = u_bitcast_f2u(-M_PI);
4590 } else {
4591 alu.src[1].sel = V_SQ_ALU_SRC_1;
4592 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4593 alu.src[2].neg = 1;
4594 }
4595
4596 alu.last = 1;
4597 r = r600_bytecode_add_alu(ctx->bc, &alu);
4598 if (r)
4599 return r;
4600 return 0;
4601 }
4602
4603 static int cayman_trig(struct r600_shader_ctx *ctx)
4604 {
4605 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4606 struct r600_bytecode_alu alu;
4607 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4608 int i, r;
4609
4610 r = tgsi_setup_trig(ctx);
4611 if (r)
4612 return r;
4613
4614
4615 for (i = 0; i < last_slot; i++) {
4616 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4617 alu.op = ctx->inst_info->op;
4618 alu.dst.chan = i;
4619
4620 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4621 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4622
4623 alu.src[0].sel = ctx->temp_reg;
4624 alu.src[0].chan = 0;
4625 if (i == last_slot - 1)
4626 alu.last = 1;
4627 r = r600_bytecode_add_alu(ctx->bc, &alu);
4628 if (r)
4629 return r;
4630 }
4631 return 0;
4632 }
4633
4634 static int tgsi_trig(struct r600_shader_ctx *ctx)
4635 {
4636 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4637 struct r600_bytecode_alu alu;
4638 int i, r;
4639 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4640
4641 r = tgsi_setup_trig(ctx);
4642 if (r)
4643 return r;
4644
4645 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4646 alu.op = ctx->inst_info->op;
4647 alu.dst.chan = 0;
4648 alu.dst.sel = ctx->temp_reg;
4649 alu.dst.write = 1;
4650
4651 alu.src[0].sel = ctx->temp_reg;
4652 alu.src[0].chan = 0;
4653 alu.last = 1;
4654 r = r600_bytecode_add_alu(ctx->bc, &alu);
4655 if (r)
4656 return r;
4657
4658 /* replicate result */
4659 for (i = 0; i < lasti + 1; i++) {
4660 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4661 continue;
4662
4663 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4664 alu.op = ALU_OP1_MOV;
4665
4666 alu.src[0].sel = ctx->temp_reg;
4667 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4668 if (i == lasti)
4669 alu.last = 1;
4670 r = r600_bytecode_add_alu(ctx->bc, &alu);
4671 if (r)
4672 return r;
4673 }
4674 return 0;
4675 }
4676
4677 static int tgsi_kill(struct r600_shader_ctx *ctx)
4678 {
4679 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4680 struct r600_bytecode_alu alu;
4681 int i, r;
4682
4683 for (i = 0; i < 4; i++) {
4684 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4685 alu.op = ctx->inst_info->op;
4686
4687 alu.dst.chan = i;
4688
4689 alu.src[0].sel = V_SQ_ALU_SRC_0;
4690
4691 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
4692 alu.src[1].sel = V_SQ_ALU_SRC_1;
4693 alu.src[1].neg = 1;
4694 } else {
4695 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4696 }
4697 if (i == 3) {
4698 alu.last = 1;
4699 }
4700 r = r600_bytecode_add_alu(ctx->bc, &alu);
4701 if (r)
4702 return r;
4703 }
4704
4705 /* kill must be last in ALU */
4706 ctx->bc->force_add_cf = 1;
4707 ctx->shader->uses_kill = TRUE;
4708 return 0;
4709 }
4710
4711 static int tgsi_lit(struct r600_shader_ctx *ctx)
4712 {
4713 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4714 struct r600_bytecode_alu alu;
4715 int r;
4716
4717 /* tmp.x = max(src.y, 0.0) */
4718 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4719 alu.op = ALU_OP2_MAX;
4720 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4721 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4722 alu.src[1].chan = 1;
4723
4724 alu.dst.sel = ctx->temp_reg;
4725 alu.dst.chan = 0;
4726 alu.dst.write = 1;
4727
4728 alu.last = 1;
4729 r = r600_bytecode_add_alu(ctx->bc, &alu);
4730 if (r)
4731 return r;
4732
4733 if (inst->Dst[0].Register.WriteMask & (1 << 2))
4734 {
4735 int chan;
4736 int sel;
4737 unsigned i;
4738
4739 if (ctx->bc->chip_class == CAYMAN) {
4740 for (i = 0; i < 3; i++) {
4741 /* tmp.z = log(tmp.x) */
4742 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4743 alu.op = ALU_OP1_LOG_CLAMPED;
4744 alu.src[0].sel = ctx->temp_reg;
4745 alu.src[0].chan = 0;
4746 alu.dst.sel = ctx->temp_reg;
4747 alu.dst.chan = i;
4748 if (i == 2) {
4749 alu.dst.write = 1;
4750 alu.last = 1;
4751 } else
4752 alu.dst.write = 0;
4753
4754 r = r600_bytecode_add_alu(ctx->bc, &alu);
4755 if (r)
4756 return r;
4757 }
4758 } else {
4759 /* tmp.z = log(tmp.x) */
4760 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4761 alu.op = ALU_OP1_LOG_CLAMPED;
4762 alu.src[0].sel = ctx->temp_reg;
4763 alu.src[0].chan = 0;
4764 alu.dst.sel = ctx->temp_reg;
4765 alu.dst.chan = 2;
4766 alu.dst.write = 1;
4767 alu.last = 1;
4768 r = r600_bytecode_add_alu(ctx->bc, &alu);
4769 if (r)
4770 return r;
4771 }
4772
4773 chan = alu.dst.chan;
4774 sel = alu.dst.sel;
4775
4776 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4777 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4778 alu.op = ALU_OP3_MUL_LIT;
4779 alu.src[0].sel = sel;
4780 alu.src[0].chan = chan;
4781 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
4782 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
4783 alu.dst.sel = ctx->temp_reg;
4784 alu.dst.chan = 0;
4785 alu.dst.write = 1;
4786 alu.is_op3 = 1;
4787 alu.last = 1;
4788 r = r600_bytecode_add_alu(ctx->bc, &alu);
4789 if (r)
4790 return r;
4791
4792 if (ctx->bc->chip_class == CAYMAN) {
4793 for (i = 0; i < 3; i++) {
4794 /* dst.z = exp(tmp.x) */
4795 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4796 alu.op = ALU_OP1_EXP_IEEE;
4797 alu.src[0].sel = ctx->temp_reg;
4798 alu.src[0].chan = 0;
4799 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4800 if (i == 2) {
4801 alu.dst.write = 1;
4802 alu.last = 1;
4803 } else
4804 alu.dst.write = 0;
4805 r = r600_bytecode_add_alu(ctx->bc, &alu);
4806 if (r)
4807 return r;
4808 }
4809 } else {
4810 /* dst.z = exp(tmp.x) */
4811 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4812 alu.op = ALU_OP1_EXP_IEEE;
4813 alu.src[0].sel = ctx->temp_reg;
4814 alu.src[0].chan = 0;
4815 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4816 alu.last = 1;
4817 r = r600_bytecode_add_alu(ctx->bc, &alu);
4818 if (r)
4819 return r;
4820 }
4821 }
4822
4823 /* dst.x, <- 1.0 */
4824 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4825 alu.op = ALU_OP1_MOV;
4826 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
4827 alu.src[0].chan = 0;
4828 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4829 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
4830 r = r600_bytecode_add_alu(ctx->bc, &alu);
4831 if (r)
4832 return r;
4833
4834 /* dst.y = max(src.x, 0.0) */
4835 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4836 alu.op = ALU_OP2_MAX;
4837 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4838 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4839 alu.src[1].chan = 0;
4840 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4841 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
4842 r = r600_bytecode_add_alu(ctx->bc, &alu);
4843 if (r)
4844 return r;
4845
4846 /* dst.w, <- 1.0 */
4847 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4848 alu.op = ALU_OP1_MOV;
4849 alu.src[0].sel = V_SQ_ALU_SRC_1;
4850 alu.src[0].chan = 0;
4851 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4852 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
4853 alu.last = 1;
4854 r = r600_bytecode_add_alu(ctx->bc, &alu);
4855 if (r)
4856 return r;
4857
4858 return 0;
4859 }
4860
4861 static int tgsi_rsq(struct r600_shader_ctx *ctx)
4862 {
4863 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4864 struct r600_bytecode_alu alu;
4865 int i, r;
4866
4867 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4868
4869 alu.op = ALU_OP1_RECIPSQRT_IEEE;
4870
4871 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4872 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4873 r600_bytecode_src_set_abs(&alu.src[i]);
4874 }
4875 alu.dst.sel = ctx->temp_reg;
4876 alu.dst.write = 1;
4877 alu.last = 1;
4878 r = r600_bytecode_add_alu(ctx->bc, &alu);
4879 if (r)
4880 return r;
4881 /* replicate result */
4882 return tgsi_helper_tempx_replicate(ctx);
4883 }
4884
4885 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
4886 {
4887 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4888 struct r600_bytecode_alu alu;
4889 int i, r;
4890
4891 for (i = 0; i < 4; i++) {
4892 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4893 alu.src[0].sel = ctx->temp_reg;
4894 alu.op = ALU_OP1_MOV;
4895 alu.dst.chan = i;
4896 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4897 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4898 if (i == 3)
4899 alu.last = 1;
4900 r = r600_bytecode_add_alu(ctx->bc, &alu);
4901 if (r)
4902 return r;
4903 }
4904 return 0;
4905 }
4906
4907 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
4908 {
4909 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4910 struct r600_bytecode_alu alu;
4911 int i, r;
4912
4913 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4914 alu.op = ctx->inst_info->op;
4915 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4916 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4917 }
4918 alu.dst.sel = ctx->temp_reg;
4919 alu.dst.write = 1;
4920 alu.last = 1;
4921 r = r600_bytecode_add_alu(ctx->bc, &alu);
4922 if (r)
4923 return r;
4924 /* replicate result */
4925 return tgsi_helper_tempx_replicate(ctx);
4926 }
4927
4928 static int cayman_pow(struct r600_shader_ctx *ctx)
4929 {
4930 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4931 int i, r;
4932 struct r600_bytecode_alu alu;
4933 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4934
4935 for (i = 0; i < 3; i++) {
4936 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4937 alu.op = ALU_OP1_LOG_IEEE;
4938 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4939 alu.dst.sel = ctx->temp_reg;
4940 alu.dst.chan = i;
4941 alu.dst.write = 1;
4942 if (i == 2)
4943 alu.last = 1;
4944 r = r600_bytecode_add_alu(ctx->bc, &alu);
4945 if (r)
4946 return r;
4947 }
4948
4949 /* b * LOG2(a) */
4950 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4951 alu.op = ALU_OP2_MUL;
4952 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4953 alu.src[1].sel = ctx->temp_reg;
4954 alu.dst.sel = ctx->temp_reg;
4955 alu.dst.write = 1;
4956 alu.last = 1;
4957 r = r600_bytecode_add_alu(ctx->bc, &alu);
4958 if (r)
4959 return r;
4960
4961 for (i = 0; i < last_slot; i++) {
4962 /* POW(a,b) = EXP2(b * LOG2(a))*/
4963 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4964 alu.op = ALU_OP1_EXP_IEEE;
4965 alu.src[0].sel = ctx->temp_reg;
4966
4967 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4968 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4969 if (i == last_slot - 1)
4970 alu.last = 1;
4971 r = r600_bytecode_add_alu(ctx->bc, &alu);
4972 if (r)
4973 return r;
4974 }
4975 return 0;
4976 }
4977
4978 static int tgsi_pow(struct r600_shader_ctx *ctx)
4979 {
4980 struct r600_bytecode_alu alu;
4981 int r;
4982
4983 /* LOG2(a) */
4984 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4985 alu.op = ALU_OP1_LOG_IEEE;
4986 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4987 alu.dst.sel = ctx->temp_reg;
4988 alu.dst.write = 1;
4989 alu.last = 1;
4990 r = r600_bytecode_add_alu(ctx->bc, &alu);
4991 if (r)
4992 return r;
4993 /* b * LOG2(a) */
4994 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4995 alu.op = ALU_OP2_MUL;
4996 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4997 alu.src[1].sel = ctx->temp_reg;
4998 alu.dst.sel = ctx->temp_reg;
4999 alu.dst.write = 1;
5000 alu.last = 1;
5001 r = r600_bytecode_add_alu(ctx->bc, &alu);
5002 if (r)
5003 return r;
5004 /* POW(a,b) = EXP2(b * LOG2(a))*/
5005 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5006 alu.op = ALU_OP1_EXP_IEEE;
5007 alu.src[0].sel = ctx->temp_reg;
5008 alu.dst.sel = ctx->temp_reg;
5009 alu.dst.write = 1;
5010 alu.last = 1;
5011 r = r600_bytecode_add_alu(ctx->bc, &alu);
5012 if (r)
5013 return r;
5014 return tgsi_helper_tempx_replicate(ctx);
5015 }
5016
5017 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5018 {
5019 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5020 struct r600_bytecode_alu alu;
5021 int i, r, j;
5022 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5023 int tmp0 = ctx->temp_reg;
5024 int tmp1 = r600_get_temp(ctx);
5025 int tmp2 = r600_get_temp(ctx);
5026 int tmp3 = r600_get_temp(ctx);
5027 /* Unsigned path:
5028 *
5029 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5030 *
5031 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5032 * 2. tmp0.z = lo (tmp0.x * src2)
5033 * 3. tmp0.w = -tmp0.z
5034 * 4. tmp0.y = hi (tmp0.x * src2)
5035 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5036 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5037 * 7. tmp1.x = tmp0.x - tmp0.w
5038 * 8. tmp1.y = tmp0.x + tmp0.w
5039 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5040 * 10. tmp0.z = hi(tmp0.x * src1) = q
5041 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5042 *
5043 * 12. tmp0.w = src1 - tmp0.y = r
5044 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5045 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5046 *
5047 * if DIV
5048 *
5049 * 15. tmp1.z = tmp0.z + 1 = q + 1
5050 * 16. tmp1.w = tmp0.z - 1 = q - 1
5051 *
5052 * else MOD
5053 *
5054 * 15. tmp1.z = tmp0.w - src2 = r - src2
5055 * 16. tmp1.w = tmp0.w + src2 = r + src2
5056 *
5057 * endif
5058 *
5059 * 17. tmp1.x = tmp1.x & tmp1.y
5060 *
5061 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5062 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5063 *
5064 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5065 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5066 *
5067 * Signed path:
5068 *
5069 * Same as unsigned, using abs values of the operands,
5070 * and fixing the sign of the result in the end.
5071 */
5072
5073 for (i = 0; i < 4; i++) {
5074 if (!(write_mask & (1<<i)))
5075 continue;
5076
5077 if (signed_op) {
5078
5079 /* tmp2.x = -src0 */
5080 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5081 alu.op = ALU_OP2_SUB_INT;
5082
5083 alu.dst.sel = tmp2;
5084 alu.dst.chan = 0;
5085 alu.dst.write = 1;
5086
5087 alu.src[0].sel = V_SQ_ALU_SRC_0;
5088
5089 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5090
5091 alu.last = 1;
5092 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5093 return r;
5094
5095 /* tmp2.y = -src1 */
5096 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5097 alu.op = ALU_OP2_SUB_INT;
5098
5099 alu.dst.sel = tmp2;
5100 alu.dst.chan = 1;
5101 alu.dst.write = 1;
5102
5103 alu.src[0].sel = V_SQ_ALU_SRC_0;
5104
5105 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5106
5107 alu.last = 1;
5108 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5109 return r;
5110
5111 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5112 /* it will be a sign of the quotient */
5113 if (!mod) {
5114
5115 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5116 alu.op = ALU_OP2_XOR_INT;
5117
5118 alu.dst.sel = tmp2;
5119 alu.dst.chan = 2;
5120 alu.dst.write = 1;
5121
5122 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5123 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5124
5125 alu.last = 1;
5126 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5127 return r;
5128 }
5129
5130 /* tmp2.x = |src0| */
5131 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5132 alu.op = ALU_OP3_CNDGE_INT;
5133 alu.is_op3 = 1;
5134
5135 alu.dst.sel = tmp2;
5136 alu.dst.chan = 0;
5137 alu.dst.write = 1;
5138
5139 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5140 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5141 alu.src[2].sel = tmp2;
5142 alu.src[2].chan = 0;
5143
5144 alu.last = 1;
5145 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5146 return r;
5147
5148 /* tmp2.y = |src1| */
5149 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5150 alu.op = ALU_OP3_CNDGE_INT;
5151 alu.is_op3 = 1;
5152
5153 alu.dst.sel = tmp2;
5154 alu.dst.chan = 1;
5155 alu.dst.write = 1;
5156
5157 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5158 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5159 alu.src[2].sel = tmp2;
5160 alu.src[2].chan = 1;
5161
5162 alu.last = 1;
5163 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5164 return r;
5165
5166 }
5167
5168 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5169 if (ctx->bc->chip_class == CAYMAN) {
5170 /* tmp3.x = u2f(src2) */
5171 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5172 alu.op = ALU_OP1_UINT_TO_FLT;
5173
5174 alu.dst.sel = tmp3;
5175 alu.dst.chan = 0;
5176 alu.dst.write = 1;
5177
5178 if (signed_op) {
5179 alu.src[0].sel = tmp2;
5180 alu.src[0].chan = 1;
5181 } else {
5182 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5183 }
5184
5185 alu.last = 1;
5186 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5187 return r;
5188
5189 /* tmp0.x = recip(tmp3.x) */
5190 for (j = 0 ; j < 3; j++) {
5191 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5192 alu.op = ALU_OP1_RECIP_IEEE;
5193
5194 alu.dst.sel = tmp0;
5195 alu.dst.chan = j;
5196 alu.dst.write = (j == 0);
5197
5198 alu.src[0].sel = tmp3;
5199 alu.src[0].chan = 0;
5200
5201 if (j == 2)
5202 alu.last = 1;
5203 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5204 return r;
5205 }
5206
5207 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5208 alu.op = ALU_OP2_MUL;
5209
5210 alu.src[0].sel = tmp0;
5211 alu.src[0].chan = 0;
5212
5213 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5214 alu.src[1].value = 0x4f800000;
5215
5216 alu.dst.sel = tmp3;
5217 alu.dst.write = 1;
5218 alu.last = 1;
5219 r = r600_bytecode_add_alu(ctx->bc, &alu);
5220 if (r)
5221 return r;
5222
5223 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5224 alu.op = ALU_OP1_FLT_TO_UINT;
5225
5226 alu.dst.sel = tmp0;
5227 alu.dst.chan = 0;
5228 alu.dst.write = 1;
5229
5230 alu.src[0].sel = tmp3;
5231 alu.src[0].chan = 0;
5232
5233 alu.last = 1;
5234 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5235 return r;
5236
5237 } else {
5238 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5239 alu.op = ALU_OP1_RECIP_UINT;
5240
5241 alu.dst.sel = tmp0;
5242 alu.dst.chan = 0;
5243 alu.dst.write = 1;
5244
5245 if (signed_op) {
5246 alu.src[0].sel = tmp2;
5247 alu.src[0].chan = 1;
5248 } else {
5249 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5250 }
5251
5252 alu.last = 1;
5253 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5254 return r;
5255 }
5256
5257 /* 2. tmp0.z = lo (tmp0.x * src2) */
5258 if (ctx->bc->chip_class == CAYMAN) {
5259 for (j = 0 ; j < 4; j++) {
5260 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5261 alu.op = ALU_OP2_MULLO_UINT;
5262
5263 alu.dst.sel = tmp0;
5264 alu.dst.chan = j;
5265 alu.dst.write = (j == 2);
5266
5267 alu.src[0].sel = tmp0;
5268 alu.src[0].chan = 0;
5269 if (signed_op) {
5270 alu.src[1].sel = tmp2;
5271 alu.src[1].chan = 1;
5272 } else {
5273 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5274 }
5275
5276 alu.last = (j == 3);
5277 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5278 return r;
5279 }
5280 } else {
5281 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5282 alu.op = ALU_OP2_MULLO_UINT;
5283
5284 alu.dst.sel = tmp0;
5285 alu.dst.chan = 2;
5286 alu.dst.write = 1;
5287
5288 alu.src[0].sel = tmp0;
5289 alu.src[0].chan = 0;
5290 if (signed_op) {
5291 alu.src[1].sel = tmp2;
5292 alu.src[1].chan = 1;
5293 } else {
5294 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5295 }
5296
5297 alu.last = 1;
5298 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5299 return r;
5300 }
5301
5302 /* 3. tmp0.w = -tmp0.z */
5303 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5304 alu.op = ALU_OP2_SUB_INT;
5305
5306 alu.dst.sel = tmp0;
5307 alu.dst.chan = 3;
5308 alu.dst.write = 1;
5309
5310 alu.src[0].sel = V_SQ_ALU_SRC_0;
5311 alu.src[1].sel = tmp0;
5312 alu.src[1].chan = 2;
5313
5314 alu.last = 1;
5315 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5316 return r;
5317
5318 /* 4. tmp0.y = hi (tmp0.x * src2) */
5319 if (ctx->bc->chip_class == CAYMAN) {
5320 for (j = 0 ; j < 4; j++) {
5321 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5322 alu.op = ALU_OP2_MULHI_UINT;
5323
5324 alu.dst.sel = tmp0;
5325 alu.dst.chan = j;
5326 alu.dst.write = (j == 1);
5327
5328 alu.src[0].sel = tmp0;
5329 alu.src[0].chan = 0;
5330
5331 if (signed_op) {
5332 alu.src[1].sel = tmp2;
5333 alu.src[1].chan = 1;
5334 } else {
5335 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5336 }
5337 alu.last = (j == 3);
5338 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5339 return r;
5340 }
5341 } else {
5342 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5343 alu.op = ALU_OP2_MULHI_UINT;
5344
5345 alu.dst.sel = tmp0;
5346 alu.dst.chan = 1;
5347 alu.dst.write = 1;
5348
5349 alu.src[0].sel = tmp0;
5350 alu.src[0].chan = 0;
5351
5352 if (signed_op) {
5353 alu.src[1].sel = tmp2;
5354 alu.src[1].chan = 1;
5355 } else {
5356 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5357 }
5358
5359 alu.last = 1;
5360 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5361 return r;
5362 }
5363
5364 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5365 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5366 alu.op = ALU_OP3_CNDE_INT;
5367 alu.is_op3 = 1;
5368
5369 alu.dst.sel = tmp0;
5370 alu.dst.chan = 2;
5371 alu.dst.write = 1;
5372
5373 alu.src[0].sel = tmp0;
5374 alu.src[0].chan = 1;
5375 alu.src[1].sel = tmp0;
5376 alu.src[1].chan = 3;
5377 alu.src[2].sel = tmp0;
5378 alu.src[2].chan = 2;
5379
5380 alu.last = 1;
5381 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5382 return r;
5383
5384 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5385 if (ctx->bc->chip_class == CAYMAN) {
5386 for (j = 0 ; j < 4; j++) {
5387 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5388 alu.op = ALU_OP2_MULHI_UINT;
5389
5390 alu.dst.sel = tmp0;
5391 alu.dst.chan = j;
5392 alu.dst.write = (j == 3);
5393
5394 alu.src[0].sel = tmp0;
5395 alu.src[0].chan = 2;
5396
5397 alu.src[1].sel = tmp0;
5398 alu.src[1].chan = 0;
5399
5400 alu.last = (j == 3);
5401 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5402 return r;
5403 }
5404 } else {
5405 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5406 alu.op = ALU_OP2_MULHI_UINT;
5407
5408 alu.dst.sel = tmp0;
5409 alu.dst.chan = 3;
5410 alu.dst.write = 1;
5411
5412 alu.src[0].sel = tmp0;
5413 alu.src[0].chan = 2;
5414
5415 alu.src[1].sel = tmp0;
5416 alu.src[1].chan = 0;
5417
5418 alu.last = 1;
5419 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5420 return r;
5421 }
5422
5423 /* 7. tmp1.x = tmp0.x - tmp0.w */
5424 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5425 alu.op = ALU_OP2_SUB_INT;
5426
5427 alu.dst.sel = tmp1;
5428 alu.dst.chan = 0;
5429 alu.dst.write = 1;
5430
5431 alu.src[0].sel = tmp0;
5432 alu.src[0].chan = 0;
5433 alu.src[1].sel = tmp0;
5434 alu.src[1].chan = 3;
5435
5436 alu.last = 1;
5437 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5438 return r;
5439
5440 /* 8. tmp1.y = tmp0.x + tmp0.w */
5441 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5442 alu.op = ALU_OP2_ADD_INT;
5443
5444 alu.dst.sel = tmp1;
5445 alu.dst.chan = 1;
5446 alu.dst.write = 1;
5447
5448 alu.src[0].sel = tmp0;
5449 alu.src[0].chan = 0;
5450 alu.src[1].sel = tmp0;
5451 alu.src[1].chan = 3;
5452
5453 alu.last = 1;
5454 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5455 return r;
5456
5457 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5458 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5459 alu.op = ALU_OP3_CNDE_INT;
5460 alu.is_op3 = 1;
5461
5462 alu.dst.sel = tmp0;
5463 alu.dst.chan = 0;
5464 alu.dst.write = 1;
5465
5466 alu.src[0].sel = tmp0;
5467 alu.src[0].chan = 1;
5468 alu.src[1].sel = tmp1;
5469 alu.src[1].chan = 1;
5470 alu.src[2].sel = tmp1;
5471 alu.src[2].chan = 0;
5472
5473 alu.last = 1;
5474 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5475 return r;
5476
5477 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5478 if (ctx->bc->chip_class == CAYMAN) {
5479 for (j = 0 ; j < 4; j++) {
5480 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5481 alu.op = ALU_OP2_MULHI_UINT;
5482
5483 alu.dst.sel = tmp0;
5484 alu.dst.chan = j;
5485 alu.dst.write = (j == 2);
5486
5487 alu.src[0].sel = tmp0;
5488 alu.src[0].chan = 0;
5489
5490 if (signed_op) {
5491 alu.src[1].sel = tmp2;
5492 alu.src[1].chan = 0;
5493 } else {
5494 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5495 }
5496
5497 alu.last = (j == 3);
5498 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5499 return r;
5500 }
5501 } else {
5502 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5503 alu.op = ALU_OP2_MULHI_UINT;
5504
5505 alu.dst.sel = tmp0;
5506 alu.dst.chan = 2;
5507 alu.dst.write = 1;
5508
5509 alu.src[0].sel = tmp0;
5510 alu.src[0].chan = 0;
5511
5512 if (signed_op) {
5513 alu.src[1].sel = tmp2;
5514 alu.src[1].chan = 0;
5515 } else {
5516 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5517 }
5518
5519 alu.last = 1;
5520 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5521 return r;
5522 }
5523
5524 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5525 if (ctx->bc->chip_class == CAYMAN) {
5526 for (j = 0 ; j < 4; j++) {
5527 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5528 alu.op = ALU_OP2_MULLO_UINT;
5529
5530 alu.dst.sel = tmp0;
5531 alu.dst.chan = j;
5532 alu.dst.write = (j == 1);
5533
5534 if (signed_op) {
5535 alu.src[0].sel = tmp2;
5536 alu.src[0].chan = 1;
5537 } else {
5538 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5539 }
5540
5541 alu.src[1].sel = tmp0;
5542 alu.src[1].chan = 2;
5543
5544 alu.last = (j == 3);
5545 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5546 return r;
5547 }
5548 } else {
5549 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5550 alu.op = ALU_OP2_MULLO_UINT;
5551
5552 alu.dst.sel = tmp0;
5553 alu.dst.chan = 1;
5554 alu.dst.write = 1;
5555
5556 if (signed_op) {
5557 alu.src[0].sel = tmp2;
5558 alu.src[0].chan = 1;
5559 } else {
5560 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5561 }
5562
5563 alu.src[1].sel = tmp0;
5564 alu.src[1].chan = 2;
5565
5566 alu.last = 1;
5567 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5568 return r;
5569 }
5570
5571 /* 12. tmp0.w = src1 - tmp0.y = r */
5572 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5573 alu.op = ALU_OP2_SUB_INT;
5574
5575 alu.dst.sel = tmp0;
5576 alu.dst.chan = 3;
5577 alu.dst.write = 1;
5578
5579 if (signed_op) {
5580 alu.src[0].sel = tmp2;
5581 alu.src[0].chan = 0;
5582 } else {
5583 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5584 }
5585
5586 alu.src[1].sel = tmp0;
5587 alu.src[1].chan = 1;
5588
5589 alu.last = 1;
5590 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5591 return r;
5592
5593 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5594 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5595 alu.op = ALU_OP2_SETGE_UINT;
5596
5597 alu.dst.sel = tmp1;
5598 alu.dst.chan = 0;
5599 alu.dst.write = 1;
5600
5601 alu.src[0].sel = tmp0;
5602 alu.src[0].chan = 3;
5603 if (signed_op) {
5604 alu.src[1].sel = tmp2;
5605 alu.src[1].chan = 1;
5606 } else {
5607 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5608 }
5609
5610 alu.last = 1;
5611 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5612 return r;
5613
5614 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5615 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5616 alu.op = ALU_OP2_SETGE_UINT;
5617
5618 alu.dst.sel = tmp1;
5619 alu.dst.chan = 1;
5620 alu.dst.write = 1;
5621
5622 if (signed_op) {
5623 alu.src[0].sel = tmp2;
5624 alu.src[0].chan = 0;
5625 } else {
5626 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5627 }
5628
5629 alu.src[1].sel = tmp0;
5630 alu.src[1].chan = 1;
5631
5632 alu.last = 1;
5633 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5634 return r;
5635
5636 if (mod) { /* UMOD */
5637
5638 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5639 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5640 alu.op = ALU_OP2_SUB_INT;
5641
5642 alu.dst.sel = tmp1;
5643 alu.dst.chan = 2;
5644 alu.dst.write = 1;
5645
5646 alu.src[0].sel = tmp0;
5647 alu.src[0].chan = 3;
5648
5649 if (signed_op) {
5650 alu.src[1].sel = tmp2;
5651 alu.src[1].chan = 1;
5652 } else {
5653 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5654 }
5655
5656 alu.last = 1;
5657 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5658 return r;
5659
5660 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5661 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5662 alu.op = ALU_OP2_ADD_INT;
5663
5664 alu.dst.sel = tmp1;
5665 alu.dst.chan = 3;
5666 alu.dst.write = 1;
5667
5668 alu.src[0].sel = tmp0;
5669 alu.src[0].chan = 3;
5670 if (signed_op) {
5671 alu.src[1].sel = tmp2;
5672 alu.src[1].chan = 1;
5673 } else {
5674 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5675 }
5676
5677 alu.last = 1;
5678 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5679 return r;
5680
5681 } else { /* UDIV */
5682
5683 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5684 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5685 alu.op = ALU_OP2_ADD_INT;
5686
5687 alu.dst.sel = tmp1;
5688 alu.dst.chan = 2;
5689 alu.dst.write = 1;
5690
5691 alu.src[0].sel = tmp0;
5692 alu.src[0].chan = 2;
5693 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5694
5695 alu.last = 1;
5696 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5697 return r;
5698
5699 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5700 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5701 alu.op = ALU_OP2_ADD_INT;
5702
5703 alu.dst.sel = tmp1;
5704 alu.dst.chan = 3;
5705 alu.dst.write = 1;
5706
5707 alu.src[0].sel = tmp0;
5708 alu.src[0].chan = 2;
5709 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
5710
5711 alu.last = 1;
5712 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5713 return r;
5714
5715 }
5716
5717 /* 17. tmp1.x = tmp1.x & tmp1.y */
5718 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5719 alu.op = ALU_OP2_AND_INT;
5720
5721 alu.dst.sel = tmp1;
5722 alu.dst.chan = 0;
5723 alu.dst.write = 1;
5724
5725 alu.src[0].sel = tmp1;
5726 alu.src[0].chan = 0;
5727 alu.src[1].sel = tmp1;
5728 alu.src[1].chan = 1;
5729
5730 alu.last = 1;
5731 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5732 return r;
5733
5734 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5735 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5736 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5737 alu.op = ALU_OP3_CNDE_INT;
5738 alu.is_op3 = 1;
5739
5740 alu.dst.sel = tmp0;
5741 alu.dst.chan = 2;
5742 alu.dst.write = 1;
5743
5744 alu.src[0].sel = tmp1;
5745 alu.src[0].chan = 0;
5746 alu.src[1].sel = tmp0;
5747 alu.src[1].chan = mod ? 3 : 2;
5748 alu.src[2].sel = tmp1;
5749 alu.src[2].chan = 2;
5750
5751 alu.last = 1;
5752 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5753 return r;
5754
5755 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5756 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5757 alu.op = ALU_OP3_CNDE_INT;
5758 alu.is_op3 = 1;
5759
5760 if (signed_op) {
5761 alu.dst.sel = tmp0;
5762 alu.dst.chan = 2;
5763 alu.dst.write = 1;
5764 } else {
5765 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5766 }
5767
5768 alu.src[0].sel = tmp1;
5769 alu.src[0].chan = 1;
5770 alu.src[1].sel = tmp1;
5771 alu.src[1].chan = 3;
5772 alu.src[2].sel = tmp0;
5773 alu.src[2].chan = 2;
5774
5775 alu.last = 1;
5776 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5777 return r;
5778
5779 if (signed_op) {
5780
5781 /* fix the sign of the result */
5782
5783 if (mod) {
5784
5785 /* tmp0.x = -tmp0.z */
5786 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5787 alu.op = ALU_OP2_SUB_INT;
5788
5789 alu.dst.sel = tmp0;
5790 alu.dst.chan = 0;
5791 alu.dst.write = 1;
5792
5793 alu.src[0].sel = V_SQ_ALU_SRC_0;
5794 alu.src[1].sel = tmp0;
5795 alu.src[1].chan = 2;
5796
5797 alu.last = 1;
5798 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5799 return r;
5800
5801 /* sign of the remainder is the same as the sign of src0 */
5802 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5803 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5804 alu.op = ALU_OP3_CNDGE_INT;
5805 alu.is_op3 = 1;
5806
5807 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5808
5809 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5810 alu.src[1].sel = tmp0;
5811 alu.src[1].chan = 2;
5812 alu.src[2].sel = tmp0;
5813 alu.src[2].chan = 0;
5814
5815 alu.last = 1;
5816 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5817 return r;
5818
5819 } else {
5820
5821 /* tmp0.x = -tmp0.z */
5822 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5823 alu.op = ALU_OP2_SUB_INT;
5824
5825 alu.dst.sel = tmp0;
5826 alu.dst.chan = 0;
5827 alu.dst.write = 1;
5828
5829 alu.src[0].sel = V_SQ_ALU_SRC_0;
5830 alu.src[1].sel = tmp0;
5831 alu.src[1].chan = 2;
5832
5833 alu.last = 1;
5834 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5835 return r;
5836
5837 /* fix the quotient sign (same as the sign of src0*src1) */
5838 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5839 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5840 alu.op = ALU_OP3_CNDGE_INT;
5841 alu.is_op3 = 1;
5842
5843 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5844
5845 alu.src[0].sel = tmp2;
5846 alu.src[0].chan = 2;
5847 alu.src[1].sel = tmp0;
5848 alu.src[1].chan = 2;
5849 alu.src[2].sel = tmp0;
5850 alu.src[2].chan = 0;
5851
5852 alu.last = 1;
5853 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5854 return r;
5855 }
5856 }
5857 }
5858 return 0;
5859 }
5860
5861 static int tgsi_udiv(struct r600_shader_ctx *ctx)
5862 {
5863 return tgsi_divmod(ctx, 0, 0);
5864 }
5865
5866 static int tgsi_umod(struct r600_shader_ctx *ctx)
5867 {
5868 return tgsi_divmod(ctx, 1, 0);
5869 }
5870
5871 static int tgsi_idiv(struct r600_shader_ctx *ctx)
5872 {
5873 return tgsi_divmod(ctx, 0, 1);
5874 }
5875
5876 static int tgsi_imod(struct r600_shader_ctx *ctx)
5877 {
5878 return tgsi_divmod(ctx, 1, 1);
5879 }
5880
5881
5882 static int tgsi_f2i(struct r600_shader_ctx *ctx)
5883 {
5884 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5885 struct r600_bytecode_alu alu;
5886 int i, r;
5887 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5888 int last_inst = tgsi_last_instruction(write_mask);
5889
5890 for (i = 0; i < 4; i++) {
5891 if (!(write_mask & (1<<i)))
5892 continue;
5893
5894 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5895 alu.op = ALU_OP1_TRUNC;
5896
5897 alu.dst.sel = ctx->temp_reg;
5898 alu.dst.chan = i;
5899 alu.dst.write = 1;
5900
5901 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5902 if (i == last_inst)
5903 alu.last = 1;
5904 r = r600_bytecode_add_alu(ctx->bc, &alu);
5905 if (r)
5906 return r;
5907 }
5908
5909 for (i = 0; i < 4; i++) {
5910 if (!(write_mask & (1<<i)))
5911 continue;
5912
5913 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5914 alu.op = ctx->inst_info->op;
5915
5916 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5917
5918 alu.src[0].sel = ctx->temp_reg;
5919 alu.src[0].chan = i;
5920
5921 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
5922 alu.last = 1;
5923 r = r600_bytecode_add_alu(ctx->bc, &alu);
5924 if (r)
5925 return r;
5926 }
5927
5928 return 0;
5929 }
5930
5931 static int tgsi_iabs(struct r600_shader_ctx *ctx)
5932 {
5933 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5934 struct r600_bytecode_alu alu;
5935 int i, r;
5936 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5937 int last_inst = tgsi_last_instruction(write_mask);
5938
5939 /* tmp = -src */
5940 for (i = 0; i < 4; i++) {
5941 if (!(write_mask & (1<<i)))
5942 continue;
5943
5944 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5945 alu.op = ALU_OP2_SUB_INT;
5946
5947 alu.dst.sel = ctx->temp_reg;
5948 alu.dst.chan = i;
5949 alu.dst.write = 1;
5950
5951 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5952 alu.src[0].sel = V_SQ_ALU_SRC_0;
5953
5954 if (i == last_inst)
5955 alu.last = 1;
5956 r = r600_bytecode_add_alu(ctx->bc, &alu);
5957 if (r)
5958 return r;
5959 }
5960
5961 /* dst = (src >= 0 ? src : tmp) */
5962 for (i = 0; i < 4; i++) {
5963 if (!(write_mask & (1<<i)))
5964 continue;
5965
5966 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5967 alu.op = ALU_OP3_CNDGE_INT;
5968 alu.is_op3 = 1;
5969 alu.dst.write = 1;
5970
5971 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5972
5973 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5974 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5975 alu.src[2].sel = ctx->temp_reg;
5976 alu.src[2].chan = i;
5977
5978 if (i == last_inst)
5979 alu.last = 1;
5980 r = r600_bytecode_add_alu(ctx->bc, &alu);
5981 if (r)
5982 return r;
5983 }
5984 return 0;
5985 }
5986
5987 static int tgsi_issg(struct r600_shader_ctx *ctx)
5988 {
5989 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5990 struct r600_bytecode_alu alu;
5991 int i, r;
5992 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5993 int last_inst = tgsi_last_instruction(write_mask);
5994
5995 /* tmp = (src >= 0 ? src : -1) */
5996 for (i = 0; i < 4; i++) {
5997 if (!(write_mask & (1<<i)))
5998 continue;
5999
6000 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6001 alu.op = ALU_OP3_CNDGE_INT;
6002 alu.is_op3 = 1;
6003
6004 alu.dst.sel = ctx->temp_reg;
6005 alu.dst.chan = i;
6006 alu.dst.write = 1;
6007
6008 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6009 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6010 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6011
6012 if (i == last_inst)
6013 alu.last = 1;
6014 r = r600_bytecode_add_alu(ctx->bc, &alu);
6015 if (r)
6016 return r;
6017 }
6018
6019 /* dst = (tmp > 0 ? 1 : tmp) */
6020 for (i = 0; i < 4; i++) {
6021 if (!(write_mask & (1<<i)))
6022 continue;
6023
6024 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6025 alu.op = ALU_OP3_CNDGT_INT;
6026 alu.is_op3 = 1;
6027 alu.dst.write = 1;
6028
6029 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6030
6031 alu.src[0].sel = ctx->temp_reg;
6032 alu.src[0].chan = i;
6033
6034 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6035
6036 alu.src[2].sel = ctx->temp_reg;
6037 alu.src[2].chan = i;
6038
6039 if (i == last_inst)
6040 alu.last = 1;
6041 r = r600_bytecode_add_alu(ctx->bc, &alu);
6042 if (r)
6043 return r;
6044 }
6045 return 0;
6046 }
6047
6048
6049
6050 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6051 {
6052 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6053 struct r600_bytecode_alu alu;
6054 int i, r;
6055
6056 /* tmp = (src > 0 ? 1 : src) */
6057 for (i = 0; i < 4; i++) {
6058 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6059 alu.op = ALU_OP3_CNDGT;
6060 alu.is_op3 = 1;
6061
6062 alu.dst.sel = ctx->temp_reg;
6063 alu.dst.chan = i;
6064
6065 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6066 alu.src[1].sel = V_SQ_ALU_SRC_1;
6067 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6068
6069 if (i == 3)
6070 alu.last = 1;
6071 r = r600_bytecode_add_alu(ctx->bc, &alu);
6072 if (r)
6073 return r;
6074 }
6075
6076 /* dst = (-tmp > 0 ? -1 : tmp) */
6077 for (i = 0; i < 4; i++) {
6078 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6079 alu.op = ALU_OP3_CNDGT;
6080 alu.is_op3 = 1;
6081 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6082
6083 alu.src[0].sel = ctx->temp_reg;
6084 alu.src[0].chan = i;
6085 alu.src[0].neg = 1;
6086
6087 alu.src[1].sel = V_SQ_ALU_SRC_1;
6088 alu.src[1].neg = 1;
6089
6090 alu.src[2].sel = ctx->temp_reg;
6091 alu.src[2].chan = i;
6092
6093 if (i == 3)
6094 alu.last = 1;
6095 r = r600_bytecode_add_alu(ctx->bc, &alu);
6096 if (r)
6097 return r;
6098 }
6099 return 0;
6100 }
6101
6102 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6103 {
6104 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6105 struct r600_bytecode_alu alu;
6106 int i, r, t1, t2;
6107
6108 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6109 int last_inst = tgsi_last_instruction(write_mask);
6110
6111 t1 = r600_get_temp(ctx);
6112
6113 for (i = 0; i < 4; i++) {
6114 if (!(write_mask & (1<<i)))
6115 continue;
6116
6117 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6118 alu.op = ALU_OP2_SETGE_INT;
6119 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6120 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6121 alu.src[1].value = 32;
6122 alu.dst.sel = ctx->temp_reg;
6123 alu.dst.chan = i;
6124 alu.dst.write = 1;
6125 alu.last = i == last_inst;
6126 r = r600_bytecode_add_alu(ctx->bc, &alu);
6127 if (r)
6128 return r;
6129 }
6130
6131 for (i = 0; i < 4; i++) {
6132 if (!(write_mask & (1<<i)))
6133 continue;
6134
6135 /* create mask tmp */
6136 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6137 alu.op = ALU_OP2_BFM_INT;
6138 alu.dst.sel = t1;
6139 alu.dst.chan = i;
6140 alu.dst.write = 1;
6141 alu.last = i == last_inst;
6142
6143 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6144 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6145
6146 r = r600_bytecode_add_alu(ctx->bc, &alu);
6147 if (r)
6148 return r;
6149 }
6150
6151 t2 = r600_get_temp(ctx);
6152
6153 for (i = 0; i < 4; i++) {
6154 if (!(write_mask & (1<<i)))
6155 continue;
6156
6157 /* shift insert left */
6158 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6159 alu.op = ALU_OP2_LSHL_INT;
6160 alu.dst.sel = t2;
6161 alu.dst.chan = i;
6162 alu.dst.write = 1;
6163 alu.last = i == last_inst;
6164
6165 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6166 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6167
6168 r = r600_bytecode_add_alu(ctx->bc, &alu);
6169 if (r)
6170 return r;
6171 }
6172
6173 for (i = 0; i < 4; i++) {
6174 if (!(write_mask & (1<<i)))
6175 continue;
6176
6177 /* actual bitfield insert */
6178 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6179 alu.op = ALU_OP3_BFI_INT;
6180 alu.is_op3 = 1;
6181 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6182 alu.dst.chan = i;
6183 alu.dst.write = 1;
6184 alu.last = i == last_inst;
6185
6186 alu.src[0].sel = t1;
6187 alu.src[0].chan = i;
6188 alu.src[1].sel = t2;
6189 alu.src[1].chan = i;
6190 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6191
6192 r = r600_bytecode_add_alu(ctx->bc, &alu);
6193 if (r)
6194 return r;
6195 }
6196
6197 for (i = 0; i < 4; i++) {
6198 if (!(write_mask & (1<<i)))
6199 continue;
6200 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6201 alu.op = ALU_OP3_CNDE_INT;
6202 alu.is_op3 = 1;
6203 alu.src[0].sel = ctx->temp_reg;
6204 alu.src[0].chan = i;
6205 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6206
6207 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6208
6209 alu.src[1].sel = alu.dst.sel;
6210 alu.src[1].chan = i;
6211
6212 alu.last = i == last_inst;
6213 r = r600_bytecode_add_alu(ctx->bc, &alu);
6214 if (r)
6215 return r;
6216 }
6217 return 0;
6218 }
6219
6220 static int tgsi_msb(struct r600_shader_ctx *ctx)
6221 {
6222 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6223 struct r600_bytecode_alu alu;
6224 int i, r, t1, t2;
6225
6226 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6227 int last_inst = tgsi_last_instruction(write_mask);
6228
6229 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6230 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6231
6232 t1 = ctx->temp_reg;
6233
6234 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6235 for (i = 0; i < 4; i++) {
6236 if (!(write_mask & (1<<i)))
6237 continue;
6238
6239 /* t1 = FFBH_INT / FFBH_UINT */
6240 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6241 alu.op = ctx->inst_info->op;
6242 alu.dst.sel = t1;
6243 alu.dst.chan = i;
6244 alu.dst.write = 1;
6245 alu.last = i == last_inst;
6246
6247 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6248
6249 r = r600_bytecode_add_alu(ctx->bc, &alu);
6250 if (r)
6251 return r;
6252 }
6253
6254 t2 = r600_get_temp(ctx);
6255
6256 for (i = 0; i < 4; i++) {
6257 if (!(write_mask & (1<<i)))
6258 continue;
6259
6260 /* t2 = 31 - t1 */
6261 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6262 alu.op = ALU_OP2_SUB_INT;
6263 alu.dst.sel = t2;
6264 alu.dst.chan = i;
6265 alu.dst.write = 1;
6266 alu.last = i == last_inst;
6267
6268 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6269 alu.src[0].value = 31;
6270 alu.src[1].sel = t1;
6271 alu.src[1].chan = i;
6272
6273 r = r600_bytecode_add_alu(ctx->bc, &alu);
6274 if (r)
6275 return r;
6276 }
6277
6278 for (i = 0; i < 4; i++) {
6279 if (!(write_mask & (1<<i)))
6280 continue;
6281
6282 /* result = t1 >= 0 ? t2 : t1 */
6283 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6284 alu.op = ALU_OP3_CNDGE_INT;
6285 alu.is_op3 = 1;
6286 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6287 alu.dst.chan = i;
6288 alu.dst.write = 1;
6289 alu.last = i == last_inst;
6290
6291 alu.src[0].sel = t1;
6292 alu.src[0].chan = i;
6293 alu.src[1].sel = t2;
6294 alu.src[1].chan = i;
6295 alu.src[2].sel = t1;
6296 alu.src[2].chan = i;
6297
6298 r = r600_bytecode_add_alu(ctx->bc, &alu);
6299 if (r)
6300 return r;
6301 }
6302
6303 return 0;
6304 }
6305
6306 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6307 {
6308 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6309 struct r600_bytecode_alu alu;
6310 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6311 unsigned location;
6312 const int input = inst->Src[0].Register.Index + ctx->shader->nsys_inputs;
6313
6314 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6315
6316 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6317 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6318 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6319 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6320 }
6321 else {
6322 location = TGSI_INTERPOLATE_LOC_CENTROID;
6323 }
6324
6325 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6326 if (k < 0)
6327 k = 0;
6328 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6329 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6330
6331 /* NOTE: currently offset is not perspective correct */
6332 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6333 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6334 int sample_gpr = -1;
6335 int gradientsH, gradientsV;
6336 struct r600_bytecode_tex tex;
6337
6338 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6339 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6340 }
6341
6342 gradientsH = r600_get_temp(ctx);
6343 gradientsV = r600_get_temp(ctx);
6344 for (i = 0; i < 2; i++) {
6345 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6346 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6347 tex.src_gpr = interp_gpr;
6348 tex.src_sel_x = interp_base_chan + 0;
6349 tex.src_sel_y = interp_base_chan + 1;
6350 tex.src_sel_z = 0;
6351 tex.src_sel_w = 0;
6352 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6353 tex.dst_sel_x = 0;
6354 tex.dst_sel_y = 1;
6355 tex.dst_sel_z = 7;
6356 tex.dst_sel_w = 7;
6357 tex.inst_mod = 1; // Use per pixel gradient calculation
6358 tex.sampler_id = 0;
6359 tex.resource_id = tex.sampler_id;
6360 r = r600_bytecode_add_tex(ctx->bc, &tex);
6361 if (r)
6362 return r;
6363 }
6364
6365 for (i = 0; i < 2; i++) {
6366 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6367 alu.op = ALU_OP3_MULADD;
6368 alu.is_op3 = 1;
6369 alu.src[0].sel = gradientsH;
6370 alu.src[0].chan = i;
6371 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6372 alu.src[1].sel = sample_gpr;
6373 alu.src[1].chan = 2;
6374 }
6375 else {
6376 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6377 }
6378 alu.src[2].sel = interp_gpr;
6379 alu.src[2].chan = interp_base_chan + i;
6380 alu.dst.sel = ctx->temp_reg;
6381 alu.dst.chan = i;
6382 alu.last = i == 1;
6383
6384 r = r600_bytecode_add_alu(ctx->bc, &alu);
6385 if (r)
6386 return r;
6387 }
6388
6389 for (i = 0; i < 2; i++) {
6390 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6391 alu.op = ALU_OP3_MULADD;
6392 alu.is_op3 = 1;
6393 alu.src[0].sel = gradientsV;
6394 alu.src[0].chan = i;
6395 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6396 alu.src[1].sel = sample_gpr;
6397 alu.src[1].chan = 3;
6398 }
6399 else {
6400 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6401 }
6402 alu.src[2].sel = ctx->temp_reg;
6403 alu.src[2].chan = i;
6404 alu.dst.sel = ctx->temp_reg;
6405 alu.dst.chan = i;
6406 alu.last = i == 1;
6407
6408 r = r600_bytecode_add_alu(ctx->bc, &alu);
6409 if (r)
6410 return r;
6411 }
6412 }
6413
6414 tmp = r600_get_temp(ctx);
6415 for (i = 0; i < 8; i++) {
6416 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6417 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6418
6419 alu.dst.sel = tmp;
6420 if ((i > 1 && i < 6)) {
6421 alu.dst.write = 1;
6422 }
6423 else {
6424 alu.dst.write = 0;
6425 }
6426 alu.dst.chan = i % 4;
6427
6428 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6429 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6430 alu.src[0].sel = ctx->temp_reg;
6431 alu.src[0].chan = 1 - (i % 2);
6432 } else {
6433 alu.src[0].sel = interp_gpr;
6434 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
6435 }
6436 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
6437 alu.src[1].chan = 0;
6438
6439 alu.last = i % 4 == 3;
6440 alu.bank_swizzle_force = SQ_ALU_VEC_210;
6441
6442 r = r600_bytecode_add_alu(ctx->bc, &alu);
6443 if (r)
6444 return r;
6445 }
6446
6447 // INTERP can't swizzle dst
6448 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6449 for (i = 0; i <= lasti; i++) {
6450 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6451 continue;
6452
6453 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6454 alu.op = ALU_OP1_MOV;
6455 alu.src[0].sel = tmp;
6456 alu.src[0].chan = ctx->src[0].swizzle[i];
6457 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6458 alu.dst.write = 1;
6459 alu.last = i == lasti;
6460 r = r600_bytecode_add_alu(ctx->bc, &alu);
6461 if (r)
6462 return r;
6463 }
6464
6465 return 0;
6466 }
6467
6468
6469 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
6470 {
6471 struct r600_bytecode_alu alu;
6472 int i, r;
6473
6474 for (i = 0; i < 4; i++) {
6475 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6476 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
6477 alu.op = ALU_OP0_NOP;
6478 alu.dst.chan = i;
6479 } else {
6480 alu.op = ALU_OP1_MOV;
6481 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6482 alu.src[0].sel = ctx->temp_reg;
6483 alu.src[0].chan = i;
6484 }
6485 if (i == 3) {
6486 alu.last = 1;
6487 }
6488 r = r600_bytecode_add_alu(ctx->bc, &alu);
6489 if (r)
6490 return r;
6491 }
6492 return 0;
6493 }
6494
6495 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
6496 unsigned temp, int chan,
6497 struct r600_bytecode_alu_src *bc_src,
6498 const struct r600_shader_src *shader_src)
6499 {
6500 struct r600_bytecode_alu alu;
6501 int r;
6502
6503 r600_bytecode_src(bc_src, shader_src, chan);
6504
6505 /* op3 operands don't support abs modifier */
6506 if (bc_src->abs) {
6507 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
6508 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6509 alu.op = ALU_OP1_MOV;
6510 alu.dst.sel = temp;
6511 alu.dst.chan = chan;
6512 alu.dst.write = 1;
6513
6514 alu.src[0] = *bc_src;
6515 alu.last = true; // sufficient?
6516 r = r600_bytecode_add_alu(ctx->bc, &alu);
6517 if (r)
6518 return r;
6519
6520 memset(bc_src, 0, sizeof(*bc_src));
6521 bc_src->sel = temp;
6522 bc_src->chan = chan;
6523 }
6524 return 0;
6525 }
6526
6527 static int tgsi_op3(struct r600_shader_ctx *ctx)
6528 {
6529 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6530 struct r600_bytecode_alu alu;
6531 int i, j, r;
6532 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6533 int temp_regs[4];
6534 unsigned op = ctx->inst_info->op;
6535
6536 if (op == ALU_OP3_MULADD_IEEE &&
6537 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6538 op = ALU_OP3_MULADD;
6539
6540 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6541 temp_regs[j] = 0;
6542 if (ctx->src[j].abs)
6543 temp_regs[j] = r600_get_temp(ctx);
6544 }
6545 for (i = 0; i < lasti + 1; i++) {
6546 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6547 continue;
6548
6549 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6550 alu.op = op;
6551 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6552 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
6553 if (r)
6554 return r;
6555 }
6556
6557 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6558 alu.dst.chan = i;
6559 alu.dst.write = 1;
6560 alu.is_op3 = 1;
6561 if (i == lasti) {
6562 alu.last = 1;
6563 }
6564 r = r600_bytecode_add_alu(ctx->bc, &alu);
6565 if (r)
6566 return r;
6567 }
6568 return 0;
6569 }
6570
6571 static int tgsi_dp(struct r600_shader_ctx *ctx)
6572 {
6573 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6574 struct r600_bytecode_alu alu;
6575 int i, j, r;
6576 unsigned op = ctx->inst_info->op;
6577 if (op == ALU_OP2_DOT4_IEEE &&
6578 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6579 op = ALU_OP2_DOT4;
6580
6581 for (i = 0; i < 4; i++) {
6582 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6583 alu.op = op;
6584 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6585 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6586 }
6587
6588 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6589 alu.dst.chan = i;
6590 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
6591 /* handle some special cases */
6592 switch (inst->Instruction.Opcode) {
6593 case TGSI_OPCODE_DP2:
6594 if (i > 1) {
6595 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6596 alu.src[0].chan = alu.src[1].chan = 0;
6597 }
6598 break;
6599 case TGSI_OPCODE_DP3:
6600 if (i > 2) {
6601 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6602 alu.src[0].chan = alu.src[1].chan = 0;
6603 }
6604 break;
6605 default:
6606 break;
6607 }
6608 if (i == 3) {
6609 alu.last = 1;
6610 }
6611 r = r600_bytecode_add_alu(ctx->bc, &alu);
6612 if (r)
6613 return r;
6614 }
6615 return 0;
6616 }
6617
6618 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
6619 unsigned index)
6620 {
6621 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6622 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
6623 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
6624 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
6625 ctx->src[index].neg || ctx->src[index].abs ||
6626 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
6627 }
6628
6629 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
6630 unsigned index)
6631 {
6632 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6633 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
6634 }
6635
6636 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
6637 {
6638 struct r600_bytecode_vtx vtx;
6639 struct r600_bytecode_alu alu;
6640 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6641 int src_gpr, r, i;
6642 int id = tgsi_tex_get_src_gpr(ctx, 1);
6643
6644 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6645 if (src_requires_loading) {
6646 for (i = 0; i < 4; i++) {
6647 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6648 alu.op = ALU_OP1_MOV;
6649 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6650 alu.dst.sel = ctx->temp_reg;
6651 alu.dst.chan = i;
6652 if (i == 3)
6653 alu.last = 1;
6654 alu.dst.write = 1;
6655 r = r600_bytecode_add_alu(ctx->bc, &alu);
6656 if (r)
6657 return r;
6658 }
6659 src_gpr = ctx->temp_reg;
6660 }
6661
6662 memset(&vtx, 0, sizeof(vtx));
6663 vtx.op = FETCH_OP_VFETCH;
6664 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6665 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6666 vtx.src_gpr = src_gpr;
6667 vtx.mega_fetch_count = 16;
6668 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6669 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6670 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
6671 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
6672 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
6673 vtx.use_const_fields = 1;
6674
6675 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
6676 return r;
6677
6678 if (ctx->bc->chip_class >= EVERGREEN)
6679 return 0;
6680
6681 for (i = 0; i < 4; i++) {
6682 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6683 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6684 continue;
6685
6686 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6687 alu.op = ALU_OP2_AND_INT;
6688
6689 alu.dst.chan = i;
6690 alu.dst.sel = vtx.dst_gpr;
6691 alu.dst.write = 1;
6692
6693 alu.src[0].sel = vtx.dst_gpr;
6694 alu.src[0].chan = i;
6695
6696 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
6697 alu.src[1].sel += (id * 2);
6698 alu.src[1].chan = i % 4;
6699 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6700
6701 if (i == lasti)
6702 alu.last = 1;
6703 r = r600_bytecode_add_alu(ctx->bc, &alu);
6704 if (r)
6705 return r;
6706 }
6707
6708 if (inst->Dst[0].Register.WriteMask & 3) {
6709 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6710 alu.op = ALU_OP2_OR_INT;
6711
6712 alu.dst.chan = 3;
6713 alu.dst.sel = vtx.dst_gpr;
6714 alu.dst.write = 1;
6715
6716 alu.src[0].sel = vtx.dst_gpr;
6717 alu.src[0].chan = 3;
6718
6719 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
6720 alu.src[1].chan = 0;
6721 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6722
6723 alu.last = 1;
6724 r = r600_bytecode_add_alu(ctx->bc, &alu);
6725 if (r)
6726 return r;
6727 }
6728 return 0;
6729 }
6730
6731 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
6732 {
6733 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6734 struct r600_bytecode_alu alu;
6735 int r;
6736 int id = tgsi_tex_get_src_gpr(ctx, 1);
6737
6738 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6739 alu.op = ALU_OP1_MOV;
6740 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6741 if (ctx->bc->chip_class >= EVERGREEN) {
6742 /* channel 0 or 2 of each word */
6743 alu.src[0].sel += (id / 2);
6744 alu.src[0].chan = (id % 2) * 2;
6745 } else {
6746 /* r600 we have them at channel 2 of the second dword */
6747 alu.src[0].sel += (id * 2) + 1;
6748 alu.src[0].chan = 1;
6749 }
6750 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6751 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
6752 alu.last = 1;
6753 r = r600_bytecode_add_alu(ctx->bc, &alu);
6754 if (r)
6755 return r;
6756 return 0;
6757 }
6758
6759 static int tgsi_tex(struct r600_shader_ctx *ctx)
6760 {
6761 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6762 struct r600_bytecode_tex tex;
6763 struct r600_bytecode_alu alu;
6764 unsigned src_gpr;
6765 int r, i, j;
6766 int opcode;
6767 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
6768 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6769 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
6770 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
6771
6772 bool txf_add_offsets = inst->Texture.NumOffsets &&
6773 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6774 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
6775
6776 /* Texture fetch instructions can only use gprs as source.
6777 * Also they cannot negate the source or take the absolute value */
6778 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
6779 tgsi_tex_src_requires_loading(ctx, 0)) ||
6780 read_compressed_msaa || txf_add_offsets;
6781
6782 boolean src_loaded = FALSE;
6783 unsigned sampler_src_reg = 1;
6784 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
6785 boolean has_txq_cube_array_z = false;
6786 unsigned sampler_index_mode;
6787
6788 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
6789 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6790 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
6791 if (inst->Dst[0].Register.WriteMask & 4) {
6792 ctx->shader->has_txq_cube_array_z_comp = true;
6793 has_txq_cube_array_z = true;
6794 }
6795
6796 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
6797 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
6798 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
6799 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
6800 sampler_src_reg = 2;
6801
6802 /* TGSI moves the sampler to src reg 3 for TXD */
6803 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
6804 sampler_src_reg = 3;
6805
6806 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6807
6808 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6809
6810 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
6811 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
6812 ctx->shader->uses_tex_buffers = true;
6813 return r600_do_buffer_txq(ctx);
6814 }
6815 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
6816 if (ctx->bc->chip_class < EVERGREEN)
6817 ctx->shader->uses_tex_buffers = true;
6818 return do_vtx_fetch_inst(ctx, src_requires_loading);
6819 }
6820 }
6821
6822 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
6823 int out_chan;
6824 /* Add perspective divide */
6825 if (ctx->bc->chip_class == CAYMAN) {
6826 out_chan = 2;
6827 for (i = 0; i < 3; i++) {
6828 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6829 alu.op = ALU_OP1_RECIP_IEEE;
6830 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6831
6832 alu.dst.sel = ctx->temp_reg;
6833 alu.dst.chan = i;
6834 if (i == 2)
6835 alu.last = 1;
6836 if (out_chan == i)
6837 alu.dst.write = 1;
6838 r = r600_bytecode_add_alu(ctx->bc, &alu);
6839 if (r)
6840 return r;
6841 }
6842
6843 } else {
6844 out_chan = 3;
6845 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6846 alu.op = ALU_OP1_RECIP_IEEE;
6847 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6848
6849 alu.dst.sel = ctx->temp_reg;
6850 alu.dst.chan = out_chan;
6851 alu.last = 1;
6852 alu.dst.write = 1;
6853 r = r600_bytecode_add_alu(ctx->bc, &alu);
6854 if (r)
6855 return r;
6856 }
6857
6858 for (i = 0; i < 3; i++) {
6859 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6860 alu.op = ALU_OP2_MUL;
6861 alu.src[0].sel = ctx->temp_reg;
6862 alu.src[0].chan = out_chan;
6863 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6864 alu.dst.sel = ctx->temp_reg;
6865 alu.dst.chan = i;
6866 alu.dst.write = 1;
6867 r = r600_bytecode_add_alu(ctx->bc, &alu);
6868 if (r)
6869 return r;
6870 }
6871 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6872 alu.op = ALU_OP1_MOV;
6873 alu.src[0].sel = V_SQ_ALU_SRC_1;
6874 alu.src[0].chan = 0;
6875 alu.dst.sel = ctx->temp_reg;
6876 alu.dst.chan = 3;
6877 alu.last = 1;
6878 alu.dst.write = 1;
6879 r = r600_bytecode_add_alu(ctx->bc, &alu);
6880 if (r)
6881 return r;
6882 src_loaded = TRUE;
6883 src_gpr = ctx->temp_reg;
6884 }
6885
6886
6887 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
6888 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6889 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6890 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
6891 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
6892
6893 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
6894 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
6895
6896 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
6897 for (i = 0; i < 4; i++) {
6898 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6899 alu.op = ALU_OP2_CUBE;
6900 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6901 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
6902 alu.dst.sel = ctx->temp_reg;
6903 alu.dst.chan = i;
6904 if (i == 3)
6905 alu.last = 1;
6906 alu.dst.write = 1;
6907 r = r600_bytecode_add_alu(ctx->bc, &alu);
6908 if (r)
6909 return r;
6910 }
6911
6912 /* tmp1.z = RCP_e(|tmp1.z|) */
6913 if (ctx->bc->chip_class == CAYMAN) {
6914 for (i = 0; i < 3; i++) {
6915 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6916 alu.op = ALU_OP1_RECIP_IEEE;
6917 alu.src[0].sel = ctx->temp_reg;
6918 alu.src[0].chan = 2;
6919 alu.src[0].abs = 1;
6920 alu.dst.sel = ctx->temp_reg;
6921 alu.dst.chan = i;
6922 if (i == 2)
6923 alu.dst.write = 1;
6924 if (i == 2)
6925 alu.last = 1;
6926 r = r600_bytecode_add_alu(ctx->bc, &alu);
6927 if (r)
6928 return r;
6929 }
6930 } else {
6931 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6932 alu.op = ALU_OP1_RECIP_IEEE;
6933 alu.src[0].sel = ctx->temp_reg;
6934 alu.src[0].chan = 2;
6935 alu.src[0].abs = 1;
6936 alu.dst.sel = ctx->temp_reg;
6937 alu.dst.chan = 2;
6938 alu.dst.write = 1;
6939 alu.last = 1;
6940 r = r600_bytecode_add_alu(ctx->bc, &alu);
6941 if (r)
6942 return r;
6943 }
6944
6945 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
6946 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
6947 * muladd has no writemask, have to use another temp
6948 */
6949 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6950 alu.op = ALU_OP3_MULADD;
6951 alu.is_op3 = 1;
6952
6953 alu.src[0].sel = ctx->temp_reg;
6954 alu.src[0].chan = 0;
6955 alu.src[1].sel = ctx->temp_reg;
6956 alu.src[1].chan = 2;
6957
6958 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
6959 alu.src[2].chan = 0;
6960 alu.src[2].value = u_bitcast_f2u(1.5f);
6961
6962 alu.dst.sel = ctx->temp_reg;
6963 alu.dst.chan = 0;
6964 alu.dst.write = 1;
6965
6966 r = r600_bytecode_add_alu(ctx->bc, &alu);
6967 if (r)
6968 return r;
6969
6970 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6971 alu.op = ALU_OP3_MULADD;
6972 alu.is_op3 = 1;
6973
6974 alu.src[0].sel = ctx->temp_reg;
6975 alu.src[0].chan = 1;
6976 alu.src[1].sel = ctx->temp_reg;
6977 alu.src[1].chan = 2;
6978
6979 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
6980 alu.src[2].chan = 0;
6981 alu.src[2].value = u_bitcast_f2u(1.5f);
6982
6983 alu.dst.sel = ctx->temp_reg;
6984 alu.dst.chan = 1;
6985 alu.dst.write = 1;
6986
6987 alu.last = 1;
6988 r = r600_bytecode_add_alu(ctx->bc, &alu);
6989 if (r)
6990 return r;
6991 /* write initial compare value into Z component
6992 - W src 0 for shadow cube
6993 - X src 1 for shadow cube array */
6994 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6995 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6996 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6997 alu.op = ALU_OP1_MOV;
6998 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
6999 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7000 else
7001 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7002 alu.dst.sel = ctx->temp_reg;
7003 alu.dst.chan = 2;
7004 alu.dst.write = 1;
7005 alu.last = 1;
7006 r = r600_bytecode_add_alu(ctx->bc, &alu);
7007 if (r)
7008 return r;
7009 }
7010
7011 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7012 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7013 if (ctx->bc->chip_class >= EVERGREEN) {
7014 int mytmp = r600_get_temp(ctx);
7015 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7016 alu.op = ALU_OP1_MOV;
7017 alu.src[0].sel = ctx->temp_reg;
7018 alu.src[0].chan = 3;
7019 alu.dst.sel = mytmp;
7020 alu.dst.chan = 0;
7021 alu.dst.write = 1;
7022 alu.last = 1;
7023 r = r600_bytecode_add_alu(ctx->bc, &alu);
7024 if (r)
7025 return r;
7026
7027 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7028 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7029 alu.op = ALU_OP3_MULADD;
7030 alu.is_op3 = 1;
7031 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7032 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7033 alu.src[1].chan = 0;
7034 alu.src[1].value = u_bitcast_f2u(8.0f);
7035 alu.src[2].sel = mytmp;
7036 alu.src[2].chan = 0;
7037 alu.dst.sel = ctx->temp_reg;
7038 alu.dst.chan = 3;
7039 alu.dst.write = 1;
7040 alu.last = 1;
7041 r = r600_bytecode_add_alu(ctx->bc, &alu);
7042 if (r)
7043 return r;
7044 } else if (ctx->bc->chip_class < EVERGREEN) {
7045 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7046 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7047 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7048 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7049 tex.src_gpr = r600_get_temp(ctx);
7050 tex.src_sel_x = 0;
7051 tex.src_sel_y = 0;
7052 tex.src_sel_z = 0;
7053 tex.src_sel_w = 0;
7054 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7055 tex.coord_type_x = 1;
7056 tex.coord_type_y = 1;
7057 tex.coord_type_z = 1;
7058 tex.coord_type_w = 1;
7059 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7060 alu.op = ALU_OP1_MOV;
7061 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7062 alu.dst.sel = tex.src_gpr;
7063 alu.dst.chan = 0;
7064 alu.last = 1;
7065 alu.dst.write = 1;
7066 r = r600_bytecode_add_alu(ctx->bc, &alu);
7067 if (r)
7068 return r;
7069
7070 r = r600_bytecode_add_tex(ctx->bc, &tex);
7071 if (r)
7072 return r;
7073 }
7074
7075 }
7076
7077 /* for cube forms of lod and bias we need to route things */
7078 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7079 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7080 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7081 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7082 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7083 alu.op = ALU_OP1_MOV;
7084 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7085 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7086 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7087 else
7088 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7089 alu.dst.sel = ctx->temp_reg;
7090 alu.dst.chan = 2;
7091 alu.last = 1;
7092 alu.dst.write = 1;
7093 r = r600_bytecode_add_alu(ctx->bc, &alu);
7094 if (r)
7095 return r;
7096 }
7097
7098 src_loaded = TRUE;
7099 src_gpr = ctx->temp_reg;
7100 }
7101
7102 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7103 int temp_h = 0, temp_v = 0;
7104 int start_val = 0;
7105
7106 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7107 if (src_loaded == TRUE)
7108 start_val = 1;
7109 else
7110 src_loaded = TRUE;
7111 for (i = start_val; i < 3; i++) {
7112 int treg = r600_get_temp(ctx);
7113
7114 if (i == 0)
7115 src_gpr = treg;
7116 else if (i == 1)
7117 temp_h = treg;
7118 else
7119 temp_v = treg;
7120
7121 for (j = 0; j < 4; j++) {
7122 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7123 alu.op = ALU_OP1_MOV;
7124 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7125 alu.dst.sel = treg;
7126 alu.dst.chan = j;
7127 if (j == 3)
7128 alu.last = 1;
7129 alu.dst.write = 1;
7130 r = r600_bytecode_add_alu(ctx->bc, &alu);
7131 if (r)
7132 return r;
7133 }
7134 }
7135 for (i = 1; i < 3; i++) {
7136 /* set gradients h/v */
7137 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7138 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7139 FETCH_OP_SET_GRADIENTS_V;
7140 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7141 tex.sampler_index_mode = sampler_index_mode;
7142 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7143 tex.resource_index_mode = sampler_index_mode;
7144
7145 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7146 tex.src_sel_x = 0;
7147 tex.src_sel_y = 1;
7148 tex.src_sel_z = 2;
7149 tex.src_sel_w = 3;
7150
7151 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7152 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7153 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7154 tex.coord_type_x = 1;
7155 tex.coord_type_y = 1;
7156 tex.coord_type_z = 1;
7157 tex.coord_type_w = 1;
7158 }
7159 r = r600_bytecode_add_tex(ctx->bc, &tex);
7160 if (r)
7161 return r;
7162 }
7163 }
7164
7165 if (src_requires_loading && !src_loaded) {
7166 for (i = 0; i < 4; i++) {
7167 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7168 alu.op = ALU_OP1_MOV;
7169 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7170 alu.dst.sel = ctx->temp_reg;
7171 alu.dst.chan = i;
7172 if (i == 3)
7173 alu.last = 1;
7174 alu.dst.write = 1;
7175 r = r600_bytecode_add_alu(ctx->bc, &alu);
7176 if (r)
7177 return r;
7178 }
7179 src_loaded = TRUE;
7180 src_gpr = ctx->temp_reg;
7181 }
7182
7183 /* get offset values */
7184 if (inst->Texture.NumOffsets) {
7185 assert(inst->Texture.NumOffsets == 1);
7186
7187 /* The texture offset feature doesn't work with the TXF instruction
7188 * and must be emulated by adding the offset to the texture coordinates. */
7189 if (txf_add_offsets) {
7190 const struct tgsi_texture_offset *off = inst->TexOffsets;
7191
7192 switch (inst->Texture.Texture) {
7193 case TGSI_TEXTURE_3D:
7194 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7195 alu.op = ALU_OP2_ADD_INT;
7196 alu.src[0].sel = src_gpr;
7197 alu.src[0].chan = 2;
7198 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7199 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7200 alu.dst.sel = src_gpr;
7201 alu.dst.chan = 2;
7202 alu.dst.write = 1;
7203 alu.last = 1;
7204 r = r600_bytecode_add_alu(ctx->bc, &alu);
7205 if (r)
7206 return r;
7207 /* fall through */
7208
7209 case TGSI_TEXTURE_2D:
7210 case TGSI_TEXTURE_SHADOW2D:
7211 case TGSI_TEXTURE_RECT:
7212 case TGSI_TEXTURE_SHADOWRECT:
7213 case TGSI_TEXTURE_2D_ARRAY:
7214 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7215 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7216 alu.op = ALU_OP2_ADD_INT;
7217 alu.src[0].sel = src_gpr;
7218 alu.src[0].chan = 1;
7219 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7220 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7221 alu.dst.sel = src_gpr;
7222 alu.dst.chan = 1;
7223 alu.dst.write = 1;
7224 alu.last = 1;
7225 r = r600_bytecode_add_alu(ctx->bc, &alu);
7226 if (r)
7227 return r;
7228 /* fall through */
7229
7230 case TGSI_TEXTURE_1D:
7231 case TGSI_TEXTURE_SHADOW1D:
7232 case TGSI_TEXTURE_1D_ARRAY:
7233 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7234 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7235 alu.op = ALU_OP2_ADD_INT;
7236 alu.src[0].sel = src_gpr;
7237 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7238 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
7239 alu.dst.sel = src_gpr;
7240 alu.dst.write = 1;
7241 alu.last = 1;
7242 r = r600_bytecode_add_alu(ctx->bc, &alu);
7243 if (r)
7244 return r;
7245 break;
7246 /* texture offsets do not apply to other texture targets */
7247 }
7248 } else {
7249 switch (inst->Texture.Texture) {
7250 case TGSI_TEXTURE_3D:
7251 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
7252 /* fallthrough */
7253 case TGSI_TEXTURE_2D:
7254 case TGSI_TEXTURE_SHADOW2D:
7255 case TGSI_TEXTURE_RECT:
7256 case TGSI_TEXTURE_SHADOWRECT:
7257 case TGSI_TEXTURE_2D_ARRAY:
7258 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7259 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
7260 /* fallthrough */
7261 case TGSI_TEXTURE_1D:
7262 case TGSI_TEXTURE_SHADOW1D:
7263 case TGSI_TEXTURE_1D_ARRAY:
7264 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7265 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
7266 }
7267 }
7268 }
7269
7270 /* Obtain the sample index for reading a compressed MSAA color texture.
7271 * To read the FMASK, we use the ldfptr instruction, which tells us
7272 * where the samples are stored.
7273 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7274 * which is the identity mapping. Each nibble says which physical sample
7275 * should be fetched to get that sample.
7276 *
7277 * Assume src.z contains the sample index. It should be modified like this:
7278 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7279 * Then fetch the texel with src.
7280 */
7281 if (read_compressed_msaa) {
7282 unsigned sample_chan = 3;
7283 unsigned temp = r600_get_temp(ctx);
7284 assert(src_loaded);
7285
7286 /* temp.w = ldfptr() */
7287 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7288 tex.op = FETCH_OP_LD;
7289 tex.inst_mod = 1; /* to indicate this is ldfptr */
7290 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7291 tex.sampler_index_mode = sampler_index_mode;
7292 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7293 tex.resource_index_mode = sampler_index_mode;
7294 tex.src_gpr = src_gpr;
7295 tex.dst_gpr = temp;
7296 tex.dst_sel_x = 7; /* mask out these components */
7297 tex.dst_sel_y = 7;
7298 tex.dst_sel_z = 7;
7299 tex.dst_sel_w = 0; /* store X */
7300 tex.src_sel_x = 0;
7301 tex.src_sel_y = 1;
7302 tex.src_sel_z = 2;
7303 tex.src_sel_w = 3;
7304 tex.offset_x = offset_x;
7305 tex.offset_y = offset_y;
7306 tex.offset_z = offset_z;
7307 r = r600_bytecode_add_tex(ctx->bc, &tex);
7308 if (r)
7309 return r;
7310
7311 /* temp.x = sample_index*4 */
7312 if (ctx->bc->chip_class == CAYMAN) {
7313 for (i = 0 ; i < 4; i++) {
7314 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7315 alu.op = ALU_OP2_MULLO_INT;
7316 alu.src[0].sel = src_gpr;
7317 alu.src[0].chan = sample_chan;
7318 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7319 alu.src[1].value = 4;
7320 alu.dst.sel = temp;
7321 alu.dst.chan = i;
7322 alu.dst.write = i == 0;
7323 if (i == 3)
7324 alu.last = 1;
7325 r = r600_bytecode_add_alu(ctx->bc, &alu);
7326 if (r)
7327 return r;
7328 }
7329 } else {
7330 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7331 alu.op = ALU_OP2_MULLO_INT;
7332 alu.src[0].sel = src_gpr;
7333 alu.src[0].chan = sample_chan;
7334 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7335 alu.src[1].value = 4;
7336 alu.dst.sel = temp;
7337 alu.dst.chan = 0;
7338 alu.dst.write = 1;
7339 alu.last = 1;
7340 r = r600_bytecode_add_alu(ctx->bc, &alu);
7341 if (r)
7342 return r;
7343 }
7344
7345 /* sample_index = temp.w >> temp.x */
7346 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7347 alu.op = ALU_OP2_LSHR_INT;
7348 alu.src[0].sel = temp;
7349 alu.src[0].chan = 3;
7350 alu.src[1].sel = temp;
7351 alu.src[1].chan = 0;
7352 alu.dst.sel = src_gpr;
7353 alu.dst.chan = sample_chan;
7354 alu.dst.write = 1;
7355 alu.last = 1;
7356 r = r600_bytecode_add_alu(ctx->bc, &alu);
7357 if (r)
7358 return r;
7359
7360 /* sample_index & 0xF */
7361 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7362 alu.op = ALU_OP2_AND_INT;
7363 alu.src[0].sel = src_gpr;
7364 alu.src[0].chan = sample_chan;
7365 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7366 alu.src[1].value = 0xF;
7367 alu.dst.sel = src_gpr;
7368 alu.dst.chan = sample_chan;
7369 alu.dst.write = 1;
7370 alu.last = 1;
7371 r = r600_bytecode_add_alu(ctx->bc, &alu);
7372 if (r)
7373 return r;
7374 #if 0
7375 /* visualize the FMASK */
7376 for (i = 0; i < 4; i++) {
7377 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7378 alu.op = ALU_OP1_INT_TO_FLT;
7379 alu.src[0].sel = src_gpr;
7380 alu.src[0].chan = sample_chan;
7381 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7382 alu.dst.chan = i;
7383 alu.dst.write = 1;
7384 alu.last = 1;
7385 r = r600_bytecode_add_alu(ctx->bc, &alu);
7386 if (r)
7387 return r;
7388 }
7389 return 0;
7390 #endif
7391 }
7392
7393 /* does this shader want a num layers from TXQ for a cube array? */
7394 if (has_txq_cube_array_z) {
7395 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7396
7397 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7398 alu.op = ALU_OP1_MOV;
7399
7400 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7401 if (ctx->bc->chip_class >= EVERGREEN) {
7402 /* channel 1 or 3 of each word */
7403 alu.src[0].sel += (id / 2);
7404 alu.src[0].chan = ((id % 2) * 2) + 1;
7405 } else {
7406 /* r600 we have them at channel 2 of the second dword */
7407 alu.src[0].sel += (id * 2) + 1;
7408 alu.src[0].chan = 2;
7409 }
7410 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7411 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
7412 alu.last = 1;
7413 r = r600_bytecode_add_alu(ctx->bc, &alu);
7414 if (r)
7415 return r;
7416 /* disable writemask from texture instruction */
7417 inst->Dst[0].Register.WriteMask &= ~4;
7418 }
7419
7420 opcode = ctx->inst_info->op;
7421 if (opcode == FETCH_OP_GATHER4 &&
7422 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
7423 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
7424 opcode = FETCH_OP_GATHER4_O;
7425
7426 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7427 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7428 encoded in the instruction are ignored. */
7429 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7430 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
7431 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7432 tex.sampler_index_mode = sampler_index_mode;
7433 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7434 tex.resource_index_mode = sampler_index_mode;
7435
7436 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
7437 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
7438 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
7439 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
7440 tex.src_sel_w = 4;
7441
7442 tex.dst_sel_x = 7;
7443 tex.dst_sel_y = 7;
7444 tex.dst_sel_z = 7;
7445 tex.dst_sel_w = 7;
7446
7447 r = r600_bytecode_add_tex(ctx->bc, &tex);
7448 if (r)
7449 return r;
7450 }
7451
7452 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7453 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7454 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7455 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7456 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
7457 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7458 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7459 switch (opcode) {
7460 case FETCH_OP_SAMPLE:
7461 opcode = FETCH_OP_SAMPLE_C;
7462 break;
7463 case FETCH_OP_SAMPLE_L:
7464 opcode = FETCH_OP_SAMPLE_C_L;
7465 break;
7466 case FETCH_OP_SAMPLE_LB:
7467 opcode = FETCH_OP_SAMPLE_C_LB;
7468 break;
7469 case FETCH_OP_SAMPLE_G:
7470 opcode = FETCH_OP_SAMPLE_C_G;
7471 break;
7472 /* Texture gather variants */
7473 case FETCH_OP_GATHER4:
7474 opcode = FETCH_OP_GATHER4_C;
7475 break;
7476 case FETCH_OP_GATHER4_O:
7477 opcode = FETCH_OP_GATHER4_C_O;
7478 break;
7479 }
7480 }
7481
7482 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7483 tex.op = opcode;
7484
7485 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7486 tex.sampler_index_mode = sampler_index_mode;
7487 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7488 tex.resource_index_mode = sampler_index_mode;
7489 tex.src_gpr = src_gpr;
7490 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7491
7492 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
7493 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
7494 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
7495 }
7496
7497 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7498 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
7499 tex.inst_mod = texture_component_select;
7500
7501 if (ctx->bc->chip_class == CAYMAN) {
7502 /* GATHER4 result order is different from TGSI TG4 */
7503 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
7504 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
7505 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
7506 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7507 } else {
7508 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7509 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7510 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7511 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7512 }
7513 }
7514 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
7515 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7516 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7517 tex.dst_sel_z = 7;
7518 tex.dst_sel_w = 7;
7519 }
7520 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7521 tex.dst_sel_x = 3;
7522 tex.dst_sel_y = 7;
7523 tex.dst_sel_z = 7;
7524 tex.dst_sel_w = 7;
7525 }
7526 else {
7527 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7528 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7529 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7530 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7531 }
7532
7533
7534 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7535 tex.src_sel_x = 4;
7536 tex.src_sel_y = 4;
7537 tex.src_sel_z = 4;
7538 tex.src_sel_w = 4;
7539 } else if (src_loaded) {
7540 tex.src_sel_x = 0;
7541 tex.src_sel_y = 1;
7542 tex.src_sel_z = 2;
7543 tex.src_sel_w = 3;
7544 } else {
7545 tex.src_sel_x = ctx->src[0].swizzle[0];
7546 tex.src_sel_y = ctx->src[0].swizzle[1];
7547 tex.src_sel_z = ctx->src[0].swizzle[2];
7548 tex.src_sel_w = ctx->src[0].swizzle[3];
7549 tex.src_rel = ctx->src[0].rel;
7550 }
7551
7552 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7553 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7554 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7555 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7556 tex.src_sel_x = 1;
7557 tex.src_sel_y = 0;
7558 tex.src_sel_z = 3;
7559 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
7560 }
7561
7562 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
7563 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
7564 tex.coord_type_x = 1;
7565 tex.coord_type_y = 1;
7566 }
7567 tex.coord_type_z = 1;
7568 tex.coord_type_w = 1;
7569
7570 tex.offset_x = offset_x;
7571 tex.offset_y = offset_y;
7572 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
7573 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7574 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
7575 tex.offset_z = 0;
7576 }
7577 else {
7578 tex.offset_z = offset_z;
7579 }
7580
7581 /* Put the depth for comparison in W.
7582 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7583 * Some instructions expect the depth in Z. */
7584 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7585 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7586 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7587 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
7588 opcode != FETCH_OP_SAMPLE_C_L &&
7589 opcode != FETCH_OP_SAMPLE_C_LB) {
7590 tex.src_sel_w = tex.src_sel_z;
7591 }
7592
7593 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
7594 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
7595 if (opcode == FETCH_OP_SAMPLE_C_L ||
7596 opcode == FETCH_OP_SAMPLE_C_LB) {
7597 /* the array index is read from Y */
7598 tex.coord_type_y = 0;
7599 } else {
7600 /* the array index is read from Z */
7601 tex.coord_type_z = 0;
7602 tex.src_sel_z = tex.src_sel_y;
7603 }
7604 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7605 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7606 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7607 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7608 (ctx->bc->chip_class >= EVERGREEN)))
7609 /* the array index is read from Z */
7610 tex.coord_type_z = 0;
7611
7612 /* mask unused source components */
7613 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
7614 switch (inst->Texture.Texture) {
7615 case TGSI_TEXTURE_2D:
7616 case TGSI_TEXTURE_RECT:
7617 tex.src_sel_z = 7;
7618 tex.src_sel_w = 7;
7619 break;
7620 case TGSI_TEXTURE_1D_ARRAY:
7621 tex.src_sel_y = 7;
7622 tex.src_sel_w = 7;
7623 break;
7624 case TGSI_TEXTURE_1D:
7625 tex.src_sel_y = 7;
7626 tex.src_sel_z = 7;
7627 tex.src_sel_w = 7;
7628 break;
7629 }
7630 }
7631
7632 r = r600_bytecode_add_tex(ctx->bc, &tex);
7633 if (r)
7634 return r;
7635
7636 /* add shadow ambient support - gallium doesn't do it yet */
7637 return 0;
7638 }
7639
7640 static int find_hw_atomic_counter(struct r600_shader_ctx *ctx,
7641 struct tgsi_full_src_register *src)
7642 {
7643 int i;
7644
7645 if (src->Register.Indirect) {
7646 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7647 if (src->Indirect.ArrayID == ctx->shader->atomics[i].array_id)
7648 return ctx->shader->atomics[i].hw_idx;
7649 }
7650 } else {
7651 uint32_t index = src->Register.Index;
7652 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7653 if (ctx->shader->atomics[i].buffer_id != src->Dimension.Index)
7654 continue;
7655 if (index > ctx->shader->atomics[i].end)
7656 continue;
7657 if (index < ctx->shader->atomics[i].start)
7658 continue;
7659 uint32_t offset = (index - ctx->shader->atomics[i].start);
7660 return ctx->shader->atomics[i].hw_idx + offset;
7661 }
7662 }
7663 assert(0);
7664 return -1;
7665 }
7666
7667
7668 static int tgsi_load_gds(struct r600_shader_ctx *ctx)
7669 {
7670 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7671 int r;
7672 struct r600_bytecode_gds gds;
7673 int uav_id = 0;
7674 int uav_index_mode = 0;
7675
7676 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
7677
7678 if (inst->Src[0].Register.Indirect)
7679 uav_index_mode = 2;
7680
7681 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
7682 gds.op = FETCH_OP_GDS_READ_RET;
7683 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7684 gds.uav_id = uav_id;
7685 gds.uav_index_mode = uav_index_mode;
7686 gds.src_gpr = ctx->temp_reg;
7687 gds.src_sel_x = 4;
7688 gds.src_sel_y = 4;
7689 gds.src_sel_z = 4;
7690 gds.dst_sel_x = 0;
7691 gds.dst_sel_y = 7;
7692 gds.dst_sel_z = 7;
7693 gds.dst_sel_w = 7;
7694 gds.src_gpr2 = ctx->temp_reg;
7695 gds.alloc_consume = 1;
7696 r = r600_bytecode_add_gds(ctx->bc, &gds);
7697 if (r)
7698 return r;
7699
7700 ctx->bc->cf_last->vpm = 1;
7701 return 0;
7702 }
7703
7704 static int tgsi_load(struct r600_shader_ctx *ctx)
7705 {
7706 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7707 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
7708 return tgsi_load_gds(ctx);
7709 return 0;
7710 }
7711
7712 static int get_gds_op(int opcode)
7713 {
7714 switch (opcode) {
7715 case TGSI_OPCODE_ATOMUADD:
7716 return FETCH_OP_GDS_ADD_RET;
7717 case TGSI_OPCODE_ATOMAND:
7718 return FETCH_OP_GDS_AND_RET;
7719 case TGSI_OPCODE_ATOMOR:
7720 return FETCH_OP_GDS_OR_RET;
7721 case TGSI_OPCODE_ATOMXOR:
7722 return FETCH_OP_GDS_XOR_RET;
7723 case TGSI_OPCODE_ATOMUMIN:
7724 return FETCH_OP_GDS_MIN_UINT_RET;
7725 case TGSI_OPCODE_ATOMUMAX:
7726 return FETCH_OP_GDS_MAX_UINT_RET;
7727 case TGSI_OPCODE_ATOMXCHG:
7728 return FETCH_OP_GDS_XCHG_RET;
7729 case TGSI_OPCODE_ATOMCAS:
7730 return FETCH_OP_GDS_CMP_XCHG_RET;
7731 default:
7732 return -1;
7733 }
7734 }
7735
7736 static int tgsi_atomic_op_gds(struct r600_shader_ctx *ctx)
7737 {
7738 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7739 struct r600_bytecode_gds gds;
7740 struct r600_bytecode_alu alu;
7741 int gds_op = get_gds_op(inst->Instruction.Opcode);
7742 int r;
7743 int uav_id = 0;
7744 int uav_index_mode = 0;
7745
7746 if (gds_op == -1) {
7747 fprintf(stderr, "unknown GDS op for opcode %d\n", inst->Instruction.Opcode);
7748 return -1;
7749 }
7750
7751 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
7752
7753 if (inst->Src[0].Register.Indirect)
7754 uav_index_mode = 2;
7755
7756 if (inst->Src[2].Register.File == TGSI_FILE_IMMEDIATE) {
7757 int value = (ctx->literals[4 * inst->Src[2].Register.Index + inst->Src[2].Register.SwizzleX]);
7758 int abs_value = abs(value);
7759 if (abs_value != value && gds_op == FETCH_OP_GDS_ADD_RET)
7760 gds_op = FETCH_OP_GDS_SUB_RET;
7761 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7762 alu.op = ALU_OP1_MOV;
7763 alu.dst.sel = ctx->temp_reg;
7764 alu.dst.chan = 0;
7765 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
7766 alu.src[0].value = abs_value;
7767 alu.last = 1;
7768 alu.dst.write = 1;
7769 r = r600_bytecode_add_alu(ctx->bc, &alu);
7770 if (r)
7771 return r;
7772 } else {
7773 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7774 alu.op = ALU_OP1_MOV;
7775 alu.dst.sel = ctx->temp_reg;
7776 alu.dst.chan = 0;
7777 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
7778 alu.last = 1;
7779 alu.dst.write = 1;
7780 r = r600_bytecode_add_alu(ctx->bc, &alu);
7781 if (r)
7782 return r;
7783 }
7784
7785 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
7786 gds.op = gds_op;
7787 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7788 gds.uav_id = uav_id;
7789 gds.uav_index_mode = uav_index_mode;
7790 gds.src_gpr = ctx->temp_reg;
7791 gds.src_gpr2 = ctx->temp_reg;
7792 gds.src_sel_x = 4;
7793 gds.src_sel_y = 0;
7794 gds.src_sel_z = 4;
7795 gds.dst_sel_x = 0;
7796 gds.dst_sel_y = 7;
7797 gds.dst_sel_z = 7;
7798 gds.dst_sel_w = 7;
7799 gds.alloc_consume = 1;
7800 r = r600_bytecode_add_gds(ctx->bc, &gds);
7801 if (r)
7802 return r;
7803 ctx->bc->cf_last->vpm = 1;
7804 return 0;
7805 }
7806
7807 static int tgsi_atomic_op(struct r600_shader_ctx *ctx)
7808 {
7809 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7810 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
7811 return tgsi_atomic_op_gds(ctx);
7812 return 0;
7813 }
7814
7815 static int tgsi_lrp(struct r600_shader_ctx *ctx)
7816 {
7817 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7818 struct r600_bytecode_alu alu;
7819 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7820 unsigned i, temp_regs[2];
7821 int r;
7822
7823 /* optimize if it's just an equal balance */
7824 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
7825 for (i = 0; i < lasti + 1; i++) {
7826 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7827 continue;
7828
7829 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7830 alu.op = ALU_OP2_ADD;
7831 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
7832 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7833 alu.omod = 3;
7834 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7835 alu.dst.chan = i;
7836 if (i == lasti) {
7837 alu.last = 1;
7838 }
7839 r = r600_bytecode_add_alu(ctx->bc, &alu);
7840 if (r)
7841 return r;
7842 }
7843 return 0;
7844 }
7845
7846 /* 1 - src0 */
7847 for (i = 0; i < lasti + 1; i++) {
7848 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7849 continue;
7850
7851 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7852 alu.op = ALU_OP2_ADD;
7853 alu.src[0].sel = V_SQ_ALU_SRC_1;
7854 alu.src[0].chan = 0;
7855 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
7856 r600_bytecode_src_toggle_neg(&alu.src[1]);
7857 alu.dst.sel = ctx->temp_reg;
7858 alu.dst.chan = i;
7859 if (i == lasti) {
7860 alu.last = 1;
7861 }
7862 alu.dst.write = 1;
7863 r = r600_bytecode_add_alu(ctx->bc, &alu);
7864 if (r)
7865 return r;
7866 }
7867
7868 /* (1 - src0) * src2 */
7869 for (i = 0; i < lasti + 1; i++) {
7870 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7871 continue;
7872
7873 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7874 alu.op = ALU_OP2_MUL;
7875 alu.src[0].sel = ctx->temp_reg;
7876 alu.src[0].chan = i;
7877 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7878 alu.dst.sel = ctx->temp_reg;
7879 alu.dst.chan = i;
7880 if (i == lasti) {
7881 alu.last = 1;
7882 }
7883 alu.dst.write = 1;
7884 r = r600_bytecode_add_alu(ctx->bc, &alu);
7885 if (r)
7886 return r;
7887 }
7888
7889 /* src0 * src1 + (1 - src0) * src2 */
7890 if (ctx->src[0].abs)
7891 temp_regs[0] = r600_get_temp(ctx);
7892 else
7893 temp_regs[0] = 0;
7894 if (ctx->src[1].abs)
7895 temp_regs[1] = r600_get_temp(ctx);
7896 else
7897 temp_regs[1] = 0;
7898
7899 for (i = 0; i < lasti + 1; i++) {
7900 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7901 continue;
7902
7903 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7904 alu.op = ALU_OP3_MULADD;
7905 alu.is_op3 = 1;
7906 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7907 if (r)
7908 return r;
7909 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
7910 if (r)
7911 return r;
7912 alu.src[2].sel = ctx->temp_reg;
7913 alu.src[2].chan = i;
7914
7915 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7916 alu.dst.chan = i;
7917 if (i == lasti) {
7918 alu.last = 1;
7919 }
7920 r = r600_bytecode_add_alu(ctx->bc, &alu);
7921 if (r)
7922 return r;
7923 }
7924 return 0;
7925 }
7926
7927 static int tgsi_cmp(struct r600_shader_ctx *ctx)
7928 {
7929 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7930 struct r600_bytecode_alu alu;
7931 int i, r, j;
7932 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7933 int temp_regs[3];
7934 unsigned op;
7935
7936 if (ctx->src[0].abs && ctx->src[0].neg) {
7937 op = ALU_OP3_CNDE;
7938 ctx->src[0].abs = 0;
7939 ctx->src[0].neg = 0;
7940 } else {
7941 op = ALU_OP3_CNDGE;
7942 }
7943
7944 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7945 temp_regs[j] = 0;
7946 if (ctx->src[j].abs)
7947 temp_regs[j] = r600_get_temp(ctx);
7948 }
7949
7950 for (i = 0; i < lasti + 1; i++) {
7951 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7952 continue;
7953
7954 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7955 alu.op = op;
7956 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7957 if (r)
7958 return r;
7959 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
7960 if (r)
7961 return r;
7962 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
7963 if (r)
7964 return r;
7965 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7966 alu.dst.chan = i;
7967 alu.dst.write = 1;
7968 alu.is_op3 = 1;
7969 if (i == lasti)
7970 alu.last = 1;
7971 r = r600_bytecode_add_alu(ctx->bc, &alu);
7972 if (r)
7973 return r;
7974 }
7975 return 0;
7976 }
7977
7978 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
7979 {
7980 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7981 struct r600_bytecode_alu alu;
7982 int i, r;
7983 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7984
7985 for (i = 0; i < lasti + 1; i++) {
7986 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7987 continue;
7988
7989 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7990 alu.op = ALU_OP3_CNDE_INT;
7991 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7992 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7993 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
7994 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7995 alu.dst.chan = i;
7996 alu.dst.write = 1;
7997 alu.is_op3 = 1;
7998 if (i == lasti)
7999 alu.last = 1;
8000 r = r600_bytecode_add_alu(ctx->bc, &alu);
8001 if (r)
8002 return r;
8003 }
8004 return 0;
8005 }
8006
8007 static int tgsi_exp(struct r600_shader_ctx *ctx)
8008 {
8009 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8010 struct r600_bytecode_alu alu;
8011 int r;
8012 unsigned i;
8013
8014 /* result.x = 2^floor(src); */
8015 if (inst->Dst[0].Register.WriteMask & 1) {
8016 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8017
8018 alu.op = ALU_OP1_FLOOR;
8019 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8020
8021 alu.dst.sel = ctx->temp_reg;
8022 alu.dst.chan = 0;
8023 alu.dst.write = 1;
8024 alu.last = 1;
8025 r = r600_bytecode_add_alu(ctx->bc, &alu);
8026 if (r)
8027 return r;
8028
8029 if (ctx->bc->chip_class == CAYMAN) {
8030 for (i = 0; i < 3; i++) {
8031 alu.op = ALU_OP1_EXP_IEEE;
8032 alu.src[0].sel = ctx->temp_reg;
8033 alu.src[0].chan = 0;
8034
8035 alu.dst.sel = ctx->temp_reg;
8036 alu.dst.chan = i;
8037 alu.dst.write = i == 0;
8038 alu.last = i == 2;
8039 r = r600_bytecode_add_alu(ctx->bc, &alu);
8040 if (r)
8041 return r;
8042 }
8043 } else {
8044 alu.op = ALU_OP1_EXP_IEEE;
8045 alu.src[0].sel = ctx->temp_reg;
8046 alu.src[0].chan = 0;
8047
8048 alu.dst.sel = ctx->temp_reg;
8049 alu.dst.chan = 0;
8050 alu.dst.write = 1;
8051 alu.last = 1;
8052 r = r600_bytecode_add_alu(ctx->bc, &alu);
8053 if (r)
8054 return r;
8055 }
8056 }
8057
8058 /* result.y = tmp - floor(tmp); */
8059 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8060 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8061
8062 alu.op = ALU_OP1_FRACT;
8063 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8064
8065 alu.dst.sel = ctx->temp_reg;
8066 #if 0
8067 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8068 if (r)
8069 return r;
8070 #endif
8071 alu.dst.write = 1;
8072 alu.dst.chan = 1;
8073
8074 alu.last = 1;
8075
8076 r = r600_bytecode_add_alu(ctx->bc, &alu);
8077 if (r)
8078 return r;
8079 }
8080
8081 /* result.z = RoughApprox2ToX(tmp);*/
8082 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
8083 if (ctx->bc->chip_class == CAYMAN) {
8084 for (i = 0; i < 3; i++) {
8085 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8086 alu.op = ALU_OP1_EXP_IEEE;
8087 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8088
8089 alu.dst.sel = ctx->temp_reg;
8090 alu.dst.chan = i;
8091 if (i == 2) {
8092 alu.dst.write = 1;
8093 alu.last = 1;
8094 }
8095
8096 r = r600_bytecode_add_alu(ctx->bc, &alu);
8097 if (r)
8098 return r;
8099 }
8100 } else {
8101 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8102 alu.op = ALU_OP1_EXP_IEEE;
8103 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8104
8105 alu.dst.sel = ctx->temp_reg;
8106 alu.dst.write = 1;
8107 alu.dst.chan = 2;
8108
8109 alu.last = 1;
8110
8111 r = r600_bytecode_add_alu(ctx->bc, &alu);
8112 if (r)
8113 return r;
8114 }
8115 }
8116
8117 /* result.w = 1.0;*/
8118 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
8119 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8120
8121 alu.op = ALU_OP1_MOV;
8122 alu.src[0].sel = V_SQ_ALU_SRC_1;
8123 alu.src[0].chan = 0;
8124
8125 alu.dst.sel = ctx->temp_reg;
8126 alu.dst.chan = 3;
8127 alu.dst.write = 1;
8128 alu.last = 1;
8129 r = r600_bytecode_add_alu(ctx->bc, &alu);
8130 if (r)
8131 return r;
8132 }
8133 return tgsi_helper_copy(ctx, inst);
8134 }
8135
8136 static int tgsi_log(struct r600_shader_ctx *ctx)
8137 {
8138 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8139 struct r600_bytecode_alu alu;
8140 int r;
8141 unsigned i;
8142
8143 /* result.x = floor(log2(|src|)); */
8144 if (inst->Dst[0].Register.WriteMask & 1) {
8145 if (ctx->bc->chip_class == CAYMAN) {
8146 for (i = 0; i < 3; i++) {
8147 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8148
8149 alu.op = ALU_OP1_LOG_IEEE;
8150 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8151 r600_bytecode_src_set_abs(&alu.src[0]);
8152
8153 alu.dst.sel = ctx->temp_reg;
8154 alu.dst.chan = i;
8155 if (i == 0)
8156 alu.dst.write = 1;
8157 if (i == 2)
8158 alu.last = 1;
8159 r = r600_bytecode_add_alu(ctx->bc, &alu);
8160 if (r)
8161 return r;
8162 }
8163
8164 } else {
8165 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8166
8167 alu.op = ALU_OP1_LOG_IEEE;
8168 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8169 r600_bytecode_src_set_abs(&alu.src[0]);
8170
8171 alu.dst.sel = ctx->temp_reg;
8172 alu.dst.chan = 0;
8173 alu.dst.write = 1;
8174 alu.last = 1;
8175 r = r600_bytecode_add_alu(ctx->bc, &alu);
8176 if (r)
8177 return r;
8178 }
8179
8180 alu.op = ALU_OP1_FLOOR;
8181 alu.src[0].sel = ctx->temp_reg;
8182 alu.src[0].chan = 0;
8183
8184 alu.dst.sel = ctx->temp_reg;
8185 alu.dst.chan = 0;
8186 alu.dst.write = 1;
8187 alu.last = 1;
8188
8189 r = r600_bytecode_add_alu(ctx->bc, &alu);
8190 if (r)
8191 return r;
8192 }
8193
8194 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
8195 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8196
8197 if (ctx->bc->chip_class == CAYMAN) {
8198 for (i = 0; i < 3; i++) {
8199 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8200
8201 alu.op = ALU_OP1_LOG_IEEE;
8202 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8203 r600_bytecode_src_set_abs(&alu.src[0]);
8204
8205 alu.dst.sel = ctx->temp_reg;
8206 alu.dst.chan = i;
8207 if (i == 1)
8208 alu.dst.write = 1;
8209 if (i == 2)
8210 alu.last = 1;
8211
8212 r = r600_bytecode_add_alu(ctx->bc, &alu);
8213 if (r)
8214 return r;
8215 }
8216 } else {
8217 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8218
8219 alu.op = ALU_OP1_LOG_IEEE;
8220 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8221 r600_bytecode_src_set_abs(&alu.src[0]);
8222
8223 alu.dst.sel = ctx->temp_reg;
8224 alu.dst.chan = 1;
8225 alu.dst.write = 1;
8226 alu.last = 1;
8227
8228 r = r600_bytecode_add_alu(ctx->bc, &alu);
8229 if (r)
8230 return r;
8231 }
8232
8233 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8234
8235 alu.op = ALU_OP1_FLOOR;
8236 alu.src[0].sel = ctx->temp_reg;
8237 alu.src[0].chan = 1;
8238
8239 alu.dst.sel = ctx->temp_reg;
8240 alu.dst.chan = 1;
8241 alu.dst.write = 1;
8242 alu.last = 1;
8243
8244 r = r600_bytecode_add_alu(ctx->bc, &alu);
8245 if (r)
8246 return r;
8247
8248 if (ctx->bc->chip_class == CAYMAN) {
8249 for (i = 0; i < 3; i++) {
8250 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8251 alu.op = ALU_OP1_EXP_IEEE;
8252 alu.src[0].sel = ctx->temp_reg;
8253 alu.src[0].chan = 1;
8254
8255 alu.dst.sel = ctx->temp_reg;
8256 alu.dst.chan = i;
8257 if (i == 1)
8258 alu.dst.write = 1;
8259 if (i == 2)
8260 alu.last = 1;
8261
8262 r = r600_bytecode_add_alu(ctx->bc, &alu);
8263 if (r)
8264 return r;
8265 }
8266 } else {
8267 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8268 alu.op = ALU_OP1_EXP_IEEE;
8269 alu.src[0].sel = ctx->temp_reg;
8270 alu.src[0].chan = 1;
8271
8272 alu.dst.sel = ctx->temp_reg;
8273 alu.dst.chan = 1;
8274 alu.dst.write = 1;
8275 alu.last = 1;
8276
8277 r = r600_bytecode_add_alu(ctx->bc, &alu);
8278 if (r)
8279 return r;
8280 }
8281
8282 if (ctx->bc->chip_class == CAYMAN) {
8283 for (i = 0; i < 3; i++) {
8284 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8285 alu.op = ALU_OP1_RECIP_IEEE;
8286 alu.src[0].sel = ctx->temp_reg;
8287 alu.src[0].chan = 1;
8288
8289 alu.dst.sel = ctx->temp_reg;
8290 alu.dst.chan = i;
8291 if (i == 1)
8292 alu.dst.write = 1;
8293 if (i == 2)
8294 alu.last = 1;
8295
8296 r = r600_bytecode_add_alu(ctx->bc, &alu);
8297 if (r)
8298 return r;
8299 }
8300 } else {
8301 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8302 alu.op = ALU_OP1_RECIP_IEEE;
8303 alu.src[0].sel = ctx->temp_reg;
8304 alu.src[0].chan = 1;
8305
8306 alu.dst.sel = ctx->temp_reg;
8307 alu.dst.chan = 1;
8308 alu.dst.write = 1;
8309 alu.last = 1;
8310
8311 r = r600_bytecode_add_alu(ctx->bc, &alu);
8312 if (r)
8313 return r;
8314 }
8315
8316 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8317
8318 alu.op = ALU_OP2_MUL;
8319
8320 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8321 r600_bytecode_src_set_abs(&alu.src[0]);
8322
8323 alu.src[1].sel = ctx->temp_reg;
8324 alu.src[1].chan = 1;
8325
8326 alu.dst.sel = ctx->temp_reg;
8327 alu.dst.chan = 1;
8328 alu.dst.write = 1;
8329 alu.last = 1;
8330
8331 r = r600_bytecode_add_alu(ctx->bc, &alu);
8332 if (r)
8333 return r;
8334 }
8335
8336 /* result.z = log2(|src|);*/
8337 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
8338 if (ctx->bc->chip_class == CAYMAN) {
8339 for (i = 0; i < 3; i++) {
8340 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8341
8342 alu.op = ALU_OP1_LOG_IEEE;
8343 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8344 r600_bytecode_src_set_abs(&alu.src[0]);
8345
8346 alu.dst.sel = ctx->temp_reg;
8347 if (i == 2)
8348 alu.dst.write = 1;
8349 alu.dst.chan = i;
8350 if (i == 2)
8351 alu.last = 1;
8352
8353 r = r600_bytecode_add_alu(ctx->bc, &alu);
8354 if (r)
8355 return r;
8356 }
8357 } else {
8358 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8359
8360 alu.op = ALU_OP1_LOG_IEEE;
8361 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8362 r600_bytecode_src_set_abs(&alu.src[0]);
8363
8364 alu.dst.sel = ctx->temp_reg;
8365 alu.dst.write = 1;
8366 alu.dst.chan = 2;
8367 alu.last = 1;
8368
8369 r = r600_bytecode_add_alu(ctx->bc, &alu);
8370 if (r)
8371 return r;
8372 }
8373 }
8374
8375 /* result.w = 1.0; */
8376 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
8377 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8378
8379 alu.op = ALU_OP1_MOV;
8380 alu.src[0].sel = V_SQ_ALU_SRC_1;
8381 alu.src[0].chan = 0;
8382
8383 alu.dst.sel = ctx->temp_reg;
8384 alu.dst.chan = 3;
8385 alu.dst.write = 1;
8386 alu.last = 1;
8387
8388 r = r600_bytecode_add_alu(ctx->bc, &alu);
8389 if (r)
8390 return r;
8391 }
8392
8393 return tgsi_helper_copy(ctx, inst);
8394 }
8395
8396 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
8397 {
8398 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8399 struct r600_bytecode_alu alu;
8400 int r;
8401 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8402 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
8403
8404 assert(inst->Dst[0].Register.Index < 3);
8405 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8406
8407 switch (inst->Instruction.Opcode) {
8408 case TGSI_OPCODE_ARL:
8409 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
8410 break;
8411 case TGSI_OPCODE_ARR:
8412 alu.op = ALU_OP1_FLT_TO_INT;
8413 break;
8414 case TGSI_OPCODE_UARL:
8415 alu.op = ALU_OP1_MOV;
8416 break;
8417 default:
8418 assert(0);
8419 return -1;
8420 }
8421
8422 for (i = 0; i <= lasti; ++i) {
8423 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8424 continue;
8425 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8426 alu.last = i == lasti;
8427 alu.dst.sel = reg;
8428 alu.dst.chan = i;
8429 alu.dst.write = 1;
8430 r = r600_bytecode_add_alu(ctx->bc, &alu);
8431 if (r)
8432 return r;
8433 }
8434
8435 if (inst->Dst[0].Register.Index > 0)
8436 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
8437 else
8438 ctx->bc->ar_loaded = 0;
8439
8440 return 0;
8441 }
8442 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
8443 {
8444 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8445 struct r600_bytecode_alu alu;
8446 int r;
8447 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8448
8449 switch (inst->Instruction.Opcode) {
8450 case TGSI_OPCODE_ARL:
8451 memset(&alu, 0, sizeof(alu));
8452 alu.op = ALU_OP1_FLOOR;
8453 alu.dst.sel = ctx->bc->ar_reg;
8454 alu.dst.write = 1;
8455 for (i = 0; i <= lasti; ++i) {
8456 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8457 alu.dst.chan = i;
8458 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8459 alu.last = i == lasti;
8460 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8461 return r;
8462 }
8463 }
8464
8465 memset(&alu, 0, sizeof(alu));
8466 alu.op = ALU_OP1_FLT_TO_INT;
8467 alu.src[0].sel = ctx->bc->ar_reg;
8468 alu.dst.sel = ctx->bc->ar_reg;
8469 alu.dst.write = 1;
8470 /* FLT_TO_INT is trans-only on r600/r700 */
8471 alu.last = TRUE;
8472 for (i = 0; i <= lasti; ++i) {
8473 alu.dst.chan = i;
8474 alu.src[0].chan = i;
8475 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8476 return r;
8477 }
8478 break;
8479 case TGSI_OPCODE_ARR:
8480 memset(&alu, 0, sizeof(alu));
8481 alu.op = ALU_OP1_FLT_TO_INT;
8482 alu.dst.sel = ctx->bc->ar_reg;
8483 alu.dst.write = 1;
8484 /* FLT_TO_INT is trans-only on r600/r700 */
8485 alu.last = TRUE;
8486 for (i = 0; i <= lasti; ++i) {
8487 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8488 alu.dst.chan = i;
8489 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8490 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8491 return r;
8492 }
8493 }
8494 break;
8495 case TGSI_OPCODE_UARL:
8496 memset(&alu, 0, sizeof(alu));
8497 alu.op = ALU_OP1_MOV;
8498 alu.dst.sel = ctx->bc->ar_reg;
8499 alu.dst.write = 1;
8500 for (i = 0; i <= lasti; ++i) {
8501 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8502 alu.dst.chan = i;
8503 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8504 alu.last = i == lasti;
8505 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8506 return r;
8507 }
8508 }
8509 break;
8510 default:
8511 assert(0);
8512 return -1;
8513 }
8514
8515 ctx->bc->ar_loaded = 0;
8516 return 0;
8517 }
8518
8519 static int tgsi_opdst(struct r600_shader_ctx *ctx)
8520 {
8521 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8522 struct r600_bytecode_alu alu;
8523 int i, r = 0;
8524
8525 for (i = 0; i < 4; i++) {
8526 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8527
8528 alu.op = ALU_OP2_MUL;
8529 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8530
8531 if (i == 0 || i == 3) {
8532 alu.src[0].sel = V_SQ_ALU_SRC_1;
8533 } else {
8534 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8535 }
8536
8537 if (i == 0 || i == 2) {
8538 alu.src[1].sel = V_SQ_ALU_SRC_1;
8539 } else {
8540 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8541 }
8542 if (i == 3)
8543 alu.last = 1;
8544 r = r600_bytecode_add_alu(ctx->bc, &alu);
8545 if (r)
8546 return r;
8547 }
8548 return 0;
8549 }
8550
8551 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
8552 {
8553 struct r600_bytecode_alu alu;
8554 int r;
8555
8556 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8557 alu.op = opcode;
8558 alu.execute_mask = 1;
8559 alu.update_pred = 1;
8560
8561 alu.dst.sel = ctx->temp_reg;
8562 alu.dst.write = 1;
8563 alu.dst.chan = 0;
8564
8565 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8566 alu.src[1].sel = V_SQ_ALU_SRC_0;
8567 alu.src[1].chan = 0;
8568
8569 alu.last = 1;
8570
8571 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
8572 if (r)
8573 return r;
8574 return 0;
8575 }
8576
8577 static int pops(struct r600_shader_ctx *ctx, int pops)
8578 {
8579 unsigned force_pop = ctx->bc->force_add_cf;
8580
8581 if (!force_pop) {
8582 int alu_pop = 3;
8583 if (ctx->bc->cf_last) {
8584 if (ctx->bc->cf_last->op == CF_OP_ALU)
8585 alu_pop = 0;
8586 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
8587 alu_pop = 1;
8588 }
8589 alu_pop += pops;
8590 if (alu_pop == 1) {
8591 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
8592 ctx->bc->force_add_cf = 1;
8593 } else if (alu_pop == 2) {
8594 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
8595 ctx->bc->force_add_cf = 1;
8596 } else {
8597 force_pop = 1;
8598 }
8599 }
8600
8601 if (force_pop) {
8602 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
8603 ctx->bc->cf_last->pop_count = pops;
8604 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8605 }
8606
8607 return 0;
8608 }
8609
8610 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
8611 unsigned reason)
8612 {
8613 struct r600_stack_info *stack = &ctx->bc->stack;
8614 unsigned elements, entries;
8615
8616 unsigned entry_size = stack->entry_size;
8617
8618 elements = (stack->loop + stack->push_wqm ) * entry_size;
8619 elements += stack->push;
8620
8621 switch (ctx->bc->chip_class) {
8622 case R600:
8623 case R700:
8624 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
8625 * the stack must be reserved to hold the current active/continue
8626 * masks */
8627 if (reason == FC_PUSH_VPM) {
8628 elements += 2;
8629 }
8630 break;
8631
8632 case CAYMAN:
8633 /* r9xx: any stack operation on empty stack consumes 2 additional
8634 * elements */
8635 elements += 2;
8636
8637 /* fallthrough */
8638 /* FIXME: do the two elements added above cover the cases for the
8639 * r8xx+ below? */
8640
8641 case EVERGREEN:
8642 /* r8xx+: 2 extra elements are not always required, but one extra
8643 * element must be added for each of the following cases:
8644 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
8645 * stack usage.
8646 * (Currently we don't use ALU_ELSE_AFTER.)
8647 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
8648 * PUSH instruction executed.
8649 *
8650 * NOTE: it seems we also need to reserve additional element in some
8651 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
8652 * then STACK_SIZE should be 2 instead of 1 */
8653 if (reason == FC_PUSH_VPM) {
8654 elements += 1;
8655 }
8656 break;
8657
8658 default:
8659 assert(0);
8660 break;
8661 }
8662
8663 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
8664 * for all chips, so we use 4 in the final formula, not the real entry_size
8665 * for the chip */
8666 entry_size = 4;
8667
8668 entries = (elements + (entry_size - 1)) / entry_size;
8669
8670 if (entries > stack->max_entries)
8671 stack->max_entries = entries;
8672 }
8673
8674 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
8675 {
8676 switch(reason) {
8677 case FC_PUSH_VPM:
8678 --ctx->bc->stack.push;
8679 assert(ctx->bc->stack.push >= 0);
8680 break;
8681 case FC_PUSH_WQM:
8682 --ctx->bc->stack.push_wqm;
8683 assert(ctx->bc->stack.push_wqm >= 0);
8684 break;
8685 case FC_LOOP:
8686 --ctx->bc->stack.loop;
8687 assert(ctx->bc->stack.loop >= 0);
8688 break;
8689 default:
8690 assert(0);
8691 break;
8692 }
8693 }
8694
8695 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
8696 {
8697 switch (reason) {
8698 case FC_PUSH_VPM:
8699 ++ctx->bc->stack.push;
8700 break;
8701 case FC_PUSH_WQM:
8702 ++ctx->bc->stack.push_wqm;
8703 case FC_LOOP:
8704 ++ctx->bc->stack.loop;
8705 break;
8706 default:
8707 assert(0);
8708 }
8709
8710 callstack_update_max_depth(ctx, reason);
8711 }
8712
8713 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
8714 {
8715 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
8716
8717 sp->mid = realloc((void *)sp->mid,
8718 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
8719 sp->mid[sp->num_mid] = ctx->bc->cf_last;
8720 sp->num_mid++;
8721 }
8722
8723 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
8724 {
8725 assert(ctx->bc->fc_sp < ARRAY_SIZE(ctx->bc->fc_stack));
8726 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
8727 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
8728 ctx->bc->fc_sp++;
8729 }
8730
8731 static void fc_poplevel(struct r600_shader_ctx *ctx)
8732 {
8733 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp - 1];
8734 free(sp->mid);
8735 sp->mid = NULL;
8736 sp->num_mid = 0;
8737 sp->start = NULL;
8738 sp->type = 0;
8739 ctx->bc->fc_sp--;
8740 }
8741
8742 #if 0
8743 static int emit_return(struct r600_shader_ctx *ctx)
8744 {
8745 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
8746 return 0;
8747 }
8748
8749 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
8750 {
8751
8752 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
8753 ctx->bc->cf_last->pop_count = pops;
8754 /* XXX work out offset */
8755 return 0;
8756 }
8757
8758 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
8759 {
8760 return 0;
8761 }
8762
8763 static void emit_testflag(struct r600_shader_ctx *ctx)
8764 {
8765
8766 }
8767
8768 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
8769 {
8770 emit_testflag(ctx);
8771 emit_jump_to_offset(ctx, 1, 4);
8772 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
8773 pops(ctx, ifidx + 1);
8774 emit_return(ctx);
8775 }
8776
8777 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
8778 {
8779 emit_testflag(ctx);
8780
8781 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8782 ctx->bc->cf_last->pop_count = 1;
8783
8784 fc_set_mid(ctx, fc_sp);
8785
8786 pops(ctx, 1);
8787 }
8788 #endif
8789
8790 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
8791 {
8792 int alu_type = CF_OP_ALU_PUSH_BEFORE;
8793
8794 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
8795 * LOOP_STARTxxx for nested loops may put the branch stack into a state
8796 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
8797 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
8798 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
8799 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
8800 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8801 alu_type = CF_OP_ALU;
8802 }
8803
8804 emit_logic_pred(ctx, opcode, alu_type);
8805
8806 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
8807
8808 fc_pushlevel(ctx, FC_IF);
8809
8810 callstack_push(ctx, FC_PUSH_VPM);
8811 return 0;
8812 }
8813
8814 static int tgsi_if(struct r600_shader_ctx *ctx)
8815 {
8816 return emit_if(ctx, ALU_OP2_PRED_SETNE);
8817 }
8818
8819 static int tgsi_uif(struct r600_shader_ctx *ctx)
8820 {
8821 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
8822 }
8823
8824 static int tgsi_else(struct r600_shader_ctx *ctx)
8825 {
8826 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
8827 ctx->bc->cf_last->pop_count = 1;
8828
8829 fc_set_mid(ctx, ctx->bc->fc_sp - 1);
8830 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id;
8831 return 0;
8832 }
8833
8834 static int tgsi_endif(struct r600_shader_ctx *ctx)
8835 {
8836 pops(ctx, 1);
8837 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_IF) {
8838 R600_ERR("if/endif unbalanced in shader\n");
8839 return -1;
8840 }
8841
8842 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid == NULL) {
8843 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
8844 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->pop_count = 1;
8845 } else {
8846 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
8847 }
8848 fc_poplevel(ctx);
8849
8850 callstack_pop(ctx, FC_PUSH_VPM);
8851 return 0;
8852 }
8853
8854 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
8855 {
8856 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
8857 * limited to 4096 iterations, like the other LOOP_* instructions. */
8858 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
8859
8860 fc_pushlevel(ctx, FC_LOOP);
8861
8862 /* check stack depth */
8863 callstack_push(ctx, FC_LOOP);
8864 return 0;
8865 }
8866
8867 static int tgsi_endloop(struct r600_shader_ctx *ctx)
8868 {
8869 unsigned i;
8870
8871 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
8872
8873 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_LOOP) {
8874 R600_ERR("loop/endloop in shader code are not paired.\n");
8875 return -EINVAL;
8876 }
8877
8878 /* fixup loop pointers - from r600isa
8879 LOOP END points to CF after LOOP START,
8880 LOOP START point to CF after LOOP END
8881 BRK/CONT point to LOOP END CF
8882 */
8883 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->id + 2;
8884
8885 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
8886
8887 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp - 1].num_mid; i++) {
8888 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[i]->cf_addr = ctx->bc->cf_last->id;
8889 }
8890 /* XXX add LOOPRET support */
8891 fc_poplevel(ctx);
8892 callstack_pop(ctx, FC_LOOP);
8893 return 0;
8894 }
8895
8896 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
8897 {
8898 unsigned int fscp;
8899
8900 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
8901 {
8902 if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
8903 break;
8904 }
8905
8906 if (fscp == 0) {
8907 R600_ERR("Break not inside loop/endloop pair\n");
8908 return -EINVAL;
8909 }
8910
8911 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8912
8913 fc_set_mid(ctx, fscp - 1);
8914
8915 return 0;
8916 }
8917
8918 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
8919 {
8920 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8921 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
8922 int r;
8923
8924 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8925 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
8926
8927 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8928 if (!r) {
8929 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
8930 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8931 return emit_inc_ring_offset(ctx, stream, TRUE);
8932 }
8933 return r;
8934 }
8935
8936 static int tgsi_umad(struct r600_shader_ctx *ctx)
8937 {
8938 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8939 struct r600_bytecode_alu alu;
8940 int i, j, k, r;
8941 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8942
8943 /* src0 * src1 */
8944 for (i = 0; i < lasti + 1; i++) {
8945 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8946 continue;
8947
8948 if (ctx->bc->chip_class == CAYMAN) {
8949 for (j = 0 ; j < 4; j++) {
8950 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8951
8952 alu.op = ALU_OP2_MULLO_UINT;
8953 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
8954 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
8955 }
8956 alu.dst.chan = j;
8957 alu.dst.sel = ctx->temp_reg;
8958 alu.dst.write = (j == i);
8959 if (j == 3)
8960 alu.last = 1;
8961 r = r600_bytecode_add_alu(ctx->bc, &alu);
8962 if (r)
8963 return r;
8964 }
8965 } else {
8966 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8967
8968 alu.dst.chan = i;
8969 alu.dst.sel = ctx->temp_reg;
8970 alu.dst.write = 1;
8971
8972 alu.op = ALU_OP2_MULLO_UINT;
8973 for (j = 0; j < 2; j++) {
8974 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
8975 }
8976
8977 alu.last = 1;
8978 r = r600_bytecode_add_alu(ctx->bc, &alu);
8979 if (r)
8980 return r;
8981 }
8982 }
8983
8984
8985 for (i = 0; i < lasti + 1; i++) {
8986 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8987 continue;
8988
8989 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8990 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8991
8992 alu.op = ALU_OP2_ADD_INT;
8993
8994 alu.src[0].sel = ctx->temp_reg;
8995 alu.src[0].chan = i;
8996
8997 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8998 if (i == lasti) {
8999 alu.last = 1;
9000 }
9001 r = r600_bytecode_add_alu(ctx->bc, &alu);
9002 if (r)
9003 return r;
9004 }
9005 return 0;
9006 }
9007
9008 static int tgsi_pk2h(struct r600_shader_ctx *ctx)
9009 {
9010 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9011 struct r600_bytecode_alu alu;
9012 int r, i;
9013 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9014
9015 /* temp.xy = f32_to_f16(src) */
9016 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9017 alu.op = ALU_OP1_FLT32_TO_FLT16;
9018 alu.dst.chan = 0;
9019 alu.dst.sel = ctx->temp_reg;
9020 alu.dst.write = 1;
9021 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9022 r = r600_bytecode_add_alu(ctx->bc, &alu);
9023 if (r)
9024 return r;
9025 alu.dst.chan = 1;
9026 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
9027 alu.last = 1;
9028 r = r600_bytecode_add_alu(ctx->bc, &alu);
9029 if (r)
9030 return r;
9031
9032 /* dst.x = temp.y * 0x10000 + temp.x */
9033 for (i = 0; i < lasti + 1; i++) {
9034 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9035 continue;
9036
9037 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9038 alu.op = ALU_OP3_MULADD_UINT24;
9039 alu.is_op3 = 1;
9040 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9041 alu.last = i == lasti;
9042 alu.src[0].sel = ctx->temp_reg;
9043 alu.src[0].chan = 1;
9044 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9045 alu.src[1].value = 0x10000;
9046 alu.src[2].sel = ctx->temp_reg;
9047 alu.src[2].chan = 0;
9048 r = r600_bytecode_add_alu(ctx->bc, &alu);
9049 if (r)
9050 return r;
9051 }
9052
9053 return 0;
9054 }
9055
9056 static int tgsi_up2h(struct r600_shader_ctx *ctx)
9057 {
9058 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9059 struct r600_bytecode_alu alu;
9060 int r, i;
9061 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9062
9063 /* temp.x = src.x */
9064 /* note: no need to mask out the high bits */
9065 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9066 alu.op = ALU_OP1_MOV;
9067 alu.dst.chan = 0;
9068 alu.dst.sel = ctx->temp_reg;
9069 alu.dst.write = 1;
9070 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9071 r = r600_bytecode_add_alu(ctx->bc, &alu);
9072 if (r)
9073 return r;
9074
9075 /* temp.y = src.x >> 16 */
9076 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9077 alu.op = ALU_OP2_LSHR_INT;
9078 alu.dst.chan = 1;
9079 alu.dst.sel = ctx->temp_reg;
9080 alu.dst.write = 1;
9081 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9082 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9083 alu.src[1].value = 16;
9084 alu.last = 1;
9085 r = r600_bytecode_add_alu(ctx->bc, &alu);
9086 if (r)
9087 return r;
9088
9089 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
9090 for (i = 0; i < lasti + 1; i++) {
9091 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9092 continue;
9093 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9094 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9095 alu.op = ALU_OP1_FLT16_TO_FLT32;
9096 alu.src[0].sel = ctx->temp_reg;
9097 alu.src[0].chan = i % 2;
9098 alu.last = i == lasti;
9099 r = r600_bytecode_add_alu(ctx->bc, &alu);
9100 if (r)
9101 return r;
9102 }
9103
9104 return 0;
9105 }
9106
9107 static int tgsi_bfe(struct r600_shader_ctx *ctx)
9108 {
9109 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9110 struct r600_bytecode_alu alu;
9111 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9112 int r, i;
9113
9114 r = tgsi_op3(ctx);
9115 if (r)
9116 return r;
9117
9118 for (i = 0; i < lasti + 1; i++) {
9119 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9120 alu.op = ALU_OP2_SETGE_INT;
9121 r600_bytecode_src(&alu.src[0], &ctx->src[2], i);
9122 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9123 alu.src[1].value = 32;
9124 alu.dst.sel = ctx->temp_reg;
9125 alu.dst.chan = i;
9126 alu.dst.write = 1;
9127 if (i == lasti)
9128 alu.last = 1;
9129 r = r600_bytecode_add_alu(ctx->bc, &alu);
9130 if (r)
9131 return r;
9132 }
9133
9134 for (i = 0; i < lasti + 1; i++) {
9135 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9136 alu.op = ALU_OP3_CNDE_INT;
9137 alu.is_op3 = 1;
9138 alu.src[0].sel = ctx->temp_reg;
9139 alu.src[1].chan = i;
9140
9141 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9142 alu.src[1].sel = alu.dst.sel;
9143 alu.src[1].chan = i;
9144 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
9145 alu.dst.write = 1;
9146 if (i == lasti)
9147 alu.last = 1;
9148 r = r600_bytecode_add_alu(ctx->bc, &alu);
9149 if (r)
9150 return r;
9151 }
9152
9153 return 0;
9154 }
9155
9156 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
9157 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
9158 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9159 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9160
9161 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
9162
9163 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
9164 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9165 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9166 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9167 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9168 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9169 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9170 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9171 /* MIN_DX10 returns non-nan result if one src is NaN, MIN returns NaN */
9172 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
9173 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
9174 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9175 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9176 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9177 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9178 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
9179 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9180 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9181 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9182 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9183 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9184 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9185 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9186 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9187 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9188 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9189 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9190 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9191 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9192 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9193 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9194 [35] = { ALU_OP0_NOP, tgsi_unsupported},
9195 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9196 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9197 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9198 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9199 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
9200 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9201 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9202 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9203 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9204 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9205 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9206 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9207 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9208 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9209 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9210 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9211 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9212 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9213 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9214 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9215 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9216 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9217 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9218 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9219 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9220 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
9221 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9222 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9223 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9224 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9225 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9226 [67] = { ALU_OP0_NOP, tgsi_unsupported},
9227 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9228 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9229 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9230 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9231 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9232 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9233 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9234 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9235 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9236 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9237 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9238 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9239 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9240 [81] = { ALU_OP0_NOP, tgsi_unsupported},
9241 [82] = { ALU_OP0_NOP, tgsi_unsupported},
9242 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9243 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9244 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9245 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9246 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
9247 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9248 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9249 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9250 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9251 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9252 [93] = { ALU_OP0_NOP, tgsi_unsupported},
9253 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9254 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9255 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9256 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9257 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9258 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9259 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9260 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9261 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9262 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9263 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9264 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9265 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9266 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9267 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9268 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9269 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9270 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9271 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9272 [113] = { ALU_OP0_NOP, tgsi_unsupported},
9273 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9274 [115] = { ALU_OP0_NOP, tgsi_unsupported},
9275 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9276 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9277 [TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
9278 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
9279 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9280 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9281 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9282 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9283 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9284 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
9285 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9286 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
9287 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9288 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9289 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9290 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9291 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9292 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9293 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9294 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9295 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9296 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9297 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
9298 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9299 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
9300 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9301 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9302 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9303 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9304 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9305 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9306 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9307 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9308 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9309 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9310 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9311 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9312 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9313 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9314 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9315 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9316 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
9317 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9318 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9319 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9320 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9321 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9322 [163] = { ALU_OP0_NOP, tgsi_unsupported},
9323 [164] = { ALU_OP0_NOP, tgsi_unsupported},
9324 [165] = { ALU_OP0_NOP, tgsi_unsupported},
9325 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
9326 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9327 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9328 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9329 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9330 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9331 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9332 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9333 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9334 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9335 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9336 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9337 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9338 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9339 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9340 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9341 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
9342 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
9343 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
9344 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
9345 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
9346 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
9347 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
9348 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
9349 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
9350 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
9351 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
9352 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
9353 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
9354 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9355 };
9356
9357 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
9358 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9359 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9360 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9361 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
9362 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
9363 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9364 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9365 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9366 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9367 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9368 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9369 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9370 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
9371 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
9372 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9373 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9374 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9375 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9376 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
9377 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9378 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9379 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9380 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9381 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9382 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9383 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9384 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9385 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9386 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9387 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9388 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9389 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9390 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9391 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9392 [35] = { ALU_OP0_NOP, tgsi_unsupported},
9393 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9394 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9395 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9396 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9397 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
9398 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9399 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9400 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9401 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9402 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9403 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9404 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9405 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9406 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9407 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9408 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9409 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9410 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9411 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9412 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
9413 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9414 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9415 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9416 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9417 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9418 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9419 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9420 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9421 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9422 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9423 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9424 [67] = { ALU_OP0_NOP, tgsi_unsupported},
9425 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9426 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9427 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9428 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9429 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9430 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9431 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9432 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9433 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9434 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9435 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9436 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9437 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9438 [82] = { ALU_OP0_NOP, tgsi_unsupported},
9439 [83] = { ALU_OP0_NOP, tgsi_unsupported},
9440 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9441 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9442 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9443 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9444 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9445 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9446 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9447 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9448 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9449 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9450 [93] = { ALU_OP0_NOP, tgsi_unsupported},
9451 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9452 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9453 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9454 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9455 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9456 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9457 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9458 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9459 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9460 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9461 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9462 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9463 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9464 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9465 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9466 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9467 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9468 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9469 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9470 [113] = { ALU_OP0_NOP, tgsi_unsupported},
9471 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9472 [115] = { ALU_OP0_NOP, tgsi_unsupported},
9473 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9474 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9475 /* Refer below for TGSI_OPCODE_DFMA */
9476 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
9477 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9478 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9479 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9480 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9481 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9482 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9483 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9484 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
9485 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9486 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9487 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9488 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9489 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9490 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9491 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9492 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9493 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9494 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9495 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9496 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9497 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9498 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9499 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9500 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9501 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9502 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9503 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9504 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9505 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9506 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9507 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9508 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9509 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9510 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9511 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9512 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9513 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9514 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9515 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9516 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9517 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9518 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
9519 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9520 [163] = { ALU_OP0_NOP, tgsi_unsupported},
9521 [164] = { ALU_OP0_NOP, tgsi_unsupported},
9522 [165] = { ALU_OP0_NOP, tgsi_unsupported},
9523 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9524 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
9525 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
9526 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
9527 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
9528 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
9529 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
9530 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
9531 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
9532 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
9533 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
9534 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9535 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9536 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9537 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9538 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9539 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9540 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9541 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
9542 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
9543 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9544 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9545 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9546 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9547 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9548 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9549 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9550 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9551 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9552 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9553 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9554 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9555 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9556 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9557 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9558 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
9559 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9560 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9561 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9562 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9563 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9564 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9565 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9566 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9567 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9568 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
9569 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9570 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9571 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9572 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9573 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9574 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9575 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9576 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9577 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9578 };
9579
9580 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
9581 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9582 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9583 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9584 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
9585 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
9586 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9587 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9588 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9589 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9590 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9591 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9592 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9593 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
9594 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
9595 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9596 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9597 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9598 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9599 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
9600 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
9601 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9602 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9603 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9604 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9605 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9606 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9607 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9608 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
9609 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
9610 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
9611 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9612 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9613 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9614 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9615 [35] = { ALU_OP0_NOP, tgsi_unsupported},
9616 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
9617 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9618 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9619 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9620 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
9621 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9622 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9623 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9624 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9625 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9626 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9627 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9628 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
9629 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9630 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9631 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9632 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9633 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9634 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9635 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
9636 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9637 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9638 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9639 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9640 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9641 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9642 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9643 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9644 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9645 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9646 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9647 [67] = { ALU_OP0_NOP, tgsi_unsupported},
9648 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9649 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9650 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9651 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9652 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9653 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9654 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9655 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9656 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9657 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9658 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9659 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9660 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9661 [82] = { ALU_OP0_NOP, tgsi_unsupported},
9662 [83] = { ALU_OP0_NOP, tgsi_unsupported},
9663 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9664 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
9665 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9666 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9667 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9668 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9669 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9670 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9671 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9672 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9673 [93] = { ALU_OP0_NOP, tgsi_unsupported},
9674 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9675 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9676 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9677 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9678 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9679 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9680 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9681 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9682 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9683 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9684 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9685 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9686 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9687 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9688 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9689 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9690 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9691 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9692 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9693 [113] = { ALU_OP0_NOP, tgsi_unsupported},
9694 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9695 [115] = { ALU_OP0_NOP, tgsi_unsupported},
9696 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9697 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9698 /* Refer below for TGSI_OPCODE_DFMA */
9699 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
9700 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9701 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9702 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9703 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9704 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9705 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9706 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9707 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
9708 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
9709 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9710 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9711 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9712 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9713 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9714 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9715 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
9716 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9717 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9718 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9719 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9720 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9721 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9722 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9723 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9724 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9725 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9726 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9727 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9728 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9729 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9730 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9731 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9732 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9733 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9734 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9735 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9736 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9737 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9738 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9739 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9740 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9741 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
9742 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9743 [163] = { ALU_OP0_NOP, tgsi_unsupported},
9744 [164] = { ALU_OP0_NOP, tgsi_unsupported},
9745 [165] = { ALU_OP0_NOP, tgsi_unsupported},
9746 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9747 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
9748 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
9749 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
9750 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
9751 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
9752 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
9753 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
9754 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
9755 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
9756 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
9757 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9758 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9759 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9760 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
9761 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
9762 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9763 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9764 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
9765 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
9766 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9767 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9768 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9769 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9770 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9771 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9772 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9773 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9774 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9775 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9776 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9777 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9778 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9779 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9780 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9781 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
9782 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9783 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9784 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9785 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9786 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9787 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9788 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9789 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9790 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9791 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
9792 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9793 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9794 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9795 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9796 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9797 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9798 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9799 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9800 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9801 };