projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600: Take ALU_EXTENDED into account when evaluating jump offsets
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm;
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
193 use_sb &= (shader->shader.processor_type != PIPE_SHADER_COMPUTE);
194
195 /* disable SB for shaders using doubles */
196 use_sb &= !shader->shader.uses_doubles;
197
198 use_sb &= !shader->shader.uses_atomics;
199 use_sb &= !shader->shader.uses_images;
200 use_sb &= !shader->shader.uses_helper_invocation;
201
202 /* Check if the bytecode has already been built. */
203 if (!shader->shader.bc.bytecode) {
204 r = r600_bytecode_build(&shader->shader.bc);
205 if (r) {
206 R600_ERR("building bytecode failed !\n");
207 goto error;
208 }
209 }
210
211 sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
212 if (dump && !sb_disasm) {
213 fprintf(stderr, "--------------------------------------------------------------\n");
214 r600_bytecode_disasm(&shader->shader.bc);
215 fprintf(stderr, "______________________________________________________________\n");
216 } else if ((dump && sb_disasm) || use_sb) {
217 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
218 dump, use_sb);
219 if (r) {
220 R600_ERR("r600_sb_bytecode_process failed !\n");
221 goto error;
222 }
223 }
224
225 if (shader->gs_copy_shader) {
226 if (dump) {
227 // dump copy shader
228 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
229 &shader->gs_copy_shader->shader, dump, 0);
230 if (r)
231 goto error;
232 }
233
234 if ((r = store_shader(ctx, shader->gs_copy_shader)))
235 goto error;
236 }
237
238 /* Store the shader in a buffer. */
239 if ((r = store_shader(ctx, shader)))
240 goto error;
241
242 /* Build state. */
243 switch (shader->shader.processor_type) {
244 case PIPE_SHADER_TESS_CTRL:
245 evergreen_update_hs_state(ctx, shader);
246 break;
247 case PIPE_SHADER_TESS_EVAL:
248 if (key.tes.as_es)
249 evergreen_update_es_state(ctx, shader);
250 else
251 evergreen_update_vs_state(ctx, shader);
252 break;
253 case PIPE_SHADER_GEOMETRY:
254 if (rctx->b.chip_class >= EVERGREEN) {
255 evergreen_update_gs_state(ctx, shader);
256 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
257 } else {
258 r600_update_gs_state(ctx, shader);
259 r600_update_vs_state(ctx, shader->gs_copy_shader);
260 }
261 break;
262 case PIPE_SHADER_VERTEX:
263 export_shader = key.vs.as_es;
264 if (rctx->b.chip_class >= EVERGREEN) {
265 if (key.vs.as_ls)
266 evergreen_update_ls_state(ctx, shader);
267 else if (key.vs.as_es)
268 evergreen_update_es_state(ctx, shader);
269 else
270 evergreen_update_vs_state(ctx, shader);
271 } else {
272 if (export_shader)
273 r600_update_es_state(ctx, shader);
274 else
275 r600_update_vs_state(ctx, shader);
276 }
277 break;
278 case PIPE_SHADER_FRAGMENT:
279 if (rctx->b.chip_class >= EVERGREEN) {
280 evergreen_update_ps_state(ctx, shader);
281 } else {
282 r600_update_ps_state(ctx, shader);
283 }
284 break;
285 case PIPE_SHADER_COMPUTE:
286 evergreen_update_ls_state(ctx, shader);
287 break;
288 default:
289 r = -EINVAL;
290 goto error;
291 }
292 return 0;
293
294 error:
295 r600_pipe_shader_destroy(ctx, shader);
296 return r;
297 }
298
299 void r600_pipe_shader_destroy(struct pipe_context *ctx UNUSED, struct r600_pipe_shader *shader)
300 {
301 r600_resource_reference(&shader->bo, NULL);
302 r600_bytecode_clear(&shader->shader.bc);
303 r600_release_command_buffer(&shader->command_buffer);
304 }
305
306 /*
307 * tgsi -> r600 shader
308 */
309 struct r600_shader_tgsi_instruction;
310
311 struct r600_shader_src {
312 unsigned sel;
313 unsigned swizzle[4];
314 unsigned neg;
315 unsigned abs;
316 unsigned rel;
317 unsigned kc_bank;
318 boolean kc_rel; /* true if cache bank is indexed */
319 uint32_t value[4];
320 };
321
322 struct eg_interp {
323 boolean enabled;
324 unsigned ij_index;
325 };
326
327 struct r600_shader_ctx {
328 struct tgsi_shader_info info;
329 struct tgsi_array_info *array_infos;
330 /* flag for each tgsi temp array if its been spilled or not */
331 bool *spilled_arrays;
332 struct tgsi_parse_context parse;
333 const struct tgsi_token *tokens;
334 unsigned type;
335 unsigned file_offset[TGSI_FILE_COUNT];
336 unsigned temp_reg;
337 const struct r600_shader_tgsi_instruction *inst_info;
338 struct r600_bytecode *bc;
339 struct r600_shader *shader;
340 struct r600_shader_src src[4];
341 uint32_t *literals;
342 uint32_t nliterals;
343 uint32_t max_driver_temp_used;
344 /* needed for evergreen interpolation */
345 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
346 /* evergreen/cayman also store sample mask in face register */
347 int face_gpr;
348 /* sample id is .w component stored in fixed point position register */
349 int fixed_pt_position_gpr;
350 int colors_used;
351 boolean clip_vertex_write;
352 unsigned cv_output;
353 unsigned edgeflag_output;
354 int helper_invoc_reg;
355 int cs_block_size_reg;
356 int cs_grid_size_reg;
357 bool cs_block_size_loaded, cs_grid_size_loaded;
358 int fragcoord_input;
359 int next_ring_offset;
360 int gs_out_ring_offset;
361 int gs_next_vertex;
362 struct r600_shader *gs_for_vs;
363 int gs_export_gpr_tregs[4];
364 int gs_rotated_input[2];
365 const struct pipe_stream_output_info *gs_stream_output_info;
366 unsigned enabled_stream_buffers_mask;
367 unsigned tess_input_info; /* temp with tess input offsets */
368 unsigned tess_output_info; /* temp with tess input offsets */
369 unsigned thread_id_gpr; /* temp with thread id calculated for images */
370 bool thread_id_gpr_loaded;
371 };
372
373 struct r600_shader_tgsi_instruction {
374 unsigned op;
375 int (*process)(struct r600_shader_ctx *ctx);
376 };
377
378 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
379 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
380 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
381 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
382 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
383 static int tgsi_else(struct r600_shader_ctx *ctx);
384 static int tgsi_endif(struct r600_shader_ctx *ctx);
385 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
386 static int tgsi_endloop(struct r600_shader_ctx *ctx);
387 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
388 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
389 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
390 unsigned int dst_reg);
391 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
392 const struct r600_shader_src *shader_src,
393 unsigned chan);
394 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
395 unsigned dst_reg, unsigned mask);
396
397 static int tgsi_last_instruction(unsigned writemask)
398 {
399 int i, lasti = 0;
400
401 for (i = 0; i < 4; i++) {
402 if (writemask & (1 << i)) {
403 lasti = i;
404 }
405 }
406 return lasti;
407 }
408
409 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
410 {
411 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
412 unsigned j;
413
414 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
415 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
416 return -EINVAL;
417 }
418 #if 0
419 if (i->Instruction.Label) {
420 R600_ERR("label unsupported\n");
421 return -EINVAL;
422 }
423 #endif
424 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
425 if (i->Src[j].Register.Dimension) {
426 switch (i->Src[j].Register.File) {
427 case TGSI_FILE_CONSTANT:
428 case TGSI_FILE_HW_ATOMIC:
429 break;
430 case TGSI_FILE_INPUT:
431 if (ctx->type == PIPE_SHADER_GEOMETRY ||
432 ctx->type == PIPE_SHADER_TESS_CTRL ||
433 ctx->type == PIPE_SHADER_TESS_EVAL)
434 break;
435 case TGSI_FILE_OUTPUT:
436 if (ctx->type == PIPE_SHADER_TESS_CTRL)
437 break;
438 default:
439 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
440 i->Src[j].Register.File,
441 i->Src[j].Register.Dimension);
442 return -EINVAL;
443 }
444 }
445 }
446 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
447 if (i->Dst[j].Register.Dimension) {
448 if (ctx->type == PIPE_SHADER_TESS_CTRL)
449 continue;
450 R600_ERR("unsupported dst (dimension)\n");
451 return -EINVAL;
452 }
453 }
454 return 0;
455 }
456
457 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
458 {
459 if (interpolate == TGSI_INTERPOLATE_COLOR ||
460 interpolate == TGSI_INTERPOLATE_LINEAR ||
461 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
462 {
463 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
464 int loc;
465
466 switch(location) {
467 case TGSI_INTERPOLATE_LOC_CENTER:
468 loc = 1;
469 break;
470 case TGSI_INTERPOLATE_LOC_CENTROID:
471 loc = 2;
472 break;
473 case TGSI_INTERPOLATE_LOC_SAMPLE:
474 default:
475 loc = 0; break;
476 }
477
478 return is_linear * 3 + loc;
479 }
480
481 return -1;
482 }
483
484 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
485 int input)
486 {
487 int i = eg_get_interpolator_index(
488 ctx->shader->input[input].interpolate,
489 ctx->shader->input[input].interpolate_location);
490 assert(i >= 0);
491 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
492 }
493
494 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
495 {
496 int i, r;
497 struct r600_bytecode_alu alu;
498 int gpr = 0, base_chan = 0;
499 int ij_index = ctx->shader->input[input].ij_index;
500
501 /* work out gpr and base_chan from index */
502 gpr = ij_index / 2;
503 base_chan = (2 * (ij_index % 2)) + 1;
504
505 for (i = 0; i < 8; i++) {
506 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
507
508 if (i < 4)
509 alu.op = ALU_OP2_INTERP_ZW;
510 else
511 alu.op = ALU_OP2_INTERP_XY;
512
513 if ((i > 1) && (i < 6)) {
514 alu.dst.sel = ctx->shader->input[input].gpr;
515 alu.dst.write = 1;
516 }
517
518 alu.dst.chan = i % 4;
519
520 alu.src[0].sel = gpr;
521 alu.src[0].chan = (base_chan - (i % 2));
522
523 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
524
525 alu.bank_swizzle_force = SQ_ALU_VEC_210;
526 if ((i % 4) == 3)
527 alu.last = 1;
528 r = r600_bytecode_add_alu(ctx->bc, &alu);
529 if (r)
530 return r;
531 }
532 return 0;
533 }
534
535 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
536 {
537 int i, r;
538 struct r600_bytecode_alu alu;
539
540 for (i = 0; i < 4; i++) {
541 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
542
543 alu.op = ALU_OP1_INTERP_LOAD_P0;
544
545 alu.dst.sel = ctx->shader->input[input].gpr;
546 alu.dst.write = 1;
547
548 alu.dst.chan = i;
549
550 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
551 alu.src[0].chan = i;
552
553 if (i == 3)
554 alu.last = 1;
555 r = r600_bytecode_add_alu(ctx->bc, &alu);
556 if (r)
557 return r;
558 }
559 return 0;
560 }
561
562 /*
563 * Special export handling in shaders
564 *
565 * shader export ARRAY_BASE for EXPORT_POS:
566 * 60 is position
567 * 61 is misc vector
568 * 62, 63 are clip distance vectors
569 *
570 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
571 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
572 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
573 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
574 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
575 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
576 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
577 * exclusive from render target index)
578 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
579 *
580 *
581 * shader export ARRAY_BASE for EXPORT_PIXEL:
582 * 0-7 CB targets
583 * 61 computed Z vector
584 *
585 * The use of the values exported in the computed Z vector are controlled
586 * by DB_SHADER_CONTROL:
587 * Z_EXPORT_ENABLE - Z as a float in RED
588 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
589 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
590 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
591 * DB_SOURCE_FORMAT - export control restrictions
592 *
593 */
594
595
596 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
597 static int r600_spi_sid(struct r600_shader_io * io)
598 {
599 int index, name = io->name;
600
601 /* These params are handled differently, they don't need
602 * semantic indices, so we'll use 0 for them.
603 */
604 if (name == TGSI_SEMANTIC_POSITION ||
605 name == TGSI_SEMANTIC_PSIZE ||
606 name == TGSI_SEMANTIC_EDGEFLAG ||
607 name == TGSI_SEMANTIC_FACE ||
608 name == TGSI_SEMANTIC_SAMPLEMASK)
609 index = 0;
610 else {
611 if (name == TGSI_SEMANTIC_GENERIC) {
612 /* For generic params simply use sid from tgsi */
613 index = io->sid;
614 } else {
615 /* For non-generic params - pack name and sid into 8 bits */
616 index = 0x80 | (name<<3) | (io->sid);
617 }
618
619 /* Make sure that all really used indices have nonzero value, so
620 * we can just compare it to 0 later instead of comparing the name
621 * with different values to detect special cases. */
622 index++;
623 }
624
625 return index;
626 };
627
628 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
629 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
630 {
631 switch (semantic_name) {
632 case TGSI_SEMANTIC_POSITION:
633 return 0;
634 case TGSI_SEMANTIC_PSIZE:
635 return 1;
636 case TGSI_SEMANTIC_CLIPDIST:
637 assert(index <= 1);
638 return 2 + index;
639 case TGSI_SEMANTIC_GENERIC:
640 if (index <= 63-4)
641 return 4 + index - 9;
642 else
643 /* same explanation as in the default statement,
644 * the only user hitting this is st/nine.
645 */
646 return 0;
647
648 /* patch indices are completely separate and thus start from 0 */
649 case TGSI_SEMANTIC_TESSOUTER:
650 return 0;
651 case TGSI_SEMANTIC_TESSINNER:
652 return 1;
653 case TGSI_SEMANTIC_PATCH:
654 return 2 + index;
655
656 default:
657 /* Don't fail here. The result of this function is only used
658 * for LS, TCS, TES, and GS, where legacy GL semantics can't
659 * occur, but this function is called for all vertex shaders
660 * before it's known whether LS will be compiled or not.
661 */
662 return 0;
663 }
664 }
665
666 /* turn input into interpolate on EG */
667 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
668 {
669 int r = 0;
670
671 if (ctx->shader->input[index].spi_sid) {
672 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
673 if (ctx->shader->input[index].interpolate > 0) {
674 evergreen_interp_assign_ij_index(ctx, index);
675 r = evergreen_interp_alu(ctx, index);
676 } else {
677 r = evergreen_interp_flat(ctx, index);
678 }
679 }
680 return r;
681 }
682
683 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
684 {
685 struct r600_bytecode_alu alu;
686 int i, r;
687 int gpr_front = ctx->shader->input[front].gpr;
688 int gpr_back = ctx->shader->input[back].gpr;
689
690 for (i = 0; i < 4; i++) {
691 memset(&alu, 0, sizeof(alu));
692 alu.op = ALU_OP3_CNDGT;
693 alu.is_op3 = 1;
694 alu.dst.write = 1;
695 alu.dst.sel = gpr_front;
696 alu.src[0].sel = ctx->face_gpr;
697 alu.src[1].sel = gpr_front;
698 alu.src[2].sel = gpr_back;
699
700 alu.dst.chan = i;
701 alu.src[1].chan = i;
702 alu.src[2].chan = i;
703 alu.last = (i==3);
704
705 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
706 return r;
707 }
708
709 return 0;
710 }
711
712 /* execute a single slot ALU calculation */
713 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
714 int dst_sel, int dst_chan,
715 int src0_sel, unsigned src0_chan_val,
716 int src1_sel, unsigned src1_chan_val)
717 {
718 struct r600_bytecode_alu alu;
719 int r, i;
720
721 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
722 for (i = 0; i < 4; i++) {
723 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
724 alu.op = op;
725 alu.src[0].sel = src0_sel;
726 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
727 alu.src[0].value = src0_chan_val;
728 else
729 alu.src[0].chan = src0_chan_val;
730 alu.src[1].sel = src1_sel;
731 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
732 alu.src[1].value = src1_chan_val;
733 else
734 alu.src[1].chan = src1_chan_val;
735 alu.dst.sel = dst_sel;
736 alu.dst.chan = i;
737 alu.dst.write = i == dst_chan;
738 alu.last = (i == 3);
739 r = r600_bytecode_add_alu(ctx->bc, &alu);
740 if (r)
741 return r;
742 }
743 return 0;
744 }
745
746 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
747 alu.op = op;
748 alu.src[0].sel = src0_sel;
749 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
750 alu.src[0].value = src0_chan_val;
751 else
752 alu.src[0].chan = src0_chan_val;
753 alu.src[1].sel = src1_sel;
754 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
755 alu.src[1].value = src1_chan_val;
756 else
757 alu.src[1].chan = src1_chan_val;
758 alu.dst.sel = dst_sel;
759 alu.dst.chan = dst_chan;
760 alu.dst.write = 1;
761 alu.last = 1;
762 r = r600_bytecode_add_alu(ctx->bc, &alu);
763 if (r)
764 return r;
765 return 0;
766 }
767
768 /* execute a single slot ALU calculation */
769 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
770 int dst_sel, int dst_chan,
771 int src0_sel, unsigned src0_chan_val,
772 int src1_sel, unsigned src1_chan_val,
773 int src2_sel, unsigned src2_chan_val)
774 {
775 struct r600_bytecode_alu alu;
776 int r;
777
778 /* validate this for other ops */
779 assert(op == ALU_OP3_MULADD_UINT24 || op == ALU_OP3_CNDE_INT || op == ALU_OP3_BFE_UINT);
780 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
781 alu.op = op;
782 alu.src[0].sel = src0_sel;
783 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
784 alu.src[0].value = src0_chan_val;
785 else
786 alu.src[0].chan = src0_chan_val;
787 alu.src[1].sel = src1_sel;
788 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
789 alu.src[1].value = src1_chan_val;
790 else
791 alu.src[1].chan = src1_chan_val;
792 alu.src[2].sel = src2_sel;
793 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
794 alu.src[2].value = src2_chan_val;
795 else
796 alu.src[2].chan = src2_chan_val;
797 alu.dst.sel = dst_sel;
798 alu.dst.chan = dst_chan;
799 alu.is_op3 = 1;
800 alu.last = 1;
801 r = r600_bytecode_add_alu(ctx->bc, &alu);
802 if (r)
803 return r;
804 return 0;
805 }
806
807 /* put it in temp_reg.x */
808 static int get_lds_offset0(struct r600_shader_ctx *ctx,
809 int rel_patch_chan,
810 int temp_reg, bool is_patch_var)
811 {
812 int r;
813
814 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
815 /* ADD
816 Dimension - patch0_offset (input_vals.z),
817 Non-dim - patch0_data_offset (input_vals.w)
818 */
819 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
820 temp_reg, 0,
821 ctx->tess_output_info, 0,
822 0, rel_patch_chan,
823 ctx->tess_output_info, is_patch_var ? 3 : 2);
824 if (r)
825 return r;
826 return 0;
827 }
828
829 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
830 {
831 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
832 }
833
834 static int r600_get_temp(struct r600_shader_ctx *ctx)
835 {
836 return ctx->temp_reg + ctx->max_driver_temp_used++;
837 }
838
839 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
840 {
841 int i;
842 i = ctx->shader->noutput++;
843 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
844 ctx->shader->output[i].sid = 0;
845 ctx->shader->output[i].gpr = 0;
846 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
847 ctx->shader->output[i].write_mask = 0x4;
848 ctx->shader->output[i].spi_sid = prim_id_sid;
849
850 return 0;
851 }
852
853 static int tgsi_barrier(struct r600_shader_ctx *ctx)
854 {
855 struct r600_bytecode_alu alu;
856 int r;
857
858 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
859 alu.op = ctx->inst_info->op;
860 alu.last = 1;
861
862 r = r600_bytecode_add_alu(ctx->bc, &alu);
863 if (r)
864 return r;
865 return 0;
866 }
867
868 static void choose_spill_arrays(struct r600_shader_ctx *ctx, int *regno, unsigned *scratch_space_needed)
869 {
870 // pick largest array and spill it, repeat until the number of temps is under limit or we run out of arrays
871 unsigned n = ctx->info.array_max[TGSI_FILE_TEMPORARY];
872 unsigned narrays_left = n;
873 bool *spilled = ctx->spilled_arrays; // assumed calloc:ed
874
875 *scratch_space_needed = 0;
876 while (*regno > 124 && narrays_left) {
877 unsigned i;
878 unsigned largest = 0;
879 unsigned largest_index = 0;
880
881 for (i = 0; i < n; i++) {
882 unsigned size = ctx->array_infos[i].range.Last - ctx->array_infos[i].range.First + 1;
883 if (!spilled[i] && size > largest) {
884 largest = size;
885 largest_index = i;
886 }
887 }
888
889 spilled[largest_index] = true;
890 *regno -= largest;
891 *scratch_space_needed += largest;
892
893 narrays_left --;
894 }
895
896 if (narrays_left == 0) {
897 ctx->info.indirect_files &= ~(1 << TGSI_FILE_TEMPORARY);
898 }
899 }
900
901 /* Take spilled temp arrays into account when translating tgsi register
902 * indexes into r600 gprs if spilled is false, or scratch array offset if
903 * spilled is true */
904 static int map_tgsi_reg_index_to_r600_gpr(struct r600_shader_ctx *ctx, unsigned tgsi_reg_index, bool *spilled)
905 {
906 unsigned i;
907 unsigned spilled_size = 0;
908
909 for (i = 0; i < ctx->info.array_max[TGSI_FILE_TEMPORARY]; i++) {
910 if (tgsi_reg_index >= ctx->array_infos[i].range.First && tgsi_reg_index <= ctx->array_infos[i].range.Last) {
911 if (ctx->spilled_arrays[i]) {
912 /* vec4 index into spilled scratch memory */
913 *spilled = true;
914 return tgsi_reg_index - ctx->array_infos[i].range.First + spilled_size;
915 }
916 else {
917 /* regular GPR array */
918 *spilled = false;
919 return tgsi_reg_index - spilled_size + ctx->file_offset[TGSI_FILE_TEMPORARY];
920 }
921 }
922
923 if (tgsi_reg_index < ctx->array_infos[i].range.First)
924 break;
925 if (ctx->spilled_arrays[i]) {
926 spilled_size += ctx->array_infos[i].range.Last - ctx->array_infos[i].range.First + 1;
927 }
928 }
929
930 /* regular GPR index, minus the holes from spilled arrays */
931 *spilled = false;
932
933 return tgsi_reg_index - spilled_size + ctx->file_offset[TGSI_FILE_TEMPORARY];
934 }
935
936 /* look up spill area base offset and array size for a spilled temp array */
937 static void get_spilled_array_base_and_size(struct r600_shader_ctx *ctx, unsigned tgsi_reg_index,
938 unsigned *array_base, unsigned *array_size)
939 {
940 unsigned i;
941 unsigned offset = 0;
942
943 for (i = 0; i < ctx->info.array_max[TGSI_FILE_TEMPORARY]; i++) {
944 if (ctx->spilled_arrays[i]) {
945 unsigned size = ctx->array_infos[i].range.Last - ctx->array_infos[i].range.First + 1;
946
947 if (tgsi_reg_index >= ctx->array_infos[i].range.First && tgsi_reg_index <= ctx->array_infos[i].range.Last) {
948 *array_base = offset;
949 *array_size = size - 1; /* hw counts from 1 */
950
951 return;
952 }
953
954 offset += size;
955 }
956 }
957 }
958
959 static int tgsi_declaration(struct r600_shader_ctx *ctx)
960 {
961 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
962 int r, i, j, count = d->Range.Last - d->Range.First + 1;
963
964 switch (d->Declaration.File) {
965 case TGSI_FILE_INPUT:
966 for (j = 0; j < count; j++) {
967 i = ctx->shader->ninput + j;
968 assert(i < ARRAY_SIZE(ctx->shader->input));
969 ctx->shader->input[i].name = d->Semantic.Name;
970 ctx->shader->input[i].sid = d->Semantic.Index + j;
971 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
972 ctx->shader->input[i].interpolate_location = d->Interp.Location;
973 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
974 if (ctx->type == PIPE_SHADER_FRAGMENT) {
975 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
976 switch (ctx->shader->input[i].name) {
977 case TGSI_SEMANTIC_FACE:
978 if (ctx->face_gpr != -1)
979 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
980 else
981 ctx->face_gpr = ctx->shader->input[i].gpr;
982 break;
983 case TGSI_SEMANTIC_COLOR:
984 ctx->colors_used++;
985 break;
986 case TGSI_SEMANTIC_POSITION:
987 ctx->fragcoord_input = i;
988 break;
989 case TGSI_SEMANTIC_PRIMID:
990 /* set this for now */
991 ctx->shader->gs_prim_id_input = true;
992 ctx->shader->ps_prim_id_input = i;
993 break;
994 }
995 if (ctx->bc->chip_class >= EVERGREEN) {
996 if ((r = evergreen_interp_input(ctx, i)))
997 return r;
998 }
999 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
1000 /* FIXME probably skip inputs if they aren't passed in the ring */
1001 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
1002 ctx->next_ring_offset += 16;
1003 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
1004 ctx->shader->gs_prim_id_input = true;
1005 }
1006 }
1007 ctx->shader->ninput += count;
1008 break;
1009 case TGSI_FILE_OUTPUT:
1010 for (j = 0; j < count; j++) {
1011 i = ctx->shader->noutput + j;
1012 assert(i < ARRAY_SIZE(ctx->shader->output));
1013 ctx->shader->output[i].name = d->Semantic.Name;
1014 ctx->shader->output[i].sid = d->Semantic.Index + j;
1015 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
1016 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
1017 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
1018 if (ctx->type == PIPE_SHADER_VERTEX ||
1019 ctx->type == PIPE_SHADER_GEOMETRY ||
1020 ctx->type == PIPE_SHADER_TESS_EVAL) {
1021 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
1022 switch (d->Semantic.Name) {
1023 case TGSI_SEMANTIC_CLIPDIST:
1024 break;
1025 case TGSI_SEMANTIC_PSIZE:
1026 ctx->shader->vs_out_misc_write = 1;
1027 ctx->shader->vs_out_point_size = 1;
1028 break;
1029 case TGSI_SEMANTIC_EDGEFLAG:
1030 ctx->shader->vs_out_misc_write = 1;
1031 ctx->shader->vs_out_edgeflag = 1;
1032 ctx->edgeflag_output = i;
1033 break;
1034 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1035 ctx->shader->vs_out_misc_write = 1;
1036 ctx->shader->vs_out_viewport = 1;
1037 break;
1038 case TGSI_SEMANTIC_LAYER:
1039 ctx->shader->vs_out_misc_write = 1;
1040 ctx->shader->vs_out_layer = 1;
1041 break;
1042 case TGSI_SEMANTIC_CLIPVERTEX:
1043 ctx->clip_vertex_write = TRUE;
1044 ctx->cv_output = i;
1045 break;
1046 }
1047 if (ctx->type == PIPE_SHADER_GEOMETRY) {
1048 ctx->gs_out_ring_offset += 16;
1049 }
1050 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
1051 switch (d->Semantic.Name) {
1052 case TGSI_SEMANTIC_COLOR:
1053 ctx->shader->nr_ps_max_color_exports++;
1054 break;
1055 }
1056 }
1057 }
1058 ctx->shader->noutput += count;
1059 break;
1060 case TGSI_FILE_TEMPORARY:
1061 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
1062 if (d->Array.ArrayID) {
1063 bool spilled;
1064 unsigned idx = map_tgsi_reg_index_to_r600_gpr(ctx,
1065 d->Range.First,
1066 &spilled);
1067
1068 if (!spilled) {
1069 r600_add_gpr_array(ctx->shader, idx,
1070 d->Range.Last - d->Range.First + 1, 0x0F);
1071 }
1072 }
1073 }
1074 break;
1075
1076 case TGSI_FILE_CONSTANT:
1077 case TGSI_FILE_SAMPLER:
1078 case TGSI_FILE_SAMPLER_VIEW:
1079 case TGSI_FILE_ADDRESS:
1080 case TGSI_FILE_BUFFER:
1081 case TGSI_FILE_IMAGE:
1082 case TGSI_FILE_MEMORY:
1083 break;
1084
1085 case TGSI_FILE_HW_ATOMIC:
1086 i = ctx->shader->nhwatomic_ranges;
1087 ctx->shader->atomics[i].start = d->Range.First;
1088 ctx->shader->atomics[i].end = d->Range.Last;
1089 ctx->shader->atomics[i].hw_idx = ctx->shader->atomic_base + ctx->shader->nhwatomic;
1090 ctx->shader->atomics[i].array_id = d->Array.ArrayID;
1091 ctx->shader->atomics[i].buffer_id = d->Dim.Index2D;
1092 ctx->shader->nhwatomic_ranges++;
1093 ctx->shader->nhwatomic += count;
1094 break;
1095
1096 case TGSI_FILE_SYSTEM_VALUE:
1097 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
1098 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
1099 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
1100 break; /* Already handled from allocate_system_value_inputs */
1101 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
1102 break;
1103 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
1104 break;
1105 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
1106 break;
1107 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1108 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1109 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1110 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1111 unsigned temp_reg = r600_get_temp(ctx);
1112
1113 r = get_lds_offset0(ctx, 2, temp_reg, true);
1114 if (r)
1115 return r;
1116
1117 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1118 temp_reg, 0,
1119 temp_reg, 0,
1120 V_SQ_ALU_SRC_LITERAL, param * 16);
1121 if (r)
1122 return r;
1123
1124 do_lds_fetch_values(ctx, temp_reg, dreg, 0xf);
1125 }
1126 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1127 /* MOV r1.x, r0.x;
1128 MOV r1.y, r0.y;
1129 */
1130 for (i = 0; i < 2; i++) {
1131 struct r600_bytecode_alu alu;
1132 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1133 alu.op = ALU_OP1_MOV;
1134 alu.src[0].sel = 0;
1135 alu.src[0].chan = 0 + i;
1136 alu.dst.sel = 1;
1137 alu.dst.chan = 0 + i;
1138 alu.dst.write = 1;
1139 alu.last = (i == 1) ? 1 : 0;
1140 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1141 return r;
1142 }
1143 /* ADD r1.z, 1.0f, -r0.x */
1144 struct r600_bytecode_alu alu;
1145 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1146 alu.op = ALU_OP2_ADD;
1147 alu.src[0].sel = V_SQ_ALU_SRC_1;
1148 alu.src[1].sel = 1;
1149 alu.src[1].chan = 0;
1150 alu.src[1].neg = 1;
1151 alu.dst.sel = 1;
1152 alu.dst.chan = 2;
1153 alu.dst.write = 1;
1154 alu.last = 1;
1155 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1156 return r;
1157
1158 /* ADD r1.z, r1.z, -r1.y */
1159 alu.op = ALU_OP2_ADD;
1160 alu.src[0].sel = 1;
1161 alu.src[0].chan = 2;
1162 alu.src[1].sel = 1;
1163 alu.src[1].chan = 1;
1164 alu.src[1].neg = 1;
1165 alu.dst.sel = 1;
1166 alu.dst.chan = 2;
1167 alu.dst.write = 1;
1168 alu.last = 1;
1169 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1170 return r;
1171 break;
1172 }
1173 break;
1174 default:
1175 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1176 return -EINVAL;
1177 }
1178 return 0;
1179 }
1180
1181 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1182 {
1183 struct tgsi_parse_context parse;
1184 struct {
1185 boolean enabled;
1186 int *reg;
1187 unsigned name, alternate_name;
1188 } inputs[2] = {
1189 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1190
1191 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1192 };
1193 int num_regs = 0;
1194 unsigned k, i;
1195
1196 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1197 return 0;
1198 }
1199
1200 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1201 while (!tgsi_parse_end_of_tokens(&parse)) {
1202 tgsi_parse_token(&parse);
1203
1204 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1205 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1206 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1207 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1208 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1209 {
1210 int interpolate, location, k;
1211
1212 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1213 location = TGSI_INTERPOLATE_LOC_CENTER;
1214 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1215 location = TGSI_INTERPOLATE_LOC_CENTER;
1216 /* Needs sample positions, currently those are always available */
1217 } else {
1218 location = TGSI_INTERPOLATE_LOC_CENTROID;
1219 }
1220
1221 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1222 k = eg_get_interpolator_index(interpolate, location);
1223 if (k >= 0)
1224 ctx->eg_interpolators[k].enabled = true;
1225 }
1226 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1227 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1228 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1229 for (k = 0; k < ARRAY_SIZE(inputs); k++) {
1230 if (d->Semantic.Name == inputs[k].name ||
1231 d->Semantic.Name == inputs[k].alternate_name) {
1232 inputs[k].enabled = true;
1233 }
1234 }
1235 }
1236 }
1237 }
1238
1239 tgsi_parse_free(&parse);
1240
1241 if (ctx->info.reads_samplemask &&
1242 (ctx->info.uses_linear_sample || ctx->info.uses_linear_sample)) {
1243 inputs[1].enabled = true;
1244 }
1245
1246 if (ctx->bc->chip_class >= EVERGREEN) {
1247 int num_baryc = 0;
1248 /* assign gpr to each interpolator according to priority */
1249 for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
1250 if (ctx->eg_interpolators[i].enabled) {
1251 ctx->eg_interpolators[i].ij_index = num_baryc;
1252 num_baryc++;
1253 }
1254 }
1255 num_baryc = (num_baryc + 1) >> 1;
1256 gpr_offset += num_baryc;
1257 }
1258
1259 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
1260 boolean enabled = inputs[i].enabled;
1261 int *reg = inputs[i].reg;
1262 unsigned name = inputs[i].name;
1263
1264 if (enabled) {
1265 int gpr = gpr_offset + num_regs++;
1266 ctx->shader->nsys_inputs++;
1267
1268 // add to inputs, allocate a gpr
1269 k = ctx->shader->ninput++;
1270 ctx->shader->input[k].name = name;
1271 ctx->shader->input[k].sid = 0;
1272 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1273 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1274 *reg = ctx->shader->input[k].gpr = gpr;
1275 }
1276 }
1277
1278 return gpr_offset + num_regs;
1279 }
1280
1281 /*
1282 * for evergreen we need to scan the shader to find the number of GPRs we need to
1283 * reserve for interpolation and system values
1284 *
1285 * we need to know if we are going to emit any sample or centroid inputs
1286 * if perspective and linear are required
1287 */
1288 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1289 {
1290 unsigned i;
1291
1292 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1293
1294 /*
1295 * Could get this information from the shader info. But right now
1296 * we interpolate all declared inputs, whereas the shader info will
1297 * only contain the bits if the inputs are actually used, so it might
1298 * not be safe...
1299 */
1300 for (i = 0; i < ctx->info.num_inputs; i++) {
1301 int k;
1302 /* skip position/face/mask/sampleid */
1303 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1304 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1305 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1306 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1307 continue;
1308
1309 k = eg_get_interpolator_index(
1310 ctx->info.input_interpolate[i],
1311 ctx->info.input_interpolate_loc[i]);
1312 if (k >= 0)
1313 ctx->eg_interpolators[k].enabled = TRUE;
1314 }
1315
1316 /* XXX PULL MODEL and LINE STIPPLE */
1317
1318 return allocate_system_value_inputs(ctx, 0);
1319 }
1320
1321 /* sample_id_sel == NULL means fetch for current sample */
1322 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1323 {
1324 struct r600_bytecode_vtx vtx;
1325 int r, t1;
1326
1327 t1 = r600_get_temp(ctx);
1328
1329 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1330 vtx.op = FETCH_OP_VFETCH;
1331 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1332 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1333 if (sample_id == NULL) {
1334 assert(ctx->fixed_pt_position_gpr != -1);
1335
1336 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1337 vtx.src_sel_x = 3;
1338 }
1339 else {
1340 struct r600_bytecode_alu alu;
1341
1342 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1343 alu.op = ALU_OP1_MOV;
1344 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1345 alu.dst.sel = t1;
1346 alu.dst.write = 1;
1347 alu.last = 1;
1348 r = r600_bytecode_add_alu(ctx->bc, &alu);
1349 if (r)
1350 return r;
1351
1352 vtx.src_gpr = t1;
1353 vtx.src_sel_x = 0;
1354 }
1355 vtx.mega_fetch_count = 16;
1356 vtx.dst_gpr = t1;
1357 vtx.dst_sel_x = 0;
1358 vtx.dst_sel_y = 1;
1359 vtx.dst_sel_z = 2;
1360 vtx.dst_sel_w = 3;
1361 vtx.data_format = FMT_32_32_32_32_FLOAT;
1362 vtx.num_format_all = 2;
1363 vtx.format_comp_all = 1;
1364 vtx.use_const_fields = 0;
1365 vtx.offset = 0;
1366 vtx.endian = r600_endian_swap(32);
1367 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1368
1369 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1370 if (r)
1371 return r;
1372
1373 return t1;
1374 }
1375
1376 static int eg_load_helper_invocation(struct r600_shader_ctx *ctx)
1377 {
1378 int r;
1379 struct r600_bytecode_alu alu;
1380
1381 /* do a vtx fetch with wqm set on the vtx fetch */
1382 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1383 alu.op = ALU_OP1_MOV;
1384 alu.dst.sel = ctx->helper_invoc_reg;
1385 alu.dst.chan = 0;
1386 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
1387 alu.src[0].value = 0xffffffff;
1388 alu.dst.write = 1;
1389 alu.last = 1;
1390 r = r600_bytecode_add_alu(ctx->bc, &alu);
1391 if (r)
1392 return r;
1393
1394 /* do a vtx fetch in VPM mode */
1395 struct r600_bytecode_vtx vtx;
1396 memset(&vtx, 0, sizeof(vtx));
1397 vtx.op = FETCH_OP_GET_BUFFER_RESINFO;
1398 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1399 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1400 vtx.src_gpr = 0;
1401 vtx.mega_fetch_count = 16; /* no idea here really... */
1402 vtx.dst_gpr = ctx->helper_invoc_reg;
1403 vtx.dst_sel_x = 4;
1404 vtx.dst_sel_y = 7; /* SEL_Y */
1405 vtx.dst_sel_z = 7; /* SEL_Z */
1406 vtx.dst_sel_w = 7; /* SEL_W */
1407 vtx.data_format = FMT_32;
1408 if ((r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx)))
1409 return r;
1410 ctx->bc->cf_last->vpm = 1;
1411 return 0;
1412 }
1413
1414 static int cm_load_helper_invocation(struct r600_shader_ctx *ctx)
1415 {
1416 int r;
1417 struct r600_bytecode_alu alu;
1418
1419 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1420 alu.op = ALU_OP1_MOV;
1421 alu.dst.sel = ctx->helper_invoc_reg;
1422 alu.dst.chan = 0;
1423 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
1424 alu.src[0].value = 0xffffffff;
1425 alu.dst.write = 1;
1426 alu.last = 1;
1427 r = r600_bytecode_add_alu(ctx->bc, &alu);
1428 if (r)
1429 return r;
1430
1431 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1432 alu.op = ALU_OP1_MOV;
1433 alu.dst.sel = ctx->helper_invoc_reg;
1434 alu.dst.chan = 0;
1435 alu.src[0].sel = V_SQ_ALU_SRC_0;
1436 alu.dst.write = 1;
1437 alu.last = 1;
1438 r = r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_VALID_PIXEL_MODE);
1439 if (r)
1440 return r;
1441
1442 return ctx->helper_invoc_reg;
1443 }
1444
1445 static int load_block_grid_size(struct r600_shader_ctx *ctx, bool load_block)
1446 {
1447 struct r600_bytecode_vtx vtx;
1448 int r, t1;
1449
1450 if (ctx->cs_block_size_loaded)
1451 return ctx->cs_block_size_reg;
1452 if (ctx->cs_grid_size_loaded)
1453 return ctx->cs_grid_size_reg;
1454
1455 t1 = load_block ? ctx->cs_block_size_reg : ctx->cs_grid_size_reg;
1456 struct r600_bytecode_alu alu;
1457 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1458 alu.op = ALU_OP1_MOV;
1459 alu.src[0].sel = V_SQ_ALU_SRC_0;
1460 alu.dst.sel = t1;
1461 alu.dst.write = 1;
1462 alu.last = 1;
1463 r = r600_bytecode_add_alu(ctx->bc, &alu);
1464 if (r)
1465 return r;
1466
1467 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1468 vtx.op = FETCH_OP_VFETCH;
1469 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1470 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1471 vtx.src_gpr = t1;
1472 vtx.src_sel_x = 0;
1473
1474 vtx.mega_fetch_count = 16;
1475 vtx.dst_gpr = t1;
1476 vtx.dst_sel_x = 0;
1477 vtx.dst_sel_y = 1;
1478 vtx.dst_sel_z = 2;
1479 vtx.dst_sel_w = 7;
1480 vtx.data_format = FMT_32_32_32_32;
1481 vtx.num_format_all = 1;
1482 vtx.format_comp_all = 0;
1483 vtx.use_const_fields = 0;
1484 vtx.offset = load_block ? 0 : 16; // first element is size of buffer
1485 vtx.endian = r600_endian_swap(32);
1486 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1487
1488 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1489 if (r)
1490 return r;
1491
1492 if (load_block)
1493 ctx->cs_block_size_loaded = true;
1494 else
1495 ctx->cs_grid_size_loaded = true;
1496 return t1;
1497 }
1498
1499 static void tgsi_src(struct r600_shader_ctx *ctx,
1500 const struct tgsi_full_src_register *tgsi_src,
1501 struct r600_shader_src *r600_src)
1502 {
1503 memset(r600_src, 0, sizeof(*r600_src));
1504 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1505 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1506 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1507 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1508 r600_src->neg = tgsi_src->Register.Negate;
1509 r600_src->abs = tgsi_src->Register.Absolute;
1510
1511 if (tgsi_src->Register.File == TGSI_FILE_TEMPORARY) {
1512 bool spilled;
1513 unsigned idx;
1514
1515 idx = map_tgsi_reg_index_to_r600_gpr(ctx, tgsi_src->Register.Index, &spilled);
1516
1517 if (spilled) {
1518 int reg = r600_get_temp(ctx);
1519 int r;
1520
1521 r600_src->sel = reg;
1522
1523 if (ctx->bc->chip_class < R700) {
1524 struct r600_bytecode_output cf;
1525
1526 memset(&cf, 0, sizeof(struct r600_bytecode_output));
1527 cf.op = CF_OP_MEM_SCRATCH;
1528 cf.elem_size = 3;
1529 cf.gpr = reg;
1530 cf.comp_mask = 0xF;
1531 cf.swizzle_x = 0;
1532 cf.swizzle_y = 1;
1533 cf.swizzle_z = 2;
1534 cf.swizzle_w = 3;
1535 cf.burst_count = 1;
1536
1537 get_spilled_array_base_and_size(ctx, tgsi_src->Register.Index,
1538 &cf.array_base, &cf.array_size);
1539
1540 if (tgsi_src->Register.Indirect) {
1541 cf.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
1542 cf.index_gpr = ctx->bc->ar_reg;
1543 }
1544 else {
1545 cf.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ;
1546 cf.array_base += idx;
1547 cf.array_size = 0;
1548 }
1549
1550 r = r600_bytecode_add_output(ctx->bc, &cf);
1551 }
1552 else {
1553 struct r600_bytecode_vtx vtx;
1554
1555 if (r600_bytecode_get_need_wait_ack(ctx->bc)) {
1556 r600_bytecode_need_wait_ack(ctx->bc, false);
1557 r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
1558 }
1559
1560 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1561 vtx.op = FETCH_OP_READ_SCRATCH;
1562 vtx.dst_gpr = reg;
1563 vtx.uncached = 1; // Must bypass cache since prior spill written in same invocation
1564 vtx.elem_size = 3;
1565 vtx.data_format = FMT_32_32_32_32;
1566 vtx.num_format_all = V_038010_SQ_NUM_FORMAT_INT;
1567 vtx.dst_sel_x = tgsi_src->Register.SwizzleX;
1568 vtx.dst_sel_y = tgsi_src->Register.SwizzleY;
1569 vtx.dst_sel_z = tgsi_src->Register.SwizzleZ;
1570 vtx.dst_sel_w = tgsi_src->Register.SwizzleW;
1571
1572 get_spilled_array_base_and_size(ctx, tgsi_src->Register.Index,
1573 &vtx.array_base, &vtx.array_size);
1574
1575 if (tgsi_src->Register.Indirect) {
1576 vtx.indexed = 1;
1577 vtx.src_gpr = ctx->bc->ar_reg;
1578 }
1579 else {
1580 vtx.array_base += idx;
1581 vtx.array_size = 0;
1582 }
1583
1584 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1585 }
1586
1587 if (r)
1588 return;
1589 }
1590 else {
1591 if (tgsi_src->Register.Indirect)
1592 r600_src->rel = V_SQ_REL_RELATIVE;
1593
1594 r600_src->sel = idx;
1595 }
1596
1597 return;
1598 }
1599
1600 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1601 int index;
1602 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1603 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1604 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1605
1606 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1607 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1608 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1609 return;
1610 }
1611 index = tgsi_src->Register.Index;
1612 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1613 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1614 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1615 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1616 r600_src->swizzle[0] = 2; // Z value
1617 r600_src->swizzle[1] = 2;
1618 r600_src->swizzle[2] = 2;
1619 r600_src->swizzle[3] = 2;
1620 r600_src->sel = ctx->face_gpr;
1621 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1622 r600_src->swizzle[0] = 3; // W value
1623 r600_src->swizzle[1] = 3;
1624 r600_src->swizzle[2] = 3;
1625 r600_src->swizzle[3] = 3;
1626 r600_src->sel = ctx->fixed_pt_position_gpr;
1627 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1628 r600_src->swizzle[0] = 0;
1629 r600_src->swizzle[1] = 1;
1630 r600_src->swizzle[2] = 4;
1631 r600_src->swizzle[3] = 4;
1632 r600_src->sel = load_sample_position(ctx, NULL, -1);
1633 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1634 r600_src->swizzle[0] = 3;
1635 r600_src->swizzle[1] = 3;
1636 r600_src->swizzle[2] = 3;
1637 r600_src->swizzle[3] = 3;
1638 r600_src->sel = 0;
1639 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1640 r600_src->swizzle[0] = 0;
1641 r600_src->swizzle[1] = 0;
1642 r600_src->swizzle[2] = 0;
1643 r600_src->swizzle[3] = 0;
1644 r600_src->sel = 0;
1645 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_THREAD_ID) {
1646 r600_src->sel = 0;
1647 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_BLOCK_ID) {
1648 r600_src->sel = 1;
1649 } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1650 r600_src->swizzle[0] = 3;
1651 r600_src->swizzle[1] = 3;
1652 r600_src->swizzle[2] = 3;
1653 r600_src->swizzle[3] = 3;
1654 r600_src->sel = 1;
1655 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1656 r600_src->swizzle[0] = 2;
1657 r600_src->swizzle[1] = 2;
1658 r600_src->swizzle[2] = 2;
1659 r600_src->swizzle[3] = 2;
1660 r600_src->sel = 0;
1661 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1662 r600_src->sel = 1;
1663 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1664 r600_src->sel = 3;
1665 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1666 r600_src->sel = 2;
1667 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1668 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
1669 r600_src->sel = ctx->tess_input_info;
1670 r600_src->swizzle[0] = 2;
1671 r600_src->swizzle[1] = 2;
1672 r600_src->swizzle[2] = 2;
1673 r600_src->swizzle[3] = 2;
1674 } else {
1675 r600_src->sel = ctx->tess_input_info;
1676 r600_src->swizzle[0] = 3;
1677 r600_src->swizzle[1] = 3;
1678 r600_src->swizzle[2] = 3;
1679 r600_src->swizzle[3] = 3;
1680 }
1681 } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1682 r600_src->sel = 0;
1683 r600_src->swizzle[0] = 0;
1684 r600_src->swizzle[1] = 0;
1685 r600_src->swizzle[2] = 0;
1686 r600_src->swizzle[3] = 0;
1687 } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1688 r600_src->sel = 0;
1689 r600_src->swizzle[0] = 3;
1690 r600_src->swizzle[1] = 3;
1691 r600_src->swizzle[2] = 3;
1692 r600_src->swizzle[3] = 3;
1693 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_GRID_SIZE) {
1694 r600_src->sel = load_block_grid_size(ctx, false);
1695 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_BLOCK_SIZE) {
1696 r600_src->sel = load_block_grid_size(ctx, true);
1697 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_HELPER_INVOCATION) {
1698 r600_src->sel = ctx->helper_invoc_reg;
1699 r600_src->swizzle[0] = 0;
1700 r600_src->swizzle[1] = 0;
1701 r600_src->swizzle[2] = 0;
1702 r600_src->swizzle[3] = 0;
1703 }
1704 } else {
1705 if (tgsi_src->Register.Indirect)
1706 r600_src->rel = V_SQ_REL_RELATIVE;
1707 r600_src->sel = tgsi_src->Register.Index;
1708 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1709 }
1710 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1711 if (tgsi_src->Register.Dimension) {
1712 r600_src->kc_bank = tgsi_src->Dimension.Index;
1713 if (tgsi_src->Dimension.Indirect) {
1714 r600_src->kc_rel = 1;
1715 }
1716 }
1717 }
1718 }
1719
1720 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1721 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1722 unsigned int dst_reg)
1723 {
1724 struct r600_bytecode_vtx vtx;
1725 unsigned int ar_reg;
1726 int r;
1727
1728 if (offset) {
1729 struct r600_bytecode_alu alu;
1730
1731 memset(&alu, 0, sizeof(alu));
1732
1733 alu.op = ALU_OP2_ADD_INT;
1734 alu.src[0].sel = ctx->bc->ar_reg;
1735 alu.src[0].chan = ar_chan;
1736
1737 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1738 alu.src[1].value = offset;
1739
1740 alu.dst.sel = dst_reg;
1741 alu.dst.chan = ar_chan;
1742 alu.dst.write = 1;
1743 alu.last = 1;
1744
1745 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1746 return r;
1747
1748 ar_reg = dst_reg;
1749 } else {
1750 ar_reg = ctx->bc->ar_reg;
1751 }
1752
1753 memset(&vtx, 0, sizeof(vtx));
1754 vtx.buffer_id = cb_idx;
1755 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1756 vtx.src_gpr = ar_reg;
1757 vtx.src_sel_x = ar_chan;
1758 vtx.mega_fetch_count = 16;
1759 vtx.dst_gpr = dst_reg;
1760 vtx.dst_sel_x = 0; /* SEL_X */
1761 vtx.dst_sel_y = 1; /* SEL_Y */
1762 vtx.dst_sel_z = 2; /* SEL_Z */
1763 vtx.dst_sel_w = 3; /* SEL_W */
1764 vtx.data_format = FMT_32_32_32_32_FLOAT;
1765 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1766 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1767 vtx.endian = r600_endian_swap(32);
1768 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1769
1770 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1771 return r;
1772
1773 return 0;
1774 }
1775
1776 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1777 {
1778 struct r600_bytecode_vtx vtx;
1779 int r;
1780 unsigned index = src->Register.Index;
1781 unsigned vtx_id = src->Dimension.Index;
1782 int offset_reg = ctx->gs_rotated_input[vtx_id / 3];
1783 int offset_chan = vtx_id % 3;
1784 int t2 = 0;
1785
1786 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1787 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1788
1789 if (offset_reg == ctx->gs_rotated_input[0] && offset_chan == 2)
1790 offset_chan = 3;
1791
1792 if (src->Dimension.Indirect || src->Register.Indirect)
1793 t2 = r600_get_temp(ctx);
1794
1795 if (src->Dimension.Indirect) {
1796 int treg[3];
1797 struct r600_bytecode_alu alu;
1798 int r, i;
1799 unsigned addr_reg;
1800 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1801 if (src->DimIndirect.Index > 0) {
1802 r = single_alu_op2(ctx, ALU_OP1_MOV,
1803 ctx->bc->ar_reg, 0,
1804 addr_reg, 0,
1805 0, 0);
1806 if (r)
1807 return r;
1808 }
1809 /*
1810 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1811 at least this is what fglrx seems to do. */
1812 for (i = 0; i < 3; i++) {
1813 treg[i] = r600_get_temp(ctx);
1814 }
1815 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1816
1817 for (i = 0; i < 3; i++) {
1818 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1819 alu.op = ALU_OP1_MOV;
1820 alu.src[0].sel = ctx->gs_rotated_input[0];
1821 alu.src[0].chan = i == 2 ? 3 : i;
1822 alu.dst.sel = treg[i];
1823 alu.dst.chan = 0;
1824 alu.dst.write = 1;
1825 alu.last = 1;
1826 r = r600_bytecode_add_alu(ctx->bc, &alu);
1827 if (r)
1828 return r;
1829 }
1830 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1831 alu.op = ALU_OP1_MOV;
1832 alu.src[0].sel = treg[0];
1833 alu.src[0].rel = 1;
1834 alu.dst.sel = t2;
1835 alu.dst.write = 1;
1836 alu.last = 1;
1837 r = r600_bytecode_add_alu(ctx->bc, &alu);
1838 if (r)
1839 return r;
1840 offset_reg = t2;
1841 offset_chan = 0;
1842 }
1843
1844 if (src->Register.Indirect) {
1845 int addr_reg;
1846 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1847
1848 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1849
1850 /* pull the value from index_reg */
1851 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1852 t2, 1,
1853 addr_reg, 0,
1854 V_SQ_ALU_SRC_LITERAL, first);
1855 if (r)
1856 return r;
1857 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1858 t2, 0,
1859 t2, 1,
1860 V_SQ_ALU_SRC_LITERAL, 4,
1861 offset_reg, offset_chan);
1862 if (r)
1863 return r;
1864 offset_reg = t2;
1865 offset_chan = 0;
1866 index = src->Register.Index - first;
1867 }
1868
1869 memset(&vtx, 0, sizeof(vtx));
1870 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1871 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1872 vtx.src_gpr = offset_reg;
1873 vtx.src_sel_x = offset_chan;
1874 vtx.offset = index * 16; /*bytes*/
1875 vtx.mega_fetch_count = 16;
1876 vtx.dst_gpr = dst_reg;
1877 vtx.dst_sel_x = 0; /* SEL_X */
1878 vtx.dst_sel_y = 1; /* SEL_Y */
1879 vtx.dst_sel_z = 2; /* SEL_Z */
1880 vtx.dst_sel_w = 3; /* SEL_W */
1881 if (ctx->bc->chip_class >= EVERGREEN) {
1882 vtx.use_const_fields = 1;
1883 } else {
1884 vtx.data_format = FMT_32_32_32_32_FLOAT;
1885 }
1886
1887 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1888 return r;
1889
1890 return 0;
1891 }
1892
1893 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1894 {
1895 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1896 unsigned i;
1897
1898 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1899 struct tgsi_full_src_register *src = &inst->Src[i];
1900
1901 if (src->Register.File == TGSI_FILE_INPUT) {
1902 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1903 /* primitive id is in R0.z */
1904 ctx->src[i].sel = 0;
1905 ctx->src[i].swizzle[0] = 2;
1906 }
1907 }
1908 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1909 int treg = r600_get_temp(ctx);
1910
1911 fetch_gs_input(ctx, src, treg);
1912 ctx->src[i].sel = treg;
1913 ctx->src[i].rel = 0;
1914 }
1915 }
1916 return 0;
1917 }
1918
1919
1920 /* Tessellation shaders pass outputs to the next shader using LDS.
1921 *
1922 * LS outputs = TCS(HS) inputs
1923 * TCS(HS) outputs = TES(DS) inputs
1924 *
1925 * The LDS layout is:
1926 * - TCS inputs for patch 0
1927 * - TCS inputs for patch 1
1928 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1929 * - ...
1930 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1931 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1932 * - TCS outputs for patch 1
1933 * - Per-patch TCS outputs for patch 1
1934 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1935 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1936 * - ...
1937 *
1938 * All three shaders VS(LS), TCS, TES share the same LDS space.
1939 */
1940 /* this will return with the dw address in temp_reg.x */
1941 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1942 const struct tgsi_full_dst_register *dst,
1943 const struct tgsi_full_src_register *src,
1944 int stride_bytes_reg, int stride_bytes_chan)
1945 {
1946 struct tgsi_full_dst_register reg;
1947 ubyte *name, *index, *array_first;
1948 int r;
1949 int param;
1950 struct tgsi_shader_info *info = &ctx->info;
1951 /* Set the register description. The address computation is the same
1952 * for sources and destinations. */
1953 if (src) {
1954 reg.Register.File = src->Register.File;
1955 reg.Register.Index = src->Register.Index;
1956 reg.Register.Indirect = src->Register.Indirect;
1957 reg.Register.Dimension = src->Register.Dimension;
1958 reg.Indirect = src->Indirect;
1959 reg.Dimension = src->Dimension;
1960 reg.DimIndirect = src->DimIndirect;
1961 } else
1962 reg = *dst;
1963
1964 /* If the register is 2-dimensional (e.g. an array of vertices
1965 * in a primitive), calculate the base address of the vertex. */
1966 if (reg.Register.Dimension) {
1967 int sel, chan;
1968 if (reg.Dimension.Indirect) {
1969 unsigned addr_reg;
1970 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1971
1972 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1973 /* pull the value from index_reg */
1974 sel = addr_reg;
1975 chan = 0;
1976 } else {
1977 sel = V_SQ_ALU_SRC_LITERAL;
1978 chan = reg.Dimension.Index;
1979 }
1980
1981 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1982 temp_reg, 0,
1983 stride_bytes_reg, stride_bytes_chan,
1984 sel, chan,
1985 temp_reg, 0);
1986 if (r)
1987 return r;
1988 }
1989
1990 if (reg.Register.File == TGSI_FILE_INPUT) {
1991 name = info->input_semantic_name;
1992 index = info->input_semantic_index;
1993 array_first = info->input_array_first;
1994 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1995 name = info->output_semantic_name;
1996 index = info->output_semantic_index;
1997 array_first = info->output_array_first;
1998 } else {
1999 assert(0);
2000 return -1;
2001 }
2002 if (reg.Register.Indirect) {
2003 int addr_reg;
2004 int first;
2005 /* Add the relative address of the element. */
2006 if (reg.Indirect.ArrayID)
2007 first = array_first[reg.Indirect.ArrayID];
2008 else
2009 first = reg.Register.Index;
2010
2011 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
2012
2013 /* pull the value from index_reg */
2014 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2015 temp_reg, 0,
2016 V_SQ_ALU_SRC_LITERAL, 16,
2017 addr_reg, 0,
2018 temp_reg, 0);
2019 if (r)
2020 return r;
2021
2022 param = r600_get_lds_unique_index(name[first],
2023 index[first]);
2024
2025 } else {
2026 param = r600_get_lds_unique_index(name[reg.Register.Index],
2027 index[reg.Register.Index]);
2028 }
2029
2030 /* add to base_addr - passed in temp_reg.x */
2031 if (param) {
2032 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2033 temp_reg, 0,
2034 temp_reg, 0,
2035 V_SQ_ALU_SRC_LITERAL, param * 16);
2036 if (r)
2037 return r;
2038
2039 }
2040 return 0;
2041 }
2042
2043 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
2044 unsigned dst_reg, unsigned mask)
2045 {
2046 struct r600_bytecode_alu alu;
2047 int r, i, lasti;
2048
2049 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
2050 ctx->bc->force_add_cf = 1;
2051
2052 lasti = tgsi_last_instruction(mask);
2053 for (i = 1; i <= lasti; i++) {
2054 if (!(mask & (1 << i)))
2055 continue;
2056
2057 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2058 temp_reg, i,
2059 temp_reg, 0,
2060 V_SQ_ALU_SRC_LITERAL, 4 * i);
2061 if (r)
2062 return r;
2063 }
2064 for (i = 0; i <= lasti; i++) {
2065 if (!(mask & (1 << i)))
2066 continue;
2067
2068 /* emit an LDS_READ_RET */
2069 memset(&alu, 0, sizeof(alu));
2070 alu.op = LDS_OP1_LDS_READ_RET;
2071 alu.src[0].sel = temp_reg;
2072 alu.src[0].chan = i;
2073 alu.src[1].sel = V_SQ_ALU_SRC_0;
2074 alu.src[2].sel = V_SQ_ALU_SRC_0;
2075 alu.dst.chan = 0;
2076 alu.is_lds_idx_op = true;
2077 alu.last = 1;
2078 r = r600_bytecode_add_alu(ctx->bc, &alu);
2079 if (r)
2080 return r;
2081 }
2082 for (i = 0; i <= lasti; i++) {
2083 if (!(mask & (1 << i)))
2084 continue;
2085
2086 /* then read from LDS_OQ_A_POP */
2087 memset(&alu, 0, sizeof(alu));
2088
2089 alu.op = ALU_OP1_MOV;
2090 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
2091 alu.src[0].chan = 0;
2092 alu.dst.sel = dst_reg;
2093 alu.dst.chan = i;
2094 alu.dst.write = 1;
2095 alu.last = 1;
2096 r = r600_bytecode_add_alu(ctx->bc, &alu);
2097 if (r)
2098 return r;
2099 }
2100 return 0;
2101 }
2102
2103 static int fetch_mask(struct tgsi_src_register *reg)
2104 {
2105 int mask = 0;
2106 mask |= 1 << reg->SwizzleX;
2107 mask |= 1 << reg->SwizzleY;
2108 mask |= 1 << reg->SwizzleZ;
2109 mask |= 1 << reg->SwizzleW;
2110 return mask;
2111 }
2112
2113 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
2114 {
2115 int r;
2116 unsigned temp_reg = r600_get_temp(ctx);
2117
2118 r = get_lds_offset0(ctx, 2, temp_reg,
2119 src->Register.Dimension ? false : true);
2120 if (r)
2121 return r;
2122
2123 /* the base address is now in temp.x */
2124 r = r600_get_byte_address(ctx, temp_reg,
2125 NULL, src, ctx->tess_output_info, 1);
2126 if (r)
2127 return r;
2128
2129 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
2130 if (r)
2131 return r;
2132 return 0;
2133 }
2134
2135 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
2136 {
2137 int r;
2138 unsigned temp_reg = r600_get_temp(ctx);
2139
2140 /* t.x = ips * r0.y */
2141 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2142 temp_reg, 0,
2143 ctx->tess_input_info, 0,
2144 0, 1);
2145
2146 if (r)
2147 return r;
2148
2149 /* the base address is now in temp.x */
2150 r = r600_get_byte_address(ctx, temp_reg,
2151 NULL, src, ctx->tess_input_info, 1);
2152 if (r)
2153 return r;
2154
2155 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
2156 if (r)
2157 return r;
2158 return 0;
2159 }
2160
2161 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
2162 {
2163 int r;
2164 unsigned temp_reg = r600_get_temp(ctx);
2165
2166 r = get_lds_offset0(ctx, 1, temp_reg,
2167 src->Register.Dimension ? false : true);
2168 if (r)
2169 return r;
2170 /* the base address is now in temp.x */
2171 r = r600_get_byte_address(ctx, temp_reg,
2172 NULL, src,
2173 ctx->tess_output_info, 1);
2174 if (r)
2175 return r;
2176
2177 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
2178 if (r)
2179 return r;
2180 return 0;
2181 }
2182
2183 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
2184 {
2185 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2186 unsigned i;
2187
2188 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2189 struct tgsi_full_src_register *src = &inst->Src[i];
2190
2191 if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
2192 int treg = r600_get_temp(ctx);
2193 fetch_tes_input(ctx, src, treg);
2194 ctx->src[i].sel = treg;
2195 ctx->src[i].rel = 0;
2196 }
2197 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
2198 int treg = r600_get_temp(ctx);
2199 fetch_tcs_input(ctx, src, treg);
2200 ctx->src[i].sel = treg;
2201 ctx->src[i].rel = 0;
2202 }
2203 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
2204 int treg = r600_get_temp(ctx);
2205 fetch_tcs_output(ctx, src, treg);
2206 ctx->src[i].sel = treg;
2207 ctx->src[i].rel = 0;
2208 }
2209 }
2210 return 0;
2211 }
2212
2213 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
2214 {
2215 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2216 struct r600_bytecode_alu alu;
2217 int i, j, k, nconst, r;
2218
2219 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
2220 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
2221 nconst++;
2222 }
2223 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
2224 }
2225 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
2226 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
2227 continue;
2228 }
2229
2230 if (ctx->src[i].rel) {
2231 int chan = inst->Src[i].Indirect.Swizzle;
2232 int treg = r600_get_temp(ctx);
2233 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
2234 return r;
2235
2236 ctx->src[i].kc_bank = 0;
2237 ctx->src[i].kc_rel = 0;
2238 ctx->src[i].sel = treg;
2239 ctx->src[i].rel = 0;
2240 j--;
2241 } else if (j > 0) {
2242 int treg = r600_get_temp(ctx);
2243 for (k = 0; k < 4; k++) {
2244 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2245 alu.op = ALU_OP1_MOV;
2246 alu.src[0].sel = ctx->src[i].sel;
2247 alu.src[0].chan = k;
2248 alu.src[0].rel = ctx->src[i].rel;
2249 alu.src[0].kc_bank = ctx->src[i].kc_bank;
2250 alu.src[0].kc_rel = ctx->src[i].kc_rel;
2251 alu.dst.sel = treg;
2252 alu.dst.chan = k;
2253 alu.dst.write = 1;
2254 if (k == 3)
2255 alu.last = 1;
2256 r = r600_bytecode_add_alu(ctx->bc, &alu);
2257 if (r)
2258 return r;
2259 }
2260 ctx->src[i].sel = treg;
2261 ctx->src[i].rel =0;
2262 j--;
2263 }
2264 }
2265 return 0;
2266 }
2267
2268 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
2269 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
2270 {
2271 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2272 struct r600_bytecode_alu alu;
2273 int i, j, k, nliteral, r;
2274
2275 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
2276 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
2277 nliteral++;
2278 }
2279 }
2280 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
2281 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
2282 int treg = r600_get_temp(ctx);
2283 for (k = 0; k < 4; k++) {
2284 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2285 alu.op = ALU_OP1_MOV;
2286 alu.src[0].sel = ctx->src[i].sel;
2287 alu.src[0].chan = k;
2288 alu.src[0].value = ctx->src[i].value[k];
2289 alu.dst.sel = treg;
2290 alu.dst.chan = k;
2291 alu.dst.write = 1;
2292 if (k == 3)
2293 alu.last = 1;
2294 r = r600_bytecode_add_alu(ctx->bc, &alu);
2295 if (r)
2296 return r;
2297 }
2298 ctx->src[i].sel = treg;
2299 j--;
2300 }
2301 }
2302 return 0;
2303 }
2304
2305 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
2306 {
2307 int i, r, count = ctx->shader->ninput;
2308
2309 for (i = 0; i < count; i++) {
2310 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
2311 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
2312 if (r)
2313 return r;
2314 }
2315 }
2316 return 0;
2317 }
2318
2319 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
2320 int stream, unsigned *stream_item_size UNUSED)
2321 {
2322 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
2323 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
2324 int j, r;
2325 unsigned i;
2326
2327 /* Sanity checking. */
2328 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
2329 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
2330 r = -EINVAL;
2331 goto out_err;
2332 }
2333 for (i = 0; i < so->num_outputs; i++) {
2334 if (so->output[i].output_buffer >= 4) {
2335 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2336 so->output[i].output_buffer);
2337 r = -EINVAL;
2338 goto out_err;
2339 }
2340 }
2341
2342 /* Initialize locations where the outputs are stored. */
2343 for (i = 0; i < so->num_outputs; i++) {
2344
2345 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2346 start_comp[i] = so->output[i].start_component;
2347 /* Lower outputs with dst_offset < start_component.
2348 *
2349 * We can only output 4D vectors with a write mask, e.g. we can
2350 * only output the W component at offset 3, etc. If we want
2351 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2352 * to move it to X and output X. */
2353 if (so->output[i].dst_offset < so->output[i].start_component) {
2354 unsigned tmp = r600_get_temp(ctx);
2355
2356 for (j = 0; j < so->output[i].num_components; j++) {
2357 struct r600_bytecode_alu alu;
2358 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2359 alu.op = ALU_OP1_MOV;
2360 alu.src[0].sel = so_gpr[i];
2361 alu.src[0].chan = so->output[i].start_component + j;
2362
2363 alu.dst.sel = tmp;
2364 alu.dst.chan = j;
2365 alu.dst.write = 1;
2366 if (j == so->output[i].num_components - 1)
2367 alu.last = 1;
2368 r = r600_bytecode_add_alu(ctx->bc, &alu);
2369 if (r)
2370 return r;
2371 }
2372 start_comp[i] = 0;
2373 so_gpr[i] = tmp;
2374 }
2375 }
2376
2377 /* Write outputs to buffers. */
2378 for (i = 0; i < so->num_outputs; i++) {
2379 struct r600_bytecode_output output;
2380
2381 if (stream != -1 && stream != so->output[i].stream)
2382 continue;
2383
2384 memset(&output, 0, sizeof(struct r600_bytecode_output));
2385 output.gpr = so_gpr[i];
2386 output.elem_size = so->output[i].num_components - 1;
2387 if (output.elem_size == 2)
2388 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2389 output.array_base = so->output[i].dst_offset - start_comp[i];
2390 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2391 output.burst_count = 1;
2392 /* array_size is an upper limit for the burst_count
2393 * with MEM_STREAM instructions */
2394 output.array_size = 0xFFF;
2395 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2396
2397 if (ctx->bc->chip_class >= EVERGREEN) {
2398 switch (so->output[i].output_buffer) {
2399 case 0:
2400 output.op = CF_OP_MEM_STREAM0_BUF0;
2401 break;
2402 case 1:
2403 output.op = CF_OP_MEM_STREAM0_BUF1;
2404 break;
2405 case 2:
2406 output.op = CF_OP_MEM_STREAM0_BUF2;
2407 break;
2408 case 3:
2409 output.op = CF_OP_MEM_STREAM0_BUF3;
2410 break;
2411 }
2412 output.op += so->output[i].stream * 4;
2413 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2414 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2415 } else {
2416 switch (so->output[i].output_buffer) {
2417 case 0:
2418 output.op = CF_OP_MEM_STREAM0;
2419 break;
2420 case 1:
2421 output.op = CF_OP_MEM_STREAM1;
2422 break;
2423 case 2:
2424 output.op = CF_OP_MEM_STREAM2;
2425 break;
2426 case 3:
2427 output.op = CF_OP_MEM_STREAM3;
2428 break;
2429 }
2430 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2431 }
2432 r = r600_bytecode_add_output(ctx->bc, &output);
2433 if (r)
2434 goto out_err;
2435 }
2436 return 0;
2437 out_err:
2438 return r;
2439 }
2440
2441 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2442 {
2443 struct r600_bytecode_alu alu;
2444 unsigned reg;
2445
2446 if (!ctx->shader->vs_out_edgeflag)
2447 return;
2448
2449 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2450
2451 /* clamp(x, 0, 1) */
2452 memset(&alu, 0, sizeof(alu));
2453 alu.op = ALU_OP1_MOV;
2454 alu.src[0].sel = reg;
2455 alu.dst.sel = reg;
2456 alu.dst.write = 1;
2457 alu.dst.clamp = 1;
2458 alu.last = 1;
2459 r600_bytecode_add_alu(ctx->bc, &alu);
2460
2461 memset(&alu, 0, sizeof(alu));
2462 alu.op = ALU_OP1_FLT_TO_INT;
2463 alu.src[0].sel = reg;
2464 alu.dst.sel = reg;
2465 alu.dst.write = 1;
2466 alu.last = 1;
2467 r600_bytecode_add_alu(ctx->bc, &alu);
2468 }
2469
2470 static int generate_gs_copy_shader(struct r600_context *rctx,
2471 struct r600_pipe_shader *gs,
2472 struct pipe_stream_output_info *so)
2473 {
2474 struct r600_shader_ctx ctx = {};
2475 struct r600_shader *gs_shader = &gs->shader;
2476 struct r600_pipe_shader *cshader;
2477 unsigned ocnt = gs_shader->noutput;
2478 struct r600_bytecode_alu alu;
2479 struct r600_bytecode_vtx vtx;
2480 struct r600_bytecode_output output;
2481 struct r600_bytecode_cf *cf_jump, *cf_pop,
2482 *last_exp_pos = NULL, *last_exp_param = NULL;
2483 int next_clip_pos = 61, next_param = 0;
2484 unsigned i, j;
2485 int ring;
2486 bool only_ring_0 = true;
2487 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2488 if (!cshader)
2489 return 0;
2490
2491 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2492 sizeof(struct r600_shader_io));
2493
2494 cshader->shader.noutput = ocnt;
2495
2496 ctx.shader = &cshader->shader;
2497 ctx.bc = &ctx.shader->bc;
2498 ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
2499
2500 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2501 rctx->screen->has_compressed_msaa_texturing);
2502
2503 ctx.bc->isa = rctx->isa;
2504
2505 cf_jump = NULL;
2506 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2507
2508 /* R0.x = R0.x & 0x3fffffff */
2509 memset(&alu, 0, sizeof(alu));
2510 alu.op = ALU_OP2_AND_INT;
2511 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2512 alu.src[1].value = 0x3fffffff;
2513 alu.dst.write = 1;
2514 r600_bytecode_add_alu(ctx.bc, &alu);
2515
2516 /* R0.y = R0.x >> 30 */
2517 memset(&alu, 0, sizeof(alu));
2518 alu.op = ALU_OP2_LSHR_INT;
2519 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2520 alu.src[1].value = 0x1e;
2521 alu.dst.chan = 1;
2522 alu.dst.write = 1;
2523 alu.last = 1;
2524 r600_bytecode_add_alu(ctx.bc, &alu);
2525
2526 /* fetch vertex data from GSVS ring */
2527 for (i = 0; i < ocnt; ++i) {
2528 struct r600_shader_io *out = &ctx.shader->output[i];
2529
2530 out->gpr = i + 1;
2531 out->ring_offset = i * 16;
2532
2533 memset(&vtx, 0, sizeof(vtx));
2534 vtx.op = FETCH_OP_VFETCH;
2535 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2536 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2537 vtx.mega_fetch_count = 16;
2538 vtx.offset = out->ring_offset;
2539 vtx.dst_gpr = out->gpr;
2540 vtx.src_gpr = 0;
2541 vtx.dst_sel_x = 0;
2542 vtx.dst_sel_y = 1;
2543 vtx.dst_sel_z = 2;
2544 vtx.dst_sel_w = 3;
2545 if (rctx->b.chip_class >= EVERGREEN) {
2546 vtx.use_const_fields = 1;
2547 } else {
2548 vtx.data_format = FMT_32_32_32_32_FLOAT;
2549 }
2550
2551 r600_bytecode_add_vtx(ctx.bc, &vtx);
2552 }
2553 ctx.temp_reg = i + 1;
2554 for (ring = 3; ring >= 0; --ring) {
2555 bool enabled = false;
2556 for (i = 0; i < so->num_outputs; i++) {
2557 if (so->output[i].stream == ring) {
2558 enabled = true;
2559 if (ring > 0)
2560 only_ring_0 = false;
2561 break;
2562 }
2563 }
2564 if (ring != 0 && !enabled) {
2565 cshader->shader.ring_item_sizes[ring] = 0;
2566 continue;
2567 }
2568
2569 if (cf_jump) {
2570 // Patch up jump label
2571 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2572 cf_pop = ctx.bc->cf_last;
2573
2574 cf_jump->cf_addr = cf_pop->id + 2;
2575 cf_jump->pop_count = 1;
2576 cf_pop->cf_addr = cf_pop->id + 2;
2577 cf_pop->pop_count = 1;
2578 }
2579
2580 /* PRED_SETE_INT __, R0.y, ring */
2581 memset(&alu, 0, sizeof(alu));
2582 alu.op = ALU_OP2_PRED_SETE_INT;
2583 alu.src[0].chan = 1;
2584 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2585 alu.src[1].value = ring;
2586 alu.execute_mask = 1;
2587 alu.update_pred = 1;
2588 alu.last = 1;
2589 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2590
2591 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2592 cf_jump = ctx.bc->cf_last;
2593
2594 if (enabled)
2595 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2596 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2597 }
2598
2599 /* bc adds nops - copy it */
2600 if (ctx.bc->chip_class == R600) {
2601 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2602 alu.op = ALU_OP0_NOP;
2603 alu.last = 1;
2604 r600_bytecode_add_alu(ctx.bc, &alu);
2605
2606 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2607 }
2608
2609 /* export vertex data */
2610 /* XXX factor out common code with r600_shader_from_tgsi ? */
2611 for (i = 0; i < ocnt; ++i) {
2612 struct r600_shader_io *out = &ctx.shader->output[i];
2613 bool instream0 = true;
2614 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2615 continue;
2616
2617 for (j = 0; j < so->num_outputs; j++) {
2618 if (so->output[j].register_index == i) {
2619 if (so->output[j].stream == 0)
2620 break;
2621 if (so->output[j].stream > 0)
2622 instream0 = false;
2623 }
2624 }
2625 if (!instream0)
2626 continue;
2627 memset(&output, 0, sizeof(output));
2628 output.gpr = out->gpr;
2629 output.elem_size = 3;
2630 output.swizzle_x = 0;
2631 output.swizzle_y = 1;
2632 output.swizzle_z = 2;
2633 output.swizzle_w = 3;
2634 output.burst_count = 1;
2635 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2636 output.op = CF_OP_EXPORT;
2637 switch (out->name) {
2638 case TGSI_SEMANTIC_POSITION:
2639 output.array_base = 60;
2640 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2641 break;
2642
2643 case TGSI_SEMANTIC_PSIZE:
2644 output.array_base = 61;
2645 if (next_clip_pos == 61)
2646 next_clip_pos = 62;
2647 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2648 output.swizzle_y = 7;
2649 output.swizzle_z = 7;
2650 output.swizzle_w = 7;
2651 ctx.shader->vs_out_misc_write = 1;
2652 ctx.shader->vs_out_point_size = 1;
2653 break;
2654 case TGSI_SEMANTIC_LAYER:
2655 if (out->spi_sid) {
2656 /* duplicate it as PARAM to pass to the pixel shader */
2657 output.array_base = next_param++;
2658 r600_bytecode_add_output(ctx.bc, &output);
2659 last_exp_param = ctx.bc->cf_last;
2660 }
2661 output.array_base = 61;
2662 if (next_clip_pos == 61)
2663 next_clip_pos = 62;
2664 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2665 output.swizzle_x = 7;
2666 output.swizzle_y = 7;
2667 output.swizzle_z = 0;
2668 output.swizzle_w = 7;
2669 ctx.shader->vs_out_misc_write = 1;
2670 ctx.shader->vs_out_layer = 1;
2671 break;
2672 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2673 if (out->spi_sid) {
2674 /* duplicate it as PARAM to pass to the pixel shader */
2675 output.array_base = next_param++;
2676 r600_bytecode_add_output(ctx.bc, &output);
2677 last_exp_param = ctx.bc->cf_last;
2678 }
2679 output.array_base = 61;
2680 if (next_clip_pos == 61)
2681 next_clip_pos = 62;
2682 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2683 ctx.shader->vs_out_misc_write = 1;
2684 ctx.shader->vs_out_viewport = 1;
2685 output.swizzle_x = 7;
2686 output.swizzle_y = 7;
2687 output.swizzle_z = 7;
2688 output.swizzle_w = 0;
2689 break;
2690 case TGSI_SEMANTIC_CLIPDIST:
2691 /* spi_sid is 0 for clipdistance outputs that were generated
2692 * for clipvertex - we don't need to pass them to PS */
2693 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2694 ctx.shader->cull_dist_write = gs->shader.cull_dist_write;
2695 ctx.shader->cc_dist_mask = gs->shader.cc_dist_mask;
2696 if (out->spi_sid) {
2697 /* duplicate it as PARAM to pass to the pixel shader */
2698 output.array_base = next_param++;
2699 r600_bytecode_add_output(ctx.bc, &output);
2700 last_exp_param = ctx.bc->cf_last;
2701 }
2702 output.array_base = next_clip_pos++;
2703 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2704 break;
2705 case TGSI_SEMANTIC_FOG:
2706 output.swizzle_y = 4; /* 0 */
2707 output.swizzle_z = 4; /* 0 */
2708 output.swizzle_w = 5; /* 1 */
2709 break;
2710 default:
2711 output.array_base = next_param++;
2712 break;
2713 }
2714 r600_bytecode_add_output(ctx.bc, &output);
2715 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2716 last_exp_param = ctx.bc->cf_last;
2717 else
2718 last_exp_pos = ctx.bc->cf_last;
2719 }
2720
2721 if (!last_exp_pos) {
2722 memset(&output, 0, sizeof(output));
2723 output.gpr = 0;
2724 output.elem_size = 3;
2725 output.swizzle_x = 7;
2726 output.swizzle_y = 7;
2727 output.swizzle_z = 7;
2728 output.swizzle_w = 7;
2729 output.burst_count = 1;
2730 output.type = 2;
2731 output.op = CF_OP_EXPORT;
2732 output.array_base = 60;
2733 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2734 r600_bytecode_add_output(ctx.bc, &output);
2735 last_exp_pos = ctx.bc->cf_last;
2736 }
2737
2738 if (!last_exp_param) {
2739 memset(&output, 0, sizeof(output));
2740 output.gpr = 0;
2741 output.elem_size = 3;
2742 output.swizzle_x = 7;
2743 output.swizzle_y = 7;
2744 output.swizzle_z = 7;
2745 output.swizzle_w = 7;
2746 output.burst_count = 1;
2747 output.type = 2;
2748 output.op = CF_OP_EXPORT;
2749 output.array_base = next_param++;
2750 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2751 r600_bytecode_add_output(ctx.bc, &output);
2752 last_exp_param = ctx.bc->cf_last;
2753 }
2754
2755 last_exp_pos->op = CF_OP_EXPORT_DONE;
2756 last_exp_param->op = CF_OP_EXPORT_DONE;
2757
2758 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2759 cf_pop = ctx.bc->cf_last;
2760
2761 cf_jump->cf_addr = cf_pop->id + 2;
2762 cf_jump->pop_count = 1;
2763 cf_pop->cf_addr = cf_pop->id + 2;
2764 cf_pop->pop_count = 1;
2765
2766 if (ctx.bc->chip_class == CAYMAN)
2767 cm_bytecode_add_cf_end(ctx.bc);
2768 else {
2769 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2770 ctx.bc->cf_last->end_of_program = 1;
2771 }
2772
2773 gs->gs_copy_shader = cshader;
2774 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2775
2776 ctx.bc->nstack = 1;
2777
2778 return r600_bytecode_build(ctx.bc);
2779 }
2780
2781 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2782 {
2783 if (ind) {
2784 struct r600_bytecode_alu alu;
2785 int r;
2786
2787 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2788 alu.op = ALU_OP2_ADD_INT;
2789 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2790 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2791 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2792 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2793 alu.dst.write = 1;
2794 alu.last = 1;
2795 r = r600_bytecode_add_alu(ctx->bc, &alu);
2796 if (r)
2797 return r;
2798 }
2799 return 0;
2800 }
2801
2802 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so UNUSED, int stream, bool ind)
2803 {
2804 struct r600_bytecode_output output;
2805 int ring_offset;
2806 unsigned i, k;
2807 int effective_stream = stream == -1 ? 0 : stream;
2808 int idx = 0;
2809
2810 for (i = 0; i < ctx->shader->noutput; i++) {
2811 if (ctx->gs_for_vs) {
2812 /* for ES we need to lookup corresponding ring offset expected by GS
2813 * (map this output to GS input by name and sid) */
2814 /* FIXME precompute offsets */
2815 ring_offset = -1;
2816 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2817 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2818 struct r600_shader_io *out = &ctx->shader->output[i];
2819 if (in->name == out->name && in->sid == out->sid)
2820 ring_offset = in->ring_offset;
2821 }
2822
2823 if (ring_offset == -1)
2824 continue;
2825 } else {
2826 ring_offset = idx * 16;
2827 idx++;
2828 }
2829
2830 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2831 continue;
2832 /* next_ring_offset after parsing input decls contains total size of
2833 * single vertex data, gs_next_vertex - current vertex index */
2834 if (!ind)
2835 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2836
2837 memset(&output, 0, sizeof(struct r600_bytecode_output));
2838 output.gpr = ctx->shader->output[i].gpr;
2839 output.elem_size = 3;
2840 output.comp_mask = 0xF;
2841 output.burst_count = 1;
2842
2843 if (ind)
2844 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2845 else
2846 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2847
2848 switch (stream) {
2849 default:
2850 case 0:
2851 output.op = CF_OP_MEM_RING; break;
2852 case 1:
2853 output.op = CF_OP_MEM_RING1; break;
2854 case 2:
2855 output.op = CF_OP_MEM_RING2; break;
2856 case 3:
2857 output.op = CF_OP_MEM_RING3; break;
2858 }
2859
2860 if (ind) {
2861 output.array_base = ring_offset >> 2; /* in dwords */
2862 output.array_size = 0xfff;
2863 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2864 } else
2865 output.array_base = ring_offset >> 2; /* in dwords */
2866 r600_bytecode_add_output(ctx->bc, &output);
2867 }
2868
2869 ++ctx->gs_next_vertex;
2870 return 0;
2871 }
2872
2873
2874 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2875 {
2876 int r;
2877 struct r600_bytecode_vtx vtx;
2878 int temp_val = ctx->temp_reg;
2879 /* need to store the TCS output somewhere */
2880 r = single_alu_op2(ctx, ALU_OP1_MOV,
2881 temp_val, 0,
2882 V_SQ_ALU_SRC_LITERAL, 0,
2883 0, 0);
2884 if (r)
2885 return r;
2886
2887 /* used by VS/TCS */
2888 if (ctx->tess_input_info) {
2889 /* fetch tcs input values into resv space */
2890 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2891 vtx.op = FETCH_OP_VFETCH;
2892 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2893 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2894 vtx.mega_fetch_count = 16;
2895 vtx.data_format = FMT_32_32_32_32;
2896 vtx.num_format_all = 2;
2897 vtx.format_comp_all = 1;
2898 vtx.use_const_fields = 0;
2899 vtx.endian = r600_endian_swap(32);
2900 vtx.srf_mode_all = 1;
2901 vtx.offset = 0;
2902 vtx.dst_gpr = ctx->tess_input_info;
2903 vtx.dst_sel_x = 0;
2904 vtx.dst_sel_y = 1;
2905 vtx.dst_sel_z = 2;
2906 vtx.dst_sel_w = 3;
2907 vtx.src_gpr = temp_val;
2908 vtx.src_sel_x = 0;
2909
2910 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2911 if (r)
2912 return r;
2913 }
2914
2915 /* used by TCS/TES */
2916 if (ctx->tess_output_info) {
2917 /* fetch tcs output values into resv space */
2918 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2919 vtx.op = FETCH_OP_VFETCH;
2920 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2921 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2922 vtx.mega_fetch_count = 16;
2923 vtx.data_format = FMT_32_32_32_32;
2924 vtx.num_format_all = 2;
2925 vtx.format_comp_all = 1;
2926 vtx.use_const_fields = 0;
2927 vtx.endian = r600_endian_swap(32);
2928 vtx.srf_mode_all = 1;
2929 vtx.offset = 16;
2930 vtx.dst_gpr = ctx->tess_output_info;
2931 vtx.dst_sel_x = 0;
2932 vtx.dst_sel_y = 1;
2933 vtx.dst_sel_z = 2;
2934 vtx.dst_sel_w = 3;
2935 vtx.src_gpr = temp_val;
2936 vtx.src_sel_x = 0;
2937
2938 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2939 if (r)
2940 return r;
2941 }
2942 return 0;
2943 }
2944
2945 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2946 {
2947 int j, r;
2948 int temp_reg;
2949 unsigned i;
2950
2951 /* fetch tcs input values into input_vals */
2952 ctx->tess_input_info = r600_get_temp(ctx);
2953 ctx->tess_output_info = 0;
2954 r = r600_fetch_tess_io_info(ctx);
2955 if (r)
2956 return r;
2957
2958 temp_reg = r600_get_temp(ctx);
2959 /* dst reg contains LDS address stride * idx */
2960 /* MUL vertexID, vertex_dw_stride */
2961 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2962 temp_reg, 0,
2963 ctx->tess_input_info, 1,
2964 0, 1); /* rel id in r0.y? */
2965 if (r)
2966 return r;
2967
2968 for (i = 0; i < ctx->shader->noutput; i++) {
2969 struct r600_bytecode_alu alu;
2970 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2971
2972 if (param) {
2973 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2974 temp_reg, 1,
2975 temp_reg, 0,
2976 V_SQ_ALU_SRC_LITERAL, param * 16);
2977 if (r)
2978 return r;
2979 }
2980
2981 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2982 temp_reg, 2,
2983 temp_reg, param ? 1 : 0,
2984 V_SQ_ALU_SRC_LITERAL, 8);
2985 if (r)
2986 return r;
2987
2988
2989 for (j = 0; j < 2; j++) {
2990 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2991 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2992 alu.op = LDS_OP3_LDS_WRITE_REL;
2993 alu.src[0].sel = temp_reg;
2994 alu.src[0].chan = chan;
2995 alu.src[1].sel = ctx->shader->output[i].gpr;
2996 alu.src[1].chan = j * 2;
2997 alu.src[2].sel = ctx->shader->output[i].gpr;
2998 alu.src[2].chan = (j * 2) + 1;
2999 alu.last = 1;
3000 alu.dst.chan = 0;
3001 alu.lds_idx = 1;
3002 alu.is_lds_idx_op = true;
3003 r = r600_bytecode_add_alu(ctx->bc, &alu);
3004 if (r)
3005 return r;
3006 }
3007 }
3008 return 0;
3009 }
3010
3011 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
3012 {
3013 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3014 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
3015 int i, r, lasti;
3016 int temp_reg = r600_get_temp(ctx);
3017 struct r600_bytecode_alu alu;
3018 unsigned write_mask = dst->Register.WriteMask;
3019
3020 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
3021 return 0;
3022
3023 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
3024 if (r)
3025 return r;
3026
3027 /* the base address is now in temp.x */
3028 r = r600_get_byte_address(ctx, temp_reg,
3029 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
3030 if (r)
3031 return r;
3032
3033 /* LDS write */
3034 lasti = tgsi_last_instruction(write_mask);
3035 for (i = 1; i <= lasti; i++) {
3036
3037 if (!(write_mask & (1 << i)))
3038 continue;
3039 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
3040 temp_reg, i,
3041 temp_reg, 0,
3042 V_SQ_ALU_SRC_LITERAL, 4 * i);
3043 if (r)
3044 return r;
3045 }
3046
3047 for (i = 0; i <= lasti; i++) {
3048 if (!(write_mask & (1 << i)))
3049 continue;
3050
3051 if ((i == 0 && ((write_mask & 3) == 3)) ||
3052 (i == 2 && ((write_mask & 0xc) == 0xc))) {
3053 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3054 alu.op = LDS_OP3_LDS_WRITE_REL;
3055 alu.src[0].sel = temp_reg;
3056 alu.src[0].chan = i;
3057
3058 alu.src[1].sel = dst->Register.Index;
3059 alu.src[1].sel += ctx->file_offset[dst->Register.File];
3060 alu.src[1].chan = i;
3061
3062 alu.src[2].sel = dst->Register.Index;
3063 alu.src[2].sel += ctx->file_offset[dst->Register.File];
3064 alu.src[2].chan = i + 1;
3065 alu.lds_idx = 1;
3066 alu.dst.chan = 0;
3067 alu.last = 1;
3068 alu.is_lds_idx_op = true;
3069 r = r600_bytecode_add_alu(ctx->bc, &alu);
3070 if (r)
3071 return r;
3072 i += 1;
3073 continue;
3074 }
3075 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3076 alu.op = LDS_OP2_LDS_WRITE;
3077 alu.src[0].sel = temp_reg;
3078 alu.src[0].chan = i;
3079
3080 alu.src[1].sel = dst->Register.Index;
3081 alu.src[1].sel += ctx->file_offset[dst->Register.File];
3082 alu.src[1].chan = i;
3083
3084 alu.src[2].sel = V_SQ_ALU_SRC_0;
3085 alu.dst.chan = 0;
3086 alu.last = 1;
3087 alu.is_lds_idx_op = true;
3088 r = r600_bytecode_add_alu(ctx->bc, &alu);
3089 if (r)
3090 return r;
3091 }
3092 return 0;
3093 }
3094
3095 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
3096 int output_idx, int nc)
3097 {
3098 int param;
3099 unsigned temp_reg = r600_get_temp(ctx);
3100 unsigned name = ctx->shader->output[output_idx].name;
3101 int dreg = ctx->shader->output[output_idx].gpr;
3102 int r;
3103
3104 param = r600_get_lds_unique_index(name, 0);
3105 r = get_lds_offset0(ctx, 1, temp_reg, true);
3106 if (r)
3107 return r;
3108
3109 if (param) {
3110 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
3111 temp_reg, 0,
3112 temp_reg, 0,
3113 V_SQ_ALU_SRC_LITERAL, param * 16);
3114 if (r)
3115 return r;
3116 }
3117
3118 do_lds_fetch_values(ctx, temp_reg, dreg, ((1u << nc) - 1));
3119 return 0;
3120 }
3121
3122 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
3123 {
3124 int stride, outer_comps, inner_comps;
3125 int tessinner_idx = -1, tessouter_idx = -1;
3126 int i, r;
3127 unsigned j;
3128 int temp_reg = r600_get_temp(ctx);
3129 int treg[3] = {-1, -1, -1};
3130 struct r600_bytecode_alu alu;
3131 struct r600_bytecode_cf *cf_jump, *cf_pop;
3132
3133 /* only execute factor emission for invocation 0 */
3134 /* PRED_SETE_INT __, R0.x, 0 */
3135 memset(&alu, 0, sizeof(alu));
3136 alu.op = ALU_OP2_PRED_SETE_INT;
3137 alu.src[0].chan = 2;
3138 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3139 alu.execute_mask = 1;
3140 alu.update_pred = 1;
3141 alu.last = 1;
3142 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
3143
3144 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
3145 cf_jump = ctx->bc->cf_last;
3146
3147 treg[0] = r600_get_temp(ctx);
3148 switch (ctx->shader->tcs_prim_mode) {
3149 case PIPE_PRIM_LINES:
3150 stride = 8; /* 2 dwords, 1 vec2 store */
3151 outer_comps = 2;
3152 inner_comps = 0;
3153 break;
3154 case PIPE_PRIM_TRIANGLES:
3155 stride = 16; /* 4 dwords, 1 vec4 store */
3156 outer_comps = 3;
3157 inner_comps = 1;
3158 treg[1] = r600_get_temp(ctx);
3159 break;
3160 case PIPE_PRIM_QUADS:
3161 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
3162 outer_comps = 4;
3163 inner_comps = 2;
3164 treg[1] = r600_get_temp(ctx);
3165 treg[2] = r600_get_temp(ctx);
3166 break;
3167 default:
3168 assert(0);
3169 return -1;
3170 }
3171
3172 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
3173 /* TF_WRITE takes index in R.x, value in R.y */
3174 for (j = 0; j < ctx->shader->noutput; j++) {
3175 if (ctx->shader->output[j].name == TGSI_SEMANTIC_TESSINNER)
3176 tessinner_idx = j;
3177 if (ctx->shader->output[j].name == TGSI_SEMANTIC_TESSOUTER)
3178 tessouter_idx = j;
3179 }
3180
3181 if (tessouter_idx == -1)
3182 return -1;
3183
3184 if (tessinner_idx == -1 && inner_comps)
3185 return -1;
3186
3187 if (tessouter_idx != -1) {
3188 r = r600_tess_factor_read(ctx, tessouter_idx, outer_comps);
3189 if (r)
3190 return r;
3191 }
3192
3193 if (tessinner_idx != -1) {
3194 r = r600_tess_factor_read(ctx, tessinner_idx, inner_comps);
3195 if (r)
3196 return r;
3197 }
3198
3199 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
3200 /* r.x = relpatchid(r0.y) * tf_stride */
3201
3202 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
3203 /* add incoming r0.w to it: t.x = t.x + r0.w */
3204 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
3205 temp_reg, 0,
3206 0, 1,
3207 V_SQ_ALU_SRC_LITERAL, stride,
3208 0, 3);
3209 if (r)
3210 return r;
3211
3212 for (i = 0; i < outer_comps + inner_comps; i++) {
3213 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
3214 int out_comp = i >= outer_comps ? i - outer_comps : i;
3215
3216 if (ctx->shader->tcs_prim_mode == PIPE_PRIM_LINES) {
3217 if (out_comp == 1)
3218 out_comp = 0;
3219 else if (out_comp == 0)
3220 out_comp = 1;
3221 }
3222
3223 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
3224 treg[i / 2], (2 * (i % 2)),
3225 temp_reg, 0,
3226 V_SQ_ALU_SRC_LITERAL, 4 * i);
3227 if (r)
3228 return r;
3229 r = single_alu_op2(ctx, ALU_OP1_MOV,
3230 treg[i / 2], 1 + (2 * (i%2)),
3231 ctx->shader->output[out_idx].gpr, out_comp,
3232 0, 0);
3233 if (r)
3234 return r;
3235 }
3236 for (i = 0; i < outer_comps + inner_comps; i++) {
3237 struct r600_bytecode_gds gds;
3238
3239 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
3240 gds.src_gpr = treg[i / 2];
3241 gds.src_sel_x = 2 * (i % 2);
3242 gds.src_sel_y = 1 + (2 * (i % 2));
3243 gds.src_sel_z = 4;
3244 gds.dst_sel_x = 7;
3245 gds.dst_sel_y = 7;
3246 gds.dst_sel_z = 7;
3247 gds.dst_sel_w = 7;
3248 gds.op = FETCH_OP_TF_WRITE;
3249 r = r600_bytecode_add_gds(ctx->bc, &gds);
3250 if (r)
3251 return r;
3252 }
3253
3254 // Patch up jump label
3255 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
3256 cf_pop = ctx->bc->cf_last;
3257
3258 cf_jump->cf_addr = cf_pop->id + 2;
3259 cf_jump->pop_count = 1;
3260 cf_pop->cf_addr = cf_pop->id + 2;
3261 cf_pop->pop_count = 1;
3262
3263 return 0;
3264 }
3265
3266 /*
3267 * We have to work out the thread ID for load and atomic
3268 * operations, which store the returned value to an index
3269 * in an intermediate buffer.
3270 * The index is calculated by taking the thread id,
3271 * calculated from the MBCNT instructions.
3272 * Then the shader engine ID is multiplied by 256,
3273 * and the wave id is added.
3274 * Then the result is multipled by 64 and thread id is
3275 * added.
3276 */
3277 static int load_thread_id_gpr(struct r600_shader_ctx *ctx)
3278 {
3279 struct r600_bytecode_alu alu;
3280 int r;
3281
3282 if (ctx->thread_id_gpr_loaded)
3283 return 0;
3284
3285 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3286 alu.op = ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT;
3287 alu.dst.sel = ctx->temp_reg;
3288 alu.dst.chan = 0;
3289 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3290 alu.src[0].value = 0xffffffff;
3291 alu.dst.write = 1;
3292 r = r600_bytecode_add_alu(ctx->bc, &alu);
3293 if (r)
3294 return r;
3295
3296 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3297 alu.op = ALU_OP1_MBCNT_32HI_INT;
3298 alu.dst.sel = ctx->temp_reg;
3299 alu.dst.chan = 1;
3300 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3301 alu.src[0].value = 0xffffffff;
3302 alu.dst.write = 1;
3303 r = r600_bytecode_add_alu(ctx->bc, &alu);
3304 if (r)
3305 return r;
3306
3307 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3308 alu.op = ALU_OP3_MULADD_UINT24;
3309 alu.dst.sel = ctx->temp_reg;
3310 alu.dst.chan = 2;
3311 alu.src[0].sel = EG_V_SQ_ALU_SRC_SE_ID;
3312 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3313 alu.src[1].value = 256;
3314 alu.src[2].sel = EG_V_SQ_ALU_SRC_HW_WAVE_ID;
3315 alu.dst.write = 1;
3316 alu.is_op3 = 1;
3317 alu.last = 1;
3318 r = r600_bytecode_add_alu(ctx->bc, &alu);
3319 if (r)
3320 return r;
3321
3322 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
3323 ctx->thread_id_gpr, 1,
3324 ctx->temp_reg, 2,
3325 V_SQ_ALU_SRC_LITERAL, 0x40,
3326 ctx->temp_reg, 0);
3327 if (r)
3328 return r;
3329 ctx->thread_id_gpr_loaded = true;
3330 return 0;
3331 }
3332
3333 static int r600_shader_from_tgsi(struct r600_context *rctx,
3334 struct r600_pipe_shader *pipeshader,
3335 union r600_shader_key key)
3336 {
3337 struct r600_screen *rscreen = rctx->screen;
3338 struct r600_shader *shader = &pipeshader->shader;
3339 struct tgsi_token *tokens = pipeshader->selector->tokens;
3340 struct pipe_stream_output_info so = pipeshader->selector->so;
3341 struct tgsi_full_immediate *immediate;
3342 struct r600_shader_ctx ctx;
3343 struct r600_bytecode_output output[ARRAY_SIZE(shader->output)];
3344 unsigned output_done, noutput;
3345 unsigned opcode;
3346 int j, k, r = 0;
3347 unsigned i;
3348 int next_param_base = 0, next_clip_base;
3349 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
3350 bool indirect_gprs;
3351 bool ring_outputs = false;
3352 bool lds_outputs = false;
3353 bool lds_inputs = false;
3354 bool pos_emitted = false;
3355
3356 ctx.bc = &shader->bc;
3357 ctx.shader = shader;
3358
3359 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
3360 rscreen->has_compressed_msaa_texturing);
3361 ctx.tokens = tokens;
3362 tgsi_scan_shader(tokens, &ctx.info);
3363 shader->indirect_files = ctx.info.indirect_files;
3364
3365 int narrays = ctx.info.array_max[TGSI_FILE_TEMPORARY];
3366 ctx.array_infos = calloc(narrays, sizeof(*ctx.array_infos));
3367 ctx.spilled_arrays = calloc(narrays, sizeof(bool));
3368 tgsi_scan_arrays(tokens, TGSI_FILE_TEMPORARY, narrays, ctx.array_infos);
3369
3370 shader->uses_helper_invocation = false;
3371 shader->uses_doubles = ctx.info.uses_doubles;
3372 shader->uses_atomics = ctx.info.file_mask[TGSI_FILE_HW_ATOMIC];
3373 shader->nsys_inputs = 0;
3374
3375 shader->uses_images = ctx.info.file_count[TGSI_FILE_IMAGE] > 0 ||
3376 ctx.info.file_count[TGSI_FILE_BUFFER] > 0;
3377 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
3378 tgsi_parse_init(&ctx.parse, tokens);
3379 ctx.type = ctx.info.processor;
3380 shader->processor_type = ctx.type;
3381 ctx.bc->type = shader->processor_type;
3382
3383 switch (ctx.type) {
3384 case PIPE_SHADER_VERTEX:
3385 shader->vs_as_gs_a = key.vs.as_gs_a;
3386 shader->vs_as_es = key.vs.as_es;
3387 shader->vs_as_ls = key.vs.as_ls;
3388 shader->atomic_base = key.vs.first_atomic_counter;
3389 if (shader->vs_as_es)
3390 ring_outputs = true;
3391 if (shader->vs_as_ls)
3392 lds_outputs = true;
3393 break;
3394 case PIPE_SHADER_GEOMETRY:
3395 ring_outputs = true;
3396 shader->atomic_base = key.gs.first_atomic_counter;
3397 shader->gs_tri_strip_adj_fix = key.gs.tri_strip_adj_fix;
3398 break;
3399 case PIPE_SHADER_TESS_CTRL:
3400 shader->tcs_prim_mode = key.tcs.prim_mode;
3401 shader->atomic_base = key.tcs.first_atomic_counter;
3402 lds_outputs = true;
3403 lds_inputs = true;
3404 break;
3405 case PIPE_SHADER_TESS_EVAL:
3406 shader->tes_as_es = key.tes.as_es;
3407 shader->atomic_base = key.tes.first_atomic_counter;
3408 lds_inputs = true;
3409 if (shader->tes_as_es)
3410 ring_outputs = true;
3411 break;
3412 case PIPE_SHADER_FRAGMENT:
3413 shader->two_side = key.ps.color_two_side;
3414 shader->atomic_base = key.ps.first_atomic_counter;
3415 shader->rat_base = key.ps.nr_cbufs;
3416 shader->image_size_const_offset = key.ps.image_size_const_offset;
3417 break;
3418 case PIPE_SHADER_COMPUTE:
3419 shader->rat_base = 0;
3420 shader->image_size_const_offset = ctx.info.file_count[TGSI_FILE_SAMPLER];
3421 break;
3422 default:
3423 break;
3424 }
3425
3426 if (shader->vs_as_es || shader->tes_as_es) {
3427 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
3428 } else {
3429 ctx.gs_for_vs = NULL;
3430 }
3431
3432 ctx.next_ring_offset = 0;
3433 ctx.gs_out_ring_offset = 0;
3434 ctx.gs_next_vertex = 0;
3435 ctx.gs_stream_output_info = &so;
3436
3437 ctx.face_gpr = -1;
3438 ctx.fixed_pt_position_gpr = -1;
3439 ctx.fragcoord_input = -1;
3440 ctx.colors_used = 0;
3441 ctx.clip_vertex_write = 0;
3442 ctx.thread_id_gpr_loaded = false;
3443
3444 ctx.helper_invoc_reg = -1;
3445 ctx.cs_block_size_reg = -1;
3446 ctx.cs_grid_size_reg = -1;
3447 ctx.cs_block_size_loaded = false;
3448 ctx.cs_grid_size_loaded = false;
3449
3450 shader->nr_ps_color_exports = 0;
3451 shader->nr_ps_max_color_exports = 0;
3452
3453
3454 /* register allocations */
3455 /* Values [0,127] correspond to GPR[0..127].
3456 * Values [128,159] correspond to constant buffer bank 0
3457 * Values [160,191] correspond to constant buffer bank 1
3458 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3459 * Values [256,287] correspond to constant buffer bank 2 (EG)
3460 * Values [288,319] correspond to constant buffer bank 3 (EG)
3461 * Other special values are shown in the list below.
3462 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3463 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3464 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3465 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3466 * 248 SQ_ALU_SRC_0: special constant 0.0.
3467 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3468 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3469 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3470 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3471 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3472 * 254 SQ_ALU_SRC_PV: previous vector result.
3473 * 255 SQ_ALU_SRC_PS: previous scalar result.
3474 */
3475 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3476 ctx.file_offset[i] = 0;
3477 }
3478
3479 if (ctx.type == PIPE_SHADER_VERTEX) {
3480
3481 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3482 if (ctx.info.num_inputs)
3483 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3484 }
3485 if (ctx.type == PIPE_SHADER_FRAGMENT) {
3486 if (ctx.bc->chip_class >= EVERGREEN)
3487 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3488 else
3489 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3490
3491 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3492 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_HELPER_INVOCATION) {
3493 ctx.helper_invoc_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3494 shader->uses_helper_invocation = true;
3495 }
3496 }
3497 }
3498 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3499 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3500 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3501 }
3502 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3503 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3504 if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3505 bool add_tesscoord = false, add_tess_inout = false;
3506 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3507 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3508 /* if we have tesscoord save one reg */
3509 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3510 add_tesscoord = true;
3511 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3512 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3513 add_tess_inout = true;
3514 }
3515 if (add_tesscoord || add_tess_inout)
3516 ctx.file_offset[TGSI_FILE_INPUT]++;
3517 if (add_tess_inout)
3518 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3519 }
3520 if (ctx.type == PIPE_SHADER_COMPUTE) {
3521 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3522 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3523 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_GRID_SIZE)
3524 ctx.cs_grid_size_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3525 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_BLOCK_SIZE)
3526 ctx.cs_block_size_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3527 }
3528 }
3529
3530 ctx.file_offset[TGSI_FILE_OUTPUT] =
3531 ctx.file_offset[TGSI_FILE_INPUT] +
3532 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3533 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3534 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3535
3536 /* Outside the GPR range. This will be translated to one of the
3537 * kcache banks later. */
3538 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3539 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3540
3541 pipeshader->scratch_space_needed = 0;
3542 int regno = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3543 ctx.info.file_max[TGSI_FILE_TEMPORARY];
3544 if (regno > 124) {
3545 choose_spill_arrays(&ctx, &regno, &pipeshader->scratch_space_needed);
3546 shader->indirect_files = ctx.info.indirect_files;
3547 }
3548 shader->needs_scratch_space = pipeshader->scratch_space_needed != 0;
3549
3550 ctx.bc->ar_reg = ++regno;
3551 ctx.bc->index_reg[0] = ++regno;
3552 ctx.bc->index_reg[1] = ++regno;
3553
3554 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3555 ctx.tess_input_info = ++regno;
3556 ctx.tess_output_info = ++regno;
3557 } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3558 ctx.tess_input_info = 0;
3559 ctx.tess_output_info = ++regno;
3560 } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
3561 ctx.gs_export_gpr_tregs[0] = ++regno;
3562 ctx.gs_export_gpr_tregs[1] = ++regno;
3563 ctx.gs_export_gpr_tregs[2] = ++regno;
3564 ctx.gs_export_gpr_tregs[3] = ++regno;
3565 if (ctx.shader->gs_tri_strip_adj_fix) {
3566 ctx.gs_rotated_input[0] = ++regno;
3567 ctx.gs_rotated_input[1] = ++regno;
3568 } else {
3569 ctx.gs_rotated_input[0] = 0;
3570 ctx.gs_rotated_input[1] = 1;
3571 }
3572 }
3573
3574 if (shader->uses_images) {
3575 ctx.thread_id_gpr = ++regno;
3576 ctx.thread_id_gpr_loaded = false;
3577 }
3578 ctx.temp_reg = ++regno;
3579
3580 shader->max_arrays = 0;
3581 shader->num_arrays = 0;
3582 if (indirect_gprs) {
3583
3584 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3585 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3586 ctx.file_offset[TGSI_FILE_OUTPUT] -
3587 ctx.file_offset[TGSI_FILE_INPUT],
3588 0x0F);
3589 }
3590 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3591 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3592 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3593 ctx.file_offset[TGSI_FILE_OUTPUT],
3594 0x0F);
3595 }
3596 }
3597
3598 ctx.nliterals = 0;
3599 ctx.literals = NULL;
3600 ctx.max_driver_temp_used = 0;
3601
3602 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3603 ctx.info.colors_written == 1;
3604 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3605 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3606
3607 if (ctx.type == PIPE_SHADER_VERTEX ||
3608 ctx.type == PIPE_SHADER_GEOMETRY ||
3609 ctx.type == PIPE_SHADER_TESS_EVAL) {
3610 shader->cc_dist_mask = (1 << (ctx.info.properties[TGSI_PROPERTY_NUM_CULLDIST_ENABLED] +
3611 ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED])) - 1;
3612 shader->clip_dist_write = (1 << ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED]) - 1;
3613 shader->cull_dist_write = ((1 << ctx.info.properties[TGSI_PROPERTY_NUM_CULLDIST_ENABLED]) - 1) << ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED];
3614 }
3615
3616 if (shader->vs_as_gs_a)
3617 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3618
3619 if (ctx.type == PIPE_SHADER_TESS_EVAL)
3620 r600_fetch_tess_io_info(&ctx);
3621
3622 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3623 tgsi_parse_token(&ctx.parse);
3624 switch (ctx.parse.FullToken.Token.Type) {
3625 case TGSI_TOKEN_TYPE_IMMEDIATE:
3626 immediate = &ctx.parse.FullToken.FullImmediate;
3627 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3628 if(ctx.literals == NULL) {
3629 r = -ENOMEM;
3630 goto out_err;
3631 }
3632 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3633 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3634 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3635 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3636 ctx.nliterals++;
3637 break;
3638 case TGSI_TOKEN_TYPE_DECLARATION:
3639 r = tgsi_declaration(&ctx);
3640 if (r)
3641 goto out_err;
3642 break;
3643 case TGSI_TOKEN_TYPE_INSTRUCTION:
3644 case TGSI_TOKEN_TYPE_PROPERTY:
3645 break;
3646 default:
3647 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3648 r = -EINVAL;
3649 goto out_err;
3650 }
3651 }
3652
3653 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3654 shader->ring_item_sizes[1] = 0;
3655 shader->ring_item_sizes[2] = 0;
3656 shader->ring_item_sizes[3] = 0;
3657
3658 /* Process two side if needed */
3659 if (shader->two_side && ctx.colors_used) {
3660 int i, count = ctx.shader->ninput;
3661 unsigned next_lds_loc = ctx.shader->nlds;
3662
3663 /* additional inputs will be allocated right after the existing inputs,
3664 * we won't need them after the color selection, so we don't need to
3665 * reserve these gprs for the rest of the shader code and to adjust
3666 * output offsets etc. */
3667 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3668 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3669
3670 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3671 if (ctx.face_gpr == -1) {
3672 i = ctx.shader->ninput++;
3673 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3674 ctx.shader->input[i].spi_sid = 0;
3675 ctx.shader->input[i].gpr = gpr++;
3676 ctx.face_gpr = ctx.shader->input[i].gpr;
3677 }
3678
3679 for (i = 0; i < count; i++) {
3680 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3681 int ni = ctx.shader->ninput++;
3682 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3683 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3684 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3685 ctx.shader->input[ni].gpr = gpr++;
3686 // TGSI to LLVM needs to know the lds position of inputs.
3687 // Non LLVM path computes it later (in process_twoside_color)
3688 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3689 ctx.shader->input[i].back_color_input = ni;
3690 if (ctx.bc->chip_class >= EVERGREEN) {
3691 if ((r = evergreen_interp_input(&ctx, ni)))
3692 return r;
3693 }
3694 }
3695 }
3696 }
3697
3698 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3699 shader->nr_ps_max_color_exports = 8;
3700
3701 if (ctx.shader->uses_helper_invocation) {
3702 if (ctx.bc->chip_class == CAYMAN)
3703 r = cm_load_helper_invocation(&ctx);
3704 else
3705 r = eg_load_helper_invocation(&ctx);
3706 if (r)
3707 return r;
3708 }
3709
3710 /*
3711 * XXX this relies on fixed_pt_position_gpr only being present when
3712 * this shader should be executed per sample. Should be the case for now...
3713 */
3714 if (ctx.fixed_pt_position_gpr != -1 && ctx.info.reads_samplemask) {
3715 /*
3716 * Fix up sample mask. The hw always gives us coverage mask for
3717 * the pixel. However, for per-sample shading, we need the
3718 * coverage for the shader invocation only.
3719 * Also, with disabled msaa, only the first bit should be set
3720 * (luckily the same fixup works for both problems).
3721 * For now, we can only do it if we know this shader is always
3722 * executed per sample (due to usage of bits in the shader
3723 * forcing per-sample execution).
3724 * If the fb is not multisampled, we'd do unnecessary work but
3725 * it should still be correct.
3726 * It will however do nothing for sample shading according
3727 * to MinSampleShading.
3728 */
3729 struct r600_bytecode_alu alu;
3730 int tmp = r600_get_temp(&ctx);
3731 assert(ctx.face_gpr != -1);
3732 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3733
3734 alu.op = ALU_OP2_LSHL_INT;
3735 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3736 alu.src[0].value = 0x1;
3737 alu.src[1].sel = ctx.fixed_pt_position_gpr;
3738 alu.src[1].chan = 3;
3739 alu.dst.sel = tmp;
3740 alu.dst.chan = 0;
3741 alu.dst.write = 1;
3742 alu.last = 1;
3743 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3744 return r;
3745
3746 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3747 alu.op = ALU_OP2_AND_INT;
3748 alu.src[0].sel = tmp;
3749 alu.src[1].sel = ctx.face_gpr;
3750 alu.src[1].chan = 2;
3751 alu.dst.sel = ctx.face_gpr;
3752 alu.dst.chan = 2;
3753 alu.dst.write = 1;
3754 alu.last = 1;
3755 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3756 return r;
3757 }
3758
3759 if (ctx.fragcoord_input >= 0) {
3760 if (ctx.bc->chip_class == CAYMAN) {
3761 for (j = 0 ; j < 4; j++) {
3762 struct r600_bytecode_alu alu;
3763 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3764 alu.op = ALU_OP1_RECIP_IEEE;
3765 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3766 alu.src[0].chan = 3;
3767
3768 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3769 alu.dst.chan = j;
3770 alu.dst.write = (j == 3);
3771 alu.last = 1;
3772 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3773 return r;
3774 }
3775 } else {
3776 struct r600_bytecode_alu alu;
3777 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3778 alu.op = ALU_OP1_RECIP_IEEE;
3779 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3780 alu.src[0].chan = 3;
3781
3782 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3783 alu.dst.chan = 3;
3784 alu.dst.write = 1;
3785 alu.last = 1;
3786 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3787 return r;
3788 }
3789 }
3790
3791 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3792 struct r600_bytecode_alu alu;
3793 int r;
3794
3795 /* GS thread with no output workaround - emit a cut at start of GS */
3796 if (ctx.bc->chip_class == R600)
3797 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3798
3799 for (j = 0; j < 4; j++) {
3800 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3801 alu.op = ALU_OP1_MOV;
3802 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3803 alu.src[0].value = 0;
3804 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3805 alu.dst.write = 1;
3806 alu.last = 1;
3807 r = r600_bytecode_add_alu(ctx.bc, &alu);
3808 if (r)
3809 return r;
3810 }
3811
3812 if (ctx.shader->gs_tri_strip_adj_fix) {
3813 r = single_alu_op2(&ctx, ALU_OP2_AND_INT,
3814 ctx.gs_rotated_input[0], 2,
3815 0, 2,
3816 V_SQ_ALU_SRC_LITERAL, 1);
3817 if (r)
3818 return r;
3819
3820 for (i = 0; i < 6; i++) {
3821 int rotated = (i + 4) % 6;
3822 int offset_reg = i / 3;
3823 int offset_chan = i % 3;
3824 int rotated_offset_reg = rotated / 3;
3825 int rotated_offset_chan = rotated % 3;
3826
3827 if (offset_reg == 0 && offset_chan == 2)
3828 offset_chan = 3;
3829 if (rotated_offset_reg == 0 && rotated_offset_chan == 2)
3830 rotated_offset_chan = 3;
3831
3832 r = single_alu_op3(&ctx, ALU_OP3_CNDE_INT,
3833 ctx.gs_rotated_input[offset_reg], offset_chan,
3834 ctx.gs_rotated_input[0], 2,
3835 offset_reg, offset_chan,
3836 rotated_offset_reg, rotated_offset_chan);
3837 if (r)
3838 return r;
3839 }
3840 }
3841 }
3842
3843 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3844 r600_fetch_tess_io_info(&ctx);
3845
3846 if (shader->two_side && ctx.colors_used) {
3847 if ((r = process_twoside_color_inputs(&ctx)))
3848 return r;
3849 }
3850
3851 tgsi_parse_init(&ctx.parse, tokens);
3852 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3853 tgsi_parse_token(&ctx.parse);
3854 switch (ctx.parse.FullToken.Token.Type) {
3855 case TGSI_TOKEN_TYPE_INSTRUCTION:
3856 r = tgsi_is_supported(&ctx);
3857 if (r)
3858 goto out_err;
3859 ctx.max_driver_temp_used = 0;
3860 /* reserve first tmp for everyone */
3861 r600_get_temp(&ctx);
3862
3863 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3864 if ((r = tgsi_split_constant(&ctx)))
3865 goto out_err;
3866 if ((r = tgsi_split_literal_constant(&ctx)))
3867 goto out_err;
3868 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3869 if ((r = tgsi_split_gs_inputs(&ctx)))
3870 goto out_err;
3871 } else if (lds_inputs) {
3872 if ((r = tgsi_split_lds_inputs(&ctx)))
3873 goto out_err;
3874 }
3875 if (ctx.bc->chip_class == CAYMAN)
3876 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3877 else if (ctx.bc->chip_class >= EVERGREEN)
3878 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3879 else
3880 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3881 r = ctx.inst_info->process(&ctx);
3882 if (r)
3883 goto out_err;
3884
3885 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3886 r = r600_store_tcs_output(&ctx);
3887 if (r)
3888 goto out_err;
3889 }
3890 break;
3891 default:
3892 break;
3893 }
3894 }
3895
3896 /* Reset the temporary register counter. */
3897 ctx.max_driver_temp_used = 0;
3898
3899 noutput = shader->noutput;
3900
3901 if (!ring_outputs && ctx.clip_vertex_write) {
3902 unsigned clipdist_temp[2];
3903
3904 clipdist_temp[0] = r600_get_temp(&ctx);
3905 clipdist_temp[1] = r600_get_temp(&ctx);
3906
3907 /* need to convert a clipvertex write into clipdistance writes and not export
3908 the clip vertex anymore */
3909
3910 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3911 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3912 shader->output[noutput].gpr = clipdist_temp[0];
3913 noutput++;
3914 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3915 shader->output[noutput].gpr = clipdist_temp[1];
3916 noutput++;
3917
3918 /* reset spi_sid for clipvertex output to avoid confusing spi */
3919 shader->output[ctx.cv_output].spi_sid = 0;
3920
3921 shader->clip_dist_write = 0xFF;
3922 shader->cc_dist_mask = 0xFF;
3923
3924 for (i = 0; i < 8; i++) {
3925 int oreg = i >> 2;
3926 int ochan = i & 3;
3927
3928 for (j = 0; j < 4; j++) {
3929 struct r600_bytecode_alu alu;
3930 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3931 alu.op = ALU_OP2_DOT4;
3932 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3933 alu.src[0].chan = j;
3934
3935 alu.src[1].sel = 512 + i;
3936 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3937 alu.src[1].chan = j;
3938
3939 alu.dst.sel = clipdist_temp[oreg];
3940 alu.dst.chan = j;
3941 alu.dst.write = (j == ochan);
3942 if (j == 3)
3943 alu.last = 1;
3944 r = r600_bytecode_add_alu(ctx.bc, &alu);
3945 if (r)
3946 return r;
3947 }
3948 }
3949 }
3950
3951 /* Add stream outputs. */
3952 if (so.num_outputs) {
3953 bool emit = false;
3954 if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
3955 emit = true;
3956 if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
3957 emit = true;
3958 if (emit)
3959 emit_streamout(&ctx, &so, -1, NULL);
3960 }
3961 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3962 convert_edgeflag_to_int(&ctx);
3963
3964 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3965 r600_emit_tess_factor(&ctx);
3966
3967 if (lds_outputs) {
3968 if (ctx.type == PIPE_SHADER_VERTEX) {
3969 if (ctx.shader->noutput)
3970 emit_lds_vs_writes(&ctx);
3971 }
3972 } else if (ring_outputs) {
3973 if (shader->vs_as_es || shader->tes_as_es) {
3974 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3975 ctx.gs_export_gpr_tregs[1] = -1;
3976 ctx.gs_export_gpr_tregs[2] = -1;
3977 ctx.gs_export_gpr_tregs[3] = -1;
3978
3979 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3980 }
3981 } else {
3982 /* Export output */
3983 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3984
3985 for (i = 0, j = 0; i < noutput; i++, j++) {
3986 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3987 output[j].gpr = shader->output[i].gpr;
3988 output[j].elem_size = 3;
3989 output[j].swizzle_x = 0;
3990 output[j].swizzle_y = 1;
3991 output[j].swizzle_z = 2;
3992 output[j].swizzle_w = 3;
3993 output[j].burst_count = 1;
3994 output[j].type = 0xffffffff;
3995 output[j].op = CF_OP_EXPORT;
3996 switch (ctx.type) {
3997 case PIPE_SHADER_VERTEX:
3998 case PIPE_SHADER_TESS_EVAL:
3999 switch (shader->output[i].name) {
4000 case TGSI_SEMANTIC_POSITION:
4001 output[j].array_base = 60;
4002 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4003 pos_emitted = true;
4004 break;
4005
4006 case TGSI_SEMANTIC_PSIZE:
4007 output[j].array_base = 61;
4008 output[j].swizzle_y = 7;
4009 output[j].swizzle_z = 7;
4010 output[j].swizzle_w = 7;
4011 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4012 pos_emitted = true;
4013 break;
4014 case TGSI_SEMANTIC_EDGEFLAG:
4015 output[j].array_base = 61;
4016 output[j].swizzle_x = 7;
4017 output[j].swizzle_y = 0;
4018 output[j].swizzle_z = 7;
4019 output[j].swizzle_w = 7;
4020 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4021 pos_emitted = true;
4022 break;
4023 case TGSI_SEMANTIC_LAYER:
4024 /* spi_sid is 0 for outputs that are
4025 * not consumed by PS */
4026 if (shader->output[i].spi_sid) {
4027 output[j].array_base = next_param_base++;
4028 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
4029 j++;
4030 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
4031 }
4032 output[j].array_base = 61;
4033 output[j].swizzle_x = 7;
4034 output[j].swizzle_y = 7;
4035 output[j].swizzle_z = 0;
4036 output[j].swizzle_w = 7;
4037 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4038 pos_emitted = true;
4039 break;
4040 case TGSI_SEMANTIC_VIEWPORT_INDEX:
4041 /* spi_sid is 0 for outputs that are
4042 * not consumed by PS */
4043 if (shader->output[i].spi_sid) {
4044 output[j].array_base = next_param_base++;
4045 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
4046 j++;
4047 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
4048 }
4049 output[j].array_base = 61;
4050 output[j].swizzle_x = 7;
4051 output[j].swizzle_y = 7;
4052 output[j].swizzle_z = 7;
4053 output[j].swizzle_w = 0;
4054 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4055 pos_emitted = true;
4056 break;
4057 case TGSI_SEMANTIC_CLIPVERTEX:
4058 j--;
4059 break;
4060 case TGSI_SEMANTIC_CLIPDIST:
4061 output[j].array_base = next_clip_base++;
4062 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4063 pos_emitted = true;
4064 /* spi_sid is 0 for clipdistance outputs that were generated
4065 * for clipvertex - we don't need to pass them to PS */
4066 if (shader->output[i].spi_sid) {
4067 j++;
4068 /* duplicate it as PARAM to pass to the pixel shader */
4069 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
4070 output[j].array_base = next_param_base++;
4071 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
4072 }
4073 break;
4074 case TGSI_SEMANTIC_FOG:
4075 output[j].swizzle_y = 4; /* 0 */
4076 output[j].swizzle_z = 4; /* 0 */
4077 output[j].swizzle_w = 5; /* 1 */
4078 break;
4079 case TGSI_SEMANTIC_PRIMID:
4080 output[j].swizzle_x = 2;
4081 output[j].swizzle_y = 4; /* 0 */
4082 output[j].swizzle_z = 4; /* 0 */
4083 output[j].swizzle_w = 4; /* 0 */
4084 break;
4085 }
4086
4087 break;
4088 case PIPE_SHADER_FRAGMENT:
4089 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
4090 /* never export more colors than the number of CBs */
4091 if (shader->output[i].sid >= max_color_exports) {
4092 /* skip export */
4093 j--;
4094 continue;
4095 }
4096 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
4097 output[j].array_base = shader->output[i].sid;
4098 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4099 shader->nr_ps_color_exports++;
4100 shader->ps_color_export_mask |= (0xf << (shader->output[i].sid * 4));
4101
4102 /* If the i-th target format is set, all previous target formats must
4103 * be non-zero to avoid hangs. - from radeonsi, seems to apply to eg as well.
4104 */
4105 if (shader->output[i].sid > 0)
4106 for (unsigned x = 0; x < shader->output[i].sid; x++)
4107 shader->ps_color_export_mask |= (1 << (x*4));
4108
4109 if (shader->output[i].sid > shader->ps_export_highest)
4110 shader->ps_export_highest = shader->output[i].sid;
4111 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
4112 for (k = 1; k < max_color_exports; k++) {
4113 j++;
4114 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
4115 output[j].gpr = shader->output[i].gpr;
4116 output[j].elem_size = 3;
4117 output[j].swizzle_x = 0;
4118 output[j].swizzle_y = 1;
4119 output[j].swizzle_z = 2;
4120 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
4121 output[j].burst_count = 1;
4122 output[j].array_base = k;
4123 output[j].op = CF_OP_EXPORT;
4124 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4125 shader->nr_ps_color_exports++;
4126 if (k > shader->ps_export_highest)
4127 shader->ps_export_highest = k;
4128 shader->ps_color_export_mask |= (0xf << (j * 4));
4129 }
4130 }
4131 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
4132 output[j].array_base = 61;
4133 output[j].swizzle_x = 2;
4134 output[j].swizzle_y = 7;
4135 output[j].swizzle_z = output[j].swizzle_w = 7;
4136 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4137 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
4138 output[j].array_base = 61;
4139 output[j].swizzle_x = 7;
4140 output[j].swizzle_y = 1;
4141 output[j].swizzle_z = output[j].swizzle_w = 7;
4142 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4143 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
4144 output[j].array_base = 61;
4145 output[j].swizzle_x = 7;
4146 output[j].swizzle_y = 7;
4147 output[j].swizzle_z = 0;
4148 output[j].swizzle_w = 7;
4149 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4150 } else {
4151 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
4152 r = -EINVAL;
4153 goto out_err;
4154 }
4155 break;
4156 case PIPE_SHADER_TESS_CTRL:
4157 break;
4158 default:
4159 R600_ERR("unsupported processor type %d\n", ctx.type);
4160 r = -EINVAL;
4161 goto out_err;
4162 }
4163
4164 if (output[j].type == 0xffffffff) {
4165 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
4166 output[j].array_base = next_param_base++;
4167 }
4168 }
4169
4170 /* add fake position export */
4171 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
4172 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
4173 output[j].gpr = 0;
4174 output[j].elem_size = 3;
4175 output[j].swizzle_x = 7;
4176 output[j].swizzle_y = 7;
4177 output[j].swizzle_z = 7;
4178 output[j].swizzle_w = 7;
4179 output[j].burst_count = 1;
4180 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4181 output[j].array_base = 60;
4182 output[j].op = CF_OP_EXPORT;
4183 j++;
4184 }
4185
4186 /* add fake param output for vertex shader if no param is exported */
4187 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
4188 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
4189 output[j].gpr = 0;
4190 output[j].elem_size = 3;
4191 output[j].swizzle_x = 7;
4192 output[j].swizzle_y = 7;
4193 output[j].swizzle_z = 7;
4194 output[j].swizzle_w = 7;
4195 output[j].burst_count = 1;
4196 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
4197 output[j].array_base = 0;
4198 output[j].op = CF_OP_EXPORT;
4199 j++;
4200 }
4201
4202 /* add fake pixel export */
4203 if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
4204 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
4205 output[j].gpr = 0;
4206 output[j].elem_size = 3;
4207 output[j].swizzle_x = 7;
4208 output[j].swizzle_y = 7;
4209 output[j].swizzle_z = 7;
4210 output[j].swizzle_w = 7;
4211 output[j].burst_count = 1;
4212 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4213 output[j].array_base = 0;
4214 output[j].op = CF_OP_EXPORT;
4215 j++;
4216 shader->nr_ps_color_exports++;
4217 shader->ps_color_export_mask = 0xf;
4218 }
4219
4220 noutput = j;
4221
4222 /* set export done on last export of each type */
4223 for (k = noutput - 1, output_done = 0; k >= 0; k--) {
4224 if (!(output_done & (1 << output[k].type))) {
4225 output_done |= (1 << output[k].type);
4226 output[k].op = CF_OP_EXPORT_DONE;
4227 }
4228 }
4229 /* add output to bytecode */
4230 for (i = 0; i < noutput; i++) {
4231 r = r600_bytecode_add_output(ctx.bc, &output[i]);
4232 if (r)
4233 goto out_err;
4234 }
4235 }
4236
4237 /* add program end */
4238 if (ctx.bc->chip_class == CAYMAN)
4239 cm_bytecode_add_cf_end(ctx.bc);
4240 else {
4241 const struct cf_op_info *last = NULL;
4242
4243 if (ctx.bc->cf_last)
4244 last = r600_isa_cf(ctx.bc->cf_last->op);
4245
4246 /* alu clause instructions don't have EOP bit, so add NOP */
4247 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_POP)
4248 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
4249
4250 ctx.bc->cf_last->end_of_program = 1;
4251 }
4252
4253 /* check GPR limit - we have 124 = 128 - 4
4254 * (4 are reserved as alu clause temporary registers) */
4255 if (ctx.bc->ngpr > 124) {
4256 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
4257 r = -ENOMEM;
4258 goto out_err;
4259 }
4260
4261 if (ctx.type == PIPE_SHADER_GEOMETRY) {
4262 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
4263 return r;
4264 }
4265
4266 free(ctx.spilled_arrays);
4267 free(ctx.array_infos);
4268 free(ctx.literals);
4269 tgsi_parse_free(&ctx.parse);
4270 return 0;
4271 out_err:
4272 free(ctx.spilled_arrays);
4273 free(ctx.array_infos);
4274 free(ctx.literals);
4275 tgsi_parse_free(&ctx.parse);
4276 return r;
4277 }
4278
4279 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
4280 {
4281 const unsigned tgsi_opcode =
4282 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
4283 R600_ERR("%s tgsi opcode unsupported\n",
4284 tgsi_get_opcode_name(tgsi_opcode));
4285 return -EINVAL;
4286 }
4287
4288 static int tgsi_end(struct r600_shader_ctx *ctx UNUSED)
4289 {
4290 return 0;
4291 }
4292
4293 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
4294 const struct r600_shader_src *shader_src,
4295 unsigned chan)
4296 {
4297 bc_src->sel = shader_src->sel;
4298 bc_src->chan = shader_src->swizzle[chan];
4299 bc_src->neg = shader_src->neg;
4300 bc_src->abs = shader_src->abs;
4301 bc_src->rel = shader_src->rel;
4302 bc_src->value = shader_src->value[bc_src->chan];
4303 bc_src->kc_bank = shader_src->kc_bank;
4304 bc_src->kc_rel = shader_src->kc_rel;
4305 }
4306
4307 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
4308 {
4309 bc_src->abs = 1;
4310 bc_src->neg = 0;
4311 }
4312
4313 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
4314 {
4315 bc_src->neg = !bc_src->neg;
4316 }
4317
4318 static void tgsi_dst(struct r600_shader_ctx *ctx,
4319 const struct tgsi_full_dst_register *tgsi_dst,
4320 unsigned swizzle,
4321 struct r600_bytecode_alu_dst *r600_dst)
4322 {
4323 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4324
4325 if (tgsi_dst->Register.File == TGSI_FILE_TEMPORARY) {
4326 bool spilled;
4327 unsigned idx;
4328
4329 idx = map_tgsi_reg_index_to_r600_gpr(ctx, tgsi_dst->Register.Index, &spilled);
4330
4331 if (spilled) {
4332 struct r600_bytecode_output cf;
4333 int reg = r600_get_temp(ctx);
4334 int r;
4335
4336 r600_dst->sel = reg;
4337 r600_dst->chan = swizzle;
4338 r600_dst->write = 1;
4339 if (inst->Instruction.Saturate) {
4340 r600_dst->clamp = 1;
4341 }
4342
4343 // needs to be added after op using tgsi_dst
4344 memset(&cf, 0, sizeof(struct r600_bytecode_output));
4345 cf.op = CF_OP_MEM_SCRATCH;
4346 cf.elem_size = 3;
4347 cf.gpr = reg;
4348 cf.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
4349 cf.mark = 1;
4350 cf.comp_mask = inst->Dst[0].Register.WriteMask;
4351 cf.swizzle_x = 0;
4352 cf.swizzle_y = 1;
4353 cf.swizzle_z = 2;
4354 cf.swizzle_w = 3;
4355 cf.burst_count = 1;
4356
4357 get_spilled_array_base_and_size(ctx, tgsi_dst->Register.Index,
4358 &cf.array_base, &cf.array_size);
4359
4360 if (tgsi_dst->Register.Indirect) {
4361 if (ctx->bc->chip_class < R700)
4362 cf.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
4363 else
4364 cf.type = 3; // V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND_ACK;
4365 cf.index_gpr = ctx->bc->ar_reg;
4366 }
4367 else {
4368 cf.array_base += idx;
4369 cf.array_size = 0;
4370 }
4371
4372 r = r600_bytecode_add_pending_output(ctx->bc, &cf);
4373 if (r)
4374 return;
4375
4376 if (ctx->bc->chip_class >= R700)
4377 r600_bytecode_need_wait_ack(ctx->bc, true);
4378
4379 return;
4380 }
4381 else {
4382 r600_dst->sel = idx;
4383 }
4384 }
4385 else {
4386 r600_dst->sel = tgsi_dst->Register.Index;
4387 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
4388 }
4389 r600_dst->chan = swizzle;
4390 r600_dst->write = 1;
4391 if (inst->Instruction.Saturate) {
4392 r600_dst->clamp = 1;
4393 }
4394 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
4395 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
4396 return;
4397 }
4398 }
4399 if (tgsi_dst->Register.Indirect)
4400 r600_dst->rel = V_SQ_REL_RELATIVE;
4401
4402 }
4403
4404 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap, int dest_temp, int op_override)
4405 {
4406 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4407 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4408 struct r600_bytecode_alu alu;
4409 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4410 int use_tmp = 0;
4411 int swizzle_x = inst->Src[0].Register.SwizzleX;
4412
4413 if (singledest) {
4414 switch (write_mask) {
4415 case 0x1:
4416 if (swizzle_x == 2) {
4417 write_mask = 0xc;
4418 use_tmp = 3;
4419 } else
4420 write_mask = 0x3;
4421 break;
4422 case 0x2:
4423 if (swizzle_x == 2) {
4424 write_mask = 0xc;
4425 use_tmp = 3;
4426 } else {
4427 write_mask = 0x3;
4428 use_tmp = 1;
4429 }
4430 break;
4431 case 0x4:
4432 if (swizzle_x == 0) {
4433 write_mask = 0x3;
4434 use_tmp = 1;
4435 } else
4436 write_mask = 0xc;
4437 break;
4438 case 0x8:
4439 if (swizzle_x == 0) {
4440 write_mask = 0x3;
4441 use_tmp = 1;
4442 } else {
4443 write_mask = 0xc;
4444 use_tmp = 3;
4445 }
4446 break;
4447 }
4448 }
4449
4450 lasti = tgsi_last_instruction(write_mask);
4451 for (i = 0; i <= lasti; i++) {
4452
4453 if (!(write_mask & (1 << i)))
4454 continue;
4455
4456 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4457
4458 if (singledest) {
4459 if (use_tmp || dest_temp) {
4460 alu.dst.sel = use_tmp ? ctx->temp_reg : dest_temp;
4461 alu.dst.chan = i;
4462 alu.dst.write = 1;
4463 } else {
4464 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4465 }
4466 if (i == 1 || i == 3)
4467 alu.dst.write = 0;
4468 } else
4469 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4470
4471 alu.op = op_override ? op_override : ctx->inst_info->op;
4472 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
4473 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4474 } else if (!swap) {
4475 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4476 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4477 }
4478 } else {
4479 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
4480 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
4481 }
4482
4483 /* handle some special cases */
4484 if (i == 1 || i == 3) {
4485 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
4486 case TGSI_OPCODE_DABS:
4487 r600_bytecode_src_set_abs(&alu.src[0]);
4488 break;
4489 default:
4490 break;
4491 }
4492 }
4493 if (i == lasti) {
4494 alu.last = 1;
4495 }
4496 r = r600_bytecode_add_alu(ctx->bc, &alu);
4497 if (r)
4498 return r;
4499 }
4500
4501 if (use_tmp) {
4502 write_mask = inst->Dst[0].Register.WriteMask;
4503
4504 lasti = tgsi_last_instruction(write_mask);
4505 /* move result from temp to dst */
4506 for (i = 0; i <= lasti; i++) {
4507 if (!(write_mask & (1 << i)))
4508 continue;
4509
4510 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4511 alu.op = ALU_OP1_MOV;
4512
4513 if (dest_temp) {
4514 alu.dst.sel = dest_temp;
4515 alu.dst.chan = i;
4516 alu.dst.write = 1;
4517 } else
4518 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4519 alu.src[0].sel = ctx->temp_reg;
4520 alu.src[0].chan = use_tmp - 1;
4521 alu.last = (i == lasti);
4522
4523 r = r600_bytecode_add_alu(ctx->bc, &alu);
4524 if (r)
4525 return r;
4526 }
4527 }
4528 return 0;
4529 }
4530
4531 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
4532 {
4533 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4534 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4535 /* confirm writemasking */
4536 if ((write_mask & 0x3) != 0x3 &&
4537 (write_mask & 0xc) != 0xc) {
4538 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
4539 return -1;
4540 }
4541 return tgsi_op2_64_params(ctx, false, false, 0, 0);
4542 }
4543
4544 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
4545 {
4546 return tgsi_op2_64_params(ctx, true, false, 0, 0);
4547 }
4548
4549 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
4550 {
4551 return tgsi_op2_64_params(ctx, true, true, 0, 0);
4552 }
4553
4554 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
4555 {
4556 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4557 struct r600_bytecode_alu alu;
4558 int i, j, r;
4559 int lasti = 3;
4560 int tmp = r600_get_temp(ctx);
4561
4562 for (i = 0; i < lasti + 1; i++) {
4563
4564 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4565 alu.op = ctx->inst_info->op;
4566 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4567 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
4568 }
4569
4570 if (inst->Dst[0].Register.WriteMask & (1 << i))
4571 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4572 else
4573 alu.dst.sel = tmp;
4574
4575 alu.dst.chan = i;
4576 alu.is_op3 = 1;
4577 if (i == lasti) {
4578 alu.last = 1;
4579 }
4580 r = r600_bytecode_add_alu(ctx->bc, &alu);
4581 if (r)
4582 return r;
4583 }
4584 return 0;
4585 }
4586
4587 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
4588 {
4589 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4590 struct r600_bytecode_alu alu;
4591 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4592 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4593 /* use temp register if trans_only and more than one dst component */
4594 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
4595 unsigned op = ctx->inst_info->op;
4596
4597 if (op == ALU_OP2_MUL_IEEE &&
4598 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
4599 op = ALU_OP2_MUL;
4600
4601 for (i = 0; i <= lasti; i++) {
4602 if (!(write_mask & (1 << i)))
4603 continue;
4604
4605 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4606 if (use_tmp) {
4607 alu.dst.sel = ctx->temp_reg;
4608 alu.dst.chan = i;
4609 alu.dst.write = 1;
4610 } else
4611 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4612
4613 alu.op = op;
4614 if (!swap) {
4615 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4616 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4617 }
4618 } else {
4619 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4620 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4621 }
4622 if (i == lasti || trans_only) {
4623 alu.last = 1;
4624 }
4625 r = r600_bytecode_add_alu(ctx->bc, &alu);
4626 if (r)
4627 return r;
4628 }
4629
4630 if (use_tmp) {
4631 /* move result from temp to dst */
4632 for (i = 0; i <= lasti; i++) {
4633 if (!(write_mask & (1 << i)))
4634 continue;
4635
4636 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4637 alu.op = ALU_OP1_MOV;
4638 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4639 alu.src[0].sel = ctx->temp_reg;
4640 alu.src[0].chan = i;
4641 alu.last = (i == lasti);
4642
4643 r = r600_bytecode_add_alu(ctx->bc, &alu);
4644 if (r)
4645 return r;
4646 }
4647 }
4648 return 0;
4649 }
4650
4651 static int tgsi_op2(struct r600_shader_ctx *ctx)
4652 {
4653 return tgsi_op2_s(ctx, 0, 0);
4654 }
4655
4656 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
4657 {
4658 return tgsi_op2_s(ctx, 1, 0);
4659 }
4660
4661 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
4662 {
4663 return tgsi_op2_s(ctx, 0, 1);
4664 }
4665
4666 static int tgsi_ineg(struct r600_shader_ctx *ctx)
4667 {
4668 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4669 struct r600_bytecode_alu alu;
4670 int i, r;
4671 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4672
4673 for (i = 0; i < lasti + 1; i++) {
4674
4675 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4676 continue;
4677 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4678 alu.op = ctx->inst_info->op;
4679
4680 alu.src[0].sel = V_SQ_ALU_SRC_0;
4681
4682 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4683
4684 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4685
4686 if (i == lasti) {
4687 alu.last = 1;
4688 }
4689 r = r600_bytecode_add_alu(ctx->bc, &alu);
4690 if (r)
4691 return r;
4692 }
4693 return 0;
4694
4695 }
4696
4697 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4698 {
4699 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4700 struct r600_bytecode_alu alu;
4701 int i, r;
4702 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4703
4704 for (i = 0; i < lasti + 1; i++) {
4705
4706 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4707 continue;
4708 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4709 alu.op = ALU_OP1_MOV;
4710
4711 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4712
4713 if (i == 1 || i == 3)
4714 r600_bytecode_src_toggle_neg(&alu.src[0]);
4715 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4716
4717 if (i == lasti) {
4718 alu.last = 1;
4719 }
4720 r = r600_bytecode_add_alu(ctx->bc, &alu);
4721 if (r)
4722 return r;
4723 }
4724 return 0;
4725
4726 }
4727
4728 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4729 {
4730 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4731 struct r600_bytecode_alu alu;
4732 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4733 int i, j, r;
4734
4735 for (i = 0; i <= 3; i++) {
4736 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4737 alu.op = ctx->inst_info->op;
4738
4739 alu.dst.sel = ctx->temp_reg;
4740 alu.dst.chan = i;
4741 alu.dst.write = 1;
4742 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4743 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4744 }
4745
4746 if (i == 3)
4747 alu.last = 1;
4748
4749 r = r600_bytecode_add_alu(ctx->bc, &alu);
4750 if (r)
4751 return r;
4752 }
4753
4754 /* Replicate significand result across channels. */
4755 for (i = 0; i <= 3; i++) {
4756 if (!(write_mask & (1 << i)))
4757 continue;
4758
4759 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4760 alu.op = ALU_OP1_MOV;
4761 alu.src[0].chan = (i & 1) + 2;
4762 alu.src[0].sel = ctx->temp_reg;
4763
4764 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4765 alu.dst.write = 1;
4766 alu.last = 1;
4767 r = r600_bytecode_add_alu(ctx->bc, &alu);
4768 if (r)
4769 return r;
4770 }
4771
4772 for (i = 0; i <= 3; i++) {
4773 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4774 /* MOV third channels to writemask dst1 */
4775 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4776 alu.op = ALU_OP1_MOV;
4777 alu.src[0].chan = 1;
4778 alu.src[0].sel = ctx->temp_reg;
4779
4780 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4781 alu.last = 1;
4782 r = r600_bytecode_add_alu(ctx->bc, &alu);
4783 if (r)
4784 return r;
4785 break;
4786 }
4787 }
4788 return 0;
4789 }
4790
4791
4792 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4793 {
4794 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4795 struct r600_bytecode_alu alu;
4796 int i, c, r;
4797 int write_mask = inst->Dst[0].Register.WriteMask;
4798 int temp_reg = r600_get_temp(ctx);
4799
4800 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4801 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4802
4803 for (c = 0; c < 2; c++) {
4804 int dchan = c * 2;
4805 if (write_mask & (0x3 << dchan)) {
4806 /* split into 24-bit int and 8-bit int */
4807 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4808 alu.op = ALU_OP2_AND_INT;
4809 alu.dst.sel = temp_reg;
4810 alu.dst.chan = dchan;
4811 r600_bytecode_src(&alu.src[0], &ctx->src[0], c);
4812 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4813 alu.src[1].value = 0xffffff00;
4814 alu.dst.write = 1;
4815 r = r600_bytecode_add_alu(ctx->bc, &alu);
4816 if (r)
4817 return r;
4818
4819 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4820 alu.op = ALU_OP2_AND_INT;
4821 alu.dst.sel = temp_reg;
4822 alu.dst.chan = dchan + 1;
4823 r600_bytecode_src(&alu.src[0], &ctx->src[0], c);
4824 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4825 alu.src[1].value = 0xff;
4826 alu.dst.write = 1;
4827 alu.last = 1;
4828 r = r600_bytecode_add_alu(ctx->bc, &alu);
4829 if (r)
4830 return r;
4831 }
4832 }
4833
4834 for (c = 0; c < 2; c++) {
4835 int dchan = c * 2;
4836 if (write_mask & (0x3 << dchan)) {
4837 for (i = dchan; i <= dchan + 1; i++) {
4838 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4839 alu.op = i == dchan ? ctx->inst_info->op : ALU_OP1_UINT_TO_FLT;
4840
4841 alu.src[0].sel = temp_reg;
4842 alu.src[0].chan = i;
4843 alu.dst.sel = temp_reg;
4844 alu.dst.chan = i;
4845 alu.dst.write = 1;
4846 if (ctx->bc->chip_class == CAYMAN)
4847 alu.last = i == dchan + 1;
4848 else
4849 alu.last = 1; /* trans only ops on evergreen */
4850
4851 r = r600_bytecode_add_alu(ctx->bc, &alu);
4852 if (r)
4853 return r;
4854 }
4855 }
4856 }
4857
4858 for (c = 0; c < 2; c++) {
4859 int dchan = c * 2;
4860 if (write_mask & (0x3 << dchan)) {
4861 for (i = 0; i < 4; i++) {
4862 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4863 alu.op = ALU_OP1_FLT32_TO_FLT64;
4864
4865 alu.src[0].chan = dchan + (i / 2);
4866 if (i == 0 || i == 2)
4867 alu.src[0].sel = temp_reg;
4868 else {
4869 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4870 alu.src[0].value = 0x0;
4871 }
4872 alu.dst.sel = ctx->temp_reg;
4873 alu.dst.chan = i;
4874 alu.last = i == 3;
4875 alu.dst.write = 1;
4876
4877 r = r600_bytecode_add_alu(ctx->bc, &alu);
4878 if (r)
4879 return r;
4880 }
4881
4882 for (i = 0; i <= 1; i++) {
4883 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4884 alu.op = ALU_OP2_ADD_64;
4885
4886 alu.src[0].chan = fp64_switch(i);
4887 alu.src[0].sel = ctx->temp_reg;
4888
4889 alu.src[1].chan = fp64_switch(i + 2);
4890 alu.src[1].sel = ctx->temp_reg;
4891 tgsi_dst(ctx, &inst->Dst[0], dchan + i, &alu.dst);
4892 alu.last = i == 1;
4893
4894 r = r600_bytecode_add_alu(ctx->bc, &alu);
4895 if (r)
4896 return r;
4897 }
4898 }
4899 }
4900
4901 return 0;
4902 }
4903
4904 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4905 {
4906 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4907 struct r600_bytecode_alu alu;
4908 int i, r;
4909 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4910 int treg = r600_get_temp(ctx);
4911 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4912 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4913
4914 /* do a 64->32 into a temp register */
4915 r = tgsi_op2_64_params(ctx, true, false, treg, ALU_OP1_FLT64_TO_FLT32);
4916 if (r)
4917 return r;
4918
4919 for (i = 0; i <= lasti; i++) {
4920 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4921 continue;
4922 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4923 alu.op = ctx->inst_info->op;
4924
4925 alu.src[0].chan = i;
4926 alu.src[0].sel = treg;
4927 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4928 alu.last = (i == lasti);
4929
4930 r = r600_bytecode_add_alu(ctx->bc, &alu);
4931 if (r)
4932 return r;
4933 }
4934
4935 return 0;
4936 }
4937
4938 static int cayman_emit_unary_double_raw(struct r600_bytecode *bc,
4939 unsigned op,
4940 int dst_reg,
4941 struct r600_shader_src *src,
4942 bool abs)
4943 {
4944 struct r600_bytecode_alu alu;
4945 const int last_slot = 3;
4946 int r;
4947
4948 /* these have to write the result to X/Y by the looks of it */
4949 for (int i = 0 ; i < last_slot; i++) {
4950 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4951 alu.op = op;
4952
4953 r600_bytecode_src(&alu.src[0], src, 1);
4954 r600_bytecode_src(&alu.src[1], src, 0);
4955
4956 if (abs)
4957 r600_bytecode_src_set_abs(&alu.src[1]);
4958
4959 alu.dst.sel = dst_reg;
4960 alu.dst.chan = i;
4961 alu.dst.write = (i == 0 || i == 1);
4962
4963 if (bc->chip_class != CAYMAN || i == last_slot - 1)
4964 alu.last = 1;
4965 r = r600_bytecode_add_alu(bc, &alu);
4966 if (r)
4967 return r;
4968 }
4969
4970 return 0;
4971 }
4972
4973 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4974 {
4975 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4976 int i, r;
4977 struct r600_bytecode_alu alu;
4978 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4979 int t1 = ctx->temp_reg;
4980
4981 /* should only be one src regs */
4982 assert(inst->Instruction.NumSrcRegs == 1);
4983
4984 /* only support one double at a time */
4985 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4986 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4987
4988 r = cayman_emit_unary_double_raw(
4989 ctx->bc, ctx->inst_info->op, t1,
4990 &ctx->src[0],
4991 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4992 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT);
4993 if (r)
4994 return r;
4995
4996 for (i = 0 ; i <= lasti; i++) {
4997 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4998 continue;
4999 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5000 alu.op = ALU_OP1_MOV;
5001 alu.src[0].sel = t1;
5002 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
5003 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5004 alu.dst.write = 1;
5005 if (i == lasti)
5006 alu.last = 1;
5007 r = r600_bytecode_add_alu(ctx->bc, &alu);
5008 if (r)
5009 return r;
5010 }
5011 return 0;
5012 }
5013
5014 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
5015 {
5016 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5017 int i, j, r;
5018 struct r600_bytecode_alu alu;
5019 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5020
5021 for (i = 0 ; i < last_slot; i++) {
5022 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5023 alu.op = ctx->inst_info->op;
5024 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5025 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
5026
5027 /* RSQ should take the absolute value of src */
5028 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
5029 r600_bytecode_src_set_abs(&alu.src[j]);
5030 }
5031 }
5032 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5033 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5034
5035 if (i == last_slot - 1)
5036 alu.last = 1;
5037 r = r600_bytecode_add_alu(ctx->bc, &alu);
5038 if (r)
5039 return r;
5040 }
5041 return 0;
5042 }
5043
5044 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
5045 {
5046 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5047 int i, j, k, r;
5048 struct r600_bytecode_alu alu;
5049 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5050 int t1 = ctx->temp_reg;
5051
5052 for (k = 0; k <= lasti; k++) {
5053 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
5054 continue;
5055
5056 for (i = 0 ; i < 4; i++) {
5057 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5058 alu.op = ctx->inst_info->op;
5059 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5060 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
5061 }
5062 alu.dst.sel = t1;
5063 alu.dst.chan = i;
5064 alu.dst.write = (i == k);
5065 if (i == 3)
5066 alu.last = 1;
5067 r = r600_bytecode_add_alu(ctx->bc, &alu);
5068 if (r)
5069 return r;
5070 }
5071 }
5072
5073 for (i = 0 ; i <= lasti; i++) {
5074 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5075 continue;
5076 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5077 alu.op = ALU_OP1_MOV;
5078 alu.src[0].sel = t1;
5079 alu.src[0].chan = i;
5080 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5081 alu.dst.write = 1;
5082 if (i == lasti)
5083 alu.last = 1;
5084 r = r600_bytecode_add_alu(ctx->bc, &alu);
5085 if (r)
5086 return r;
5087 }
5088
5089 return 0;
5090 }
5091
5092
5093 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
5094 {
5095 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5096 int i, j, k, r;
5097 struct r600_bytecode_alu alu;
5098 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5099 int t1 = ctx->temp_reg;
5100
5101 /* t1 would get overwritten below if we actually tried to
5102 * multiply two pairs of doubles at a time. */
5103 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
5104 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
5105
5106 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
5107
5108 for (i = 0; i < 4; i++) {
5109 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5110 alu.op = ctx->inst_info->op;
5111 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5112 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));
5113 }
5114 alu.dst.sel = t1;
5115 alu.dst.chan = i;
5116 alu.dst.write = 1;
5117 if (i == 3)
5118 alu.last = 1;
5119 r = r600_bytecode_add_alu(ctx->bc, &alu);
5120 if (r)
5121 return r;
5122 }
5123
5124 for (i = 0; i <= lasti; i++) {
5125 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5126 continue;
5127 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5128 alu.op = ALU_OP1_MOV;
5129 alu.src[0].sel = t1;
5130 alu.src[0].chan = i;
5131 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5132 alu.dst.write = 1;
5133 if (i == lasti)
5134 alu.last = 1;
5135 r = r600_bytecode_add_alu(ctx->bc, &alu);
5136 if (r)
5137 return r;
5138 }
5139
5140 return 0;
5141 }
5142
5143 /*
5144 * Emit RECIP_64 + MUL_64 to implement division.
5145 */
5146 static int cayman_ddiv_instr(struct r600_shader_ctx *ctx)
5147 {
5148 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5149 int r;
5150 struct r600_bytecode_alu alu;
5151 int t1 = ctx->temp_reg;
5152 int k;
5153
5154 /* Only support one double at a time. This is the same constraint as
5155 * in DMUL lowering. */
5156 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
5157 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
5158
5159 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
5160
5161 r = cayman_emit_unary_double_raw(ctx->bc, ALU_OP2_RECIP_64, t1, &ctx->src[1], false);
5162 if (r)
5163 return r;
5164
5165 for (int i = 0; i < 4; i++) {
5166 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5167 alu.op = ALU_OP2_MUL_64;
5168
5169 r600_bytecode_src(&alu.src[0], &ctx->src[0], k * 2 + ((i == 3) ? 0 : 1));
5170
5171 alu.src[1].sel = t1;
5172 alu.src[1].chan = (i == 3) ? 0 : 1;
5173
5174 alu.dst.sel = t1;
5175 alu.dst.chan = i;
5176 alu.dst.write = 1;
5177 if (i == 3)
5178 alu.last = 1;
5179 r = r600_bytecode_add_alu(ctx->bc, &alu);
5180 if (r)
5181 return r;
5182 }
5183
5184 for (int i = 0; i < 2; i++) {
5185 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5186 alu.op = ALU_OP1_MOV;
5187 alu.src[0].sel = t1;
5188 alu.src[0].chan = i;
5189 tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
5190 alu.dst.write = 1;
5191 if (i == 1)
5192 alu.last = 1;
5193 r = r600_bytecode_add_alu(ctx->bc, &alu);
5194 if (r)
5195 return r;
5196 }
5197 return 0;
5198 }
5199
5200 /*
5201 * r600 - trunc to -PI..PI range
5202 * r700 - normalize by dividing by 2PI
5203 * see fdo bug 27901
5204 */
5205 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
5206 {
5207 int r;
5208 struct r600_bytecode_alu alu;
5209
5210 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5211 alu.op = ALU_OP3_MULADD;
5212 alu.is_op3 = 1;
5213
5214 alu.dst.chan = 0;
5215 alu.dst.sel = ctx->temp_reg;
5216 alu.dst.write = 1;
5217
5218 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5219
5220 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5221 alu.src[1].chan = 0;
5222 alu.src[1].value = u_bitcast_f2u(0.5f * M_1_PI);
5223 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
5224 alu.src[2].chan = 0;
5225 alu.last = 1;
5226 r = r600_bytecode_add_alu(ctx->bc, &alu);
5227 if (r)
5228 return r;
5229
5230 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5231 alu.op = ALU_OP1_FRACT;
5232
5233 alu.dst.chan = 0;
5234 alu.dst.sel = ctx->temp_reg;
5235 alu.dst.write = 1;
5236
5237 alu.src[0].sel = ctx->temp_reg;
5238 alu.src[0].chan = 0;
5239 alu.last = 1;
5240 r = r600_bytecode_add_alu(ctx->bc, &alu);
5241 if (r)
5242 return r;
5243
5244 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5245 alu.op = ALU_OP3_MULADD;
5246 alu.is_op3 = 1;
5247
5248 alu.dst.chan = 0;
5249 alu.dst.sel = ctx->temp_reg;
5250 alu.dst.write = 1;
5251
5252 alu.src[0].sel = ctx->temp_reg;
5253 alu.src[0].chan = 0;
5254
5255 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5256 alu.src[1].chan = 0;
5257 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
5258 alu.src[2].chan = 0;
5259
5260 if (ctx->bc->chip_class == R600) {
5261 alu.src[1].value = u_bitcast_f2u(2.0f * M_PI);
5262 alu.src[2].value = u_bitcast_f2u(-M_PI);
5263 } else {
5264 alu.src[1].sel = V_SQ_ALU_SRC_1;
5265 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
5266 alu.src[2].neg = 1;
5267 }
5268
5269 alu.last = 1;
5270 r = r600_bytecode_add_alu(ctx->bc, &alu);
5271 if (r)
5272 return r;
5273 return 0;
5274 }
5275
5276 static int cayman_trig(struct r600_shader_ctx *ctx)
5277 {
5278 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5279 struct r600_bytecode_alu alu;
5280 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5281 int i, r;
5282
5283 r = tgsi_setup_trig(ctx);
5284 if (r)
5285 return r;
5286
5287
5288 for (i = 0; i < last_slot; i++) {
5289 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5290 alu.op = ctx->inst_info->op;
5291 alu.dst.chan = i;
5292
5293 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5294 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5295
5296 alu.src[0].sel = ctx->temp_reg;
5297 alu.src[0].chan = 0;
5298 if (i == last_slot - 1)
5299 alu.last = 1;
5300 r = r600_bytecode_add_alu(ctx->bc, &alu);
5301 if (r)
5302 return r;
5303 }
5304 return 0;
5305 }
5306
5307 static int tgsi_trig(struct r600_shader_ctx *ctx)
5308 {
5309 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5310 struct r600_bytecode_alu alu;
5311 int i, r;
5312 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5313
5314 r = tgsi_setup_trig(ctx);
5315 if (r)
5316 return r;
5317
5318 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5319 alu.op = ctx->inst_info->op;
5320 alu.dst.chan = 0;
5321 alu.dst.sel = ctx->temp_reg;
5322 alu.dst.write = 1;
5323
5324 alu.src[0].sel = ctx->temp_reg;
5325 alu.src[0].chan = 0;
5326 alu.last = 1;
5327 r = r600_bytecode_add_alu(ctx->bc, &alu);
5328 if (r)
5329 return r;
5330
5331 /* replicate result */
5332 for (i = 0; i < lasti + 1; i++) {
5333 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5334 continue;
5335
5336 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5337 alu.op = ALU_OP1_MOV;
5338
5339 alu.src[0].sel = ctx->temp_reg;
5340 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5341 if (i == lasti)
5342 alu.last = 1;
5343 r = r600_bytecode_add_alu(ctx->bc, &alu);
5344 if (r)
5345 return r;
5346 }
5347 return 0;
5348 }
5349
5350 static int tgsi_kill(struct r600_shader_ctx *ctx)
5351 {
5352 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5353 struct r600_bytecode_alu alu;
5354 int i, r;
5355
5356 for (i = 0; i < 4; i++) {
5357 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5358 alu.op = ctx->inst_info->op;
5359
5360 alu.dst.chan = i;
5361
5362 alu.src[0].sel = V_SQ_ALU_SRC_0;
5363
5364 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
5365 alu.src[1].sel = V_SQ_ALU_SRC_1;
5366 alu.src[1].neg = 1;
5367 } else {
5368 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5369 }
5370 if (i == 3) {
5371 alu.last = 1;
5372 }
5373 r = r600_bytecode_add_alu(ctx->bc, &alu);
5374 if (r)
5375 return r;
5376 }
5377
5378 /* kill must be last in ALU */
5379 ctx->bc->force_add_cf = 1;
5380 ctx->shader->uses_kill = TRUE;
5381 return 0;
5382 }
5383
5384 static int tgsi_lit(struct r600_shader_ctx *ctx)
5385 {
5386 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5387 struct r600_bytecode_alu alu;
5388 int r;
5389
5390 /* tmp.x = max(src.y, 0.0) */
5391 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5392 alu.op = ALU_OP2_MAX;
5393 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
5394 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
5395 alu.src[1].chan = 1;
5396
5397 alu.dst.sel = ctx->temp_reg;
5398 alu.dst.chan = 0;
5399 alu.dst.write = 1;
5400
5401 alu.last = 1;
5402 r = r600_bytecode_add_alu(ctx->bc, &alu);
5403 if (r)
5404 return r;
5405
5406 if (inst->Dst[0].Register.WriteMask & (1 << 2))
5407 {
5408 int chan;
5409 int sel;
5410 unsigned i;
5411
5412 if (ctx->bc->chip_class == CAYMAN) {
5413 for (i = 0; i < 3; i++) {
5414 /* tmp.z = log(tmp.x) */
5415 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5416 alu.op = ALU_OP1_LOG_CLAMPED;
5417 alu.src[0].sel = ctx->temp_reg;
5418 alu.src[0].chan = 0;
5419 alu.dst.sel = ctx->temp_reg;
5420 alu.dst.chan = i;
5421 if (i == 2) {
5422 alu.dst.write = 1;
5423 alu.last = 1;
5424 } else
5425 alu.dst.write = 0;
5426
5427 r = r600_bytecode_add_alu(ctx->bc, &alu);
5428 if (r)
5429 return r;
5430 }
5431 } else {
5432 /* tmp.z = log(tmp.x) */
5433 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5434 alu.op = ALU_OP1_LOG_CLAMPED;
5435 alu.src[0].sel = ctx->temp_reg;
5436 alu.src[0].chan = 0;
5437 alu.dst.sel = ctx->temp_reg;
5438 alu.dst.chan = 2;
5439 alu.dst.write = 1;
5440 alu.last = 1;
5441 r = r600_bytecode_add_alu(ctx->bc, &alu);
5442 if (r)
5443 return r;
5444 }
5445
5446 chan = alu.dst.chan;
5447 sel = alu.dst.sel;
5448
5449 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
5450 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5451 alu.op = ALU_OP3_MUL_LIT;
5452 alu.src[0].sel = sel;
5453 alu.src[0].chan = chan;
5454 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
5455 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
5456 alu.dst.sel = ctx->temp_reg;
5457 alu.dst.chan = 0;
5458 alu.dst.write = 1;
5459 alu.is_op3 = 1;
5460 alu.last = 1;
5461 r = r600_bytecode_add_alu(ctx->bc, &alu);
5462 if (r)
5463 return r;
5464
5465 if (ctx->bc->chip_class == CAYMAN) {
5466 for (i = 0; i < 3; i++) {
5467 /* dst.z = exp(tmp.x) */
5468 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5469 alu.op = ALU_OP1_EXP_IEEE;
5470 alu.src[0].sel = ctx->temp_reg;
5471 alu.src[0].chan = 0;
5472 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5473 if (i == 2) {
5474 alu.dst.write = 1;
5475 alu.last = 1;
5476 } else
5477 alu.dst.write = 0;
5478 r = r600_bytecode_add_alu(ctx->bc, &alu);
5479 if (r)
5480 return r;
5481 }
5482 } else {
5483 /* dst.z = exp(tmp.x) */
5484 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5485 alu.op = ALU_OP1_EXP_IEEE;
5486 alu.src[0].sel = ctx->temp_reg;
5487 alu.src[0].chan = 0;
5488 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
5489 alu.last = 1;
5490 r = r600_bytecode_add_alu(ctx->bc, &alu);
5491 if (r)
5492 return r;
5493 }
5494 }
5495
5496 /* dst.x, <- 1.0 */
5497 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5498 alu.op = ALU_OP1_MOV;
5499 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
5500 alu.src[0].chan = 0;
5501 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
5502 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
5503 r = r600_bytecode_add_alu(ctx->bc, &alu);
5504 if (r)
5505 return r;
5506
5507 /* dst.y = max(src.x, 0.0) */
5508 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5509 alu.op = ALU_OP2_MAX;
5510 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5511 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
5512 alu.src[1].chan = 0;
5513 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
5514 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
5515 r = r600_bytecode_add_alu(ctx->bc, &alu);
5516 if (r)
5517 return r;
5518
5519 /* dst.w, <- 1.0 */
5520 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5521 alu.op = ALU_OP1_MOV;
5522 alu.src[0].sel = V_SQ_ALU_SRC_1;
5523 alu.src[0].chan = 0;
5524 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
5525 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
5526 alu.last = 1;
5527 r = r600_bytecode_add_alu(ctx->bc, &alu);
5528 if (r)
5529 return r;
5530
5531 return 0;
5532 }
5533
5534 static int tgsi_rsq(struct r600_shader_ctx *ctx)
5535 {
5536 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5537 struct r600_bytecode_alu alu;
5538 int i, r;
5539
5540 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5541
5542 alu.op = ALU_OP1_RECIPSQRT_IEEE;
5543
5544 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5545 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
5546 r600_bytecode_src_set_abs(&alu.src[i]);
5547 }
5548 alu.dst.sel = ctx->temp_reg;
5549 alu.dst.write = 1;
5550 alu.last = 1;
5551 r = r600_bytecode_add_alu(ctx->bc, &alu);
5552 if (r)
5553 return r;
5554 /* replicate result */
5555 return tgsi_helper_tempx_replicate(ctx);
5556 }
5557
5558 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
5559 {
5560 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5561 struct r600_bytecode_alu alu;
5562 int i, r;
5563
5564 for (i = 0; i < 4; i++) {
5565 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5566 alu.src[0].sel = ctx->temp_reg;
5567 alu.op = ALU_OP1_MOV;
5568 alu.dst.chan = i;
5569 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5570 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5571 if (i == 3)
5572 alu.last = 1;
5573 r = r600_bytecode_add_alu(ctx->bc, &alu);
5574 if (r)
5575 return r;
5576 }
5577 return 0;
5578 }
5579
5580 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
5581 {
5582 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5583 struct r600_bytecode_alu alu;
5584 int i, r;
5585
5586 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5587 alu.op = ctx->inst_info->op;
5588 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5589 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
5590 }
5591 alu.dst.sel = ctx->temp_reg;
5592 alu.dst.write = 1;
5593 alu.last = 1;
5594 r = r600_bytecode_add_alu(ctx->bc, &alu);
5595 if (r)
5596 return r;
5597 /* replicate result */
5598 return tgsi_helper_tempx_replicate(ctx);
5599 }
5600
5601 static int cayman_pow(struct r600_shader_ctx *ctx)
5602 {
5603 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5604 int i, r;
5605 struct r600_bytecode_alu alu;
5606 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5607
5608 for (i = 0; i < 3; i++) {
5609 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5610 alu.op = ALU_OP1_LOG_IEEE;
5611 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5612 alu.dst.sel = ctx->temp_reg;
5613 alu.dst.chan = i;
5614 alu.dst.write = 1;
5615 if (i == 2)
5616 alu.last = 1;
5617 r = r600_bytecode_add_alu(ctx->bc, &alu);
5618 if (r)
5619 return r;
5620 }
5621
5622 /* b * LOG2(a) */
5623 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5624 alu.op = ALU_OP2_MUL;
5625 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5626 alu.src[1].sel = ctx->temp_reg;
5627 alu.dst.sel = ctx->temp_reg;
5628 alu.dst.write = 1;
5629 alu.last = 1;
5630 r = r600_bytecode_add_alu(ctx->bc, &alu);
5631 if (r)
5632 return r;
5633
5634 for (i = 0; i < last_slot; i++) {
5635 /* POW(a,b) = EXP2(b * LOG2(a))*/
5636 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5637 alu.op = ALU_OP1_EXP_IEEE;
5638 alu.src[0].sel = ctx->temp_reg;
5639
5640 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5641 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5642 if (i == last_slot - 1)
5643 alu.last = 1;
5644 r = r600_bytecode_add_alu(ctx->bc, &alu);
5645 if (r)
5646 return r;
5647 }
5648 return 0;
5649 }
5650
5651 static int tgsi_pow(struct r600_shader_ctx *ctx)
5652 {
5653 struct r600_bytecode_alu alu;
5654 int r;
5655
5656 /* LOG2(a) */
5657 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5658 alu.op = ALU_OP1_LOG_IEEE;
5659 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5660 alu.dst.sel = ctx->temp_reg;
5661 alu.dst.write = 1;
5662 alu.last = 1;
5663 r = r600_bytecode_add_alu(ctx->bc, &alu);
5664 if (r)
5665 return r;
5666 /* b * LOG2(a) */
5667 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5668 alu.op = ALU_OP2_MUL;
5669 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5670 alu.src[1].sel = ctx->temp_reg;
5671 alu.dst.sel = ctx->temp_reg;
5672 alu.dst.write = 1;
5673 alu.last = 1;
5674 r = r600_bytecode_add_alu(ctx->bc, &alu);
5675 if (r)
5676 return r;
5677 /* POW(a,b) = EXP2(b * LOG2(a))*/
5678 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5679 alu.op = ALU_OP1_EXP_IEEE;
5680 alu.src[0].sel = ctx->temp_reg;
5681 alu.dst.sel = ctx->temp_reg;
5682 alu.dst.write = 1;
5683 alu.last = 1;
5684 r = r600_bytecode_add_alu(ctx->bc, &alu);
5685 if (r)
5686 return r;
5687 return tgsi_helper_tempx_replicate(ctx);
5688 }
5689
5690 static int emit_mul_int_op(struct r600_bytecode *bc,
5691 struct r600_bytecode_alu *alu_src)
5692 {
5693 struct r600_bytecode_alu alu;
5694 int i, r;
5695 alu = *alu_src;
5696 if (bc->chip_class == CAYMAN) {
5697 for (i = 0; i < 4; i++) {
5698 alu.dst.chan = i;
5699 alu.dst.write = (i == alu_src->dst.chan);
5700 alu.last = (i == 3);
5701
5702 r = r600_bytecode_add_alu(bc, &alu);
5703 if (r)
5704 return r;
5705 }
5706 } else {
5707 alu.last = 1;
5708 r = r600_bytecode_add_alu(bc, &alu);
5709 if (r)
5710 return r;
5711 }
5712 return 0;
5713 }
5714
5715 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5716 {
5717 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5718 struct r600_bytecode_alu alu;
5719 int i, r, j;
5720 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5721 int tmp0 = ctx->temp_reg;
5722 int tmp1 = r600_get_temp(ctx);
5723 int tmp2 = r600_get_temp(ctx);
5724 int tmp3 = r600_get_temp(ctx);
5725 /* Unsigned path:
5726 *
5727 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5728 *
5729 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5730 * 2. tmp0.z = lo (tmp0.x * src2)
5731 * 3. tmp0.w = -tmp0.z
5732 * 4. tmp0.y = hi (tmp0.x * src2)
5733 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5734 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5735 * 7. tmp1.x = tmp0.x - tmp0.w
5736 * 8. tmp1.y = tmp0.x + tmp0.w
5737 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5738 * 10. tmp0.z = hi(tmp0.x * src1) = q
5739 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5740 *
5741 * 12. tmp0.w = src1 - tmp0.y = r
5742 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5743 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5744 *
5745 * if DIV
5746 *
5747 * 15. tmp1.z = tmp0.z + 1 = q + 1
5748 * 16. tmp1.w = tmp0.z - 1 = q - 1
5749 *
5750 * else MOD
5751 *
5752 * 15. tmp1.z = tmp0.w - src2 = r - src2
5753 * 16. tmp1.w = tmp0.w + src2 = r + src2
5754 *
5755 * endif
5756 *
5757 * 17. tmp1.x = tmp1.x & tmp1.y
5758 *
5759 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5760 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5761 *
5762 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5763 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5764 *
5765 * Signed path:
5766 *
5767 * Same as unsigned, using abs values of the operands,
5768 * and fixing the sign of the result in the end.
5769 */
5770
5771 for (i = 0; i < 4; i++) {
5772 if (!(write_mask & (1<<i)))
5773 continue;
5774
5775 if (signed_op) {
5776
5777 /* tmp2.x = -src0 */
5778 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5779 alu.op = ALU_OP2_SUB_INT;
5780
5781 alu.dst.sel = tmp2;
5782 alu.dst.chan = 0;
5783 alu.dst.write = 1;
5784
5785 alu.src[0].sel = V_SQ_ALU_SRC_0;
5786
5787 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5788
5789 alu.last = 1;
5790 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5791 return r;
5792
5793 /* tmp2.y = -src1 */
5794 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5795 alu.op = ALU_OP2_SUB_INT;
5796
5797 alu.dst.sel = tmp2;
5798 alu.dst.chan = 1;
5799 alu.dst.write = 1;
5800
5801 alu.src[0].sel = V_SQ_ALU_SRC_0;
5802
5803 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5804
5805 alu.last = 1;
5806 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5807 return r;
5808
5809 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5810 /* it will be a sign of the quotient */
5811 if (!mod) {
5812
5813 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5814 alu.op = ALU_OP2_XOR_INT;
5815
5816 alu.dst.sel = tmp2;
5817 alu.dst.chan = 2;
5818 alu.dst.write = 1;
5819
5820 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5821 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5822
5823 alu.last = 1;
5824 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5825 return r;
5826 }
5827
5828 /* tmp2.x = |src0| */
5829 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5830 alu.op = ALU_OP3_CNDGE_INT;
5831 alu.is_op3 = 1;
5832
5833 alu.dst.sel = tmp2;
5834 alu.dst.chan = 0;
5835 alu.dst.write = 1;
5836
5837 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5838 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5839 alu.src[2].sel = tmp2;
5840 alu.src[2].chan = 0;
5841
5842 alu.last = 1;
5843 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5844 return r;
5845
5846 /* tmp2.y = |src1| */
5847 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5848 alu.op = ALU_OP3_CNDGE_INT;
5849 alu.is_op3 = 1;
5850
5851 alu.dst.sel = tmp2;
5852 alu.dst.chan = 1;
5853 alu.dst.write = 1;
5854
5855 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5856 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5857 alu.src[2].sel = tmp2;
5858 alu.src[2].chan = 1;
5859
5860 alu.last = 1;
5861 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5862 return r;
5863
5864 }
5865
5866 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5867 if (ctx->bc->chip_class == CAYMAN) {
5868 /* tmp3.x = u2f(src2) */
5869 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5870 alu.op = ALU_OP1_UINT_TO_FLT;
5871
5872 alu.dst.sel = tmp3;
5873 alu.dst.chan = 0;
5874 alu.dst.write = 1;
5875
5876 if (signed_op) {
5877 alu.src[0].sel = tmp2;
5878 alu.src[0].chan = 1;
5879 } else {
5880 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5881 }
5882
5883 alu.last = 1;
5884 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5885 return r;
5886
5887 /* tmp0.x = recip(tmp3.x) */
5888 for (j = 0 ; j < 3; j++) {
5889 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5890 alu.op = ALU_OP1_RECIP_IEEE;
5891
5892 alu.dst.sel = tmp0;
5893 alu.dst.chan = j;
5894 alu.dst.write = (j == 0);
5895
5896 alu.src[0].sel = tmp3;
5897 alu.src[0].chan = 0;
5898
5899 if (j == 2)
5900 alu.last = 1;
5901 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5902 return r;
5903 }
5904
5905 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5906 alu.op = ALU_OP2_MUL;
5907
5908 alu.src[0].sel = tmp0;
5909 alu.src[0].chan = 0;
5910
5911 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5912 alu.src[1].value = 0x4f800000;
5913
5914 alu.dst.sel = tmp3;
5915 alu.dst.write = 1;
5916 alu.last = 1;
5917 r = r600_bytecode_add_alu(ctx->bc, &alu);
5918 if (r)
5919 return r;
5920
5921 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5922 alu.op = ALU_OP1_FLT_TO_UINT;
5923
5924 alu.dst.sel = tmp0;
5925 alu.dst.chan = 0;
5926 alu.dst.write = 1;
5927
5928 alu.src[0].sel = tmp3;
5929 alu.src[0].chan = 0;
5930
5931 alu.last = 1;
5932 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5933 return r;
5934
5935 } else {
5936 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5937 alu.op = ALU_OP1_RECIP_UINT;
5938
5939 alu.dst.sel = tmp0;
5940 alu.dst.chan = 0;
5941 alu.dst.write = 1;
5942
5943 if (signed_op) {
5944 alu.src[0].sel = tmp2;
5945 alu.src[0].chan = 1;
5946 } else {
5947 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5948 }
5949
5950 alu.last = 1;
5951 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5952 return r;
5953 }
5954
5955 /* 2. tmp0.z = lo (tmp0.x * src2) */
5956 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5957 alu.op = ALU_OP2_MULLO_UINT;
5958
5959 alu.dst.sel = tmp0;
5960 alu.dst.chan = 2;
5961 alu.dst.write = 1;
5962
5963 alu.src[0].sel = tmp0;
5964 alu.src[0].chan = 0;
5965 if (signed_op) {
5966 alu.src[1].sel = tmp2;
5967 alu.src[1].chan = 1;
5968 } else {
5969 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5970 }
5971
5972 if ((r = emit_mul_int_op(ctx->bc, &alu)))
5973 return r;
5974
5975 /* 3. tmp0.w = -tmp0.z */
5976 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5977 alu.op = ALU_OP2_SUB_INT;
5978
5979 alu.dst.sel = tmp0;
5980 alu.dst.chan = 3;
5981 alu.dst.write = 1;
5982
5983 alu.src[0].sel = V_SQ_ALU_SRC_0;
5984 alu.src[1].sel = tmp0;
5985 alu.src[1].chan = 2;
5986
5987 alu.last = 1;
5988 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5989 return r;
5990
5991 /* 4. tmp0.y = hi (tmp0.x * src2) */
5992 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5993 alu.op = ALU_OP2_MULHI_UINT;
5994
5995 alu.dst.sel = tmp0;
5996 alu.dst.chan = 1;
5997 alu.dst.write = 1;
5998
5999 alu.src[0].sel = tmp0;
6000 alu.src[0].chan = 0;
6001
6002 if (signed_op) {
6003 alu.src[1].sel = tmp2;
6004 alu.src[1].chan = 1;
6005 } else {
6006 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
6007 }
6008
6009 if ((r = emit_mul_int_op(ctx->bc, &alu)))
6010 return r;
6011
6012 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
6013 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6014 alu.op = ALU_OP3_CNDE_INT;
6015 alu.is_op3 = 1;
6016
6017 alu.dst.sel = tmp0;
6018 alu.dst.chan = 2;
6019 alu.dst.write = 1;
6020
6021 alu.src[0].sel = tmp0;
6022 alu.src[0].chan = 1;
6023 alu.src[1].sel = tmp0;
6024 alu.src[1].chan = 3;
6025 alu.src[2].sel = tmp0;
6026 alu.src[2].chan = 2;
6027
6028 alu.last = 1;
6029 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6030 return r;
6031
6032 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
6033 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6034 alu.op = ALU_OP2_MULHI_UINT;
6035
6036 alu.dst.sel = tmp0;
6037 alu.dst.chan = 3;
6038 alu.dst.write = 1;
6039
6040 alu.src[0].sel = tmp0;
6041 alu.src[0].chan = 2;
6042
6043 alu.src[1].sel = tmp0;
6044 alu.src[1].chan = 0;
6045
6046 if ((r = emit_mul_int_op(ctx->bc, &alu)))
6047 return r;
6048
6049 /* 7. tmp1.x = tmp0.x - tmp0.w */
6050 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6051 alu.op = ALU_OP2_SUB_INT;
6052
6053 alu.dst.sel = tmp1;
6054 alu.dst.chan = 0;
6055 alu.dst.write = 1;
6056
6057 alu.src[0].sel = tmp0;
6058 alu.src[0].chan = 0;
6059 alu.src[1].sel = tmp0;
6060 alu.src[1].chan = 3;
6061
6062 alu.last = 1;
6063 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6064 return r;
6065
6066 /* 8. tmp1.y = tmp0.x + tmp0.w */
6067 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6068 alu.op = ALU_OP2_ADD_INT;
6069
6070 alu.dst.sel = tmp1;
6071 alu.dst.chan = 1;
6072 alu.dst.write = 1;
6073
6074 alu.src[0].sel = tmp0;
6075 alu.src[0].chan = 0;
6076 alu.src[1].sel = tmp0;
6077 alu.src[1].chan = 3;
6078
6079 alu.last = 1;
6080 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6081 return r;
6082
6083 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
6084 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6085 alu.op = ALU_OP3_CNDE_INT;
6086 alu.is_op3 = 1;
6087
6088 alu.dst.sel = tmp0;
6089 alu.dst.chan = 0;
6090 alu.dst.write = 1;
6091
6092 alu.src[0].sel = tmp0;
6093 alu.src[0].chan = 1;
6094 alu.src[1].sel = tmp1;
6095 alu.src[1].chan = 1;
6096 alu.src[2].sel = tmp1;
6097 alu.src[2].chan = 0;
6098
6099 alu.last = 1;
6100 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6101 return r;
6102
6103 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
6104 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6105 alu.op = ALU_OP2_MULHI_UINT;
6106
6107 alu.dst.sel = tmp0;
6108 alu.dst.chan = 2;
6109 alu.dst.write = 1;
6110
6111 alu.src[0].sel = tmp0;
6112 alu.src[0].chan = 0;
6113
6114 if (signed_op) {
6115 alu.src[1].sel = tmp2;
6116 alu.src[1].chan = 0;
6117 } else {
6118 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6119 }
6120
6121 if ((r = emit_mul_int_op(ctx->bc, &alu)))
6122 return r;
6123
6124 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
6125 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6126 alu.op = ALU_OP2_MULLO_UINT;
6127
6128 alu.dst.sel = tmp0;
6129 alu.dst.chan = 1;
6130 alu.dst.write = 1;
6131
6132 if (signed_op) {
6133 alu.src[0].sel = tmp2;
6134 alu.src[0].chan = 1;
6135 } else {
6136 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6137 }
6138
6139 alu.src[1].sel = tmp0;
6140 alu.src[1].chan = 2;
6141
6142 if ((r = emit_mul_int_op(ctx->bc, &alu)))
6143 return r;
6144
6145 /* 12. tmp0.w = src1 - tmp0.y = r */
6146 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6147 alu.op = ALU_OP2_SUB_INT;
6148
6149 alu.dst.sel = tmp0;
6150 alu.dst.chan = 3;
6151 alu.dst.write = 1;
6152
6153 if (signed_op) {
6154 alu.src[0].sel = tmp2;
6155 alu.src[0].chan = 0;
6156 } else {
6157 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6158 }
6159
6160 alu.src[1].sel = tmp0;
6161 alu.src[1].chan = 1;
6162
6163 alu.last = 1;
6164 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6165 return r;
6166
6167 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
6168 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6169 alu.op = ALU_OP2_SETGE_UINT;
6170
6171 alu.dst.sel = tmp1;
6172 alu.dst.chan = 0;
6173 alu.dst.write = 1;
6174
6175 alu.src[0].sel = tmp0;
6176 alu.src[0].chan = 3;
6177 if (signed_op) {
6178 alu.src[1].sel = tmp2;
6179 alu.src[1].chan = 1;
6180 } else {
6181 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
6182 }
6183
6184 alu.last = 1;
6185 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6186 return r;
6187
6188 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
6189 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6190 alu.op = ALU_OP2_SETGE_UINT;
6191
6192 alu.dst.sel = tmp1;
6193 alu.dst.chan = 1;
6194 alu.dst.write = 1;
6195
6196 if (signed_op) {
6197 alu.src[0].sel = tmp2;
6198 alu.src[0].chan = 0;
6199 } else {
6200 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6201 }
6202
6203 alu.src[1].sel = tmp0;
6204 alu.src[1].chan = 1;
6205
6206 alu.last = 1;
6207 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6208 return r;
6209
6210 if (mod) { /* UMOD */
6211
6212 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
6213 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6214 alu.op = ALU_OP2_SUB_INT;
6215
6216 alu.dst.sel = tmp1;
6217 alu.dst.chan = 2;
6218 alu.dst.write = 1;
6219
6220 alu.src[0].sel = tmp0;
6221 alu.src[0].chan = 3;
6222
6223 if (signed_op) {
6224 alu.src[1].sel = tmp2;
6225 alu.src[1].chan = 1;
6226 } else {
6227 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
6228 }
6229
6230 alu.last = 1;
6231 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6232 return r;
6233
6234 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
6235 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6236 alu.op = ALU_OP2_ADD_INT;
6237
6238 alu.dst.sel = tmp1;
6239 alu.dst.chan = 3;
6240 alu.dst.write = 1;
6241
6242 alu.src[0].sel = tmp0;
6243 alu.src[0].chan = 3;
6244 if (signed_op) {
6245 alu.src[1].sel = tmp2;
6246 alu.src[1].chan = 1;
6247 } else {
6248 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
6249 }
6250
6251 alu.last = 1;
6252 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6253 return r;
6254
6255 } else { /* UDIV */
6256
6257 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
6258 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6259 alu.op = ALU_OP2_ADD_INT;
6260
6261 alu.dst.sel = tmp1;
6262 alu.dst.chan = 2;
6263 alu.dst.write = 1;
6264
6265 alu.src[0].sel = tmp0;
6266 alu.src[0].chan = 2;
6267 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6268
6269 alu.last = 1;
6270 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6271 return r;
6272
6273 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
6274 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6275 alu.op = ALU_OP2_ADD_INT;
6276
6277 alu.dst.sel = tmp1;
6278 alu.dst.chan = 3;
6279 alu.dst.write = 1;
6280
6281 alu.src[0].sel = tmp0;
6282 alu.src[0].chan = 2;
6283 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
6284
6285 alu.last = 1;
6286 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6287 return r;
6288
6289 }
6290
6291 /* 17. tmp1.x = tmp1.x & tmp1.y */
6292 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6293 alu.op = ALU_OP2_AND_INT;
6294
6295 alu.dst.sel = tmp1;
6296 alu.dst.chan = 0;
6297 alu.dst.write = 1;
6298
6299 alu.src[0].sel = tmp1;
6300 alu.src[0].chan = 0;
6301 alu.src[1].sel = tmp1;
6302 alu.src[1].chan = 1;
6303
6304 alu.last = 1;
6305 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6306 return r;
6307
6308 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
6309 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
6310 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6311 alu.op = ALU_OP3_CNDE_INT;
6312 alu.is_op3 = 1;
6313
6314 alu.dst.sel = tmp0;
6315 alu.dst.chan = 2;
6316 alu.dst.write = 1;
6317
6318 alu.src[0].sel = tmp1;
6319 alu.src[0].chan = 0;
6320 alu.src[1].sel = tmp0;
6321 alu.src[1].chan = mod ? 3 : 2;
6322 alu.src[2].sel = tmp1;
6323 alu.src[2].chan = 2;
6324
6325 alu.last = 1;
6326 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6327 return r;
6328
6329 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
6330 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6331 alu.op = ALU_OP3_CNDE_INT;
6332 alu.is_op3 = 1;
6333
6334 if (signed_op) {
6335 alu.dst.sel = tmp0;
6336 alu.dst.chan = 2;
6337 alu.dst.write = 1;
6338 } else {
6339 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6340 }
6341
6342 alu.src[0].sel = tmp1;
6343 alu.src[0].chan = 1;
6344 alu.src[1].sel = tmp1;
6345 alu.src[1].chan = 3;
6346 alu.src[2].sel = tmp0;
6347 alu.src[2].chan = 2;
6348
6349 alu.last = 1;
6350 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6351 return r;
6352
6353 if (signed_op) {
6354
6355 /* fix the sign of the result */
6356
6357 if (mod) {
6358
6359 /* tmp0.x = -tmp0.z */
6360 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6361 alu.op = ALU_OP2_SUB_INT;
6362
6363 alu.dst.sel = tmp0;
6364 alu.dst.chan = 0;
6365 alu.dst.write = 1;
6366
6367 alu.src[0].sel = V_SQ_ALU_SRC_0;
6368 alu.src[1].sel = tmp0;
6369 alu.src[1].chan = 2;
6370
6371 alu.last = 1;
6372 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6373 return r;
6374
6375 /* sign of the remainder is the same as the sign of src0 */
6376 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
6377 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6378 alu.op = ALU_OP3_CNDGE_INT;
6379 alu.is_op3 = 1;
6380
6381 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6382
6383 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6384 alu.src[1].sel = tmp0;
6385 alu.src[1].chan = 2;
6386 alu.src[2].sel = tmp0;
6387 alu.src[2].chan = 0;
6388
6389 alu.last = 1;
6390 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6391 return r;
6392
6393 } else {
6394
6395 /* tmp0.x = -tmp0.z */
6396 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6397 alu.op = ALU_OP2_SUB_INT;
6398
6399 alu.dst.sel = tmp0;
6400 alu.dst.chan = 0;
6401 alu.dst.write = 1;
6402
6403 alu.src[0].sel = V_SQ_ALU_SRC_0;
6404 alu.src[1].sel = tmp0;
6405 alu.src[1].chan = 2;
6406
6407 alu.last = 1;
6408 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6409 return r;
6410
6411 /* fix the quotient sign (same as the sign of src0*src1) */
6412 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
6413 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6414 alu.op = ALU_OP3_CNDGE_INT;
6415 alu.is_op3 = 1;
6416
6417 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6418
6419 alu.src[0].sel = tmp2;
6420 alu.src[0].chan = 2;
6421 alu.src[1].sel = tmp0;
6422 alu.src[1].chan = 2;
6423 alu.src[2].sel = tmp0;
6424 alu.src[2].chan = 0;
6425
6426 alu.last = 1;
6427 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6428 return r;
6429 }
6430 }
6431 }
6432 return 0;
6433 }
6434
6435 static int tgsi_udiv(struct r600_shader_ctx *ctx)
6436 {
6437 return tgsi_divmod(ctx, 0, 0);
6438 }
6439
6440 static int tgsi_umod(struct r600_shader_ctx *ctx)
6441 {
6442 return tgsi_divmod(ctx, 1, 0);
6443 }
6444
6445 static int tgsi_idiv(struct r600_shader_ctx *ctx)
6446 {
6447 return tgsi_divmod(ctx, 0, 1);
6448 }
6449
6450 static int tgsi_imod(struct r600_shader_ctx *ctx)
6451 {
6452 return tgsi_divmod(ctx, 1, 1);
6453 }
6454
6455
6456 static int tgsi_f2i(struct r600_shader_ctx *ctx)
6457 {
6458 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6459 struct r600_bytecode_alu alu;
6460 int i, r;
6461 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6462 int last_inst = tgsi_last_instruction(write_mask);
6463
6464 for (i = 0; i < 4; i++) {
6465 if (!(write_mask & (1<<i)))
6466 continue;
6467
6468 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6469 alu.op = ALU_OP1_TRUNC;
6470
6471 alu.dst.sel = ctx->temp_reg;
6472 alu.dst.chan = i;
6473 alu.dst.write = 1;
6474
6475 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6476 if (i == last_inst)
6477 alu.last = 1;
6478 r = r600_bytecode_add_alu(ctx->bc, &alu);
6479 if (r)
6480 return r;
6481 }
6482
6483 for (i = 0; i < 4; i++) {
6484 if (!(write_mask & (1<<i)))
6485 continue;
6486
6487 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6488 alu.op = ctx->inst_info->op;
6489
6490 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6491
6492 alu.src[0].sel = ctx->temp_reg;
6493 alu.src[0].chan = i;
6494
6495 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
6496 alu.last = 1;
6497 r = r600_bytecode_add_alu(ctx->bc, &alu);
6498 if (r)
6499 return r;
6500 }
6501
6502 return 0;
6503 }
6504
6505 static int tgsi_iabs(struct r600_shader_ctx *ctx)
6506 {
6507 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6508 struct r600_bytecode_alu alu;
6509 int i, r;
6510 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6511 int last_inst = tgsi_last_instruction(write_mask);
6512
6513 /* tmp = -src */
6514 for (i = 0; i < 4; i++) {
6515 if (!(write_mask & (1<<i)))
6516 continue;
6517
6518 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6519 alu.op = ALU_OP2_SUB_INT;
6520
6521 alu.dst.sel = ctx->temp_reg;
6522 alu.dst.chan = i;
6523 alu.dst.write = 1;
6524
6525 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6526 alu.src[0].sel = V_SQ_ALU_SRC_0;
6527
6528 if (i == last_inst)
6529 alu.last = 1;
6530 r = r600_bytecode_add_alu(ctx->bc, &alu);
6531 if (r)
6532 return r;
6533 }
6534
6535 /* dst = (src >= 0 ? src : tmp) */
6536 for (i = 0; i < 4; i++) {
6537 if (!(write_mask & (1<<i)))
6538 continue;
6539
6540 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6541 alu.op = ALU_OP3_CNDGE_INT;
6542 alu.is_op3 = 1;
6543 alu.dst.write = 1;
6544
6545 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6546
6547 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6548 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6549 alu.src[2].sel = ctx->temp_reg;
6550 alu.src[2].chan = i;
6551
6552 if (i == last_inst)
6553 alu.last = 1;
6554 r = r600_bytecode_add_alu(ctx->bc, &alu);
6555 if (r)
6556 return r;
6557 }
6558 return 0;
6559 }
6560
6561 static int tgsi_issg(struct r600_shader_ctx *ctx)
6562 {
6563 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6564 struct r600_bytecode_alu alu;
6565 int i, r;
6566 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6567 int last_inst = tgsi_last_instruction(write_mask);
6568
6569 /* tmp = (src >= 0 ? src : -1) */
6570 for (i = 0; i < 4; i++) {
6571 if (!(write_mask & (1<<i)))
6572 continue;
6573
6574 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6575 alu.op = ALU_OP3_CNDGE_INT;
6576 alu.is_op3 = 1;
6577
6578 alu.dst.sel = ctx->temp_reg;
6579 alu.dst.chan = i;
6580 alu.dst.write = 1;
6581
6582 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6583 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6584 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6585
6586 if (i == last_inst)
6587 alu.last = 1;
6588 r = r600_bytecode_add_alu(ctx->bc, &alu);
6589 if (r)
6590 return r;
6591 }
6592
6593 /* dst = (tmp > 0 ? 1 : tmp) */
6594 for (i = 0; i < 4; i++) {
6595 if (!(write_mask & (1<<i)))
6596 continue;
6597
6598 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6599 alu.op = ALU_OP3_CNDGT_INT;
6600 alu.is_op3 = 1;
6601 alu.dst.write = 1;
6602
6603 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6604
6605 alu.src[0].sel = ctx->temp_reg;
6606 alu.src[0].chan = i;
6607
6608 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6609
6610 alu.src[2].sel = ctx->temp_reg;
6611 alu.src[2].chan = i;
6612
6613 if (i == last_inst)
6614 alu.last = 1;
6615 r = r600_bytecode_add_alu(ctx->bc, &alu);
6616 if (r)
6617 return r;
6618 }
6619 return 0;
6620 }
6621
6622
6623
6624 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6625 {
6626 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6627 struct r600_bytecode_alu alu;
6628 int i, r;
6629
6630 /* tmp = (src > 0 ? 1 : src) */
6631 for (i = 0; i < 4; i++) {
6632 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6633 alu.op = ALU_OP3_CNDGT;
6634 alu.is_op3 = 1;
6635
6636 alu.dst.sel = ctx->temp_reg;
6637 alu.dst.chan = i;
6638
6639 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6640 alu.src[1].sel = V_SQ_ALU_SRC_1;
6641 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6642
6643 if (i == 3)
6644 alu.last = 1;
6645 r = r600_bytecode_add_alu(ctx->bc, &alu);
6646 if (r)
6647 return r;
6648 }
6649
6650 /* dst = (-tmp > 0 ? -1 : tmp) */
6651 for (i = 0; i < 4; i++) {
6652 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6653 alu.op = ALU_OP3_CNDGT;
6654 alu.is_op3 = 1;
6655 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6656
6657 alu.src[0].sel = ctx->temp_reg;
6658 alu.src[0].chan = i;
6659 alu.src[0].neg = 1;
6660
6661 alu.src[1].sel = V_SQ_ALU_SRC_1;
6662 alu.src[1].neg = 1;
6663
6664 alu.src[2].sel = ctx->temp_reg;
6665 alu.src[2].chan = i;
6666
6667 if (i == 3)
6668 alu.last = 1;
6669 r = r600_bytecode_add_alu(ctx->bc, &alu);
6670 if (r)
6671 return r;
6672 }
6673 return 0;
6674 }
6675
6676 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6677 {
6678 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6679 struct r600_bytecode_alu alu;
6680 int i, r, t1, t2;
6681
6682 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6683 int last_inst = tgsi_last_instruction(write_mask);
6684
6685 t1 = r600_get_temp(ctx);
6686
6687 for (i = 0; i < 4; i++) {
6688 if (!(write_mask & (1<<i)))
6689 continue;
6690
6691 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6692 alu.op = ALU_OP2_SETGE_INT;
6693 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6694 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6695 alu.src[1].value = 32;
6696 alu.dst.sel = ctx->temp_reg;
6697 alu.dst.chan = i;
6698 alu.dst.write = 1;
6699 alu.last = i == last_inst;
6700 r = r600_bytecode_add_alu(ctx->bc, &alu);
6701 if (r)
6702 return r;
6703 }
6704
6705 for (i = 0; i < 4; i++) {
6706 if (!(write_mask & (1<<i)))
6707 continue;
6708
6709 /* create mask tmp */
6710 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6711 alu.op = ALU_OP2_BFM_INT;
6712 alu.dst.sel = t1;
6713 alu.dst.chan = i;
6714 alu.dst.write = 1;
6715 alu.last = i == last_inst;
6716
6717 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6718 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6719
6720 r = r600_bytecode_add_alu(ctx->bc, &alu);
6721 if (r)
6722 return r;
6723 }
6724
6725 t2 = r600_get_temp(ctx);
6726
6727 for (i = 0; i < 4; i++) {
6728 if (!(write_mask & (1<<i)))
6729 continue;
6730
6731 /* shift insert left */
6732 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6733 alu.op = ALU_OP2_LSHL_INT;
6734 alu.dst.sel = t2;
6735 alu.dst.chan = i;
6736 alu.dst.write = 1;
6737 alu.last = i == last_inst;
6738
6739 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6740 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6741
6742 r = r600_bytecode_add_alu(ctx->bc, &alu);
6743 if (r)
6744 return r;
6745 }
6746
6747 for (i = 0; i < 4; i++) {
6748 if (!(write_mask & (1<<i)))
6749 continue;
6750
6751 /* actual bitfield insert */
6752 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6753 alu.op = ALU_OP3_BFI_INT;
6754 alu.is_op3 = 1;
6755 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6756 alu.dst.chan = i;
6757 alu.dst.write = 1;
6758 alu.last = i == last_inst;
6759
6760 alu.src[0].sel = t1;
6761 alu.src[0].chan = i;
6762 alu.src[1].sel = t2;
6763 alu.src[1].chan = i;
6764 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6765
6766 r = r600_bytecode_add_alu(ctx->bc, &alu);
6767 if (r)
6768 return r;
6769 }
6770
6771 for (i = 0; i < 4; i++) {
6772 if (!(write_mask & (1<<i)))
6773 continue;
6774 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6775 alu.op = ALU_OP3_CNDE_INT;
6776 alu.is_op3 = 1;
6777 alu.src[0].sel = ctx->temp_reg;
6778 alu.src[0].chan = i;
6779 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6780
6781 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6782
6783 alu.src[1].sel = alu.dst.sel;
6784 alu.src[1].chan = i;
6785
6786 alu.last = i == last_inst;
6787 r = r600_bytecode_add_alu(ctx->bc, &alu);
6788 if (r)
6789 return r;
6790 }
6791 return 0;
6792 }
6793
6794 static int tgsi_msb(struct r600_shader_ctx *ctx)
6795 {
6796 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6797 struct r600_bytecode_alu alu;
6798 int i, r, t1, t2;
6799
6800 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6801 int last_inst = tgsi_last_instruction(write_mask);
6802
6803 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6804 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6805
6806 t1 = ctx->temp_reg;
6807
6808 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6809 for (i = 0; i < 4; i++) {
6810 if (!(write_mask & (1<<i)))
6811 continue;
6812
6813 /* t1 = FFBH_INT / FFBH_UINT */
6814 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6815 alu.op = ctx->inst_info->op;
6816 alu.dst.sel = t1;
6817 alu.dst.chan = i;
6818 alu.dst.write = 1;
6819 alu.last = i == last_inst;
6820
6821 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6822
6823 r = r600_bytecode_add_alu(ctx->bc, &alu);
6824 if (r)
6825 return r;
6826 }
6827
6828 t2 = r600_get_temp(ctx);
6829
6830 for (i = 0; i < 4; i++) {
6831 if (!(write_mask & (1<<i)))
6832 continue;
6833
6834 /* t2 = 31 - t1 */
6835 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6836 alu.op = ALU_OP2_SUB_INT;
6837 alu.dst.sel = t2;
6838 alu.dst.chan = i;
6839 alu.dst.write = 1;
6840 alu.last = i == last_inst;
6841
6842 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6843 alu.src[0].value = 31;
6844 alu.src[1].sel = t1;
6845 alu.src[1].chan = i;
6846
6847 r = r600_bytecode_add_alu(ctx->bc, &alu);
6848 if (r)
6849 return r;
6850 }
6851
6852 for (i = 0; i < 4; i++) {
6853 if (!(write_mask & (1<<i)))
6854 continue;
6855
6856 /* result = t1 >= 0 ? t2 : t1 */
6857 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6858 alu.op = ALU_OP3_CNDGE_INT;
6859 alu.is_op3 = 1;
6860 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6861 alu.dst.chan = i;
6862 alu.dst.write = 1;
6863 alu.last = i == last_inst;
6864
6865 alu.src[0].sel = t1;
6866 alu.src[0].chan = i;
6867 alu.src[1].sel = t2;
6868 alu.src[1].chan = i;
6869 alu.src[2].sel = t1;
6870 alu.src[2].chan = i;
6871
6872 r = r600_bytecode_add_alu(ctx->bc, &alu);
6873 if (r)
6874 return r;
6875 }
6876
6877 return 0;
6878 }
6879
6880 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6881 {
6882 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6883 struct r600_bytecode_alu alu;
6884 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6885 unsigned location;
6886 const int input = inst->Src[0].Register.Index + ctx->shader->nsys_inputs;
6887
6888 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6889
6890 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6891 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6892 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6893 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6894 }
6895 else {
6896 location = TGSI_INTERPOLATE_LOC_CENTROID;
6897 }
6898
6899 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6900 if (k < 0)
6901 k = 0;
6902 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6903 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6904
6905 /* NOTE: currently offset is not perspective correct */
6906 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6907 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6908 int sample_gpr = -1;
6909 int gradientsH, gradientsV;
6910 struct r600_bytecode_tex tex;
6911
6912 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6913 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6914 }
6915
6916 gradientsH = r600_get_temp(ctx);
6917 gradientsV = r600_get_temp(ctx);
6918 for (i = 0; i < 2; i++) {
6919 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6920 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6921 tex.src_gpr = interp_gpr;
6922 tex.src_sel_x = interp_base_chan + 0;
6923 tex.src_sel_y = interp_base_chan + 1;
6924 tex.src_sel_z = 0;
6925 tex.src_sel_w = 0;
6926 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6927 tex.dst_sel_x = 0;
6928 tex.dst_sel_y = 1;
6929 tex.dst_sel_z = 7;
6930 tex.dst_sel_w = 7;
6931 tex.inst_mod = 1; // Use per pixel gradient calculation
6932 tex.sampler_id = 0;
6933 tex.resource_id = tex.sampler_id;
6934 r = r600_bytecode_add_tex(ctx->bc, &tex);
6935 if (r)
6936 return r;
6937 }
6938
6939 for (i = 0; i < 2; i++) {
6940 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6941 alu.op = ALU_OP3_MULADD;
6942 alu.is_op3 = 1;
6943 alu.src[0].sel = gradientsH;
6944 alu.src[0].chan = i;
6945 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6946 alu.src[1].sel = sample_gpr;
6947 alu.src[1].chan = 2;
6948 }
6949 else {
6950 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6951 }
6952 alu.src[2].sel = interp_gpr;
6953 alu.src[2].chan = interp_base_chan + i;
6954 alu.dst.sel = ctx->temp_reg;
6955 alu.dst.chan = i;
6956 alu.last = i == 1;
6957
6958 r = r600_bytecode_add_alu(ctx->bc, &alu);
6959 if (r)
6960 return r;
6961 }
6962
6963 for (i = 0; i < 2; i++) {
6964 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6965 alu.op = ALU_OP3_MULADD;
6966 alu.is_op3 = 1;
6967 alu.src[0].sel = gradientsV;
6968 alu.src[0].chan = i;
6969 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6970 alu.src[1].sel = sample_gpr;
6971 alu.src[1].chan = 3;
6972 }
6973 else {
6974 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6975 }
6976 alu.src[2].sel = ctx->temp_reg;
6977 alu.src[2].chan = i;
6978 alu.dst.sel = ctx->temp_reg;
6979 alu.dst.chan = i;
6980 alu.last = i == 1;
6981
6982 r = r600_bytecode_add_alu(ctx->bc, &alu);
6983 if (r)
6984 return r;
6985 }
6986 }
6987
6988 tmp = r600_get_temp(ctx);
6989 for (i = 0; i < 8; i++) {
6990 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6991 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6992
6993 alu.dst.sel = tmp;
6994 if ((i > 1 && i < 6)) {
6995 alu.dst.write = 1;
6996 }
6997 else {
6998 alu.dst.write = 0;
6999 }
7000 alu.dst.chan = i % 4;
7001
7002 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
7003 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
7004 alu.src[0].sel = ctx->temp_reg;
7005 alu.src[0].chan = 1 - (i % 2);
7006 } else {
7007 alu.src[0].sel = interp_gpr;
7008 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
7009 }
7010 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
7011 alu.src[1].chan = 0;
7012
7013 alu.last = i % 4 == 3;
7014 alu.bank_swizzle_force = SQ_ALU_VEC_210;
7015
7016 r = r600_bytecode_add_alu(ctx->bc, &alu);
7017 if (r)
7018 return r;
7019 }
7020
7021 // INTERP can't swizzle dst
7022 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7023 for (i = 0; i <= lasti; i++) {
7024 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7025 continue;
7026
7027 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7028 alu.op = ALU_OP1_MOV;
7029 alu.src[0].sel = tmp;
7030 alu.src[0].chan = ctx->src[0].swizzle[i];
7031 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7032 alu.dst.write = 1;
7033 alu.last = i == lasti;
7034 r = r600_bytecode_add_alu(ctx->bc, &alu);
7035 if (r)
7036 return r;
7037 }
7038
7039 return 0;
7040 }
7041
7042
7043 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
7044 {
7045 struct r600_bytecode_alu alu;
7046 int i, r;
7047
7048 for (i = 0; i < 4; i++) {
7049 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7050 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
7051 alu.op = ALU_OP0_NOP;
7052 alu.dst.chan = i;
7053 } else {
7054 alu.op = ALU_OP1_MOV;
7055 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7056 alu.src[0].sel = ctx->temp_reg;
7057 alu.src[0].chan = i;
7058 }
7059 if (i == 3) {
7060 alu.last = 1;
7061 }
7062 r = r600_bytecode_add_alu(ctx->bc, &alu);
7063 if (r)
7064 return r;
7065 }
7066 return 0;
7067 }
7068
7069 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
7070 unsigned temp, int chan,
7071 struct r600_bytecode_alu_src *bc_src,
7072 const struct r600_shader_src *shader_src)
7073 {
7074 struct r600_bytecode_alu alu;
7075 int r;
7076
7077 r600_bytecode_src(bc_src, shader_src, chan);
7078
7079 /* op3 operands don't support abs modifier */
7080 if (bc_src->abs) {
7081 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
7082 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7083 alu.op = ALU_OP1_MOV;
7084 alu.dst.sel = temp;
7085 alu.dst.chan = chan;
7086 alu.dst.write = 1;
7087
7088 alu.src[0] = *bc_src;
7089 alu.last = true; // sufficient?
7090 r = r600_bytecode_add_alu(ctx->bc, &alu);
7091 if (r)
7092 return r;
7093
7094 memset(bc_src, 0, sizeof(*bc_src));
7095 bc_src->sel = temp;
7096 bc_src->chan = chan;
7097 }
7098 return 0;
7099 }
7100
7101 static int tgsi_op3_dst(struct r600_shader_ctx *ctx, int dst)
7102 {
7103 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7104 struct r600_bytecode_alu alu;
7105 int i, j, r;
7106 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7107 int temp_regs[4];
7108 unsigned op = ctx->inst_info->op;
7109
7110 if (op == ALU_OP3_MULADD_IEEE &&
7111 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
7112 op = ALU_OP3_MULADD;
7113
7114 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7115 temp_regs[j] = 0;
7116 if (ctx->src[j].abs)
7117 temp_regs[j] = r600_get_temp(ctx);
7118 }
7119 for (i = 0; i < lasti + 1; i++) {
7120 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7121 continue;
7122
7123 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7124 alu.op = op;
7125 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7126 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
7127 if (r)
7128 return r;
7129 }
7130
7131 if (dst == -1) {
7132 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7133 } else {
7134 alu.dst.sel = dst;
7135 }
7136 alu.dst.chan = i;
7137 alu.dst.write = 1;
7138 alu.is_op3 = 1;
7139 if (i == lasti) {
7140 alu.last = 1;
7141 }
7142 r = r600_bytecode_add_alu(ctx->bc, &alu);
7143 if (r)
7144 return r;
7145 }
7146 return 0;
7147 }
7148
7149 static int tgsi_op3(struct r600_shader_ctx *ctx)
7150 {
7151 return tgsi_op3_dst(ctx, -1);
7152 }
7153
7154 static int tgsi_dp(struct r600_shader_ctx *ctx)
7155 {
7156 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7157 struct r600_bytecode_alu alu;
7158 int i, j, r;
7159 unsigned op = ctx->inst_info->op;
7160 if (op == ALU_OP2_DOT4_IEEE &&
7161 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
7162 op = ALU_OP2_DOT4;
7163
7164 for (i = 0; i < 4; i++) {
7165 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7166 alu.op = op;
7167 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7168 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
7169 }
7170
7171 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7172 alu.dst.chan = i;
7173 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
7174 /* handle some special cases */
7175 switch (inst->Instruction.Opcode) {
7176 case TGSI_OPCODE_DP2:
7177 if (i > 1) {
7178 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
7179 alu.src[0].chan = alu.src[1].chan = 0;
7180 }
7181 break;
7182 case TGSI_OPCODE_DP3:
7183 if (i > 2) {
7184 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
7185 alu.src[0].chan = alu.src[1].chan = 0;
7186 }
7187 break;
7188 default:
7189 break;
7190 }
7191 if (i == 3) {
7192 alu.last = 1;
7193 }
7194 r = r600_bytecode_add_alu(ctx->bc, &alu);
7195 if (r)
7196 return r;
7197 }
7198 return 0;
7199 }
7200
7201 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
7202 unsigned index)
7203 {
7204 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7205 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
7206 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
7207 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
7208 ctx->src[index].neg || ctx->src[index].abs ||
7209 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
7210 }
7211
7212 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
7213 unsigned index)
7214 {
7215 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7216 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
7217 }
7218
7219 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
7220 {
7221 struct r600_bytecode_vtx vtx;
7222 struct r600_bytecode_alu alu;
7223 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7224 int src_gpr, r, i;
7225 int id = tgsi_tex_get_src_gpr(ctx, 1);
7226 int sampler_index_mode = inst->Src[1].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7227
7228 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
7229 if (src_requires_loading) {
7230 for (i = 0; i < 4; i++) {
7231 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7232 alu.op = ALU_OP1_MOV;
7233 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7234 alu.dst.sel = ctx->temp_reg;
7235 alu.dst.chan = i;
7236 if (i == 3)
7237 alu.last = 1;
7238 alu.dst.write = 1;
7239 r = r600_bytecode_add_alu(ctx->bc, &alu);
7240 if (r)
7241 return r;
7242 }
7243 src_gpr = ctx->temp_reg;
7244 }
7245
7246 memset(&vtx, 0, sizeof(vtx));
7247 vtx.op = FETCH_OP_VFETCH;
7248 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
7249 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
7250 vtx.src_gpr = src_gpr;
7251 vtx.mega_fetch_count = 16;
7252 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7253 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
7254 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
7255 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
7256 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
7257 vtx.use_const_fields = 1;
7258 vtx.buffer_index_mode = sampler_index_mode;
7259
7260 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
7261 return r;
7262
7263 if (ctx->bc->chip_class >= EVERGREEN)
7264 return 0;
7265
7266 for (i = 0; i < 4; i++) {
7267 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7268 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7269 continue;
7270
7271 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7272 alu.op = ALU_OP2_AND_INT;
7273
7274 alu.dst.chan = i;
7275 alu.dst.sel = vtx.dst_gpr;
7276 alu.dst.write = 1;
7277
7278 alu.src[0].sel = vtx.dst_gpr;
7279 alu.src[0].chan = i;
7280
7281 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
7282 alu.src[1].sel += (id * 2);
7283 alu.src[1].chan = i % 4;
7284 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7285
7286 if (i == lasti)
7287 alu.last = 1;
7288 r = r600_bytecode_add_alu(ctx->bc, &alu);
7289 if (r)
7290 return r;
7291 }
7292
7293 if (inst->Dst[0].Register.WriteMask & 3) {
7294 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7295 alu.op = ALU_OP2_OR_INT;
7296
7297 alu.dst.chan = 3;
7298 alu.dst.sel = vtx.dst_gpr;
7299 alu.dst.write = 1;
7300
7301 alu.src[0].sel = vtx.dst_gpr;
7302 alu.src[0].chan = 3;
7303
7304 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
7305 alu.src[1].chan = 0;
7306 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7307
7308 alu.last = 1;
7309 r = r600_bytecode_add_alu(ctx->bc, &alu);
7310 if (r)
7311 return r;
7312 }
7313 return 0;
7314 }
7315
7316 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx, int reg_idx, int offset, int eg_buffer_base)
7317 {
7318 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7319 int r;
7320 int id = tgsi_tex_get_src_gpr(ctx, reg_idx) + offset;
7321 int sampler_index_mode = inst->Src[reg_idx].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7322
7323 if (ctx->bc->chip_class < EVERGREEN) {
7324 struct r600_bytecode_alu alu;
7325 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7326 alu.op = ALU_OP1_MOV;
7327 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7328 /* r600 we have them at channel 2 of the second dword */
7329 alu.src[0].sel += (id * 2) + 1;
7330 alu.src[0].chan = 1;
7331 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7332 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
7333 alu.last = 1;
7334 r = r600_bytecode_add_alu(ctx->bc, &alu);
7335 if (r)
7336 return r;
7337 return 0;
7338 } else {
7339 struct r600_bytecode_vtx vtx;
7340 memset(&vtx, 0, sizeof(vtx));
7341 vtx.op = FETCH_OP_GET_BUFFER_RESINFO;
7342 vtx.buffer_id = id + eg_buffer_base;
7343 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
7344 vtx.src_gpr = 0;
7345 vtx.mega_fetch_count = 16; /* no idea here really... */
7346 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7347 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
7348 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 4 : 7; /* SEL_Y */
7349 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 4 : 7; /* SEL_Z */
7350 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 4 : 7; /* SEL_W */
7351 vtx.data_format = FMT_32_32_32_32;
7352 vtx.buffer_index_mode = sampler_index_mode;
7353
7354 if ((r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx)))
7355 return r;
7356 return 0;
7357 }
7358 }
7359
7360
7361 static int tgsi_tex(struct r600_shader_ctx *ctx)
7362 {
7363 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7364 struct r600_bytecode_tex tex;
7365 struct r600_bytecode_alu alu;
7366 unsigned src_gpr;
7367 int r, i, j;
7368 int opcode;
7369 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
7370 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
7371 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
7372 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
7373
7374 bool txf_add_offsets = inst->Texture.NumOffsets &&
7375 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
7376 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
7377
7378 /* Texture fetch instructions can only use gprs as source.
7379 * Also they cannot negate the source or take the absolute value */
7380 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
7381 tgsi_tex_src_requires_loading(ctx, 0)) ||
7382 read_compressed_msaa || txf_add_offsets;
7383
7384 boolean src_loaded = FALSE;
7385 unsigned sampler_src_reg = 1;
7386 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
7387 boolean has_txq_cube_array_z = false;
7388 unsigned sampler_index_mode;
7389
7390 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
7391 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7392 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
7393 if (inst->Dst[0].Register.WriteMask & 4) {
7394 ctx->shader->has_txq_cube_array_z_comp = true;
7395 has_txq_cube_array_z = true;
7396 }
7397
7398 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
7399 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7400 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
7401 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
7402 sampler_src_reg = 2;
7403
7404 /* TGSI moves the sampler to src reg 3 for TXD */
7405 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
7406 sampler_src_reg = 3;
7407
7408 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7409
7410 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
7411
7412 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
7413 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
7414 if (ctx->bc->chip_class < EVERGREEN)
7415 ctx->shader->uses_tex_buffers = true;
7416 return r600_do_buffer_txq(ctx, 1, 0, R600_MAX_CONST_BUFFERS);
7417 }
7418 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
7419 if (ctx->bc->chip_class < EVERGREEN)
7420 ctx->shader->uses_tex_buffers = true;
7421 return do_vtx_fetch_inst(ctx, src_requires_loading);
7422 }
7423 }
7424
7425 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
7426 int out_chan;
7427 /* Add perspective divide */
7428 if (ctx->bc->chip_class == CAYMAN) {
7429 out_chan = 2;
7430 for (i = 0; i < 3; i++) {
7431 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7432 alu.op = ALU_OP1_RECIP_IEEE;
7433 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7434
7435 alu.dst.sel = ctx->temp_reg;
7436 alu.dst.chan = i;
7437 if (i == 2)
7438 alu.last = 1;
7439 if (out_chan == i)
7440 alu.dst.write = 1;
7441 r = r600_bytecode_add_alu(ctx->bc, &alu);
7442 if (r)
7443 return r;
7444 }
7445
7446 } else {
7447 out_chan = 3;
7448 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7449 alu.op = ALU_OP1_RECIP_IEEE;
7450 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7451
7452 alu.dst.sel = ctx->temp_reg;
7453 alu.dst.chan = out_chan;
7454 alu.last = 1;
7455 alu.dst.write = 1;
7456 r = r600_bytecode_add_alu(ctx->bc, &alu);
7457 if (r)
7458 return r;
7459 }
7460
7461 for (i = 0; i < 3; i++) {
7462 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7463 alu.op = ALU_OP2_MUL;
7464 alu.src[0].sel = ctx->temp_reg;
7465 alu.src[0].chan = out_chan;
7466 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
7467 alu.dst.sel = ctx->temp_reg;
7468 alu.dst.chan = i;
7469 alu.dst.write = 1;
7470 r = r600_bytecode_add_alu(ctx->bc, &alu);
7471 if (r)
7472 return r;
7473 }
7474 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7475 alu.op = ALU_OP1_MOV;
7476 alu.src[0].sel = V_SQ_ALU_SRC_1;
7477 alu.src[0].chan = 0;
7478 alu.dst.sel = ctx->temp_reg;
7479 alu.dst.chan = 3;
7480 alu.last = 1;
7481 alu.dst.write = 1;
7482 r = r600_bytecode_add_alu(ctx->bc, &alu);
7483 if (r)
7484 return r;
7485 src_loaded = TRUE;
7486 src_gpr = ctx->temp_reg;
7487 }
7488
7489
7490 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7491 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7492 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7493 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7494 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
7495
7496 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
7497 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
7498
7499 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
7500 for (i = 0; i < 4; i++) {
7501 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7502 alu.op = ALU_OP2_CUBE;
7503 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
7504 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
7505 alu.dst.sel = ctx->temp_reg;
7506 alu.dst.chan = i;
7507 if (i == 3)
7508 alu.last = 1;
7509 alu.dst.write = 1;
7510 r = r600_bytecode_add_alu(ctx->bc, &alu);
7511 if (r)
7512 return r;
7513 }
7514
7515 /* tmp1.z = RCP_e(|tmp1.z|) */
7516 if (ctx->bc->chip_class == CAYMAN) {
7517 for (i = 0; i < 3; i++) {
7518 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7519 alu.op = ALU_OP1_RECIP_IEEE;
7520 alu.src[0].sel = ctx->temp_reg;
7521 alu.src[0].chan = 2;
7522 alu.src[0].abs = 1;
7523 alu.dst.sel = ctx->temp_reg;
7524 alu.dst.chan = i;
7525 if (i == 2)
7526 alu.dst.write = 1;
7527 if (i == 2)
7528 alu.last = 1;
7529 r = r600_bytecode_add_alu(ctx->bc, &alu);
7530 if (r)
7531 return r;
7532 }
7533 } else {
7534 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7535 alu.op = ALU_OP1_RECIP_IEEE;
7536 alu.src[0].sel = ctx->temp_reg;
7537 alu.src[0].chan = 2;
7538 alu.src[0].abs = 1;
7539 alu.dst.sel = ctx->temp_reg;
7540 alu.dst.chan = 2;
7541 alu.dst.write = 1;
7542 alu.last = 1;
7543 r = r600_bytecode_add_alu(ctx->bc, &alu);
7544 if (r)
7545 return r;
7546 }
7547
7548 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
7549 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
7550 * muladd has no writemask, have to use another temp
7551 */
7552 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7553 alu.op = ALU_OP3_MULADD;
7554 alu.is_op3 = 1;
7555
7556 alu.src[0].sel = ctx->temp_reg;
7557 alu.src[0].chan = 0;
7558 alu.src[1].sel = ctx->temp_reg;
7559 alu.src[1].chan = 2;
7560
7561 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7562 alu.src[2].chan = 0;
7563 alu.src[2].value = u_bitcast_f2u(1.5f);
7564
7565 alu.dst.sel = ctx->temp_reg;
7566 alu.dst.chan = 0;
7567 alu.dst.write = 1;
7568
7569 r = r600_bytecode_add_alu(ctx->bc, &alu);
7570 if (r)
7571 return r;
7572
7573 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7574 alu.op = ALU_OP3_MULADD;
7575 alu.is_op3 = 1;
7576
7577 alu.src[0].sel = ctx->temp_reg;
7578 alu.src[0].chan = 1;
7579 alu.src[1].sel = ctx->temp_reg;
7580 alu.src[1].chan = 2;
7581
7582 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7583 alu.src[2].chan = 0;
7584 alu.src[2].value = u_bitcast_f2u(1.5f);
7585
7586 alu.dst.sel = ctx->temp_reg;
7587 alu.dst.chan = 1;
7588 alu.dst.write = 1;
7589
7590 alu.last = 1;
7591 r = r600_bytecode_add_alu(ctx->bc, &alu);
7592 if (r)
7593 return r;
7594 /* write initial compare value into Z component
7595 - W src 0 for shadow cube
7596 - X src 1 for shadow cube array */
7597 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7598 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7599 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7600 alu.op = ALU_OP1_MOV;
7601 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
7602 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7603 else
7604 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7605 alu.dst.sel = ctx->temp_reg;
7606 alu.dst.chan = 2;
7607 alu.dst.write = 1;
7608 alu.last = 1;
7609 r = r600_bytecode_add_alu(ctx->bc, &alu);
7610 if (r)
7611 return r;
7612 }
7613
7614 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7615 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7616 if (ctx->bc->chip_class >= EVERGREEN) {
7617 int mytmp = r600_get_temp(ctx);
7618 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7619 alu.op = ALU_OP1_MOV;
7620 alu.src[0].sel = ctx->temp_reg;
7621 alu.src[0].chan = 3;
7622 alu.dst.sel = mytmp;
7623 alu.dst.chan = 0;
7624 alu.dst.write = 1;
7625 alu.last = 1;
7626 r = r600_bytecode_add_alu(ctx->bc, &alu);
7627 if (r)
7628 return r;
7629
7630 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7631 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7632 alu.op = ALU_OP3_MULADD;
7633 alu.is_op3 = 1;
7634 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7635 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7636 alu.src[1].chan = 0;
7637 alu.src[1].value = u_bitcast_f2u(8.0f);
7638 alu.src[2].sel = mytmp;
7639 alu.src[2].chan = 0;
7640 alu.dst.sel = ctx->temp_reg;
7641 alu.dst.chan = 3;
7642 alu.dst.write = 1;
7643 alu.last = 1;
7644 r = r600_bytecode_add_alu(ctx->bc, &alu);
7645 if (r)
7646 return r;
7647 } else if (ctx->bc->chip_class < EVERGREEN) {
7648 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7649 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7650 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7651 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7652 tex.src_gpr = r600_get_temp(ctx);
7653 tex.src_sel_x = 0;
7654 tex.src_sel_y = 0;
7655 tex.src_sel_z = 0;
7656 tex.src_sel_w = 0;
7657 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7658 tex.coord_type_x = 1;
7659 tex.coord_type_y = 1;
7660 tex.coord_type_z = 1;
7661 tex.coord_type_w = 1;
7662 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7663 alu.op = ALU_OP1_MOV;
7664 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7665 alu.dst.sel = tex.src_gpr;
7666 alu.dst.chan = 0;
7667 alu.last = 1;
7668 alu.dst.write = 1;
7669 r = r600_bytecode_add_alu(ctx->bc, &alu);
7670 if (r)
7671 return r;
7672
7673 r = r600_bytecode_add_tex(ctx->bc, &tex);
7674 if (r)
7675 return r;
7676 }
7677
7678 }
7679
7680 /* for cube forms of lod and bias we need to route things */
7681 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7682 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7683 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7684 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7685 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7686 alu.op = ALU_OP1_MOV;
7687 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7688 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7689 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7690 else
7691 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7692 alu.dst.sel = ctx->temp_reg;
7693 alu.dst.chan = 2;
7694 alu.last = 1;
7695 alu.dst.write = 1;
7696 r = r600_bytecode_add_alu(ctx->bc, &alu);
7697 if (r)
7698 return r;
7699 }
7700
7701 src_loaded = TRUE;
7702 src_gpr = ctx->temp_reg;
7703 }
7704
7705 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7706 int temp_h = 0, temp_v = 0;
7707 int start_val = 0;
7708
7709 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7710 if (src_loaded == TRUE)
7711 start_val = 1;
7712 else
7713 src_loaded = TRUE;
7714 for (i = start_val; i < 3; i++) {
7715 int treg = r600_get_temp(ctx);
7716
7717 if (i == 0)
7718 src_gpr = treg;
7719 else if (i == 1)
7720 temp_h = treg;
7721 else
7722 temp_v = treg;
7723
7724 for (j = 0; j < 4; j++) {
7725 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7726 alu.op = ALU_OP1_MOV;
7727 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7728 alu.dst.sel = treg;
7729 alu.dst.chan = j;
7730 if (j == 3)
7731 alu.last = 1;
7732 alu.dst.write = 1;
7733 r = r600_bytecode_add_alu(ctx->bc, &alu);
7734 if (r)
7735 return r;
7736 }
7737 }
7738 for (i = 1; i < 3; i++) {
7739 /* set gradients h/v */
7740 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7741 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7742 FETCH_OP_SET_GRADIENTS_V;
7743 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7744 tex.sampler_index_mode = sampler_index_mode;
7745 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7746 tex.resource_index_mode = sampler_index_mode;
7747
7748 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7749 tex.src_sel_x = 0;
7750 tex.src_sel_y = 1;
7751 tex.src_sel_z = 2;
7752 tex.src_sel_w = 3;
7753
7754 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7755 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7756 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7757 tex.coord_type_x = 1;
7758 tex.coord_type_y = 1;
7759 tex.coord_type_z = 1;
7760 tex.coord_type_w = 1;
7761 }
7762 r = r600_bytecode_add_tex(ctx->bc, &tex);
7763 if (r)
7764 return r;
7765 }
7766 }
7767
7768 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7769 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
7770 * incorrectly forces nearest filtering if the texture format is integer.
7771 * The only effect it has on Gather4, which always returns 4 texels for
7772 * bilinear filtering, is that the final coordinates are off by 0.5 of
7773 * the texel size.
7774 *
7775 * The workaround is to subtract 0.5 from the unnormalized coordinates,
7776 * or (0.5 / size) from the normalized coordinates.
7777 */
7778 if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
7779 inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT) {
7780 int treg = r600_get_temp(ctx);
7781
7782 /* mov array and comparison oordinate to temp_reg if needed */
7783 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7784 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7785 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY) && !src_loaded) {
7786 int end = inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ? 3 : 2;
7787 for (i = 2; i <= end; i++) {
7788 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7789 alu.op = ALU_OP1_MOV;
7790 alu.dst.sel = ctx->temp_reg;
7791 alu.dst.chan = i;
7792 alu.dst.write = 1;
7793 alu.last = (i == end);
7794 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7795 r = r600_bytecode_add_alu(ctx->bc, &alu);
7796 if (r)
7797 return r;
7798 }
7799 }
7800
7801 if (inst->Texture.Texture == TGSI_TEXTURE_RECT ||
7802 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
7803 for (i = 0; i < 2; i++) {
7804 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7805 alu.op = ALU_OP2_ADD;
7806 alu.dst.sel = ctx->temp_reg;
7807 alu.dst.chan = i;
7808 alu.dst.write = 1;
7809 alu.last = i == 1;
7810 if (src_loaded) {
7811 alu.src[0].sel = ctx->temp_reg;
7812 alu.src[0].chan = i;
7813 } else
7814 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7815 alu.src[1].sel = V_SQ_ALU_SRC_0_5;
7816 alu.src[1].neg = 1;
7817 r = r600_bytecode_add_alu(ctx->bc, &alu);
7818 if (r)
7819 return r;
7820 }
7821 } else {
7822 /* execute a TXQ */
7823 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7824 tex.op = FETCH_OP_GET_TEXTURE_RESINFO;
7825 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7826 tex.sampler_index_mode = sampler_index_mode;
7827 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7828 tex.resource_index_mode = sampler_index_mode;
7829 tex.dst_gpr = treg;
7830 tex.src_sel_x = 4;
7831 tex.src_sel_y = 4;
7832 tex.src_sel_z = 4;
7833 tex.src_sel_w = 4;
7834 tex.dst_sel_x = 0;
7835 tex.dst_sel_y = 1;
7836 tex.dst_sel_z = 7;
7837 tex.dst_sel_w = 7;
7838 r = r600_bytecode_add_tex(ctx->bc, &tex);
7839 if (r)
7840 return r;
7841
7842 /* coord.xy = -0.5 * (1.0/int_to_flt(size)) + coord.xy */
7843 if (ctx->bc->chip_class == CAYMAN) {
7844 /* */
7845 for (i = 0; i < 2; i++) {
7846 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7847 alu.op = ALU_OP1_INT_TO_FLT;
7848 alu.dst.sel = treg;
7849 alu.dst.chan = i;
7850 alu.dst.write = 1;
7851 alu.src[0].sel = treg;
7852 alu.src[0].chan = i;
7853 alu.last = (i == 1) ? 1 : 0;
7854 r = r600_bytecode_add_alu(ctx->bc, &alu);
7855 if (r)
7856 return r;
7857 }
7858 for (j = 0; j < 2; j++) {
7859 for (i = 0; i < 3; i++) {
7860 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7861 alu.op = ALU_OP1_RECIP_IEEE;
7862 alu.src[0].sel = treg;
7863 alu.src[0].chan = j;
7864 alu.dst.sel = treg;
7865 alu.dst.chan = i;
7866 if (i == 2)
7867 alu.last = 1;
7868 if (i == j)
7869 alu.dst.write = 1;
7870 r = r600_bytecode_add_alu(ctx->bc, &alu);
7871 if (r)
7872 return r;
7873 }
7874 }
7875 } else {
7876 for (i = 0; i < 2; i++) {
7877 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7878 alu.op = ALU_OP1_INT_TO_FLT;
7879 alu.dst.sel = treg;
7880 alu.dst.chan = i;
7881 alu.dst.write = 1;
7882 alu.src[0].sel = treg;
7883 alu.src[0].chan = i;
7884 alu.last = 1;
7885 r = r600_bytecode_add_alu(ctx->bc, &alu);
7886 if (r)
7887 return r;
7888 }
7889 for (i = 0; i < 2; i++) {
7890 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7891 alu.op = ALU_OP1_RECIP_IEEE;
7892 alu.src[0].sel = treg;
7893 alu.src[0].chan = i;
7894 alu.dst.sel = treg;
7895 alu.dst.chan = i;
7896 alu.last = 1;
7897 alu.dst.write = 1;
7898 r = r600_bytecode_add_alu(ctx->bc, &alu);
7899 if (r)
7900 return r;
7901 }
7902 }
7903 for (i = 0; i < 2; i++) {
7904 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7905 alu.op = ALU_OP3_MULADD;
7906 alu.is_op3 = 1;
7907 alu.dst.sel = ctx->temp_reg;
7908 alu.dst.chan = i;
7909 alu.dst.write = 1;
7910 alu.last = i == 1;
7911 alu.src[0].sel = treg;
7912 alu.src[0].chan = i;
7913 alu.src[1].sel = V_SQ_ALU_SRC_0_5;
7914 alu.src[1].neg = 1;
7915 if (src_loaded) {
7916 alu.src[2].sel = ctx->temp_reg;
7917 alu.src[2].chan = i;
7918 } else
7919 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
7920 r = r600_bytecode_add_alu(ctx->bc, &alu);
7921 if (r)
7922 return r;
7923 }
7924 }
7925 src_loaded = TRUE;
7926 src_gpr = ctx->temp_reg;
7927 }
7928 }
7929
7930 if (src_requires_loading && !src_loaded) {
7931 for (i = 0; i < 4; i++) {
7932 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7933 alu.op = ALU_OP1_MOV;
7934 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7935 alu.dst.sel = ctx->temp_reg;
7936 alu.dst.chan = i;
7937 if (i == 3)
7938 alu.last = 1;
7939 alu.dst.write = 1;
7940 r = r600_bytecode_add_alu(ctx->bc, &alu);
7941 if (r)
7942 return r;
7943 }
7944 src_loaded = TRUE;
7945 src_gpr = ctx->temp_reg;
7946 }
7947
7948 /* get offset values */
7949 if (inst->Texture.NumOffsets) {
7950 assert(inst->Texture.NumOffsets == 1);
7951
7952 /* The texture offset feature doesn't work with the TXF instruction
7953 * and must be emulated by adding the offset to the texture coordinates. */
7954 if (txf_add_offsets) {
7955 const struct tgsi_texture_offset *off = inst->TexOffsets;
7956
7957 switch (inst->Texture.Texture) {
7958 case TGSI_TEXTURE_3D:
7959 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7960 alu.op = ALU_OP2_ADD_INT;
7961 alu.src[0].sel = src_gpr;
7962 alu.src[0].chan = 2;
7963 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7964 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7965 alu.dst.sel = src_gpr;
7966 alu.dst.chan = 2;
7967 alu.dst.write = 1;
7968 alu.last = 1;
7969 r = r600_bytecode_add_alu(ctx->bc, &alu);
7970 if (r)
7971 return r;
7972 /* fall through */
7973
7974 case TGSI_TEXTURE_2D:
7975 case TGSI_TEXTURE_SHADOW2D:
7976 case TGSI_TEXTURE_RECT:
7977 case TGSI_TEXTURE_SHADOWRECT:
7978 case TGSI_TEXTURE_2D_ARRAY:
7979 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7980 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7981 alu.op = ALU_OP2_ADD_INT;
7982 alu.src[0].sel = src_gpr;
7983 alu.src[0].chan = 1;
7984 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7985 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7986 alu.dst.sel = src_gpr;
7987 alu.dst.chan = 1;
7988 alu.dst.write = 1;
7989 alu.last = 1;
7990 r = r600_bytecode_add_alu(ctx->bc, &alu);
7991 if (r)
7992 return r;
7993 /* fall through */
7994
7995 case TGSI_TEXTURE_1D:
7996 case TGSI_TEXTURE_SHADOW1D:
7997 case TGSI_TEXTURE_1D_ARRAY:
7998 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7999 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8000 alu.op = ALU_OP2_ADD_INT;
8001 alu.src[0].sel = src_gpr;
8002 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8003 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
8004 alu.dst.sel = src_gpr;
8005 alu.dst.write = 1;
8006 alu.last = 1;
8007 r = r600_bytecode_add_alu(ctx->bc, &alu);
8008 if (r)
8009 return r;
8010 break;
8011 /* texture offsets do not apply to other texture targets */
8012 }
8013 } else {
8014 switch (inst->Texture.Texture) {
8015 case TGSI_TEXTURE_3D:
8016 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
8017 /* fallthrough */
8018 case TGSI_TEXTURE_2D:
8019 case TGSI_TEXTURE_SHADOW2D:
8020 case TGSI_TEXTURE_RECT:
8021 case TGSI_TEXTURE_SHADOWRECT:
8022 case TGSI_TEXTURE_2D_ARRAY:
8023 case TGSI_TEXTURE_SHADOW2D_ARRAY:
8024 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
8025 /* fallthrough */
8026 case TGSI_TEXTURE_1D:
8027 case TGSI_TEXTURE_SHADOW1D:
8028 case TGSI_TEXTURE_1D_ARRAY:
8029 case TGSI_TEXTURE_SHADOW1D_ARRAY:
8030 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
8031 }
8032 }
8033 }
8034
8035 /* Obtain the sample index for reading a compressed MSAA color texture.
8036 * To read the FMASK, we use the ldfptr instruction, which tells us
8037 * where the samples are stored.
8038 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
8039 * which is the identity mapping. Each nibble says which physical sample
8040 * should be fetched to get that sample.
8041 *
8042 * Assume src.z contains the sample index. It should be modified like this:
8043 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
8044 * Then fetch the texel with src.
8045 */
8046 if (read_compressed_msaa) {
8047 unsigned sample_chan = 3;
8048 unsigned temp = r600_get_temp(ctx);
8049 assert(src_loaded);
8050
8051 /* temp.w = ldfptr() */
8052 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
8053 tex.op = FETCH_OP_LD;
8054 tex.inst_mod = 1; /* to indicate this is ldfptr */
8055 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
8056 tex.sampler_index_mode = sampler_index_mode;
8057 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
8058 tex.resource_index_mode = sampler_index_mode;
8059 tex.src_gpr = src_gpr;
8060 tex.dst_gpr = temp;
8061 tex.dst_sel_x = 7; /* mask out these components */
8062 tex.dst_sel_y = 7;
8063 tex.dst_sel_z = 7;
8064 tex.dst_sel_w = 0; /* store X */
8065 tex.src_sel_x = 0;
8066 tex.src_sel_y = 1;
8067 tex.src_sel_z = 2;
8068 tex.src_sel_w = 3;
8069 tex.offset_x = offset_x;
8070 tex.offset_y = offset_y;
8071 tex.offset_z = offset_z;
8072 r = r600_bytecode_add_tex(ctx->bc, &tex);
8073 if (r)
8074 return r;
8075
8076 /* temp.x = sample_index*4 */
8077 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8078 alu.op = ALU_OP2_MULLO_INT;
8079 alu.src[0].sel = src_gpr;
8080 alu.src[0].chan = sample_chan;
8081 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8082 alu.src[1].value = 4;
8083 alu.dst.sel = temp;
8084 alu.dst.chan = 0;
8085 alu.dst.write = 1;
8086 r = emit_mul_int_op(ctx->bc, &alu);
8087 if (r)
8088 return r;
8089
8090 /* sample_index = temp.w >> temp.x */
8091 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8092 alu.op = ALU_OP2_LSHR_INT;
8093 alu.src[0].sel = temp;
8094 alu.src[0].chan = 3;
8095 alu.src[1].sel = temp;
8096 alu.src[1].chan = 0;
8097 alu.dst.sel = src_gpr;
8098 alu.dst.chan = sample_chan;
8099 alu.dst.write = 1;
8100 alu.last = 1;
8101 r = r600_bytecode_add_alu(ctx->bc, &alu);
8102 if (r)
8103 return r;
8104
8105 /* sample_index & 0xF */
8106 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8107 alu.op = ALU_OP2_AND_INT;
8108 alu.src[0].sel = src_gpr;
8109 alu.src[0].chan = sample_chan;
8110 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8111 alu.src[1].value = 0xF;
8112 alu.dst.sel = src_gpr;
8113 alu.dst.chan = sample_chan;
8114 alu.dst.write = 1;
8115 alu.last = 1;
8116 r = r600_bytecode_add_alu(ctx->bc, &alu);
8117 if (r)
8118 return r;
8119 #if 0
8120 /* visualize the FMASK */
8121 for (i = 0; i < 4; i++) {
8122 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8123 alu.op = ALU_OP1_INT_TO_FLT;
8124 alu.src[0].sel = src_gpr;
8125 alu.src[0].chan = sample_chan;
8126 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8127 alu.dst.chan = i;
8128 alu.dst.write = 1;
8129 alu.last = 1;
8130 r = r600_bytecode_add_alu(ctx->bc, &alu);
8131 if (r)
8132 return r;
8133 }
8134 return 0;
8135 #endif
8136 }
8137
8138 /* does this shader want a num layers from TXQ for a cube array? */
8139 if (has_txq_cube_array_z) {
8140 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
8141
8142 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8143 alu.op = ALU_OP1_MOV;
8144
8145 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
8146 if (ctx->bc->chip_class >= EVERGREEN) {
8147 /* with eg each dword is number of cubes */
8148 alu.src[0].sel += id / 4;
8149 alu.src[0].chan = id % 4;
8150 } else {
8151 /* r600 we have them at channel 2 of the second dword */
8152 alu.src[0].sel += (id * 2) + 1;
8153 alu.src[0].chan = 2;
8154 }
8155 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
8156 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
8157 alu.last = 1;
8158 r = r600_bytecode_add_alu(ctx->bc, &alu);
8159 if (r)
8160 return r;
8161 /* disable writemask from texture instruction */
8162 inst->Dst[0].Register.WriteMask &= ~4;
8163 }
8164
8165 opcode = ctx->inst_info->op;
8166 if (opcode == FETCH_OP_GATHER4 &&
8167 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
8168 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
8169 opcode = FETCH_OP_GATHER4_O;
8170
8171 /* GATHER4_O/GATHER4_C_O use offset values loaded by
8172 SET_TEXTURE_OFFSETS instruction. The immediate offset values
8173 encoded in the instruction are ignored. */
8174 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
8175 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
8176 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
8177 tex.sampler_index_mode = sampler_index_mode;
8178 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
8179 tex.resource_index_mode = sampler_index_mode;
8180
8181 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
8182 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
8183 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
8184 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
8185 tex.src_sel_w = 4;
8186
8187 tex.dst_sel_x = 7;
8188 tex.dst_sel_y = 7;
8189 tex.dst_sel_z = 7;
8190 tex.dst_sel_w = 7;
8191
8192 r = r600_bytecode_add_tex(ctx->bc, &tex);
8193 if (r)
8194 return r;
8195 }
8196
8197 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
8198 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
8199 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
8200 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
8201 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
8202 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
8203 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
8204 switch (opcode) {
8205 case FETCH_OP_SAMPLE:
8206 opcode = FETCH_OP_SAMPLE_C;
8207 break;
8208 case FETCH_OP_SAMPLE_L:
8209 opcode = FETCH_OP_SAMPLE_C_L;
8210 break;
8211 case FETCH_OP_SAMPLE_LB:
8212 opcode = FETCH_OP_SAMPLE_C_LB;
8213 break;
8214 case FETCH_OP_SAMPLE_G:
8215 opcode = FETCH_OP_SAMPLE_C_G;
8216 break;
8217 /* Texture gather variants */
8218 case FETCH_OP_GATHER4:
8219 opcode = FETCH_OP_GATHER4_C;
8220 break;
8221 case FETCH_OP_GATHER4_O:
8222 opcode = FETCH_OP_GATHER4_C_O;
8223 break;
8224 }
8225 }
8226
8227 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
8228 tex.op = opcode;
8229
8230 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
8231 tex.sampler_index_mode = sampler_index_mode;
8232 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
8233 tex.resource_index_mode = sampler_index_mode;
8234 tex.src_gpr = src_gpr;
8235 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8236
8237 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
8238 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
8239 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
8240 }
8241
8242 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
8243 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
8244 tex.inst_mod = texture_component_select;
8245
8246 if (ctx->bc->chip_class == CAYMAN) {
8247 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8248 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8249 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
8250 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8251 } else {
8252 /* GATHER4 result order is different from TGSI TG4 */
8253 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 1 : 7;
8254 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 2 : 7;
8255 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 0 : 7;
8256 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8257 }
8258 }
8259 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
8260 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8261 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8262 tex.dst_sel_z = 7;
8263 tex.dst_sel_w = 7;
8264 }
8265 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
8266 tex.dst_sel_x = 3;
8267 tex.dst_sel_y = 7;
8268 tex.dst_sel_z = 7;
8269 tex.dst_sel_w = 7;
8270 }
8271 else {
8272 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8273 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8274 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
8275 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8276 }
8277
8278
8279 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
8280 tex.src_sel_x = 4;
8281 tex.src_sel_y = 4;
8282 tex.src_sel_z = 4;
8283 tex.src_sel_w = 4;
8284 } else if (src_loaded) {
8285 tex.src_sel_x = 0;
8286 tex.src_sel_y = 1;
8287 tex.src_sel_z = 2;
8288 tex.src_sel_w = 3;
8289 } else {
8290 tex.src_sel_x = ctx->src[0].swizzle[0];
8291 tex.src_sel_y = ctx->src[0].swizzle[1];
8292 tex.src_sel_z = ctx->src[0].swizzle[2];
8293 tex.src_sel_w = ctx->src[0].swizzle[3];
8294 tex.src_rel = ctx->src[0].rel;
8295 }
8296
8297 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
8298 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
8299 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
8300 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
8301 tex.src_sel_x = 1;
8302 tex.src_sel_y = 0;
8303 tex.src_sel_z = 3;
8304 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
8305 }
8306
8307 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
8308 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
8309 tex.coord_type_x = 1;
8310 tex.coord_type_y = 1;
8311 }
8312 tex.coord_type_z = 1;
8313 tex.coord_type_w = 1;
8314
8315 tex.offset_x = offset_x;
8316 tex.offset_y = offset_y;
8317 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
8318 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
8319 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
8320 tex.offset_z = 0;
8321 }
8322 else {
8323 tex.offset_z = offset_z;
8324 }
8325
8326 /* Put the depth for comparison in W.
8327 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
8328 * Some instructions expect the depth in Z. */
8329 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
8330 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
8331 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
8332 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
8333 opcode != FETCH_OP_SAMPLE_C_L &&
8334 opcode != FETCH_OP_SAMPLE_C_LB) {
8335 tex.src_sel_w = tex.src_sel_z;
8336 }
8337
8338 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
8339 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
8340 if (opcode == FETCH_OP_SAMPLE_C_L ||
8341 opcode == FETCH_OP_SAMPLE_C_LB) {
8342 /* the array index is read from Y */
8343 tex.coord_type_y = 0;
8344 } else {
8345 /* the array index is read from Z */
8346 tex.coord_type_z = 0;
8347 tex.src_sel_z = tex.src_sel_y;
8348 }
8349 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
8350 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
8351 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
8352 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
8353 (ctx->bc->chip_class >= EVERGREEN)))
8354 /* the array index is read from Z */
8355 tex.coord_type_z = 0;
8356
8357 /* mask unused source components */
8358 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
8359 switch (inst->Texture.Texture) {
8360 case TGSI_TEXTURE_2D:
8361 case TGSI_TEXTURE_RECT:
8362 tex.src_sel_z = 7;
8363 tex.src_sel_w = 7;
8364 break;
8365 case TGSI_TEXTURE_1D_ARRAY:
8366 tex.src_sel_y = 7;
8367 tex.src_sel_w = 7;
8368 break;
8369 case TGSI_TEXTURE_1D:
8370 tex.src_sel_y = 7;
8371 tex.src_sel_z = 7;
8372 tex.src_sel_w = 7;
8373 break;
8374 }
8375 }
8376
8377 r = r600_bytecode_add_tex(ctx->bc, &tex);
8378 if (r)
8379 return r;
8380
8381 /* add shadow ambient support - gallium doesn't do it yet */
8382 return 0;
8383 }
8384
8385 static int find_hw_atomic_counter(struct r600_shader_ctx *ctx,
8386 struct tgsi_full_src_register *src)
8387 {
8388 unsigned i;
8389
8390 if (src->Register.Indirect) {
8391 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
8392 if (src->Indirect.ArrayID == ctx->shader->atomics[i].array_id)
8393 return ctx->shader->atomics[i].hw_idx;
8394 }
8395 } else {
8396 uint32_t index = src->Register.Index;
8397 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
8398 if (ctx->shader->atomics[i].buffer_id != (unsigned)src->Dimension.Index)
8399 continue;
8400 if (index > ctx->shader->atomics[i].end)
8401 continue;
8402 if (index < ctx->shader->atomics[i].start)
8403 continue;
8404 uint32_t offset = (index - ctx->shader->atomics[i].start);
8405 return ctx->shader->atomics[i].hw_idx + offset;
8406 }
8407 }
8408 assert(0);
8409 return -1;
8410 }
8411
8412 static int tgsi_set_gds_temp(struct r600_shader_ctx *ctx,
8413 int *uav_id_p, int *uav_index_mode_p)
8414 {
8415 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8416 int uav_id, uav_index_mode = 0;
8417 int r;
8418 bool is_cm = (ctx->bc->chip_class == CAYMAN);
8419
8420 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
8421
8422 if (inst->Src[0].Register.Indirect) {
8423 if (is_cm) {
8424 struct r600_bytecode_alu alu;
8425 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8426 alu.op = ALU_OP2_LSHL_INT;
8427 alu.src[0].sel = get_address_file_reg(ctx, inst->Src[0].Indirect.Index);
8428 alu.src[0].chan = 0;
8429 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8430 alu.src[1].value = 2;
8431 alu.dst.sel = ctx->temp_reg;
8432 alu.dst.chan = 0;
8433 alu.dst.write = 1;
8434 alu.last = 1;
8435 r = r600_bytecode_add_alu(ctx->bc, &alu);
8436 if (r)
8437 return r;
8438
8439 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8440 ctx->temp_reg, 0,
8441 ctx->temp_reg, 0,
8442 V_SQ_ALU_SRC_LITERAL, uav_id * 4);
8443 if (r)
8444 return r;
8445 } else
8446 uav_index_mode = 2;
8447 } else if (is_cm) {
8448 r = single_alu_op2(ctx, ALU_OP1_MOV,
8449 ctx->temp_reg, 0,
8450 V_SQ_ALU_SRC_LITERAL, uav_id * 4,
8451 0, 0);
8452 if (r)
8453 return r;
8454 }
8455 *uav_id_p = uav_id;
8456 *uav_index_mode_p = uav_index_mode;
8457 return 0;
8458 }
8459
8460 static int tgsi_load_gds(struct r600_shader_ctx *ctx)
8461 {
8462 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8463 int r;
8464 struct r600_bytecode_gds gds;
8465 int uav_id = 0;
8466 int uav_index_mode = 0;
8467 bool is_cm = (ctx->bc->chip_class == CAYMAN);
8468
8469 r = tgsi_set_gds_temp(ctx, &uav_id, &uav_index_mode);
8470 if (r)
8471 return r;
8472
8473 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
8474 gds.op = FETCH_OP_GDS_READ_RET;
8475 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8476 gds.uav_id = is_cm ? 0 : uav_id;
8477 gds.uav_index_mode = is_cm ? 0 : uav_index_mode;
8478 gds.src_gpr = ctx->temp_reg;
8479 gds.src_sel_x = (is_cm) ? 0 : 4;
8480 gds.src_sel_y = 4;
8481 gds.src_sel_z = 4;
8482 gds.dst_sel_x = 0;
8483 gds.dst_sel_y = 7;
8484 gds.dst_sel_z = 7;
8485 gds.dst_sel_w = 7;
8486 gds.src_gpr2 = 0;
8487 gds.alloc_consume = !is_cm;
8488 r = r600_bytecode_add_gds(ctx->bc, &gds);
8489 if (r)
8490 return r;
8491
8492 ctx->bc->cf_last->vpm = 1;
8493 return 0;
8494 }
8495
8496 /* this fixes up 1D arrays properly */
8497 static int load_index_src(struct r600_shader_ctx *ctx, int src_index, int *idx_gpr)
8498 {
8499 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8500 int r, i;
8501 struct r600_bytecode_alu alu;
8502 int temp_reg = r600_get_temp(ctx);
8503
8504 for (i = 0; i < 4; i++) {
8505 bool def_val = true, write_zero = false;
8506 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8507 alu.op = ALU_OP1_MOV;
8508 alu.dst.sel = temp_reg;
8509 alu.dst.chan = i;
8510
8511 switch (inst->Memory.Texture) {
8512 case TGSI_TEXTURE_BUFFER:
8513 case TGSI_TEXTURE_1D:
8514 if (i == 1 || i == 2 || i == 3) {
8515 write_zero = true;
8516 }
8517 break;
8518 case TGSI_TEXTURE_1D_ARRAY:
8519 if (i == 1 || i == 3)
8520 write_zero = true;
8521 else if (i == 2) {
8522 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], 1);
8523 def_val = false;
8524 }
8525 break;
8526 case TGSI_TEXTURE_2D:
8527 if (i == 2 || i == 3)
8528 write_zero = true;
8529 break;
8530 default:
8531 if (i == 3)
8532 write_zero = true;
8533 break;
8534 }
8535
8536 if (write_zero) {
8537 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
8538 alu.src[0].value = 0;
8539 } else if (def_val) {
8540 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], i);
8541 }
8542
8543 if (i == 3)
8544 alu.last = 1;
8545 alu.dst.write = 1;
8546 r = r600_bytecode_add_alu(ctx->bc, &alu);
8547 if (r)
8548 return r;
8549 }
8550 *idx_gpr = temp_reg;
8551 return 0;
8552 }
8553
8554 static int load_buffer_coord(struct r600_shader_ctx *ctx, int src_idx,
8555 int temp_reg)
8556 {
8557 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8558 int r;
8559 if (inst->Src[src_idx].Register.File == TGSI_FILE_IMMEDIATE) {
8560 int value = (ctx->literals[4 * inst->Src[src_idx].Register.Index + inst->Src[src_idx].Register.SwizzleX]);
8561 r = single_alu_op2(ctx, ALU_OP1_MOV,
8562 temp_reg, 0,
8563 V_SQ_ALU_SRC_LITERAL, value >> 2,
8564 0, 0);
8565 if (r)
8566 return r;
8567 } else {
8568 struct r600_bytecode_alu alu;
8569 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8570 alu.op = ALU_OP2_LSHR_INT;
8571 r600_bytecode_src(&alu.src[0], &ctx->src[src_idx], 0);
8572 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8573 alu.src[1].value = 2;
8574 alu.dst.sel = temp_reg;
8575 alu.dst.write = 1;
8576 alu.last = 1;
8577 r = r600_bytecode_add_alu(ctx->bc, &alu);
8578 if (r)
8579 return r;
8580 }
8581 return 0;
8582 }
8583
8584 static int tgsi_load_buffer(struct r600_shader_ctx *ctx)
8585 {
8586 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8587 /* have to work out the offset into the RAT immediate return buffer */
8588 struct r600_bytecode_vtx vtx;
8589 struct r600_bytecode_cf *cf;
8590 int r;
8591 int temp_reg = r600_get_temp(ctx);
8592 unsigned rat_index_mode;
8593 unsigned base;
8594
8595 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8596 base = R600_IMAGE_REAL_RESOURCE_OFFSET + ctx->info.file_count[TGSI_FILE_IMAGE];
8597
8598 r = load_buffer_coord(ctx, 1, temp_reg);
8599 if (r)
8600 return r;
8601 ctx->bc->cf_last->barrier = 1;
8602 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8603 vtx.op = FETCH_OP_VFETCH;
8604 vtx.buffer_id = inst->Src[0].Register.Index + base;
8605 vtx.buffer_index_mode = rat_index_mode;
8606 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8607 vtx.src_gpr = temp_reg;
8608 vtx.src_sel_x = 0;
8609 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8610 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
8611 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
8612 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
8613 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
8614 vtx.num_format_all = 1;
8615 vtx.format_comp_all = 1;
8616 vtx.srf_mode_all = 0;
8617
8618 if (inst->Dst[0].Register.WriteMask & 8) {
8619 vtx.data_format = FMT_32_32_32_32;
8620 vtx.use_const_fields = 0;
8621 } else if (inst->Dst[0].Register.WriteMask & 4) {
8622 vtx.data_format = FMT_32_32_32;
8623 vtx.use_const_fields = 0;
8624 } else if (inst->Dst[0].Register.WriteMask & 2) {
8625 vtx.data_format = FMT_32_32;
8626 vtx.use_const_fields = 0;
8627 } else {
8628 vtx.data_format = FMT_32;
8629 vtx.use_const_fields = 0;
8630 }
8631
8632 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8633 if (r)
8634 return r;
8635 cf = ctx->bc->cf_last;
8636 cf->barrier = 1;
8637 return 0;
8638 }
8639
8640 static int tgsi_load_rat(struct r600_shader_ctx *ctx)
8641 {
8642 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8643 /* have to work out the offset into the RAT immediate return buffer */
8644 struct r600_bytecode_vtx vtx;
8645 struct r600_bytecode_cf *cf;
8646 int r;
8647 int idx_gpr;
8648 unsigned format, num_format, format_comp, endian;
8649 const struct util_format_description *desc;
8650 unsigned rat_index_mode;
8651 unsigned immed_base;
8652
8653 r = load_thread_id_gpr(ctx);
8654 if (r)
8655 return r;
8656
8657 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8658
8659 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
8660 r = load_index_src(ctx, 1, &idx_gpr);
8661 if (r)
8662 return r;
8663
8664 if (rat_index_mode)
8665 egcm_load_index_reg(ctx->bc, 1, false);
8666
8667 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8668 cf = ctx->bc->cf_last;
8669
8670 cf->rat.id = ctx->shader->rat_base + inst->Src[0].Register.Index;
8671 cf->rat.inst = V_RAT_INST_NOP_RTN;
8672 cf->rat.index_mode = rat_index_mode;
8673 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
8674 cf->output.gpr = ctx->thread_id_gpr;
8675 cf->output.index_gpr = idx_gpr;
8676 cf->output.comp_mask = 0xf;
8677 cf->output.burst_count = 1;
8678 cf->vpm = 1;
8679 cf->barrier = 1;
8680 cf->mark = 1;
8681 cf->output.elem_size = 0;
8682
8683 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
8684 cf = ctx->bc->cf_last;
8685 cf->barrier = 1;
8686
8687 desc = util_format_description(inst->Memory.Format);
8688 r600_vertex_data_type(inst->Memory.Format,
8689 &format, &num_format, &format_comp, &endian);
8690 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8691 vtx.op = FETCH_OP_VFETCH;
8692 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
8693 vtx.buffer_index_mode = rat_index_mode;
8694 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8695 vtx.src_gpr = ctx->thread_id_gpr;
8696 vtx.src_sel_x = 1;
8697 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8698 vtx.dst_sel_x = desc->swizzle[0];
8699 vtx.dst_sel_y = desc->swizzle[1];
8700 vtx.dst_sel_z = desc->swizzle[2];
8701 vtx.dst_sel_w = desc->swizzle[3];
8702 vtx.srf_mode_all = 1;
8703 vtx.data_format = format;
8704 vtx.num_format_all = num_format;
8705 vtx.format_comp_all = format_comp;
8706 vtx.endian = endian;
8707 vtx.offset = 0;
8708 vtx.mega_fetch_count = 3;
8709 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8710 if (r)
8711 return r;
8712 cf = ctx->bc->cf_last;
8713 cf->barrier = 1;
8714 return 0;
8715 }
8716
8717 static int tgsi_load_lds(struct r600_shader_ctx *ctx)
8718 {
8719 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8720 struct r600_bytecode_alu alu;
8721 int r;
8722 int temp_reg = r600_get_temp(ctx);
8723
8724 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8725 alu.op = ALU_OP1_MOV;
8726 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
8727 alu.dst.sel = temp_reg;
8728 alu.dst.write = 1;
8729 alu.last = 1;
8730 r = r600_bytecode_add_alu(ctx->bc, &alu);
8731 if (r)
8732 return r;
8733
8734 r = do_lds_fetch_values(ctx, temp_reg,
8735 ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index, inst->Dst[0].Register.WriteMask);
8736 if (r)
8737 return r;
8738 return 0;
8739 }
8740
8741 static int tgsi_load(struct r600_shader_ctx *ctx)
8742 {
8743 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8744 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
8745 return tgsi_load_rat(ctx);
8746 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
8747 return tgsi_load_gds(ctx);
8748 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
8749 return tgsi_load_buffer(ctx);
8750 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
8751 return tgsi_load_lds(ctx);
8752 return 0;
8753 }
8754
8755 static int tgsi_store_buffer_rat(struct r600_shader_ctx *ctx)
8756 {
8757 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8758 struct r600_bytecode_cf *cf;
8759 int r, i;
8760 unsigned rat_index_mode;
8761 int lasti;
8762 int temp_reg = r600_get_temp(ctx), treg2 = r600_get_temp(ctx);
8763
8764 r = load_buffer_coord(ctx, 0, treg2);
8765 if (r)
8766 return r;
8767
8768 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8769 if (rat_index_mode)
8770 egcm_load_index_reg(ctx->bc, 1, false);
8771
8772 for (i = 0; i <= 3; i++) {
8773 struct r600_bytecode_alu alu;
8774 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8775 alu.op = ALU_OP1_MOV;
8776 alu.dst.sel = temp_reg;
8777 alu.dst.chan = i;
8778 alu.src[0].sel = V_SQ_ALU_SRC_0;
8779 alu.last = (i == 3);
8780 alu.dst.write = 1;
8781 r = r600_bytecode_add_alu(ctx->bc, &alu);
8782 if (r)
8783 return r;
8784 }
8785
8786 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8787 for (i = 0; i <= lasti; i++) {
8788 struct r600_bytecode_alu alu;
8789 if (!((1 << i) & inst->Dst[0].Register.WriteMask))
8790 continue;
8791
8792 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8793 temp_reg, 0,
8794 treg2, 0,
8795 V_SQ_ALU_SRC_LITERAL, i);
8796 if (r)
8797 return r;
8798
8799 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8800 alu.op = ALU_OP1_MOV;
8801 alu.dst.sel = ctx->temp_reg;
8802 alu.dst.chan = 0;
8803
8804 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8805 alu.last = 1;
8806 alu.dst.write = 1;
8807 r = r600_bytecode_add_alu(ctx->bc, &alu);
8808 if (r)
8809 return r;
8810
8811 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8812 cf = ctx->bc->cf_last;
8813
8814 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index + ctx->info.file_count[TGSI_FILE_IMAGE];
8815 cf->rat.inst = V_RAT_INST_STORE_TYPED;
8816 cf->rat.index_mode = rat_index_mode;
8817 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
8818 cf->output.gpr = ctx->temp_reg;
8819 cf->output.index_gpr = temp_reg;
8820 cf->output.comp_mask = 1;
8821 cf->output.burst_count = 1;
8822 cf->vpm = 1;
8823 cf->barrier = 1;
8824 cf->output.elem_size = 0;
8825 }
8826 return 0;
8827 }
8828
8829 static int tgsi_store_rat(struct r600_shader_ctx *ctx)
8830 {
8831 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8832 struct r600_bytecode_cf *cf;
8833 bool src_requires_loading = false;
8834 int val_gpr, idx_gpr;
8835 int r, i;
8836 unsigned rat_index_mode;
8837
8838 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8839
8840 r = load_index_src(ctx, 0, &idx_gpr);
8841 if (r)
8842 return r;
8843
8844 if (inst->Src[1].Register.File != TGSI_FILE_TEMPORARY)
8845 src_requires_loading = true;
8846
8847 if (src_requires_loading) {
8848 struct r600_bytecode_alu alu;
8849 for (i = 0; i < 4; i++) {
8850 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8851 alu.op = ALU_OP1_MOV;
8852 alu.dst.sel = ctx->temp_reg;
8853 alu.dst.chan = i;
8854
8855 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8856 if (i == 3)
8857 alu.last = 1;
8858 alu.dst.write = 1;
8859 r = r600_bytecode_add_alu(ctx->bc, &alu);
8860 if (r)
8861 return r;
8862 }
8863 val_gpr = ctx->temp_reg;
8864 } else
8865 val_gpr = tgsi_tex_get_src_gpr(ctx, 1);
8866 if (rat_index_mode)
8867 egcm_load_index_reg(ctx->bc, 1, false);
8868
8869 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8870 cf = ctx->bc->cf_last;
8871
8872 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index;
8873 cf->rat.inst = V_RAT_INST_STORE_TYPED;
8874 cf->rat.index_mode = rat_index_mode;
8875 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
8876 cf->output.gpr = val_gpr;
8877 cf->output.index_gpr = idx_gpr;
8878 cf->output.comp_mask = 0xf;
8879 cf->output.burst_count = 1;
8880 cf->vpm = 1;
8881 cf->barrier = 1;
8882 cf->output.elem_size = 0;
8883 return 0;
8884 }
8885
8886 static int tgsi_store_lds(struct r600_shader_ctx *ctx)
8887 {
8888 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8889 struct r600_bytecode_alu alu;
8890 int r, i, lasti;
8891 int write_mask = inst->Dst[0].Register.WriteMask;
8892 int temp_reg = r600_get_temp(ctx);
8893
8894 /* LDS write */
8895 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8896 alu.op = ALU_OP1_MOV;
8897 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8898 alu.dst.sel = temp_reg;
8899 alu.dst.write = 1;
8900 alu.last = 1;
8901 r = r600_bytecode_add_alu(ctx->bc, &alu);
8902 if (r)
8903 return r;
8904
8905 lasti = tgsi_last_instruction(write_mask);
8906 for (i = 1; i <= lasti; i++) {
8907 if (!(write_mask & (1 << i)))
8908 continue;
8909 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8910 temp_reg, i,
8911 temp_reg, 0,
8912 V_SQ_ALU_SRC_LITERAL, 4 * i);
8913 if (r)
8914 return r;
8915 }
8916 for (i = 0; i <= lasti; i++) {
8917 if (!(write_mask & (1 << i)))
8918 continue;
8919
8920 if ((i == 0 && ((write_mask & 3) == 3)) ||
8921 (i == 2 && ((write_mask & 0xc) == 0xc))) {
8922 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8923 alu.op = LDS_OP3_LDS_WRITE_REL;
8924
8925 alu.src[0].sel = temp_reg;
8926 alu.src[0].chan = i;
8927 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8928 r600_bytecode_src(&alu.src[2], &ctx->src[1], i + 1);
8929 alu.last = 1;
8930 alu.is_lds_idx_op = true;
8931 alu.lds_idx = 1;
8932 r = r600_bytecode_add_alu(ctx->bc, &alu);
8933 if (r)
8934 return r;
8935 i += 1;
8936 continue;
8937 }
8938 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8939 alu.op = LDS_OP2_LDS_WRITE;
8940
8941 alu.src[0].sel = temp_reg;
8942 alu.src[0].chan = i;
8943 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8944
8945 alu.last = 1;
8946 alu.is_lds_idx_op = true;
8947
8948 r = r600_bytecode_add_alu(ctx->bc, &alu);
8949 if (r)
8950 return r;
8951 }
8952 return 0;
8953 }
8954
8955 static int tgsi_store(struct r600_shader_ctx *ctx)
8956 {
8957 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8958 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER)
8959 return tgsi_store_buffer_rat(ctx);
8960 else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY)
8961 return tgsi_store_lds(ctx);
8962 else
8963 return tgsi_store_rat(ctx);
8964 }
8965
8966 static int tgsi_atomic_op_rat(struct r600_shader_ctx *ctx)
8967 {
8968 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8969 /* have to work out the offset into the RAT immediate return buffer */
8970 struct r600_bytecode_alu alu;
8971 struct r600_bytecode_vtx vtx;
8972 struct r600_bytecode_cf *cf;
8973 int r;
8974 int idx_gpr;
8975 unsigned format, num_format, format_comp, endian;
8976 const struct util_format_description *desc;
8977 unsigned rat_index_mode;
8978 unsigned immed_base;
8979 unsigned rat_base;
8980
8981 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
8982 rat_base = ctx->shader->rat_base;
8983
8984 r = load_thread_id_gpr(ctx);
8985 if (r)
8986 return r;
8987
8988 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
8989 immed_base += ctx->info.file_count[TGSI_FILE_IMAGE];
8990 rat_base += ctx->info.file_count[TGSI_FILE_IMAGE];
8991
8992 r = load_buffer_coord(ctx, 1, ctx->temp_reg);
8993 if (r)
8994 return r;
8995 idx_gpr = ctx->temp_reg;
8996 } else {
8997 r = load_index_src(ctx, 1, &idx_gpr);
8998 if (r)
8999 return r;
9000 }
9001
9002 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
9003
9004 if (ctx->inst_info->op == V_RAT_INST_CMPXCHG_INT_RTN) {
9005 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9006 alu.op = ALU_OP1_MOV;
9007 alu.dst.sel = ctx->thread_id_gpr;
9008 alu.dst.chan = 0;
9009 alu.dst.write = 1;
9010 r600_bytecode_src(&alu.src[0], &ctx->src[3], 0);
9011 alu.last = 1;
9012 r = r600_bytecode_add_alu(ctx->bc, &alu);
9013 if (r)
9014 return r;
9015
9016 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9017 alu.op = ALU_OP1_MOV;
9018 alu.dst.sel = ctx->thread_id_gpr;
9019 if (ctx->bc->chip_class == CAYMAN)
9020 alu.dst.chan = 2;
9021 else
9022 alu.dst.chan = 3;
9023 alu.dst.write = 1;
9024 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
9025 alu.last = 1;
9026 r = r600_bytecode_add_alu(ctx->bc, &alu);
9027 if (r)
9028 return r;
9029 } else {
9030 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9031 alu.op = ALU_OP1_MOV;
9032 alu.dst.sel = ctx->thread_id_gpr;
9033 alu.dst.chan = 0;
9034 alu.dst.write = 1;
9035 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
9036 alu.last = 1;
9037 r = r600_bytecode_add_alu(ctx->bc, &alu);
9038 if (r)
9039 return r;
9040 }
9041
9042 if (rat_index_mode)
9043 egcm_load_index_reg(ctx->bc, 1, false);
9044 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
9045 cf = ctx->bc->cf_last;
9046
9047 cf->rat.id = rat_base + inst->Src[0].Register.Index;
9048 cf->rat.inst = ctx->inst_info->op;
9049 cf->rat.index_mode = rat_index_mode;
9050 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
9051 cf->output.gpr = ctx->thread_id_gpr;
9052 cf->output.index_gpr = idx_gpr;
9053 cf->output.comp_mask = 0xf;
9054 cf->output.burst_count = 1;
9055 cf->vpm = 1;
9056 cf->barrier = 1;
9057 cf->mark = 1;
9058 cf->output.elem_size = 0;
9059 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
9060 cf = ctx->bc->cf_last;
9061 cf->barrier = 1;
9062 cf->cf_addr = 1;
9063
9064 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
9065 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
9066 desc = util_format_description(inst->Memory.Format);
9067 r600_vertex_data_type(inst->Memory.Format,
9068 &format, &num_format, &format_comp, &endian);
9069 vtx.dst_sel_x = desc->swizzle[0];
9070 } else {
9071 format = FMT_32;
9072 num_format = 1;
9073 format_comp = 0;
9074 endian = 0;
9075 vtx.dst_sel_x = 0;
9076 }
9077 vtx.op = FETCH_OP_VFETCH;
9078 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
9079 vtx.buffer_index_mode = rat_index_mode;
9080 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
9081 vtx.src_gpr = ctx->thread_id_gpr;
9082 vtx.src_sel_x = 1;
9083 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
9084 vtx.dst_sel_y = 7;
9085 vtx.dst_sel_z = 7;
9086 vtx.dst_sel_w = 7;
9087 vtx.use_const_fields = 0;
9088 vtx.srf_mode_all = 1;
9089 vtx.data_format = format;
9090 vtx.num_format_all = num_format;
9091 vtx.format_comp_all = format_comp;
9092 vtx.endian = endian;
9093 vtx.offset = 0;
9094 vtx.mega_fetch_count = 0xf;
9095 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
9096 if (r)
9097 return r;
9098 cf = ctx->bc->cf_last;
9099 cf->vpm = 1;
9100 cf->barrier = 1;
9101 return 0;
9102 }
9103
9104 static int get_gds_op(int opcode)
9105 {
9106 switch (opcode) {
9107 case TGSI_OPCODE_ATOMUADD:
9108 return FETCH_OP_GDS_ADD_RET;
9109 case TGSI_OPCODE_ATOMAND:
9110 return FETCH_OP_GDS_AND_RET;
9111 case TGSI_OPCODE_ATOMOR:
9112 return FETCH_OP_GDS_OR_RET;
9113 case TGSI_OPCODE_ATOMXOR:
9114 return FETCH_OP_GDS_XOR_RET;
9115 case TGSI_OPCODE_ATOMUMIN:
9116 return FETCH_OP_GDS_MIN_UINT_RET;
9117 case TGSI_OPCODE_ATOMUMAX:
9118 return FETCH_OP_GDS_MAX_UINT_RET;
9119 case TGSI_OPCODE_ATOMXCHG:
9120 return FETCH_OP_GDS_XCHG_RET;
9121 case TGSI_OPCODE_ATOMCAS:
9122 return FETCH_OP_GDS_CMP_XCHG_RET;
9123 default:
9124 return -1;
9125 }
9126 }
9127
9128 static int tgsi_atomic_op_gds(struct r600_shader_ctx *ctx)
9129 {
9130 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9131 struct r600_bytecode_gds gds;
9132 struct r600_bytecode_alu alu;
9133 int gds_op = get_gds_op(inst->Instruction.Opcode);
9134 int r;
9135 int uav_id = 0;
9136 int uav_index_mode = 0;
9137 bool is_cm = (ctx->bc->chip_class == CAYMAN);
9138
9139 if (gds_op == -1) {
9140 fprintf(stderr, "unknown GDS op for opcode %d\n", inst->Instruction.Opcode);
9141 return -1;
9142 }
9143
9144 r = tgsi_set_gds_temp(ctx, &uav_id, &uav_index_mode);
9145 if (r)
9146 return r;
9147
9148 if (gds_op == FETCH_OP_GDS_CMP_XCHG_RET) {
9149 if (inst->Src[3].Register.File == TGSI_FILE_IMMEDIATE) {
9150 int value = (ctx->literals[4 * inst->Src[3].Register.Index + inst->Src[3].Register.SwizzleX]);
9151 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9152 alu.op = ALU_OP1_MOV;
9153 alu.dst.sel = ctx->temp_reg;
9154 alu.dst.chan = is_cm ? 2 : 1;
9155 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
9156 alu.src[0].value = value;
9157 alu.last = 1;
9158 alu.dst.write = 1;
9159 r = r600_bytecode_add_alu(ctx->bc, &alu);
9160 if (r)
9161 return r;
9162 } else {
9163 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9164 alu.op = ALU_OP1_MOV;
9165 alu.dst.sel = ctx->temp_reg;
9166 alu.dst.chan = is_cm ? 2 : 1;
9167 r600_bytecode_src(&alu.src[0], &ctx->src[3], 0);
9168 alu.last = 1;
9169 alu.dst.write = 1;
9170 r = r600_bytecode_add_alu(ctx->bc, &alu);
9171 if (r)
9172 return r;
9173 }
9174 }
9175 if (inst->Src[2].Register.File == TGSI_FILE_IMMEDIATE) {
9176 int value = (ctx->literals[4 * inst->Src[2].Register.Index + inst->Src[2].Register.SwizzleX]);
9177 int abs_value = abs(value);
9178 if (abs_value != value && gds_op == FETCH_OP_GDS_ADD_RET)
9179 gds_op = FETCH_OP_GDS_SUB_RET;
9180 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9181 alu.op = ALU_OP1_MOV;
9182 alu.dst.sel = ctx->temp_reg;
9183 alu.dst.chan = is_cm ? 1 : 0;
9184 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
9185 alu.src[0].value = abs_value;
9186 alu.last = 1;
9187 alu.dst.write = 1;
9188 r = r600_bytecode_add_alu(ctx->bc, &alu);
9189 if (r)
9190 return r;
9191 } else {
9192 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9193 alu.op = ALU_OP1_MOV;
9194 alu.dst.sel = ctx->temp_reg;
9195 alu.dst.chan = is_cm ? 1 : 0;
9196 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
9197 alu.last = 1;
9198 alu.dst.write = 1;
9199 r = r600_bytecode_add_alu(ctx->bc, &alu);
9200 if (r)
9201 return r;
9202 }
9203
9204
9205 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
9206 gds.op = gds_op;
9207 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
9208 gds.uav_id = is_cm ? 0 : uav_id;
9209 gds.uav_index_mode = is_cm ? 0 : uav_index_mode;
9210 gds.src_gpr = ctx->temp_reg;
9211 gds.src_gpr2 = 0;
9212 gds.src_sel_x = is_cm ? 0 : 4;
9213 gds.src_sel_y = is_cm ? 1 : 0;
9214 if (gds_op == FETCH_OP_GDS_CMP_XCHG_RET)
9215 gds.src_sel_z = is_cm ? 2 : 1;
9216 else
9217 gds.src_sel_z = 7;
9218 gds.dst_sel_x = 0;
9219 gds.dst_sel_y = 7;
9220 gds.dst_sel_z = 7;
9221 gds.dst_sel_w = 7;
9222 gds.alloc_consume = !is_cm;
9223
9224 r = r600_bytecode_add_gds(ctx->bc, &gds);
9225 if (r)
9226 return r;
9227 ctx->bc->cf_last->vpm = 1;
9228 return 0;
9229 }
9230
9231 static int get_lds_op(int opcode)
9232 {
9233 switch (opcode) {
9234 case TGSI_OPCODE_ATOMUADD:
9235 return LDS_OP2_LDS_ADD_RET;
9236 case TGSI_OPCODE_ATOMAND:
9237 return LDS_OP2_LDS_AND_RET;
9238 case TGSI_OPCODE_ATOMOR:
9239 return LDS_OP2_LDS_OR_RET;
9240 case TGSI_OPCODE_ATOMXOR:
9241 return LDS_OP2_LDS_XOR_RET;
9242 case TGSI_OPCODE_ATOMUMIN:
9243 return LDS_OP2_LDS_MIN_UINT_RET;
9244 case TGSI_OPCODE_ATOMUMAX:
9245 return LDS_OP2_LDS_MAX_UINT_RET;
9246 case TGSI_OPCODE_ATOMIMIN:
9247 return LDS_OP2_LDS_MIN_INT_RET;
9248 case TGSI_OPCODE_ATOMIMAX:
9249 return LDS_OP2_LDS_MAX_INT_RET;
9250 case TGSI_OPCODE_ATOMXCHG:
9251 return LDS_OP2_LDS_XCHG_RET;
9252 case TGSI_OPCODE_ATOMCAS:
9253 return LDS_OP3_LDS_CMP_XCHG_RET;
9254 default:
9255 return -1;
9256 }
9257 }
9258
9259 static int tgsi_atomic_op_lds(struct r600_shader_ctx *ctx)
9260 {
9261 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9262 int lds_op = get_lds_op(inst->Instruction.Opcode);
9263 int r;
9264
9265 struct r600_bytecode_alu alu;
9266 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9267 alu.op = lds_op;
9268 alu.is_lds_idx_op = true;
9269 alu.last = 1;
9270 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
9271 r600_bytecode_src(&alu.src[1], &ctx->src[2], 0);
9272 if (lds_op == LDS_OP3_LDS_CMP_XCHG_RET)
9273 r600_bytecode_src(&alu.src[2], &ctx->src[3], 0);
9274 else
9275 alu.src[2].sel = V_SQ_ALU_SRC_0;
9276 r = r600_bytecode_add_alu(ctx->bc, &alu);
9277 if (r)
9278 return r;
9279
9280 /* then read from LDS_OQ_A_POP */
9281 memset(&alu, 0, sizeof(alu));
9282
9283 alu.op = ALU_OP1_MOV;
9284 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
9285 alu.src[0].chan = 0;
9286 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
9287 alu.dst.write = 1;
9288 alu.last = 1;
9289 r = r600_bytecode_add_alu(ctx->bc, &alu);
9290 if (r)
9291 return r;
9292
9293 return 0;
9294 }
9295
9296 static int tgsi_atomic_op(struct r600_shader_ctx *ctx)
9297 {
9298 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9299 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
9300 return tgsi_atomic_op_rat(ctx);
9301 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
9302 return tgsi_atomic_op_gds(ctx);
9303 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
9304 return tgsi_atomic_op_rat(ctx);
9305 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
9306 return tgsi_atomic_op_lds(ctx);
9307 return 0;
9308 }
9309
9310 static int tgsi_resq(struct r600_shader_ctx *ctx)
9311 {
9312 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9313 unsigned sampler_index_mode;
9314 struct r600_bytecode_tex tex;
9315 int r;
9316 boolean has_txq_cube_array_z = false;
9317
9318 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
9319 (inst->Src[0].Register.File == TGSI_FILE_IMAGE && inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
9320 if (ctx->bc->chip_class < EVERGREEN)
9321 ctx->shader->uses_tex_buffers = true;
9322 unsigned eg_buffer_base = 0;
9323 eg_buffer_base = R600_IMAGE_REAL_RESOURCE_OFFSET;
9324 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
9325 eg_buffer_base += ctx->info.file_count[TGSI_FILE_IMAGE];
9326 return r600_do_buffer_txq(ctx, 0, ctx->shader->image_size_const_offset, eg_buffer_base);
9327 }
9328
9329 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY &&
9330 inst->Dst[0].Register.WriteMask & 4) {
9331 ctx->shader->has_txq_cube_array_z_comp = true;
9332 has_txq_cube_array_z = true;
9333 }
9334
9335 sampler_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
9336 if (sampler_index_mode)
9337 egcm_load_index_reg(ctx->bc, 1, false);
9338
9339
9340 /* does this shader want a num layers from TXQ for a cube array? */
9341 if (has_txq_cube_array_z) {
9342 int id = tgsi_tex_get_src_gpr(ctx, 0) + ctx->shader->image_size_const_offset;
9343 struct r600_bytecode_alu alu;
9344
9345 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9346 alu.op = ALU_OP1_MOV;
9347
9348 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
9349 /* with eg each dword is either number of cubes */
9350 alu.src[0].sel += id / 4;
9351 alu.src[0].chan = id % 4;
9352 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
9353 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
9354 alu.last = 1;
9355 r = r600_bytecode_add_alu(ctx->bc, &alu);
9356 if (r)
9357 return r;
9358 /* disable writemask from texture instruction */
9359 inst->Dst[0].Register.WriteMask &= ~4;
9360 }
9361 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
9362 tex.op = ctx->inst_info->op;
9363 tex.sampler_id = R600_IMAGE_REAL_RESOURCE_OFFSET + inst->Src[0].Register.Index;
9364 tex.sampler_index_mode = sampler_index_mode;
9365 tex.resource_id = tex.sampler_id;
9366 tex.resource_index_mode = sampler_index_mode;
9367 tex.src_sel_x = 4;
9368 tex.src_sel_y = 4;
9369 tex.src_sel_z = 4;
9370 tex.src_sel_w = 4;
9371 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
9372 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
9373 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
9374 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
9375 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
9376 r = r600_bytecode_add_tex(ctx->bc, &tex);
9377 if (r)
9378 return r;
9379
9380 return 0;
9381 }
9382
9383 static int tgsi_lrp(struct r600_shader_ctx *ctx)
9384 {
9385 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9386 struct r600_bytecode_alu alu;
9387 unsigned lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9388 unsigned i, temp_regs[2];
9389 int r;
9390
9391 /* optimize if it's just an equal balance */
9392 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
9393 for (i = 0; i < lasti + 1; i++) {
9394 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9395 continue;
9396
9397 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9398 alu.op = ALU_OP2_ADD;
9399 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
9400 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9401 alu.omod = 3;
9402 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9403 alu.dst.chan = i;
9404 if (i == lasti) {
9405 alu.last = 1;
9406 }
9407 r = r600_bytecode_add_alu(ctx->bc, &alu);
9408 if (r)
9409 return r;
9410 }
9411 return 0;
9412 }
9413
9414 /* 1 - src0 */
9415 for (i = 0; i < lasti + 1; i++) {
9416 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9417 continue;
9418
9419 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9420 alu.op = ALU_OP2_ADD;
9421 alu.src[0].sel = V_SQ_ALU_SRC_1;
9422 alu.src[0].chan = 0;
9423 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
9424 r600_bytecode_src_toggle_neg(&alu.src[1]);
9425 alu.dst.sel = ctx->temp_reg;
9426 alu.dst.chan = i;
9427 if (i == lasti) {
9428 alu.last = 1;
9429 }
9430 alu.dst.write = 1;
9431 r = r600_bytecode_add_alu(ctx->bc, &alu);
9432 if (r)
9433 return r;
9434 }
9435
9436 /* (1 - src0) * src2 */
9437 for (i = 0; i < lasti + 1; i++) {
9438 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9439 continue;
9440
9441 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9442 alu.op = ALU_OP2_MUL;
9443 alu.src[0].sel = ctx->temp_reg;
9444 alu.src[0].chan = i;
9445 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9446 alu.dst.sel = ctx->temp_reg;
9447 alu.dst.chan = i;
9448 if (i == lasti) {
9449 alu.last = 1;
9450 }
9451 alu.dst.write = 1;
9452 r = r600_bytecode_add_alu(ctx->bc, &alu);
9453 if (r)
9454 return r;
9455 }
9456
9457 /* src0 * src1 + (1 - src0) * src2 */
9458 if (ctx->src[0].abs)
9459 temp_regs[0] = r600_get_temp(ctx);
9460 else
9461 temp_regs[0] = 0;
9462 if (ctx->src[1].abs)
9463 temp_regs[1] = r600_get_temp(ctx);
9464 else
9465 temp_regs[1] = 0;
9466
9467 for (i = 0; i < lasti + 1; i++) {
9468 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9469 continue;
9470
9471 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9472 alu.op = ALU_OP3_MULADD;
9473 alu.is_op3 = 1;
9474 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
9475 if (r)
9476 return r;
9477 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
9478 if (r)
9479 return r;
9480 alu.src[2].sel = ctx->temp_reg;
9481 alu.src[2].chan = i;
9482
9483 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9484 alu.dst.chan = i;
9485 if (i == lasti) {
9486 alu.last = 1;
9487 }
9488 r = r600_bytecode_add_alu(ctx->bc, &alu);
9489 if (r)
9490 return r;
9491 }
9492 return 0;
9493 }
9494
9495 static int tgsi_cmp(struct r600_shader_ctx *ctx)
9496 {
9497 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9498 struct r600_bytecode_alu alu;
9499 int i, r, j;
9500 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9501 int temp_regs[3];
9502 unsigned op;
9503
9504 if (ctx->src[0].abs && ctx->src[0].neg) {
9505 op = ALU_OP3_CNDE;
9506 ctx->src[0].abs = 0;
9507 ctx->src[0].neg = 0;
9508 } else {
9509 op = ALU_OP3_CNDGE;
9510 }
9511
9512 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
9513 temp_regs[j] = 0;
9514 if (ctx->src[j].abs)
9515 temp_regs[j] = r600_get_temp(ctx);
9516 }
9517
9518 for (i = 0; i < lasti + 1; i++) {
9519 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9520 continue;
9521
9522 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9523 alu.op = op;
9524 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
9525 if (r)
9526 return r;
9527 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
9528 if (r)
9529 return r;
9530 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
9531 if (r)
9532 return r;
9533 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9534 alu.dst.chan = i;
9535 alu.dst.write = 1;
9536 alu.is_op3 = 1;
9537 if (i == lasti)
9538 alu.last = 1;
9539 r = r600_bytecode_add_alu(ctx->bc, &alu);
9540 if (r)
9541 return r;
9542 }
9543 return 0;
9544 }
9545
9546 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
9547 {
9548 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9549 struct r600_bytecode_alu alu;
9550 int i, r;
9551 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9552
9553 for (i = 0; i < lasti + 1; i++) {
9554 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9555 continue;
9556
9557 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9558 alu.op = ALU_OP3_CNDE_INT;
9559 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9560 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9561 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
9562 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9563 alu.dst.chan = i;
9564 alu.dst.write = 1;
9565 alu.is_op3 = 1;
9566 if (i == lasti)
9567 alu.last = 1;
9568 r = r600_bytecode_add_alu(ctx->bc, &alu);
9569 if (r)
9570 return r;
9571 }
9572 return 0;
9573 }
9574
9575 static int tgsi_exp(struct r600_shader_ctx *ctx)
9576 {
9577 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9578 struct r600_bytecode_alu alu;
9579 int r;
9580 unsigned i;
9581
9582 /* result.x = 2^floor(src); */
9583 if (inst->Dst[0].Register.WriteMask & 1) {
9584 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9585
9586 alu.op = ALU_OP1_FLOOR;
9587 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9588
9589 alu.dst.sel = ctx->temp_reg;
9590 alu.dst.chan = 0;
9591 alu.dst.write = 1;
9592 alu.last = 1;
9593 r = r600_bytecode_add_alu(ctx->bc, &alu);
9594 if (r)
9595 return r;
9596
9597 if (ctx->bc->chip_class == CAYMAN) {
9598 for (i = 0; i < 3; i++) {
9599 alu.op = ALU_OP1_EXP_IEEE;
9600 alu.src[0].sel = ctx->temp_reg;
9601 alu.src[0].chan = 0;
9602
9603 alu.dst.sel = ctx->temp_reg;
9604 alu.dst.chan = i;
9605 alu.dst.write = i == 0;
9606 alu.last = i == 2;
9607 r = r600_bytecode_add_alu(ctx->bc, &alu);
9608 if (r)
9609 return r;
9610 }
9611 } else {
9612 alu.op = ALU_OP1_EXP_IEEE;
9613 alu.src[0].sel = ctx->temp_reg;
9614 alu.src[0].chan = 0;
9615
9616 alu.dst.sel = ctx->temp_reg;
9617 alu.dst.chan = 0;
9618 alu.dst.write = 1;
9619 alu.last = 1;
9620 r = r600_bytecode_add_alu(ctx->bc, &alu);
9621 if (r)
9622 return r;
9623 }
9624 }
9625
9626 /* result.y = tmp - floor(tmp); */
9627 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
9628 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9629
9630 alu.op = ALU_OP1_FRACT;
9631 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9632
9633 alu.dst.sel = ctx->temp_reg;
9634 #if 0
9635 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9636 if (r)
9637 return r;
9638 #endif
9639 alu.dst.write = 1;
9640 alu.dst.chan = 1;
9641
9642 alu.last = 1;
9643
9644 r = r600_bytecode_add_alu(ctx->bc, &alu);
9645 if (r)
9646 return r;
9647 }
9648
9649 /* result.z = RoughApprox2ToX(tmp);*/
9650 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
9651 if (ctx->bc->chip_class == CAYMAN) {
9652 for (i = 0; i < 3; i++) {
9653 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9654 alu.op = ALU_OP1_EXP_IEEE;
9655 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9656
9657 alu.dst.sel = ctx->temp_reg;
9658 alu.dst.chan = i;
9659 if (i == 2) {
9660 alu.dst.write = 1;
9661 alu.last = 1;
9662 }
9663
9664 r = r600_bytecode_add_alu(ctx->bc, &alu);
9665 if (r)
9666 return r;
9667 }
9668 } else {
9669 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9670 alu.op = ALU_OP1_EXP_IEEE;
9671 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9672
9673 alu.dst.sel = ctx->temp_reg;
9674 alu.dst.write = 1;
9675 alu.dst.chan = 2;
9676
9677 alu.last = 1;
9678
9679 r = r600_bytecode_add_alu(ctx->bc, &alu);
9680 if (r)
9681 return r;
9682 }
9683 }
9684
9685 /* result.w = 1.0;*/
9686 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
9687 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9688
9689 alu.op = ALU_OP1_MOV;
9690 alu.src[0].sel = V_SQ_ALU_SRC_1;
9691 alu.src[0].chan = 0;
9692
9693 alu.dst.sel = ctx->temp_reg;
9694 alu.dst.chan = 3;
9695 alu.dst.write = 1;
9696 alu.last = 1;
9697 r = r600_bytecode_add_alu(ctx->bc, &alu);
9698 if (r)
9699 return r;
9700 }
9701 return tgsi_helper_copy(ctx, inst);
9702 }
9703
9704 static int tgsi_log(struct r600_shader_ctx *ctx)
9705 {
9706 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9707 struct r600_bytecode_alu alu;
9708 int r;
9709 unsigned i;
9710
9711 /* result.x = floor(log2(|src|)); */
9712 if (inst->Dst[0].Register.WriteMask & 1) {
9713 if (ctx->bc->chip_class == CAYMAN) {
9714 for (i = 0; i < 3; i++) {
9715 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9716
9717 alu.op = ALU_OP1_LOG_IEEE;
9718 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9719 r600_bytecode_src_set_abs(&alu.src[0]);
9720
9721 alu.dst.sel = ctx->temp_reg;
9722 alu.dst.chan = i;
9723 if (i == 0)
9724 alu.dst.write = 1;
9725 if (i == 2)
9726 alu.last = 1;
9727 r = r600_bytecode_add_alu(ctx->bc, &alu);
9728 if (r)
9729 return r;
9730 }
9731
9732 } else {
9733 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9734
9735 alu.op = ALU_OP1_LOG_IEEE;
9736 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9737 r600_bytecode_src_set_abs(&alu.src[0]);
9738
9739 alu.dst.sel = ctx->temp_reg;
9740 alu.dst.chan = 0;
9741 alu.dst.write = 1;
9742 alu.last = 1;
9743 r = r600_bytecode_add_alu(ctx->bc, &alu);
9744 if (r)
9745 return r;
9746 }
9747
9748 alu.op = ALU_OP1_FLOOR;
9749 alu.src[0].sel = ctx->temp_reg;
9750 alu.src[0].chan = 0;
9751
9752 alu.dst.sel = ctx->temp_reg;
9753 alu.dst.chan = 0;
9754 alu.dst.write = 1;
9755 alu.last = 1;
9756
9757 r = r600_bytecode_add_alu(ctx->bc, &alu);
9758 if (r)
9759 return r;
9760 }
9761
9762 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
9763 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
9764
9765 if (ctx->bc->chip_class == CAYMAN) {
9766 for (i = 0; i < 3; i++) {
9767 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9768
9769 alu.op = ALU_OP1_LOG_IEEE;
9770 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9771 r600_bytecode_src_set_abs(&alu.src[0]);
9772
9773 alu.dst.sel = ctx->temp_reg;
9774 alu.dst.chan = i;
9775 if (i == 1)
9776 alu.dst.write = 1;
9777 if (i == 2)
9778 alu.last = 1;
9779
9780 r = r600_bytecode_add_alu(ctx->bc, &alu);
9781 if (r)
9782 return r;
9783 }
9784 } else {
9785 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9786
9787 alu.op = ALU_OP1_LOG_IEEE;
9788 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9789 r600_bytecode_src_set_abs(&alu.src[0]);
9790
9791 alu.dst.sel = ctx->temp_reg;
9792 alu.dst.chan = 1;
9793 alu.dst.write = 1;
9794 alu.last = 1;
9795
9796 r = r600_bytecode_add_alu(ctx->bc, &alu);
9797 if (r)
9798 return r;
9799 }
9800
9801 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9802
9803 alu.op = ALU_OP1_FLOOR;
9804 alu.src[0].sel = ctx->temp_reg;
9805 alu.src[0].chan = 1;
9806
9807 alu.dst.sel = ctx->temp_reg;
9808 alu.dst.chan = 1;
9809 alu.dst.write = 1;
9810 alu.last = 1;
9811
9812 r = r600_bytecode_add_alu(ctx->bc, &alu);
9813 if (r)
9814 return r;
9815
9816 if (ctx->bc->chip_class == CAYMAN) {
9817 for (i = 0; i < 3; i++) {
9818 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9819 alu.op = ALU_OP1_EXP_IEEE;
9820 alu.src[0].sel = ctx->temp_reg;
9821 alu.src[0].chan = 1;
9822
9823 alu.dst.sel = ctx->temp_reg;
9824 alu.dst.chan = i;
9825 if (i == 1)
9826 alu.dst.write = 1;
9827 if (i == 2)
9828 alu.last = 1;
9829
9830 r = r600_bytecode_add_alu(ctx->bc, &alu);
9831 if (r)
9832 return r;
9833 }
9834 } else {
9835 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9836 alu.op = ALU_OP1_EXP_IEEE;
9837 alu.src[0].sel = ctx->temp_reg;
9838 alu.src[0].chan = 1;
9839
9840 alu.dst.sel = ctx->temp_reg;
9841 alu.dst.chan = 1;
9842 alu.dst.write = 1;
9843 alu.last = 1;
9844
9845 r = r600_bytecode_add_alu(ctx->bc, &alu);
9846 if (r)
9847 return r;
9848 }
9849
9850 if (ctx->bc->chip_class == CAYMAN) {
9851 for (i = 0; i < 3; i++) {
9852 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9853 alu.op = ALU_OP1_RECIP_IEEE;
9854 alu.src[0].sel = ctx->temp_reg;
9855 alu.src[0].chan = 1;
9856
9857 alu.dst.sel = ctx->temp_reg;
9858 alu.dst.chan = i;
9859 if (i == 1)
9860 alu.dst.write = 1;
9861 if (i == 2)
9862 alu.last = 1;
9863
9864 r = r600_bytecode_add_alu(ctx->bc, &alu);
9865 if (r)
9866 return r;
9867 }
9868 } else {
9869 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9870 alu.op = ALU_OP1_RECIP_IEEE;
9871 alu.src[0].sel = ctx->temp_reg;
9872 alu.src[0].chan = 1;
9873
9874 alu.dst.sel = ctx->temp_reg;
9875 alu.dst.chan = 1;
9876 alu.dst.write = 1;
9877 alu.last = 1;
9878
9879 r = r600_bytecode_add_alu(ctx->bc, &alu);
9880 if (r)
9881 return r;
9882 }
9883
9884 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9885
9886 alu.op = ALU_OP2_MUL;
9887
9888 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9889 r600_bytecode_src_set_abs(&alu.src[0]);
9890
9891 alu.src[1].sel = ctx->temp_reg;
9892 alu.src[1].chan = 1;
9893
9894 alu.dst.sel = ctx->temp_reg;
9895 alu.dst.chan = 1;
9896 alu.dst.write = 1;
9897 alu.last = 1;
9898
9899 r = r600_bytecode_add_alu(ctx->bc, &alu);
9900 if (r)
9901 return r;
9902 }
9903
9904 /* result.z = log2(|src|);*/
9905 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
9906 if (ctx->bc->chip_class == CAYMAN) {
9907 for (i = 0; i < 3; i++) {
9908 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9909
9910 alu.op = ALU_OP1_LOG_IEEE;
9911 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9912 r600_bytecode_src_set_abs(&alu.src[0]);
9913
9914 alu.dst.sel = ctx->temp_reg;
9915 if (i == 2)
9916 alu.dst.write = 1;
9917 alu.dst.chan = i;
9918 if (i == 2)
9919 alu.last = 1;
9920
9921 r = r600_bytecode_add_alu(ctx->bc, &alu);
9922 if (r)
9923 return r;
9924 }
9925 } else {
9926 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9927
9928 alu.op = ALU_OP1_LOG_IEEE;
9929 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9930 r600_bytecode_src_set_abs(&alu.src[0]);
9931
9932 alu.dst.sel = ctx->temp_reg;
9933 alu.dst.write = 1;
9934 alu.dst.chan = 2;
9935 alu.last = 1;
9936
9937 r = r600_bytecode_add_alu(ctx->bc, &alu);
9938 if (r)
9939 return r;
9940 }
9941 }
9942
9943 /* result.w = 1.0; */
9944 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
9945 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9946
9947 alu.op = ALU_OP1_MOV;
9948 alu.src[0].sel = V_SQ_ALU_SRC_1;
9949 alu.src[0].chan = 0;
9950
9951 alu.dst.sel = ctx->temp_reg;
9952 alu.dst.chan = 3;
9953 alu.dst.write = 1;
9954 alu.last = 1;
9955
9956 r = r600_bytecode_add_alu(ctx->bc, &alu);
9957 if (r)
9958 return r;
9959 }
9960
9961 return tgsi_helper_copy(ctx, inst);
9962 }
9963
9964 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
9965 {
9966 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9967 struct r600_bytecode_alu alu;
9968 int r;
9969 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9970 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
9971
9972 assert(inst->Dst[0].Register.Index < 3);
9973 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9974
9975 switch (inst->Instruction.Opcode) {
9976 case TGSI_OPCODE_ARL:
9977 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
9978 break;
9979 case TGSI_OPCODE_ARR:
9980 alu.op = ALU_OP1_FLT_TO_INT;
9981 break;
9982 case TGSI_OPCODE_UARL:
9983 alu.op = ALU_OP1_MOV;
9984 break;
9985 default:
9986 assert(0);
9987 return -1;
9988 }
9989
9990 for (i = 0; i <= lasti; ++i) {
9991 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9992 continue;
9993 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9994 alu.last = i == lasti;
9995 alu.dst.sel = reg;
9996 alu.dst.chan = i;
9997 alu.dst.write = 1;
9998 r = r600_bytecode_add_alu(ctx->bc, &alu);
9999 if (r)
10000 return r;
10001 }
10002
10003 if (inst->Dst[0].Register.Index > 0)
10004 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
10005 else
10006 ctx->bc->ar_loaded = 0;
10007
10008 return 0;
10009 }
10010 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
10011 {
10012 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10013 struct r600_bytecode_alu alu;
10014 int r;
10015 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10016
10017 switch (inst->Instruction.Opcode) {
10018 case TGSI_OPCODE_ARL:
10019 memset(&alu, 0, sizeof(alu));
10020 alu.op = ALU_OP1_FLOOR;
10021 alu.dst.sel = ctx->bc->ar_reg;
10022 alu.dst.write = 1;
10023 for (i = 0; i <= lasti; ++i) {
10024 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
10025 alu.dst.chan = i;
10026 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
10027 alu.last = i == lasti;
10028 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
10029 return r;
10030 }
10031 }
10032
10033 memset(&alu, 0, sizeof(alu));
10034 alu.op = ALU_OP1_FLT_TO_INT;
10035 alu.src[0].sel = ctx->bc->ar_reg;
10036 alu.dst.sel = ctx->bc->ar_reg;
10037 alu.dst.write = 1;
10038 /* FLT_TO_INT is trans-only on r600/r700 */
10039 alu.last = TRUE;
10040 for (i = 0; i <= lasti; ++i) {
10041 alu.dst.chan = i;
10042 alu.src[0].chan = i;
10043 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
10044 return r;
10045 }
10046 break;
10047 case TGSI_OPCODE_ARR:
10048 memset(&alu, 0, sizeof(alu));
10049 alu.op = ALU_OP1_FLT_TO_INT;
10050 alu.dst.sel = ctx->bc->ar_reg;
10051 alu.dst.write = 1;
10052 /* FLT_TO_INT is trans-only on r600/r700 */
10053 alu.last = TRUE;
10054 for (i = 0; i <= lasti; ++i) {
10055 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
10056 alu.dst.chan = i;
10057 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
10058 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
10059 return r;
10060 }
10061 }
10062 break;
10063 case TGSI_OPCODE_UARL:
10064 memset(&alu, 0, sizeof(alu));
10065 alu.op = ALU_OP1_MOV;
10066 alu.dst.sel = ctx->bc->ar_reg;
10067 alu.dst.write = 1;
10068 for (i = 0; i <= lasti; ++i) {
10069 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
10070 alu.dst.chan = i;
10071 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
10072 alu.last = i == lasti;
10073 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
10074 return r;
10075 }
10076 }
10077 break;
10078 default:
10079 assert(0);
10080 return -1;
10081 }
10082
10083 ctx->bc->ar_loaded = 0;
10084 return 0;
10085 }
10086
10087 static int tgsi_opdst(struct r600_shader_ctx *ctx)
10088 {
10089 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10090 struct r600_bytecode_alu alu;
10091 int i, r = 0;
10092
10093 for (i = 0; i < 4; i++) {
10094 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10095
10096 alu.op = ALU_OP2_MUL;
10097 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10098
10099 if (i == 0 || i == 3) {
10100 alu.src[0].sel = V_SQ_ALU_SRC_1;
10101 } else {
10102 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
10103 }
10104
10105 if (i == 0 || i == 2) {
10106 alu.src[1].sel = V_SQ_ALU_SRC_1;
10107 } else {
10108 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
10109 }
10110 if (i == 3)
10111 alu.last = 1;
10112 r = r600_bytecode_add_alu(ctx->bc, &alu);
10113 if (r)
10114 return r;
10115 }
10116 return 0;
10117 }
10118
10119 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type,
10120 struct r600_bytecode_alu_src *src)
10121 {
10122 struct r600_bytecode_alu alu;
10123 int r;
10124
10125 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10126 alu.op = opcode;
10127 alu.execute_mask = 1;
10128 alu.update_pred = 1;
10129
10130 alu.dst.sel = ctx->temp_reg;
10131 alu.dst.write = 1;
10132 alu.dst.chan = 0;
10133
10134 alu.src[0] = *src;
10135 alu.src[1].sel = V_SQ_ALU_SRC_0;
10136 alu.src[1].chan = 0;
10137
10138 alu.last = 1;
10139
10140 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
10141 if (r)
10142 return r;
10143 return 0;
10144 }
10145
10146 static int pops(struct r600_shader_ctx *ctx, int pops)
10147 {
10148 unsigned force_pop = ctx->bc->force_add_cf;
10149
10150 if (!force_pop) {
10151 int alu_pop = 3;
10152 if (ctx->bc->cf_last) {
10153 if (ctx->bc->cf_last->op == CF_OP_ALU)
10154 alu_pop = 0;
10155 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
10156 alu_pop = 1;
10157 }
10158 alu_pop += pops;
10159 if (alu_pop == 1) {
10160 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
10161 ctx->bc->force_add_cf = 1;
10162 } else if (alu_pop == 2) {
10163 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
10164 ctx->bc->force_add_cf = 1;
10165 } else {
10166 force_pop = 1;
10167 }
10168 }
10169
10170 if (force_pop) {
10171 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
10172 ctx->bc->cf_last->pop_count = pops;
10173 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
10174 }
10175
10176 return 0;
10177 }
10178
10179 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
10180 unsigned reason)
10181 {
10182 struct r600_stack_info *stack = &ctx->bc->stack;
10183 unsigned elements;
10184 int entries;
10185
10186 unsigned entry_size = stack->entry_size;
10187
10188 elements = (stack->loop + stack->push_wqm ) * entry_size;
10189 elements += stack->push;
10190
10191 switch (ctx->bc->chip_class) {
10192 case R600:
10193 case R700:
10194 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
10195 * the stack must be reserved to hold the current active/continue
10196 * masks */
10197 if (reason == FC_PUSH_VPM) {
10198 elements += 2;
10199 }
10200 break;
10201
10202 case CAYMAN:
10203 /* r9xx: any stack operation on empty stack consumes 2 additional
10204 * elements */
10205 elements += 2;
10206
10207 /* fallthrough */
10208 /* FIXME: do the two elements added above cover the cases for the
10209 * r8xx+ below? */
10210
10211 case EVERGREEN:
10212 /* r8xx+: 2 extra elements are not always required, but one extra
10213 * element must be added for each of the following cases:
10214 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
10215 * stack usage.
10216 * (Currently we don't use ALU_ELSE_AFTER.)
10217 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
10218 * PUSH instruction executed.
10219 *
10220 * NOTE: it seems we also need to reserve additional element in some
10221 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
10222 * then STACK_SIZE should be 2 instead of 1 */
10223 if (reason == FC_PUSH_VPM) {
10224 elements += 1;
10225 }
10226 break;
10227
10228 default:
10229 assert(0);
10230 break;
10231 }
10232
10233 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
10234 * for all chips, so we use 4 in the final formula, not the real entry_size
10235 * for the chip */
10236 entry_size = 4;
10237
10238 entries = (elements + (entry_size - 1)) / entry_size;
10239
10240 if (entries > stack->max_entries)
10241 stack->max_entries = entries;
10242 }
10243
10244 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
10245 {
10246 switch(reason) {
10247 case FC_PUSH_VPM:
10248 --ctx->bc->stack.push;
10249 assert(ctx->bc->stack.push >= 0);
10250 break;
10251 case FC_PUSH_WQM:
10252 --ctx->bc->stack.push_wqm;
10253 assert(ctx->bc->stack.push_wqm >= 0);
10254 break;
10255 case FC_LOOP:
10256 --ctx->bc->stack.loop;
10257 assert(ctx->bc->stack.loop >= 0);
10258 break;
10259 default:
10260 assert(0);
10261 break;
10262 }
10263 }
10264
10265 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
10266 {
10267 switch (reason) {
10268 case FC_PUSH_VPM:
10269 ++ctx->bc->stack.push;
10270 break;
10271 case FC_PUSH_WQM:
10272 ++ctx->bc->stack.push_wqm;
10273 case FC_LOOP:
10274 ++ctx->bc->stack.loop;
10275 break;
10276 default:
10277 assert(0);
10278 }
10279
10280 callstack_update_max_depth(ctx, reason);
10281 }
10282
10283 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
10284 {
10285 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
10286
10287 sp->mid = realloc((void *)sp->mid,
10288 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
10289 sp->mid[sp->num_mid] = ctx->bc->cf_last;
10290 sp->num_mid++;
10291 }
10292
10293 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
10294 {
10295 assert(ctx->bc->fc_sp < ARRAY_SIZE(ctx->bc->fc_stack));
10296 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
10297 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
10298 ctx->bc->fc_sp++;
10299 }
10300
10301 static void fc_poplevel(struct r600_shader_ctx *ctx)
10302 {
10303 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp - 1];
10304 free(sp->mid);
10305 sp->mid = NULL;
10306 sp->num_mid = 0;
10307 sp->start = NULL;
10308 sp->type = 0;
10309 ctx->bc->fc_sp--;
10310 }
10311
10312 #if 0
10313 static int emit_return(struct r600_shader_ctx *ctx)
10314 {
10315 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
10316 return 0;
10317 }
10318
10319 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
10320 {
10321
10322 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
10323 ctx->bc->cf_last->pop_count = pops;
10324 /* XXX work out offset */
10325 return 0;
10326 }
10327
10328 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
10329 {
10330 return 0;
10331 }
10332
10333 static void emit_testflag(struct r600_shader_ctx *ctx)
10334 {
10335
10336 }
10337
10338 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
10339 {
10340 emit_testflag(ctx);
10341 emit_jump_to_offset(ctx, 1, 4);
10342 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
10343 pops(ctx, ifidx + 1);
10344 emit_return(ctx);
10345 }
10346
10347 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
10348 {
10349 emit_testflag(ctx);
10350
10351 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
10352 ctx->bc->cf_last->pop_count = 1;
10353
10354 fc_set_mid(ctx, fc_sp);
10355
10356 pops(ctx, 1);
10357 }
10358 #endif
10359
10360 static int emit_if(struct r600_shader_ctx *ctx, int opcode,
10361 struct r600_bytecode_alu_src *src)
10362 {
10363 int alu_type = CF_OP_ALU_PUSH_BEFORE;
10364
10365 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
10366 * LOOP_STARTxxx for nested loops may put the branch stack into a state
10367 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
10368 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
10369 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
10370 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
10371 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
10372 alu_type = CF_OP_ALU;
10373 }
10374
10375 emit_logic_pred(ctx, opcode, alu_type, src);
10376
10377 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
10378
10379 fc_pushlevel(ctx, FC_IF);
10380
10381 callstack_push(ctx, FC_PUSH_VPM);
10382 return 0;
10383 }
10384
10385 static int tgsi_if(struct r600_shader_ctx *ctx)
10386 {
10387 struct r600_bytecode_alu_src alu_src;
10388 r600_bytecode_src(&alu_src, &ctx->src[0], 0);
10389
10390 return emit_if(ctx, ALU_OP2_PRED_SETNE, &alu_src);
10391 }
10392
10393 static int tgsi_uif(struct r600_shader_ctx *ctx)
10394 {
10395 struct r600_bytecode_alu_src alu_src;
10396 r600_bytecode_src(&alu_src, &ctx->src[0], 0);
10397 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
10398 }
10399
10400 static int tgsi_else(struct r600_shader_ctx *ctx)
10401 {
10402 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
10403 ctx->bc->cf_last->pop_count = 1;
10404
10405 fc_set_mid(ctx, ctx->bc->fc_sp - 1);
10406 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id;
10407 return 0;
10408 }
10409
10410 static int tgsi_endif(struct r600_shader_ctx *ctx)
10411 {
10412 int offset = 2;
10413 pops(ctx, 1);
10414 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_IF) {
10415 R600_ERR("if/endif unbalanced in shader\n");
10416 return -1;
10417 }
10418
10419 /* ALU_EXTENDED needs 4 DWords instead of two, adjust jump target offset accordingly */
10420 if (ctx->bc->cf_last->eg_alu_extended)
10421 offset += 2;
10422
10423 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid == NULL) {
10424 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + offset;
10425 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->pop_count = 1;
10426 } else {
10427 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = ctx->bc->cf_last->id + offset;
10428 }
10429 fc_poplevel(ctx);
10430
10431 callstack_pop(ctx, FC_PUSH_VPM);
10432 return 0;
10433 }
10434
10435 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
10436 {
10437 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
10438 * limited to 4096 iterations, like the other LOOP_* instructions. */
10439 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
10440
10441 fc_pushlevel(ctx, FC_LOOP);
10442
10443 /* check stack depth */
10444 callstack_push(ctx, FC_LOOP);
10445 return 0;
10446 }
10447
10448 static int tgsi_endloop(struct r600_shader_ctx *ctx)
10449 {
10450 int i;
10451
10452 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
10453
10454 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_LOOP) {
10455 R600_ERR("loop/endloop in shader code are not paired.\n");
10456 return -EINVAL;
10457 }
10458
10459 /* fixup loop pointers - from r600isa
10460 LOOP END points to CF after LOOP START,
10461 LOOP START point to CF after LOOP END
10462 BRK/CONT point to LOOP END CF
10463 */
10464 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->id + 2;
10465
10466 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
10467
10468 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp - 1].num_mid; i++) {
10469 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[i]->cf_addr = ctx->bc->cf_last->id;
10470 }
10471 /* XXX add LOOPRET support */
10472 fc_poplevel(ctx);
10473 callstack_pop(ctx, FC_LOOP);
10474 return 0;
10475 }
10476
10477 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
10478 {
10479 unsigned int fscp;
10480
10481 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
10482 {
10483 if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
10484 break;
10485 }
10486
10487 if (fscp == 0) {
10488 R600_ERR("Break not inside loop/endloop pair\n");
10489 return -EINVAL;
10490 }
10491
10492 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
10493
10494 fc_set_mid(ctx, fscp - 1);
10495
10496 return 0;
10497 }
10498
10499 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
10500 {
10501 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10502 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
10503 int r;
10504
10505 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
10506 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
10507
10508 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
10509 if (!r) {
10510 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
10511 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
10512 return emit_inc_ring_offset(ctx, stream, TRUE);
10513 }
10514 return r;
10515 }
10516
10517 static int tgsi_umad(struct r600_shader_ctx *ctx)
10518 {
10519 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10520 struct r600_bytecode_alu alu;
10521 int i, j, r;
10522 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10523
10524 /* src0 * src1 */
10525 for (i = 0; i < lasti + 1; i++) {
10526 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10527 continue;
10528
10529 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10530
10531 alu.dst.chan = i;
10532 alu.dst.sel = ctx->temp_reg;
10533 alu.dst.write = 1;
10534
10535 alu.op = ALU_OP2_MULLO_UINT;
10536 for (j = 0; j < 2; j++) {
10537 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
10538 }
10539
10540 alu.last = 1;
10541 r = emit_mul_int_op(ctx->bc, &alu);
10542 if (r)
10543 return r;
10544 }
10545
10546
10547 for (i = 0; i < lasti + 1; i++) {
10548 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10549 continue;
10550
10551 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10552 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10553
10554 alu.op = ALU_OP2_ADD_INT;
10555
10556 alu.src[0].sel = ctx->temp_reg;
10557 alu.src[0].chan = i;
10558
10559 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
10560 if (i == lasti) {
10561 alu.last = 1;
10562 }
10563 r = r600_bytecode_add_alu(ctx->bc, &alu);
10564 if (r)
10565 return r;
10566 }
10567 return 0;
10568 }
10569
10570 static int tgsi_pk2h(struct r600_shader_ctx *ctx)
10571 {
10572 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10573 struct r600_bytecode_alu alu;
10574 int r, i;
10575 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10576
10577 /* temp.xy = f32_to_f16(src) */
10578 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10579 alu.op = ALU_OP1_FLT32_TO_FLT16;
10580 alu.dst.chan = 0;
10581 alu.dst.sel = ctx->temp_reg;
10582 alu.dst.write = 1;
10583 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10584 r = r600_bytecode_add_alu(ctx->bc, &alu);
10585 if (r)
10586 return r;
10587 alu.dst.chan = 1;
10588 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
10589 alu.last = 1;
10590 r = r600_bytecode_add_alu(ctx->bc, &alu);
10591 if (r)
10592 return r;
10593
10594 /* dst.x = temp.y * 0x10000 + temp.x */
10595 for (i = 0; i < lasti + 1; i++) {
10596 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10597 continue;
10598
10599 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10600 alu.op = ALU_OP3_MULADD_UINT24;
10601 alu.is_op3 = 1;
10602 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10603 alu.last = i == lasti;
10604 alu.src[0].sel = ctx->temp_reg;
10605 alu.src[0].chan = 1;
10606 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10607 alu.src[1].value = 0x10000;
10608 alu.src[2].sel = ctx->temp_reg;
10609 alu.src[2].chan = 0;
10610 r = r600_bytecode_add_alu(ctx->bc, &alu);
10611 if (r)
10612 return r;
10613 }
10614
10615 return 0;
10616 }
10617
10618 static int tgsi_up2h(struct r600_shader_ctx *ctx)
10619 {
10620 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10621 struct r600_bytecode_alu alu;
10622 int r, i;
10623 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10624
10625 /* temp.x = src.x */
10626 /* note: no need to mask out the high bits */
10627 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10628 alu.op = ALU_OP1_MOV;
10629 alu.dst.chan = 0;
10630 alu.dst.sel = ctx->temp_reg;
10631 alu.dst.write = 1;
10632 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10633 r = r600_bytecode_add_alu(ctx->bc, &alu);
10634 if (r)
10635 return r;
10636
10637 /* temp.y = src.x >> 16 */
10638 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10639 alu.op = ALU_OP2_LSHR_INT;
10640 alu.dst.chan = 1;
10641 alu.dst.sel = ctx->temp_reg;
10642 alu.dst.write = 1;
10643 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10644 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10645 alu.src[1].value = 16;
10646 alu.last = 1;
10647 r = r600_bytecode_add_alu(ctx->bc, &alu);
10648 if (r)
10649 return r;
10650
10651 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
10652 for (i = 0; i < lasti + 1; i++) {
10653 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10654 continue;
10655 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10656 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10657 alu.op = ALU_OP1_FLT16_TO_FLT32;
10658 alu.src[0].sel = ctx->temp_reg;
10659 alu.src[0].chan = i % 2;
10660 alu.last = i == lasti;
10661 r = r600_bytecode_add_alu(ctx->bc, &alu);
10662 if (r)
10663 return r;
10664 }
10665
10666 return 0;
10667 }
10668
10669 static int tgsi_bfe(struct r600_shader_ctx *ctx)
10670 {
10671 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10672 struct r600_bytecode_alu alu;
10673 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10674 int r, i;
10675 int dst = -1;
10676
10677 if ((inst->Src[0].Register.File == inst->Dst[0].Register.File &&
10678 inst->Src[0].Register.Index == inst->Dst[0].Register.Index) ||
10679 (inst->Src[2].Register.File == inst->Dst[0].Register.File &&
10680 inst->Src[2].Register.Index == inst->Dst[0].Register.Index))
10681 dst = r600_get_temp(ctx);
10682
10683 r = tgsi_op3_dst(ctx, dst);
10684 if (r)
10685 return r;
10686
10687 for (i = 0; i < lasti + 1; i++) {
10688 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10689 alu.op = ALU_OP2_SETGE_INT;
10690 r600_bytecode_src(&alu.src[0], &ctx->src[2], i);
10691 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10692 alu.src[1].value = 32;
10693 alu.dst.sel = ctx->temp_reg;
10694 alu.dst.chan = i;
10695 alu.dst.write = 1;
10696 if (i == lasti)
10697 alu.last = 1;
10698 r = r600_bytecode_add_alu(ctx->bc, &alu);
10699 if (r)
10700 return r;
10701 }
10702
10703 for (i = 0; i < lasti + 1; i++) {
10704 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10705 alu.op = ALU_OP3_CNDE_INT;
10706 alu.is_op3 = 1;
10707 alu.src[0].sel = ctx->temp_reg;
10708 alu.src[0].chan = i;
10709
10710 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10711 if (dst != -1)
10712 alu.src[1].sel = dst;
10713 else
10714 alu.src[1].sel = alu.dst.sel;
10715 alu.src[1].chan = i;
10716 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
10717 alu.dst.write = 1;
10718 if (i == lasti)
10719 alu.last = 1;
10720 r = r600_bytecode_add_alu(ctx->bc, &alu);
10721 if (r)
10722 return r;
10723 }
10724
10725 return 0;
10726 }
10727
10728 static int tgsi_clock(struct r600_shader_ctx *ctx)
10729 {
10730 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10731 struct r600_bytecode_alu alu;
10732 int r;
10733
10734 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10735 alu.op = ALU_OP1_MOV;
10736 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
10737 alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_LO;
10738 r = r600_bytecode_add_alu(ctx->bc, &alu);
10739 if (r)
10740 return r;
10741 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10742 alu.op = ALU_OP1_MOV;
10743 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
10744 alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_HI;
10745 r = r600_bytecode_add_alu(ctx->bc, &alu);
10746 if (r)
10747 return r;
10748 return 0;
10749 }
10750
10751 static int emit_u64add(struct r600_shader_ctx *ctx, int op,
10752 int treg,
10753 int src0_sel, int src0_chan,
10754 int src1_sel, int src1_chan)
10755 {
10756 struct r600_bytecode_alu alu;
10757 int r;
10758 int opc;
10759
10760 if (op == ALU_OP2_ADD_INT)
10761 opc = ALU_OP2_ADDC_UINT;
10762 else
10763 opc = ALU_OP2_SUBB_UINT;
10764
10765 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10766 alu.op = op; ;
10767 alu.dst.sel = treg;
10768 alu.dst.chan = 0;
10769 alu.dst.write = 1;
10770 alu.src[0].sel = src0_sel;
10771 alu.src[0].chan = src0_chan + 0;
10772 alu.src[1].sel = src1_sel;
10773 alu.src[1].chan = src1_chan + 0;
10774 alu.src[1].neg = 0;
10775 r = r600_bytecode_add_alu(ctx->bc, &alu);
10776 if (r)
10777 return r;
10778
10779 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10780 alu.op = op;
10781 alu.dst.sel = treg;
10782 alu.dst.chan = 1;
10783 alu.dst.write = 1;
10784 alu.src[0].sel = src0_sel;
10785 alu.src[0].chan = src0_chan + 1;
10786 alu.src[1].sel = src1_sel;
10787 alu.src[1].chan = src1_chan + 1;
10788 alu.src[1].neg = 0;
10789 r = r600_bytecode_add_alu(ctx->bc, &alu);
10790 if (r)
10791 return r;
10792
10793 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10794 alu.op = opc;
10795 alu.dst.sel = treg;
10796 alu.dst.chan = 2;
10797 alu.dst.write = 1;
10798 alu.last = 1;
10799 alu.src[0].sel = src0_sel;
10800 alu.src[0].chan = src0_chan + 0;
10801 alu.src[1].sel = src1_sel;
10802 alu.src[1].chan = src1_chan + 0;
10803 alu.src[1].neg = 0;
10804 r = r600_bytecode_add_alu(ctx->bc, &alu);
10805 if (r)
10806 return r;
10807
10808 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10809 alu.op = op;
10810 alu.dst.sel = treg;
10811 alu.dst.chan = 1;
10812 alu.dst.write = 1;
10813 alu.src[0].sel = treg;
10814 alu.src[0].chan = 1;
10815 alu.src[1].sel = treg;
10816 alu.src[1].chan = 2;
10817 alu.last = 1;
10818 r = r600_bytecode_add_alu(ctx->bc, &alu);
10819 if (r)
10820 return r;
10821 return 0;
10822 }
10823
10824 static int egcm_u64add(struct r600_shader_ctx *ctx)
10825 {
10826 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10827 struct r600_bytecode_alu alu;
10828 int r;
10829 int treg = ctx->temp_reg;
10830 int op = ALU_OP2_ADD_INT, opc = ALU_OP2_ADDC_UINT;
10831
10832 if (ctx->src[1].neg) {
10833 op = ALU_OP2_SUB_INT;
10834 opc = ALU_OP2_SUBB_UINT;
10835 }
10836 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10837 alu.op = op; ;
10838 alu.dst.sel = treg;
10839 alu.dst.chan = 0;
10840 alu.dst.write = 1;
10841 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10842 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10843 alu.src[1].neg = 0;
10844 r = r600_bytecode_add_alu(ctx->bc, &alu);
10845 if (r)
10846 return r;
10847
10848 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10849 alu.op = op;
10850 alu.dst.sel = treg;
10851 alu.dst.chan = 1;
10852 alu.dst.write = 1;
10853 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
10854 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
10855 alu.src[1].neg = 0;
10856 r = r600_bytecode_add_alu(ctx->bc, &alu);
10857 if (r)
10858 return r;
10859
10860 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10861 alu.op = opc ;
10862 alu.dst.sel = treg;
10863 alu.dst.chan = 2;
10864 alu.dst.write = 1;
10865 alu.last = 1;
10866 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10867 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10868 alu.src[1].neg = 0;
10869 r = r600_bytecode_add_alu(ctx->bc, &alu);
10870 if (r)
10871 return r;
10872
10873 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10874 alu.op = op;
10875 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
10876 alu.src[0].sel = treg;
10877 alu.src[0].chan = 1;
10878 alu.src[1].sel = treg;
10879 alu.src[1].chan = 2;
10880 alu.last = 1;
10881 r = r600_bytecode_add_alu(ctx->bc, &alu);
10882 if (r)
10883 return r;
10884 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10885 alu.op = ALU_OP1_MOV;
10886 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
10887 alu.src[0].sel = treg;
10888 alu.src[0].chan = 0;
10889 alu.last = 1;
10890 r = r600_bytecode_add_alu(ctx->bc, &alu);
10891 if (r)
10892 return r;
10893 return 0;
10894 }
10895
10896 /* result.y = mul_high a, b
10897 result.x = mul a,b
10898 result.y += a.x * b.y + a.y * b.x;
10899 */
10900 static int egcm_u64mul(struct r600_shader_ctx *ctx)
10901 {
10902 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10903 struct r600_bytecode_alu alu;
10904 int r;
10905 int treg = ctx->temp_reg;
10906
10907 /* temp.x = mul_lo a.x, b.x */
10908 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10909 alu.op = ALU_OP2_MULLO_UINT;
10910 alu.dst.sel = treg;
10911 alu.dst.chan = 0;
10912 alu.dst.write = 1;
10913 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10914 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10915 r = emit_mul_int_op(ctx->bc, &alu);
10916 if (r)
10917 return r;
10918
10919 /* temp.y = mul_hi a.x, b.x */
10920 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10921 alu.op = ALU_OP2_MULHI_UINT;
10922 alu.dst.sel = treg;
10923 alu.dst.chan = 1;
10924 alu.dst.write = 1;
10925 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10926 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10927 r = emit_mul_int_op(ctx->bc, &alu);
10928 if (r)
10929 return r;
10930
10931 /* temp.z = mul a.x, b.y */
10932 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10933 alu.op = ALU_OP2_MULLO_UINT;
10934 alu.dst.sel = treg;
10935 alu.dst.chan = 2;
10936 alu.dst.write = 1;
10937 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10938 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
10939 r = emit_mul_int_op(ctx->bc, &alu);
10940 if (r)
10941 return r;
10942
10943 /* temp.w = mul a.y, b.x */
10944 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10945 alu.op = ALU_OP2_MULLO_UINT;
10946 alu.dst.sel = treg;
10947 alu.dst.chan = 3;
10948 alu.dst.write = 1;
10949 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
10950 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10951 r = emit_mul_int_op(ctx->bc, &alu);
10952 if (r)
10953 return r;
10954
10955 /* temp.z = temp.z + temp.w */
10956 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10957 alu.op = ALU_OP2_ADD_INT;
10958 alu.dst.sel = treg;
10959 alu.dst.chan = 2;
10960 alu.dst.write = 1;
10961 alu.src[0].sel = treg;
10962 alu.src[0].chan = 2;
10963 alu.src[1].sel = treg;
10964 alu.src[1].chan = 3;
10965 alu.last = 1;
10966 r = r600_bytecode_add_alu(ctx->bc, &alu);
10967 if (r)
10968 return r;
10969
10970 /* temp.y = temp.y + temp.z */
10971 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10972 alu.op = ALU_OP2_ADD_INT;
10973 alu.dst.sel = treg;
10974 alu.dst.chan = 1;
10975 alu.dst.write = 1;
10976 alu.src[0].sel = treg;
10977 alu.src[0].chan = 1;
10978 alu.src[1].sel = treg;
10979 alu.src[1].chan = 2;
10980 alu.last = 1;
10981 r = r600_bytecode_add_alu(ctx->bc, &alu);
10982 if (r)
10983 return r;
10984
10985 /* dst.x = temp.x */
10986 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10987 alu.op = ALU_OP1_MOV;
10988 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
10989 alu.src[0].sel = treg;
10990 alu.src[0].chan = 0;
10991 r = r600_bytecode_add_alu(ctx->bc, &alu);
10992 if (r)
10993 return r;
10994
10995 /* dst.y = temp.y */
10996 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10997 alu.op = ALU_OP1_MOV;
10998 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
10999 alu.src[0].sel = treg;
11000 alu.src[0].chan = 1;
11001 alu.last = 1;
11002 r = r600_bytecode_add_alu(ctx->bc, &alu);
11003 if (r)
11004 return r;
11005
11006 return 0;
11007 }
11008
11009 static int emit_u64sge(struct r600_shader_ctx *ctx,
11010 int treg,
11011 int src0_sel, int src0_base_chan,
11012 int src1_sel, int src1_base_chan)
11013 {
11014 int r;
11015 /* for 64-bit sge */
11016 /* result = (src0.y > src1.y) || ((src0.y == src1.y) && src0.x >= src1.x)) */
11017 r = single_alu_op2(ctx, ALU_OP2_SETGT_UINT,
11018 treg, 1,
11019 src0_sel, src0_base_chan + 1,
11020 src1_sel, src1_base_chan + 1);
11021 if (r)
11022 return r;
11023
11024 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
11025 treg, 0,
11026 src0_sel, src0_base_chan,
11027 src1_sel, src1_base_chan);
11028 if (r)
11029 return r;
11030
11031 r = single_alu_op2(ctx, ALU_OP2_SETE_INT,
11032 treg, 2,
11033 src0_sel, src0_base_chan + 1,
11034 src1_sel, src1_base_chan + 1);
11035 if (r)
11036 return r;
11037
11038 r = single_alu_op2(ctx, ALU_OP2_AND_INT,
11039 treg, 0,
11040 treg, 0,
11041 treg, 2);
11042 if (r)
11043 return r;
11044
11045 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
11046 treg, 0,
11047 treg, 0,
11048 treg, 1);
11049 if (r)
11050 return r;
11051 return 0;
11052 }
11053
11054 /* this isn't a complete div it's just enough for qbo shader to work */
11055 static int egcm_u64div(struct r600_shader_ctx *ctx)
11056 {
11057 struct r600_bytecode_alu alu;
11058 struct r600_bytecode_alu_src alu_num_hi, alu_num_lo, alu_denom_hi, alu_denom_lo, alu_src;
11059 int r, i;
11060 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
11061
11062 /* make sure we are dividing my a const with 0 in the high bits */
11063 if (ctx->src[1].sel != V_SQ_ALU_SRC_LITERAL)
11064 return -1;
11065 if (ctx->src[1].value[ctx->src[1].swizzle[1]] != 0)
11066 return -1;
11067 /* make sure we are doing one division */
11068 if (inst->Dst[0].Register.WriteMask != 0x3)
11069 return -1;
11070
11071 /* emit_if uses ctx->temp_reg so we can't */
11072 int treg = r600_get_temp(ctx);
11073 int tmp_num = r600_get_temp(ctx);
11074 int sub_tmp = r600_get_temp(ctx);
11075
11076 /* tmp quot are tmp_num.zw */
11077 r600_bytecode_src(&alu_num_lo, &ctx->src[0], 0);
11078 r600_bytecode_src(&alu_num_hi, &ctx->src[0], 1);
11079 r600_bytecode_src(&alu_denom_lo, &ctx->src[1], 0);
11080 r600_bytecode_src(&alu_denom_hi, &ctx->src[1], 1);
11081
11082 /* MOV tmp_num.xy, numerator */
11083 r = single_alu_op2(ctx, ALU_OP1_MOV,
11084 tmp_num, 0,
11085 alu_num_lo.sel, alu_num_lo.chan,
11086 0, 0);
11087 if (r)
11088 return r;
11089 r = single_alu_op2(ctx, ALU_OP1_MOV,
11090 tmp_num, 1,
11091 alu_num_hi.sel, alu_num_hi.chan,
11092 0, 0);
11093 if (r)
11094 return r;
11095
11096 r = single_alu_op2(ctx, ALU_OP1_MOV,
11097 tmp_num, 2,
11098 V_SQ_ALU_SRC_LITERAL, 0,
11099 0, 0);
11100 if (r)
11101 return r;
11102
11103 r = single_alu_op2(ctx, ALU_OP1_MOV,
11104 tmp_num, 3,
11105 V_SQ_ALU_SRC_LITERAL, 0,
11106 0, 0);
11107 if (r)
11108 return r;
11109
11110 /* treg 0 is log2_denom */
11111 /* normally this gets the MSB for the denom high value
11112 - however we know this will always be 0 here. */
11113 r = single_alu_op2(ctx,
11114 ALU_OP1_MOV,
11115 treg, 0,
11116 V_SQ_ALU_SRC_LITERAL, 32,
11117 0, 0);
11118 if (r)
11119 return r;
11120
11121 /* normally check demon hi for 0, but we know it is already */
11122 /* t0.z = num_hi >= denom_lo */
11123 r = single_alu_op2(ctx,
11124 ALU_OP2_SETGE_UINT,
11125 treg, 1,
11126 alu_num_hi.sel, alu_num_hi.chan,
11127 V_SQ_ALU_SRC_LITERAL, alu_denom_lo.value);
11128 if (r)
11129 return r;
11130
11131 memset(&alu_src, 0, sizeof(alu_src));
11132 alu_src.sel = treg;
11133 alu_src.chan = 1;
11134 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
11135 if (r)
11136 return r;
11137
11138 /* for loops in here */
11139 /* get msb t0.x = msb(src[1].x) first */
11140 int msb_lo = util_last_bit(alu_denom_lo.value);
11141 r = single_alu_op2(ctx, ALU_OP1_MOV,
11142 treg, 0,
11143 V_SQ_ALU_SRC_LITERAL, msb_lo,
11144 0, 0);
11145 if (r)
11146 return r;
11147
11148 /* unroll the asm here */
11149 for (i = 0; i < 31; i++) {
11150 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
11151 treg, 2,
11152 V_SQ_ALU_SRC_LITERAL, i,
11153 treg, 0);
11154 if (r)
11155 return r;
11156
11157 /* we can do this on the CPU */
11158 uint32_t denom_lo_shl = alu_denom_lo.value << (31 - i);
11159 /* t0.z = tmp_num.y >= t0.z */
11160 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
11161 treg, 1,
11162 tmp_num, 1,
11163 V_SQ_ALU_SRC_LITERAL, denom_lo_shl);
11164 if (r)
11165 return r;
11166
11167 r = single_alu_op2(ctx, ALU_OP2_AND_INT,
11168 treg, 1,
11169 treg, 1,
11170 treg, 2);
11171 if (r)
11172 return r;
11173
11174 memset(&alu_src, 0, sizeof(alu_src));
11175 alu_src.sel = treg;
11176 alu_src.chan = 1;
11177 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
11178 if (r)
11179 return r;
11180
11181 r = single_alu_op2(ctx, ALU_OP2_SUB_INT,
11182 tmp_num, 1,
11183 tmp_num, 1,
11184 V_SQ_ALU_SRC_LITERAL, denom_lo_shl);
11185 if (r)
11186 return r;
11187
11188 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
11189 tmp_num, 3,
11190 tmp_num, 3,
11191 V_SQ_ALU_SRC_LITERAL, 1U << (31 - i));
11192 if (r)
11193 return r;
11194
11195 r = tgsi_endif(ctx);
11196 if (r)
11197 return r;
11198 }
11199
11200 /* log2_denom is always <= 31, so manually peel the last loop
11201 * iteration.
11202 */
11203 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
11204 treg, 1,
11205 tmp_num, 1,
11206 V_SQ_ALU_SRC_LITERAL, alu_denom_lo.value);
11207 if (r)
11208 return r;
11209
11210 memset(&alu_src, 0, sizeof(alu_src));
11211 alu_src.sel = treg;
11212 alu_src.chan = 1;
11213 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
11214 if (r)
11215 return r;
11216
11217 r = single_alu_op2(ctx, ALU_OP2_SUB_INT,
11218 tmp_num, 1,
11219 tmp_num, 1,
11220 V_SQ_ALU_SRC_LITERAL, alu_denom_lo.value);
11221 if (r)
11222 return r;
11223
11224 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
11225 tmp_num, 3,
11226 tmp_num, 3,
11227 V_SQ_ALU_SRC_LITERAL, 1U);
11228 if (r)
11229 return r;
11230 r = tgsi_endif(ctx);
11231 if (r)
11232 return r;
11233
11234 r = tgsi_endif(ctx);
11235 if (r)
11236 return r;
11237
11238 /* onto the second loop to unroll */
11239 for (i = 0; i < 31; i++) {
11240 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
11241 treg, 1,
11242 V_SQ_ALU_SRC_LITERAL, (63 - (31 - i)),
11243 treg, 0);
11244 if (r)
11245 return r;
11246
11247 uint64_t denom_shl = (uint64_t)alu_denom_lo.value << (31 - i);
11248 r = single_alu_op2(ctx, ALU_OP1_MOV,
11249 treg, 2,
11250 V_SQ_ALU_SRC_LITERAL, (denom_shl & 0xffffffff),
11251 0, 0);
11252 if (r)
11253 return r;
11254
11255 r = single_alu_op2(ctx, ALU_OP1_MOV,
11256 treg, 3,
11257 V_SQ_ALU_SRC_LITERAL, (denom_shl >> 32),
11258 0, 0);
11259 if (r)
11260 return r;
11261
11262 r = emit_u64sge(ctx, sub_tmp,
11263 tmp_num, 0,
11264 treg, 2);
11265 if (r)
11266 return r;
11267
11268 r = single_alu_op2(ctx, ALU_OP2_AND_INT,
11269 treg, 1,
11270 treg, 1,
11271 sub_tmp, 0);
11272 if (r)
11273 return r;
11274
11275 memset(&alu_src, 0, sizeof(alu_src));
11276 alu_src.sel = treg;
11277 alu_src.chan = 1;
11278 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
11279 if (r)
11280 return r;
11281
11282
11283 r = emit_u64add(ctx, ALU_OP2_SUB_INT,
11284 sub_tmp,
11285 tmp_num, 0,
11286 treg, 2);
11287 if (r)
11288 return r;
11289
11290 r = single_alu_op2(ctx, ALU_OP1_MOV,
11291 tmp_num, 0,
11292 sub_tmp, 0,
11293 0, 0);
11294 if (r)
11295 return r;
11296
11297 r = single_alu_op2(ctx, ALU_OP1_MOV,
11298 tmp_num, 1,
11299 sub_tmp, 1,
11300 0, 0);
11301 if (r)
11302 return r;
11303
11304 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
11305 tmp_num, 2,
11306 tmp_num, 2,
11307 V_SQ_ALU_SRC_LITERAL, 1U << (31 - i));
11308 if (r)
11309 return r;
11310
11311 r = tgsi_endif(ctx);
11312 if (r)
11313 return r;
11314 }
11315
11316 /* log2_denom is always <= 63, so manually peel the last loop
11317 * iteration.
11318 */
11319 uint64_t denom_shl = (uint64_t)alu_denom_lo.value;
11320 r = single_alu_op2(ctx, ALU_OP1_MOV,
11321 treg, 2,
11322 V_SQ_ALU_SRC_LITERAL, (denom_shl & 0xffffffff),
11323 0, 0);
11324 if (r)
11325 return r;
11326
11327 r = single_alu_op2(ctx, ALU_OP1_MOV,
11328 treg, 3,
11329 V_SQ_ALU_SRC_LITERAL, (denom_shl >> 32),
11330 0, 0);
11331 if (r)
11332 return r;
11333
11334 r = emit_u64sge(ctx, sub_tmp,
11335 tmp_num, 0,
11336 treg, 2);
11337 if (r)
11338 return r;
11339
11340 memset(&alu_src, 0, sizeof(alu_src));
11341 alu_src.sel = sub_tmp;
11342 alu_src.chan = 0;
11343 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
11344 if (r)
11345 return r;
11346
11347 r = emit_u64add(ctx, ALU_OP2_SUB_INT,
11348 sub_tmp,
11349 tmp_num, 0,
11350 treg, 2);
11351 if (r)
11352 return r;
11353
11354 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
11355 tmp_num, 2,
11356 tmp_num, 2,
11357 V_SQ_ALU_SRC_LITERAL, 1U);
11358 if (r)
11359 return r;
11360 r = tgsi_endif(ctx);
11361 if (r)
11362 return r;
11363
11364 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11365 alu.op = ALU_OP1_MOV;
11366 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
11367 alu.src[0].sel = tmp_num;
11368 alu.src[0].chan = 2;
11369 r = r600_bytecode_add_alu(ctx->bc, &alu);
11370 if (r)
11371 return r;
11372
11373 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11374 alu.op = ALU_OP1_MOV;
11375 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
11376 alu.src[0].sel = tmp_num;
11377 alu.src[0].chan = 3;
11378 alu.last = 1;
11379 r = r600_bytecode_add_alu(ctx->bc, &alu);
11380 if (r)
11381 return r;
11382 return 0;
11383 }
11384
11385 static int egcm_u64sne(struct r600_shader_ctx *ctx)
11386 {
11387 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
11388 struct r600_bytecode_alu alu;
11389 int r;
11390 int treg = ctx->temp_reg;
11391
11392 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11393 alu.op = ALU_OP2_SETNE_INT;
11394 alu.dst.sel = treg;
11395 alu.dst.chan = 0;
11396 alu.dst.write = 1;
11397 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
11398 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
11399 r = r600_bytecode_add_alu(ctx->bc, &alu);
11400 if (r)
11401 return r;
11402
11403 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11404 alu.op = ALU_OP2_SETNE_INT;
11405 alu.dst.sel = treg;
11406 alu.dst.chan = 1;
11407 alu.dst.write = 1;
11408 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
11409 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
11410 alu.last = 1;
11411 r = r600_bytecode_add_alu(ctx->bc, &alu);
11412 if (r)
11413 return r;
11414
11415 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11416 alu.op = ALU_OP2_OR_INT;
11417 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
11418 alu.src[0].sel = treg;
11419 alu.src[0].chan = 0;
11420 alu.src[1].sel = treg;
11421 alu.src[1].chan = 1;
11422 alu.last = 1;
11423 r = r600_bytecode_add_alu(ctx->bc, &alu);
11424 if (r)
11425 return r;
11426 return 0;
11427 }
11428
11429 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
11430 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
11431 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
11432 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
11433
11434 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
11435
11436 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
11437 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
11438 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
11439 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
11440 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
11441 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11442 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11443 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
11444 /* MIN_DX10 returns non-nan result if one src is NaN, MIN returns NaN */
11445 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
11446 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
11447 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
11448 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
11449 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
11450 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
11451 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
11452 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
11453 [21] = { ALU_OP0_NOP, tgsi_unsupported},
11454 [22] = { ALU_OP0_NOP, tgsi_unsupported},
11455 [23] = { ALU_OP0_NOP, tgsi_unsupported},
11456 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
11457 [25] = { ALU_OP0_NOP, tgsi_unsupported},
11458 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
11459 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
11460 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
11461 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
11462 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
11463 [31] = { ALU_OP0_NOP, tgsi_unsupported},
11464 [32] = { ALU_OP0_NOP, tgsi_unsupported},
11465 [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_unsupported},
11466 [34] = { ALU_OP0_NOP, tgsi_unsupported},
11467 [35] = { ALU_OP0_NOP, tgsi_unsupported},
11468 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
11469 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11470 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11471 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
11472 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
11473 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
11474 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
11475 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11476 [44] = { ALU_OP0_NOP, tgsi_unsupported},
11477 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
11478 [46] = { ALU_OP0_NOP, tgsi_unsupported},
11479 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
11480 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
11481 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
11482 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
11483 [51] = { ALU_OP0_NOP, tgsi_unsupported},
11484 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
11485 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
11486 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
11487 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
11488 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
11489 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
11490 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11491 [59] = { ALU_OP0_NOP, tgsi_unsupported},
11492 [60] = { ALU_OP0_NOP, tgsi_unsupported},
11493 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
11494 [62] = { ALU_OP0_NOP, tgsi_unsupported},
11495 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
11496 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
11497 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
11498 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
11499 [67] = { ALU_OP0_NOP, tgsi_unsupported},
11500 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11501 [69] = { ALU_OP0_NOP, tgsi_unsupported},
11502 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
11503 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11504 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11505 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
11506 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
11507 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
11508 [76] = { ALU_OP0_NOP, tgsi_unsupported},
11509 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
11510 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
11511 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
11512 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
11513 [81] = { ALU_OP0_NOP, tgsi_unsupported},
11514 [82] = { ALU_OP0_NOP, tgsi_unsupported},
11515 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
11516 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
11517 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
11518 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
11519 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
11520 [88] = { ALU_OP0_NOP, tgsi_unsupported},
11521 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
11522 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
11523 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
11524 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
11525 [93] = { ALU_OP0_NOP, tgsi_unsupported},
11526 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
11527 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11528 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
11529 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
11530 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
11531 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
11532 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11533 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
11534 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11535 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11536 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
11537 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
11538 [106] = { ALU_OP0_NOP, tgsi_unsupported},
11539 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
11540 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
11541 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
11542 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
11543 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
11544 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
11545 [113] = { ALU_OP0_NOP, tgsi_unsupported},
11546 [114] = { ALU_OP0_NOP, tgsi_unsupported},
11547 [115] = { ALU_OP0_NOP, tgsi_unsupported},
11548 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
11549 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
11550 [TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
11551 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
11552 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
11553 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
11554 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
11555 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
11556 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
11557 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
11558 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
11559 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
11560 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
11561 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
11562 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
11563 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
11564 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
11565 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
11566 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
11567 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
11568 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
11569 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
11570 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
11571 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
11572 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
11573 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11574 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
11575 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
11576 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11577 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
11578 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
11579 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
11580 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
11581 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
11582 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
11583 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
11584 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
11585 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
11586 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
11587 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
11588 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
11589 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
11590 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
11591 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
11592 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
11593 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
11594 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
11595 [163] = { ALU_OP0_NOP, tgsi_unsupported},
11596 [164] = { ALU_OP0_NOP, tgsi_unsupported},
11597 [165] = { ALU_OP0_NOP, tgsi_unsupported},
11598 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
11599 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
11600 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
11601 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
11602 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
11603 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
11604 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
11605 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
11606 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
11607 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
11608 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
11609 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
11610 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11611 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11612 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
11613 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
11614 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
11615 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
11616 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
11617 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
11618 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
11619 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
11620 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
11621 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
11622 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
11623 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
11624 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
11625 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
11626 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
11627 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
11628 };
11629
11630 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
11631 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
11632 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
11633 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
11634 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
11635 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
11636 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
11637 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
11638 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
11639 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
11640 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11641 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11642 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
11643 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
11644 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
11645 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
11646 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
11647 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
11648 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
11649 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
11650 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
11651 [21] = { ALU_OP0_NOP, tgsi_unsupported},
11652 [22] = { ALU_OP0_NOP, tgsi_unsupported},
11653 [23] = { ALU_OP0_NOP, tgsi_unsupported},
11654 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
11655 [25] = { ALU_OP0_NOP, tgsi_unsupported},
11656 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
11657 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
11658 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
11659 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
11660 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
11661 [31] = { ALU_OP0_NOP, tgsi_unsupported},
11662 [32] = { ALU_OP0_NOP, tgsi_unsupported},
11663 [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_clock},
11664 [34] = { ALU_OP0_NOP, tgsi_unsupported},
11665 [35] = { ALU_OP0_NOP, tgsi_unsupported},
11666 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
11667 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11668 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11669 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
11670 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
11671 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
11672 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
11673 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11674 [44] = { ALU_OP0_NOP, tgsi_unsupported},
11675 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
11676 [46] = { ALU_OP0_NOP, tgsi_unsupported},
11677 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
11678 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
11679 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
11680 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
11681 [51] = { ALU_OP0_NOP, tgsi_unsupported},
11682 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
11683 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
11684 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
11685 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
11686 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
11687 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
11688 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11689 [59] = { ALU_OP0_NOP, tgsi_unsupported},
11690 [60] = { ALU_OP0_NOP, tgsi_unsupported},
11691 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
11692 [62] = { ALU_OP0_NOP, tgsi_unsupported},
11693 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
11694 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
11695 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
11696 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
11697 [67] = { ALU_OP0_NOP, tgsi_unsupported},
11698 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11699 [69] = { ALU_OP0_NOP, tgsi_unsupported},
11700 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
11701 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11702 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11703 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
11704 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
11705 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
11706 [76] = { ALU_OP0_NOP, tgsi_unsupported},
11707 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
11708 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
11709 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11710 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11711 [82] = { ALU_OP0_NOP, tgsi_unsupported},
11712 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
11713 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
11714 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
11715 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
11716 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
11717 [88] = { ALU_OP0_NOP, tgsi_unsupported},
11718 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
11719 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
11720 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
11721 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
11722 [93] = { ALU_OP0_NOP, tgsi_unsupported},
11723 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
11724 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11725 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
11726 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
11727 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
11728 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
11729 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11730 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
11731 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11732 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11733 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
11734 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
11735 [106] = { ALU_OP0_NOP, tgsi_unsupported},
11736 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
11737 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
11738 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
11739 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
11740 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
11741 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
11742 [113] = { ALU_OP0_NOP, tgsi_unsupported},
11743 [114] = { ALU_OP0_NOP, tgsi_unsupported},
11744 [115] = { ALU_OP0_NOP, tgsi_unsupported},
11745 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
11746 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
11747 /* Refer below for TGSI_OPCODE_DFMA */
11748 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
11749 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
11750 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
11751 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
11752 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
11753 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
11754 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
11755 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
11756 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
11757 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
11758 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
11759 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
11760 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
11761 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
11762 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
11763 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
11764 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
11765 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
11766 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
11767 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
11768 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
11769 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
11770 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11771 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
11772 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
11773 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11774 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
11775 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
11776 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
11777 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
11778 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
11779 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
11780 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
11781 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
11782 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
11783 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
11784 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
11785 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
11786 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
11787 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
11788 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
11789 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
11790 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
11791 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
11792 [163] = { ALU_OP0_NOP, tgsi_unsupported},
11793 [164] = { ALU_OP0_NOP, tgsi_unsupported},
11794 [165] = { ALU_OP0_NOP, tgsi_unsupported},
11795 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
11796 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
11797 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
11798 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
11799 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
11800 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
11801 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
11802 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
11803 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
11804 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
11805 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
11806 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
11807 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11808 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11809 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
11810 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
11811 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
11812 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
11813 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
11814 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
11815 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
11816 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
11817 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
11818 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
11819 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
11820 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
11821 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
11822 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
11823 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
11824 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
11825 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
11826 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
11827 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
11828 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
11829 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
11830 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
11831 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
11832 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
11833 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
11834 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
11835 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
11836 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
11837 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
11838 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
11839 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
11840 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
11841 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
11842 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
11843 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
11844 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
11845 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
11846 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
11847 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
11848 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
11849 [TGSI_OPCODE_U64SNE] = { ALU_OP0_NOP, egcm_u64sne },
11850 [TGSI_OPCODE_U64ADD] = { ALU_OP0_NOP, egcm_u64add },
11851 [TGSI_OPCODE_U64MUL] = { ALU_OP0_NOP, egcm_u64mul },
11852 [TGSI_OPCODE_U64DIV] = { ALU_OP0_NOP, egcm_u64div },
11853 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
11854 };
11855
11856 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
11857 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
11858 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
11859 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
11860 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
11861 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
11862 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
11863 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
11864 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
11865 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
11866 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11867 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11868 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
11869 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
11870 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
11871 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
11872 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
11873 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
11874 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
11875 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
11876 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
11877 [21] = { ALU_OP0_NOP, tgsi_unsupported},
11878 [22] = { ALU_OP0_NOP, tgsi_unsupported},
11879 [23] = { ALU_OP0_NOP, tgsi_unsupported},
11880 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
11881 [25] = { ALU_OP0_NOP, tgsi_unsupported},
11882 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
11883 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
11884 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
11885 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
11886 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
11887 [31] = { ALU_OP0_NOP, tgsi_unsupported},
11888 [32] = { ALU_OP0_NOP, tgsi_unsupported},
11889 [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_clock},
11890 [34] = { ALU_OP0_NOP, tgsi_unsupported},
11891 [35] = { ALU_OP0_NOP, tgsi_unsupported},
11892 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
11893 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11894 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11895 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
11896 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
11897 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
11898 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
11899 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11900 [44] = { ALU_OP0_NOP, tgsi_unsupported},
11901 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
11902 [46] = { ALU_OP0_NOP, tgsi_unsupported},
11903 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
11904 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
11905 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
11906 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
11907 [51] = { ALU_OP0_NOP, tgsi_unsupported},
11908 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
11909 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
11910 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
11911 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
11912 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
11913 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
11914 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11915 [59] = { ALU_OP0_NOP, tgsi_unsupported},
11916 [60] = { ALU_OP0_NOP, tgsi_unsupported},
11917 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
11918 [62] = { ALU_OP0_NOP, tgsi_unsupported},
11919 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
11920 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
11921 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
11922 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
11923 [67] = { ALU_OP0_NOP, tgsi_unsupported},
11924 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11925 [69] = { ALU_OP0_NOP, tgsi_unsupported},
11926 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
11927 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11928 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11929 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
11930 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
11931 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
11932 [76] = { ALU_OP0_NOP, tgsi_unsupported},
11933 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
11934 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
11935 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11936 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11937 [82] = { ALU_OP0_NOP, tgsi_unsupported},
11938 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
11939 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
11940 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
11941 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
11942 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
11943 [88] = { ALU_OP0_NOP, tgsi_unsupported},
11944 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
11945 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
11946 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
11947 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
11948 [93] = { ALU_OP0_NOP, tgsi_unsupported},
11949 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
11950 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11951 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
11952 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
11953 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
11954 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
11955 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11956 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
11957 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11958 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11959 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
11960 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
11961 [106] = { ALU_OP0_NOP, tgsi_unsupported},
11962 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
11963 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
11964 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
11965 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
11966 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
11967 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
11968 [113] = { ALU_OP0_NOP, tgsi_unsupported},
11969 [114] = { ALU_OP0_NOP, tgsi_unsupported},
11970 [115] = { ALU_OP0_NOP, tgsi_unsupported},
11971 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
11972 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
11973 /* Refer below for TGSI_OPCODE_DFMA */
11974 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
11975 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
11976 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
11977 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
11978 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
11979 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
11980 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
11981 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
11982 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
11983 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
11984 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
11985 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
11986 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
11987 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
11988 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
11989 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
11990 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
11991 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
11992 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
11993 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
11994 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
11995 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
11996 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11997 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
11998 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
11999 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
12000 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
12001 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
12002 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
12003 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
12004 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
12005 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
12006 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
12007 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
12008 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
12009 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
12010 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
12011 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
12012 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
12013 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
12014 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
12015 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
12016 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
12017 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
12018 [163] = { ALU_OP0_NOP, tgsi_unsupported},
12019 [164] = { ALU_OP0_NOP, tgsi_unsupported},
12020 [165] = { ALU_OP0_NOP, tgsi_unsupported},
12021 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
12022 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
12023 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
12024 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
12025 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
12026 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
12027 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
12028 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
12029 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
12030 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
12031 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
12032 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
12033 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
12034 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
12035 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
12036 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
12037 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
12038 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
12039 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
12040 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
12041 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
12042 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
12043 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
12044 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
12045 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
12046 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
12047 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
12048 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
12049 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
12050 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
12051 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
12052 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
12053 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
12054 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
12055 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
12056 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
12057 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
12058 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
12059 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
12060 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
12061 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
12062 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
12063 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
12064 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
12065 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
12066 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
12067 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
12068 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
12069 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
12070 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
12071 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
12072 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
12073 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
12074 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
12075 [TGSI_OPCODE_U64SNE] = { ALU_OP0_NOP, egcm_u64sne },
12076 [TGSI_OPCODE_U64ADD] = { ALU_OP0_NOP, egcm_u64add },
12077 [TGSI_OPCODE_U64MUL] = { ALU_OP0_NOP, egcm_u64mul },
12078 [TGSI_OPCODE_U64DIV] = { ALU_OP0_NOP, egcm_u64div },
12079 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
12080 };