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r600g: use the values from the correct literals
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_screen.h"
29 #include "r600_context.h"
30 #include "r600_shader.h"
31 #include "r600_asm.h"
32 #include "r600_sq.h"
33 #include "r600d.h"
34 #include <stdio.h>
35 #include <errno.h>
36
37
38 struct r600_shader_tgsi_instruction;
39
40 struct r600_shader_ctx {
41 struct tgsi_shader_info info;
42 struct tgsi_parse_context parse;
43 const struct tgsi_token *tokens;
44 unsigned type;
45 unsigned file_offset[TGSI_FILE_COUNT];
46 unsigned temp_reg;
47 struct r600_shader_tgsi_instruction *inst_info;
48 struct r600_bc *bc;
49 struct r600_shader *shader;
50 u32 value[4];
51 u32 *literals;
52 u32 nliterals;
53 };
54
55 struct r600_shader_tgsi_instruction {
56 unsigned tgsi_opcode;
57 unsigned is_op3;
58 unsigned r600_opcode;
59 int (*process)(struct r600_shader_ctx *ctx);
60 };
61
62 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[];
63 static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
64
65 static int r600_shader_update(struct pipe_context *ctx, struct r600_shader *shader)
66 {
67 struct r600_context *rctx = r600_context(ctx);
68 const struct util_format_description *desc;
69 enum pipe_format resource_format[160];
70 unsigned i, nresources = 0;
71 struct r600_bc *bc = &shader->bc;
72 struct r600_bc_cf *cf;
73 struct r600_bc_vtx *vtx;
74
75 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
76 return 0;
77 for (i = 0; i < rctx->vertex_elements->count; i++) {
78 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
79 }
80 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
81 switch (cf->inst) {
82 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
83 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
84 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
85 desc = util_format_description(resource_format[vtx->buffer_id]);
86 if (desc == NULL) {
87 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
88 return -EINVAL;
89 }
90 vtx->dst_sel_x = desc->swizzle[0];
91 vtx->dst_sel_y = desc->swizzle[1];
92 vtx->dst_sel_z = desc->swizzle[2];
93 vtx->dst_sel_w = desc->swizzle[3];
94 }
95 break;
96 default:
97 break;
98 }
99 }
100 return r600_bc_build(&shader->bc);
101 }
102
103 int r600_pipe_shader_create(struct pipe_context *ctx,
104 struct r600_context_state *rpshader,
105 const struct tgsi_token *tokens)
106 {
107 struct r600_screen *rscreen = r600_screen(ctx->screen);
108 int r;
109
110 //fprintf(stderr, "--------------------------------------------------------------\n");
111 //tgsi_dump(tokens, 0);
112 if (rpshader == NULL)
113 return -ENOMEM;
114 rpshader->shader.family = radeon_get_family(rscreen->rw);
115 r = r600_shader_from_tgsi(tokens, &rpshader->shader);
116 if (r) {
117 R600_ERR("translation from TGSI failed !\n");
118 return r;
119 }
120 r = r600_bc_build(&rpshader->shader.bc);
121 if (r) {
122 R600_ERR("building bytecode failed !\n");
123 return r;
124 }
125 //fprintf(stderr, "______________________________________________________________\n");
126 return 0;
127 }
128
129 static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_state *rpshader)
130 {
131 struct r600_screen *rscreen = r600_screen(ctx->screen);
132 struct r600_shader *rshader = &rpshader->shader;
133 struct radeon_state *state;
134 unsigned i, tmp;
135
136 rpshader->rstate = radeon_state_decref(rpshader->rstate);
137 state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
138 if (state == NULL)
139 return -ENOMEM;
140 for (i = 0; i < 10; i++) {
141 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
142 }
143 /* so far never got proper semantic id from tgsi */
144 for (i = 0; i < 32; i++) {
145 tmp = i << ((i & 3) * 8);
146 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp;
147 }
148 state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
149 state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
150 S_028868_STACK_SIZE(rshader->bc.nstack);
151 rpshader->rstate = state;
152 rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
153 rpshader->rstate->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
154 rpshader->rstate->nbo = 2;
155 rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
156 rpshader->rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
157 return radeon_state_pm4(state);
158 }
159
160 static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_state *rpshader)
161 {
162 const struct pipe_rasterizer_state *rasterizer;
163 struct r600_screen *rscreen = r600_screen(ctx->screen);
164 struct r600_shader *rshader = &rpshader->shader;
165 struct r600_context *rctx = r600_context(ctx);
166 struct radeon_state *state;
167 unsigned i, tmp, exports_ps, num_cout;
168
169 rasterizer = &rctx->rasterizer->state.rasterizer;
170 rpshader->rstate = radeon_state_decref(rpshader->rstate);
171 state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
172 if (state == NULL)
173 return -ENOMEM;
174 for (i = 0; i < rshader->ninput; i++) {
175 tmp = S_028644_SEMANTIC(i);
176 tmp |= S_028644_SEL_CENTROID(1);
177 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
178 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR) {
179 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
180 }
181 if (rasterizer->sprite_coord_enable & (1 << i)) {
182 tmp |= S_028644_PT_SPRITE_TEX(1);
183 }
184 state->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
185 }
186
187 exports_ps = 0;
188 num_cout = 0;
189 for (i = 0; i < rshader->noutput; i++) {
190 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
191 exports_ps |= 1;
192 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
193 exports_ps |= (1 << (num_cout+1));
194 num_cout++;
195 }
196 }
197 if (!exports_ps) {
198 /* always at least export 1 component per pixel */
199 exports_ps = 2;
200 }
201 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
202 S_0286CC_PERSP_GRADIENT_ENA(1);
203 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
204 state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
205 S_028868_STACK_SIZE(rshader->bc.nstack);
206 state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
207 rpshader->rstate = state;
208 rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
209 rpshader->rstate->nbo = 1;
210 rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
211 return radeon_state_pm4(state);
212 }
213
214 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_context_state *rpshader)
215 {
216 struct r600_screen *rscreen = r600_screen(ctx->screen);
217 struct r600_context *rctx = r600_context(ctx);
218 struct r600_shader *rshader = &rpshader->shader;
219 int r;
220
221 /* copy new shader */
222 radeon_bo_decref(rscreen->rw, rpshader->bo);
223 rpshader->bo = NULL;
224 rpshader->bo = radeon_bo(rscreen->rw, 0, rshader->bc.ndw * 4,
225 4096, NULL);
226 if (rpshader->bo == NULL) {
227 return -ENOMEM;
228 }
229 radeon_bo_map(rscreen->rw, rpshader->bo);
230 memcpy(rpshader->bo->data, rshader->bc.bytecode, rshader->bc.ndw * 4);
231 radeon_bo_unmap(rscreen->rw, rpshader->bo);
232 /* build state */
233 rshader->flat_shade = rctx->flat_shade;
234 switch (rshader->processor_type) {
235 case TGSI_PROCESSOR_VERTEX:
236 r = r600_pipe_shader_vs(ctx, rpshader);
237 break;
238 case TGSI_PROCESSOR_FRAGMENT:
239 r = r600_pipe_shader_ps(ctx, rpshader);
240 break;
241 default:
242 r = -EINVAL;
243 break;
244 }
245 return r;
246 }
247
248 int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_context_state *rpshader)
249 {
250 struct r600_context *rctx = r600_context(ctx);
251 int r;
252
253 if (rpshader == NULL)
254 return -EINVAL;
255 /* there should be enough input */
256 if (rctx->vertex_elements->count < rpshader->shader.bc.nresource) {
257 R600_ERR("%d resources provided, expecting %d\n",
258 rctx->vertex_elements->count, rpshader->shader.bc.nresource);
259 return -EINVAL;
260 }
261 r = r600_shader_update(ctx, &rpshader->shader);
262 if (r)
263 return r;
264 return r600_pipe_shader(ctx, rpshader);
265 }
266
267 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
268 {
269 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
270 int j;
271
272 if (i->Instruction.NumDstRegs > 1) {
273 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
274 return -EINVAL;
275 }
276 if (i->Instruction.Predicate) {
277 R600_ERR("predicate unsupported\n");
278 return -EINVAL;
279 }
280 #if 0
281 if (i->Instruction.Label) {
282 R600_ERR("label unsupported\n");
283 return -EINVAL;
284 }
285 #endif
286 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
287 if (i->Src[j].Register.Indirect ||
288 i->Src[j].Register.Dimension ||
289 i->Src[j].Register.Absolute) {
290 R600_ERR("unsupported src (indirect|dimension|absolute)\n");
291 return -EINVAL;
292 }
293 }
294 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
295 if (i->Dst[j].Register.Indirect || i->Dst[j].Register.Dimension) {
296 R600_ERR("unsupported dst (indirect|dimension)\n");
297 return -EINVAL;
298 }
299 }
300 return 0;
301 }
302
303 static int tgsi_declaration(struct r600_shader_ctx *ctx)
304 {
305 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
306 struct r600_bc_vtx vtx;
307 unsigned i;
308 int r;
309
310 switch (d->Declaration.File) {
311 case TGSI_FILE_INPUT:
312 i = ctx->shader->ninput++;
313 ctx->shader->input[i].name = d->Semantic.Name;
314 ctx->shader->input[i].sid = d->Semantic.Index;
315 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
316 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
317 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
318 /* turn input into fetch */
319 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
320 vtx.inst = 0;
321 vtx.fetch_type = 0;
322 vtx.buffer_id = i;
323 /* register containing the index into the buffer */
324 vtx.src_gpr = 0;
325 vtx.src_sel_x = 0;
326 vtx.mega_fetch_count = 0x1F;
327 vtx.dst_gpr = ctx->shader->input[i].gpr;
328 vtx.dst_sel_x = 0;
329 vtx.dst_sel_y = 1;
330 vtx.dst_sel_z = 2;
331 vtx.dst_sel_w = 3;
332 r = r600_bc_add_vtx(ctx->bc, &vtx);
333 if (r)
334 return r;
335 }
336 break;
337 case TGSI_FILE_OUTPUT:
338 i = ctx->shader->noutput++;
339 ctx->shader->output[i].name = d->Semantic.Name;
340 ctx->shader->output[i].sid = d->Semantic.Index;
341 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
342 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
343 break;
344 case TGSI_FILE_CONSTANT:
345 case TGSI_FILE_TEMPORARY:
346 case TGSI_FILE_SAMPLER:
347 break;
348 default:
349 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
350 return -EINVAL;
351 }
352 return 0;
353 }
354
355 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
356 {
357 struct tgsi_full_immediate *immediate;
358 struct r600_shader_ctx ctx;
359 struct r600_bc_output output[32];
360 unsigned output_done, noutput;
361 unsigned opcode;
362 int i, r = 0, pos0;
363
364 ctx.bc = &shader->bc;
365 ctx.shader = shader;
366 r = r600_bc_init(ctx.bc, shader->family);
367 if (r)
368 return r;
369 ctx.tokens = tokens;
370 tgsi_scan_shader(tokens, &ctx.info);
371 tgsi_parse_init(&ctx.parse, tokens);
372 ctx.type = ctx.parse.FullHeader.Processor.Processor;
373 shader->processor_type = ctx.type;
374
375 /* register allocations */
376 /* Values [0,127] correspond to GPR[0..127].
377 * Values [128,159] correspond to constant buffer bank 0
378 * Values [160,191] correspond to constant buffer bank 1
379 * Values [256,511] correspond to cfile constants c[0..255].
380 * Other special values are shown in the list below.
381 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
382 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
383 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
384 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
385 * 248 SQ_ALU_SRC_0: special constant 0.0.
386 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
387 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
388 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
389 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
390 * 253 SQ_ALU_SRC_LITERAL: literal constant.
391 * 254 SQ_ALU_SRC_PV: previous vector result.
392 * 255 SQ_ALU_SRC_PS: previous scalar result.
393 */
394 for (i = 0; i < TGSI_FILE_COUNT; i++) {
395 ctx.file_offset[i] = 0;
396 }
397 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
398 ctx.file_offset[TGSI_FILE_INPUT] = 1;
399 }
400 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
401 ctx.info.file_count[TGSI_FILE_INPUT];
402 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
403 ctx.info.file_count[TGSI_FILE_OUTPUT];
404 ctx.file_offset[TGSI_FILE_CONSTANT] = 256;
405 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
406 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
407 ctx.info.file_count[TGSI_FILE_TEMPORARY];
408
409 ctx.nliterals = 0;
410 ctx.literals = NULL;
411
412 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
413 tgsi_parse_token(&ctx.parse);
414 switch (ctx.parse.FullToken.Token.Type) {
415 case TGSI_TOKEN_TYPE_IMMEDIATE:
416 immediate = &ctx.parse.FullToken.FullImmediate;
417 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
418 if(ctx.literals == NULL) {
419 r = -ENOMEM;
420 goto out_err;
421 }
422 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
423 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
424 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
425 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
426 ctx.nliterals++;
427 break;
428 case TGSI_TOKEN_TYPE_DECLARATION:
429 r = tgsi_declaration(&ctx);
430 if (r)
431 goto out_err;
432 break;
433 case TGSI_TOKEN_TYPE_INSTRUCTION:
434 r = tgsi_is_supported(&ctx);
435 if (r)
436 goto out_err;
437 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
438 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
439 r = ctx.inst_info->process(&ctx);
440 if (r)
441 goto out_err;
442 r = r600_bc_add_literal(ctx.bc, ctx.value);
443 if (r)
444 goto out_err;
445 break;
446 default:
447 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
448 r = -EINVAL;
449 goto out_err;
450 }
451 }
452 /* export output */
453 noutput = shader->noutput;
454 for (i = 0, pos0 = 0; i < noutput; i++) {
455 memset(&output[i], 0, sizeof(struct r600_bc_output));
456 output[i].gpr = shader->output[i].gpr;
457 output[i].elem_size = 3;
458 output[i].swizzle_x = 0;
459 output[i].swizzle_y = 1;
460 output[i].swizzle_z = 2;
461 output[i].swizzle_w = 3;
462 output[i].barrier = 1;
463 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
464 output[i].array_base = i - pos0;
465 output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
466 switch (ctx.type) {
467 case TGSI_PROCESSOR_VERTEX:
468 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
469 output[i].array_base = 60;
470 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
471 /* position doesn't count in array_base */
472 pos0++;
473 }
474 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
475 output[i].array_base = 61;
476 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
477 /* position doesn't count in array_base */
478 pos0++;
479 }
480 break;
481 case TGSI_PROCESSOR_FRAGMENT:
482 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
483 output[i].array_base = shader->output[i].sid;
484 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
485 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
486 output[i].array_base = 61;
487 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
488 } else {
489 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
490 r = -EINVAL;
491 goto out_err;
492 }
493 break;
494 default:
495 R600_ERR("unsupported processor type %d\n", ctx.type);
496 r = -EINVAL;
497 goto out_err;
498 }
499 }
500 /* add fake param output for vertex shader if no param is exported */
501 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
502 for (i = 0, pos0 = 0; i < noutput; i++) {
503 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
504 pos0 = 1;
505 break;
506 }
507 }
508 if (!pos0) {
509 memset(&output[i], 0, sizeof(struct r600_bc_output));
510 output[i].gpr = 0;
511 output[i].elem_size = 3;
512 output[i].swizzle_x = 0;
513 output[i].swizzle_y = 1;
514 output[i].swizzle_z = 2;
515 output[i].swizzle_w = 3;
516 output[i].barrier = 1;
517 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
518 output[i].array_base = 0;
519 output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
520 noutput++;
521 }
522 }
523 /* add fake pixel export */
524 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
525 memset(&output[0], 0, sizeof(struct r600_bc_output));
526 output[0].gpr = 0;
527 output[0].elem_size = 3;
528 output[0].swizzle_x = 7;
529 output[0].swizzle_y = 7;
530 output[0].swizzle_z = 7;
531 output[0].swizzle_w = 7;
532 output[0].barrier = 1;
533 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
534 output[0].array_base = 0;
535 output[0].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
536 noutput++;
537 }
538 /* set export done on last export of each type */
539 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
540 if (i == (noutput - 1)) {
541 output[i].end_of_program = 1;
542 }
543 if (!(output_done & (1 << output[i].type))) {
544 output_done |= (1 << output[i].type);
545 output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE;
546 }
547 }
548 /* add output to bytecode */
549 for (i = 0; i < noutput; i++) {
550 r = r600_bc_add_output(ctx.bc, &output[i]);
551 if (r)
552 goto out_err;
553 }
554 free(ctx.literals);
555 tgsi_parse_free(&ctx.parse);
556 return 0;
557 out_err:
558 free(ctx.literals);
559 tgsi_parse_free(&ctx.parse);
560 return r;
561 }
562
563 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
564 {
565 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
566 return -EINVAL;
567 }
568
569 static int tgsi_end(struct r600_shader_ctx *ctx)
570 {
571 return 0;
572 }
573
574 static int tgsi_src(struct r600_shader_ctx *ctx,
575 const struct tgsi_full_src_register *tgsi_src,
576 struct r600_bc_alu_src *r600_src)
577 {
578 int index;
579 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
580 r600_src->sel = tgsi_src->Register.Index;
581 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
582 r600_src->sel = 0;
583 index = tgsi_src->Register.Index;
584 ctx->value[0] = ctx->literals[index * 4 + 0];
585 ctx->value[1] = ctx->literals[index * 4 + 1];
586 ctx->value[2] = ctx->literals[index * 4 + 2];
587 ctx->value[3] = ctx->literals[index * 4 + 3];
588 }
589 r600_src->neg = tgsi_src->Register.Negate;
590 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
591 return 0;
592 }
593
594 static int tgsi_dst(struct r600_shader_ctx *ctx,
595 const struct tgsi_full_dst_register *tgsi_dst,
596 unsigned swizzle,
597 struct r600_bc_alu_dst *r600_dst)
598 {
599 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
600
601 r600_dst->sel = tgsi_dst->Register.Index;
602 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
603 r600_dst->chan = swizzle;
604 r600_dst->write = 1;
605 if (inst->Instruction.Saturate) {
606 r600_dst->clamp = 1;
607 }
608 return 0;
609 }
610
611 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
612 {
613 switch (swizzle) {
614 case 0:
615 return tgsi_src->Register.SwizzleX;
616 case 1:
617 return tgsi_src->Register.SwizzleY;
618 case 2:
619 return tgsi_src->Register.SwizzleZ;
620 case 3:
621 return tgsi_src->Register.SwizzleW;
622 default:
623 return 0;
624 }
625 }
626
627 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
628 {
629 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
630 struct r600_bc_alu alu;
631 int i, j, k, nconst, r;
632
633 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
634 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
635 nconst++;
636 }
637 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
638 if (r) {
639 return r;
640 }
641 }
642 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
643 if (inst->Src[j].Register.File == TGSI_FILE_CONSTANT && j > 0) {
644 for (k = 0; k < 4; k++) {
645 memset(&alu, 0, sizeof(struct r600_bc_alu));
646 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
647 alu.src[0].sel = r600_src[0].sel;
648 alu.src[0].chan = k;
649 alu.dst.sel = ctx->temp_reg + j;
650 alu.dst.chan = k;
651 alu.dst.write = 1;
652 if (k == 3)
653 alu.last = 1;
654 r = r600_bc_add_alu(ctx->bc, &alu);
655 if (r)
656 return r;
657 }
658 r600_src[0].sel = ctx->temp_reg + j;
659 j--;
660 }
661 }
662 return 0;
663 }
664
665 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
666 {
667 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
668 struct r600_bc_alu_src r600_src[3];
669 struct r600_bc_alu alu;
670 int i, j, r;
671 int lasti = 0;
672
673 for (i = 0; i < 4; i++) {
674 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
675 lasti = i;
676 }
677 }
678
679 r = tgsi_split_constant(ctx, r600_src);
680 if (r)
681 return r;
682 for (i = 0; i < lasti + 1; i++) {
683 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
684 continue;
685
686 memset(&alu, 0, sizeof(struct r600_bc_alu));
687 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
688 if (r)
689 return r;
690
691 alu.inst = ctx->inst_info->r600_opcode;
692 if (!swap) {
693 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
694 alu.src[j] = r600_src[j];
695 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
696 }
697 } else {
698 alu.src[0] = r600_src[1];
699 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
700
701 alu.src[1] = r600_src[0];
702 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
703 }
704 /* handle some special cases */
705 switch (ctx->inst_info->tgsi_opcode) {
706 case TGSI_OPCODE_SUB:
707 alu.src[1].neg = 1;
708 break;
709 case TGSI_OPCODE_ABS:
710 alu.src[0].abs = 1;
711 break;
712 default:
713 break;
714 }
715 if (i == lasti) {
716 alu.last = 1;
717 }
718 r = r600_bc_add_alu(ctx->bc, &alu);
719 if (r)
720 return r;
721 }
722 return 0;
723 }
724
725 static int tgsi_op2(struct r600_shader_ctx *ctx)
726 {
727 return tgsi_op2_s(ctx, 0);
728 }
729
730 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
731 {
732 return tgsi_op2_s(ctx, 1);
733 }
734
735 /*
736 * r600 - trunc to -PI..PI range
737 * r700 - normalize by dividing by 2PI
738 * see fdo bug 27901
739 */
740 static int tgsi_trig(struct r600_shader_ctx *ctx)
741 {
742 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
743 struct r600_bc_alu_src r600_src[3];
744 struct r600_bc_alu alu;
745 int i, r;
746 uint32_t lit_vals[4];
747
748 memset(lit_vals, 0, 4*4);
749 r = tgsi_split_constant(ctx, r600_src);
750 if (r)
751 return r;
752 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
753 lit_vals[1] = fui(0.5f);
754
755 memset(&alu, 0, sizeof(struct r600_bc_alu));
756 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
757 alu.is_op3 = 1;
758
759 alu.dst.chan = 0;
760 alu.dst.sel = ctx->temp_reg;
761 alu.dst.write = 1;
762
763 alu.src[0] = r600_src[0];
764 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
765
766 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
767 alu.src[1].chan = 0;
768 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
769 alu.src[2].chan = 1;
770 alu.last = 1;
771 r = r600_bc_add_alu(ctx->bc, &alu);
772 if (r)
773 return r;
774 r = r600_bc_add_literal(ctx->bc, lit_vals);
775 if (r)
776 return r;
777
778 memset(&alu, 0, sizeof(struct r600_bc_alu));
779 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT;
780
781 alu.dst.chan = 0;
782 alu.dst.sel = ctx->temp_reg;
783 alu.dst.write = 1;
784
785 alu.src[0].sel = ctx->temp_reg;
786 alu.src[0].chan = 0;
787 alu.last = 1;
788 r = r600_bc_add_alu(ctx->bc, &alu);
789 if (r)
790 return r;
791
792 if (ctx->bc->chiprev == 0) {
793 lit_vals[0] = fui(3.1415926535897f * 2.0f);
794 lit_vals[1] = fui(-3.1415926535897f);
795 } else {
796 lit_vals[0] = fui(1.0f);
797 lit_vals[1] = fui(-0.5f);
798 }
799
800 memset(&alu, 0, sizeof(struct r600_bc_alu));
801 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
802 alu.is_op3 = 1;
803
804 alu.dst.chan = 0;
805 alu.dst.sel = ctx->temp_reg;
806 alu.dst.write = 1;
807
808 alu.src[0].sel = ctx->temp_reg;
809 alu.src[0].chan = 0;
810
811 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
812 alu.src[1].chan = 0;
813 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
814 alu.src[2].chan = 1;
815 alu.last = 1;
816 r = r600_bc_add_alu(ctx->bc, &alu);
817 if (r)
818 return r;
819 r = r600_bc_add_literal(ctx->bc, lit_vals);
820 if (r)
821 return r;
822
823 memset(&alu, 0, sizeof(struct r600_bc_alu));
824 alu.inst = ctx->inst_info->r600_opcode;
825 alu.dst.chan = 0;
826 alu.dst.sel = ctx->temp_reg;
827 alu.dst.write = 1;
828
829 alu.src[0].sel = ctx->temp_reg;
830 alu.src[0].chan = 0;
831 alu.last = 1;
832 r = r600_bc_add_alu(ctx->bc, &alu);
833 if (r)
834 return r;
835
836 /* replicate result */
837 for (i = 0; i < 4; i++) {
838 memset(&alu, 0, sizeof(struct r600_bc_alu));
839 alu.src[0].sel = ctx->temp_reg;
840 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
841 alu.dst.chan = i;
842 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
843 if (r)
844 return r;
845 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
846 if (i == 3)
847 alu.last = 1;
848 r = r600_bc_add_alu(ctx->bc, &alu);
849 if (r)
850 return r;
851 }
852 return 0;
853 }
854
855 static int tgsi_kill(struct r600_shader_ctx *ctx)
856 {
857 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
858 struct r600_bc_alu alu;
859 int i, r;
860
861 for (i = 0; i < 4; i++) {
862 memset(&alu, 0, sizeof(struct r600_bc_alu));
863 alu.inst = ctx->inst_info->r600_opcode;
864 alu.dst.chan = i;
865 alu.src[0].sel = V_SQ_ALU_SRC_0;
866 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
867 if (r)
868 return r;
869 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
870 if (i == 3) {
871 alu.last = 1;
872 }
873 r = r600_bc_add_alu(ctx->bc, &alu);
874 if (r)
875 return r;
876 }
877 return 0;
878 }
879
880 static int tgsi_lit(struct r600_shader_ctx *ctx)
881 {
882 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
883 struct r600_bc_alu alu;
884 int r;
885
886 /* dst.x, <- 1.0 */
887 memset(&alu, 0, sizeof(struct r600_bc_alu));
888 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
889 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
890 alu.src[0].chan = 0;
891 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
892 if (r)
893 return r;
894 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
895 r = r600_bc_add_alu(ctx->bc, &alu);
896 if (r)
897 return r;
898
899 /* dst.y = max(src.x, 0.0) */
900 memset(&alu, 0, sizeof(struct r600_bc_alu));
901 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX;
902 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
903 if (r)
904 return r;
905 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
906 alu.src[1].chan = tgsi_chan(&inst->Src[0], 0);
907 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
908 if (r)
909 return r;
910 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
911 r = r600_bc_add_alu(ctx->bc, &alu);
912 if (r)
913 return r;
914
915 /* dst.z = NOP - fill Z slot */
916 memset(&alu, 0, sizeof(struct r600_bc_alu));
917 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
918 alu.dst.chan = 2;
919 r = r600_bc_add_alu(ctx->bc, &alu);
920 if (r)
921 return r;
922
923 /* dst.w, <- 1.0 */
924 memset(&alu, 0, sizeof(struct r600_bc_alu));
925 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
926 alu.src[0].sel = V_SQ_ALU_SRC_1;
927 alu.src[0].chan = 0;
928 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
929 if (r)
930 return r;
931 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
932 alu.last = 1;
933 r = r600_bc_add_alu(ctx->bc, &alu);
934 if (r)
935 return r;
936
937 if (inst->Dst[0].Register.WriteMask & (1 << 2))
938 {
939 int chan;
940 int sel;
941
942 /* dst.z = log(src.y) */
943 memset(&alu, 0, sizeof(struct r600_bc_alu));
944 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED;
945 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
946 if (r)
947 return r;
948 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
949 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
950 if (r)
951 return r;
952 alu.last = 1;
953 r = r600_bc_add_alu(ctx->bc, &alu);
954 if (r)
955 return r;
956
957 chan = alu.dst.chan;
958 sel = alu.dst.sel;
959
960 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
961 memset(&alu, 0, sizeof(struct r600_bc_alu));
962 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
963 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
964 if (r)
965 return r;
966 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
967 alu.src[1].sel = sel;
968 alu.src[1].chan = chan;
969 r = tgsi_src(ctx, &inst->Src[0], &alu.src[2]);
970 if (r)
971 return r;
972 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
973 alu.dst.sel = ctx->temp_reg;
974 alu.dst.chan = 0;
975 alu.dst.write = 1;
976 alu.is_op3 = 1;
977 alu.last = 1;
978 r = r600_bc_add_alu(ctx->bc, &alu);
979 if (r)
980 return r;
981
982 /* dst.z = exp(tmp.x) */
983 memset(&alu, 0, sizeof(struct r600_bc_alu));
984 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
985 alu.src[0].sel = ctx->temp_reg;
986 alu.src[0].chan = 0;
987 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
988 if (r)
989 return r;
990 alu.last = 1;
991 r = r600_bc_add_alu(ctx->bc, &alu);
992 if (r)
993 return r;
994 }
995 return 0;
996 }
997
998 static int tgsi_trans(struct r600_shader_ctx *ctx)
999 {
1000 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1001 struct r600_bc_alu alu;
1002 int i, j, r;
1003
1004 for (i = 0; i < 4; i++) {
1005 memset(&alu, 0, sizeof(struct r600_bc_alu));
1006 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
1007 alu.inst = ctx->inst_info->r600_opcode;
1008 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1009 r = tgsi_src(ctx, &inst->Src[j], &alu.src[j]);
1010 if (r)
1011 return r;
1012 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1013 }
1014 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1015 if (r)
1016 return r;
1017 alu.last = 1;
1018 r = r600_bc_add_alu(ctx->bc, &alu);
1019 if (r)
1020 return r;
1021 }
1022 }
1023 return 0;
1024 }
1025
1026 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1027 {
1028 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1029 struct r600_bc_alu alu;
1030 int i, r;
1031
1032 for (i = 0; i < 4; i++) {
1033 memset(&alu, 0, sizeof(struct r600_bc_alu));
1034 alu.src[0].sel = ctx->temp_reg;
1035 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
1036 alu.dst.chan = i;
1037 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1038 if (r)
1039 return r;
1040 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1041 if (i == 3)
1042 alu.last = 1;
1043 r = r600_bc_add_alu(ctx->bc, &alu);
1044 if (r)
1045 return r;
1046 }
1047 return 0;
1048 }
1049
1050 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1051 {
1052 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1053 struct r600_bc_alu alu;
1054 int i, r;
1055
1056 memset(&alu, 0, sizeof(struct r600_bc_alu));
1057 alu.inst = ctx->inst_info->r600_opcode;
1058 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1059 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1060 if (r)
1061 return r;
1062 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1063 }
1064 alu.dst.sel = ctx->temp_reg;
1065 alu.dst.write = 1;
1066 alu.last = 1;
1067 r = r600_bc_add_alu(ctx->bc, &alu);
1068 if (r)
1069 return r;
1070 /* replicate result */
1071 return tgsi_helper_tempx_replicate(ctx);
1072 }
1073
1074 static int tgsi_pow(struct r600_shader_ctx *ctx)
1075 {
1076 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1077 struct r600_bc_alu alu;
1078 int r;
1079
1080 /* LOG2(a) */
1081 memset(&alu, 0, sizeof(struct r600_bc_alu));
1082 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE;
1083 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1084 if (r)
1085 return r;
1086 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1087 alu.dst.sel = ctx->temp_reg;
1088 alu.dst.write = 1;
1089 alu.last = 1;
1090 r = r600_bc_add_alu(ctx->bc, &alu);
1091 if (r)
1092 return r;
1093 r = r600_bc_add_literal(ctx->bc,ctx->value);
1094 if (r)
1095 return r;
1096 /* b * LOG2(a) */
1097 memset(&alu, 0, sizeof(struct r600_bc_alu));
1098 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE;
1099 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1100 if (r)
1101 return r;
1102 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1103 alu.src[1].sel = ctx->temp_reg;
1104 alu.dst.sel = ctx->temp_reg;
1105 alu.dst.write = 1;
1106 alu.last = 1;
1107 r = r600_bc_add_alu(ctx->bc, &alu);
1108 if (r)
1109 return r;
1110 r = r600_bc_add_literal(ctx->bc,ctx->value);
1111 if (r)
1112 return r;
1113 /* POW(a,b) = EXP2(b * LOG2(a))*/
1114 memset(&alu, 0, sizeof(struct r600_bc_alu));
1115 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
1116 alu.src[0].sel = ctx->temp_reg;
1117 alu.dst.sel = ctx->temp_reg;
1118 alu.dst.write = 1;
1119 alu.last = 1;
1120 r = r600_bc_add_alu(ctx->bc, &alu);
1121 if (r)
1122 return r;
1123 r = r600_bc_add_literal(ctx->bc,ctx->value);
1124 if (r)
1125 return r;
1126 return tgsi_helper_tempx_replicate(ctx);
1127 }
1128
1129 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1130 {
1131 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1132 struct r600_bc_alu alu;
1133 struct r600_bc_alu_src r600_src[3];
1134 int i, r;
1135
1136 r = tgsi_split_constant(ctx, r600_src);
1137 if (r)
1138 return r;
1139
1140 /* tmp = (src > 0 ? 1 : src) */
1141 for (i = 0; i < 4; i++) {
1142 memset(&alu, 0, sizeof(struct r600_bc_alu));
1143 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT;
1144 alu.is_op3 = 1;
1145 alu.dst.sel = ctx->temp_reg;
1146 alu.dst.write = 1;
1147
1148 alu.src[0] = r600_src[0];
1149 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1150
1151 alu.src[1].sel = V_SQ_ALU_SRC_1;
1152
1153 alu.src[2] = r600_src[0];
1154 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1155 if (i == 3)
1156 alu.last = 1;
1157 r = r600_bc_add_alu(ctx->bc, &alu);
1158 if (r)
1159 return r;
1160 }
1161
1162 /* dst = (-tmp > 0 ? -1 : tmp) */
1163 for (i = 0; i < 4; i++) {
1164 memset(&alu, 0, sizeof(struct r600_bc_alu));
1165 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT;
1166 alu.is_op3 = 1;
1167 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1168 if (r)
1169 return r;
1170
1171 alu.src[0].sel = ctx->temp_reg;
1172 alu.src[0].neg = 1;
1173
1174 alu.src[1].sel = V_SQ_ALU_SRC_1;
1175 alu.src[1].neg = 1;
1176
1177 alu.src[2].sel = ctx->temp_reg;
1178
1179 alu.dst.write = 1;
1180 if (i == 3)
1181 alu.last = 1;
1182 r = r600_bc_add_alu(ctx->bc, &alu);
1183 if (r)
1184 return r;
1185 }
1186 return 0;
1187 }
1188
1189 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1190 {
1191 struct r600_bc_alu alu;
1192 int i, r;
1193
1194 r = r600_bc_add_literal(ctx->bc, ctx->value);
1195 if (r)
1196 return r;
1197 for (i = 0; i < 4; i++) {
1198 memset(&alu, 0, sizeof(struct r600_bc_alu));
1199 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1200 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
1201 alu.dst.chan = i;
1202 } else {
1203 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
1204 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1205 if (r)
1206 return r;
1207 alu.src[0].sel = ctx->temp_reg;
1208 alu.src[0].chan = i;
1209 }
1210 if (i == 3) {
1211 alu.last = 1;
1212 }
1213 r = r600_bc_add_alu(ctx->bc, &alu);
1214 if (r)
1215 return r;
1216 }
1217 return 0;
1218 }
1219
1220 static int tgsi_op3(struct r600_shader_ctx *ctx)
1221 {
1222 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1223 struct r600_bc_alu_src r600_src[3];
1224 struct r600_bc_alu alu;
1225 int i, j, r;
1226
1227 r = tgsi_split_constant(ctx, r600_src);
1228 if (r)
1229 return r;
1230 /* do it in 2 step as op3 doesn't support writemask */
1231 for (i = 0; i < 4; i++) {
1232 memset(&alu, 0, sizeof(struct r600_bc_alu));
1233 alu.inst = ctx->inst_info->r600_opcode;
1234 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1235 alu.src[j] = r600_src[j];
1236 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1237 }
1238 alu.dst.sel = ctx->temp_reg;
1239 alu.dst.chan = i;
1240 alu.dst.write = 1;
1241 alu.is_op3 = 1;
1242 if (i == 3) {
1243 alu.last = 1;
1244 }
1245 r = r600_bc_add_alu(ctx->bc, &alu);
1246 if (r)
1247 return r;
1248 }
1249 return tgsi_helper_copy(ctx, inst);
1250 }
1251
1252 static int tgsi_dp(struct r600_shader_ctx *ctx)
1253 {
1254 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1255 struct r600_bc_alu_src r600_src[3];
1256 struct r600_bc_alu alu;
1257 int i, j, r;
1258
1259 r = tgsi_split_constant(ctx, r600_src);
1260 if (r)
1261 return r;
1262 for (i = 0; i < 4; i++) {
1263 memset(&alu, 0, sizeof(struct r600_bc_alu));
1264 alu.inst = ctx->inst_info->r600_opcode;
1265 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1266 alu.src[j] = r600_src[j];
1267 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1268 }
1269 alu.dst.sel = ctx->temp_reg;
1270 alu.dst.chan = i;
1271 alu.dst.write = 1;
1272 /* handle some special cases */
1273 switch (ctx->inst_info->tgsi_opcode) {
1274 case TGSI_OPCODE_DP2:
1275 if (i > 1) {
1276 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1277 alu.src[0].chan = alu.src[1].chan = 0;
1278 }
1279 break;
1280 case TGSI_OPCODE_DP3:
1281 if (i > 2) {
1282 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1283 alu.src[0].chan = alu.src[1].chan = 0;
1284 }
1285 break;
1286 case TGSI_OPCODE_DPH:
1287 if (i == 3) {
1288 alu.src[0].sel = V_SQ_ALU_SRC_1;
1289 alu.src[0].chan = 0;
1290 alu.src[0].neg = 0;
1291 }
1292 break;
1293 default:
1294 break;
1295 }
1296 if (i == 3) {
1297 alu.last = 1;
1298 }
1299 r = r600_bc_add_alu(ctx->bc, &alu);
1300 if (r)
1301 return r;
1302 }
1303 return tgsi_helper_copy(ctx, inst);
1304 }
1305
1306 static int tgsi_tex(struct r600_shader_ctx *ctx)
1307 {
1308 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1309 struct r600_bc_tex tex;
1310 struct r600_bc_alu alu;
1311 unsigned src_gpr;
1312 int r, i;
1313
1314 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1315
1316 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1317 /* Add perspective divide */
1318 memset(&alu, 0, sizeof(struct r600_bc_alu));
1319 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE;
1320 alu.src[0].sel = src_gpr;
1321 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1322 alu.dst.sel = ctx->temp_reg;
1323 alu.dst.chan = 3;
1324 alu.last = 1;
1325 alu.dst.write = 1;
1326 r = r600_bc_add_alu(ctx->bc, &alu);
1327 if (r)
1328 return r;
1329
1330 for (i = 0; i < 3; i++) {
1331 memset(&alu, 0, sizeof(struct r600_bc_alu));
1332 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
1333 alu.src[0].sel = ctx->temp_reg;
1334 alu.src[0].chan = 3;
1335 alu.src[1].sel = src_gpr;
1336 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1337 alu.dst.sel = ctx->temp_reg;
1338 alu.dst.chan = i;
1339 alu.dst.write = 1;
1340 r = r600_bc_add_alu(ctx->bc, &alu);
1341 if (r)
1342 return r;
1343 }
1344 memset(&alu, 0, sizeof(struct r600_bc_alu));
1345 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
1346 alu.src[0].sel = V_SQ_ALU_SRC_1;
1347 alu.src[0].chan = 0;
1348 alu.dst.sel = ctx->temp_reg;
1349 alu.dst.chan = 3;
1350 alu.last = 1;
1351 alu.dst.write = 1;
1352 r = r600_bc_add_alu(ctx->bc, &alu);
1353 if (r)
1354 return r;
1355 src_gpr = ctx->temp_reg;
1356 } else if (inst->Src[0].Register.File != TGSI_FILE_TEMPORARY) {
1357 for (i = 0; i < 4; i++) {
1358 memset(&alu, 0, sizeof(struct r600_bc_alu));
1359 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
1360 alu.src[0].sel = src_gpr;
1361 alu.src[0].chan = i;
1362 alu.dst.sel = ctx->temp_reg;
1363 alu.dst.chan = i;
1364 if (i == 3)
1365 alu.last = 1;
1366 alu.dst.write = 1;
1367 r = r600_bc_add_alu(ctx->bc, &alu);
1368 if (r)
1369 return r;
1370 }
1371 src_gpr = ctx->temp_reg;
1372 }
1373
1374 memset(&tex, 0, sizeof(struct r600_bc_tex));
1375 tex.inst = ctx->inst_info->r600_opcode;
1376 tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1377 tex.sampler_id = tex.resource_id;
1378 tex.src_gpr = src_gpr;
1379 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1380 tex.dst_sel_x = 0;
1381 tex.dst_sel_y = 1;
1382 tex.dst_sel_z = 2;
1383 tex.dst_sel_w = 3;
1384 tex.src_sel_x = 0;
1385 tex.src_sel_y = 1;
1386 tex.src_sel_z = 2;
1387 tex.src_sel_w = 3;
1388
1389 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1390 tex.coord_type_x = 1;
1391 tex.coord_type_y = 1;
1392 tex.coord_type_z = 1;
1393 tex.coord_type_w = 1;
1394 }
1395 return r600_bc_add_tex(ctx->bc, &tex);
1396 }
1397
1398 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1399 {
1400 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1401 struct r600_bc_alu_src r600_src[3];
1402 struct r600_bc_alu alu;
1403 unsigned i;
1404 int r;
1405
1406 r = tgsi_split_constant(ctx, r600_src);
1407 if (r)
1408 return r;
1409 /* 1 - src0 */
1410 for (i = 0; i < 4; i++) {
1411 memset(&alu, 0, sizeof(struct r600_bc_alu));
1412 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD;
1413 alu.src[0].sel = V_SQ_ALU_SRC_1;
1414 alu.src[0].chan = 0;
1415 alu.src[1] = r600_src[0];
1416 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1417 alu.src[1].neg = 1;
1418 alu.dst.sel = ctx->temp_reg;
1419 alu.dst.chan = i;
1420 if (i == 3) {
1421 alu.last = 1;
1422 }
1423 alu.dst.write = 1;
1424 r = r600_bc_add_alu(ctx->bc, &alu);
1425 if (r)
1426 return r;
1427 }
1428 r = r600_bc_add_literal(ctx->bc, ctx->value);
1429 if (r)
1430 return r;
1431
1432 /* (1 - src0) * src2 */
1433 for (i = 0; i < 4; i++) {
1434 memset(&alu, 0, sizeof(struct r600_bc_alu));
1435 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
1436 alu.src[0].sel = ctx->temp_reg;
1437 alu.src[0].chan = i;
1438 alu.src[1] = r600_src[2];
1439 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1440 alu.dst.sel = ctx->temp_reg;
1441 alu.dst.chan = i;
1442 if (i == 3) {
1443 alu.last = 1;
1444 }
1445 alu.dst.write = 1;
1446 r = r600_bc_add_alu(ctx->bc, &alu);
1447 if (r)
1448 return r;
1449 }
1450 r = r600_bc_add_literal(ctx->bc, ctx->value);
1451 if (r)
1452 return r;
1453
1454 /* src0 * src1 + (1 - src0) * src2 */
1455 for (i = 0; i < 4; i++) {
1456 memset(&alu, 0, sizeof(struct r600_bc_alu));
1457 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
1458 alu.is_op3 = 1;
1459 alu.src[0] = r600_src[0];
1460 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1461 alu.src[1] = r600_src[1];
1462 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1463 alu.src[2].sel = ctx->temp_reg;
1464 alu.src[2].chan = i;
1465 alu.dst.sel = ctx->temp_reg;
1466 alu.dst.chan = i;
1467 if (i == 3) {
1468 alu.last = 1;
1469 }
1470 r = r600_bc_add_alu(ctx->bc, &alu);
1471 if (r)
1472 return r;
1473 }
1474 return tgsi_helper_copy(ctx, inst);
1475 }
1476
1477 static int tgsi_cmp(struct r600_shader_ctx *ctx)
1478 {
1479 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1480 struct r600_bc_alu_src r600_src[3];
1481 struct r600_bc_alu alu;
1482 int use_temp = 0;
1483 int i, r;
1484
1485 r = tgsi_split_constant(ctx, r600_src);
1486 if (r)
1487 return r;
1488
1489 if (inst->Dst[0].Register.WriteMask != 0xf)
1490 use_temp = 1;
1491
1492 for (i = 0; i < 4; i++) {
1493 memset(&alu, 0, sizeof(struct r600_bc_alu));
1494 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE;
1495 alu.src[0] = r600_src[0];
1496 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1497
1498 alu.src[1] = r600_src[2];
1499 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1500
1501 alu.src[2] = r600_src[1];
1502 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
1503
1504 if (use_temp)
1505 alu.dst.sel = ctx->temp_reg;
1506 else {
1507 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1508 if (r)
1509 return r;
1510 }
1511 alu.dst.chan = i;
1512 alu.dst.write = 1;
1513 alu.is_op3 = 1;
1514 if (i == 3)
1515 alu.last = 1;
1516 r = r600_bc_add_alu(ctx->bc, &alu);
1517 if (r)
1518 return r;
1519 }
1520 if (use_temp)
1521 return tgsi_helper_copy(ctx, inst);
1522 return 0;
1523 }
1524
1525 static int tgsi_xpd(struct r600_shader_ctx *ctx)
1526 {
1527 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1528 struct r600_bc_alu_src r600_src[3];
1529 struct r600_bc_alu alu;
1530 uint32_t use_temp = 0;
1531 int i, r;
1532
1533 if (inst->Dst[0].Register.WriteMask != 0xf)
1534 use_temp = 1;
1535
1536 r = tgsi_split_constant(ctx, r600_src);
1537 if (r)
1538 return r;
1539
1540 for (i = 0; i < 4; i++) {
1541 memset(&alu, 0, sizeof(struct r600_bc_alu));
1542 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
1543
1544 alu.src[0] = r600_src[0];
1545 switch (i) {
1546 case 0:
1547 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
1548 break;
1549 case 1:
1550 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1551 break;
1552 case 2:
1553 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1554 break;
1555 case 3:
1556 alu.src[0].sel = V_SQ_ALU_SRC_0;
1557 alu.src[0].chan = i;
1558 }
1559
1560 alu.src[1] = r600_src[1];
1561 switch (i) {
1562 case 0:
1563 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
1564 break;
1565 case 1:
1566 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
1567 break;
1568 case 2:
1569 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
1570 break;
1571 case 3:
1572 alu.src[1].sel = V_SQ_ALU_SRC_0;
1573 alu.src[1].chan = i;
1574 }
1575
1576 alu.dst.sel = ctx->temp_reg;
1577 alu.dst.chan = i;
1578 alu.dst.write = 1;
1579
1580 if (i == 3)
1581 alu.last = 1;
1582 r = r600_bc_add_alu(ctx->bc, &alu);
1583 if (r)
1584 return r;
1585 }
1586
1587 for (i = 0; i < 4; i++) {
1588 memset(&alu, 0, sizeof(struct r600_bc_alu));
1589 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
1590
1591 alu.src[0] = r600_src[0];
1592 switch (i) {
1593 case 0:
1594 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1595 break;
1596 case 1:
1597 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
1598 break;
1599 case 2:
1600 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1601 break;
1602 case 3:
1603 alu.src[0].sel = V_SQ_ALU_SRC_0;
1604 alu.src[0].chan = i;
1605 }
1606
1607 alu.src[1] = r600_src[1];
1608 switch (i) {
1609 case 0:
1610 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
1611 break;
1612 case 1:
1613 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
1614 break;
1615 case 2:
1616 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
1617 break;
1618 case 3:
1619 alu.src[1].sel = V_SQ_ALU_SRC_0;
1620 alu.src[1].chan = i;
1621 }
1622
1623 alu.src[2].sel = ctx->temp_reg;
1624 alu.src[2].neg = 1;
1625 alu.src[2].chan = i;
1626
1627 if (use_temp)
1628 alu.dst.sel = ctx->temp_reg;
1629 else {
1630 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1631 if (r)
1632 return r;
1633 }
1634 alu.dst.chan = i;
1635 alu.dst.write = 1;
1636 alu.is_op3 = 1;
1637 if (i == 3)
1638 alu.last = 1;
1639 r = r600_bc_add_alu(ctx->bc, &alu);
1640 if (r)
1641 return r;
1642 }
1643 if (use_temp)
1644 return tgsi_helper_copy(ctx, inst);
1645 return 0;
1646 }
1647
1648 static int tgsi_exp(struct r600_shader_ctx *ctx)
1649 {
1650 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1651 struct r600_bc_alu_src r600_src[3];
1652 struct r600_bc_alu alu;
1653 uint32_t use_temp = 0;
1654 int i, r;
1655
1656 /* result.x = 2^floor(src); */
1657 if (inst->Dst[0].Register.WriteMask & 1) {
1658 memset(&alu, 0, sizeof(struct r600_bc_alu));
1659
1660 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR;
1661 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1662 if (r)
1663 return r;
1664
1665 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1666
1667 alu.dst.sel = ctx->temp_reg;
1668 alu.dst.chan = 0;
1669 alu.dst.write = 1;
1670 alu.last = 1;
1671 r = r600_bc_add_alu(ctx->bc, &alu);
1672 if (r)
1673 return r;
1674
1675 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
1676 alu.src[0].sel = ctx->temp_reg;
1677 alu.src[0].chan = 0;
1678
1679 alu.dst.sel = ctx->temp_reg;
1680 alu.dst.chan = 0;
1681 alu.dst.write = 1;
1682 alu.last = 1;
1683 r = r600_bc_add_alu(ctx->bc, &alu);
1684 if (r)
1685 return r;
1686 }
1687
1688 /* result.y = tmp - floor(tmp); */
1689 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
1690 memset(&alu, 0, sizeof(struct r600_bc_alu));
1691
1692 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT;
1693 alu.src[0] = r600_src[0];
1694 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1695 if (r)
1696 return r;
1697 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1698
1699 alu.dst.sel = ctx->temp_reg;
1700 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1701 // if (r)
1702 // return r;
1703 alu.dst.write = 1;
1704 alu.dst.chan = 1;
1705
1706 alu.last = 1;
1707
1708 r = r600_bc_add_alu(ctx->bc, &alu);
1709 if (r)
1710 return r;
1711 }
1712
1713 /* result.z = RoughApprox2ToX(tmp);*/
1714 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
1715 memset(&alu, 0, sizeof(struct r600_bc_alu));
1716 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
1717 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1718 if (r)
1719 return r;
1720 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1721
1722 alu.dst.sel = ctx->temp_reg;
1723 alu.dst.write = 1;
1724 alu.dst.chan = 2;
1725
1726 alu.last = 1;
1727
1728 r = r600_bc_add_alu(ctx->bc, &alu);
1729 if (r)
1730 return r;
1731
1732 }
1733
1734 /* result.w = 1.0;*/
1735 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
1736 memset(&alu, 0, sizeof(struct r600_bc_alu));
1737
1738 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
1739 alu.src[0].sel = V_SQ_ALU_SRC_1;
1740 alu.src[0].chan = 0;
1741
1742 alu.dst.sel = ctx->temp_reg;
1743 alu.dst.chan = 3;
1744 alu.dst.write = 1;
1745 alu.last = 1;
1746 r = r600_bc_add_alu(ctx->bc, &alu);
1747 if (r)
1748 return r;
1749 }
1750 return tgsi_helper_copy(ctx, inst);
1751 }
1752
1753 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
1754 {
1755 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1756 struct r600_bc_alu alu, *lalu;
1757 struct r600_bc_cf *last;
1758 int r;
1759
1760 memset(&alu, 0, sizeof(struct r600_bc_alu));
1761 alu.inst = opcode;
1762 alu.predicate = 1;
1763
1764 alu.dst.sel = ctx->temp_reg;
1765 alu.dst.write = 1;
1766 alu.dst.chan = 0;
1767
1768 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1769 if (r)
1770 return r;
1771 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1772 alu.src[1].sel = V_SQ_ALU_SRC_0;
1773 alu.src[1].chan = 0;
1774
1775 alu.last = 1;
1776
1777 r = r600_bc_add_alu_type(ctx->bc, &alu, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE);
1778 if (r)
1779 return r;
1780
1781 return 0;
1782 }
1783
1784 static int pops(struct r600_shader_ctx *ctx, int pops)
1785 {
1786 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_POP);
1787 ctx->bc->cf_last->pop_count = pops;
1788 return 0;
1789 }
1790
1791 static int tgsi_if(struct r600_shader_ctx *ctx)
1792 {
1793 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1794
1795 emit_logic_pred(ctx, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE);
1796
1797 ctx->bc->fc_sp++;
1798 ctx->bc->fc_stack[ctx->bc->fc_sp].type = FC_IF;
1799 ctx->bc->fc_stack[ctx->bc->fc_sp].mid = NULL;
1800 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
1801
1802 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
1803 return 0;
1804 }
1805
1806 static int tgsi_else(struct r600_shader_ctx *ctx)
1807 {
1808 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1809 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_ELSE);
1810 ctx->bc->cf_last->pop_count = 1;
1811
1812 /* fixup mid */
1813 ctx->bc->fc_stack[ctx->bc->fc_sp].mid = ctx->bc->cf_last;
1814 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
1815 return 0;
1816 }
1817
1818 static int tgsi_endif(struct r600_shader_ctx *ctx)
1819 {
1820 pops(ctx, 1);
1821 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
1822 R600_ERR("if/endif unbalanced in shader\n");
1823 return -1;
1824 }
1825
1826 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
1827 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
1828 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
1829 } else {
1830 ctx->bc->fc_stack[ctx->bc->fc_sp].mid->cf_addr = ctx->bc->cf_last->id + 2;
1831 }
1832 ctx->bc->fc_sp--;
1833
1834 return 0;
1835 }
1836
1837 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
1838 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1839 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
1840 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
1841 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
1842 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
1843 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
1844 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1845 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
1846 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
1847 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
1848 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
1849 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1850 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
1851 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
1852 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
1853 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
1854 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
1855 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
1856 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
1857 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1858 /* gap */
1859 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1860 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1861 /* gap */
1862 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1863 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1864 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
1865 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1866 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
1867 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1868 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
1869 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
1870 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
1871 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
1872 /* gap */
1873 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1874 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
1875 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1876 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
1877 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
1878 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
1879 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
1880 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* predicated kill */
1881 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1882 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1883 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1884 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1885 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1886 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
1887 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1888 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
1889 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
1890 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
1891 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
1892 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1893 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
1894 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1895 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
1896 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1897 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1898 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1899 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1900 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1901 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1902 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1903 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1904 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1905 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1906 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
1907 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
1908 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1909 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
1910 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1911 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1912 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
1913 {TGSI_OPCODE_TXL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1914 {TGSI_OPCODE_BRK, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1915 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
1916 /* gap */
1917 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1918 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1919 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
1920 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
1921 /* gap */
1922 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1923 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1924 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1925 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1926 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1927 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1928 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1929 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
1930 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1931 /* gap */
1932 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1933 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1934 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1935 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1936 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1937 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1938 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1939 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1940 {TGSI_OPCODE_CONT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1941 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1942 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1943 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1944 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1945 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1946 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1947 /* gap */
1948 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1949 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1950 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1951 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1952 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1953 /* gap */
1954 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1955 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1956 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1957 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1958 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1959 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1960 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1961 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1962 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
1963 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
1964 /* gap */
1965 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1966 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1967 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1968 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1969 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1970 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1971 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1972 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1973 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1974 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1975 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1976 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1977 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1978 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1979 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1980 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1981 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1982 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1983 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1984 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1985 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1986 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1987 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1988 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1989 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1990 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1991 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1992 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1993 };