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r600g: fix dp2, dp3, dp4 tokens
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "util/u_format.h"
27 #include "r600_screen.h"
28 #include "r600_context.h"
29 #include "r600_shader.h"
30 #include "r600_asm.h"
31 #include "r600_sq.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
37
38 static int r600_shader_update(struct pipe_context *ctx, struct r600_shader *shader)
39 {
40 struct r600_context *rctx = r600_context(ctx);
41 const struct util_format_description *desc;
42 enum pipe_format resource_format[160];
43 unsigned i, nresources = 0;
44 struct r600_bc *bc = &shader->bc;
45 struct r600_bc_cf *cf;
46 struct r600_bc_vtx *vtx;
47
48 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
49 return 0;
50 for (i = 0; i < rctx->vertex_elements->count; i++) {
51 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
52 }
53 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
54 switch (cf->inst) {
55 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
56 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
57 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
58 desc = util_format_description(resource_format[vtx->buffer_id]);
59 if (desc == NULL) {
60 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
61 return -EINVAL;
62 }
63 vtx->dst_sel_x = desc->swizzle[0];
64 vtx->dst_sel_y = desc->swizzle[1];
65 vtx->dst_sel_z = desc->swizzle[2];
66 vtx->dst_sel_w = desc->swizzle[3];
67 }
68 break;
69 default:
70 break;
71 }
72 }
73 return r600_bc_build(&shader->bc);
74 }
75
76 struct r600_pipe_shader *r600_pipe_shader_create(struct pipe_context *ctx,
77 const struct tgsi_token *tokens)
78 {
79 struct r600_screen *rscreen = r600_screen(ctx->screen);
80 struct r600_pipe_shader *rpshader = CALLOC_STRUCT(r600_pipe_shader);
81 int r;
82
83 fprintf(stderr, "--------------------------------------------------------------\n");
84 tgsi_dump(tokens, 0);
85 if (rpshader == NULL)
86 return NULL;
87 rpshader->shader.family = radeon_get_family(rscreen->rw);
88 r = r600_shader_from_tgsi(tokens, &rpshader->shader);
89 if (r) {
90 R600_ERR("translation from TGSI failed !\n");
91 goto out_err;
92 }
93 r = r600_bc_build(&rpshader->shader.bc);
94 if (r) {
95 R600_ERR("building bytecode failed !\n");
96 goto out_err;
97 }
98 fprintf(stderr, "______________________________________________________________\n");
99 return rpshader;
100 out_err:
101 free(rpshader);
102 return NULL;
103 }
104
105 static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *rpshader)
106 {
107 struct r600_screen *rscreen = r600_screen(ctx->screen);
108 struct r600_shader *rshader = &rpshader->shader;
109 struct radeon_state *state;
110 unsigned i, j, tmp;
111
112 rpshader->state = radeon_state_decref(rpshader->state);
113 state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
114 if (state == NULL)
115 return -ENOMEM;
116 for (i = 0; i < 10; i++) {
117 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
118 }
119 for (i = 0, j = 0; i < rshader->noutput; i++) {
120 if (rshader->output[i].name != TGSI_SEMANTIC_POSITION) {
121 tmp = rshader->output[i].sid << ((j & 3) * 8);
122 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + j / 4] |= tmp;
123 j++;
124 }
125 }
126 state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
127 state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr);
128 rpshader->state = state;
129 rpshader->state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
130 rpshader->state->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
131 rpshader->state->nbo = 2;
132 rpshader->state->placement[0] = RADEON_GEM_DOMAIN_GTT;
133 return radeon_state_pm4(state);
134 }
135
136 static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *rpshader)
137 {
138 struct r600_screen *rscreen = r600_screen(ctx->screen);
139 struct r600_shader *rshader = &rpshader->shader;
140 struct radeon_state *state;
141 unsigned i, tmp;
142
143 rpshader->state = radeon_state_decref(rpshader->state);
144 state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
145 if (state == NULL)
146 return -ENOMEM;
147 for (i = 0; i < rshader->ninput; i++) {
148 tmp = S_028644_SEMANTIC(rshader->input[i].sid);
149 tmp |= S_028644_SEL_CENTROID(1);
150 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
151 state->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
152 }
153 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
154 S_0286CC_PERSP_GRADIENT_ENA(1);
155 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
156 state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr);
157 state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = 0x00000002;
158 rpshader->state = state;
159 rpshader->state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
160 rpshader->state->nbo = 1;
161 rpshader->state->placement[0] = RADEON_GEM_DOMAIN_GTT;
162 return radeon_state_pm4(state);
163 }
164
165 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *rpshader)
166 {
167 struct r600_screen *rscreen = r600_screen(ctx->screen);
168 struct r600_context *rctx = r600_context(ctx);
169 struct r600_shader *rshader = &rpshader->shader;
170 int r;
171
172 /* copy new shader */
173 radeon_bo_decref(rscreen->rw, rpshader->bo);
174 rpshader->bo = NULL;
175 rpshader->bo = radeon_bo(rscreen->rw, 0, rshader->bc.ndw * 4,
176 4096, NULL);
177 if (rpshader->bo == NULL) {
178 return -ENOMEM;
179 }
180 radeon_bo_map(rscreen->rw, rpshader->bo);
181 memcpy(rpshader->bo->data, rshader->bc.bytecode, rshader->bc.ndw * 4);
182 radeon_bo_unmap(rscreen->rw, rpshader->bo);
183 /* build state */
184 rshader->flat_shade = rctx->flat_shade;
185 switch (rshader->processor_type) {
186 case TGSI_PROCESSOR_VERTEX:
187 r = r600_pipe_shader_vs(ctx, rpshader);
188 break;
189 case TGSI_PROCESSOR_FRAGMENT:
190 r = r600_pipe_shader_ps(ctx, rpshader);
191 break;
192 default:
193 r = -EINVAL;
194 break;
195 }
196 return r;
197 }
198
199 int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rpshader)
200 {
201 struct r600_context *rctx = r600_context(ctx);
202 int r;
203
204 if (rpshader == NULL)
205 return -EINVAL;
206 /* there should be enough input */
207 if (rctx->vertex_elements->count < rpshader->shader.bc.nresource) {
208 R600_ERR("%d resources provided, expecting %d\n",
209 rctx->vertex_elements->count, rpshader->shader.bc.nresource);
210 return -EINVAL;
211 }
212 r = r600_shader_update(ctx, &rpshader->shader);
213 if (r)
214 return r;
215 return r600_pipe_shader(ctx, rpshader);
216 }
217
218 struct r600_shader_tgsi_instruction;
219
220 struct r600_shader_ctx {
221 struct tgsi_shader_info info;
222 struct tgsi_parse_context parse;
223 const struct tgsi_token *tokens;
224 unsigned type;
225 unsigned file_offset[TGSI_FILE_COUNT];
226 unsigned temp_reg;
227 struct r600_shader_tgsi_instruction *inst_info;
228 struct r600_bc *bc;
229 struct r600_shader *shader;
230 };
231
232 struct r600_shader_tgsi_instruction {
233 unsigned tgsi_opcode;
234 unsigned is_op3;
235 unsigned r600_opcode;
236 int (*process)(struct r600_shader_ctx *ctx);
237 };
238
239 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[];
240
241 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
242 {
243 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
244 int j;
245
246 if (i->Instruction.NumDstRegs > 1) {
247 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
248 return -EINVAL;
249 }
250 if (i->Instruction.Saturate) {
251 R600_ERR("staturate unsupported\n");
252 return -EINVAL;
253 }
254 if (i->Instruction.Predicate) {
255 R600_ERR("predicate unsupported\n");
256 return -EINVAL;
257 }
258 if (i->Instruction.Label) {
259 R600_ERR("label unsupported\n");
260 return -EINVAL;
261 }
262 if (i->Instruction.Texture) {
263 R600_ERR("texture unsupported\n");
264 return -EINVAL;
265 }
266 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
267 if (i->Src[j].Register.Indirect ||
268 i->Src[j].Register.Dimension ||
269 i->Src[j].Register.Absolute) {
270 R600_ERR("unsupported src (indirect|dimension|absolute)\n");
271 return -EINVAL;
272 }
273 }
274 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
275 if (i->Dst[j].Register.Indirect || i->Dst[j].Register.Dimension) {
276 R600_ERR("unsupported dst (indirect|dimension)\n");
277 return -EINVAL;
278 }
279 }
280 return 0;
281 }
282
283 static int tgsi_declaration(struct r600_shader_ctx *ctx)
284 {
285 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
286 struct r600_bc_vtx vtx;
287 unsigned i;
288 int r;
289
290 switch (d->Declaration.File) {
291 case TGSI_FILE_INPUT:
292 i = ctx->shader->ninput++;
293 ctx->shader->input[i].name = d->Semantic.Name;
294 ctx->shader->input[i].sid = d->Semantic.Index;
295 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
296 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
297 /* turn input into fetch */
298 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
299 vtx.inst = 0;
300 vtx.fetch_type = 0;
301 vtx.buffer_id = i;
302 /* register containing the index into the buffer */
303 vtx.src_gpr = 0;
304 vtx.src_sel_x = 0;
305 vtx.mega_fetch_count = 0x1F;
306 vtx.dst_gpr = ctx->shader->input[i].gpr;
307 vtx.dst_sel_x = 0;
308 vtx.dst_sel_y = 1;
309 vtx.dst_sel_z = 2;
310 vtx.dst_sel_w = 3;
311 r = r600_bc_add_vtx(ctx->bc, &vtx);
312 if (r)
313 return r;
314 }
315 break;
316 case TGSI_FILE_OUTPUT:
317 i = ctx->shader->noutput++;
318 ctx->shader->output[i].name = d->Semantic.Name;
319 ctx->shader->output[i].sid = d->Semantic.Index;
320 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
321 break;
322 case TGSI_FILE_CONSTANT:
323 case TGSI_FILE_TEMPORARY:
324 break;
325 default:
326 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
327 return -EINVAL;
328 }
329 return 0;
330 }
331
332 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
333 {
334 struct tgsi_full_immediate *immediate;
335 struct r600_shader_ctx ctx;
336 struct r600_bc_output output;
337 unsigned opcode;
338 int i, r = 0, pos0;
339 u32 value[4];
340
341 ctx.bc = &shader->bc;
342 ctx.shader = shader;
343 r = r600_bc_init(ctx.bc, shader->family);
344 if (r)
345 return r;
346 ctx.tokens = tokens;
347 tgsi_scan_shader(tokens, &ctx.info);
348 tgsi_parse_init(&ctx.parse, tokens);
349 ctx.type = ctx.parse.FullHeader.Processor.Processor;
350 shader->processor_type = ctx.type;
351
352 /* register allocations */
353 /* Values [0,127] correspond to GPR[0..127].
354 * Values [256,511] correspond to cfile constants c[0..255].
355 * Other special values are shown in the list below.
356 * 248 SQ_ALU_SRC_0: special constant 0.0.
357 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
358 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
359 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
360 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
361 * 253 SQ_ALU_SRC_LITERAL: literal constant.
362 * 254 SQ_ALU_SRC_PV: previous vector result.
363 * 255 SQ_ALU_SRC_PS: previous scalar result.
364 */
365 for (i = 0; i < TGSI_FILE_COUNT; i++) {
366 ctx.file_offset[i] = 0;
367 }
368 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
369 ctx.file_offset[TGSI_FILE_INPUT] = 1;
370 }
371 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
372 ctx.info.file_count[TGSI_FILE_INPUT];
373 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
374 ctx.info.file_count[TGSI_FILE_OUTPUT];
375 ctx.file_offset[TGSI_FILE_CONSTANT] = 256;
376 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
377 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
378 ctx.info.file_count[TGSI_FILE_TEMPORARY];
379
380 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
381 tgsi_parse_token(&ctx.parse);
382 switch (ctx.parse.FullToken.Token.Type) {
383 case TGSI_TOKEN_TYPE_IMMEDIATE:
384 // R600_ERR("TGSI_TOKEN_TYPE_IMMEDIATE unsupported\n");
385 immediate = &ctx.parse.FullToken.FullImmediate;
386 value[0] = immediate->u[0].Uint;
387 value[1] = immediate->u[1].Uint;
388 value[2] = immediate->u[2].Uint;
389 value[3] = immediate->u[3].Uint;
390 break;
391 case TGSI_TOKEN_TYPE_DECLARATION:
392 r = tgsi_declaration(&ctx);
393 if (r)
394 goto out_err;
395 break;
396 case TGSI_TOKEN_TYPE_INSTRUCTION:
397 r = tgsi_is_supported(&ctx);
398 if (r)
399 goto out_err;
400 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
401 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
402 r = ctx.inst_info->process(&ctx);
403 if (r)
404 goto out_err;
405 r = r600_bc_add_literal(ctx.bc, value);
406 if (r)
407 goto out_err;
408 break;
409 default:
410 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
411 r = -EINVAL;
412 goto out_err;
413 }
414 }
415 /* export output */
416 for (i = 0, pos0 = 0; i < shader->noutput; i++) {
417 memset(&output, 0, sizeof(struct r600_bc_output));
418 output.gpr = shader->output[i].gpr;
419 output.elem_size = 3;
420 output.swizzle_x = 0;
421 output.swizzle_y = 1;
422 output.swizzle_z = 2;
423 output.swizzle_w = 3;
424 output.barrier = 1;
425 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
426 output.array_base = i - pos0;
427 output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE;
428 switch (ctx.type == TGSI_PROCESSOR_VERTEX) {
429 case TGSI_PROCESSOR_VERTEX:
430 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
431 output.array_base = 60;
432 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
433 /* position doesn't count in array_base */
434 pos0 = 1;
435 }
436 break;
437 case TGSI_PROCESSOR_FRAGMENT:
438 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
439 output.array_base = 0;
440 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
441 } else {
442 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
443 r = -EINVAL;
444 goto out_err;
445 }
446 break;
447 default:
448 R600_ERR("unsupported processor type %d\n", ctx.type);
449 r = -EINVAL;
450 goto out_err;
451 }
452 if (i == (shader->noutput - 1)) {
453 output.end_of_program = 1;
454 }
455 r = r600_bc_add_output(ctx.bc, &output);
456 if (r)
457 goto out_err;
458 }
459 tgsi_parse_free(&ctx.parse);
460 return 0;
461 out_err:
462 tgsi_parse_free(&ctx.parse);
463 return r;
464 }
465
466 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
467 {
468 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
469 return -EINVAL;
470 }
471
472 static int tgsi_end(struct r600_shader_ctx *ctx)
473 {
474 return 0;
475 }
476
477 static int tgsi_src(struct r600_shader_ctx *ctx,
478 const struct tgsi_full_src_register *tgsi_src,
479 unsigned swizzle,
480 struct r600_bc_alu_src *r600_src)
481 {
482 r600_src->sel = tgsi_src->Register.Index;
483 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
484 r600_src->sel = 0;
485 }
486 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
487 switch (swizzle) {
488 case 0:
489 r600_src->chan = tgsi_src->Register.SwizzleX;
490 break;
491 case 1:
492 r600_src->chan = tgsi_src->Register.SwizzleY;
493 break;
494 case 2:
495 r600_src->chan = tgsi_src->Register.SwizzleZ;
496 break;
497 case 3:
498 r600_src->chan = tgsi_src->Register.SwizzleW;
499 break;
500 default:
501 return -EINVAL;
502 }
503 return 0;
504 }
505
506 static int tgsi_dst(struct r600_shader_ctx *ctx,
507 const struct tgsi_full_dst_register *tgsi_dst,
508 unsigned swizzle,
509 struct r600_bc_alu_dst *r600_dst)
510 {
511 r600_dst->sel = tgsi_dst->Register.Index;
512 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
513 r600_dst->chan = swizzle;
514 r600_dst->write = 1;
515 return 0;
516 }
517
518 static int tgsi_op2(struct r600_shader_ctx *ctx)
519 {
520 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
521 struct r600_bc_alu alu;
522 int i, j, r;
523
524 for (i = 0; i < 4; i++) {
525 memset(&alu, 0, sizeof(struct r600_bc_alu));
526 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
527 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
528 } else {
529 alu.inst = ctx->inst_info->r600_opcode;
530 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
531 r = tgsi_src(ctx, &inst->Src[j], i, &alu.src[j]);
532 if (r)
533 return r;
534 }
535 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
536 if (r)
537 return r;
538 }
539 /* handle some special cases */
540 switch (ctx->inst_info->tgsi_opcode) {
541 case TGSI_OPCODE_SUB:
542 alu.src[1].neg = 1;
543 break;
544 default:
545 break;
546 }
547 if (i == 3) {
548 alu.last = 1;
549 }
550 r = r600_bc_add_alu(ctx->bc, &alu);
551 if (r)
552 return r;
553 }
554 return 0;
555 }
556
557 static int tgsi_slt(struct r600_shader_ctx *ctx)
558 {
559 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
560 struct r600_bc_alu alu;
561 int i, r;
562
563 for (i = 0; i < 4; i++) {
564 memset(&alu, 0, sizeof(struct r600_bc_alu));
565 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
566 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
567 } else {
568 alu.inst = ctx->inst_info->r600_opcode;
569 r = tgsi_src(ctx, &inst->Src[0], i, &alu.src[1]);
570 if (r)
571 return r;
572 r = tgsi_src(ctx, &inst->Src[1], i, &alu.src[0]);
573 if (r)
574 return r;
575 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
576 if (r)
577 return r;
578 }
579 if (i == 3) {
580 alu.last = 1;
581 }
582 r = r600_bc_add_alu(ctx->bc, &alu);
583 if (r)
584 return r;
585 }
586 return 0;
587 }
588
589 static int tgsi_trans(struct r600_shader_ctx *ctx)
590 {
591 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
592 struct r600_bc_alu alu;
593 int i, j, r;
594
595 for (i = 0; i < 4; i++) {
596 memset(&alu, 0, sizeof(struct r600_bc_alu));
597 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
598 alu.inst = ctx->inst_info->r600_opcode;
599 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
600 r = tgsi_src(ctx, &inst->Src[j], i, &alu.src[j]);
601 if (r)
602 return r;
603 }
604 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
605 if (r)
606 return r;
607 alu.last = 1;
608 r = r600_bc_add_alu(ctx->bc, &alu);
609 if (r)
610 return r;
611 }
612 }
613 return 0;
614 }
615
616 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
617 {
618 struct r600_bc_alu alu;
619 int i, r;
620
621 for (i = 0; i < 4; i++) {
622 memset(&alu, 0, sizeof(struct r600_bc_alu));
623 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
624 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
625 } else {
626 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
627 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
628 if (r)
629 return r;
630 alu.src[0].sel = ctx->temp_reg;
631 alu.src[0].chan = i;
632 }
633 if (i == 3) {
634 alu.last = 1;
635 }
636 r = r600_bc_add_alu(ctx->bc, &alu);
637 if (r)
638 return r;
639 }
640 return 0;
641 }
642
643 static int tgsi_op3(struct r600_shader_ctx *ctx)
644 {
645 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
646 struct r600_bc_alu alu;
647 int i, j, r;
648
649 /* do it in 2 step as op3 doesn't support writemask */
650 for (i = 0; i < 4; i++) {
651 memset(&alu, 0, sizeof(struct r600_bc_alu));
652 alu.inst = ctx->inst_info->r600_opcode;
653 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
654 r = tgsi_src(ctx, &inst->Src[j], i, &alu.src[j]);
655 if (r)
656 return r;
657 }
658 alu.dst.sel = ctx->temp_reg;
659 alu.dst.chan = i;
660 alu.dst.write = 1;
661 alu.is_op3 = 1;
662 if (i == 3) {
663 alu.last = 1;
664 }
665 r = r600_bc_add_alu(ctx->bc, &alu);
666 if (r)
667 return r;
668 }
669 return tgsi_helper_copy(ctx, inst);
670 }
671
672 static int tgsi_dp(struct r600_shader_ctx *ctx)
673 {
674 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
675 struct r600_bc_alu alu;
676 int i, j, r;
677
678 for (i = 0; i < 4; i++) {
679 memset(&alu, 0, sizeof(struct r600_bc_alu));
680 alu.inst = ctx->inst_info->r600_opcode;
681 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
682 r = tgsi_src(ctx, &inst->Src[j], i, &alu.src[j]);
683 if (r)
684 return r;
685 }
686 alu.dst.sel = ctx->temp_reg;
687 alu.dst.chan = i;
688 alu.dst.write = 1;
689 /* handle some special cases */
690 switch (ctx->inst_info->tgsi_opcode) {
691 case TGSI_OPCODE_DP2:
692 if (i > 1) {
693 alu.src[0].sel = alu.src[1].sel = 248;
694 alu.src[0].chan = alu.src[1].chan = 0;
695 }
696 break;
697 case TGSI_OPCODE_DP3:
698 if (i > 2) {
699 alu.src[0].sel = alu.src[1].sel = 248;
700 alu.src[0].chan = alu.src[1].chan = 0;
701 }
702 break;
703 default:
704 break;
705 }
706 if (i == 3) {
707 alu.last = 1;
708 }
709 r = r600_bc_add_alu(ctx->bc, &alu);
710 if (r)
711 return r;
712 }
713 return tgsi_helper_copy(ctx, inst);
714 }
715
716 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
717 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
718 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
719 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
720 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
721 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans},
722 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
723 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
724 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
725 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
726 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
727 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
728 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
729 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
730 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
731 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_slt},
732 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
733 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
734 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
735 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
736 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
737 /* gap */
738 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
739 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
740 /* gap */
741 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
742 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
743 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
744 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
745 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
746 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
747 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
748 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
749 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
750 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
751 /* gap */
752 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
753 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
754 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
755 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
756 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
757 {TGSI_OPCODE_DDX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
758 {TGSI_OPCODE_DDY, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
759 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* predicated kill */
760 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
761 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
762 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
763 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
764 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
765 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
766 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
767 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
768 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
769 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
770 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
771 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
772 {TGSI_OPCODE_TEX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
773 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
774 {TGSI_OPCODE_TXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
775 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
776 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
777 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
778 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
779 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
780 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
781 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
782 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
783 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
784 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
785 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* SGN */
786 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
787 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
788 {TGSI_OPCODE_TXB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
789 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
790 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
791 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
792 {TGSI_OPCODE_TXL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
793 {TGSI_OPCODE_BRK, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
794 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
795 /* gap */
796 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
797 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
798 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
799 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
800 /* gap */
801 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
802 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
803 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
804 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
805 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
806 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
807 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
808 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
809 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
810 /* gap */
811 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
812 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
813 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
814 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
815 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
816 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
817 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
818 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
819 {TGSI_OPCODE_CONT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
820 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
821 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
822 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
823 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
824 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
825 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
826 /* gap */
827 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
828 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
829 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
830 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
831 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
832 /* gap */
833 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
834 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
835 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
836 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
837 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
838 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
839 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
840 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
841 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* conditional kill */
842 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
843 /* gap */
844 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
845 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
846 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
847 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
848 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
849 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
850 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
851 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
852 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
853 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
854 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
855 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
856 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
857 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
858 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
859 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
860 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
861 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
862 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
863 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
864 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
865 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
866 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
867 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
868 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
869 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
870 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
871 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
872 };