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r600g: drop use_mem_constant.
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
37 {
38 struct r600_pipe_state *rstate = &shader->rstate;
39 struct r600_shader *rshader = &shader->shader;
40 unsigned spi_vs_out_id[10];
41 unsigned i, tmp;
42
43 /* clear previous register */
44 rstate->nregs = 0;
45
46 /* so far never got proper semantic id from tgsi */
47 for (i = 0; i < 10; i++) {
48 spi_vs_out_id[i] = 0;
49 }
50 for (i = 0; i < 32; i++) {
51 tmp = i << ((i & 3) * 8);
52 spi_vs_out_id[i / 4] |= tmp;
53 }
54 for (i = 0; i < 10; i++) {
55 r600_pipe_state_add_reg(rstate,
56 R_028614_SPI_VS_OUT_ID_0 + i * 4,
57 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
58 }
59
60 r600_pipe_state_add_reg(rstate,
61 R_0286C4_SPI_VS_OUT_CONFIG,
62 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
63 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate,
65 R_028868_SQ_PGM_RESOURCES_VS,
66 S_028868_NUM_GPRS(rshader->bc.ngpr) |
67 S_028868_STACK_SIZE(rshader->bc.nstack),
68 0xFFFFFFFF, NULL);
69 r600_pipe_state_add_reg(rstate,
70 R_0288A4_SQ_PGM_RESOURCES_FS,
71 0x00000000, 0xFFFFFFFF, NULL);
72 r600_pipe_state_add_reg(rstate,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS,
74 0x00000000, 0xFFFFFFFF, NULL);
75 r600_pipe_state_add_reg(rstate,
76 R_0288DC_SQ_PGM_CF_OFFSET_FS,
77 0x00000000, 0xFFFFFFFF, NULL);
78 r600_pipe_state_add_reg(rstate,
79 R_028858_SQ_PGM_START_VS,
80 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
81 r600_pipe_state_add_reg(rstate,
82 R_028894_SQ_PGM_START_FS,
83 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
84
85 r600_pipe_state_add_reg(rstate,
86 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
87 0xFFFFFFFF, NULL);
88
89 }
90
91 int r600_find_vs_semantic_index(struct r600_shader *vs,
92 struct r600_shader *ps, int id)
93 {
94 struct r600_shader_io *input = &ps->input[id];
95
96 for (int i = 0; i < vs->noutput; i++) {
97 if (input->name == vs->output[i].name &&
98 input->sid == vs->output[i].sid) {
99 return i - 1;
100 }
101 }
102 return 0;
103 }
104
105 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
106 {
107 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
108 struct r600_pipe_state *rstate = &shader->rstate;
109 struct r600_shader *rshader = &shader->shader;
110 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
111 boolean have_pos = FALSE, have_face = FALSE;
112
113 /* clear previous register */
114 rstate->nregs = 0;
115
116 for (i = 0; i < rshader->ninput; i++) {
117 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
118 tmp |= S_028644_SEL_CENTROID(1);
119 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
120 have_pos = TRUE;
121 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
122 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
123 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
124 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
125 }
126 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
127 have_face = TRUE;
128 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
129 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
130 tmp |= S_028644_PT_SPRITE_TEX(1);
131 }
132 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
133 }
134 for (i = 0; i < rshader->noutput; i++) {
135 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
136 r600_pipe_state_add_reg(rstate,
137 R_02880C_DB_SHADER_CONTROL,
138 S_02880C_Z_EXPORT_ENABLE(1),
139 S_02880C_Z_EXPORT_ENABLE(1), NULL);
140 }
141
142 exports_ps = 0;
143 num_cout = 0;
144 for (i = 0; i < rshader->noutput; i++) {
145 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
146 exports_ps |= 1;
147 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
148 num_cout++;
149 }
150 }
151 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
152 if (!exports_ps) {
153 /* always at least export 1 component per pixel */
154 exports_ps = 2;
155 }
156
157 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
158 S_0286CC_PERSP_GRADIENT_ENA(1);
159 spi_input_z = 0;
160 if (have_pos) {
161 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
162 S_0286CC_BARYC_SAMPLE_CNTL(1);
163 spi_input_z |= 1;
164 }
165 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
166 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, S_0286D0_FRONT_FACE_ENA(have_face), 0xFFFFFFFF, NULL);
167 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
168 r600_pipe_state_add_reg(rstate,
169 R_028840_SQ_PGM_START_PS,
170 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
171 r600_pipe_state_add_reg(rstate,
172 R_028850_SQ_PGM_RESOURCES_PS,
173 S_028868_NUM_GPRS(rshader->bc.ngpr) |
174 S_028868_STACK_SIZE(rshader->bc.nstack),
175 0xFFFFFFFF, NULL);
176 r600_pipe_state_add_reg(rstate,
177 R_028854_SQ_PGM_EXPORTS_PS,
178 exports_ps, 0xFFFFFFFF, NULL);
179 r600_pipe_state_add_reg(rstate,
180 R_0288CC_SQ_PGM_CF_OFFSET_PS,
181 0x00000000, 0xFFFFFFFF, NULL);
182
183 if (rshader->uses_kill) {
184 /* only set some bits here, the other bits are set in the dsa state */
185 r600_pipe_state_add_reg(rstate,
186 R_02880C_DB_SHADER_CONTROL,
187 S_02880C_KILL_ENABLE(1),
188 S_02880C_KILL_ENABLE(1), NULL);
189 }
190 r600_pipe_state_add_reg(rstate,
191 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
192 0xFFFFFFFF, NULL);
193 }
194
195 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
196 {
197 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
198 struct r600_shader *rshader = &shader->shader;
199 void *ptr;
200
201 /* copy new shader */
202 if (shader->bo == NULL) {
203 shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
204 if (shader->bo == NULL) {
205 return -ENOMEM;
206 }
207 ptr = r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
208 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
209 r600_bo_unmap(rctx->radeon, shader->bo);
210 }
211 /* build state */
212 rshader->flat_shade = rctx->flatshade;
213 switch (rshader->processor_type) {
214 case TGSI_PROCESSOR_VERTEX:
215 if (rshader->family >= CHIP_CEDAR) {
216 evergreen_pipe_shader_vs(ctx, shader);
217 } else {
218 r600_pipe_shader_vs(ctx, shader);
219 }
220 break;
221 case TGSI_PROCESSOR_FRAGMENT:
222 if (rshader->family >= CHIP_CEDAR) {
223 evergreen_pipe_shader_ps(ctx, shader);
224 } else {
225 r600_pipe_shader_ps(ctx, shader);
226 }
227 break;
228 default:
229 return -EINVAL;
230 }
231 r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
232 return 0;
233 }
234
235 static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rshader)
236 {
237 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
238 struct r600_shader *shader = &rshader->shader;
239 const struct util_format_description *desc;
240 enum pipe_format resource_format[160];
241 unsigned i, nresources = 0;
242 struct r600_bc *bc = &shader->bc;
243 struct r600_bc_cf *cf;
244 struct r600_bc_vtx *vtx;
245
246 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
247 return 0;
248 /* doing a full memcmp fell over the refcount */
249 if ((rshader->vertex_elements.count == rctx->vertex_elements->count) &&
250 (!memcmp(&rshader->vertex_elements.elements, &rctx->vertex_elements->elements, 32 * sizeof(struct pipe_vertex_element)))) {
251 return 0;
252 }
253 rshader->vertex_elements = *rctx->vertex_elements;
254 for (i = 0; i < rctx->vertex_elements->count; i++) {
255 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
256 }
257 r600_bo_reference(rctx->radeon, &rshader->bo, NULL);
258 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
259 switch (cf->inst) {
260 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
261 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
262 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
263 desc = util_format_description(resource_format[vtx->buffer_id]);
264 if (desc == NULL) {
265 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
266 return -EINVAL;
267 }
268 vtx->dst_sel_x = desc->swizzle[0];
269 vtx->dst_sel_y = desc->swizzle[1];
270 vtx->dst_sel_z = desc->swizzle[2];
271 vtx->dst_sel_w = desc->swizzle[3];
272 }
273 break;
274 default:
275 break;
276 }
277 }
278 return r600_bc_build(&shader->bc);
279 }
280
281 int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *shader)
282 {
283 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
284 int r;
285
286 if (shader == NULL)
287 return -EINVAL;
288 /* there should be enough input */
289 if (rctx->vertex_elements->count < shader->shader.bc.nresource) {
290 R600_ERR("%d resources provided, expecting %d\n",
291 rctx->vertex_elements->count, shader->shader.bc.nresource);
292 return -EINVAL;
293 }
294 r = r600_shader_update(ctx, shader);
295 if (r)
296 return r;
297 return r600_pipe_shader(ctx, shader);
298 }
299
300 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
301 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
302 {
303 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
304 int r;
305
306 //fprintf(stderr, "--------------------------------------------------------------\n");
307 //tgsi_dump(tokens, 0);
308 shader->shader.family = r600_get_family(rctx->radeon);
309 r = r600_shader_from_tgsi(tokens, &shader->shader);
310 if (r) {
311 R600_ERR("translation from TGSI failed !\n");
312 return r;
313 }
314 r = r600_bc_build(&shader->shader.bc);
315 if (r) {
316 R600_ERR("building bytecode failed !\n");
317 return r;
318 }
319 //fprintf(stderr, "______________________________________________________________\n");
320 return 0;
321 }
322
323 /*
324 * tgsi -> r600 shader
325 */
326 struct r600_shader_tgsi_instruction;
327
328 struct r600_shader_ctx {
329 struct tgsi_shader_info info;
330 struct tgsi_parse_context parse;
331 const struct tgsi_token *tokens;
332 unsigned type;
333 unsigned file_offset[TGSI_FILE_COUNT];
334 unsigned temp_reg;
335 struct r600_shader_tgsi_instruction *inst_info;
336 struct r600_bc *bc;
337 struct r600_shader *shader;
338 u32 value[4];
339 u32 *literals;
340 u32 nliterals;
341 u32 max_driver_temp_used;
342 };
343
344 struct r600_shader_tgsi_instruction {
345 unsigned tgsi_opcode;
346 unsigned is_op3;
347 unsigned r600_opcode;
348 int (*process)(struct r600_shader_ctx *ctx);
349 };
350
351 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
352 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
353
354 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
355 {
356 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
357 int j;
358
359 if (i->Instruction.NumDstRegs > 1) {
360 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
361 return -EINVAL;
362 }
363 if (i->Instruction.Predicate) {
364 R600_ERR("predicate unsupported\n");
365 return -EINVAL;
366 }
367 #if 0
368 if (i->Instruction.Label) {
369 R600_ERR("label unsupported\n");
370 return -EINVAL;
371 }
372 #endif
373 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
374 if (i->Src[j].Register.Dimension ||
375 i->Src[j].Register.Absolute) {
376 R600_ERR("unsupported src %d (dimension %d|absolute %d)\n", j,
377 i->Src[j].Register.Dimension,
378 i->Src[j].Register.Absolute);
379 return -EINVAL;
380 }
381 }
382 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
383 if (i->Dst[j].Register.Dimension) {
384 R600_ERR("unsupported dst (dimension)\n");
385 return -EINVAL;
386 }
387 }
388 return 0;
389 }
390
391 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int gpr)
392 {
393 int i, r;
394 struct r600_bc_alu alu;
395
396 for (i = 0; i < 8; i++) {
397 memset(&alu, 0, sizeof(struct r600_bc_alu));
398
399 if (i < 4)
400 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
401 else
402 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
403
404 if ((i > 1) && (i < 6)) {
405 alu.dst.sel = ctx->shader->input[gpr].gpr;
406 alu.dst.write = 1;
407 }
408
409 alu.dst.chan = i % 4;
410 alu.src[0].chan = (1 - (i % 2));
411 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + gpr;
412
413 alu.bank_swizzle_force = SQ_ALU_VEC_210;
414 if ((i % 4) == 3)
415 alu.last = 1;
416 r = r600_bc_add_alu(ctx->bc, &alu);
417 if (r)
418 return r;
419 }
420 return 0;
421 }
422
423
424 static int tgsi_declaration(struct r600_shader_ctx *ctx)
425 {
426 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
427 struct r600_bc_vtx vtx;
428 unsigned i;
429 int r;
430
431 switch (d->Declaration.File) {
432 case TGSI_FILE_INPUT:
433 i = ctx->shader->ninput++;
434 ctx->shader->input[i].name = d->Semantic.Name;
435 ctx->shader->input[i].sid = d->Semantic.Index;
436 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
437 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
438 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
439 /* turn input into fetch */
440 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
441 vtx.inst = 0;
442 vtx.fetch_type = 0;
443 vtx.buffer_id = i;
444 /* register containing the index into the buffer */
445 vtx.src_gpr = 0;
446 vtx.src_sel_x = 0;
447 vtx.mega_fetch_count = 0x1F;
448 vtx.dst_gpr = ctx->shader->input[i].gpr;
449 vtx.dst_sel_x = 0;
450 vtx.dst_sel_y = 1;
451 vtx.dst_sel_z = 2;
452 vtx.dst_sel_w = 3;
453 vtx.use_const_fields = 1;
454 r = r600_bc_add_vtx(ctx->bc, &vtx);
455 if (r)
456 return r;
457 }
458 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == 2) {
459 /* turn input into interpolate on EG */
460 evergreen_interp_alu(ctx, i);
461 }
462 break;
463 case TGSI_FILE_OUTPUT:
464 i = ctx->shader->noutput++;
465 ctx->shader->output[i].name = d->Semantic.Name;
466 ctx->shader->output[i].sid = d->Semantic.Index;
467 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
468 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
469 break;
470 case TGSI_FILE_CONSTANT:
471 case TGSI_FILE_TEMPORARY:
472 case TGSI_FILE_SAMPLER:
473 case TGSI_FILE_ADDRESS:
474 break;
475 default:
476 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
477 return -EINVAL;
478 }
479 return 0;
480 }
481
482 static int r600_get_temp(struct r600_shader_ctx *ctx)
483 {
484 return ctx->temp_reg + ctx->max_driver_temp_used++;
485 }
486
487 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
488 {
489 struct tgsi_full_immediate *immediate;
490 struct r600_shader_ctx ctx;
491 struct r600_bc_output output[32];
492 unsigned output_done, noutput;
493 unsigned opcode;
494 int i, r = 0, pos0;
495
496 ctx.bc = &shader->bc;
497 ctx.shader = shader;
498 r = r600_bc_init(ctx.bc, shader->family);
499 if (r)
500 return r;
501 ctx.tokens = tokens;
502 tgsi_scan_shader(tokens, &ctx.info);
503 tgsi_parse_init(&ctx.parse, tokens);
504 ctx.type = ctx.parse.FullHeader.Processor.Processor;
505 shader->processor_type = ctx.type;
506
507 /* register allocations */
508 /* Values [0,127] correspond to GPR[0..127].
509 * Values [128,159] correspond to constant buffer bank 0
510 * Values [160,191] correspond to constant buffer bank 1
511 * Values [256,511] correspond to cfile constants c[0..255].
512 * Other special values are shown in the list below.
513 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
514 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
515 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
516 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
517 * 248 SQ_ALU_SRC_0: special constant 0.0.
518 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
519 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
520 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
521 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
522 * 253 SQ_ALU_SRC_LITERAL: literal constant.
523 * 254 SQ_ALU_SRC_PV: previous vector result.
524 * 255 SQ_ALU_SRC_PS: previous scalar result.
525 */
526 for (i = 0; i < TGSI_FILE_COUNT; i++) {
527 ctx.file_offset[i] = 0;
528 }
529 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
530 ctx.file_offset[TGSI_FILE_INPUT] = 1;
531 }
532 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
533 ctx.info.file_count[TGSI_FILE_INPUT];
534 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
535 ctx.info.file_count[TGSI_FILE_OUTPUT];
536
537 ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
538
539 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
540 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
541 ctx.info.file_count[TGSI_FILE_TEMPORARY];
542
543 ctx.nliterals = 0;
544 ctx.literals = NULL;
545
546 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
547 tgsi_parse_token(&ctx.parse);
548 switch (ctx.parse.FullToken.Token.Type) {
549 case TGSI_TOKEN_TYPE_IMMEDIATE:
550 immediate = &ctx.parse.FullToken.FullImmediate;
551 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
552 if(ctx.literals == NULL) {
553 r = -ENOMEM;
554 goto out_err;
555 }
556 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
557 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
558 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
559 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
560 ctx.nliterals++;
561 break;
562 case TGSI_TOKEN_TYPE_DECLARATION:
563 r = tgsi_declaration(&ctx);
564 if (r)
565 goto out_err;
566 break;
567 case TGSI_TOKEN_TYPE_INSTRUCTION:
568 r = tgsi_is_supported(&ctx);
569 if (r)
570 goto out_err;
571 ctx.max_driver_temp_used = 0;
572 /* reserve first tmp for everyone */
573 r600_get_temp(&ctx);
574 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
575 if (ctx.bc->chiprev == 2)
576 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
577 else
578 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
579 r = ctx.inst_info->process(&ctx);
580 if (r)
581 goto out_err;
582 r = r600_bc_add_literal(ctx.bc, ctx.value);
583 if (r)
584 goto out_err;
585 break;
586 default:
587 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
588 r = -EINVAL;
589 goto out_err;
590 }
591 }
592 /* export output */
593 noutput = shader->noutput;
594 for (i = 0, pos0 = 0; i < noutput; i++) {
595 memset(&output[i], 0, sizeof(struct r600_bc_output));
596 output[i].gpr = shader->output[i].gpr;
597 output[i].elem_size = 3;
598 output[i].swizzle_x = 0;
599 output[i].swizzle_y = 1;
600 output[i].swizzle_z = 2;
601 output[i].swizzle_w = 3;
602 output[i].barrier = 1;
603 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
604 output[i].array_base = i - pos0;
605 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
606 switch (ctx.type) {
607 case TGSI_PROCESSOR_VERTEX:
608 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
609 output[i].array_base = 60;
610 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
611 /* position doesn't count in array_base */
612 pos0++;
613 }
614 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
615 output[i].array_base = 61;
616 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
617 /* position doesn't count in array_base */
618 pos0++;
619 }
620 break;
621 case TGSI_PROCESSOR_FRAGMENT:
622 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
623 output[i].array_base = shader->output[i].sid;
624 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
625 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
626 output[i].array_base = 61;
627 output[i].swizzle_x = 2;
628 output[i].swizzle_y = output[i].swizzle_z = output[i].swizzle_w = 7;
629 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
630 } else {
631 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
632 r = -EINVAL;
633 goto out_err;
634 }
635 break;
636 default:
637 R600_ERR("unsupported processor type %d\n", ctx.type);
638 r = -EINVAL;
639 goto out_err;
640 }
641 }
642 /* add fake param output for vertex shader if no param is exported */
643 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
644 for (i = 0, pos0 = 0; i < noutput; i++) {
645 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
646 pos0 = 1;
647 break;
648 }
649 }
650 if (!pos0) {
651 memset(&output[i], 0, sizeof(struct r600_bc_output));
652 output[i].gpr = 0;
653 output[i].elem_size = 3;
654 output[i].swizzle_x = 0;
655 output[i].swizzle_y = 1;
656 output[i].swizzle_z = 2;
657 output[i].swizzle_w = 3;
658 output[i].barrier = 1;
659 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
660 output[i].array_base = 0;
661 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
662 noutput++;
663 }
664 }
665 /* add fake pixel export */
666 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
667 memset(&output[0], 0, sizeof(struct r600_bc_output));
668 output[0].gpr = 0;
669 output[0].elem_size = 3;
670 output[0].swizzle_x = 7;
671 output[0].swizzle_y = 7;
672 output[0].swizzle_z = 7;
673 output[0].swizzle_w = 7;
674 output[0].barrier = 1;
675 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
676 output[0].array_base = 0;
677 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
678 noutput++;
679 }
680 /* set export done on last export of each type */
681 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
682 if (i == (noutput - 1)) {
683 output[i].end_of_program = 1;
684 }
685 if (!(output_done & (1 << output[i].type))) {
686 output_done |= (1 << output[i].type);
687 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
688 }
689 }
690 /* add output to bytecode */
691 for (i = 0; i < noutput; i++) {
692 r = r600_bc_add_output(ctx.bc, &output[i]);
693 if (r)
694 goto out_err;
695 }
696 free(ctx.literals);
697 tgsi_parse_free(&ctx.parse);
698 return 0;
699 out_err:
700 free(ctx.literals);
701 tgsi_parse_free(&ctx.parse);
702 return r;
703 }
704
705 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
706 {
707 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
708 return -EINVAL;
709 }
710
711 static int tgsi_end(struct r600_shader_ctx *ctx)
712 {
713 return 0;
714 }
715
716 static int tgsi_src(struct r600_shader_ctx *ctx,
717 const struct tgsi_full_src_register *tgsi_src,
718 struct r600_bc_alu_src *r600_src)
719 {
720 int index;
721 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
722 r600_src->sel = tgsi_src->Register.Index;
723 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
724 r600_src->sel = 0;
725 index = tgsi_src->Register.Index;
726 ctx->value[0] = ctx->literals[index * 4 + 0];
727 ctx->value[1] = ctx->literals[index * 4 + 1];
728 ctx->value[2] = ctx->literals[index * 4 + 2];
729 ctx->value[3] = ctx->literals[index * 4 + 3];
730 }
731 if (tgsi_src->Register.Indirect)
732 r600_src->rel = V_SQ_REL_RELATIVE;
733 r600_src->neg = tgsi_src->Register.Negate;
734 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
735 return 0;
736 }
737
738 static int tgsi_dst(struct r600_shader_ctx *ctx,
739 const struct tgsi_full_dst_register *tgsi_dst,
740 unsigned swizzle,
741 struct r600_bc_alu_dst *r600_dst)
742 {
743 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
744
745 r600_dst->sel = tgsi_dst->Register.Index;
746 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
747 r600_dst->chan = swizzle;
748 r600_dst->write = 1;
749 if (tgsi_dst->Register.Indirect)
750 r600_dst->rel = V_SQ_REL_RELATIVE;
751 if (inst->Instruction.Saturate) {
752 r600_dst->clamp = 1;
753 }
754 return 0;
755 }
756
757 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
758 {
759 switch (swizzle) {
760 case 0:
761 return tgsi_src->Register.SwizzleX;
762 case 1:
763 return tgsi_src->Register.SwizzleY;
764 case 2:
765 return tgsi_src->Register.SwizzleZ;
766 case 3:
767 return tgsi_src->Register.SwizzleW;
768 default:
769 return 0;
770 }
771 }
772
773 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
774 {
775 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
776 struct r600_bc_alu alu;
777 int i, j, k, nconst, r;
778
779 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
780 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
781 nconst++;
782 }
783 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
784 if (r) {
785 return r;
786 }
787 }
788 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
789 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
790 int treg = r600_get_temp(ctx);
791 for (k = 0; k < 4; k++) {
792 memset(&alu, 0, sizeof(struct r600_bc_alu));
793 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
794 alu.src[0].sel = r600_src[i].sel;
795 alu.src[0].chan = k;
796 alu.dst.sel = treg;
797 alu.dst.chan = k;
798 alu.dst.write = 1;
799 if (k == 3)
800 alu.last = 1;
801 r = r600_bc_add_alu(ctx->bc, &alu);
802 if (r)
803 return r;
804 }
805 r600_src[i].sel = treg;
806 j--;
807 }
808 }
809 return 0;
810 }
811
812 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
813 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
814 {
815 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
816 struct r600_bc_alu alu;
817 int i, j, k, nliteral, r;
818
819 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
820 if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
821 nliteral++;
822 }
823 }
824 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
825 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
826 int treg = r600_get_temp(ctx);
827 for (k = 0; k < 4; k++) {
828 memset(&alu, 0, sizeof(struct r600_bc_alu));
829 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
830 alu.src[0].sel = r600_src[i].sel;
831 alu.src[0].chan = k;
832 alu.dst.sel = treg;
833 alu.dst.chan = k;
834 alu.dst.write = 1;
835 if (k == 3)
836 alu.last = 1;
837 r = r600_bc_add_alu(ctx->bc, &alu);
838 if (r)
839 return r;
840 }
841 r = r600_bc_add_literal(ctx->bc, &ctx->literals[inst->Src[i].Register.Index * 4]);
842 if (r)
843 return r;
844 r600_src[i].sel = treg;
845 j--;
846 }
847 }
848 return 0;
849 }
850
851 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
852 {
853 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
854 struct r600_bc_alu_src r600_src[3];
855 struct r600_bc_alu alu;
856 int i, j, r;
857 int lasti = 0;
858
859 for (i = 0; i < 4; i++) {
860 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
861 lasti = i;
862 }
863 }
864
865 r = tgsi_split_constant(ctx, r600_src);
866 if (r)
867 return r;
868 r = tgsi_split_literal_constant(ctx, r600_src);
869 if (r)
870 return r;
871 for (i = 0; i < lasti + 1; i++) {
872 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
873 continue;
874
875 memset(&alu, 0, sizeof(struct r600_bc_alu));
876 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
877 if (r)
878 return r;
879
880 alu.inst = ctx->inst_info->r600_opcode;
881 if (!swap) {
882 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
883 alu.src[j] = r600_src[j];
884 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
885 }
886 } else {
887 alu.src[0] = r600_src[1];
888 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
889
890 alu.src[1] = r600_src[0];
891 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
892 }
893 /* handle some special cases */
894 switch (ctx->inst_info->tgsi_opcode) {
895 case TGSI_OPCODE_SUB:
896 alu.src[1].neg = 1;
897 break;
898 case TGSI_OPCODE_ABS:
899 alu.src[0].abs = 1;
900 break;
901 default:
902 break;
903 }
904 if (i == lasti) {
905 alu.last = 1;
906 }
907 r = r600_bc_add_alu(ctx->bc, &alu);
908 if (r)
909 return r;
910 }
911 return 0;
912 }
913
914 static int tgsi_op2(struct r600_shader_ctx *ctx)
915 {
916 return tgsi_op2_s(ctx, 0);
917 }
918
919 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
920 {
921 return tgsi_op2_s(ctx, 1);
922 }
923
924 /*
925 * r600 - trunc to -PI..PI range
926 * r700 - normalize by dividing by 2PI
927 * see fdo bug 27901
928 */
929 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
930 struct r600_bc_alu_src r600_src[3])
931 {
932 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
933 int r;
934 uint32_t lit_vals[4];
935 struct r600_bc_alu alu;
936
937 memset(lit_vals, 0, 4*4);
938 r = tgsi_split_constant(ctx, r600_src);
939 if (r)
940 return r;
941 r = tgsi_split_literal_constant(ctx, r600_src);
942 if (r)
943 return r;
944
945 r = tgsi_split_literal_constant(ctx, r600_src);
946 if (r)
947 return r;
948
949 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
950 lit_vals[1] = fui(0.5f);
951
952 memset(&alu, 0, sizeof(struct r600_bc_alu));
953 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
954 alu.is_op3 = 1;
955
956 alu.dst.chan = 0;
957 alu.dst.sel = ctx->temp_reg;
958 alu.dst.write = 1;
959
960 alu.src[0] = r600_src[0];
961 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
962
963 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
964 alu.src[1].chan = 0;
965 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
966 alu.src[2].chan = 1;
967 alu.last = 1;
968 r = r600_bc_add_alu(ctx->bc, &alu);
969 if (r)
970 return r;
971 r = r600_bc_add_literal(ctx->bc, lit_vals);
972 if (r)
973 return r;
974
975 memset(&alu, 0, sizeof(struct r600_bc_alu));
976 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
977
978 alu.dst.chan = 0;
979 alu.dst.sel = ctx->temp_reg;
980 alu.dst.write = 1;
981
982 alu.src[0].sel = ctx->temp_reg;
983 alu.src[0].chan = 0;
984 alu.last = 1;
985 r = r600_bc_add_alu(ctx->bc, &alu);
986 if (r)
987 return r;
988
989 if (ctx->bc->chiprev == 0) {
990 lit_vals[0] = fui(3.1415926535897f * 2.0f);
991 lit_vals[1] = fui(-3.1415926535897f);
992 } else {
993 lit_vals[0] = fui(1.0f);
994 lit_vals[1] = fui(-0.5f);
995 }
996
997 memset(&alu, 0, sizeof(struct r600_bc_alu));
998 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
999 alu.is_op3 = 1;
1000
1001 alu.dst.chan = 0;
1002 alu.dst.sel = ctx->temp_reg;
1003 alu.dst.write = 1;
1004
1005 alu.src[0].sel = ctx->temp_reg;
1006 alu.src[0].chan = 0;
1007
1008 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1009 alu.src[1].chan = 0;
1010 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1011 alu.src[2].chan = 1;
1012 alu.last = 1;
1013 r = r600_bc_add_alu(ctx->bc, &alu);
1014 if (r)
1015 return r;
1016 r = r600_bc_add_literal(ctx->bc, lit_vals);
1017 if (r)
1018 return r;
1019 return 0;
1020 }
1021
1022 static int tgsi_trig(struct r600_shader_ctx *ctx)
1023 {
1024 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1025 struct r600_bc_alu_src r600_src[3];
1026 struct r600_bc_alu alu;
1027 int i, r;
1028 int lasti = 0;
1029
1030 r = tgsi_setup_trig(ctx, r600_src);
1031 if (r)
1032 return r;
1033
1034 memset(&alu, 0, sizeof(struct r600_bc_alu));
1035 alu.inst = ctx->inst_info->r600_opcode;
1036 alu.dst.chan = 0;
1037 alu.dst.sel = ctx->temp_reg;
1038 alu.dst.write = 1;
1039
1040 alu.src[0].sel = ctx->temp_reg;
1041 alu.src[0].chan = 0;
1042 alu.last = 1;
1043 r = r600_bc_add_alu(ctx->bc, &alu);
1044 if (r)
1045 return r;
1046
1047 /* replicate result */
1048 for (i = 0; i < 4; i++) {
1049 if (inst->Dst[0].Register.WriteMask & (1 << i))
1050 lasti = i;
1051 }
1052 for (i = 0; i < lasti + 1; i++) {
1053 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1054 continue;
1055
1056 memset(&alu, 0, sizeof(struct r600_bc_alu));
1057 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1058
1059 alu.src[0].sel = ctx->temp_reg;
1060 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1061 if (r)
1062 return r;
1063 if (i == lasti)
1064 alu.last = 1;
1065 r = r600_bc_add_alu(ctx->bc, &alu);
1066 if (r)
1067 return r;
1068 }
1069 return 0;
1070 }
1071
1072 static int tgsi_scs(struct r600_shader_ctx *ctx)
1073 {
1074 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1075 struct r600_bc_alu_src r600_src[3];
1076 struct r600_bc_alu alu;
1077 int r;
1078
1079 /* We'll only need the trig stuff if we are going to write to the
1080 * X or Y components of the destination vector.
1081 */
1082 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1083 r = tgsi_setup_trig(ctx, r600_src);
1084 if (r)
1085 return r;
1086 }
1087
1088 /* dst.x = COS */
1089 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1090 memset(&alu, 0, sizeof(struct r600_bc_alu));
1091 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1092 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1093 if (r)
1094 return r;
1095
1096 alu.src[0].sel = ctx->temp_reg;
1097 alu.src[0].chan = 0;
1098 alu.last = 1;
1099 r = r600_bc_add_alu(ctx->bc, &alu);
1100 if (r)
1101 return r;
1102 }
1103
1104 /* dst.y = SIN */
1105 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1106 memset(&alu, 0, sizeof(struct r600_bc_alu));
1107 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1108 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1109 if (r)
1110 return r;
1111
1112 alu.src[0].sel = ctx->temp_reg;
1113 alu.src[0].chan = 0;
1114 alu.last = 1;
1115 r = r600_bc_add_alu(ctx->bc, &alu);
1116 if (r)
1117 return r;
1118 }
1119
1120 /* dst.z = 0.0; */
1121 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1122 memset(&alu, 0, sizeof(struct r600_bc_alu));
1123
1124 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1125
1126 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1127 if (r)
1128 return r;
1129
1130 alu.src[0].sel = V_SQ_ALU_SRC_0;
1131 alu.src[0].chan = 0;
1132
1133 alu.last = 1;
1134
1135 r = r600_bc_add_alu(ctx->bc, &alu);
1136 if (r)
1137 return r;
1138
1139 r = r600_bc_add_literal(ctx->bc, ctx->value);
1140 if (r)
1141 return r;
1142 }
1143
1144 /* dst.w = 1.0; */
1145 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1146 memset(&alu, 0, sizeof(struct r600_bc_alu));
1147
1148 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1149
1150 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1151 if (r)
1152 return r;
1153
1154 alu.src[0].sel = V_SQ_ALU_SRC_1;
1155 alu.src[0].chan = 0;
1156
1157 alu.last = 1;
1158
1159 r = r600_bc_add_alu(ctx->bc, &alu);
1160 if (r)
1161 return r;
1162
1163 r = r600_bc_add_literal(ctx->bc, ctx->value);
1164 if (r)
1165 return r;
1166 }
1167
1168 return 0;
1169 }
1170
1171 static int tgsi_kill(struct r600_shader_ctx *ctx)
1172 {
1173 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1174 struct r600_bc_alu alu;
1175 int i, r;
1176
1177 for (i = 0; i < 4; i++) {
1178 memset(&alu, 0, sizeof(struct r600_bc_alu));
1179 alu.inst = ctx->inst_info->r600_opcode;
1180
1181 alu.dst.chan = i;
1182
1183 alu.src[0].sel = V_SQ_ALU_SRC_0;
1184
1185 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1186 alu.src[1].sel = V_SQ_ALU_SRC_1;
1187 alu.src[1].neg = 1;
1188 } else {
1189 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1190 if (r)
1191 return r;
1192 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1193 }
1194 if (i == 3) {
1195 alu.last = 1;
1196 }
1197 r = r600_bc_add_alu(ctx->bc, &alu);
1198 if (r)
1199 return r;
1200 }
1201 r = r600_bc_add_literal(ctx->bc, ctx->value);
1202 if (r)
1203 return r;
1204
1205 /* kill must be last in ALU */
1206 ctx->bc->force_add_cf = 1;
1207 ctx->shader->uses_kill = TRUE;
1208 return 0;
1209 }
1210
1211 static int tgsi_lit(struct r600_shader_ctx *ctx)
1212 {
1213 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1214 struct r600_bc_alu alu;
1215 struct r600_bc_alu_src r600_src[3];
1216 int r;
1217
1218 r = tgsi_split_constant(ctx, r600_src);
1219 if (r)
1220 return r;
1221 r = tgsi_split_literal_constant(ctx, r600_src);
1222 if (r)
1223 return r;
1224
1225 /* dst.x, <- 1.0 */
1226 memset(&alu, 0, sizeof(struct r600_bc_alu));
1227 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1228 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1229 alu.src[0].chan = 0;
1230 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1231 if (r)
1232 return r;
1233 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1234 r = r600_bc_add_alu(ctx->bc, &alu);
1235 if (r)
1236 return r;
1237
1238 /* dst.y = max(src.x, 0.0) */
1239 memset(&alu, 0, sizeof(struct r600_bc_alu));
1240 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1241 alu.src[0] = r600_src[0];
1242 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1243 alu.src[1].chan = 0;
1244 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1245 if (r)
1246 return r;
1247 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1248 r = r600_bc_add_alu(ctx->bc, &alu);
1249 if (r)
1250 return r;
1251
1252 /* dst.w, <- 1.0 */
1253 memset(&alu, 0, sizeof(struct r600_bc_alu));
1254 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1255 alu.src[0].sel = V_SQ_ALU_SRC_1;
1256 alu.src[0].chan = 0;
1257 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1258 if (r)
1259 return r;
1260 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1261 alu.last = 1;
1262 r = r600_bc_add_alu(ctx->bc, &alu);
1263 if (r)
1264 return r;
1265
1266 r = r600_bc_add_literal(ctx->bc, ctx->value);
1267 if (r)
1268 return r;
1269
1270 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1271 {
1272 int chan;
1273 int sel;
1274
1275 /* dst.z = log(src.y) */
1276 memset(&alu, 0, sizeof(struct r600_bc_alu));
1277 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1278 alu.src[0] = r600_src[0];
1279 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1280 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1281 if (r)
1282 return r;
1283 alu.last = 1;
1284 r = r600_bc_add_alu(ctx->bc, &alu);
1285 if (r)
1286 return r;
1287
1288 r = r600_bc_add_literal(ctx->bc, ctx->value);
1289 if (r)
1290 return r;
1291
1292 chan = alu.dst.chan;
1293 sel = alu.dst.sel;
1294
1295 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1296 memset(&alu, 0, sizeof(struct r600_bc_alu));
1297 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1298 alu.src[0] = r600_src[0];
1299 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1300 alu.src[1].sel = sel;
1301 alu.src[1].chan = chan;
1302
1303 alu.src[2] = r600_src[0];
1304 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1305 alu.dst.sel = ctx->temp_reg;
1306 alu.dst.chan = 0;
1307 alu.dst.write = 1;
1308 alu.is_op3 = 1;
1309 alu.last = 1;
1310 r = r600_bc_add_alu(ctx->bc, &alu);
1311 if (r)
1312 return r;
1313
1314 r = r600_bc_add_literal(ctx->bc, ctx->value);
1315 if (r)
1316 return r;
1317 /* dst.z = exp(tmp.x) */
1318 memset(&alu, 0, sizeof(struct r600_bc_alu));
1319 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1320 alu.src[0].sel = ctx->temp_reg;
1321 alu.src[0].chan = 0;
1322 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1323 if (r)
1324 return r;
1325 alu.last = 1;
1326 r = r600_bc_add_alu(ctx->bc, &alu);
1327 if (r)
1328 return r;
1329 }
1330 return 0;
1331 }
1332
1333 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1334 {
1335 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1336 struct r600_bc_alu alu;
1337 int i, r;
1338
1339 memset(&alu, 0, sizeof(struct r600_bc_alu));
1340
1341 /* FIXME:
1342 * For state trackers other than OpenGL, we'll want to use
1343 * _RECIPSQRT_IEEE instead.
1344 */
1345 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1346
1347 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1348 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1349 if (r)
1350 return r;
1351 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1352 alu.src[i].abs = 1;
1353 }
1354 alu.dst.sel = ctx->temp_reg;
1355 alu.dst.write = 1;
1356 alu.last = 1;
1357 r = r600_bc_add_alu(ctx->bc, &alu);
1358 if (r)
1359 return r;
1360 r = r600_bc_add_literal(ctx->bc, ctx->value);
1361 if (r)
1362 return r;
1363 /* replicate result */
1364 return tgsi_helper_tempx_replicate(ctx);
1365 }
1366
1367 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1368 {
1369 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1370 struct r600_bc_alu alu;
1371 int i, r;
1372
1373 for (i = 0; i < 4; i++) {
1374 memset(&alu, 0, sizeof(struct r600_bc_alu));
1375 alu.src[0].sel = ctx->temp_reg;
1376 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1377 alu.dst.chan = i;
1378 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1379 if (r)
1380 return r;
1381 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1382 if (i == 3)
1383 alu.last = 1;
1384 r = r600_bc_add_alu(ctx->bc, &alu);
1385 if (r)
1386 return r;
1387 }
1388 return 0;
1389 }
1390
1391 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1392 {
1393 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1394 struct r600_bc_alu alu;
1395 int i, r;
1396
1397 memset(&alu, 0, sizeof(struct r600_bc_alu));
1398 alu.inst = ctx->inst_info->r600_opcode;
1399 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1400 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1401 if (r)
1402 return r;
1403 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1404 }
1405 alu.dst.sel = ctx->temp_reg;
1406 alu.dst.write = 1;
1407 alu.last = 1;
1408 r = r600_bc_add_alu(ctx->bc, &alu);
1409 if (r)
1410 return r;
1411 r = r600_bc_add_literal(ctx->bc, ctx->value);
1412 if (r)
1413 return r;
1414 /* replicate result */
1415 return tgsi_helper_tempx_replicate(ctx);
1416 }
1417
1418 static int tgsi_pow(struct r600_shader_ctx *ctx)
1419 {
1420 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1421 struct r600_bc_alu alu;
1422 int r;
1423
1424 /* LOG2(a) */
1425 memset(&alu, 0, sizeof(struct r600_bc_alu));
1426 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1427 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1428 if (r)
1429 return r;
1430 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1431 alu.dst.sel = ctx->temp_reg;
1432 alu.dst.write = 1;
1433 alu.last = 1;
1434 r = r600_bc_add_alu(ctx->bc, &alu);
1435 if (r)
1436 return r;
1437 r = r600_bc_add_literal(ctx->bc,ctx->value);
1438 if (r)
1439 return r;
1440 /* b * LOG2(a) */
1441 memset(&alu, 0, sizeof(struct r600_bc_alu));
1442 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE);
1443 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1444 if (r)
1445 return r;
1446 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1447 alu.src[1].sel = ctx->temp_reg;
1448 alu.dst.sel = ctx->temp_reg;
1449 alu.dst.write = 1;
1450 alu.last = 1;
1451 r = r600_bc_add_alu(ctx->bc, &alu);
1452 if (r)
1453 return r;
1454 r = r600_bc_add_literal(ctx->bc,ctx->value);
1455 if (r)
1456 return r;
1457 /* POW(a,b) = EXP2(b * LOG2(a))*/
1458 memset(&alu, 0, sizeof(struct r600_bc_alu));
1459 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1460 alu.src[0].sel = ctx->temp_reg;
1461 alu.dst.sel = ctx->temp_reg;
1462 alu.dst.write = 1;
1463 alu.last = 1;
1464 r = r600_bc_add_alu(ctx->bc, &alu);
1465 if (r)
1466 return r;
1467 r = r600_bc_add_literal(ctx->bc,ctx->value);
1468 if (r)
1469 return r;
1470 return tgsi_helper_tempx_replicate(ctx);
1471 }
1472
1473 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1474 {
1475 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1476 struct r600_bc_alu alu;
1477 struct r600_bc_alu_src r600_src[3];
1478 int i, r;
1479
1480 r = tgsi_split_constant(ctx, r600_src);
1481 if (r)
1482 return r;
1483 r = tgsi_split_literal_constant(ctx, r600_src);
1484 if (r)
1485 return r;
1486
1487 /* tmp = (src > 0 ? 1 : src) */
1488 for (i = 0; i < 4; i++) {
1489 memset(&alu, 0, sizeof(struct r600_bc_alu));
1490 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1491 alu.is_op3 = 1;
1492
1493 alu.dst.sel = ctx->temp_reg;
1494 alu.dst.chan = i;
1495
1496 alu.src[0] = r600_src[0];
1497 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1498
1499 alu.src[1].sel = V_SQ_ALU_SRC_1;
1500
1501 alu.src[2] = r600_src[0];
1502 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1503 if (i == 3)
1504 alu.last = 1;
1505 r = r600_bc_add_alu(ctx->bc, &alu);
1506 if (r)
1507 return r;
1508 }
1509 r = r600_bc_add_literal(ctx->bc, ctx->value);
1510 if (r)
1511 return r;
1512
1513 /* dst = (-tmp > 0 ? -1 : tmp) */
1514 for (i = 0; i < 4; i++) {
1515 memset(&alu, 0, sizeof(struct r600_bc_alu));
1516 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1517 alu.is_op3 = 1;
1518 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1519 if (r)
1520 return r;
1521
1522 alu.src[0].sel = ctx->temp_reg;
1523 alu.src[0].chan = i;
1524 alu.src[0].neg = 1;
1525
1526 alu.src[1].sel = V_SQ_ALU_SRC_1;
1527 alu.src[1].neg = 1;
1528
1529 alu.src[2].sel = ctx->temp_reg;
1530 alu.src[2].chan = i;
1531
1532 if (i == 3)
1533 alu.last = 1;
1534 r = r600_bc_add_alu(ctx->bc, &alu);
1535 if (r)
1536 return r;
1537 }
1538 return 0;
1539 }
1540
1541 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1542 {
1543 struct r600_bc_alu alu;
1544 int i, r;
1545
1546 r = r600_bc_add_literal(ctx->bc, ctx->value);
1547 if (r)
1548 return r;
1549 for (i = 0; i < 4; i++) {
1550 memset(&alu, 0, sizeof(struct r600_bc_alu));
1551 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1552 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1553 alu.dst.chan = i;
1554 } else {
1555 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1556 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1557 if (r)
1558 return r;
1559 alu.src[0].sel = ctx->temp_reg;
1560 alu.src[0].chan = i;
1561 }
1562 if (i == 3) {
1563 alu.last = 1;
1564 }
1565 r = r600_bc_add_alu(ctx->bc, &alu);
1566 if (r)
1567 return r;
1568 }
1569 return 0;
1570 }
1571
1572 static int tgsi_op3(struct r600_shader_ctx *ctx)
1573 {
1574 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1575 struct r600_bc_alu_src r600_src[3];
1576 struct r600_bc_alu alu;
1577 int i, j, r;
1578
1579 r = tgsi_split_constant(ctx, r600_src);
1580 if (r)
1581 return r;
1582 r = tgsi_split_literal_constant(ctx, r600_src);
1583 if (r)
1584 return r;
1585 /* do it in 2 step as op3 doesn't support writemask */
1586 for (i = 0; i < 4; i++) {
1587 memset(&alu, 0, sizeof(struct r600_bc_alu));
1588 alu.inst = ctx->inst_info->r600_opcode;
1589 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1590 alu.src[j] = r600_src[j];
1591 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1592 }
1593 alu.dst.sel = ctx->temp_reg;
1594 alu.dst.chan = i;
1595 alu.dst.write = 1;
1596 alu.is_op3 = 1;
1597 if (i == 3) {
1598 alu.last = 1;
1599 }
1600 r = r600_bc_add_alu(ctx->bc, &alu);
1601 if (r)
1602 return r;
1603 }
1604 return tgsi_helper_copy(ctx, inst);
1605 }
1606
1607 static int tgsi_dp(struct r600_shader_ctx *ctx)
1608 {
1609 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1610 struct r600_bc_alu_src r600_src[3];
1611 struct r600_bc_alu alu;
1612 int i, j, r;
1613
1614 r = tgsi_split_constant(ctx, r600_src);
1615 if (r)
1616 return r;
1617 r = tgsi_split_literal_constant(ctx, r600_src);
1618 if (r)
1619 return r;
1620 for (i = 0; i < 4; i++) {
1621 memset(&alu, 0, sizeof(struct r600_bc_alu));
1622 alu.inst = ctx->inst_info->r600_opcode;
1623 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1624 alu.src[j] = r600_src[j];
1625 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1626 }
1627 alu.dst.sel = ctx->temp_reg;
1628 alu.dst.chan = i;
1629 alu.dst.write = 1;
1630 /* handle some special cases */
1631 switch (ctx->inst_info->tgsi_opcode) {
1632 case TGSI_OPCODE_DP2:
1633 if (i > 1) {
1634 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1635 alu.src[0].chan = alu.src[1].chan = 0;
1636 }
1637 break;
1638 case TGSI_OPCODE_DP3:
1639 if (i > 2) {
1640 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1641 alu.src[0].chan = alu.src[1].chan = 0;
1642 }
1643 break;
1644 case TGSI_OPCODE_DPH:
1645 if (i == 3) {
1646 alu.src[0].sel = V_SQ_ALU_SRC_1;
1647 alu.src[0].chan = 0;
1648 alu.src[0].neg = 0;
1649 }
1650 break;
1651 default:
1652 break;
1653 }
1654 if (i == 3) {
1655 alu.last = 1;
1656 }
1657 r = r600_bc_add_alu(ctx->bc, &alu);
1658 if (r)
1659 return r;
1660 }
1661 return tgsi_helper_copy(ctx, inst);
1662 }
1663
1664 static int tgsi_tex(struct r600_shader_ctx *ctx)
1665 {
1666 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1667 struct r600_bc_tex tex;
1668 struct r600_bc_alu alu;
1669 unsigned src_gpr;
1670 int r, i;
1671 int opcode;
1672 boolean src_not_temp = inst->Src[0].Register.File != TGSI_FILE_TEMPORARY;
1673 uint32_t lit_vals[4];
1674
1675 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1676
1677 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1678 /* Add perspective divide */
1679 memset(&alu, 0, sizeof(struct r600_bc_alu));
1680 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1681 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1682 if (r)
1683 return r;
1684
1685 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1686 alu.dst.sel = ctx->temp_reg;
1687 alu.dst.chan = 3;
1688 alu.last = 1;
1689 alu.dst.write = 1;
1690 r = r600_bc_add_alu(ctx->bc, &alu);
1691 if (r)
1692 return r;
1693
1694 for (i = 0; i < 3; i++) {
1695 memset(&alu, 0, sizeof(struct r600_bc_alu));
1696 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1697 alu.src[0].sel = ctx->temp_reg;
1698 alu.src[0].chan = 3;
1699 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1700 if (r)
1701 return r;
1702 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1703 alu.dst.sel = ctx->temp_reg;
1704 alu.dst.chan = i;
1705 alu.dst.write = 1;
1706 r = r600_bc_add_alu(ctx->bc, &alu);
1707 if (r)
1708 return r;
1709 }
1710 memset(&alu, 0, sizeof(struct r600_bc_alu));
1711 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1712 alu.src[0].sel = V_SQ_ALU_SRC_1;
1713 alu.src[0].chan = 0;
1714 alu.dst.sel = ctx->temp_reg;
1715 alu.dst.chan = 3;
1716 alu.last = 1;
1717 alu.dst.write = 1;
1718 r = r600_bc_add_alu(ctx->bc, &alu);
1719 if (r)
1720 return r;
1721 src_not_temp = FALSE;
1722 src_gpr = ctx->temp_reg;
1723 }
1724
1725 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1726 int src_chan, src2_chan;
1727
1728 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1729 for (i = 0; i < 4; i++) {
1730 memset(&alu, 0, sizeof(struct r600_bc_alu));
1731 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1732 switch (i) {
1733 case 0:
1734 src_chan = 2;
1735 src2_chan = 1;
1736 break;
1737 case 1:
1738 src_chan = 2;
1739 src2_chan = 0;
1740 break;
1741 case 2:
1742 src_chan = 0;
1743 src2_chan = 2;
1744 break;
1745 case 3:
1746 src_chan = 1;
1747 src2_chan = 2;
1748 break;
1749 default:
1750 assert(0);
1751 src_chan = 0;
1752 src2_chan = 0;
1753 break;
1754 }
1755 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1756 if (r)
1757 return r;
1758 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1759 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1760 if (r)
1761 return r;
1762 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1763 alu.dst.sel = ctx->temp_reg;
1764 alu.dst.chan = i;
1765 if (i == 3)
1766 alu.last = 1;
1767 alu.dst.write = 1;
1768 r = r600_bc_add_alu(ctx->bc, &alu);
1769 if (r)
1770 return r;
1771 }
1772
1773 /* tmp1.z = RCP_e(|tmp1.z|) */
1774 memset(&alu, 0, sizeof(struct r600_bc_alu));
1775 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1776 alu.src[0].sel = ctx->temp_reg;
1777 alu.src[0].chan = 2;
1778 alu.src[0].abs = 1;
1779 alu.dst.sel = ctx->temp_reg;
1780 alu.dst.chan = 2;
1781 alu.dst.write = 1;
1782 alu.last = 1;
1783 r = r600_bc_add_alu(ctx->bc, &alu);
1784 if (r)
1785 return r;
1786
1787 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1788 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1789 * muladd has no writemask, have to use another temp
1790 */
1791 memset(&alu, 0, sizeof(struct r600_bc_alu));
1792 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1793 alu.is_op3 = 1;
1794
1795 alu.src[0].sel = ctx->temp_reg;
1796 alu.src[0].chan = 0;
1797 alu.src[1].sel = ctx->temp_reg;
1798 alu.src[1].chan = 2;
1799
1800 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1801 alu.src[2].chan = 0;
1802
1803 alu.dst.sel = ctx->temp_reg;
1804 alu.dst.chan = 0;
1805 alu.dst.write = 1;
1806
1807 r = r600_bc_add_alu(ctx->bc, &alu);
1808 if (r)
1809 return r;
1810
1811 memset(&alu, 0, sizeof(struct r600_bc_alu));
1812 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1813 alu.is_op3 = 1;
1814
1815 alu.src[0].sel = ctx->temp_reg;
1816 alu.src[0].chan = 1;
1817 alu.src[1].sel = ctx->temp_reg;
1818 alu.src[1].chan = 2;
1819
1820 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1821 alu.src[2].chan = 0;
1822
1823 alu.dst.sel = ctx->temp_reg;
1824 alu.dst.chan = 1;
1825 alu.dst.write = 1;
1826
1827 alu.last = 1;
1828 r = r600_bc_add_alu(ctx->bc, &alu);
1829 if (r)
1830 return r;
1831
1832 lit_vals[0] = fui(1.5f);
1833
1834 r = r600_bc_add_literal(ctx->bc, lit_vals);
1835 if (r)
1836 return r;
1837 src_not_temp = FALSE;
1838 src_gpr = ctx->temp_reg;
1839 }
1840
1841 if (src_not_temp) {
1842 for (i = 0; i < 4; i++) {
1843 memset(&alu, 0, sizeof(struct r600_bc_alu));
1844 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1845 alu.src[0].sel = src_gpr;
1846 alu.src[0].chan = i;
1847 alu.dst.sel = ctx->temp_reg;
1848 alu.dst.chan = i;
1849 if (i == 3)
1850 alu.last = 1;
1851 alu.dst.write = 1;
1852 r = r600_bc_add_alu(ctx->bc, &alu);
1853 if (r)
1854 return r;
1855 }
1856 src_gpr = ctx->temp_reg;
1857 }
1858
1859 opcode = ctx->inst_info->r600_opcode;
1860 if (opcode == SQ_TEX_INST_SAMPLE &&
1861 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1862 opcode = SQ_TEX_INST_SAMPLE_C;
1863
1864 memset(&tex, 0, sizeof(struct r600_bc_tex));
1865 tex.inst = opcode;
1866 tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1867 tex.sampler_id = tex.resource_id;
1868 tex.src_gpr = src_gpr;
1869 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1870 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
1871 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
1872 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
1873 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
1874 tex.src_sel_x = 0;
1875 tex.src_sel_y = 1;
1876 tex.src_sel_z = 2;
1877 tex.src_sel_w = 3;
1878
1879 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1880 tex.src_sel_x = 1;
1881 tex.src_sel_y = 0;
1882 tex.src_sel_z = 3;
1883 tex.src_sel_w = 1;
1884 }
1885
1886 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1887 tex.coord_type_x = 1;
1888 tex.coord_type_y = 1;
1889 tex.coord_type_z = 1;
1890 tex.coord_type_w = 1;
1891 }
1892
1893 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1894 tex.src_sel_w = 2;
1895
1896 r = r600_bc_add_tex(ctx->bc, &tex);
1897 if (r)
1898 return r;
1899
1900 /* add shadow ambient support - gallium doesn't do it yet */
1901 return 0;
1902
1903 }
1904
1905 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1906 {
1907 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1908 struct r600_bc_alu_src r600_src[3];
1909 struct r600_bc_alu alu;
1910 unsigned i;
1911 int r;
1912
1913 r = tgsi_split_constant(ctx, r600_src);
1914 if (r)
1915 return r;
1916 r = tgsi_split_literal_constant(ctx, r600_src);
1917 if (r)
1918 return r;
1919 /* 1 - src0 */
1920 for (i = 0; i < 4; i++) {
1921 memset(&alu, 0, sizeof(struct r600_bc_alu));
1922 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1923 alu.src[0].sel = V_SQ_ALU_SRC_1;
1924 alu.src[0].chan = 0;
1925 alu.src[1] = r600_src[0];
1926 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1927 alu.src[1].neg = 1;
1928 alu.dst.sel = ctx->temp_reg;
1929 alu.dst.chan = i;
1930 if (i == 3) {
1931 alu.last = 1;
1932 }
1933 alu.dst.write = 1;
1934 r = r600_bc_add_alu(ctx->bc, &alu);
1935 if (r)
1936 return r;
1937 }
1938 r = r600_bc_add_literal(ctx->bc, ctx->value);
1939 if (r)
1940 return r;
1941
1942 /* (1 - src0) * src2 */
1943 for (i = 0; i < 4; i++) {
1944 memset(&alu, 0, sizeof(struct r600_bc_alu));
1945 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1946 alu.src[0].sel = ctx->temp_reg;
1947 alu.src[0].chan = i;
1948 alu.src[1] = r600_src[2];
1949 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1950 alu.dst.sel = ctx->temp_reg;
1951 alu.dst.chan = i;
1952 if (i == 3) {
1953 alu.last = 1;
1954 }
1955 alu.dst.write = 1;
1956 r = r600_bc_add_alu(ctx->bc, &alu);
1957 if (r)
1958 return r;
1959 }
1960 r = r600_bc_add_literal(ctx->bc, ctx->value);
1961 if (r)
1962 return r;
1963
1964 /* src0 * src1 + (1 - src0) * src2 */
1965 for (i = 0; i < 4; i++) {
1966 memset(&alu, 0, sizeof(struct r600_bc_alu));
1967 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1968 alu.is_op3 = 1;
1969 alu.src[0] = r600_src[0];
1970 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1971 alu.src[1] = r600_src[1];
1972 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1973 alu.src[2].sel = ctx->temp_reg;
1974 alu.src[2].chan = i;
1975 alu.dst.sel = ctx->temp_reg;
1976 alu.dst.chan = i;
1977 if (i == 3) {
1978 alu.last = 1;
1979 }
1980 r = r600_bc_add_alu(ctx->bc, &alu);
1981 if (r)
1982 return r;
1983 }
1984 return tgsi_helper_copy(ctx, inst);
1985 }
1986
1987 static int tgsi_cmp(struct r600_shader_ctx *ctx)
1988 {
1989 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1990 struct r600_bc_alu_src r600_src[3];
1991 struct r600_bc_alu alu;
1992 int use_temp = 0;
1993 int i, r;
1994
1995 r = tgsi_split_constant(ctx, r600_src);
1996 if (r)
1997 return r;
1998 r = tgsi_split_literal_constant(ctx, r600_src);
1999 if (r)
2000 return r;
2001
2002 if (inst->Dst[0].Register.WriteMask != 0xf)
2003 use_temp = 1;
2004
2005 for (i = 0; i < 4; i++) {
2006 memset(&alu, 0, sizeof(struct r600_bc_alu));
2007 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
2008 alu.src[0] = r600_src[0];
2009 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2010
2011 alu.src[1] = r600_src[2];
2012 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
2013
2014 alu.src[2] = r600_src[1];
2015 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
2016
2017 if (use_temp)
2018 alu.dst.sel = ctx->temp_reg;
2019 else {
2020 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2021 if (r)
2022 return r;
2023 }
2024 alu.dst.chan = i;
2025 alu.dst.write = 1;
2026 alu.is_op3 = 1;
2027 if (i == 3)
2028 alu.last = 1;
2029 r = r600_bc_add_alu(ctx->bc, &alu);
2030 if (r)
2031 return r;
2032 }
2033 if (use_temp)
2034 return tgsi_helper_copy(ctx, inst);
2035 return 0;
2036 }
2037
2038 static int tgsi_xpd(struct r600_shader_ctx *ctx)
2039 {
2040 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2041 struct r600_bc_alu_src r600_src[3];
2042 struct r600_bc_alu alu;
2043 uint32_t use_temp = 0;
2044 int i, r;
2045
2046 if (inst->Dst[0].Register.WriteMask != 0xf)
2047 use_temp = 1;
2048
2049 r = tgsi_split_constant(ctx, r600_src);
2050 if (r)
2051 return r;
2052 r = tgsi_split_literal_constant(ctx, r600_src);
2053 if (r)
2054 return r;
2055
2056 for (i = 0; i < 4; i++) {
2057 memset(&alu, 0, sizeof(struct r600_bc_alu));
2058 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2059
2060 alu.src[0] = r600_src[0];
2061 switch (i) {
2062 case 0:
2063 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2064 break;
2065 case 1:
2066 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2067 break;
2068 case 2:
2069 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2070 break;
2071 case 3:
2072 alu.src[0].sel = V_SQ_ALU_SRC_0;
2073 alu.src[0].chan = i;
2074 }
2075
2076 alu.src[1] = r600_src[1];
2077 switch (i) {
2078 case 0:
2079 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2080 break;
2081 case 1:
2082 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2083 break;
2084 case 2:
2085 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2086 break;
2087 case 3:
2088 alu.src[1].sel = V_SQ_ALU_SRC_0;
2089 alu.src[1].chan = i;
2090 }
2091
2092 alu.dst.sel = ctx->temp_reg;
2093 alu.dst.chan = i;
2094 alu.dst.write = 1;
2095
2096 if (i == 3)
2097 alu.last = 1;
2098 r = r600_bc_add_alu(ctx->bc, &alu);
2099 if (r)
2100 return r;
2101
2102 r = r600_bc_add_literal(ctx->bc, ctx->value);
2103 if (r)
2104 return r;
2105 }
2106
2107 for (i = 0; i < 4; i++) {
2108 memset(&alu, 0, sizeof(struct r600_bc_alu));
2109 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2110
2111 alu.src[0] = r600_src[0];
2112 switch (i) {
2113 case 0:
2114 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2115 break;
2116 case 1:
2117 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2118 break;
2119 case 2:
2120 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2121 break;
2122 case 3:
2123 alu.src[0].sel = V_SQ_ALU_SRC_0;
2124 alu.src[0].chan = i;
2125 }
2126
2127 alu.src[1] = r600_src[1];
2128 switch (i) {
2129 case 0:
2130 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2131 break;
2132 case 1:
2133 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2134 break;
2135 case 2:
2136 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2137 break;
2138 case 3:
2139 alu.src[1].sel = V_SQ_ALU_SRC_0;
2140 alu.src[1].chan = i;
2141 }
2142
2143 alu.src[2].sel = ctx->temp_reg;
2144 alu.src[2].neg = 1;
2145 alu.src[2].chan = i;
2146
2147 if (use_temp)
2148 alu.dst.sel = ctx->temp_reg;
2149 else {
2150 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2151 if (r)
2152 return r;
2153 }
2154 alu.dst.chan = i;
2155 alu.dst.write = 1;
2156 alu.is_op3 = 1;
2157 if (i == 3)
2158 alu.last = 1;
2159 r = r600_bc_add_alu(ctx->bc, &alu);
2160 if (r)
2161 return r;
2162
2163 r = r600_bc_add_literal(ctx->bc, ctx->value);
2164 if (r)
2165 return r;
2166 }
2167 if (use_temp)
2168 return tgsi_helper_copy(ctx, inst);
2169 return 0;
2170 }
2171
2172 static int tgsi_exp(struct r600_shader_ctx *ctx)
2173 {
2174 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2175 struct r600_bc_alu_src r600_src[3];
2176 struct r600_bc_alu alu;
2177 int r;
2178
2179 /* result.x = 2^floor(src); */
2180 if (inst->Dst[0].Register.WriteMask & 1) {
2181 memset(&alu, 0, sizeof(struct r600_bc_alu));
2182
2183 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2184 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2185 if (r)
2186 return r;
2187
2188 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2189
2190 alu.dst.sel = ctx->temp_reg;
2191 alu.dst.chan = 0;
2192 alu.dst.write = 1;
2193 alu.last = 1;
2194 r = r600_bc_add_alu(ctx->bc, &alu);
2195 if (r)
2196 return r;
2197
2198 r = r600_bc_add_literal(ctx->bc, ctx->value);
2199 if (r)
2200 return r;
2201
2202 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2203 alu.src[0].sel = ctx->temp_reg;
2204 alu.src[0].chan = 0;
2205
2206 alu.dst.sel = ctx->temp_reg;
2207 alu.dst.chan = 0;
2208 alu.dst.write = 1;
2209 alu.last = 1;
2210 r = r600_bc_add_alu(ctx->bc, &alu);
2211 if (r)
2212 return r;
2213
2214 r = r600_bc_add_literal(ctx->bc, ctx->value);
2215 if (r)
2216 return r;
2217 }
2218
2219 /* result.y = tmp - floor(tmp); */
2220 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2221 memset(&alu, 0, sizeof(struct r600_bc_alu));
2222
2223 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2224 alu.src[0] = r600_src[0];
2225 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2226 if (r)
2227 return r;
2228 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2229
2230 alu.dst.sel = ctx->temp_reg;
2231 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2232 // if (r)
2233 // return r;
2234 alu.dst.write = 1;
2235 alu.dst.chan = 1;
2236
2237 alu.last = 1;
2238
2239 r = r600_bc_add_alu(ctx->bc, &alu);
2240 if (r)
2241 return r;
2242 r = r600_bc_add_literal(ctx->bc, ctx->value);
2243 if (r)
2244 return r;
2245 }
2246
2247 /* result.z = RoughApprox2ToX(tmp);*/
2248 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2249 memset(&alu, 0, sizeof(struct r600_bc_alu));
2250 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2251 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2252 if (r)
2253 return r;
2254 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2255
2256 alu.dst.sel = ctx->temp_reg;
2257 alu.dst.write = 1;
2258 alu.dst.chan = 2;
2259
2260 alu.last = 1;
2261
2262 r = r600_bc_add_alu(ctx->bc, &alu);
2263 if (r)
2264 return r;
2265 r = r600_bc_add_literal(ctx->bc, ctx->value);
2266 if (r)
2267 return r;
2268 }
2269
2270 /* result.w = 1.0;*/
2271 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2272 memset(&alu, 0, sizeof(struct r600_bc_alu));
2273
2274 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2275 alu.src[0].sel = V_SQ_ALU_SRC_1;
2276 alu.src[0].chan = 0;
2277
2278 alu.dst.sel = ctx->temp_reg;
2279 alu.dst.chan = 3;
2280 alu.dst.write = 1;
2281 alu.last = 1;
2282 r = r600_bc_add_alu(ctx->bc, &alu);
2283 if (r)
2284 return r;
2285 r = r600_bc_add_literal(ctx->bc, ctx->value);
2286 if (r)
2287 return r;
2288 }
2289 return tgsi_helper_copy(ctx, inst);
2290 }
2291
2292 static int tgsi_log(struct r600_shader_ctx *ctx)
2293 {
2294 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2295 struct r600_bc_alu alu;
2296 int r;
2297
2298 /* result.x = floor(log2(src)); */
2299 if (inst->Dst[0].Register.WriteMask & 1) {
2300 memset(&alu, 0, sizeof(struct r600_bc_alu));
2301
2302 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2303 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2304 if (r)
2305 return r;
2306
2307 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2308
2309 alu.dst.sel = ctx->temp_reg;
2310 alu.dst.chan = 0;
2311 alu.dst.write = 1;
2312 alu.last = 1;
2313 r = r600_bc_add_alu(ctx->bc, &alu);
2314 if (r)
2315 return r;
2316
2317 r = r600_bc_add_literal(ctx->bc, ctx->value);
2318 if (r)
2319 return r;
2320
2321 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2322 alu.src[0].sel = ctx->temp_reg;
2323 alu.src[0].chan = 0;
2324
2325 alu.dst.sel = ctx->temp_reg;
2326 alu.dst.chan = 0;
2327 alu.dst.write = 1;
2328 alu.last = 1;
2329
2330 r = r600_bc_add_alu(ctx->bc, &alu);
2331 if (r)
2332 return r;
2333
2334 r = r600_bc_add_literal(ctx->bc, ctx->value);
2335 if (r)
2336 return r;
2337 }
2338
2339 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2340 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2341 memset(&alu, 0, sizeof(struct r600_bc_alu));
2342
2343 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2344 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2345 if (r)
2346 return r;
2347
2348 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2349
2350 alu.dst.sel = ctx->temp_reg;
2351 alu.dst.chan = 1;
2352 alu.dst.write = 1;
2353 alu.last = 1;
2354
2355 r = r600_bc_add_alu(ctx->bc, &alu);
2356 if (r)
2357 return r;
2358
2359 r = r600_bc_add_literal(ctx->bc, ctx->value);
2360 if (r)
2361 return r;
2362
2363 memset(&alu, 0, sizeof(struct r600_bc_alu));
2364
2365 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2366 alu.src[0].sel = ctx->temp_reg;
2367 alu.src[0].chan = 1;
2368
2369 alu.dst.sel = ctx->temp_reg;
2370 alu.dst.chan = 1;
2371 alu.dst.write = 1;
2372 alu.last = 1;
2373
2374 r = r600_bc_add_alu(ctx->bc, &alu);
2375 if (r)
2376 return r;
2377
2378 r = r600_bc_add_literal(ctx->bc, ctx->value);
2379 if (r)
2380 return r;
2381
2382 memset(&alu, 0, sizeof(struct r600_bc_alu));
2383
2384 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2385 alu.src[0].sel = ctx->temp_reg;
2386 alu.src[0].chan = 1;
2387
2388 alu.dst.sel = ctx->temp_reg;
2389 alu.dst.chan = 1;
2390 alu.dst.write = 1;
2391 alu.last = 1;
2392
2393 r = r600_bc_add_alu(ctx->bc, &alu);
2394 if (r)
2395 return r;
2396
2397 r = r600_bc_add_literal(ctx->bc, ctx->value);
2398 if (r)
2399 return r;
2400
2401 memset(&alu, 0, sizeof(struct r600_bc_alu));
2402
2403 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2404 alu.src[0].sel = ctx->temp_reg;
2405 alu.src[0].chan = 1;
2406
2407 alu.dst.sel = ctx->temp_reg;
2408 alu.dst.chan = 1;
2409 alu.dst.write = 1;
2410 alu.last = 1;
2411
2412 r = r600_bc_add_alu(ctx->bc, &alu);
2413 if (r)
2414 return r;
2415
2416 r = r600_bc_add_literal(ctx->bc, ctx->value);
2417 if (r)
2418 return r;
2419
2420 memset(&alu, 0, sizeof(struct r600_bc_alu));
2421
2422 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2423
2424 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2425 if (r)
2426 return r;
2427
2428 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2429
2430 alu.src[1].sel = ctx->temp_reg;
2431 alu.src[1].chan = 1;
2432
2433 alu.dst.sel = ctx->temp_reg;
2434 alu.dst.chan = 1;
2435 alu.dst.write = 1;
2436 alu.last = 1;
2437
2438 r = r600_bc_add_alu(ctx->bc, &alu);
2439 if (r)
2440 return r;
2441
2442 r = r600_bc_add_literal(ctx->bc, ctx->value);
2443 if (r)
2444 return r;
2445 }
2446
2447 /* result.z = log2(src);*/
2448 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2449 memset(&alu, 0, sizeof(struct r600_bc_alu));
2450
2451 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2452 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2453 if (r)
2454 return r;
2455
2456 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2457
2458 alu.dst.sel = ctx->temp_reg;
2459 alu.dst.write = 1;
2460 alu.dst.chan = 2;
2461 alu.last = 1;
2462
2463 r = r600_bc_add_alu(ctx->bc, &alu);
2464 if (r)
2465 return r;
2466
2467 r = r600_bc_add_literal(ctx->bc, ctx->value);
2468 if (r)
2469 return r;
2470 }
2471
2472 /* result.w = 1.0; */
2473 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2474 memset(&alu, 0, sizeof(struct r600_bc_alu));
2475
2476 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2477 alu.src[0].sel = V_SQ_ALU_SRC_1;
2478 alu.src[0].chan = 0;
2479
2480 alu.dst.sel = ctx->temp_reg;
2481 alu.dst.chan = 3;
2482 alu.dst.write = 1;
2483 alu.last = 1;
2484
2485 r = r600_bc_add_alu(ctx->bc, &alu);
2486 if (r)
2487 return r;
2488
2489 r = r600_bc_add_literal(ctx->bc, ctx->value);
2490 if (r)
2491 return r;
2492 }
2493
2494 return tgsi_helper_copy(ctx, inst);
2495 }
2496
2497 /* r6/7 only for now */
2498 static int tgsi_arl(struct r600_shader_ctx *ctx)
2499 {
2500 /* TODO from r600c, ar values don't persist between clauses */
2501 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2502 struct r600_bc_alu alu;
2503 int r;
2504 memset(&alu, 0, sizeof(struct r600_bc_alu));
2505
2506 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2507
2508 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2509 if (r)
2510 return r;
2511 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2512
2513 alu.last = 1;
2514
2515 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2516 if (r)
2517 return r;
2518 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2519 return 0;
2520 }
2521
2522 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2523 {
2524 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2525 struct r600_bc_alu alu;
2526 int i, r = 0;
2527
2528 for (i = 0; i < 4; i++) {
2529 memset(&alu, 0, sizeof(struct r600_bc_alu));
2530
2531 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2532 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2533 if (r)
2534 return r;
2535
2536 if (i == 0 || i == 3) {
2537 alu.src[0].sel = V_SQ_ALU_SRC_1;
2538 } else {
2539 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2540 if (r)
2541 return r;
2542 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2543 }
2544
2545 if (i == 0 || i == 2) {
2546 alu.src[1].sel = V_SQ_ALU_SRC_1;
2547 } else {
2548 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2549 if (r)
2550 return r;
2551 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2552 }
2553 if (i == 3)
2554 alu.last = 1;
2555 r = r600_bc_add_alu(ctx->bc, &alu);
2556 if (r)
2557 return r;
2558 }
2559 return 0;
2560 }
2561
2562 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2563 {
2564 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2565 struct r600_bc_alu alu;
2566 int r;
2567
2568 memset(&alu, 0, sizeof(struct r600_bc_alu));
2569 alu.inst = opcode;
2570 alu.predicate = 1;
2571
2572 alu.dst.sel = ctx->temp_reg;
2573 alu.dst.write = 1;
2574 alu.dst.chan = 0;
2575
2576 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2577 if (r)
2578 return r;
2579 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2580 alu.src[1].sel = V_SQ_ALU_SRC_0;
2581 alu.src[1].chan = 0;
2582
2583 alu.last = 1;
2584
2585 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2586 if (r)
2587 return r;
2588 return 0;
2589 }
2590
2591 static int pops(struct r600_shader_ctx *ctx, int pops)
2592 {
2593 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2594 ctx->bc->cf_last->pop_count = pops;
2595 return 0;
2596 }
2597
2598 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2599 {
2600 switch(reason) {
2601 case FC_PUSH_VPM:
2602 ctx->bc->callstack[ctx->bc->call_sp].current--;
2603 break;
2604 case FC_PUSH_WQM:
2605 case FC_LOOP:
2606 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2607 break;
2608 case FC_REP:
2609 /* TOODO : for 16 vp asic should -= 2; */
2610 ctx->bc->callstack[ctx->bc->call_sp].current --;
2611 break;
2612 }
2613 }
2614
2615 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2616 {
2617 if (check_max_only) {
2618 int diff;
2619 switch (reason) {
2620 case FC_PUSH_VPM:
2621 diff = 1;
2622 break;
2623 case FC_PUSH_WQM:
2624 diff = 4;
2625 break;
2626 default:
2627 assert(0);
2628 diff = 0;
2629 }
2630 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2631 ctx->bc->callstack[ctx->bc->call_sp].max) {
2632 ctx->bc->callstack[ctx->bc->call_sp].max =
2633 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2634 }
2635 return;
2636 }
2637 switch (reason) {
2638 case FC_PUSH_VPM:
2639 ctx->bc->callstack[ctx->bc->call_sp].current++;
2640 break;
2641 case FC_PUSH_WQM:
2642 case FC_LOOP:
2643 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2644 break;
2645 case FC_REP:
2646 ctx->bc->callstack[ctx->bc->call_sp].current++;
2647 break;
2648 }
2649
2650 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2651 ctx->bc->callstack[ctx->bc->call_sp].max) {
2652 ctx->bc->callstack[ctx->bc->call_sp].max =
2653 ctx->bc->callstack[ctx->bc->call_sp].current;
2654 }
2655 }
2656
2657 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2658 {
2659 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2660
2661 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2662 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2663 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2664 sp->num_mid++;
2665 }
2666
2667 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2668 {
2669 ctx->bc->fc_sp++;
2670 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2671 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2672 }
2673
2674 static void fc_poplevel(struct r600_shader_ctx *ctx)
2675 {
2676 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2677 if (sp->mid) {
2678 free(sp->mid);
2679 sp->mid = NULL;
2680 }
2681 sp->num_mid = 0;
2682 sp->start = NULL;
2683 sp->type = 0;
2684 ctx->bc->fc_sp--;
2685 }
2686
2687 #if 0
2688 static int emit_return(struct r600_shader_ctx *ctx)
2689 {
2690 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2691 return 0;
2692 }
2693
2694 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2695 {
2696
2697 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2698 ctx->bc->cf_last->pop_count = pops;
2699 /* TODO work out offset */
2700 return 0;
2701 }
2702
2703 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2704 {
2705 return 0;
2706 }
2707
2708 static void emit_testflag(struct r600_shader_ctx *ctx)
2709 {
2710
2711 }
2712
2713 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2714 {
2715 emit_testflag(ctx);
2716 emit_jump_to_offset(ctx, 1, 4);
2717 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2718 pops(ctx, ifidx + 1);
2719 emit_return(ctx);
2720 }
2721
2722 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2723 {
2724 emit_testflag(ctx);
2725
2726 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2727 ctx->bc->cf_last->pop_count = 1;
2728
2729 fc_set_mid(ctx, fc_sp);
2730
2731 pops(ctx, 1);
2732 }
2733 #endif
2734
2735 static int tgsi_if(struct r600_shader_ctx *ctx)
2736 {
2737 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2738
2739 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2740
2741 fc_pushlevel(ctx, FC_IF);
2742
2743 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2744 return 0;
2745 }
2746
2747 static int tgsi_else(struct r600_shader_ctx *ctx)
2748 {
2749 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2750 ctx->bc->cf_last->pop_count = 1;
2751
2752 fc_set_mid(ctx, ctx->bc->fc_sp);
2753 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2754 return 0;
2755 }
2756
2757 static int tgsi_endif(struct r600_shader_ctx *ctx)
2758 {
2759 pops(ctx, 1);
2760 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2761 R600_ERR("if/endif unbalanced in shader\n");
2762 return -1;
2763 }
2764
2765 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2766 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2767 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2768 } else {
2769 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2770 }
2771 fc_poplevel(ctx);
2772
2773 callstack_decrease_current(ctx, FC_PUSH_VPM);
2774 return 0;
2775 }
2776
2777 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2778 {
2779 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2780
2781 fc_pushlevel(ctx, FC_LOOP);
2782
2783 /* check stack depth */
2784 callstack_check_depth(ctx, FC_LOOP, 0);
2785 return 0;
2786 }
2787
2788 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2789 {
2790 int i;
2791
2792 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2793
2794 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2795 R600_ERR("loop/endloop in shader code are not paired.\n");
2796 return -EINVAL;
2797 }
2798
2799 /* fixup loop pointers - from r600isa
2800 LOOP END points to CF after LOOP START,
2801 LOOP START point to CF after LOOP END
2802 BRK/CONT point to LOOP END CF
2803 */
2804 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2805
2806 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2807
2808 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2809 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2810 }
2811 /* TODO add LOOPRET support */
2812 fc_poplevel(ctx);
2813 callstack_decrease_current(ctx, FC_LOOP);
2814 return 0;
2815 }
2816
2817 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2818 {
2819 unsigned int fscp;
2820
2821 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2822 {
2823 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2824 break;
2825 }
2826
2827 if (fscp == 0) {
2828 R600_ERR("Break not inside loop/endloop pair\n");
2829 return -EINVAL;
2830 }
2831
2832 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2833 ctx->bc->cf_last->pop_count = 1;
2834
2835 fc_set_mid(ctx, fscp);
2836
2837 pops(ctx, 1);
2838 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2839 return 0;
2840 }
2841
2842 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2843 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_arl},
2844 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2845 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2846
2847 /* FIXME:
2848 * For state trackers other than OpenGL, we'll want to use
2849 * _RECIP_IEEE instead.
2850 */
2851 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2852
2853 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2854 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2855 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2856 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2857 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2858 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2859 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2860 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2861 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2862 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2863 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2864 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2865 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2866 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2867 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2868 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2869 /* gap */
2870 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2871 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2872 /* gap */
2873 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2874 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2875 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2876 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2877 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2878 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2879 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2880 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2881 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2882 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2883 /* gap */
2884 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2885 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2886 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2887 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2888 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2889 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2890 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2891 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2892 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2893 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2894 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2895 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2896 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2897 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2898 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2899 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2900 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2901 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2902 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2903 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2904 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2905 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2906 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2907 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2908 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2909 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2910 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2911 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2912 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2913 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2914 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2915 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2916 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2917 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2918 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2919 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2920 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2921 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2922 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2923 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2924 {TGSI_OPCODE_TXL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2925 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2926 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2927 /* gap */
2928 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2929 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2930 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2931 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2932 /* gap */
2933 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2934 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2935 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2936 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2937 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2938 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2939 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2940 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2941 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2942 /* gap */
2943 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2944 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2945 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2946 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2947 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2948 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2949 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2950 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2951 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2952 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2953 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2954 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2955 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2956 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2957 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2958 /* gap */
2959 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2960 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2961 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2962 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2963 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2964 /* gap */
2965 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2966 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2967 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2968 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2969 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2970 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2971 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2972 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2973 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2974 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2975 /* gap */
2976 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2977 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2978 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2979 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2980 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2981 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2982 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2983 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2984 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2985 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2986 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2987 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2988 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2989 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2990 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2991 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2992 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2993 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2994 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2995 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2996 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2997 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2998 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2999 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3000 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3001 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3002 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3003 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3004 };
3005
3006 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
3007 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3008 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3009 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
3010 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
3011 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
3012 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
3013 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3014 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
3015 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3016 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3017 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3018 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
3019 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
3020 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
3021 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
3022 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
3023 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
3024 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3025 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
3026 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3027 /* gap */
3028 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3029 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3030 /* gap */
3031 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3032 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3033 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3034 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3035 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3036 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3037 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3038 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3039 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3040 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3041 /* gap */
3042 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3043 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3044 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3045 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3046 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3047 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3048 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3049 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3050 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3051 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3052 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3053 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3054 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3055 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3056 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3057 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3058 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3059 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3060 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3061 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3062 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3063 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3064 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3065 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3066 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3067 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3068 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3069 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3070 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3071 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3072 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3073 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3074 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3075 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3076 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3077 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3078 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3079 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3080 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3081 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3082 {TGSI_OPCODE_TXL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3083 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3084 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3085 /* gap */
3086 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3087 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3088 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3089 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3090 /* gap */
3091 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3092 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3093 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3094 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3095 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3096 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3097 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3098 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3099 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3100 /* gap */
3101 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3102 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3103 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3104 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3105 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3106 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3107 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3108 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3109 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3110 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3111 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3112 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3113 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3114 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3115 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3116 /* gap */
3117 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3118 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3119 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3120 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3121 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3122 /* gap */
3123 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3124 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3125 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3126 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3127 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3128 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3129 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3130 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3131 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3132 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3133 /* gap */
3134 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3135 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3136 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3137 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3138 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3139 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3140 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3141 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3142 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3143 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3144 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3145 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3146 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3147 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3148 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3149 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3150 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3151 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3152 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3153 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3154 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3155 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3156 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3157 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3158 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3159 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3160 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3161 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3162 };