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r600g/llvm: Don't feed LLVM output through r600_bytecode_build()
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include <stdio.h>
39 #include <errno.h>
40 #include <byteswap.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
64 struct r600_pipe_shader *pipeshader,
65 struct r600_shader_key key);
66
67 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
68 int size, unsigned comp_mask) {
69
70 if (!size)
71 return;
72
73 if (ps->num_arrays == ps->max_arrays) {
74 ps->max_arrays += 64;
75 ps->arrays = realloc(ps->arrays, ps->max_arrays *
76 sizeof(struct r600_shader_array));
77 }
78
79 int n = ps->num_arrays;
80 ++ps->num_arrays;
81
82 ps->arrays[n].comp_mask = comp_mask;
83 ps->arrays[n].gpr_start = start_gpr;
84 ps->arrays[n].gpr_count = size;
85 }
86
87 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
88 {
89 struct tgsi_parse_context parse;
90
91 if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
92 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
93 return ~0;
94 }
95 return parse.FullHeader.Processor.Processor;
96 }
97
98 static bool r600_can_dump_shader(struct r600_screen *rscreen, unsigned processor_type)
99 {
100 switch (processor_type) {
101 case TGSI_PROCESSOR_VERTEX:
102 return (rscreen->debug_flags & DBG_VS) != 0;
103 case TGSI_PROCESSOR_GEOMETRY:
104 return (rscreen->debug_flags & DBG_GS) != 0;
105 case TGSI_PROCESSOR_FRAGMENT:
106 return (rscreen->debug_flags & DBG_PS) != 0;
107 case TGSI_PROCESSOR_COMPUTE:
108 return (rscreen->debug_flags & DBG_CS) != 0;
109 default:
110 return false;
111 }
112 }
113
114 static void r600_dump_streamout(struct pipe_stream_output_info *so)
115 {
116 unsigned i;
117
118 fprintf(stderr, "STREAMOUT\n");
119 for (i = 0; i < so->num_outputs; i++) {
120 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
121 so->output[i].start_component;
122 fprintf(stderr, " %i: MEM_STREAM0_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
123 i, so->output[i].output_buffer,
124 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
125 so->output[i].register_index,
126 mask & 1 ? "x" : "",
127 mask & 2 ? "y" : "",
128 mask & 4 ? "z" : "",
129 mask & 8 ? "w" : "",
130 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
131 }
132 }
133
134 int r600_pipe_shader_create(struct pipe_context *ctx,
135 struct r600_pipe_shader *shader,
136 struct r600_shader_key key)
137 {
138 struct r600_context *rctx = (struct r600_context *)ctx;
139 struct r600_pipe_shader_selector *sel = shader->selector;
140 int r, i;
141 uint32_t *ptr;
142 bool dump = r600_can_dump_shader(rctx->screen, tgsi_get_processor_type(sel->tokens));
143 unsigned use_sb = rctx->screen->debug_flags & DBG_SB;
144 unsigned sb_disasm = use_sb || (rctx->screen->debug_flags & DBG_SB_DISASM);
145
146 shader->shader.bc.isa = rctx->isa;
147
148 if (dump) {
149 fprintf(stderr, "--------------------------------------------------------------\n");
150 tgsi_dump(sel->tokens, 0);
151
152 if (sel->so.num_outputs) {
153 r600_dump_streamout(&sel->so);
154 }
155 }
156 r = r600_shader_from_tgsi(rctx->screen, shader, key);
157 if (r) {
158 R600_ERR("translation from TGSI failed !\n");
159 return r;
160 }
161
162 /* Check if the bytecode has already been built. When using the llvm
163 * backend, r600_shader_from_tgsi() will take care of building the
164 * bytecode.
165 */
166 if (!shader->shader.bc.bytecode) {
167 r = r600_bytecode_build(&shader->shader.bc);
168 if (r) {
169 R600_ERR("building bytecode failed !\n");
170 return r;
171 }
172 }
173
174 if (dump && !sb_disasm) {
175 fprintf(stderr, "--------------------------------------------------------------\n");
176 r600_bytecode_disasm(&shader->shader.bc);
177 fprintf(stderr, "______________________________________________________________\n");
178 } else if ((dump && sb_disasm) || use_sb) {
179 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
180 dump, use_sb);
181 if (r) {
182 R600_ERR("r600_sb_bytecode_process failed !\n");
183 return r;
184 }
185 }
186
187 /* Store the shader in a buffer. */
188 if (shader->bo == NULL) {
189 shader->bo = (struct r600_resource*)
190 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
191 if (shader->bo == NULL) {
192 return -ENOMEM;
193 }
194 ptr = r600_buffer_mmap_sync_with_rings(rctx, shader->bo, PIPE_TRANSFER_WRITE);
195 if (R600_BIG_ENDIAN) {
196 for (i = 0; i < shader->shader.bc.ndw; ++i) {
197 ptr[i] = bswap_32(shader->shader.bc.bytecode[i]);
198 }
199 } else {
200 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
201 }
202 rctx->ws->buffer_unmap(shader->bo->cs_buf);
203 }
204
205 /* Build state. */
206 switch (shader->shader.processor_type) {
207 case TGSI_PROCESSOR_VERTEX:
208 if (rctx->chip_class >= EVERGREEN) {
209 evergreen_update_vs_state(ctx, shader);
210 } else {
211 r600_update_vs_state(ctx, shader);
212 }
213 break;
214 case TGSI_PROCESSOR_FRAGMENT:
215 if (rctx->chip_class >= EVERGREEN) {
216 evergreen_update_ps_state(ctx, shader);
217 } else {
218 r600_update_ps_state(ctx, shader);
219 }
220 break;
221 default:
222 return -EINVAL;
223 }
224 return 0;
225 }
226
227 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
228 {
229 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
230 r600_bytecode_clear(&shader->shader.bc);
231 r600_release_command_buffer(&shader->command_buffer);
232 }
233
234 /*
235 * tgsi -> r600 shader
236 */
237 struct r600_shader_tgsi_instruction;
238
239 struct r600_shader_src {
240 unsigned sel;
241 unsigned swizzle[4];
242 unsigned neg;
243 unsigned abs;
244 unsigned rel;
245 unsigned kc_bank;
246 uint32_t value[4];
247 };
248
249 struct r600_shader_ctx {
250 struct tgsi_shader_info info;
251 struct tgsi_parse_context parse;
252 const struct tgsi_token *tokens;
253 unsigned type;
254 unsigned file_offset[TGSI_FILE_COUNT];
255 unsigned temp_reg;
256 struct r600_shader_tgsi_instruction *inst_info;
257 struct r600_bytecode *bc;
258 struct r600_shader *shader;
259 struct r600_shader_src src[4];
260 uint32_t *literals;
261 uint32_t nliterals;
262 uint32_t max_driver_temp_used;
263 boolean use_llvm;
264 /* needed for evergreen interpolation */
265 boolean input_centroid;
266 boolean input_linear;
267 boolean input_perspective;
268 int num_interp_gpr;
269 int face_gpr;
270 int colors_used;
271 boolean clip_vertex_write;
272 unsigned cv_output;
273 int fragcoord_input;
274 int native_integers;
275 };
276
277 struct r600_shader_tgsi_instruction {
278 unsigned tgsi_opcode;
279 unsigned is_op3;
280 unsigned op;
281 int (*process)(struct r600_shader_ctx *ctx);
282 };
283
284 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
285 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
286 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
287 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
288 static int tgsi_else(struct r600_shader_ctx *ctx);
289 static int tgsi_endif(struct r600_shader_ctx *ctx);
290 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
291 static int tgsi_endloop(struct r600_shader_ctx *ctx);
292 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
293
294 #ifdef HAVE_OPENCL
295 int r600_compute_shader_create(struct pipe_context * ctx,
296 LLVMModuleRef mod, struct r600_bytecode * bytecode)
297 {
298 struct r600_context *r600_ctx = (struct r600_context *)ctx;
299 struct r600_shader_ctx shader_ctx;
300 boolean use_kill = false;
301 bool dump = (r600_ctx->screen->debug_flags & DBG_CS) != 0;
302 unsigned use_sb = r600_ctx->screen->debug_flags & DBG_SB_CS;
303 unsigned sb_disasm = use_sb ||
304 (r600_ctx->screen->debug_flags & DBG_SB_DISASM);
305
306 shader_ctx.bc = bytecode;
307 r600_bytecode_init(shader_ctx.bc, r600_ctx->chip_class, r600_ctx->family,
308 r600_ctx->screen->msaa_texture_support);
309 shader_ctx.bc->type = TGSI_PROCESSOR_COMPUTE;
310 shader_ctx.bc->isa = r600_ctx->isa;
311 r600_llvm_compile(mod, r600_ctx->family,
312 shader_ctx.bc, &use_kill, dump);
313
314 if (dump && !sb_disasm) {
315 r600_bytecode_disasm(shader_ctx.bc);
316 } else if ((dump && sb_disasm) || use_sb) {
317 if (r600_sb_bytecode_process(r600_ctx, shader_ctx.bc, NULL, dump, use_sb))
318 R600_ERR("r600_sb_bytecode_process failed!\n");
319 }
320
321 return 1;
322 }
323
324 #endif /* HAVE_OPENCL */
325
326 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
327 {
328 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
329 int j;
330
331 if (i->Instruction.NumDstRegs > 1) {
332 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
333 return -EINVAL;
334 }
335 if (i->Instruction.Predicate) {
336 R600_ERR("predicate unsupported\n");
337 return -EINVAL;
338 }
339 #if 0
340 if (i->Instruction.Label) {
341 R600_ERR("label unsupported\n");
342 return -EINVAL;
343 }
344 #endif
345 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
346 if (i->Src[j].Register.Dimension) {
347 if (i->Src[j].Register.File != TGSI_FILE_CONSTANT) {
348 R600_ERR("unsupported src %d (dimension %d)\n", j,
349 i->Src[j].Register.Dimension);
350 return -EINVAL;
351 }
352 }
353 }
354 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
355 if (i->Dst[j].Register.Dimension) {
356 R600_ERR("unsupported dst (dimension)\n");
357 return -EINVAL;
358 }
359 }
360 return 0;
361 }
362
363 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
364 int input)
365 {
366 int ij_index = 0;
367
368 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
369 if (ctx->shader->input[input].centroid)
370 ij_index++;
371 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
372 /* if we have perspective add one */
373 if (ctx->input_perspective) {
374 ij_index++;
375 /* if we have perspective centroid */
376 if (ctx->input_centroid)
377 ij_index++;
378 }
379 if (ctx->shader->input[input].centroid)
380 ij_index++;
381 }
382
383 ctx->shader->input[input].ij_index = ij_index;
384 }
385
386 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
387 {
388 int i, r;
389 struct r600_bytecode_alu alu;
390 int gpr = 0, base_chan = 0;
391 int ij_index = ctx->shader->input[input].ij_index;
392
393 /* work out gpr and base_chan from index */
394 gpr = ij_index / 2;
395 base_chan = (2 * (ij_index % 2)) + 1;
396
397 for (i = 0; i < 8; i++) {
398 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
399
400 if (i < 4)
401 alu.op = ALU_OP2_INTERP_ZW;
402 else
403 alu.op = ALU_OP2_INTERP_XY;
404
405 if ((i > 1) && (i < 6)) {
406 alu.dst.sel = ctx->shader->input[input].gpr;
407 alu.dst.write = 1;
408 }
409
410 alu.dst.chan = i % 4;
411
412 alu.src[0].sel = gpr;
413 alu.src[0].chan = (base_chan - (i % 2));
414
415 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
416
417 alu.bank_swizzle_force = SQ_ALU_VEC_210;
418 if ((i % 4) == 3)
419 alu.last = 1;
420 r = r600_bytecode_add_alu(ctx->bc, &alu);
421 if (r)
422 return r;
423 }
424 return 0;
425 }
426
427 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
428 {
429 int i, r;
430 struct r600_bytecode_alu alu;
431
432 for (i = 0; i < 4; i++) {
433 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
434
435 alu.op = ALU_OP1_INTERP_LOAD_P0;
436
437 alu.dst.sel = ctx->shader->input[input].gpr;
438 alu.dst.write = 1;
439
440 alu.dst.chan = i;
441
442 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
443 alu.src[0].chan = i;
444
445 if (i == 3)
446 alu.last = 1;
447 r = r600_bytecode_add_alu(ctx->bc, &alu);
448 if (r)
449 return r;
450 }
451 return 0;
452 }
453
454 /*
455 * Special export handling in shaders
456 *
457 * shader export ARRAY_BASE for EXPORT_POS:
458 * 60 is position
459 * 61 is misc vector
460 * 62, 63 are clip distance vectors
461 *
462 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
463 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
464 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
465 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
466 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
467 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
468 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
469 * exclusive from render target index)
470 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
471 *
472 *
473 * shader export ARRAY_BASE for EXPORT_PIXEL:
474 * 0-7 CB targets
475 * 61 computed Z vector
476 *
477 * The use of the values exported in the computed Z vector are controlled
478 * by DB_SHADER_CONTROL:
479 * Z_EXPORT_ENABLE - Z as a float in RED
480 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
481 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
482 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
483 * DB_SOURCE_FORMAT - export control restrictions
484 *
485 */
486
487
488 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
489 static int r600_spi_sid(struct r600_shader_io * io)
490 {
491 int index, name = io->name;
492
493 /* These params are handled differently, they don't need
494 * semantic indices, so we'll use 0 for them.
495 */
496 if (name == TGSI_SEMANTIC_POSITION ||
497 name == TGSI_SEMANTIC_PSIZE ||
498 name == TGSI_SEMANTIC_FACE)
499 index = 0;
500 else {
501 if (name == TGSI_SEMANTIC_GENERIC) {
502 /* For generic params simply use sid from tgsi */
503 index = io->sid;
504 } else {
505 /* For non-generic params - pack name and sid into 8 bits */
506 index = 0x80 | (name<<3) | (io->sid);
507 }
508
509 /* Make sure that all really used indices have nonzero value, so
510 * we can just compare it to 0 later instead of comparing the name
511 * with different values to detect special cases. */
512 index++;
513 }
514
515 return index;
516 };
517
518 /* turn input into interpolate on EG */
519 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
520 {
521 int r = 0;
522
523 if (ctx->shader->input[index].spi_sid) {
524 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
525 if (ctx->shader->input[index].interpolate > 0) {
526 evergreen_interp_assign_ij_index(ctx, index);
527 if (!ctx->use_llvm)
528 r = evergreen_interp_alu(ctx, index);
529 } else {
530 if (!ctx->use_llvm)
531 r = evergreen_interp_flat(ctx, index);
532 }
533 }
534 return r;
535 }
536
537 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
538 {
539 struct r600_bytecode_alu alu;
540 int i, r;
541 int gpr_front = ctx->shader->input[front].gpr;
542 int gpr_back = ctx->shader->input[back].gpr;
543
544 for (i = 0; i < 4; i++) {
545 memset(&alu, 0, sizeof(alu));
546 alu.op = ALU_OP3_CNDGT;
547 alu.is_op3 = 1;
548 alu.dst.write = 1;
549 alu.dst.sel = gpr_front;
550 alu.src[0].sel = ctx->face_gpr;
551 alu.src[1].sel = gpr_front;
552 alu.src[2].sel = gpr_back;
553
554 alu.dst.chan = i;
555 alu.src[1].chan = i;
556 alu.src[2].chan = i;
557 alu.last = (i==3);
558
559 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
560 return r;
561 }
562
563 return 0;
564 }
565
566 static int tgsi_declaration(struct r600_shader_ctx *ctx)
567 {
568 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
569 int r, i, j, count = d->Range.Last - d->Range.First + 1;
570
571 switch (d->Declaration.File) {
572 case TGSI_FILE_INPUT:
573 i = ctx->shader->ninput;
574 ctx->shader->ninput += count;
575 ctx->shader->input[i].name = d->Semantic.Name;
576 ctx->shader->input[i].sid = d->Semantic.Index;
577 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
578 ctx->shader->input[i].centroid = d->Interp.Centroid;
579 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
580 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
581 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
582 switch (ctx->shader->input[i].name) {
583 case TGSI_SEMANTIC_FACE:
584 ctx->face_gpr = ctx->shader->input[i].gpr;
585 break;
586 case TGSI_SEMANTIC_COLOR:
587 ctx->colors_used++;
588 break;
589 case TGSI_SEMANTIC_POSITION:
590 ctx->fragcoord_input = i;
591 break;
592 }
593 if (ctx->bc->chip_class >= EVERGREEN) {
594 if ((r = evergreen_interp_input(ctx, i)))
595 return r;
596 }
597 }
598 for (j = 1; j < count; ++j) {
599 ctx->shader->input[i + j] = ctx->shader->input[i];
600 ctx->shader->input[i + j].gpr += j;
601 }
602 break;
603 case TGSI_FILE_OUTPUT:
604 i = ctx->shader->noutput++;
605 ctx->shader->output[i].name = d->Semantic.Name;
606 ctx->shader->output[i].sid = d->Semantic.Index;
607 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
608 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
609 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
610 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
611 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
612 switch (d->Semantic.Name) {
613 case TGSI_SEMANTIC_CLIPDIST:
614 ctx->shader->clip_dist_write |= d->Declaration.UsageMask << (d->Semantic.Index << 2);
615 break;
616 case TGSI_SEMANTIC_PSIZE:
617 ctx->shader->vs_out_misc_write = 1;
618 ctx->shader->vs_out_point_size = 1;
619 break;
620 case TGSI_SEMANTIC_CLIPVERTEX:
621 ctx->clip_vertex_write = TRUE;
622 ctx->cv_output = i;
623 break;
624 }
625 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
626 switch (d->Semantic.Name) {
627 case TGSI_SEMANTIC_COLOR:
628 ctx->shader->nr_ps_max_color_exports++;
629 break;
630 }
631 }
632 break;
633 case TGSI_FILE_TEMPORARY:
634 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
635 if (d->Array.ArrayID) {
636 r600_add_gpr_array(ctx->shader,
637 ctx->file_offset[TGSI_FILE_TEMPORARY] +
638 d->Range.First,
639 d->Range.Last - d->Range.First + 1, 0x0F);
640 }
641 }
642 break;
643
644 case TGSI_FILE_CONSTANT:
645 case TGSI_FILE_SAMPLER:
646 case TGSI_FILE_ADDRESS:
647 break;
648
649 case TGSI_FILE_SYSTEM_VALUE:
650 if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
651 if (!ctx->native_integers) {
652 struct r600_bytecode_alu alu;
653 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
654
655 alu.op = ALU_OP1_INT_TO_FLT;
656 alu.src[0].sel = 0;
657 alu.src[0].chan = 3;
658
659 alu.dst.sel = 0;
660 alu.dst.chan = 3;
661 alu.dst.write = 1;
662 alu.last = 1;
663
664 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
665 return r;
666 }
667 break;
668 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
669 break;
670 default:
671 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
672 return -EINVAL;
673 }
674 return 0;
675 }
676
677 static int r600_get_temp(struct r600_shader_ctx *ctx)
678 {
679 return ctx->temp_reg + ctx->max_driver_temp_used++;
680 }
681
682 /*
683 * for evergreen we need to scan the shader to find the number of GPRs we need to
684 * reserve for interpolation.
685 *
686 * we need to know if we are going to emit
687 * any centroid inputs
688 * if perspective and linear are required
689 */
690 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
691 {
692 int i;
693 int num_baryc;
694
695 ctx->input_linear = FALSE;
696 ctx->input_perspective = FALSE;
697 ctx->input_centroid = FALSE;
698 ctx->num_interp_gpr = 1;
699
700 /* any centroid inputs */
701 for (i = 0; i < ctx->info.num_inputs; i++) {
702 /* skip position/face */
703 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
704 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
705 continue;
706 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
707 ctx->input_linear = TRUE;
708 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
709 ctx->input_perspective = TRUE;
710 if (ctx->info.input_centroid[i])
711 ctx->input_centroid = TRUE;
712 }
713
714 num_baryc = 0;
715 /* ignoring sample for now */
716 if (ctx->input_perspective)
717 num_baryc++;
718 if (ctx->input_linear)
719 num_baryc++;
720 if (ctx->input_centroid)
721 num_baryc *= 2;
722
723 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
724
725 /* XXX PULL MODEL and LINE STIPPLE, FIXED PT POS */
726 return ctx->num_interp_gpr;
727 }
728
729 static void tgsi_src(struct r600_shader_ctx *ctx,
730 const struct tgsi_full_src_register *tgsi_src,
731 struct r600_shader_src *r600_src)
732 {
733 memset(r600_src, 0, sizeof(*r600_src));
734 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
735 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
736 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
737 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
738 r600_src->neg = tgsi_src->Register.Negate;
739 r600_src->abs = tgsi_src->Register.Absolute;
740
741 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
742 int index;
743 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
744 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
745 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
746
747 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
748 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
749 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
750 return;
751 }
752 index = tgsi_src->Register.Index;
753 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
754 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
755 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
756 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
757 r600_src->swizzle[0] = 3;
758 r600_src->swizzle[1] = 3;
759 r600_src->swizzle[2] = 3;
760 r600_src->swizzle[3] = 3;
761 r600_src->sel = 0;
762 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
763 r600_src->swizzle[0] = 0;
764 r600_src->swizzle[1] = 0;
765 r600_src->swizzle[2] = 0;
766 r600_src->swizzle[3] = 0;
767 r600_src->sel = 0;
768 }
769 } else {
770 if (tgsi_src->Register.Indirect)
771 r600_src->rel = V_SQ_REL_RELATIVE;
772 r600_src->sel = tgsi_src->Register.Index;
773 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
774 }
775 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
776 if (tgsi_src->Register.Dimension) {
777 r600_src->kc_bank = tgsi_src->Dimension.Index;
778 }
779 }
780 }
781
782 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int cb_idx, unsigned int offset, unsigned int dst_reg)
783 {
784 struct r600_bytecode_vtx vtx;
785 unsigned int ar_reg;
786 int r;
787
788 if (offset) {
789 struct r600_bytecode_alu alu;
790
791 memset(&alu, 0, sizeof(alu));
792
793 alu.op = ALU_OP2_ADD_INT;
794 alu.src[0].sel = ctx->bc->ar_reg;
795
796 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
797 alu.src[1].value = offset;
798
799 alu.dst.sel = dst_reg;
800 alu.dst.write = 1;
801 alu.last = 1;
802
803 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
804 return r;
805
806 ar_reg = dst_reg;
807 } else {
808 ar_reg = ctx->bc->ar_reg;
809 }
810
811 memset(&vtx, 0, sizeof(vtx));
812 vtx.buffer_id = cb_idx;
813 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
814 vtx.src_gpr = ar_reg;
815 vtx.mega_fetch_count = 16;
816 vtx.dst_gpr = dst_reg;
817 vtx.dst_sel_x = 0; /* SEL_X */
818 vtx.dst_sel_y = 1; /* SEL_Y */
819 vtx.dst_sel_z = 2; /* SEL_Z */
820 vtx.dst_sel_w = 3; /* SEL_W */
821 vtx.data_format = FMT_32_32_32_32_FLOAT;
822 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
823 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
824 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
825 vtx.endian = r600_endian_swap(32);
826
827 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
828 return r;
829
830 return 0;
831 }
832
833 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
834 {
835 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
836 struct r600_bytecode_alu alu;
837 int i, j, k, nconst, r;
838
839 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
840 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
841 nconst++;
842 }
843 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
844 }
845 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
846 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
847 continue;
848 }
849
850 if (ctx->src[i].rel) {
851 int treg = r600_get_temp(ctx);
852 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].sel - 512, treg)))
853 return r;
854
855 ctx->src[i].kc_bank = 0;
856 ctx->src[i].sel = treg;
857 ctx->src[i].rel = 0;
858 j--;
859 } else if (j > 0) {
860 int treg = r600_get_temp(ctx);
861 for (k = 0; k < 4; k++) {
862 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
863 alu.op = ALU_OP1_MOV;
864 alu.src[0].sel = ctx->src[i].sel;
865 alu.src[0].chan = k;
866 alu.src[0].rel = ctx->src[i].rel;
867 alu.dst.sel = treg;
868 alu.dst.chan = k;
869 alu.dst.write = 1;
870 if (k == 3)
871 alu.last = 1;
872 r = r600_bytecode_add_alu(ctx->bc, &alu);
873 if (r)
874 return r;
875 }
876 ctx->src[i].sel = treg;
877 ctx->src[i].rel =0;
878 j--;
879 }
880 }
881 return 0;
882 }
883
884 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
885 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
886 {
887 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
888 struct r600_bytecode_alu alu;
889 int i, j, k, nliteral, r;
890
891 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
892 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
893 nliteral++;
894 }
895 }
896 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
897 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
898 int treg = r600_get_temp(ctx);
899 for (k = 0; k < 4; k++) {
900 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
901 alu.op = ALU_OP1_MOV;
902 alu.src[0].sel = ctx->src[i].sel;
903 alu.src[0].chan = k;
904 alu.src[0].value = ctx->src[i].value[k];
905 alu.dst.sel = treg;
906 alu.dst.chan = k;
907 alu.dst.write = 1;
908 if (k == 3)
909 alu.last = 1;
910 r = r600_bytecode_add_alu(ctx->bc, &alu);
911 if (r)
912 return r;
913 }
914 ctx->src[i].sel = treg;
915 j--;
916 }
917 }
918 return 0;
919 }
920
921 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
922 {
923 int i, r, count = ctx->shader->ninput;
924
925 for (i = 0; i < count; i++) {
926 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
927 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
928 if (r)
929 return r;
930 }
931 }
932 return 0;
933 }
934
935
936 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
937 struct r600_pipe_shader *pipeshader,
938 struct r600_shader_key key)
939 {
940 struct r600_shader *shader = &pipeshader->shader;
941 struct tgsi_token *tokens = pipeshader->selector->tokens;
942 struct pipe_stream_output_info so = pipeshader->selector->so;
943 struct tgsi_full_immediate *immediate;
944 struct tgsi_full_property *property;
945 struct r600_shader_ctx ctx;
946 struct r600_bytecode_output output[32];
947 unsigned output_done, noutput;
948 unsigned opcode;
949 int i, j, k, r = 0;
950 int next_pixel_base = 0, next_pos_base = 60, next_param_base = 0;
951 /* Declarations used by llvm code */
952 bool use_llvm = false;
953 bool indirect_gprs;
954
955 #ifdef R600_USE_LLVM
956 use_llvm = !(rscreen->debug_flags & DBG_NO_LLVM);
957 #endif
958 ctx.bc = &shader->bc;
959 ctx.shader = shader;
960 ctx.native_integers = true;
961
962 r600_bytecode_init(ctx.bc, rscreen->chip_class, rscreen->family,
963 rscreen->msaa_texture_support);
964 ctx.tokens = tokens;
965 tgsi_scan_shader(tokens, &ctx.info);
966 shader->indirect_files = ctx.info.indirect_files;
967 indirect_gprs = ctx.info.indirect_files & ~(1 << TGSI_FILE_CONSTANT);
968 tgsi_parse_init(&ctx.parse, tokens);
969 ctx.type = ctx.parse.FullHeader.Processor.Processor;
970 shader->processor_type = ctx.type;
971 ctx.bc->type = shader->processor_type;
972
973 ctx.face_gpr = -1;
974 ctx.fragcoord_input = -1;
975 ctx.colors_used = 0;
976 ctx.clip_vertex_write = 0;
977
978 shader->nr_ps_color_exports = 0;
979 shader->nr_ps_max_color_exports = 0;
980
981 shader->two_side = key.color_two_side;
982
983 /* register allocations */
984 /* Values [0,127] correspond to GPR[0..127].
985 * Values [128,159] correspond to constant buffer bank 0
986 * Values [160,191] correspond to constant buffer bank 1
987 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
988 * Values [256,287] correspond to constant buffer bank 2 (EG)
989 * Values [288,319] correspond to constant buffer bank 3 (EG)
990 * Other special values are shown in the list below.
991 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
992 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
993 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
994 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
995 * 248 SQ_ALU_SRC_0: special constant 0.0.
996 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
997 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
998 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
999 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1000 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1001 * 254 SQ_ALU_SRC_PV: previous vector result.
1002 * 255 SQ_ALU_SRC_PS: previous scalar result.
1003 */
1004 for (i = 0; i < TGSI_FILE_COUNT; i++) {
1005 ctx.file_offset[i] = 0;
1006 }
1007
1008 #ifdef R600_USE_LLVM
1009 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
1010 fprintf(stderr, "Warning: R600 LLVM backend does not support "
1011 "indirect adressing. Falling back to TGSI "
1012 "backend.\n");
1013 use_llvm = 0;
1014 }
1015 #endif
1016 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1017 ctx.file_offset[TGSI_FILE_INPUT] = 1;
1018 if (!use_llvm) {
1019 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
1020 }
1021 }
1022 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
1023 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
1024 }
1025 ctx.use_llvm = use_llvm;
1026
1027 if (use_llvm) {
1028 ctx.file_offset[TGSI_FILE_OUTPUT] =
1029 ctx.file_offset[TGSI_FILE_INPUT];
1030 } else {
1031 ctx.file_offset[TGSI_FILE_OUTPUT] =
1032 ctx.file_offset[TGSI_FILE_INPUT] +
1033 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1034 }
1035 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
1036 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
1037
1038 /* Outside the GPR range. This will be translated to one of the
1039 * kcache banks later. */
1040 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
1041
1042 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
1043 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
1044 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
1045 ctx.temp_reg = ctx.bc->ar_reg + 1;
1046
1047 if (indirect_gprs) {
1048 shader->max_arrays = 0;
1049 shader->num_arrays = 0;
1050
1051 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
1052 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
1053 ctx.file_offset[TGSI_FILE_OUTPUT] -
1054 ctx.file_offset[TGSI_FILE_INPUT],
1055 0x0F);
1056 }
1057 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
1058 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
1059 ctx.file_offset[TGSI_FILE_TEMPORARY] -
1060 ctx.file_offset[TGSI_FILE_OUTPUT],
1061 0x0F);
1062 }
1063 }
1064
1065 ctx.nliterals = 0;
1066 ctx.literals = NULL;
1067 shader->fs_write_all = FALSE;
1068 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1069 tgsi_parse_token(&ctx.parse);
1070 switch (ctx.parse.FullToken.Token.Type) {
1071 case TGSI_TOKEN_TYPE_IMMEDIATE:
1072 immediate = &ctx.parse.FullToken.FullImmediate;
1073 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
1074 if(ctx.literals == NULL) {
1075 r = -ENOMEM;
1076 goto out_err;
1077 }
1078 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
1079 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
1080 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
1081 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
1082 ctx.nliterals++;
1083 break;
1084 case TGSI_TOKEN_TYPE_DECLARATION:
1085 r = tgsi_declaration(&ctx);
1086 if (r)
1087 goto out_err;
1088 break;
1089 case TGSI_TOKEN_TYPE_INSTRUCTION:
1090 break;
1091 case TGSI_TOKEN_TYPE_PROPERTY:
1092 property = &ctx.parse.FullToken.FullProperty;
1093 switch (property->Property.PropertyName) {
1094 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1095 if (property->u[0].Data == 1)
1096 shader->fs_write_all = TRUE;
1097 break;
1098 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1099 /* we don't need this one */
1100 break;
1101 }
1102 break;
1103 default:
1104 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
1105 r = -EINVAL;
1106 goto out_err;
1107 }
1108 }
1109
1110 /* Process two side if needed */
1111 if (shader->two_side && ctx.colors_used) {
1112 int i, count = ctx.shader->ninput;
1113 unsigned next_lds_loc = ctx.shader->nlds;
1114
1115 /* additional inputs will be allocated right after the existing inputs,
1116 * we won't need them after the color selection, so we don't need to
1117 * reserve these gprs for the rest of the shader code and to adjust
1118 * output offsets etc. */
1119 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
1120 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1121
1122 if (ctx.face_gpr == -1) {
1123 i = ctx.shader->ninput++;
1124 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
1125 ctx.shader->input[i].spi_sid = 0;
1126 ctx.shader->input[i].gpr = gpr++;
1127 ctx.face_gpr = ctx.shader->input[i].gpr;
1128 }
1129
1130 for (i = 0; i < count; i++) {
1131 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1132 int ni = ctx.shader->ninput++;
1133 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
1134 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
1135 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
1136 ctx.shader->input[ni].gpr = gpr++;
1137 // TGSI to LLVM needs to know the lds position of inputs.
1138 // Non LLVM path computes it later (in process_twoside_color)
1139 ctx.shader->input[ni].lds_pos = next_lds_loc++;
1140 ctx.shader->input[i].back_color_input = ni;
1141 if (ctx.bc->chip_class >= EVERGREEN) {
1142 if ((r = evergreen_interp_input(&ctx, ni)))
1143 return r;
1144 }
1145 }
1146 }
1147 }
1148
1149 /* LLVM backend setup */
1150 #ifdef R600_USE_LLVM
1151 if (use_llvm) {
1152 struct radeon_llvm_context radeon_llvm_ctx;
1153 LLVMModuleRef mod;
1154 bool dump = r600_can_dump_shader(rscreen, ctx.type);
1155 boolean use_kill = false;
1156
1157 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
1158 radeon_llvm_ctx.type = ctx.type;
1159 radeon_llvm_ctx.two_side = shader->two_side;
1160 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
1161 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
1162 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
1163 radeon_llvm_ctx.color_buffer_count = MAX2(key.nr_cbufs , 1);
1164 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
1165 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->chip_class >= EVERGREEN);
1166 radeon_llvm_ctx.stream_outputs = &so;
1167 radeon_llvm_ctx.clip_vertex = ctx.cv_output;
1168 radeon_llvm_ctx.alpha_to_one = key.alpha_to_one;
1169 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
1170
1171 if (r600_llvm_compile(mod, rscreen->family, ctx.bc, &use_kill, dump)) {
1172 radeon_llvm_dispose(&radeon_llvm_ctx);
1173 use_llvm = 0;
1174 fprintf(stderr, "R600 LLVM backend failed to compile "
1175 "shader. Falling back to TGSI\n");
1176 } else {
1177 ctx.file_offset[TGSI_FILE_OUTPUT] =
1178 ctx.file_offset[TGSI_FILE_INPUT];
1179 }
1180 if (use_kill)
1181 ctx.shader->uses_kill = use_kill;
1182 radeon_llvm_dispose(&radeon_llvm_ctx);
1183 }
1184 #endif
1185 /* End of LLVM backend setup */
1186
1187 if (shader->fs_write_all && rscreen->chip_class >= EVERGREEN)
1188 shader->nr_ps_max_color_exports = 8;
1189
1190 if (!use_llvm) {
1191 if (ctx.fragcoord_input >= 0) {
1192 if (ctx.bc->chip_class == CAYMAN) {
1193 for (j = 0 ; j < 4; j++) {
1194 struct r600_bytecode_alu alu;
1195 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1196 alu.op = ALU_OP1_RECIP_IEEE;
1197 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1198 alu.src[0].chan = 3;
1199
1200 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1201 alu.dst.chan = j;
1202 alu.dst.write = (j == 3);
1203 alu.last = 1;
1204 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1205 return r;
1206 }
1207 } else {
1208 struct r600_bytecode_alu alu;
1209 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1210 alu.op = ALU_OP1_RECIP_IEEE;
1211 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1212 alu.src[0].chan = 3;
1213
1214 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1215 alu.dst.chan = 3;
1216 alu.dst.write = 1;
1217 alu.last = 1;
1218 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1219 return r;
1220 }
1221 }
1222
1223 if (shader->two_side && ctx.colors_used) {
1224 if ((r = process_twoside_color_inputs(&ctx)))
1225 return r;
1226 }
1227
1228 tgsi_parse_init(&ctx.parse, tokens);
1229 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1230 tgsi_parse_token(&ctx.parse);
1231 switch (ctx.parse.FullToken.Token.Type) {
1232 case TGSI_TOKEN_TYPE_INSTRUCTION:
1233 r = tgsi_is_supported(&ctx);
1234 if (r)
1235 goto out_err;
1236 ctx.max_driver_temp_used = 0;
1237 /* reserve first tmp for everyone */
1238 r600_get_temp(&ctx);
1239
1240 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
1241 if ((r = tgsi_split_constant(&ctx)))
1242 goto out_err;
1243 if ((r = tgsi_split_literal_constant(&ctx)))
1244 goto out_err;
1245 if (ctx.bc->chip_class == CAYMAN)
1246 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
1247 else if (ctx.bc->chip_class >= EVERGREEN)
1248 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
1249 else
1250 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
1251 r = ctx.inst_info->process(&ctx);
1252 if (r)
1253 goto out_err;
1254 break;
1255 default:
1256 break;
1257 }
1258 }
1259 }
1260
1261 /* Reset the temporary register counter. */
1262 ctx.max_driver_temp_used = 0;
1263
1264 noutput = shader->noutput;
1265
1266 if (ctx.clip_vertex_write) {
1267 unsigned clipdist_temp[2];
1268
1269 clipdist_temp[0] = r600_get_temp(&ctx);
1270 clipdist_temp[1] = r600_get_temp(&ctx);
1271
1272 /* need to convert a clipvertex write into clipdistance writes and not export
1273 the clip vertex anymore */
1274
1275 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
1276 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1277 shader->output[noutput].gpr = clipdist_temp[0];
1278 noutput++;
1279 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1280 shader->output[noutput].gpr = clipdist_temp[1];
1281 noutput++;
1282
1283 /* reset spi_sid for clipvertex output to avoid confusing spi */
1284 shader->output[ctx.cv_output].spi_sid = 0;
1285
1286 shader->clip_dist_write = 0xFF;
1287
1288 for (i = 0; i < 8; i++) {
1289 int oreg = i >> 2;
1290 int ochan = i & 3;
1291
1292 for (j = 0; j < 4; j++) {
1293 struct r600_bytecode_alu alu;
1294 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1295 alu.op = ALU_OP2_DOT4;
1296 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
1297 alu.src[0].chan = j;
1298
1299 alu.src[1].sel = 512 + i;
1300 alu.src[1].kc_bank = R600_UCP_CONST_BUFFER;
1301 alu.src[1].chan = j;
1302
1303 alu.dst.sel = clipdist_temp[oreg];
1304 alu.dst.chan = j;
1305 alu.dst.write = (j == ochan);
1306 if (j == 3)
1307 alu.last = 1;
1308 if (!use_llvm)
1309 r = r600_bytecode_add_alu(ctx.bc, &alu);
1310 if (r)
1311 return r;
1312 }
1313 }
1314 }
1315
1316 /* Add stream outputs. */
1317 if (ctx.type == TGSI_PROCESSOR_VERTEX && so.num_outputs && !use_llvm) {
1318 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1319
1320 /* Sanity checking. */
1321 if (so.num_outputs > PIPE_MAX_SHADER_OUTPUTS) {
1322 R600_ERR("Too many stream outputs: %d\n", so.num_outputs);
1323 r = -EINVAL;
1324 goto out_err;
1325 }
1326 for (i = 0; i < so.num_outputs; i++) {
1327 if (so.output[i].output_buffer >= 4) {
1328 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1329 so.output[i].output_buffer);
1330 r = -EINVAL;
1331 goto out_err;
1332 }
1333 }
1334
1335 /* Initialize locations where the outputs are stored. */
1336 for (i = 0; i < so.num_outputs; i++) {
1337 so_gpr[i] = shader->output[so.output[i].register_index].gpr;
1338
1339 /* Lower outputs with dst_offset < start_component.
1340 *
1341 * We can only output 4D vectors with a write mask, e.g. we can
1342 * only output the W component at offset 3, etc. If we want
1343 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1344 * to move it to X and output X. */
1345 if (so.output[i].dst_offset < so.output[i].start_component) {
1346 unsigned tmp = r600_get_temp(&ctx);
1347
1348 for (j = 0; j < so.output[i].num_components; j++) {
1349 struct r600_bytecode_alu alu;
1350 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1351 alu.op = ALU_OP1_MOV;
1352 alu.src[0].sel = so_gpr[i];
1353 alu.src[0].chan = so.output[i].start_component + j;
1354
1355 alu.dst.sel = tmp;
1356 alu.dst.chan = j;
1357 alu.dst.write = 1;
1358 if (j == so.output[i].num_components - 1)
1359 alu.last = 1;
1360 r = r600_bytecode_add_alu(ctx.bc, &alu);
1361 if (r)
1362 return r;
1363 }
1364 so.output[i].start_component = 0;
1365 so_gpr[i] = tmp;
1366 }
1367 }
1368
1369 /* Write outputs to buffers. */
1370 for (i = 0; i < so.num_outputs; i++) {
1371 struct r600_bytecode_output output;
1372
1373 memset(&output, 0, sizeof(struct r600_bytecode_output));
1374 output.gpr = so_gpr[i];
1375 output.elem_size = so.output[i].num_components;
1376 output.array_base = so.output[i].dst_offset - so.output[i].start_component;
1377 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1378 output.burst_count = 1;
1379 output.barrier = 1;
1380 /* array_size is an upper limit for the burst_count
1381 * with MEM_STREAM instructions */
1382 output.array_size = 0xFFF;
1383 output.comp_mask = ((1 << so.output[i].num_components) - 1) << so.output[i].start_component;
1384 if (ctx.bc->chip_class >= EVERGREEN) {
1385 switch (so.output[i].output_buffer) {
1386 case 0:
1387 output.op = CF_OP_MEM_STREAM0_BUF0;
1388 break;
1389 case 1:
1390 output.op = CF_OP_MEM_STREAM0_BUF1;
1391 break;
1392 case 2:
1393 output.op = CF_OP_MEM_STREAM0_BUF2;
1394 break;
1395 case 3:
1396 output.op = CF_OP_MEM_STREAM0_BUF3;
1397 break;
1398 }
1399 } else {
1400 switch (so.output[i].output_buffer) {
1401 case 0:
1402 output.op = CF_OP_MEM_STREAM0;
1403 break;
1404 case 1:
1405 output.op = CF_OP_MEM_STREAM1;
1406 break;
1407 case 2:
1408 output.op = CF_OP_MEM_STREAM2;
1409 break;
1410 case 3:
1411 output.op = CF_OP_MEM_STREAM3;
1412 break;
1413 }
1414 }
1415 r = r600_bytecode_add_output(ctx.bc, &output);
1416 if (r)
1417 goto out_err;
1418 }
1419 }
1420
1421 /* export output */
1422 for (i = 0, j = 0; i < noutput; i++, j++) {
1423 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1424 output[j].gpr = shader->output[i].gpr;
1425 output[j].elem_size = 3;
1426 output[j].swizzle_x = 0;
1427 output[j].swizzle_y = 1;
1428 output[j].swizzle_z = 2;
1429 output[j].swizzle_w = 3;
1430 output[j].burst_count = 1;
1431 output[j].barrier = 1;
1432 output[j].type = -1;
1433 output[j].op = CF_OP_EXPORT;
1434 switch (ctx.type) {
1435 case TGSI_PROCESSOR_VERTEX:
1436 switch (shader->output[i].name) {
1437 case TGSI_SEMANTIC_POSITION:
1438 output[j].array_base = next_pos_base++;
1439 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1440 break;
1441
1442 case TGSI_SEMANTIC_PSIZE:
1443 output[j].array_base = next_pos_base++;
1444 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1445 break;
1446 case TGSI_SEMANTIC_CLIPVERTEX:
1447 j--;
1448 break;
1449 case TGSI_SEMANTIC_CLIPDIST:
1450 output[j].array_base = next_pos_base++;
1451 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1452 /* spi_sid is 0 for clipdistance outputs that were generated
1453 * for clipvertex - we don't need to pass them to PS */
1454 if (shader->output[i].spi_sid) {
1455 j++;
1456 /* duplicate it as PARAM to pass to the pixel shader */
1457 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
1458 output[j].array_base = next_param_base++;
1459 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1460 }
1461 break;
1462 case TGSI_SEMANTIC_FOG:
1463 output[j].swizzle_y = 4; /* 0 */
1464 output[j].swizzle_z = 4; /* 0 */
1465 output[j].swizzle_w = 5; /* 1 */
1466 break;
1467 }
1468 break;
1469 case TGSI_PROCESSOR_FRAGMENT:
1470 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
1471 /* never export more colors than the number of CBs */
1472 if (next_pixel_base && next_pixel_base >= key.nr_cbufs) {
1473 /* skip export */
1474 j--;
1475 continue;
1476 }
1477 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1478 output[j].array_base = next_pixel_base++;
1479 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1480 shader->nr_ps_color_exports++;
1481 if (shader->fs_write_all && (rscreen->chip_class >= EVERGREEN)) {
1482 for (k = 1; k < key.nr_cbufs; k++) {
1483 j++;
1484 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1485 output[j].gpr = shader->output[i].gpr;
1486 output[j].elem_size = 3;
1487 output[j].swizzle_x = 0;
1488 output[j].swizzle_y = 1;
1489 output[j].swizzle_z = 2;
1490 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1491 output[j].burst_count = 1;
1492 output[j].barrier = 1;
1493 output[j].array_base = next_pixel_base++;
1494 output[j].op = CF_OP_EXPORT;
1495 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1496 shader->nr_ps_color_exports++;
1497 }
1498 }
1499 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
1500 output[j].array_base = 61;
1501 output[j].swizzle_x = 2;
1502 output[j].swizzle_y = 7;
1503 output[j].swizzle_z = output[j].swizzle_w = 7;
1504 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1505 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
1506 output[j].array_base = 61;
1507 output[j].swizzle_x = 7;
1508 output[j].swizzle_y = 1;
1509 output[j].swizzle_z = output[j].swizzle_w = 7;
1510 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1511 } else {
1512 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
1513 r = -EINVAL;
1514 goto out_err;
1515 }
1516 break;
1517 default:
1518 R600_ERR("unsupported processor type %d\n", ctx.type);
1519 r = -EINVAL;
1520 goto out_err;
1521 }
1522
1523 if (output[j].type==-1) {
1524 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1525 output[j].array_base = next_param_base++;
1526 }
1527 }
1528
1529 /* add fake position export */
1530 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_pos_base == 60) {
1531 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1532 output[j].gpr = 0;
1533 output[j].elem_size = 3;
1534 output[j].swizzle_x = 7;
1535 output[j].swizzle_y = 7;
1536 output[j].swizzle_z = 7;
1537 output[j].swizzle_w = 7;
1538 output[j].burst_count = 1;
1539 output[j].barrier = 1;
1540 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1541 output[j].array_base = next_pos_base;
1542 output[j].op = CF_OP_EXPORT;
1543 j++;
1544 }
1545
1546 /* add fake param output for vertex shader if no param is exported */
1547 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
1548 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1549 output[j].gpr = 0;
1550 output[j].elem_size = 3;
1551 output[j].swizzle_x = 7;
1552 output[j].swizzle_y = 7;
1553 output[j].swizzle_z = 7;
1554 output[j].swizzle_w = 7;
1555 output[j].burst_count = 1;
1556 output[j].barrier = 1;
1557 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1558 output[j].array_base = 0;
1559 output[j].op = CF_OP_EXPORT;
1560 j++;
1561 }
1562
1563 /* add fake pixel export */
1564 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && next_pixel_base == 0) {
1565 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1566 output[j].gpr = 0;
1567 output[j].elem_size = 3;
1568 output[j].swizzle_x = 7;
1569 output[j].swizzle_y = 7;
1570 output[j].swizzle_z = 7;
1571 output[j].swizzle_w = 7;
1572 output[j].burst_count = 1;
1573 output[j].barrier = 1;
1574 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1575 output[j].array_base = 0;
1576 output[j].op = CF_OP_EXPORT;
1577 j++;
1578 }
1579
1580 noutput = j;
1581
1582 /* set export done on last export of each type */
1583 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
1584 if (ctx.bc->chip_class < CAYMAN) {
1585 if (i == (noutput - 1)) {
1586 output[i].end_of_program = 1;
1587 }
1588 }
1589 if (!(output_done & (1 << output[i].type))) {
1590 output_done |= (1 << output[i].type);
1591 output[i].op = CF_OP_EXPORT_DONE;
1592 }
1593 }
1594 /* add output to bytecode */
1595 if (!use_llvm) {
1596 for (i = 0; i < noutput; i++) {
1597 r = r600_bytecode_add_output(ctx.bc, &output[i]);
1598 if (r)
1599 goto out_err;
1600 }
1601 }
1602 /* add program end */
1603 if (!use_llvm && ctx.bc->chip_class == CAYMAN)
1604 cm_bytecode_add_cf_end(ctx.bc);
1605
1606 /* check GPR limit - we have 124 = 128 - 4
1607 * (4 are reserved as alu clause temporary registers) */
1608 if (ctx.bc->ngpr > 124) {
1609 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
1610 r = -ENOMEM;
1611 goto out_err;
1612 }
1613
1614 free(ctx.literals);
1615 tgsi_parse_free(&ctx.parse);
1616 return 0;
1617 out_err:
1618 free(ctx.literals);
1619 tgsi_parse_free(&ctx.parse);
1620 return r;
1621 }
1622
1623 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
1624 {
1625 R600_ERR("%s tgsi opcode unsupported\n",
1626 tgsi_get_opcode_name(ctx->inst_info->tgsi_opcode));
1627 return -EINVAL;
1628 }
1629
1630 static int tgsi_end(struct r600_shader_ctx *ctx)
1631 {
1632 return 0;
1633 }
1634
1635 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
1636 const struct r600_shader_src *shader_src,
1637 unsigned chan)
1638 {
1639 bc_src->sel = shader_src->sel;
1640 bc_src->chan = shader_src->swizzle[chan];
1641 bc_src->neg = shader_src->neg;
1642 bc_src->abs = shader_src->abs;
1643 bc_src->rel = shader_src->rel;
1644 bc_src->value = shader_src->value[bc_src->chan];
1645 bc_src->kc_bank = shader_src->kc_bank;
1646 }
1647
1648 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
1649 {
1650 bc_src->abs = 1;
1651 bc_src->neg = 0;
1652 }
1653
1654 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
1655 {
1656 bc_src->neg = !bc_src->neg;
1657 }
1658
1659 static void tgsi_dst(struct r600_shader_ctx *ctx,
1660 const struct tgsi_full_dst_register *tgsi_dst,
1661 unsigned swizzle,
1662 struct r600_bytecode_alu_dst *r600_dst)
1663 {
1664 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1665
1666 r600_dst->sel = tgsi_dst->Register.Index;
1667 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
1668 r600_dst->chan = swizzle;
1669 r600_dst->write = 1;
1670 if (tgsi_dst->Register.Indirect)
1671 r600_dst->rel = V_SQ_REL_RELATIVE;
1672 if (inst->Instruction.Saturate) {
1673 r600_dst->clamp = 1;
1674 }
1675 }
1676
1677 static int tgsi_last_instruction(unsigned writemask)
1678 {
1679 int i, lasti = 0;
1680
1681 for (i = 0; i < 4; i++) {
1682 if (writemask & (1 << i)) {
1683 lasti = i;
1684 }
1685 }
1686 return lasti;
1687 }
1688
1689 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
1690 {
1691 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1692 struct r600_bytecode_alu alu;
1693 int i, j, r;
1694 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1695
1696 for (i = 0; i < lasti + 1; i++) {
1697 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1698 continue;
1699
1700 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1701 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1702
1703 alu.op = ctx->inst_info->op;
1704 if (!swap) {
1705 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1706 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
1707 }
1708 } else {
1709 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
1710 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1711 }
1712 /* handle some special cases */
1713 switch (ctx->inst_info->tgsi_opcode) {
1714 case TGSI_OPCODE_SUB:
1715 r600_bytecode_src_toggle_neg(&alu.src[1]);
1716 break;
1717 case TGSI_OPCODE_ABS:
1718 r600_bytecode_src_set_abs(&alu.src[0]);
1719 break;
1720 default:
1721 break;
1722 }
1723 if (i == lasti || trans_only) {
1724 alu.last = 1;
1725 }
1726 r = r600_bytecode_add_alu(ctx->bc, &alu);
1727 if (r)
1728 return r;
1729 }
1730 return 0;
1731 }
1732
1733 static int tgsi_op2(struct r600_shader_ctx *ctx)
1734 {
1735 return tgsi_op2_s(ctx, 0, 0);
1736 }
1737
1738 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
1739 {
1740 return tgsi_op2_s(ctx, 1, 0);
1741 }
1742
1743 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
1744 {
1745 return tgsi_op2_s(ctx, 0, 1);
1746 }
1747
1748 static int tgsi_ineg(struct r600_shader_ctx *ctx)
1749 {
1750 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1751 struct r600_bytecode_alu alu;
1752 int i, r;
1753 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1754
1755 for (i = 0; i < lasti + 1; i++) {
1756
1757 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1758 continue;
1759 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1760 alu.op = ctx->inst_info->op;
1761
1762 alu.src[0].sel = V_SQ_ALU_SRC_0;
1763
1764 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1765
1766 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1767
1768 if (i == lasti) {
1769 alu.last = 1;
1770 }
1771 r = r600_bytecode_add_alu(ctx->bc, &alu);
1772 if (r)
1773 return r;
1774 }
1775 return 0;
1776
1777 }
1778
1779 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
1780 {
1781 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1782 int i, j, r;
1783 struct r600_bytecode_alu alu;
1784 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1785
1786 for (i = 0 ; i < last_slot; i++) {
1787 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1788 alu.op = ctx->inst_info->op;
1789 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1790 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
1791
1792 /* RSQ should take the absolute value of src */
1793 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_RSQ) {
1794 r600_bytecode_src_set_abs(&alu.src[j]);
1795 }
1796 }
1797 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1798 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1799
1800 if (i == last_slot - 1)
1801 alu.last = 1;
1802 r = r600_bytecode_add_alu(ctx->bc, &alu);
1803 if (r)
1804 return r;
1805 }
1806 return 0;
1807 }
1808
1809 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
1810 {
1811 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1812 int i, j, k, r;
1813 struct r600_bytecode_alu alu;
1814 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1815 for (k = 0; k < last_slot; k++) {
1816 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
1817 continue;
1818
1819 for (i = 0 ; i < 4; i++) {
1820 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1821 alu.op = ctx->inst_info->op;
1822 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1823 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
1824 }
1825 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1826 alu.dst.write = (i == k);
1827 if (i == 3)
1828 alu.last = 1;
1829 r = r600_bytecode_add_alu(ctx->bc, &alu);
1830 if (r)
1831 return r;
1832 }
1833 }
1834 return 0;
1835 }
1836
1837 /*
1838 * r600 - trunc to -PI..PI range
1839 * r700 - normalize by dividing by 2PI
1840 * see fdo bug 27901
1841 */
1842 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
1843 {
1844 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
1845 static float double_pi = 3.1415926535 * 2;
1846 static float neg_pi = -3.1415926535;
1847
1848 int r;
1849 struct r600_bytecode_alu alu;
1850
1851 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1852 alu.op = ALU_OP3_MULADD;
1853 alu.is_op3 = 1;
1854
1855 alu.dst.chan = 0;
1856 alu.dst.sel = ctx->temp_reg;
1857 alu.dst.write = 1;
1858
1859 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
1860
1861 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1862 alu.src[1].chan = 0;
1863 alu.src[1].value = *(uint32_t *)&half_inv_pi;
1864 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1865 alu.src[2].chan = 0;
1866 alu.last = 1;
1867 r = r600_bytecode_add_alu(ctx->bc, &alu);
1868 if (r)
1869 return r;
1870
1871 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1872 alu.op = ALU_OP1_FRACT;
1873
1874 alu.dst.chan = 0;
1875 alu.dst.sel = ctx->temp_reg;
1876 alu.dst.write = 1;
1877
1878 alu.src[0].sel = ctx->temp_reg;
1879 alu.src[0].chan = 0;
1880 alu.last = 1;
1881 r = r600_bytecode_add_alu(ctx->bc, &alu);
1882 if (r)
1883 return r;
1884
1885 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1886 alu.op = ALU_OP3_MULADD;
1887 alu.is_op3 = 1;
1888
1889 alu.dst.chan = 0;
1890 alu.dst.sel = ctx->temp_reg;
1891 alu.dst.write = 1;
1892
1893 alu.src[0].sel = ctx->temp_reg;
1894 alu.src[0].chan = 0;
1895
1896 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1897 alu.src[1].chan = 0;
1898 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1899 alu.src[2].chan = 0;
1900
1901 if (ctx->bc->chip_class == R600) {
1902 alu.src[1].value = *(uint32_t *)&double_pi;
1903 alu.src[2].value = *(uint32_t *)&neg_pi;
1904 } else {
1905 alu.src[1].sel = V_SQ_ALU_SRC_1;
1906 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1907 alu.src[2].neg = 1;
1908 }
1909
1910 alu.last = 1;
1911 r = r600_bytecode_add_alu(ctx->bc, &alu);
1912 if (r)
1913 return r;
1914 return 0;
1915 }
1916
1917 static int cayman_trig(struct r600_shader_ctx *ctx)
1918 {
1919 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1920 struct r600_bytecode_alu alu;
1921 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1922 int i, r;
1923
1924 r = tgsi_setup_trig(ctx);
1925 if (r)
1926 return r;
1927
1928
1929 for (i = 0; i < last_slot; i++) {
1930 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1931 alu.op = ctx->inst_info->op;
1932 alu.dst.chan = i;
1933
1934 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1935 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1936
1937 alu.src[0].sel = ctx->temp_reg;
1938 alu.src[0].chan = 0;
1939 if (i == last_slot - 1)
1940 alu.last = 1;
1941 r = r600_bytecode_add_alu(ctx->bc, &alu);
1942 if (r)
1943 return r;
1944 }
1945 return 0;
1946 }
1947
1948 static int tgsi_trig(struct r600_shader_ctx *ctx)
1949 {
1950 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1951 struct r600_bytecode_alu alu;
1952 int i, r;
1953 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1954
1955 r = tgsi_setup_trig(ctx);
1956 if (r)
1957 return r;
1958
1959 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1960 alu.op = ctx->inst_info->op;
1961 alu.dst.chan = 0;
1962 alu.dst.sel = ctx->temp_reg;
1963 alu.dst.write = 1;
1964
1965 alu.src[0].sel = ctx->temp_reg;
1966 alu.src[0].chan = 0;
1967 alu.last = 1;
1968 r = r600_bytecode_add_alu(ctx->bc, &alu);
1969 if (r)
1970 return r;
1971
1972 /* replicate result */
1973 for (i = 0; i < lasti + 1; i++) {
1974 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1975 continue;
1976
1977 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1978 alu.op = ALU_OP1_MOV;
1979
1980 alu.src[0].sel = ctx->temp_reg;
1981 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1982 if (i == lasti)
1983 alu.last = 1;
1984 r = r600_bytecode_add_alu(ctx->bc, &alu);
1985 if (r)
1986 return r;
1987 }
1988 return 0;
1989 }
1990
1991 static int tgsi_scs(struct r600_shader_ctx *ctx)
1992 {
1993 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1994 struct r600_bytecode_alu alu;
1995 int i, r;
1996
1997 /* We'll only need the trig stuff if we are going to write to the
1998 * X or Y components of the destination vector.
1999 */
2000 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
2001 r = tgsi_setup_trig(ctx);
2002 if (r)
2003 return r;
2004 }
2005
2006 /* dst.x = COS */
2007 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2008 if (ctx->bc->chip_class == CAYMAN) {
2009 for (i = 0 ; i < 3; i++) {
2010 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2011 alu.op = ALU_OP1_COS;
2012 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2013
2014 if (i == 0)
2015 alu.dst.write = 1;
2016 else
2017 alu.dst.write = 0;
2018 alu.src[0].sel = ctx->temp_reg;
2019 alu.src[0].chan = 0;
2020 if (i == 2)
2021 alu.last = 1;
2022 r = r600_bytecode_add_alu(ctx->bc, &alu);
2023 if (r)
2024 return r;
2025 }
2026 } else {
2027 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2028 alu.op = ALU_OP1_COS;
2029 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2030
2031 alu.src[0].sel = ctx->temp_reg;
2032 alu.src[0].chan = 0;
2033 alu.last = 1;
2034 r = r600_bytecode_add_alu(ctx->bc, &alu);
2035 if (r)
2036 return r;
2037 }
2038 }
2039
2040 /* dst.y = SIN */
2041 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2042 if (ctx->bc->chip_class == CAYMAN) {
2043 for (i = 0 ; i < 3; i++) {
2044 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2045 alu.op = ALU_OP1_SIN;
2046 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2047 if (i == 1)
2048 alu.dst.write = 1;
2049 else
2050 alu.dst.write = 0;
2051 alu.src[0].sel = ctx->temp_reg;
2052 alu.src[0].chan = 0;
2053 if (i == 2)
2054 alu.last = 1;
2055 r = r600_bytecode_add_alu(ctx->bc, &alu);
2056 if (r)
2057 return r;
2058 }
2059 } else {
2060 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2061 alu.op = ALU_OP1_SIN;
2062 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2063
2064 alu.src[0].sel = ctx->temp_reg;
2065 alu.src[0].chan = 0;
2066 alu.last = 1;
2067 r = r600_bytecode_add_alu(ctx->bc, &alu);
2068 if (r)
2069 return r;
2070 }
2071 }
2072
2073 /* dst.z = 0.0; */
2074 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2075 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2076
2077 alu.op = ALU_OP1_MOV;
2078
2079 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2080
2081 alu.src[0].sel = V_SQ_ALU_SRC_0;
2082 alu.src[0].chan = 0;
2083
2084 alu.last = 1;
2085
2086 r = r600_bytecode_add_alu(ctx->bc, &alu);
2087 if (r)
2088 return r;
2089 }
2090
2091 /* dst.w = 1.0; */
2092 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2093 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2094
2095 alu.op = ALU_OP1_MOV;
2096
2097 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2098
2099 alu.src[0].sel = V_SQ_ALU_SRC_1;
2100 alu.src[0].chan = 0;
2101
2102 alu.last = 1;
2103
2104 r = r600_bytecode_add_alu(ctx->bc, &alu);
2105 if (r)
2106 return r;
2107 }
2108
2109 return 0;
2110 }
2111
2112 static int tgsi_kill(struct r600_shader_ctx *ctx)
2113 {
2114 struct r600_bytecode_alu alu;
2115 int i, r;
2116
2117 for (i = 0; i < 4; i++) {
2118 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2119 alu.op = ctx->inst_info->op;
2120
2121 alu.dst.chan = i;
2122
2123 alu.src[0].sel = V_SQ_ALU_SRC_0;
2124
2125 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
2126 alu.src[1].sel = V_SQ_ALU_SRC_1;
2127 alu.src[1].neg = 1;
2128 } else {
2129 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2130 }
2131 if (i == 3) {
2132 alu.last = 1;
2133 }
2134 r = r600_bytecode_add_alu(ctx->bc, &alu);
2135 if (r)
2136 return r;
2137 }
2138
2139 /* kill must be last in ALU */
2140 ctx->bc->force_add_cf = 1;
2141 ctx->shader->uses_kill = TRUE;
2142 return 0;
2143 }
2144
2145 static int tgsi_lit(struct r600_shader_ctx *ctx)
2146 {
2147 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2148 struct r600_bytecode_alu alu;
2149 int r;
2150
2151 /* tmp.x = max(src.y, 0.0) */
2152 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2153 alu.op = ALU_OP2_MAX;
2154 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
2155 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2156 alu.src[1].chan = 1;
2157
2158 alu.dst.sel = ctx->temp_reg;
2159 alu.dst.chan = 0;
2160 alu.dst.write = 1;
2161
2162 alu.last = 1;
2163 r = r600_bytecode_add_alu(ctx->bc, &alu);
2164 if (r)
2165 return r;
2166
2167 if (inst->Dst[0].Register.WriteMask & (1 << 2))
2168 {
2169 int chan;
2170 int sel;
2171 int i;
2172
2173 if (ctx->bc->chip_class == CAYMAN) {
2174 for (i = 0; i < 3; i++) {
2175 /* tmp.z = log(tmp.x) */
2176 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2177 alu.op = ALU_OP1_LOG_CLAMPED;
2178 alu.src[0].sel = ctx->temp_reg;
2179 alu.src[0].chan = 0;
2180 alu.dst.sel = ctx->temp_reg;
2181 alu.dst.chan = i;
2182 if (i == 2) {
2183 alu.dst.write = 1;
2184 alu.last = 1;
2185 } else
2186 alu.dst.write = 0;
2187
2188 r = r600_bytecode_add_alu(ctx->bc, &alu);
2189 if (r)
2190 return r;
2191 }
2192 } else {
2193 /* tmp.z = log(tmp.x) */
2194 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2195 alu.op = ALU_OP1_LOG_CLAMPED;
2196 alu.src[0].sel = ctx->temp_reg;
2197 alu.src[0].chan = 0;
2198 alu.dst.sel = ctx->temp_reg;
2199 alu.dst.chan = 2;
2200 alu.dst.write = 1;
2201 alu.last = 1;
2202 r = r600_bytecode_add_alu(ctx->bc, &alu);
2203 if (r)
2204 return r;
2205 }
2206
2207 chan = alu.dst.chan;
2208 sel = alu.dst.sel;
2209
2210 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
2211 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2212 alu.op = ALU_OP3_MUL_LIT;
2213 alu.src[0].sel = sel;
2214 alu.src[0].chan = chan;
2215 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
2216 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
2217 alu.dst.sel = ctx->temp_reg;
2218 alu.dst.chan = 0;
2219 alu.dst.write = 1;
2220 alu.is_op3 = 1;
2221 alu.last = 1;
2222 r = r600_bytecode_add_alu(ctx->bc, &alu);
2223 if (r)
2224 return r;
2225
2226 if (ctx->bc->chip_class == CAYMAN) {
2227 for (i = 0; i < 3; i++) {
2228 /* dst.z = exp(tmp.x) */
2229 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2230 alu.op = ALU_OP1_EXP_IEEE;
2231 alu.src[0].sel = ctx->temp_reg;
2232 alu.src[0].chan = 0;
2233 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2234 if (i == 2) {
2235 alu.dst.write = 1;
2236 alu.last = 1;
2237 } else
2238 alu.dst.write = 0;
2239 r = r600_bytecode_add_alu(ctx->bc, &alu);
2240 if (r)
2241 return r;
2242 }
2243 } else {
2244 /* dst.z = exp(tmp.x) */
2245 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2246 alu.op = ALU_OP1_EXP_IEEE;
2247 alu.src[0].sel = ctx->temp_reg;
2248 alu.src[0].chan = 0;
2249 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2250 alu.last = 1;
2251 r = r600_bytecode_add_alu(ctx->bc, &alu);
2252 if (r)
2253 return r;
2254 }
2255 }
2256
2257 /* dst.x, <- 1.0 */
2258 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2259 alu.op = ALU_OP1_MOV;
2260 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
2261 alu.src[0].chan = 0;
2262 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2263 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
2264 r = r600_bytecode_add_alu(ctx->bc, &alu);
2265 if (r)
2266 return r;
2267
2268 /* dst.y = max(src.x, 0.0) */
2269 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2270 alu.op = ALU_OP2_MAX;
2271 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2272 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2273 alu.src[1].chan = 0;
2274 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2275 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
2276 r = r600_bytecode_add_alu(ctx->bc, &alu);
2277 if (r)
2278 return r;
2279
2280 /* dst.w, <- 1.0 */
2281 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2282 alu.op = ALU_OP1_MOV;
2283 alu.src[0].sel = V_SQ_ALU_SRC_1;
2284 alu.src[0].chan = 0;
2285 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2286 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
2287 alu.last = 1;
2288 r = r600_bytecode_add_alu(ctx->bc, &alu);
2289 if (r)
2290 return r;
2291
2292 return 0;
2293 }
2294
2295 static int tgsi_rsq(struct r600_shader_ctx *ctx)
2296 {
2297 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2298 struct r600_bytecode_alu alu;
2299 int i, r;
2300
2301 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2302
2303 /* XXX:
2304 * For state trackers other than OpenGL, we'll want to use
2305 * _RECIPSQRT_IEEE instead.
2306 */
2307 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
2308
2309 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2310 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2311 r600_bytecode_src_set_abs(&alu.src[i]);
2312 }
2313 alu.dst.sel = ctx->temp_reg;
2314 alu.dst.write = 1;
2315 alu.last = 1;
2316 r = r600_bytecode_add_alu(ctx->bc, &alu);
2317 if (r)
2318 return r;
2319 /* replicate result */
2320 return tgsi_helper_tempx_replicate(ctx);
2321 }
2322
2323 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
2324 {
2325 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2326 struct r600_bytecode_alu alu;
2327 int i, r;
2328
2329 for (i = 0; i < 4; i++) {
2330 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2331 alu.src[0].sel = ctx->temp_reg;
2332 alu.op = ALU_OP1_MOV;
2333 alu.dst.chan = i;
2334 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2335 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2336 if (i == 3)
2337 alu.last = 1;
2338 r = r600_bytecode_add_alu(ctx->bc, &alu);
2339 if (r)
2340 return r;
2341 }
2342 return 0;
2343 }
2344
2345 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
2346 {
2347 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2348 struct r600_bytecode_alu alu;
2349 int i, r;
2350
2351 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2352 alu.op = ctx->inst_info->op;
2353 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2354 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2355 }
2356 alu.dst.sel = ctx->temp_reg;
2357 alu.dst.write = 1;
2358 alu.last = 1;
2359 r = r600_bytecode_add_alu(ctx->bc, &alu);
2360 if (r)
2361 return r;
2362 /* replicate result */
2363 return tgsi_helper_tempx_replicate(ctx);
2364 }
2365
2366 static int cayman_pow(struct r600_shader_ctx *ctx)
2367 {
2368 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2369 int i, r;
2370 struct r600_bytecode_alu alu;
2371 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2372
2373 for (i = 0; i < 3; i++) {
2374 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2375 alu.op = ALU_OP1_LOG_IEEE;
2376 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2377 alu.dst.sel = ctx->temp_reg;
2378 alu.dst.chan = i;
2379 alu.dst.write = 1;
2380 if (i == 2)
2381 alu.last = 1;
2382 r = r600_bytecode_add_alu(ctx->bc, &alu);
2383 if (r)
2384 return r;
2385 }
2386
2387 /* b * LOG2(a) */
2388 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2389 alu.op = ALU_OP2_MUL;
2390 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2391 alu.src[1].sel = ctx->temp_reg;
2392 alu.dst.sel = ctx->temp_reg;
2393 alu.dst.write = 1;
2394 alu.last = 1;
2395 r = r600_bytecode_add_alu(ctx->bc, &alu);
2396 if (r)
2397 return r;
2398
2399 for (i = 0; i < last_slot; i++) {
2400 /* POW(a,b) = EXP2(b * LOG2(a))*/
2401 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2402 alu.op = ALU_OP1_EXP_IEEE;
2403 alu.src[0].sel = ctx->temp_reg;
2404
2405 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2406 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2407 if (i == last_slot - 1)
2408 alu.last = 1;
2409 r = r600_bytecode_add_alu(ctx->bc, &alu);
2410 if (r)
2411 return r;
2412 }
2413 return 0;
2414 }
2415
2416 static int tgsi_pow(struct r600_shader_ctx *ctx)
2417 {
2418 struct r600_bytecode_alu alu;
2419 int r;
2420
2421 /* LOG2(a) */
2422 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2423 alu.op = ALU_OP1_LOG_IEEE;
2424 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2425 alu.dst.sel = ctx->temp_reg;
2426 alu.dst.write = 1;
2427 alu.last = 1;
2428 r = r600_bytecode_add_alu(ctx->bc, &alu);
2429 if (r)
2430 return r;
2431 /* b * LOG2(a) */
2432 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2433 alu.op = ALU_OP2_MUL;
2434 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2435 alu.src[1].sel = ctx->temp_reg;
2436 alu.dst.sel = ctx->temp_reg;
2437 alu.dst.write = 1;
2438 alu.last = 1;
2439 r = r600_bytecode_add_alu(ctx->bc, &alu);
2440 if (r)
2441 return r;
2442 /* POW(a,b) = EXP2(b * LOG2(a))*/
2443 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2444 alu.op = ALU_OP1_EXP_IEEE;
2445 alu.src[0].sel = ctx->temp_reg;
2446 alu.dst.sel = ctx->temp_reg;
2447 alu.dst.write = 1;
2448 alu.last = 1;
2449 r = r600_bytecode_add_alu(ctx->bc, &alu);
2450 if (r)
2451 return r;
2452 return tgsi_helper_tempx_replicate(ctx);
2453 }
2454
2455 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
2456 {
2457 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2458 struct r600_bytecode_alu alu;
2459 int i, r, j;
2460 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2461 int tmp0 = ctx->temp_reg;
2462 int tmp1 = r600_get_temp(ctx);
2463 int tmp2 = r600_get_temp(ctx);
2464 int tmp3 = r600_get_temp(ctx);
2465 /* Unsigned path:
2466 *
2467 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
2468 *
2469 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
2470 * 2. tmp0.z = lo (tmp0.x * src2)
2471 * 3. tmp0.w = -tmp0.z
2472 * 4. tmp0.y = hi (tmp0.x * src2)
2473 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
2474 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
2475 * 7. tmp1.x = tmp0.x - tmp0.w
2476 * 8. tmp1.y = tmp0.x + tmp0.w
2477 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
2478 * 10. tmp0.z = hi(tmp0.x * src1) = q
2479 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
2480 *
2481 * 12. tmp0.w = src1 - tmp0.y = r
2482 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
2483 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
2484 *
2485 * if DIV
2486 *
2487 * 15. tmp1.z = tmp0.z + 1 = q + 1
2488 * 16. tmp1.w = tmp0.z - 1 = q - 1
2489 *
2490 * else MOD
2491 *
2492 * 15. tmp1.z = tmp0.w - src2 = r - src2
2493 * 16. tmp1.w = tmp0.w + src2 = r + src2
2494 *
2495 * endif
2496 *
2497 * 17. tmp1.x = tmp1.x & tmp1.y
2498 *
2499 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
2500 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
2501 *
2502 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
2503 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
2504 *
2505 * Signed path:
2506 *
2507 * Same as unsigned, using abs values of the operands,
2508 * and fixing the sign of the result in the end.
2509 */
2510
2511 for (i = 0; i < 4; i++) {
2512 if (!(write_mask & (1<<i)))
2513 continue;
2514
2515 if (signed_op) {
2516
2517 /* tmp2.x = -src0 */
2518 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2519 alu.op = ALU_OP2_SUB_INT;
2520
2521 alu.dst.sel = tmp2;
2522 alu.dst.chan = 0;
2523 alu.dst.write = 1;
2524
2525 alu.src[0].sel = V_SQ_ALU_SRC_0;
2526
2527 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2528
2529 alu.last = 1;
2530 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2531 return r;
2532
2533 /* tmp2.y = -src1 */
2534 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2535 alu.op = ALU_OP2_SUB_INT;
2536
2537 alu.dst.sel = tmp2;
2538 alu.dst.chan = 1;
2539 alu.dst.write = 1;
2540
2541 alu.src[0].sel = V_SQ_ALU_SRC_0;
2542
2543 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2544
2545 alu.last = 1;
2546 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2547 return r;
2548
2549 /* tmp2.z sign bit is set if src0 and src2 signs are different */
2550 /* it will be a sign of the quotient */
2551 if (!mod) {
2552
2553 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2554 alu.op = ALU_OP2_XOR_INT;
2555
2556 alu.dst.sel = tmp2;
2557 alu.dst.chan = 2;
2558 alu.dst.write = 1;
2559
2560 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2561 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2562
2563 alu.last = 1;
2564 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2565 return r;
2566 }
2567
2568 /* tmp2.x = |src0| */
2569 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2570 alu.op = ALU_OP3_CNDGE_INT;
2571 alu.is_op3 = 1;
2572
2573 alu.dst.sel = tmp2;
2574 alu.dst.chan = 0;
2575 alu.dst.write = 1;
2576
2577 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2578 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2579 alu.src[2].sel = tmp2;
2580 alu.src[2].chan = 0;
2581
2582 alu.last = 1;
2583 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2584 return r;
2585
2586 /* tmp2.y = |src1| */
2587 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2588 alu.op = ALU_OP3_CNDGE_INT;
2589 alu.is_op3 = 1;
2590
2591 alu.dst.sel = tmp2;
2592 alu.dst.chan = 1;
2593 alu.dst.write = 1;
2594
2595 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2596 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2597 alu.src[2].sel = tmp2;
2598 alu.src[2].chan = 1;
2599
2600 alu.last = 1;
2601 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2602 return r;
2603
2604 }
2605
2606 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
2607 if (ctx->bc->chip_class == CAYMAN) {
2608 /* tmp3.x = u2f(src2) */
2609 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2610 alu.op = ALU_OP1_UINT_TO_FLT;
2611
2612 alu.dst.sel = tmp3;
2613 alu.dst.chan = 0;
2614 alu.dst.write = 1;
2615
2616 if (signed_op) {
2617 alu.src[0].sel = tmp2;
2618 alu.src[0].chan = 1;
2619 } else {
2620 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2621 }
2622
2623 alu.last = 1;
2624 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2625 return r;
2626
2627 /* tmp0.x = recip(tmp3.x) */
2628 for (j = 0 ; j < 3; j++) {
2629 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2630 alu.op = ALU_OP1_RECIP_IEEE;
2631
2632 alu.dst.sel = tmp0;
2633 alu.dst.chan = j;
2634 alu.dst.write = (j == 0);
2635
2636 alu.src[0].sel = tmp3;
2637 alu.src[0].chan = 0;
2638
2639 if (j == 2)
2640 alu.last = 1;
2641 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2642 return r;
2643 }
2644
2645 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2646 alu.op = ALU_OP2_MUL;
2647
2648 alu.src[0].sel = tmp0;
2649 alu.src[0].chan = 0;
2650
2651 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2652 alu.src[1].value = 0x4f800000;
2653
2654 alu.dst.sel = tmp3;
2655 alu.dst.write = 1;
2656 alu.last = 1;
2657 r = r600_bytecode_add_alu(ctx->bc, &alu);
2658 if (r)
2659 return r;
2660
2661 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2662 alu.op = ALU_OP1_FLT_TO_UINT;
2663
2664 alu.dst.sel = tmp0;
2665 alu.dst.chan = 0;
2666 alu.dst.write = 1;
2667
2668 alu.src[0].sel = tmp3;
2669 alu.src[0].chan = 0;
2670
2671 alu.last = 1;
2672 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2673 return r;
2674
2675 } else {
2676 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2677 alu.op = ALU_OP1_RECIP_UINT;
2678
2679 alu.dst.sel = tmp0;
2680 alu.dst.chan = 0;
2681 alu.dst.write = 1;
2682
2683 if (signed_op) {
2684 alu.src[0].sel = tmp2;
2685 alu.src[0].chan = 1;
2686 } else {
2687 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2688 }
2689
2690 alu.last = 1;
2691 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2692 return r;
2693 }
2694
2695 /* 2. tmp0.z = lo (tmp0.x * src2) */
2696 if (ctx->bc->chip_class == CAYMAN) {
2697 for (j = 0 ; j < 4; j++) {
2698 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2699 alu.op = ALU_OP2_MULLO_UINT;
2700
2701 alu.dst.sel = tmp0;
2702 alu.dst.chan = j;
2703 alu.dst.write = (j == 2);
2704
2705 alu.src[0].sel = tmp0;
2706 alu.src[0].chan = 0;
2707 if (signed_op) {
2708 alu.src[1].sel = tmp2;
2709 alu.src[1].chan = 1;
2710 } else {
2711 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2712 }
2713
2714 alu.last = (j == 3);
2715 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2716 return r;
2717 }
2718 } else {
2719 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2720 alu.op = ALU_OP2_MULLO_UINT;
2721
2722 alu.dst.sel = tmp0;
2723 alu.dst.chan = 2;
2724 alu.dst.write = 1;
2725
2726 alu.src[0].sel = tmp0;
2727 alu.src[0].chan = 0;
2728 if (signed_op) {
2729 alu.src[1].sel = tmp2;
2730 alu.src[1].chan = 1;
2731 } else {
2732 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2733 }
2734
2735 alu.last = 1;
2736 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2737 return r;
2738 }
2739
2740 /* 3. tmp0.w = -tmp0.z */
2741 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2742 alu.op = ALU_OP2_SUB_INT;
2743
2744 alu.dst.sel = tmp0;
2745 alu.dst.chan = 3;
2746 alu.dst.write = 1;
2747
2748 alu.src[0].sel = V_SQ_ALU_SRC_0;
2749 alu.src[1].sel = tmp0;
2750 alu.src[1].chan = 2;
2751
2752 alu.last = 1;
2753 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2754 return r;
2755
2756 /* 4. tmp0.y = hi (tmp0.x * src2) */
2757 if (ctx->bc->chip_class == CAYMAN) {
2758 for (j = 0 ; j < 4; j++) {
2759 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2760 alu.op = ALU_OP2_MULHI_UINT;
2761
2762 alu.dst.sel = tmp0;
2763 alu.dst.chan = j;
2764 alu.dst.write = (j == 1);
2765
2766 alu.src[0].sel = tmp0;
2767 alu.src[0].chan = 0;
2768
2769 if (signed_op) {
2770 alu.src[1].sel = tmp2;
2771 alu.src[1].chan = 1;
2772 } else {
2773 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2774 }
2775 alu.last = (j == 3);
2776 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2777 return r;
2778 }
2779 } else {
2780 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2781 alu.op = ALU_OP2_MULHI_UINT;
2782
2783 alu.dst.sel = tmp0;
2784 alu.dst.chan = 1;
2785 alu.dst.write = 1;
2786
2787 alu.src[0].sel = tmp0;
2788 alu.src[0].chan = 0;
2789
2790 if (signed_op) {
2791 alu.src[1].sel = tmp2;
2792 alu.src[1].chan = 1;
2793 } else {
2794 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2795 }
2796
2797 alu.last = 1;
2798 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2799 return r;
2800 }
2801
2802 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
2803 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2804 alu.op = ALU_OP3_CNDE_INT;
2805 alu.is_op3 = 1;
2806
2807 alu.dst.sel = tmp0;
2808 alu.dst.chan = 2;
2809 alu.dst.write = 1;
2810
2811 alu.src[0].sel = tmp0;
2812 alu.src[0].chan = 1;
2813 alu.src[1].sel = tmp0;
2814 alu.src[1].chan = 3;
2815 alu.src[2].sel = tmp0;
2816 alu.src[2].chan = 2;
2817
2818 alu.last = 1;
2819 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2820 return r;
2821
2822 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
2823 if (ctx->bc->chip_class == CAYMAN) {
2824 for (j = 0 ; j < 4; j++) {
2825 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2826 alu.op = ALU_OP2_MULHI_UINT;
2827
2828 alu.dst.sel = tmp0;
2829 alu.dst.chan = j;
2830 alu.dst.write = (j == 3);
2831
2832 alu.src[0].sel = tmp0;
2833 alu.src[0].chan = 2;
2834
2835 alu.src[1].sel = tmp0;
2836 alu.src[1].chan = 0;
2837
2838 alu.last = (j == 3);
2839 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2840 return r;
2841 }
2842 } else {
2843 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2844 alu.op = ALU_OP2_MULHI_UINT;
2845
2846 alu.dst.sel = tmp0;
2847 alu.dst.chan = 3;
2848 alu.dst.write = 1;
2849
2850 alu.src[0].sel = tmp0;
2851 alu.src[0].chan = 2;
2852
2853 alu.src[1].sel = tmp0;
2854 alu.src[1].chan = 0;
2855
2856 alu.last = 1;
2857 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2858 return r;
2859 }
2860
2861 /* 7. tmp1.x = tmp0.x - tmp0.w */
2862 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2863 alu.op = ALU_OP2_SUB_INT;
2864
2865 alu.dst.sel = tmp1;
2866 alu.dst.chan = 0;
2867 alu.dst.write = 1;
2868
2869 alu.src[0].sel = tmp0;
2870 alu.src[0].chan = 0;
2871 alu.src[1].sel = tmp0;
2872 alu.src[1].chan = 3;
2873
2874 alu.last = 1;
2875 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2876 return r;
2877
2878 /* 8. tmp1.y = tmp0.x + tmp0.w */
2879 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2880 alu.op = ALU_OP2_ADD_INT;
2881
2882 alu.dst.sel = tmp1;
2883 alu.dst.chan = 1;
2884 alu.dst.write = 1;
2885
2886 alu.src[0].sel = tmp0;
2887 alu.src[0].chan = 0;
2888 alu.src[1].sel = tmp0;
2889 alu.src[1].chan = 3;
2890
2891 alu.last = 1;
2892 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2893 return r;
2894
2895 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
2896 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2897 alu.op = ALU_OP3_CNDE_INT;
2898 alu.is_op3 = 1;
2899
2900 alu.dst.sel = tmp0;
2901 alu.dst.chan = 0;
2902 alu.dst.write = 1;
2903
2904 alu.src[0].sel = tmp0;
2905 alu.src[0].chan = 1;
2906 alu.src[1].sel = tmp1;
2907 alu.src[1].chan = 1;
2908 alu.src[2].sel = tmp1;
2909 alu.src[2].chan = 0;
2910
2911 alu.last = 1;
2912 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2913 return r;
2914
2915 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
2916 if (ctx->bc->chip_class == CAYMAN) {
2917 for (j = 0 ; j < 4; j++) {
2918 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2919 alu.op = ALU_OP2_MULHI_UINT;
2920
2921 alu.dst.sel = tmp0;
2922 alu.dst.chan = j;
2923 alu.dst.write = (j == 2);
2924
2925 alu.src[0].sel = tmp0;
2926 alu.src[0].chan = 0;
2927
2928 if (signed_op) {
2929 alu.src[1].sel = tmp2;
2930 alu.src[1].chan = 0;
2931 } else {
2932 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2933 }
2934
2935 alu.last = (j == 3);
2936 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2937 return r;
2938 }
2939 } else {
2940 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2941 alu.op = ALU_OP2_MULHI_UINT;
2942
2943 alu.dst.sel = tmp0;
2944 alu.dst.chan = 2;
2945 alu.dst.write = 1;
2946
2947 alu.src[0].sel = tmp0;
2948 alu.src[0].chan = 0;
2949
2950 if (signed_op) {
2951 alu.src[1].sel = tmp2;
2952 alu.src[1].chan = 0;
2953 } else {
2954 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2955 }
2956
2957 alu.last = 1;
2958 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2959 return r;
2960 }
2961
2962 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
2963 if (ctx->bc->chip_class == CAYMAN) {
2964 for (j = 0 ; j < 4; j++) {
2965 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2966 alu.op = ALU_OP2_MULLO_UINT;
2967
2968 alu.dst.sel = tmp0;
2969 alu.dst.chan = j;
2970 alu.dst.write = (j == 1);
2971
2972 if (signed_op) {
2973 alu.src[0].sel = tmp2;
2974 alu.src[0].chan = 1;
2975 } else {
2976 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2977 }
2978
2979 alu.src[1].sel = tmp0;
2980 alu.src[1].chan = 2;
2981
2982 alu.last = (j == 3);
2983 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2984 return r;
2985 }
2986 } else {
2987 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2988 alu.op = ALU_OP2_MULLO_UINT;
2989
2990 alu.dst.sel = tmp0;
2991 alu.dst.chan = 1;
2992 alu.dst.write = 1;
2993
2994 if (signed_op) {
2995 alu.src[0].sel = tmp2;
2996 alu.src[0].chan = 1;
2997 } else {
2998 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2999 }
3000
3001 alu.src[1].sel = tmp0;
3002 alu.src[1].chan = 2;
3003
3004 alu.last = 1;
3005 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3006 return r;
3007 }
3008
3009 /* 12. tmp0.w = src1 - tmp0.y = r */
3010 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3011 alu.op = ALU_OP2_SUB_INT;
3012
3013 alu.dst.sel = tmp0;
3014 alu.dst.chan = 3;
3015 alu.dst.write = 1;
3016
3017 if (signed_op) {
3018 alu.src[0].sel = tmp2;
3019 alu.src[0].chan = 0;
3020 } else {
3021 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3022 }
3023
3024 alu.src[1].sel = tmp0;
3025 alu.src[1].chan = 1;
3026
3027 alu.last = 1;
3028 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3029 return r;
3030
3031 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
3032 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3033 alu.op = ALU_OP2_SETGE_UINT;
3034
3035 alu.dst.sel = tmp1;
3036 alu.dst.chan = 0;
3037 alu.dst.write = 1;
3038
3039 alu.src[0].sel = tmp0;
3040 alu.src[0].chan = 3;
3041 if (signed_op) {
3042 alu.src[1].sel = tmp2;
3043 alu.src[1].chan = 1;
3044 } else {
3045 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3046 }
3047
3048 alu.last = 1;
3049 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3050 return r;
3051
3052 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
3053 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3054 alu.op = ALU_OP2_SETGE_UINT;
3055
3056 alu.dst.sel = tmp1;
3057 alu.dst.chan = 1;
3058 alu.dst.write = 1;
3059
3060 if (signed_op) {
3061 alu.src[0].sel = tmp2;
3062 alu.src[0].chan = 0;
3063 } else {
3064 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3065 }
3066
3067 alu.src[1].sel = tmp0;
3068 alu.src[1].chan = 1;
3069
3070 alu.last = 1;
3071 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3072 return r;
3073
3074 if (mod) { /* UMOD */
3075
3076 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
3077 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3078 alu.op = ALU_OP2_SUB_INT;
3079
3080 alu.dst.sel = tmp1;
3081 alu.dst.chan = 2;
3082 alu.dst.write = 1;
3083
3084 alu.src[0].sel = tmp0;
3085 alu.src[0].chan = 3;
3086
3087 if (signed_op) {
3088 alu.src[1].sel = tmp2;
3089 alu.src[1].chan = 1;
3090 } else {
3091 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3092 }
3093
3094 alu.last = 1;
3095 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3096 return r;
3097
3098 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
3099 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3100 alu.op = ALU_OP2_ADD_INT;
3101
3102 alu.dst.sel = tmp1;
3103 alu.dst.chan = 3;
3104 alu.dst.write = 1;
3105
3106 alu.src[0].sel = tmp0;
3107 alu.src[0].chan = 3;
3108 if (signed_op) {
3109 alu.src[1].sel = tmp2;
3110 alu.src[1].chan = 1;
3111 } else {
3112 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3113 }
3114
3115 alu.last = 1;
3116 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3117 return r;
3118
3119 } else { /* UDIV */
3120
3121 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
3122 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3123 alu.op = ALU_OP2_ADD_INT;
3124
3125 alu.dst.sel = tmp1;
3126 alu.dst.chan = 2;
3127 alu.dst.write = 1;
3128
3129 alu.src[0].sel = tmp0;
3130 alu.src[0].chan = 2;
3131 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3132
3133 alu.last = 1;
3134 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3135 return r;
3136
3137 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
3138 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3139 alu.op = ALU_OP2_ADD_INT;
3140
3141 alu.dst.sel = tmp1;
3142 alu.dst.chan = 3;
3143 alu.dst.write = 1;
3144
3145 alu.src[0].sel = tmp0;
3146 alu.src[0].chan = 2;
3147 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
3148
3149 alu.last = 1;
3150 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3151 return r;
3152
3153 }
3154
3155 /* 17. tmp1.x = tmp1.x & tmp1.y */
3156 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3157 alu.op = ALU_OP2_AND_INT;
3158
3159 alu.dst.sel = tmp1;
3160 alu.dst.chan = 0;
3161 alu.dst.write = 1;
3162
3163 alu.src[0].sel = tmp1;
3164 alu.src[0].chan = 0;
3165 alu.src[1].sel = tmp1;
3166 alu.src[1].chan = 1;
3167
3168 alu.last = 1;
3169 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3170 return r;
3171
3172 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
3173 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
3174 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3175 alu.op = ALU_OP3_CNDE_INT;
3176 alu.is_op3 = 1;
3177
3178 alu.dst.sel = tmp0;
3179 alu.dst.chan = 2;
3180 alu.dst.write = 1;
3181
3182 alu.src[0].sel = tmp1;
3183 alu.src[0].chan = 0;
3184 alu.src[1].sel = tmp0;
3185 alu.src[1].chan = mod ? 3 : 2;
3186 alu.src[2].sel = tmp1;
3187 alu.src[2].chan = 2;
3188
3189 alu.last = 1;
3190 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3191 return r;
3192
3193 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
3194 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3195 alu.op = ALU_OP3_CNDE_INT;
3196 alu.is_op3 = 1;
3197
3198 if (signed_op) {
3199 alu.dst.sel = tmp0;
3200 alu.dst.chan = 2;
3201 alu.dst.write = 1;
3202 } else {
3203 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3204 }
3205
3206 alu.src[0].sel = tmp1;
3207 alu.src[0].chan = 1;
3208 alu.src[1].sel = tmp1;
3209 alu.src[1].chan = 3;
3210 alu.src[2].sel = tmp0;
3211 alu.src[2].chan = 2;
3212
3213 alu.last = 1;
3214 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3215 return r;
3216
3217 if (signed_op) {
3218
3219 /* fix the sign of the result */
3220
3221 if (mod) {
3222
3223 /* tmp0.x = -tmp0.z */
3224 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3225 alu.op = ALU_OP2_SUB_INT;
3226
3227 alu.dst.sel = tmp0;
3228 alu.dst.chan = 0;
3229 alu.dst.write = 1;
3230
3231 alu.src[0].sel = V_SQ_ALU_SRC_0;
3232 alu.src[1].sel = tmp0;
3233 alu.src[1].chan = 2;
3234
3235 alu.last = 1;
3236 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3237 return r;
3238
3239 /* sign of the remainder is the same as the sign of src0 */
3240 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
3241 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3242 alu.op = ALU_OP3_CNDGE_INT;
3243 alu.is_op3 = 1;
3244
3245 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3246
3247 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3248 alu.src[1].sel = tmp0;
3249 alu.src[1].chan = 2;
3250 alu.src[2].sel = tmp0;
3251 alu.src[2].chan = 0;
3252
3253 alu.last = 1;
3254 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3255 return r;
3256
3257 } else {
3258
3259 /* tmp0.x = -tmp0.z */
3260 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3261 alu.op = ALU_OP2_SUB_INT;
3262
3263 alu.dst.sel = tmp0;
3264 alu.dst.chan = 0;
3265 alu.dst.write = 1;
3266
3267 alu.src[0].sel = V_SQ_ALU_SRC_0;
3268 alu.src[1].sel = tmp0;
3269 alu.src[1].chan = 2;
3270
3271 alu.last = 1;
3272 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3273 return r;
3274
3275 /* fix the quotient sign (same as the sign of src0*src1) */
3276 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
3277 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3278 alu.op = ALU_OP3_CNDGE_INT;
3279 alu.is_op3 = 1;
3280
3281 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3282
3283 alu.src[0].sel = tmp2;
3284 alu.src[0].chan = 2;
3285 alu.src[1].sel = tmp0;
3286 alu.src[1].chan = 2;
3287 alu.src[2].sel = tmp0;
3288 alu.src[2].chan = 0;
3289
3290 alu.last = 1;
3291 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3292 return r;
3293 }
3294 }
3295 }
3296 return 0;
3297 }
3298
3299 static int tgsi_udiv(struct r600_shader_ctx *ctx)
3300 {
3301 return tgsi_divmod(ctx, 0, 0);
3302 }
3303
3304 static int tgsi_umod(struct r600_shader_ctx *ctx)
3305 {
3306 return tgsi_divmod(ctx, 1, 0);
3307 }
3308
3309 static int tgsi_idiv(struct r600_shader_ctx *ctx)
3310 {
3311 return tgsi_divmod(ctx, 0, 1);
3312 }
3313
3314 static int tgsi_imod(struct r600_shader_ctx *ctx)
3315 {
3316 return tgsi_divmod(ctx, 1, 1);
3317 }
3318
3319
3320 static int tgsi_f2i(struct r600_shader_ctx *ctx)
3321 {
3322 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3323 struct r600_bytecode_alu alu;
3324 int i, r;
3325 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3326 int last_inst = tgsi_last_instruction(write_mask);
3327
3328 for (i = 0; i < 4; i++) {
3329 if (!(write_mask & (1<<i)))
3330 continue;
3331
3332 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3333 alu.op = ALU_OP1_TRUNC;
3334
3335 alu.dst.sel = ctx->temp_reg;
3336 alu.dst.chan = i;
3337 alu.dst.write = 1;
3338
3339 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3340 if (i == last_inst)
3341 alu.last = 1;
3342 r = r600_bytecode_add_alu(ctx->bc, &alu);
3343 if (r)
3344 return r;
3345 }
3346
3347 for (i = 0; i < 4; i++) {
3348 if (!(write_mask & (1<<i)))
3349 continue;
3350
3351 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3352 alu.op = ctx->inst_info->op;
3353
3354 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3355
3356 alu.src[0].sel = ctx->temp_reg;
3357 alu.src[0].chan = i;
3358
3359 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
3360 alu.last = 1;
3361 r = r600_bytecode_add_alu(ctx->bc, &alu);
3362 if (r)
3363 return r;
3364 }
3365
3366 return 0;
3367 }
3368
3369 static int tgsi_iabs(struct r600_shader_ctx *ctx)
3370 {
3371 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3372 struct r600_bytecode_alu alu;
3373 int i, r;
3374 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3375 int last_inst = tgsi_last_instruction(write_mask);
3376
3377 /* tmp = -src */
3378 for (i = 0; i < 4; i++) {
3379 if (!(write_mask & (1<<i)))
3380 continue;
3381
3382 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3383 alu.op = ALU_OP2_SUB_INT;
3384
3385 alu.dst.sel = ctx->temp_reg;
3386 alu.dst.chan = i;
3387 alu.dst.write = 1;
3388
3389 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3390 alu.src[0].sel = V_SQ_ALU_SRC_0;
3391
3392 if (i == last_inst)
3393 alu.last = 1;
3394 r = r600_bytecode_add_alu(ctx->bc, &alu);
3395 if (r)
3396 return r;
3397 }
3398
3399 /* dst = (src >= 0 ? src : tmp) */
3400 for (i = 0; i < 4; i++) {
3401 if (!(write_mask & (1<<i)))
3402 continue;
3403
3404 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3405 alu.op = ALU_OP3_CNDGE_INT;
3406 alu.is_op3 = 1;
3407 alu.dst.write = 1;
3408
3409 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3410
3411 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3412 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3413 alu.src[2].sel = ctx->temp_reg;
3414 alu.src[2].chan = i;
3415
3416 if (i == last_inst)
3417 alu.last = 1;
3418 r = r600_bytecode_add_alu(ctx->bc, &alu);
3419 if (r)
3420 return r;
3421 }
3422 return 0;
3423 }
3424
3425 static int tgsi_issg(struct r600_shader_ctx *ctx)
3426 {
3427 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3428 struct r600_bytecode_alu alu;
3429 int i, r;
3430 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3431 int last_inst = tgsi_last_instruction(write_mask);
3432
3433 /* tmp = (src >= 0 ? src : -1) */
3434 for (i = 0; i < 4; i++) {
3435 if (!(write_mask & (1<<i)))
3436 continue;
3437
3438 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3439 alu.op = ALU_OP3_CNDGE_INT;
3440 alu.is_op3 = 1;
3441
3442 alu.dst.sel = ctx->temp_reg;
3443 alu.dst.chan = i;
3444 alu.dst.write = 1;
3445
3446 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3447 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3448 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
3449
3450 if (i == last_inst)
3451 alu.last = 1;
3452 r = r600_bytecode_add_alu(ctx->bc, &alu);
3453 if (r)
3454 return r;
3455 }
3456
3457 /* dst = (tmp > 0 ? 1 : tmp) */
3458 for (i = 0; i < 4; i++) {
3459 if (!(write_mask & (1<<i)))
3460 continue;
3461
3462 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3463 alu.op = ALU_OP3_CNDGT_INT;
3464 alu.is_op3 = 1;
3465 alu.dst.write = 1;
3466
3467 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3468
3469 alu.src[0].sel = ctx->temp_reg;
3470 alu.src[0].chan = i;
3471
3472 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3473
3474 alu.src[2].sel = ctx->temp_reg;
3475 alu.src[2].chan = i;
3476
3477 if (i == last_inst)
3478 alu.last = 1;
3479 r = r600_bytecode_add_alu(ctx->bc, &alu);
3480 if (r)
3481 return r;
3482 }
3483 return 0;
3484 }
3485
3486
3487
3488 static int tgsi_ssg(struct r600_shader_ctx *ctx)
3489 {
3490 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3491 struct r600_bytecode_alu alu;
3492 int i, r;
3493
3494 /* tmp = (src > 0 ? 1 : src) */
3495 for (i = 0; i < 4; i++) {
3496 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3497 alu.op = ALU_OP3_CNDGT;
3498 alu.is_op3 = 1;
3499
3500 alu.dst.sel = ctx->temp_reg;
3501 alu.dst.chan = i;
3502
3503 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3504 alu.src[1].sel = V_SQ_ALU_SRC_1;
3505 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
3506
3507 if (i == 3)
3508 alu.last = 1;
3509 r = r600_bytecode_add_alu(ctx->bc, &alu);
3510 if (r)
3511 return r;
3512 }
3513
3514 /* dst = (-tmp > 0 ? -1 : tmp) */
3515 for (i = 0; i < 4; i++) {
3516 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3517 alu.op = ALU_OP3_CNDGT;
3518 alu.is_op3 = 1;
3519 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3520
3521 alu.src[0].sel = ctx->temp_reg;
3522 alu.src[0].chan = i;
3523 alu.src[0].neg = 1;
3524
3525 alu.src[1].sel = V_SQ_ALU_SRC_1;
3526 alu.src[1].neg = 1;
3527
3528 alu.src[2].sel = ctx->temp_reg;
3529 alu.src[2].chan = i;
3530
3531 if (i == 3)
3532 alu.last = 1;
3533 r = r600_bytecode_add_alu(ctx->bc, &alu);
3534 if (r)
3535 return r;
3536 }
3537 return 0;
3538 }
3539
3540 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
3541 {
3542 struct r600_bytecode_alu alu;
3543 int i, r;
3544
3545 for (i = 0; i < 4; i++) {
3546 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3547 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
3548 alu.op = ALU_OP0_NOP;
3549 alu.dst.chan = i;
3550 } else {
3551 alu.op = ALU_OP1_MOV;
3552 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3553 alu.src[0].sel = ctx->temp_reg;
3554 alu.src[0].chan = i;
3555 }
3556 if (i == 3) {
3557 alu.last = 1;
3558 }
3559 r = r600_bytecode_add_alu(ctx->bc, &alu);
3560 if (r)
3561 return r;
3562 }
3563 return 0;
3564 }
3565
3566 static int tgsi_op3(struct r600_shader_ctx *ctx)
3567 {
3568 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3569 struct r600_bytecode_alu alu;
3570 int i, j, r;
3571 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3572
3573 for (i = 0; i < lasti + 1; i++) {
3574 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3575 continue;
3576
3577 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3578 alu.op = ctx->inst_info->op;
3579 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3580 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3581 }
3582
3583 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3584 alu.dst.chan = i;
3585 alu.dst.write = 1;
3586 alu.is_op3 = 1;
3587 if (i == lasti) {
3588 alu.last = 1;
3589 }
3590 r = r600_bytecode_add_alu(ctx->bc, &alu);
3591 if (r)
3592 return r;
3593 }
3594 return 0;
3595 }
3596
3597 static int tgsi_dp(struct r600_shader_ctx *ctx)
3598 {
3599 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3600 struct r600_bytecode_alu alu;
3601 int i, j, r;
3602
3603 for (i = 0; i < 4; i++) {
3604 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3605 alu.op = ctx->inst_info->op;
3606 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3607 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3608 }
3609
3610 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3611 alu.dst.chan = i;
3612 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3613 /* handle some special cases */
3614 switch (ctx->inst_info->tgsi_opcode) {
3615 case TGSI_OPCODE_DP2:
3616 if (i > 1) {
3617 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3618 alu.src[0].chan = alu.src[1].chan = 0;
3619 }
3620 break;
3621 case TGSI_OPCODE_DP3:
3622 if (i > 2) {
3623 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3624 alu.src[0].chan = alu.src[1].chan = 0;
3625 }
3626 break;
3627 case TGSI_OPCODE_DPH:
3628 if (i == 3) {
3629 alu.src[0].sel = V_SQ_ALU_SRC_1;
3630 alu.src[0].chan = 0;
3631 alu.src[0].neg = 0;
3632 }
3633 break;
3634 default:
3635 break;
3636 }
3637 if (i == 3) {
3638 alu.last = 1;
3639 }
3640 r = r600_bytecode_add_alu(ctx->bc, &alu);
3641 if (r)
3642 return r;
3643 }
3644 return 0;
3645 }
3646
3647 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
3648 unsigned index)
3649 {
3650 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3651 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
3652 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
3653 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
3654 ctx->src[index].neg || ctx->src[index].abs;
3655 }
3656
3657 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
3658 unsigned index)
3659 {
3660 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3661 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
3662 }
3663
3664 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
3665 {
3666 struct r600_bytecode_vtx vtx;
3667 struct r600_bytecode_alu alu;
3668 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3669 int src_gpr, r, i;
3670 int id = tgsi_tex_get_src_gpr(ctx, 1);
3671
3672 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
3673 if (src_requires_loading) {
3674 for (i = 0; i < 4; i++) {
3675 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3676 alu.op = ALU_OP1_MOV;
3677 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3678 alu.dst.sel = ctx->temp_reg;
3679 alu.dst.chan = i;
3680 if (i == 3)
3681 alu.last = 1;
3682 alu.dst.write = 1;
3683 r = r600_bytecode_add_alu(ctx->bc, &alu);
3684 if (r)
3685 return r;
3686 }
3687 src_gpr = ctx->temp_reg;
3688 }
3689
3690 memset(&vtx, 0, sizeof(vtx));
3691 vtx.op = FETCH_OP_VFETCH;
3692 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
3693 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
3694 vtx.src_gpr = src_gpr;
3695 vtx.mega_fetch_count = 16;
3696 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
3697 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
3698 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
3699 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
3700 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
3701 vtx.use_const_fields = 1;
3702 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
3703
3704 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
3705 return r;
3706
3707 if (ctx->bc->chip_class >= EVERGREEN)
3708 return 0;
3709
3710 for (i = 0; i < 4; i++) {
3711 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3712 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3713 continue;
3714
3715 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3716 alu.op = ALU_OP2_AND_INT;
3717
3718 alu.dst.chan = i;
3719 alu.dst.sel = vtx.dst_gpr;
3720 alu.dst.write = 1;
3721
3722 alu.src[0].sel = vtx.dst_gpr;
3723 alu.src[0].chan = i;
3724
3725 alu.src[1].sel = 512 + (id * 2);
3726 alu.src[1].chan = i % 4;
3727 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3728
3729 if (i == lasti)
3730 alu.last = 1;
3731 r = r600_bytecode_add_alu(ctx->bc, &alu);
3732 if (r)
3733 return r;
3734 }
3735
3736 if (inst->Dst[0].Register.WriteMask & 3) {
3737 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3738 alu.op = ALU_OP2_OR_INT;
3739
3740 alu.dst.chan = 3;
3741 alu.dst.sel = vtx.dst_gpr;
3742 alu.dst.write = 1;
3743
3744 alu.src[0].sel = vtx.dst_gpr;
3745 alu.src[0].chan = 3;
3746
3747 alu.src[1].sel = 512 + (id * 2) + 1;
3748 alu.src[1].chan = 0;
3749 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3750
3751 alu.last = 1;
3752 r = r600_bytecode_add_alu(ctx->bc, &alu);
3753 if (r)
3754 return r;
3755 }
3756 return 0;
3757 }
3758
3759 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
3760 {
3761 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3762 struct r600_bytecode_alu alu;
3763 int r;
3764 int id = tgsi_tex_get_src_gpr(ctx, 1);
3765
3766 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3767 alu.op = ALU_OP1_MOV;
3768
3769 if (ctx->bc->chip_class >= EVERGREEN) {
3770 alu.src[0].sel = 512 + (id / 4);
3771 alu.src[0].chan = id % 4;
3772 } else {
3773 /* r600 we have them at channel 2 of the second dword */
3774 alu.src[0].sel = 512 + (id * 2) + 1;
3775 alu.src[0].chan = 1;
3776 }
3777 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3778 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3779 alu.last = 1;
3780 r = r600_bytecode_add_alu(ctx->bc, &alu);
3781 if (r)
3782 return r;
3783 return 0;
3784 }
3785
3786 static int tgsi_tex(struct r600_shader_ctx *ctx)
3787 {
3788 static float one_point_five = 1.5f;
3789 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3790 struct r600_bytecode_tex tex;
3791 struct r600_bytecode_alu alu;
3792 unsigned src_gpr;
3793 int r, i, j;
3794 int opcode;
3795 bool read_compressed_msaa = ctx->bc->msaa_texture_mode == MSAA_TEXTURE_COMPRESSED &&
3796 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
3797 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
3798 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
3799 /* Texture fetch instructions can only use gprs as source.
3800 * Also they cannot negate the source or take the absolute value */
3801 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
3802 tgsi_tex_src_requires_loading(ctx, 0)) ||
3803 read_compressed_msaa;
3804 boolean src_loaded = FALSE;
3805 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
3806 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
3807 boolean has_txq_cube_array_z = false;
3808
3809 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
3810 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
3811 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
3812 if (inst->Dst[0].Register.WriteMask & 4) {
3813 ctx->shader->has_txq_cube_array_z_comp = true;
3814 has_txq_cube_array_z = true;
3815 }
3816
3817 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
3818 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
3819 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
3820 sampler_src_reg = 2;
3821
3822 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
3823
3824 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
3825 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
3826 ctx->shader->uses_tex_buffers = true;
3827 return r600_do_buffer_txq(ctx);
3828 }
3829 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
3830 if (ctx->bc->chip_class < EVERGREEN)
3831 ctx->shader->uses_tex_buffers = true;
3832 return do_vtx_fetch_inst(ctx, src_requires_loading);
3833 }
3834 }
3835
3836 if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
3837 /* get offset values */
3838 if (inst->Texture.NumOffsets) {
3839 assert(inst->Texture.NumOffsets == 1);
3840
3841 offset_x = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
3842 offset_y = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
3843 offset_z = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
3844 }
3845 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
3846 /* TGSI moves the sampler to src reg 3 for TXD */
3847 sampler_src_reg = 3;
3848
3849 for (i = 1; i < 3; i++) {
3850 /* set gradients h/v */
3851 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
3852 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
3853 FETCH_OP_SET_GRADIENTS_V;
3854 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
3855 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
3856
3857 if (tgsi_tex_src_requires_loading(ctx, i)) {
3858 tex.src_gpr = r600_get_temp(ctx);
3859 tex.src_sel_x = 0;
3860 tex.src_sel_y = 1;
3861 tex.src_sel_z = 2;
3862 tex.src_sel_w = 3;
3863
3864 for (j = 0; j < 4; j++) {
3865 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3866 alu.op = ALU_OP1_MOV;
3867 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
3868 alu.dst.sel = tex.src_gpr;
3869 alu.dst.chan = j;
3870 if (j == 3)
3871 alu.last = 1;
3872 alu.dst.write = 1;
3873 r = r600_bytecode_add_alu(ctx->bc, &alu);
3874 if (r)
3875 return r;
3876 }
3877
3878 } else {
3879 tex.src_gpr = tgsi_tex_get_src_gpr(ctx, i);
3880 tex.src_sel_x = ctx->src[i].swizzle[0];
3881 tex.src_sel_y = ctx->src[i].swizzle[1];
3882 tex.src_sel_z = ctx->src[i].swizzle[2];
3883 tex.src_sel_w = ctx->src[i].swizzle[3];
3884 tex.src_rel = ctx->src[i].rel;
3885 }
3886 tex.dst_gpr = ctx->temp_reg; /* just to avoid confusing the asm scheduler */
3887 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
3888 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
3889 tex.coord_type_x = 1;
3890 tex.coord_type_y = 1;
3891 tex.coord_type_z = 1;
3892 tex.coord_type_w = 1;
3893 }
3894 r = r600_bytecode_add_tex(ctx->bc, &tex);
3895 if (r)
3896 return r;
3897 }
3898 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
3899 int out_chan;
3900 /* Add perspective divide */
3901 if (ctx->bc->chip_class == CAYMAN) {
3902 out_chan = 2;
3903 for (i = 0; i < 3; i++) {
3904 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3905 alu.op = ALU_OP1_RECIP_IEEE;
3906 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3907
3908 alu.dst.sel = ctx->temp_reg;
3909 alu.dst.chan = i;
3910 if (i == 2)
3911 alu.last = 1;
3912 if (out_chan == i)
3913 alu.dst.write = 1;
3914 r = r600_bytecode_add_alu(ctx->bc, &alu);
3915 if (r)
3916 return r;
3917 }
3918
3919 } else {
3920 out_chan = 3;
3921 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3922 alu.op = ALU_OP1_RECIP_IEEE;
3923 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3924
3925 alu.dst.sel = ctx->temp_reg;
3926 alu.dst.chan = out_chan;
3927 alu.last = 1;
3928 alu.dst.write = 1;
3929 r = r600_bytecode_add_alu(ctx->bc, &alu);
3930 if (r)
3931 return r;
3932 }
3933
3934 for (i = 0; i < 3; i++) {
3935 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3936 alu.op = ALU_OP2_MUL;
3937 alu.src[0].sel = ctx->temp_reg;
3938 alu.src[0].chan = out_chan;
3939 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3940 alu.dst.sel = ctx->temp_reg;
3941 alu.dst.chan = i;
3942 alu.dst.write = 1;
3943 r = r600_bytecode_add_alu(ctx->bc, &alu);
3944 if (r)
3945 return r;
3946 }
3947 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3948 alu.op = ALU_OP1_MOV;
3949 alu.src[0].sel = V_SQ_ALU_SRC_1;
3950 alu.src[0].chan = 0;
3951 alu.dst.sel = ctx->temp_reg;
3952 alu.dst.chan = 3;
3953 alu.last = 1;
3954 alu.dst.write = 1;
3955 r = r600_bytecode_add_alu(ctx->bc, &alu);
3956 if (r)
3957 return r;
3958 src_loaded = TRUE;
3959 src_gpr = ctx->temp_reg;
3960 }
3961
3962 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
3963 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
3964 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
3965 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
3966 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
3967 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
3968
3969 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
3970 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
3971
3972 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
3973 for (i = 0; i < 4; i++) {
3974 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3975 alu.op = ALU_OP2_CUBE;
3976 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
3977 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
3978 alu.dst.sel = ctx->temp_reg;
3979 alu.dst.chan = i;
3980 if (i == 3)
3981 alu.last = 1;
3982 alu.dst.write = 1;
3983 r = r600_bytecode_add_alu(ctx->bc, &alu);
3984 if (r)
3985 return r;
3986 }
3987
3988 /* tmp1.z = RCP_e(|tmp1.z|) */
3989 if (ctx->bc->chip_class == CAYMAN) {
3990 for (i = 0; i < 3; i++) {
3991 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3992 alu.op = ALU_OP1_RECIP_IEEE;
3993 alu.src[0].sel = ctx->temp_reg;
3994 alu.src[0].chan = 2;
3995 alu.src[0].abs = 1;
3996 alu.dst.sel = ctx->temp_reg;
3997 alu.dst.chan = i;
3998 if (i == 2)
3999 alu.dst.write = 1;
4000 if (i == 2)
4001 alu.last = 1;
4002 r = r600_bytecode_add_alu(ctx->bc, &alu);
4003 if (r)
4004 return r;
4005 }
4006 } else {
4007 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4008 alu.op = ALU_OP1_RECIP_IEEE;
4009 alu.src[0].sel = ctx->temp_reg;
4010 alu.src[0].chan = 2;
4011 alu.src[0].abs = 1;
4012 alu.dst.sel = ctx->temp_reg;
4013 alu.dst.chan = 2;
4014 alu.dst.write = 1;
4015 alu.last = 1;
4016 r = r600_bytecode_add_alu(ctx->bc, &alu);
4017 if (r)
4018 return r;
4019 }
4020
4021 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
4022 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
4023 * muladd has no writemask, have to use another temp
4024 */
4025 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4026 alu.op = ALU_OP3_MULADD;
4027 alu.is_op3 = 1;
4028
4029 alu.src[0].sel = ctx->temp_reg;
4030 alu.src[0].chan = 0;
4031 alu.src[1].sel = ctx->temp_reg;
4032 alu.src[1].chan = 2;
4033
4034 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4035 alu.src[2].chan = 0;
4036 alu.src[2].value = *(uint32_t *)&one_point_five;
4037
4038 alu.dst.sel = ctx->temp_reg;
4039 alu.dst.chan = 0;
4040 alu.dst.write = 1;
4041
4042 r = r600_bytecode_add_alu(ctx->bc, &alu);
4043 if (r)
4044 return r;
4045
4046 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4047 alu.op = ALU_OP3_MULADD;
4048 alu.is_op3 = 1;
4049
4050 alu.src[0].sel = ctx->temp_reg;
4051 alu.src[0].chan = 1;
4052 alu.src[1].sel = ctx->temp_reg;
4053 alu.src[1].chan = 2;
4054
4055 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4056 alu.src[2].chan = 0;
4057 alu.src[2].value = *(uint32_t *)&one_point_five;
4058
4059 alu.dst.sel = ctx->temp_reg;
4060 alu.dst.chan = 1;
4061 alu.dst.write = 1;
4062
4063 alu.last = 1;
4064 r = r600_bytecode_add_alu(ctx->bc, &alu);
4065 if (r)
4066 return r;
4067 /* write initial compare value into Z component
4068 - W src 0 for shadow cube
4069 - X src 1 for shadow cube array */
4070 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4071 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4072 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4073 alu.op = ALU_OP1_MOV;
4074 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4075 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4076 else
4077 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4078 alu.dst.sel = ctx->temp_reg;
4079 alu.dst.chan = 2;
4080 alu.dst.write = 1;
4081 alu.last = 1;
4082 r = r600_bytecode_add_alu(ctx->bc, &alu);
4083 if (r)
4084 return r;
4085 }
4086
4087 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4088 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4089 if (ctx->bc->chip_class >= EVERGREEN) {
4090 int mytmp = r600_get_temp(ctx);
4091 static const float eight = 8.0f;
4092 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4093 alu.op = ALU_OP1_MOV;
4094 alu.src[0].sel = ctx->temp_reg;
4095 alu.src[0].chan = 3;
4096 alu.dst.sel = mytmp;
4097 alu.dst.chan = 0;
4098 alu.dst.write = 1;
4099 alu.last = 1;
4100 r = r600_bytecode_add_alu(ctx->bc, &alu);
4101 if (r)
4102 return r;
4103
4104 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
4105 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4106 alu.op = ALU_OP3_MULADD;
4107 alu.is_op3 = 1;
4108 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4109 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4110 alu.src[1].chan = 0;
4111 alu.src[1].value = *(uint32_t *)&eight;
4112 alu.src[2].sel = mytmp;
4113 alu.src[2].chan = 0;
4114 alu.dst.sel = ctx->temp_reg;
4115 alu.dst.chan = 3;
4116 alu.dst.write = 1;
4117 alu.last = 1;
4118 r = r600_bytecode_add_alu(ctx->bc, &alu);
4119 if (r)
4120 return r;
4121 } else if (ctx->bc->chip_class < EVERGREEN) {
4122 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4123 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
4124 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4125 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4126 tex.src_gpr = r600_get_temp(ctx);
4127 tex.src_sel_x = 0;
4128 tex.src_sel_y = 0;
4129 tex.src_sel_z = 0;
4130 tex.src_sel_w = 0;
4131 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4132 tex.coord_type_x = 1;
4133 tex.coord_type_y = 1;
4134 tex.coord_type_z = 1;
4135 tex.coord_type_w = 1;
4136 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4137 alu.op = ALU_OP1_MOV;
4138 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4139 alu.dst.sel = tex.src_gpr;
4140 alu.dst.chan = 0;
4141 alu.last = 1;
4142 alu.dst.write = 1;
4143 r = r600_bytecode_add_alu(ctx->bc, &alu);
4144 if (r)
4145 return r;
4146
4147 r = r600_bytecode_add_tex(ctx->bc, &tex);
4148 if (r)
4149 return r;
4150 }
4151
4152 }
4153
4154 /* for cube forms of lod and bias we need to route things */
4155 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
4156 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
4157 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4158 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
4159 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4160 alu.op = ALU_OP1_MOV;
4161 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4162 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4163 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4164 else
4165 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4166 alu.dst.sel = ctx->temp_reg;
4167 alu.dst.chan = 2;
4168 alu.last = 1;
4169 alu.dst.write = 1;
4170 r = r600_bytecode_add_alu(ctx->bc, &alu);
4171 if (r)
4172 return r;
4173 }
4174
4175 src_loaded = TRUE;
4176 src_gpr = ctx->temp_reg;
4177 }
4178
4179 if (src_requires_loading && !src_loaded) {
4180 for (i = 0; i < 4; i++) {
4181 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4182 alu.op = ALU_OP1_MOV;
4183 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4184 alu.dst.sel = ctx->temp_reg;
4185 alu.dst.chan = i;
4186 if (i == 3)
4187 alu.last = 1;
4188 alu.dst.write = 1;
4189 r = r600_bytecode_add_alu(ctx->bc, &alu);
4190 if (r)
4191 return r;
4192 }
4193 src_loaded = TRUE;
4194 src_gpr = ctx->temp_reg;
4195 }
4196
4197 /* Obtain the sample index for reading a compressed MSAA color texture.
4198 * To read the FMASK, we use the ldfptr instruction, which tells us
4199 * where the samples are stored.
4200 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
4201 * which is the identity mapping. Each nibble says which physical sample
4202 * should be fetched to get that sample.
4203 *
4204 * Assume src.z contains the sample index. It should be modified like this:
4205 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
4206 * Then fetch the texel with src.
4207 */
4208 if (read_compressed_msaa) {
4209 unsigned sample_chan = 3;
4210 unsigned temp = r600_get_temp(ctx);
4211 assert(src_loaded);
4212
4213 /* temp.w = ldfptr() */
4214 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4215 tex.op = FETCH_OP_LD;
4216 tex.inst_mod = 1; /* to indicate this is ldfptr */
4217 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4218 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4219 tex.src_gpr = src_gpr;
4220 tex.dst_gpr = temp;
4221 tex.dst_sel_x = 7; /* mask out these components */
4222 tex.dst_sel_y = 7;
4223 tex.dst_sel_z = 7;
4224 tex.dst_sel_w = 0; /* store X */
4225 tex.src_sel_x = 0;
4226 tex.src_sel_y = 1;
4227 tex.src_sel_z = 2;
4228 tex.src_sel_w = 3;
4229 tex.offset_x = offset_x;
4230 tex.offset_y = offset_y;
4231 tex.offset_z = offset_z;
4232 r = r600_bytecode_add_tex(ctx->bc, &tex);
4233 if (r)
4234 return r;
4235
4236 /* temp.x = sample_index*4 */
4237 if (ctx->bc->chip_class == CAYMAN) {
4238 for (i = 0 ; i < 4; i++) {
4239 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4240 alu.op = ALU_OP2_MULLO_INT;
4241 alu.src[0].sel = src_gpr;
4242 alu.src[0].chan = sample_chan;
4243 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4244 alu.src[1].value = 4;
4245 alu.dst.sel = temp;
4246 alu.dst.chan = i;
4247 alu.dst.write = i == 0;
4248 if (i == 3)
4249 alu.last = 1;
4250 r = r600_bytecode_add_alu(ctx->bc, &alu);
4251 if (r)
4252 return r;
4253 }
4254 } else {
4255 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4256 alu.op = ALU_OP2_MULLO_INT;
4257 alu.src[0].sel = src_gpr;
4258 alu.src[0].chan = sample_chan;
4259 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4260 alu.src[1].value = 4;
4261 alu.dst.sel = temp;
4262 alu.dst.chan = 0;
4263 alu.dst.write = 1;
4264 alu.last = 1;
4265 r = r600_bytecode_add_alu(ctx->bc, &alu);
4266 if (r)
4267 return r;
4268 }
4269
4270 /* sample_index = temp.w >> temp.x */
4271 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4272 alu.op = ALU_OP2_LSHR_INT;
4273 alu.src[0].sel = temp;
4274 alu.src[0].chan = 3;
4275 alu.src[1].sel = temp;
4276 alu.src[1].chan = 0;
4277 alu.dst.sel = src_gpr;
4278 alu.dst.chan = sample_chan;
4279 alu.dst.write = 1;
4280 alu.last = 1;
4281 r = r600_bytecode_add_alu(ctx->bc, &alu);
4282 if (r)
4283 return r;
4284
4285 /* sample_index & 0xF */
4286 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4287 alu.op = ALU_OP2_AND_INT;
4288 alu.src[0].sel = src_gpr;
4289 alu.src[0].chan = sample_chan;
4290 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4291 alu.src[1].value = 0xF;
4292 alu.dst.sel = src_gpr;
4293 alu.dst.chan = sample_chan;
4294 alu.dst.write = 1;
4295 alu.last = 1;
4296 r = r600_bytecode_add_alu(ctx->bc, &alu);
4297 if (r)
4298 return r;
4299 #if 0
4300 /* visualize the FMASK */
4301 for (i = 0; i < 4; i++) {
4302 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4303 alu.op = ALU_OP1_INT_TO_FLT;
4304 alu.src[0].sel = src_gpr;
4305 alu.src[0].chan = sample_chan;
4306 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4307 alu.dst.chan = i;
4308 alu.dst.write = 1;
4309 alu.last = 1;
4310 r = r600_bytecode_add_alu(ctx->bc, &alu);
4311 if (r)
4312 return r;
4313 }
4314 return 0;
4315 #endif
4316 }
4317
4318 /* does this shader want a num layers from TXQ for a cube array? */
4319 if (has_txq_cube_array_z) {
4320 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4321
4322 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4323 alu.op = ALU_OP1_MOV;
4324
4325 alu.src[0].sel = 512 + (id / 4);
4326 alu.src[0].kc_bank = R600_TXQ_CONST_BUFFER;
4327 alu.src[0].chan = id % 4;
4328 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4329 alu.last = 1;
4330 r = r600_bytecode_add_alu(ctx->bc, &alu);
4331 if (r)
4332 return r;
4333 /* disable writemask from texture instruction */
4334 inst->Dst[0].Register.WriteMask &= ~4;
4335 }
4336
4337 opcode = ctx->inst_info->op;
4338 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4339 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4340 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4341 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4342 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
4343 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4344 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4345 switch (opcode) {
4346 case FETCH_OP_SAMPLE:
4347 opcode = FETCH_OP_SAMPLE_C;
4348 break;
4349 case FETCH_OP_SAMPLE_L:
4350 opcode = FETCH_OP_SAMPLE_C_L;
4351 break;
4352 case FETCH_OP_SAMPLE_LB:
4353 opcode = FETCH_OP_SAMPLE_C_LB;
4354 break;
4355 case FETCH_OP_SAMPLE_G:
4356 opcode = FETCH_OP_SAMPLE_C_G;
4357 break;
4358 }
4359 }
4360
4361 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4362 tex.op = opcode;
4363
4364 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4365 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4366 tex.src_gpr = src_gpr;
4367 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4368 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
4369 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
4370 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
4371 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
4372
4373 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
4374 tex.src_sel_x = 4;
4375 tex.src_sel_y = 4;
4376 tex.src_sel_z = 4;
4377 tex.src_sel_w = 4;
4378 } else if (src_loaded) {
4379 tex.src_sel_x = 0;
4380 tex.src_sel_y = 1;
4381 tex.src_sel_z = 2;
4382 tex.src_sel_w = 3;
4383 } else {
4384 tex.src_sel_x = ctx->src[0].swizzle[0];
4385 tex.src_sel_y = ctx->src[0].swizzle[1];
4386 tex.src_sel_z = ctx->src[0].swizzle[2];
4387 tex.src_sel_w = ctx->src[0].swizzle[3];
4388 tex.src_rel = ctx->src[0].rel;
4389 }
4390
4391 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4392 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4393 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4394 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4395 tex.src_sel_x = 1;
4396 tex.src_sel_y = 0;
4397 tex.src_sel_z = 3;
4398 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
4399 }
4400
4401 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
4402 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
4403 tex.coord_type_x = 1;
4404 tex.coord_type_y = 1;
4405 }
4406 tex.coord_type_z = 1;
4407 tex.coord_type_w = 1;
4408
4409 tex.offset_x = offset_x;
4410 tex.offset_y = offset_y;
4411 tex.offset_z = offset_z;
4412
4413 /* Put the depth for comparison in W.
4414 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
4415 * Some instructions expect the depth in Z. */
4416 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4417 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4418 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4419 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
4420 opcode != FETCH_OP_SAMPLE_C_L &&
4421 opcode != FETCH_OP_SAMPLE_C_LB) {
4422 tex.src_sel_w = tex.src_sel_z;
4423 }
4424
4425 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
4426 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
4427 if (opcode == FETCH_OP_SAMPLE_C_L ||
4428 opcode == FETCH_OP_SAMPLE_C_LB) {
4429 /* the array index is read from Y */
4430 tex.coord_type_y = 0;
4431 } else {
4432 /* the array index is read from Z */
4433 tex.coord_type_z = 0;
4434 tex.src_sel_z = tex.src_sel_y;
4435 }
4436 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
4437 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4438 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4439 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4440 (ctx->bc->chip_class >= EVERGREEN)))
4441 /* the array index is read from Z */
4442 tex.coord_type_z = 0;
4443
4444 /* mask unused source components */
4445 if (opcode == FETCH_OP_SAMPLE) {
4446 switch (inst->Texture.Texture) {
4447 case TGSI_TEXTURE_2D:
4448 case TGSI_TEXTURE_RECT:
4449 tex.src_sel_z = 7;
4450 tex.src_sel_w = 7;
4451 break;
4452 case TGSI_TEXTURE_1D_ARRAY:
4453 tex.src_sel_y = 7;
4454 tex.src_sel_w = 7;
4455 break;
4456 case TGSI_TEXTURE_1D:
4457 tex.src_sel_y = 7;
4458 tex.src_sel_z = 7;
4459 tex.src_sel_w = 7;
4460 break;
4461 }
4462 }
4463
4464 r = r600_bytecode_add_tex(ctx->bc, &tex);
4465 if (r)
4466 return r;
4467
4468 /* add shadow ambient support - gallium doesn't do it yet */
4469 return 0;
4470 }
4471
4472 static int tgsi_lrp(struct r600_shader_ctx *ctx)
4473 {
4474 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4475 struct r600_bytecode_alu alu;
4476 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4477 unsigned i;
4478 int r;
4479
4480 /* optimize if it's just an equal balance */
4481 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
4482 for (i = 0; i < lasti + 1; i++) {
4483 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4484 continue;
4485
4486 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4487 alu.op = ALU_OP2_ADD;
4488 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4489 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4490 alu.omod = 3;
4491 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4492 alu.dst.chan = i;
4493 if (i == lasti) {
4494 alu.last = 1;
4495 }
4496 r = r600_bytecode_add_alu(ctx->bc, &alu);
4497 if (r)
4498 return r;
4499 }
4500 return 0;
4501 }
4502
4503 /* 1 - src0 */
4504 for (i = 0; i < lasti + 1; i++) {
4505 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4506 continue;
4507
4508 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4509 alu.op = ALU_OP2_ADD;
4510 alu.src[0].sel = V_SQ_ALU_SRC_1;
4511 alu.src[0].chan = 0;
4512 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4513 r600_bytecode_src_toggle_neg(&alu.src[1]);
4514 alu.dst.sel = ctx->temp_reg;
4515 alu.dst.chan = i;
4516 if (i == lasti) {
4517 alu.last = 1;
4518 }
4519 alu.dst.write = 1;
4520 r = r600_bytecode_add_alu(ctx->bc, &alu);
4521 if (r)
4522 return r;
4523 }
4524
4525 /* (1 - src0) * src2 */
4526 for (i = 0; i < lasti + 1; i++) {
4527 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4528 continue;
4529
4530 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4531 alu.op = ALU_OP2_MUL;
4532 alu.src[0].sel = ctx->temp_reg;
4533 alu.src[0].chan = i;
4534 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4535 alu.dst.sel = ctx->temp_reg;
4536 alu.dst.chan = i;
4537 if (i == lasti) {
4538 alu.last = 1;
4539 }
4540 alu.dst.write = 1;
4541 r = r600_bytecode_add_alu(ctx->bc, &alu);
4542 if (r)
4543 return r;
4544 }
4545
4546 /* src0 * src1 + (1 - src0) * src2 */
4547 for (i = 0; i < lasti + 1; i++) {
4548 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4549 continue;
4550
4551 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4552 alu.op = ALU_OP3_MULADD;
4553 alu.is_op3 = 1;
4554 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4555 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4556 alu.src[2].sel = ctx->temp_reg;
4557 alu.src[2].chan = i;
4558
4559 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4560 alu.dst.chan = i;
4561 if (i == lasti) {
4562 alu.last = 1;
4563 }
4564 r = r600_bytecode_add_alu(ctx->bc, &alu);
4565 if (r)
4566 return r;
4567 }
4568 return 0;
4569 }
4570
4571 static int tgsi_cmp(struct r600_shader_ctx *ctx)
4572 {
4573 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4574 struct r600_bytecode_alu alu;
4575 int i, r;
4576 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4577
4578 for (i = 0; i < lasti + 1; i++) {
4579 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4580 continue;
4581
4582 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4583 alu.op = ALU_OP3_CNDGE;
4584 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4585 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4586 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4587 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4588 alu.dst.chan = i;
4589 alu.dst.write = 1;
4590 alu.is_op3 = 1;
4591 if (i == lasti)
4592 alu.last = 1;
4593 r = r600_bytecode_add_alu(ctx->bc, &alu);
4594 if (r)
4595 return r;
4596 }
4597 return 0;
4598 }
4599
4600 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
4601 {
4602 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4603 struct r600_bytecode_alu alu;
4604 int i, r;
4605 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4606
4607 for (i = 0; i < lasti + 1; i++) {
4608 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4609 continue;
4610
4611 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4612 alu.op = ALU_OP3_CNDGE_INT;
4613 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4614 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4615 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4616 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4617 alu.dst.chan = i;
4618 alu.dst.write = 1;
4619 alu.is_op3 = 1;
4620 if (i == lasti)
4621 alu.last = 1;
4622 r = r600_bytecode_add_alu(ctx->bc, &alu);
4623 if (r)
4624 return r;
4625 }
4626 return 0;
4627 }
4628
4629 static int tgsi_xpd(struct r600_shader_ctx *ctx)
4630 {
4631 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4632 static const unsigned int src0_swizzle[] = {2, 0, 1};
4633 static const unsigned int src1_swizzle[] = {1, 2, 0};
4634 struct r600_bytecode_alu alu;
4635 uint32_t use_temp = 0;
4636 int i, r;
4637
4638 if (inst->Dst[0].Register.WriteMask != 0xf)
4639 use_temp = 1;
4640
4641 for (i = 0; i < 4; i++) {
4642 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4643 alu.op = ALU_OP2_MUL;
4644 if (i < 3) {
4645 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4646 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
4647 } else {
4648 alu.src[0].sel = V_SQ_ALU_SRC_0;
4649 alu.src[0].chan = i;
4650 alu.src[1].sel = V_SQ_ALU_SRC_0;
4651 alu.src[1].chan = i;
4652 }
4653
4654 alu.dst.sel = ctx->temp_reg;
4655 alu.dst.chan = i;
4656 alu.dst.write = 1;
4657
4658 if (i == 3)
4659 alu.last = 1;
4660 r = r600_bytecode_add_alu(ctx->bc, &alu);
4661 if (r)
4662 return r;
4663 }
4664
4665 for (i = 0; i < 4; i++) {
4666 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4667 alu.op = ALU_OP3_MULADD;
4668
4669 if (i < 3) {
4670 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
4671 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
4672 } else {
4673 alu.src[0].sel = V_SQ_ALU_SRC_0;
4674 alu.src[0].chan = i;
4675 alu.src[1].sel = V_SQ_ALU_SRC_0;
4676 alu.src[1].chan = i;
4677 }
4678
4679 alu.src[2].sel = ctx->temp_reg;
4680 alu.src[2].neg = 1;
4681 alu.src[2].chan = i;
4682
4683 if (use_temp)
4684 alu.dst.sel = ctx->temp_reg;
4685 else
4686 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4687 alu.dst.chan = i;
4688 alu.dst.write = 1;
4689 alu.is_op3 = 1;
4690 if (i == 3)
4691 alu.last = 1;
4692 r = r600_bytecode_add_alu(ctx->bc, &alu);
4693 if (r)
4694 return r;
4695 }
4696 if (use_temp)
4697 return tgsi_helper_copy(ctx, inst);
4698 return 0;
4699 }
4700
4701 static int tgsi_exp(struct r600_shader_ctx *ctx)
4702 {
4703 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4704 struct r600_bytecode_alu alu;
4705 int r;
4706 int i;
4707
4708 /* result.x = 2^floor(src); */
4709 if (inst->Dst[0].Register.WriteMask & 1) {
4710 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4711
4712 alu.op = ALU_OP1_FLOOR;
4713 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4714
4715 alu.dst.sel = ctx->temp_reg;
4716 alu.dst.chan = 0;
4717 alu.dst.write = 1;
4718 alu.last = 1;
4719 r = r600_bytecode_add_alu(ctx->bc, &alu);
4720 if (r)
4721 return r;
4722
4723 if (ctx->bc->chip_class == CAYMAN) {
4724 for (i = 0; i < 3; i++) {
4725 alu.op = ALU_OP1_EXP_IEEE;
4726 alu.src[0].sel = ctx->temp_reg;
4727 alu.src[0].chan = 0;
4728
4729 alu.dst.sel = ctx->temp_reg;
4730 alu.dst.chan = i;
4731 alu.dst.write = i == 0;
4732 alu.last = i == 2;
4733 r = r600_bytecode_add_alu(ctx->bc, &alu);
4734 if (r)
4735 return r;
4736 }
4737 } else {
4738 alu.op = ALU_OP1_EXP_IEEE;
4739 alu.src[0].sel = ctx->temp_reg;
4740 alu.src[0].chan = 0;
4741
4742 alu.dst.sel = ctx->temp_reg;
4743 alu.dst.chan = 0;
4744 alu.dst.write = 1;
4745 alu.last = 1;
4746 r = r600_bytecode_add_alu(ctx->bc, &alu);
4747 if (r)
4748 return r;
4749 }
4750 }
4751
4752 /* result.y = tmp - floor(tmp); */
4753 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
4754 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4755
4756 alu.op = ALU_OP1_FRACT;
4757 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4758
4759 alu.dst.sel = ctx->temp_reg;
4760 #if 0
4761 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4762 if (r)
4763 return r;
4764 #endif
4765 alu.dst.write = 1;
4766 alu.dst.chan = 1;
4767
4768 alu.last = 1;
4769
4770 r = r600_bytecode_add_alu(ctx->bc, &alu);
4771 if (r)
4772 return r;
4773 }
4774
4775 /* result.z = RoughApprox2ToX(tmp);*/
4776 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
4777 if (ctx->bc->chip_class == CAYMAN) {
4778 for (i = 0; i < 3; i++) {
4779 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4780 alu.op = ALU_OP1_EXP_IEEE;
4781 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4782
4783 alu.dst.sel = ctx->temp_reg;
4784 alu.dst.chan = i;
4785 if (i == 2) {
4786 alu.dst.write = 1;
4787 alu.last = 1;
4788 }
4789
4790 r = r600_bytecode_add_alu(ctx->bc, &alu);
4791 if (r)
4792 return r;
4793 }
4794 } else {
4795 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4796 alu.op = ALU_OP1_EXP_IEEE;
4797 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4798
4799 alu.dst.sel = ctx->temp_reg;
4800 alu.dst.write = 1;
4801 alu.dst.chan = 2;
4802
4803 alu.last = 1;
4804
4805 r = r600_bytecode_add_alu(ctx->bc, &alu);
4806 if (r)
4807 return r;
4808 }
4809 }
4810
4811 /* result.w = 1.0;*/
4812 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
4813 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4814
4815 alu.op = ALU_OP1_MOV;
4816 alu.src[0].sel = V_SQ_ALU_SRC_1;
4817 alu.src[0].chan = 0;
4818
4819 alu.dst.sel = ctx->temp_reg;
4820 alu.dst.chan = 3;
4821 alu.dst.write = 1;
4822 alu.last = 1;
4823 r = r600_bytecode_add_alu(ctx->bc, &alu);
4824 if (r)
4825 return r;
4826 }
4827 return tgsi_helper_copy(ctx, inst);
4828 }
4829
4830 static int tgsi_log(struct r600_shader_ctx *ctx)
4831 {
4832 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4833 struct r600_bytecode_alu alu;
4834 int r;
4835 int i;
4836
4837 /* result.x = floor(log2(|src|)); */
4838 if (inst->Dst[0].Register.WriteMask & 1) {
4839 if (ctx->bc->chip_class == CAYMAN) {
4840 for (i = 0; i < 3; i++) {
4841 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4842
4843 alu.op = ALU_OP1_LOG_IEEE;
4844 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4845 r600_bytecode_src_set_abs(&alu.src[0]);
4846
4847 alu.dst.sel = ctx->temp_reg;
4848 alu.dst.chan = i;
4849 if (i == 0)
4850 alu.dst.write = 1;
4851 if (i == 2)
4852 alu.last = 1;
4853 r = r600_bytecode_add_alu(ctx->bc, &alu);
4854 if (r)
4855 return r;
4856 }
4857
4858 } else {
4859 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4860
4861 alu.op = ALU_OP1_LOG_IEEE;
4862 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4863 r600_bytecode_src_set_abs(&alu.src[0]);
4864
4865 alu.dst.sel = ctx->temp_reg;
4866 alu.dst.chan = 0;
4867 alu.dst.write = 1;
4868 alu.last = 1;
4869 r = r600_bytecode_add_alu(ctx->bc, &alu);
4870 if (r)
4871 return r;
4872 }
4873
4874 alu.op = ALU_OP1_FLOOR;
4875 alu.src[0].sel = ctx->temp_reg;
4876 alu.src[0].chan = 0;
4877
4878 alu.dst.sel = ctx->temp_reg;
4879 alu.dst.chan = 0;
4880 alu.dst.write = 1;
4881 alu.last = 1;
4882
4883 r = r600_bytecode_add_alu(ctx->bc, &alu);
4884 if (r)
4885 return r;
4886 }
4887
4888 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
4889 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
4890
4891 if (ctx->bc->chip_class == CAYMAN) {
4892 for (i = 0; i < 3; i++) {
4893 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4894
4895 alu.op = ALU_OP1_LOG_IEEE;
4896 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4897 r600_bytecode_src_set_abs(&alu.src[0]);
4898
4899 alu.dst.sel = ctx->temp_reg;
4900 alu.dst.chan = i;
4901 if (i == 1)
4902 alu.dst.write = 1;
4903 if (i == 2)
4904 alu.last = 1;
4905
4906 r = r600_bytecode_add_alu(ctx->bc, &alu);
4907 if (r)
4908 return r;
4909 }
4910 } else {
4911 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4912
4913 alu.op = ALU_OP1_LOG_IEEE;
4914 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4915 r600_bytecode_src_set_abs(&alu.src[0]);
4916
4917 alu.dst.sel = ctx->temp_reg;
4918 alu.dst.chan = 1;
4919 alu.dst.write = 1;
4920 alu.last = 1;
4921
4922 r = r600_bytecode_add_alu(ctx->bc, &alu);
4923 if (r)
4924 return r;
4925 }
4926
4927 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4928
4929 alu.op = ALU_OP1_FLOOR;
4930 alu.src[0].sel = ctx->temp_reg;
4931 alu.src[0].chan = 1;
4932
4933 alu.dst.sel = ctx->temp_reg;
4934 alu.dst.chan = 1;
4935 alu.dst.write = 1;
4936 alu.last = 1;
4937
4938 r = r600_bytecode_add_alu(ctx->bc, &alu);
4939 if (r)
4940 return r;
4941
4942 if (ctx->bc->chip_class == CAYMAN) {
4943 for (i = 0; i < 3; i++) {
4944 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4945 alu.op = ALU_OP1_EXP_IEEE;
4946 alu.src[0].sel = ctx->temp_reg;
4947 alu.src[0].chan = 1;
4948
4949 alu.dst.sel = ctx->temp_reg;
4950 alu.dst.chan = i;
4951 if (i == 1)
4952 alu.dst.write = 1;
4953 if (i == 2)
4954 alu.last = 1;
4955
4956 r = r600_bytecode_add_alu(ctx->bc, &alu);
4957 if (r)
4958 return r;
4959 }
4960 } else {
4961 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4962 alu.op = ALU_OP1_EXP_IEEE;
4963 alu.src[0].sel = ctx->temp_reg;
4964 alu.src[0].chan = 1;
4965
4966 alu.dst.sel = ctx->temp_reg;
4967 alu.dst.chan = 1;
4968 alu.dst.write = 1;
4969 alu.last = 1;
4970
4971 r = r600_bytecode_add_alu(ctx->bc, &alu);
4972 if (r)
4973 return r;
4974 }
4975
4976 if (ctx->bc->chip_class == CAYMAN) {
4977 for (i = 0; i < 3; i++) {
4978 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4979 alu.op = ALU_OP1_RECIP_IEEE;
4980 alu.src[0].sel = ctx->temp_reg;
4981 alu.src[0].chan = 1;
4982
4983 alu.dst.sel = ctx->temp_reg;
4984 alu.dst.chan = i;
4985 if (i == 1)
4986 alu.dst.write = 1;
4987 if (i == 2)
4988 alu.last = 1;
4989
4990 r = r600_bytecode_add_alu(ctx->bc, &alu);
4991 if (r)
4992 return r;
4993 }
4994 } else {
4995 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4996 alu.op = ALU_OP1_RECIP_IEEE;
4997 alu.src[0].sel = ctx->temp_reg;
4998 alu.src[0].chan = 1;
4999
5000 alu.dst.sel = ctx->temp_reg;
5001 alu.dst.chan = 1;
5002 alu.dst.write = 1;
5003 alu.last = 1;
5004
5005 r = r600_bytecode_add_alu(ctx->bc, &alu);
5006 if (r)
5007 return r;
5008 }
5009
5010 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5011
5012 alu.op = ALU_OP2_MUL;
5013
5014 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5015 r600_bytecode_src_set_abs(&alu.src[0]);
5016
5017 alu.src[1].sel = ctx->temp_reg;
5018 alu.src[1].chan = 1;
5019
5020 alu.dst.sel = ctx->temp_reg;
5021 alu.dst.chan = 1;
5022 alu.dst.write = 1;
5023 alu.last = 1;
5024
5025 r = r600_bytecode_add_alu(ctx->bc, &alu);
5026 if (r)
5027 return r;
5028 }
5029
5030 /* result.z = log2(|src|);*/
5031 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
5032 if (ctx->bc->chip_class == CAYMAN) {
5033 for (i = 0; i < 3; i++) {
5034 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5035
5036 alu.op = ALU_OP1_LOG_IEEE;
5037 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5038 r600_bytecode_src_set_abs(&alu.src[0]);
5039
5040 alu.dst.sel = ctx->temp_reg;
5041 if (i == 2)
5042 alu.dst.write = 1;
5043 alu.dst.chan = i;
5044 if (i == 2)
5045 alu.last = 1;
5046
5047 r = r600_bytecode_add_alu(ctx->bc, &alu);
5048 if (r)
5049 return r;
5050 }
5051 } else {
5052 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5053
5054 alu.op = ALU_OP1_LOG_IEEE;
5055 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5056 r600_bytecode_src_set_abs(&alu.src[0]);
5057
5058 alu.dst.sel = ctx->temp_reg;
5059 alu.dst.write = 1;
5060 alu.dst.chan = 2;
5061 alu.last = 1;
5062
5063 r = r600_bytecode_add_alu(ctx->bc, &alu);
5064 if (r)
5065 return r;
5066 }
5067 }
5068
5069 /* result.w = 1.0; */
5070 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
5071 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5072
5073 alu.op = ALU_OP1_MOV;
5074 alu.src[0].sel = V_SQ_ALU_SRC_1;
5075 alu.src[0].chan = 0;
5076
5077 alu.dst.sel = ctx->temp_reg;
5078 alu.dst.chan = 3;
5079 alu.dst.write = 1;
5080 alu.last = 1;
5081
5082 r = r600_bytecode_add_alu(ctx->bc, &alu);
5083 if (r)
5084 return r;
5085 }
5086
5087 return tgsi_helper_copy(ctx, inst);
5088 }
5089
5090 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
5091 {
5092 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5093 struct r600_bytecode_alu alu;
5094 int r;
5095
5096 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5097
5098 switch (inst->Instruction.Opcode) {
5099 case TGSI_OPCODE_ARL:
5100 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
5101 break;
5102 case TGSI_OPCODE_ARR:
5103 alu.op = ALU_OP1_FLT_TO_INT;
5104 break;
5105 case TGSI_OPCODE_UARL:
5106 alu.op = ALU_OP1_MOV;
5107 break;
5108 default:
5109 assert(0);
5110 return -1;
5111 }
5112
5113 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5114 alu.last = 1;
5115 alu.dst.sel = ctx->bc->ar_reg;
5116 alu.dst.write = 1;
5117 r = r600_bytecode_add_alu(ctx->bc, &alu);
5118 if (r)
5119 return r;
5120
5121 ctx->bc->ar_loaded = 0;
5122 return 0;
5123 }
5124 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
5125 {
5126 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5127 struct r600_bytecode_alu alu;
5128 int r;
5129
5130 switch (inst->Instruction.Opcode) {
5131 case TGSI_OPCODE_ARL:
5132 memset(&alu, 0, sizeof(alu));
5133 alu.op = ALU_OP1_FLOOR;
5134 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5135 alu.dst.sel = ctx->bc->ar_reg;
5136 alu.dst.write = 1;
5137 alu.last = 1;
5138
5139 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5140 return r;
5141
5142 memset(&alu, 0, sizeof(alu));
5143 alu.op = ALU_OP1_FLT_TO_INT;
5144 alu.src[0].sel = ctx->bc->ar_reg;
5145 alu.dst.sel = ctx->bc->ar_reg;
5146 alu.dst.write = 1;
5147 alu.last = 1;
5148
5149 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5150 return r;
5151 break;
5152 case TGSI_OPCODE_ARR:
5153 memset(&alu, 0, sizeof(alu));
5154 alu.op = ALU_OP1_FLT_TO_INT;
5155 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5156 alu.dst.sel = ctx->bc->ar_reg;
5157 alu.dst.write = 1;
5158 alu.last = 1;
5159
5160 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5161 return r;
5162 break;
5163 case TGSI_OPCODE_UARL:
5164 memset(&alu, 0, sizeof(alu));
5165 alu.op = ALU_OP1_MOV;
5166 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5167 alu.dst.sel = ctx->bc->ar_reg;
5168 alu.dst.write = 1;
5169 alu.last = 1;
5170
5171 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5172 return r;
5173 break;
5174 default:
5175 assert(0);
5176 return -1;
5177 }
5178
5179 ctx->bc->ar_loaded = 0;
5180 return 0;
5181 }
5182
5183 static int tgsi_opdst(struct r600_shader_ctx *ctx)
5184 {
5185 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5186 struct r600_bytecode_alu alu;
5187 int i, r = 0;
5188
5189 for (i = 0; i < 4; i++) {
5190 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5191
5192 alu.op = ALU_OP2_MUL;
5193 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5194
5195 if (i == 0 || i == 3) {
5196 alu.src[0].sel = V_SQ_ALU_SRC_1;
5197 } else {
5198 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5199 }
5200
5201 if (i == 0 || i == 2) {
5202 alu.src[1].sel = V_SQ_ALU_SRC_1;
5203 } else {
5204 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5205 }
5206 if (i == 3)
5207 alu.last = 1;
5208 r = r600_bytecode_add_alu(ctx->bc, &alu);
5209 if (r)
5210 return r;
5211 }
5212 return 0;
5213 }
5214
5215 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
5216 {
5217 struct r600_bytecode_alu alu;
5218 int r;
5219
5220 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5221 alu.op = opcode;
5222 alu.execute_mask = 1;
5223 alu.update_pred = 1;
5224
5225 alu.dst.sel = ctx->temp_reg;
5226 alu.dst.write = 1;
5227 alu.dst.chan = 0;
5228
5229 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5230 alu.src[1].sel = V_SQ_ALU_SRC_0;
5231 alu.src[1].chan = 0;
5232
5233 alu.last = 1;
5234
5235 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
5236 if (r)
5237 return r;
5238 return 0;
5239 }
5240
5241 static int pops(struct r600_shader_ctx *ctx, int pops)
5242 {
5243 unsigned force_pop = ctx->bc->force_add_cf;
5244
5245 if (!force_pop) {
5246 int alu_pop = 3;
5247 if (ctx->bc->cf_last) {
5248 if (ctx->bc->cf_last->op == CF_OP_ALU)
5249 alu_pop = 0;
5250 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
5251 alu_pop = 1;
5252 }
5253 alu_pop += pops;
5254 if (alu_pop == 1) {
5255 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
5256 ctx->bc->force_add_cf = 1;
5257 } else if (alu_pop == 2) {
5258 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
5259 ctx->bc->force_add_cf = 1;
5260 } else {
5261 force_pop = 1;
5262 }
5263 }
5264
5265 if (force_pop) {
5266 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
5267 ctx->bc->cf_last->pop_count = pops;
5268 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5269 }
5270
5271 return 0;
5272 }
5273
5274 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
5275 unsigned reason)
5276 {
5277 struct r600_stack_info *stack = &ctx->bc->stack;
5278 unsigned elements, entries;
5279
5280 unsigned entry_size = stack->entry_size;
5281
5282 elements = (stack->loop + stack->push_wqm ) * entry_size;
5283 elements += stack->push;
5284
5285 switch (ctx->bc->chip_class) {
5286 case R600:
5287 case R700:
5288 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
5289 * the stack must be reserved to hold the current active/continue
5290 * masks */
5291 if (reason == FC_PUSH_VPM) {
5292 elements += 2;
5293 }
5294 break;
5295
5296 case CAYMAN:
5297 /* r9xx: any stack operation on empty stack consumes 2 additional
5298 * elements */
5299 elements += 2;
5300
5301 /* fallthrough */
5302 /* FIXME: do the two elements added above cover the cases for the
5303 * r8xx+ below? */
5304
5305 case EVERGREEN:
5306 /* r8xx+: 2 extra elements are not always required, but one extra
5307 * element must be added for each of the following cases:
5308 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
5309 * stack usage.
5310 * (Currently we don't use ALU_ELSE_AFTER.)
5311 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
5312 * PUSH instruction executed.
5313 *
5314 * NOTE: it seems we also need to reserve additional element in some
5315 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
5316 * then STACK_SIZE should be 2 instead of 1 */
5317 if (reason == FC_PUSH_VPM) {
5318 elements += 1;
5319 }
5320 break;
5321
5322 default:
5323 assert(0);
5324 break;
5325 }
5326
5327 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
5328 * for all chips, so we use 4 in the final formula, not the real entry_size
5329 * for the chip */
5330 entry_size = 4;
5331
5332 entries = (elements + (entry_size - 1)) / entry_size;
5333
5334 if (entries > stack->max_entries)
5335 stack->max_entries = entries;
5336 }
5337
5338 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
5339 {
5340 switch(reason) {
5341 case FC_PUSH_VPM:
5342 --ctx->bc->stack.push;
5343 assert(ctx->bc->stack.push >= 0);
5344 break;
5345 case FC_PUSH_WQM:
5346 --ctx->bc->stack.push_wqm;
5347 assert(ctx->bc->stack.push_wqm >= 0);
5348 break;
5349 case FC_LOOP:
5350 --ctx->bc->stack.loop;
5351 assert(ctx->bc->stack.loop >= 0);
5352 break;
5353 default:
5354 assert(0);
5355 break;
5356 }
5357 }
5358
5359 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
5360 {
5361 switch (reason) {
5362 case FC_PUSH_VPM:
5363 ++ctx->bc->stack.push;
5364 break;
5365 case FC_PUSH_WQM:
5366 ++ctx->bc->stack.push_wqm;
5367 case FC_LOOP:
5368 ++ctx->bc->stack.loop;
5369 break;
5370 default:
5371 assert(0);
5372 }
5373
5374 callstack_update_max_depth(ctx, reason);
5375 }
5376
5377 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
5378 {
5379 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
5380
5381 sp->mid = realloc((void *)sp->mid,
5382 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
5383 sp->mid[sp->num_mid] = ctx->bc->cf_last;
5384 sp->num_mid++;
5385 }
5386
5387 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
5388 {
5389 ctx->bc->fc_sp++;
5390 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
5391 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
5392 }
5393
5394 static void fc_poplevel(struct r600_shader_ctx *ctx)
5395 {
5396 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
5397 free(sp->mid);
5398 sp->mid = NULL;
5399 sp->num_mid = 0;
5400 sp->start = NULL;
5401 sp->type = 0;
5402 ctx->bc->fc_sp--;
5403 }
5404
5405 #if 0
5406 static int emit_return(struct r600_shader_ctx *ctx)
5407 {
5408 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
5409 return 0;
5410 }
5411
5412 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
5413 {
5414
5415 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
5416 ctx->bc->cf_last->pop_count = pops;
5417 /* XXX work out offset */
5418 return 0;
5419 }
5420
5421 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
5422 {
5423 return 0;
5424 }
5425
5426 static void emit_testflag(struct r600_shader_ctx *ctx)
5427 {
5428
5429 }
5430
5431 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
5432 {
5433 emit_testflag(ctx);
5434 emit_jump_to_offset(ctx, 1, 4);
5435 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
5436 pops(ctx, ifidx + 1);
5437 emit_return(ctx);
5438 }
5439
5440 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
5441 {
5442 emit_testflag(ctx);
5443
5444 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5445 ctx->bc->cf_last->pop_count = 1;
5446
5447 fc_set_mid(ctx, fc_sp);
5448
5449 pops(ctx, 1);
5450 }
5451 #endif
5452
5453 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
5454 {
5455 int alu_type = CF_OP_ALU_PUSH_BEFORE;
5456
5457 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
5458 * LOOP_STARTxxx for nested loops may put the branch stack into a state
5459 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
5460 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
5461 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
5462 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
5463 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5464 alu_type = CF_OP_ALU;
5465 }
5466
5467 emit_logic_pred(ctx, opcode, alu_type);
5468
5469 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
5470
5471 fc_pushlevel(ctx, FC_IF);
5472
5473 callstack_push(ctx, FC_PUSH_VPM);
5474 return 0;
5475 }
5476
5477 static int tgsi_if(struct r600_shader_ctx *ctx)
5478 {
5479 return emit_if(ctx, ALU_OP2_PRED_SETNE);
5480 }
5481
5482 static int tgsi_uif(struct r600_shader_ctx *ctx)
5483 {
5484 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
5485 }
5486
5487 static int tgsi_else(struct r600_shader_ctx *ctx)
5488 {
5489 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
5490 ctx->bc->cf_last->pop_count = 1;
5491
5492 fc_set_mid(ctx, ctx->bc->fc_sp);
5493 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
5494 return 0;
5495 }
5496
5497 static int tgsi_endif(struct r600_shader_ctx *ctx)
5498 {
5499 pops(ctx, 1);
5500 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
5501 R600_ERR("if/endif unbalanced in shader\n");
5502 return -1;
5503 }
5504
5505 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
5506 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5507 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
5508 } else {
5509 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
5510 }
5511 fc_poplevel(ctx);
5512
5513 callstack_pop(ctx, FC_PUSH_VPM);
5514 return 0;
5515 }
5516
5517 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
5518 {
5519 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
5520 * limited to 4096 iterations, like the other LOOP_* instructions. */
5521 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
5522
5523 fc_pushlevel(ctx, FC_LOOP);
5524
5525 /* check stack depth */
5526 callstack_push(ctx, FC_LOOP);
5527 return 0;
5528 }
5529
5530 static int tgsi_endloop(struct r600_shader_ctx *ctx)
5531 {
5532 int i;
5533
5534 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
5535
5536 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
5537 R600_ERR("loop/endloop in shader code are not paired.\n");
5538 return -EINVAL;
5539 }
5540
5541 /* fixup loop pointers - from r600isa
5542 LOOP END points to CF after LOOP START,
5543 LOOP START point to CF after LOOP END
5544 BRK/CONT point to LOOP END CF
5545 */
5546 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
5547
5548 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5549
5550 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
5551 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
5552 }
5553 /* XXX add LOOPRET support */
5554 fc_poplevel(ctx);
5555 callstack_pop(ctx, FC_LOOP);
5556 return 0;
5557 }
5558
5559 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
5560 {
5561 unsigned int fscp;
5562
5563 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
5564 {
5565 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
5566 break;
5567 }
5568
5569 if (fscp == 0) {
5570 R600_ERR("Break not inside loop/endloop pair\n");
5571 return -EINVAL;
5572 }
5573
5574 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5575
5576 fc_set_mid(ctx, fscp);
5577
5578 return 0;
5579 }
5580
5581 static int tgsi_umad(struct r600_shader_ctx *ctx)
5582 {
5583 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5584 struct r600_bytecode_alu alu;
5585 int i, j, k, r;
5586 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5587
5588 /* src0 * src1 */
5589 for (i = 0; i < lasti + 1; i++) {
5590 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5591 continue;
5592
5593 if (ctx->bc->chip_class == CAYMAN) {
5594 for (j = 0 ; j < 4; j++) {
5595 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5596
5597 alu.op = ALU_OP2_MULLO_UINT;
5598 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
5599 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
5600 }
5601 tgsi_dst(ctx, &inst->Dst[0], j, &alu.dst);
5602 alu.dst.sel = ctx->temp_reg;
5603 alu.dst.write = (j == i);
5604 if (j == 3)
5605 alu.last = 1;
5606 r = r600_bytecode_add_alu(ctx->bc, &alu);
5607 if (r)
5608 return r;
5609 }
5610 } else {
5611 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5612
5613 alu.dst.chan = i;
5614 alu.dst.sel = ctx->temp_reg;
5615 alu.dst.write = 1;
5616
5617 alu.op = ALU_OP2_MULLO_UINT;
5618 for (j = 0; j < 2; j++) {
5619 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
5620 }
5621
5622 alu.last = 1;
5623 r = r600_bytecode_add_alu(ctx->bc, &alu);
5624 if (r)
5625 return r;
5626 }
5627 }
5628
5629
5630 for (i = 0; i < lasti + 1; i++) {
5631 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5632 continue;
5633
5634 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5635 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5636
5637 alu.op = ALU_OP2_ADD_INT;
5638
5639 alu.src[0].sel = ctx->temp_reg;
5640 alu.src[0].chan = i;
5641
5642 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5643 if (i == lasti) {
5644 alu.last = 1;
5645 }
5646 r = r600_bytecode_add_alu(ctx->bc, &alu);
5647 if (r)
5648 return r;
5649 }
5650 return 0;
5651 }
5652
5653 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
5654 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_r600_arl},
5655 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
5656 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
5657
5658 /* XXX:
5659 * For state trackers other than OpenGL, we'll want to use
5660 * _RECIP_IEEE instead.
5661 */
5662 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
5663
5664 {TGSI_OPCODE_RSQ, 0, ALU_OP0_NOP, tgsi_rsq},
5665 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
5666 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
5667 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
5668 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
5669 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
5670 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
5671 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
5672 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
5673 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
5674 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
5675 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
5676 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
5677 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
5678 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
5679 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
5680 /* gap */
5681 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
5682 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
5683 /* gap */
5684 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
5685 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
5686 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
5687 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
5688 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
5689 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
5690 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
5691 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
5692 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
5693 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
5694 /* gap */
5695 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
5696 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
5697 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
5698 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
5699 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
5700 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
5701 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
5702 {TGSI_OPCODE_KILP, 0, ALU_OP2_KILLGT, tgsi_kill}, /* predicated kill */
5703 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5704 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5705 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5706 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5707 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5708 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
5709 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5710 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
5711 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
5712 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
5713 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
5714 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
5715 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
5716 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
5717 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
5718 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5719 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5720 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5721 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5722 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
5723 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
5724 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_r600_arl},
5725 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
5726 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
5727 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
5728 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
5729 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
5730 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
5731 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5732 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
5733 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
5734 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
5735 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5736 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
5737 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
5738 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
5739 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
5740 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
5741 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
5742 /* gap */
5743 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
5744 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
5745 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
5746 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
5747 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
5748 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
5749 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
5750 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
5751 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2_trans},
5752 /* gap */
5753 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
5754 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
5755 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
5756 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
5757 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
5758 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5759 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
5760 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5761 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
5762 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
5763 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
5764 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
5765 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5766 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
5767 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5768 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5769 /* gap */
5770 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
5771 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
5772 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
5773 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
5774 /* gap */
5775 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
5776 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
5777 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
5778 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
5779 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
5780 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
5781 /* gap */
5782 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
5783 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
5784 {TGSI_OPCODE_KIL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
5785 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
5786 /* gap */
5787 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
5788 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
5789 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
5790 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
5791 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
5792 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
5793 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
5794 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2_trans},
5795 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
5796 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
5797 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
5798 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
5799 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
5800 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
5801 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
5802 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
5803 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
5804 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
5805 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
5806 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
5807 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2_trans},
5808 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
5809 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2_swap},
5810 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
5811 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
5812 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
5813 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
5814 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
5815 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
5816 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
5817 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
5818 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
5819 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
5820 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
5821 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
5822 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
5823 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
5824 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
5825 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
5826 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_r600_arl},
5827 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
5828 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
5829 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
5830 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5831 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
5832 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5833 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5834 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5835 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
5836 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
5837 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
5838 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
5839 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
5840 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
5841 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
5842 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
5843 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
5844 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
5845 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
5846 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
5847 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5848 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5849 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
5850 };
5851
5852 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
5853 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
5854 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
5855 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
5856 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
5857 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
5858 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
5859 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
5860 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
5861 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
5862 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
5863 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
5864 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
5865 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
5866 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
5867 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
5868 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
5869 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
5870 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
5871 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
5872 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
5873 /* gap */
5874 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
5875 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
5876 /* gap */
5877 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
5878 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
5879 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
5880 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
5881 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
5882 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
5883 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
5884 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
5885 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
5886 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
5887 /* gap */
5888 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
5889 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
5890 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
5891 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
5892 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
5893 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
5894 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
5895 {TGSI_OPCODE_KILP, 0, ALU_OP2_KILLGT, tgsi_kill}, /* predicated kill */
5896 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5897 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5898 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5899 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5900 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5901 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
5902 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5903 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
5904 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
5905 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
5906 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
5907 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
5908 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
5909 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
5910 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
5911 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5912 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5913 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5914 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5915 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
5916 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
5917 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
5918 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
5919 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
5920 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
5921 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
5922 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
5923 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
5924 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5925 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
5926 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
5927 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
5928 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5929 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
5930 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
5931 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
5932 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
5933 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
5934 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
5935 /* gap */
5936 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
5937 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
5938 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
5939 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
5940 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
5941 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
5942 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
5943 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
5944 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
5945 /* gap */
5946 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
5947 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
5948 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
5949 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
5950 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
5951 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5952 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
5953 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5954 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
5955 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
5956 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
5957 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
5958 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5959 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
5960 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5961 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5962 /* gap */
5963 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
5964 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
5965 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
5966 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
5967 /* gap */
5968 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
5969 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
5970 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
5971 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
5972 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
5973 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
5974 /* gap */
5975 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
5976 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
5977 {TGSI_OPCODE_KIL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
5978 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
5979 /* gap */
5980 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
5981 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_f2i},
5982 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
5983 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
5984 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
5985 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
5986 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
5987 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
5988 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
5989 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_f2i},
5990 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
5991 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
5992 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
5993 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
5994 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
5995 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
5996 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
5997 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
5998 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
5999 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6000 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6001 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6002 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6003 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6004 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6005 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6006 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6007 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6008 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6009 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6010 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6011 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6012 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6013 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6014 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6015 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6016 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6017 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6018 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6019 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6020 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6021 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6022 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6023 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6024 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6025 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6026 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6027 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6028 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6029 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6030 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6031 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6032 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6033 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6034 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6035 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6036 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6037 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6038 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6039 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6040 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6041 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6042 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6043 };
6044
6045 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
6046 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
6047 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6048 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6049 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
6050 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
6051 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6052 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6053 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6054 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6055 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6056 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6057 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6058 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6059 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6060 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6061 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6062 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6063 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6064 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6065 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6066 /* gap */
6067 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
6068 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6069 /* gap */
6070 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6071 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6072 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6073 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6074 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6075 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6076 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
6077 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
6078 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, cayman_pow},
6079 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6080 /* gap */
6081 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6082 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6083 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6084 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6085 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, cayman_trig},
6086 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6087 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6088 {TGSI_OPCODE_KILP, 0, ALU_OP2_KILLGT, tgsi_kill}, /* predicated kill */
6089 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6090 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6091 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6092 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6093 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6094 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6095 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6096 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6097 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, cayman_trig},
6098 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6099 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6100 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6101 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6102 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6103 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6104 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6105 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6106 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6107 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6108 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6109 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6110 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6111 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6112 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6113 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6114 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6115 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6116 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6117 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6118 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6119 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6120 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6121 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6122 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6123 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6124 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6125 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6126 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6127 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6128 /* gap */
6129 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6130 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6131 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6132 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6133 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6134 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2},
6135 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6136 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6137 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6138 /* gap */
6139 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6140 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6141 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6142 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6143 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6144 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6145 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6146 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6147 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6148 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
6149 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
6150 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6151 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6152 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6153 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6154 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6155 /* gap */
6156 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6157 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6158 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6159 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6160 /* gap */
6161 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
6162 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
6163 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
6164 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
6165 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6166 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6167 /* gap */
6168 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6169 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6170 {TGSI_OPCODE_KIL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6171 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6172 /* gap */
6173 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6174 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2},
6175 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6176 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6177 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6178 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6179 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6180 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
6181 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6182 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2},
6183 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2},
6184 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6185 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6186 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6187 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6188 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6189 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6190 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_INT, cayman_mul_int_instr},
6191 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6192 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6193 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6194 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6195 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6196 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6197 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6198 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6199 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6200 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6201 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6202 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6203 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6204 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6205 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6206 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6207 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6208 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6209 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6210 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6211 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6212 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6213 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6214 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6215 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6216 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6217 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6218 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6219 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6220 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6221 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6222 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6223 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6224 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6225 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6226 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6227 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6228 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6229 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6230 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6231 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6232 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6233 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6234 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6235 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6236 };