2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_info.h"
25 #include "tgsi/tgsi_parse.h"
26 #include "tgsi/tgsi_scan.h"
27 #include "tgsi/tgsi_dump.h"
28 #include "util/u_format.h"
29 #include "r600_pipe.h"
32 #include "r600_formats.h"
33 #include "r600_opcodes.h"
40 Why CAYMAN got loops for lots of instructions is explained here.
42 -These 8xx t-slot only ops are implemented in all vector slots.
43 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
44 These 8xx t-slot only opcodes become vector ops, with all four
45 slots expecting the arguments on sources a and b. Result is
46 broadcast to all channels.
47 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
48 These 8xx t-slot only opcodes become vector ops in the z, y, and
50 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
51 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
54 The w slot may have an independent co-issued operation, or if the
55 result is required to be in the w slot, the opcode above may be
56 issued in the w slot as well.
57 The compiler must issue the source argument to slots z, y, and x
60 static int r600_pipe_shader(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
62 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
63 struct r600_shader
*rshader
= &shader
->shader
;
68 if (shader
->bo
== NULL
) {
69 shader
->bo
= (struct r600_resource
*)
70 pipe_buffer_create(ctx
->screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_IMMUTABLE
, rshader
->bc
.ndw
* 4);
71 if (shader
->bo
== NULL
) {
74 ptr
= (uint32_t*)rctx
->ws
->buffer_map(shader
->bo
->buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
75 if (R600_BIG_ENDIAN
) {
76 for (i
= 0; i
< rshader
->bc
.ndw
; ++i
) {
77 ptr
[i
] = bswap_32(rshader
->bc
.bytecode
[i
]);
80 memcpy(ptr
, rshader
->bc
.bytecode
, rshader
->bc
.ndw
* sizeof(*ptr
));
82 rctx
->ws
->buffer_unmap(shader
->bo
->buf
);
85 switch (rshader
->processor_type
) {
86 case TGSI_PROCESSOR_VERTEX
:
87 if (rctx
->chip_class
>= EVERGREEN
) {
88 evergreen_pipe_shader_vs(ctx
, shader
);
90 r600_pipe_shader_vs(ctx
, shader
);
93 case TGSI_PROCESSOR_FRAGMENT
:
94 if (rctx
->chip_class
>= EVERGREEN
) {
95 evergreen_pipe_shader_ps(ctx
, shader
);
97 r600_pipe_shader_ps(ctx
, shader
);
106 static int r600_shader_from_tgsi(struct r600_context
* rctx
, struct r600_pipe_shader
*pipeshader
);
108 int r600_pipe_shader_create(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
110 static int dump_shaders
= -1;
111 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
114 /* Would like some magic "get_bool_option_once" routine.
116 if (dump_shaders
== -1)
117 dump_shaders
= debug_get_bool_option("R600_DUMP_SHADERS", FALSE
);
120 fprintf(stderr
, "--------------------------------------------------------------\n");
121 tgsi_dump(shader
->tokens
, 0);
123 if (shader
->so
.num_outputs
) {
125 fprintf(stderr
, "STREAMOUT\n");
126 for (i
= 0; i
< shader
->so
.num_outputs
; i
++) {
127 unsigned mask
= ((1 << shader
->so
.output
[i
].num_components
) - 1) <<
128 shader
->so
.output
[i
].start_component
;
129 fprintf(stderr
, " %i: MEM_STREAM0_BUF%i OUT[%i].%s%s%s%s\n", i
,
130 shader
->so
.output
[i
].output_buffer
, shader
->so
.output
[i
].register_index
,
131 mask
& 1 ? "x" : "_",
132 (mask
>> 1) & 1 ? "y" : "_",
133 (mask
>> 2) & 1 ? "z" : "_",
134 (mask
>> 3) & 1 ? "w" : "_");
138 r
= r600_shader_from_tgsi(rctx
, shader
);
140 R600_ERR("translation from TGSI failed !\n");
143 r
= r600_bytecode_build(&shader
->shader
.bc
);
145 R600_ERR("building bytecode failed !\n");
149 r600_bytecode_dump(&shader
->shader
.bc
);
150 fprintf(stderr
, "______________________________________________________________\n");
152 return r600_pipe_shader(ctx
, shader
);
155 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
157 pipe_resource_reference((struct pipe_resource
**)&shader
->bo
, NULL
);
158 r600_bytecode_clear(&shader
->shader
.bc
);
160 memset(&shader
->shader
,0,sizeof(struct r600_shader
));
164 * tgsi -> r600 shader
166 struct r600_shader_tgsi_instruction
;
168 struct r600_shader_src
{
177 struct r600_shader_ctx
{
178 struct tgsi_shader_info info
;
179 struct tgsi_parse_context parse
;
180 const struct tgsi_token
*tokens
;
182 unsigned file_offset
[TGSI_FILE_COUNT
];
184 struct r600_shader_tgsi_instruction
*inst_info
;
185 struct r600_bytecode
*bc
;
186 struct r600_shader
*shader
;
187 struct r600_shader_src src
[4];
190 uint32_t max_driver_temp_used
;
191 /* needed for evergreen interpolation */
192 boolean input_centroid
;
193 boolean input_linear
;
194 boolean input_perspective
;
198 boolean clip_vertex_write
;
203 struct r600_shader_tgsi_instruction
{
204 unsigned tgsi_opcode
;
206 unsigned r600_opcode
;
207 int (*process
)(struct r600_shader_ctx
*ctx
);
210 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[], eg_shader_tgsi_instruction
[], cm_shader_tgsi_instruction
[];
211 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
);
213 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
215 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
218 if (i
->Instruction
.NumDstRegs
> 1) {
219 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
222 if (i
->Instruction
.Predicate
) {
223 R600_ERR("predicate unsupported\n");
227 if (i
->Instruction
.Label
) {
228 R600_ERR("label unsupported\n");
232 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
233 if (i
->Src
[j
].Register
.Dimension
) {
234 R600_ERR("unsupported src %d (dimension %d)\n", j
,
235 i
->Src
[j
].Register
.Dimension
);
239 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
240 if (i
->Dst
[j
].Register
.Dimension
) {
241 R600_ERR("unsupported dst (dimension)\n");
248 static int evergreen_interp_alu(struct r600_shader_ctx
*ctx
, int input
)
251 struct r600_bytecode_alu alu
;
252 int gpr
= 0, base_chan
= 0;
255 if (ctx
->shader
->input
[input
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
) {
257 if (ctx
->shader
->input
[input
].centroid
)
259 } else if (ctx
->shader
->input
[input
].interpolate
== TGSI_INTERPOLATE_LINEAR
) {
261 /* if we have perspective add one */
262 if (ctx
->input_perspective
) {
264 /* if we have perspective centroid */
265 if (ctx
->input_centroid
)
268 if (ctx
->shader
->input
[input
].centroid
)
272 /* work out gpr and base_chan from index */
274 base_chan
= (2 * (ij_index
% 2)) + 1;
276 for (i
= 0; i
< 8; i
++) {
277 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
280 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW
;
282 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY
;
284 if ((i
> 1) && (i
< 6)) {
285 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
289 alu
.dst
.chan
= i
% 4;
291 alu
.src
[0].sel
= gpr
;
292 alu
.src
[0].chan
= (base_chan
- (i
% 2));
294 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
296 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
299 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
306 static int evergreen_interp_flat(struct r600_shader_ctx
*ctx
, int input
)
309 struct r600_bytecode_alu alu
;
311 for (i
= 0; i
< 4; i
++) {
312 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
314 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0
;
316 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
321 alu
.src
[0].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
326 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
334 * Special export handling in shaders
336 * shader export ARRAY_BASE for EXPORT_POS:
339 * 62, 63 are clip distance vectors
341 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
342 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
343 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
344 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
345 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
346 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
347 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
348 * exclusive from render target index)
349 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
352 * shader export ARRAY_BASE for EXPORT_PIXEL:
354 * 61 computed Z vector
356 * The use of the values exported in the computed Z vector are controlled
357 * by DB_SHADER_CONTROL:
358 * Z_EXPORT_ENABLE - Z as a float in RED
359 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
360 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
361 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
362 * DB_SOURCE_FORMAT - export control restrictions
367 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
368 static int r600_spi_sid(struct r600_shader_io
* io
)
370 int index
, name
= io
->name
;
372 /* These params are handled differently, they don't need
373 * semantic indices, so we'll use 0 for them.
375 if (name
== TGSI_SEMANTIC_POSITION
||
376 name
== TGSI_SEMANTIC_PSIZE
||
377 name
== TGSI_SEMANTIC_FACE
)
380 if (name
== TGSI_SEMANTIC_GENERIC
) {
381 /* For generic params simply use sid from tgsi */
384 /* For non-generic params - pack name and sid into 8 bits */
385 index
= 0x80 | (name
<<3) | (io
->sid
);
388 /* Make sure that all really used indices have nonzero value, so
389 * we can just compare it to 0 later instead of comparing the name
390 * with different values to detect special cases. */
397 /* turn input into interpolate on EG */
398 static int evergreen_interp_input(struct r600_shader_ctx
*ctx
, int index
)
402 if (ctx
->shader
->input
[index
].spi_sid
) {
403 ctx
->shader
->input
[index
].lds_pos
= ctx
->shader
->nlds
++;
404 if (ctx
->shader
->input
[index
].interpolate
> 0) {
405 r
= evergreen_interp_alu(ctx
, index
);
407 r
= evergreen_interp_flat(ctx
, index
);
413 static int select_twoside_color(struct r600_shader_ctx
*ctx
, int front
, int back
)
415 struct r600_bytecode_alu alu
;
417 int gpr_front
= ctx
->shader
->input
[front
].gpr
;
418 int gpr_back
= ctx
->shader
->input
[back
].gpr
;
420 for (i
= 0; i
< 4; i
++) {
421 memset(&alu
, 0, sizeof(alu
));
422 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
425 alu
.dst
.sel
= gpr_front
;
426 alu
.src
[0].sel
= ctx
->face_gpr
;
427 alu
.src
[1].sel
= gpr_front
;
428 alu
.src
[2].sel
= gpr_back
;
435 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
442 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
444 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
448 switch (d
->Declaration
.File
) {
449 case TGSI_FILE_INPUT
:
450 i
= ctx
->shader
->ninput
++;
451 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
452 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
;
453 ctx
->shader
->input
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->input
[i
]);
454 ctx
->shader
->input
[i
].interpolate
= d
->Declaration
.Interpolate
;
455 ctx
->shader
->input
[i
].centroid
= d
->Declaration
.Centroid
;
456 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + d
->Range
.First
;
457 if (ctx
->type
== TGSI_PROCESSOR_FRAGMENT
) {
458 switch (ctx
->shader
->input
[i
].name
) {
459 case TGSI_SEMANTIC_FACE
:
460 ctx
->face_gpr
= ctx
->shader
->input
[i
].gpr
;
462 case TGSI_SEMANTIC_COLOR
:
465 case TGSI_SEMANTIC_POSITION
:
466 ctx
->fragcoord_input
= i
;
469 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
470 if ((r
= evergreen_interp_input(ctx
, i
)))
475 case TGSI_FILE_OUTPUT
:
476 i
= ctx
->shader
->noutput
++;
477 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
478 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
;
479 ctx
->shader
->output
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->output
[i
]);
480 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + d
->Range
.First
;
481 ctx
->shader
->output
[i
].interpolate
= d
->Declaration
.Interpolate
;
482 ctx
->shader
->output
[i
].write_mask
= d
->Declaration
.UsageMask
;
483 if (ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
484 switch (d
->Semantic
.Name
) {
485 case TGSI_SEMANTIC_CLIPDIST
:
486 ctx
->shader
->clip_dist_write
|= d
->Declaration
.UsageMask
<< (d
->Semantic
.Index
<< 2);
488 case TGSI_SEMANTIC_PSIZE
:
489 ctx
->shader
->vs_out_misc_write
= 1;
490 ctx
->shader
->vs_out_point_size
= 1;
492 case TGSI_SEMANTIC_CLIPVERTEX
:
493 ctx
->clip_vertex_write
= TRUE
;
499 case TGSI_FILE_CONSTANT
:
500 case TGSI_FILE_TEMPORARY
:
501 case TGSI_FILE_SAMPLER
:
502 case TGSI_FILE_ADDRESS
:
505 case TGSI_FILE_SYSTEM_VALUE
:
506 if (d
->Semantic
.Name
== TGSI_SEMANTIC_INSTANCEID
) {
507 struct r600_bytecode_alu alu
;
508 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
510 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
);
519 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
522 } else if (d
->Semantic
.Name
== TGSI_SEMANTIC_VERTEXID
)
525 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
531 static int r600_get_temp(struct r600_shader_ctx
*ctx
)
533 return ctx
->temp_reg
+ ctx
->max_driver_temp_used
++;
537 * for evergreen we need to scan the shader to find the number of GPRs we need to
538 * reserve for interpolation.
540 * we need to know if we are going to emit
541 * any centroid inputs
542 * if perspective and linear are required
544 static int evergreen_gpr_count(struct r600_shader_ctx
*ctx
)
549 ctx
->input_linear
= FALSE
;
550 ctx
->input_perspective
= FALSE
;
551 ctx
->input_centroid
= FALSE
;
552 ctx
->num_interp_gpr
= 1;
554 /* any centroid inputs */
555 for (i
= 0; i
< ctx
->info
.num_inputs
; i
++) {
556 /* skip position/face */
557 if (ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_POSITION
||
558 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_FACE
)
560 if (ctx
->info
.input_interpolate
[i
] == TGSI_INTERPOLATE_LINEAR
)
561 ctx
->input_linear
= TRUE
;
562 if (ctx
->info
.input_interpolate
[i
] == TGSI_INTERPOLATE_PERSPECTIVE
)
563 ctx
->input_perspective
= TRUE
;
564 if (ctx
->info
.input_centroid
[i
])
565 ctx
->input_centroid
= TRUE
;
569 /* ignoring sample for now */
570 if (ctx
->input_perspective
)
572 if (ctx
->input_linear
)
574 if (ctx
->input_centroid
)
577 ctx
->num_interp_gpr
+= (num_baryc
+ 1) >> 1;
579 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
580 return ctx
->num_interp_gpr
;
583 static void tgsi_src(struct r600_shader_ctx
*ctx
,
584 const struct tgsi_full_src_register
*tgsi_src
,
585 struct r600_shader_src
*r600_src
)
587 memset(r600_src
, 0, sizeof(*r600_src
));
588 r600_src
->swizzle
[0] = tgsi_src
->Register
.SwizzleX
;
589 r600_src
->swizzle
[1] = tgsi_src
->Register
.SwizzleY
;
590 r600_src
->swizzle
[2] = tgsi_src
->Register
.SwizzleZ
;
591 r600_src
->swizzle
[3] = tgsi_src
->Register
.SwizzleW
;
592 r600_src
->neg
= tgsi_src
->Register
.Negate
;
593 r600_src
->abs
= tgsi_src
->Register
.Absolute
;
595 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
597 if ((tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleY
) &&
598 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleZ
) &&
599 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleW
)) {
601 index
= tgsi_src
->Register
.Index
* 4 + tgsi_src
->Register
.SwizzleX
;
602 r600_bytecode_special_constants(ctx
->literals
[index
], &r600_src
->sel
, &r600_src
->neg
);
603 if (r600_src
->sel
!= V_SQ_ALU_SRC_LITERAL
)
606 index
= tgsi_src
->Register
.Index
;
607 r600_src
->sel
= V_SQ_ALU_SRC_LITERAL
;
608 memcpy(r600_src
->value
, ctx
->literals
+ index
* 4, sizeof(r600_src
->value
));
609 } else if (tgsi_src
->Register
.File
== TGSI_FILE_SYSTEM_VALUE
) {
610 if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INSTANCEID
) {
611 r600_src
->swizzle
[0] = 3;
612 r600_src
->swizzle
[1] = 3;
613 r600_src
->swizzle
[2] = 3;
614 r600_src
->swizzle
[3] = 3;
616 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_VERTEXID
) {
617 r600_src
->swizzle
[0] = 0;
618 r600_src
->swizzle
[1] = 0;
619 r600_src
->swizzle
[2] = 0;
620 r600_src
->swizzle
[3] = 0;
624 if (tgsi_src
->Register
.Indirect
)
625 r600_src
->rel
= V_SQ_REL_RELATIVE
;
626 r600_src
->sel
= tgsi_src
->Register
.Index
;
627 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
631 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
, unsigned int offset
, unsigned int dst_reg
)
633 struct r600_bytecode_vtx vtx
;
638 struct r600_bytecode_alu alu
;
640 memset(&alu
, 0, sizeof(alu
));
642 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
643 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
645 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
646 alu
.src
[1].value
= offset
;
648 alu
.dst
.sel
= dst_reg
;
652 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
657 ar_reg
= ctx
->bc
->ar_reg
;
660 memset(&vtx
, 0, sizeof(vtx
));
661 vtx
.fetch_type
= 2; /* VTX_FETCH_NO_INDEX_OFFSET */
662 vtx
.src_gpr
= ar_reg
;
663 vtx
.mega_fetch_count
= 16;
664 vtx
.dst_gpr
= dst_reg
;
665 vtx
.dst_sel_x
= 0; /* SEL_X */
666 vtx
.dst_sel_y
= 1; /* SEL_Y */
667 vtx
.dst_sel_z
= 2; /* SEL_Z */
668 vtx
.dst_sel_w
= 3; /* SEL_W */
669 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
670 vtx
.num_format_all
= 2; /* NUM_FORMAT_SCALED */
671 vtx
.format_comp_all
= 1; /* FORMAT_COMP_SIGNED */
672 vtx
.srf_mode_all
= 1; /* SRF_MODE_NO_ZERO */
673 vtx
.endian
= r600_endian_swap(32);
675 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
681 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
)
683 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
684 struct r600_bytecode_alu alu
;
685 int i
, j
, k
, nconst
, r
;
687 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
688 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
691 tgsi_src(ctx
, &inst
->Src
[i
], &ctx
->src
[i
]);
693 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
694 if (inst
->Src
[i
].Register
.File
!= TGSI_FILE_CONSTANT
) {
698 if (ctx
->src
[i
].rel
) {
699 int treg
= r600_get_temp(ctx
);
700 if ((r
= tgsi_fetch_rel_const(ctx
, ctx
->src
[i
].sel
- 512, treg
)))
703 ctx
->src
[i
].sel
= treg
;
707 int treg
= r600_get_temp(ctx
);
708 for (k
= 0; k
< 4; k
++) {
709 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
710 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
711 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
713 alu
.src
[0].rel
= ctx
->src
[i
].rel
;
719 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
723 ctx
->src
[i
].sel
= treg
;
731 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
732 static int tgsi_split_literal_constant(struct r600_shader_ctx
*ctx
)
734 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
735 struct r600_bytecode_alu alu
;
736 int i
, j
, k
, nliteral
, r
;
738 for (i
= 0, nliteral
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
739 if (ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
743 for (i
= 0, j
= nliteral
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
744 if (j
> 0 && ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
745 int treg
= r600_get_temp(ctx
);
746 for (k
= 0; k
< 4; k
++) {
747 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
748 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
749 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
751 alu
.src
[0].value
= ctx
->src
[i
].value
[k
];
757 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
761 ctx
->src
[i
].sel
= treg
;
768 static int process_twoside_color_inputs(struct r600_shader_ctx
*ctx
)
770 int i
, r
, count
= ctx
->shader
->ninput
;
772 /* additional inputs will be allocated right after the existing inputs,
773 * we won't need them after the color selection, so we don't need to
774 * reserve these gprs for the rest of the shader code and to adjust
775 * output offsets etc. */
776 int gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] +
777 ctx
->info
.file_max
[TGSI_FILE_INPUT
] + 1;
779 if (ctx
->face_gpr
== -1) {
780 i
= ctx
->shader
->ninput
++;
781 ctx
->shader
->input
[i
].name
= TGSI_SEMANTIC_FACE
;
782 ctx
->shader
->input
[i
].spi_sid
= 0;
783 ctx
->shader
->input
[i
].gpr
= gpr
++;
784 ctx
->face_gpr
= ctx
->shader
->input
[i
].gpr
;
787 for (i
= 0; i
< count
; i
++) {
788 if (ctx
->shader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
) {
789 int ni
= ctx
->shader
->ninput
++;
790 memcpy(&ctx
->shader
->input
[ni
],&ctx
->shader
->input
[i
], sizeof(struct r600_shader_io
));
791 ctx
->shader
->input
[ni
].name
= TGSI_SEMANTIC_BCOLOR
;
792 ctx
->shader
->input
[ni
].spi_sid
= r600_spi_sid(&ctx
->shader
->input
[ni
]);
793 ctx
->shader
->input
[ni
].gpr
= gpr
++;
795 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
796 r
= evergreen_interp_input(ctx
, ni
);
801 r
= select_twoside_color(ctx
, i
, ni
);
809 static int r600_shader_from_tgsi(struct r600_context
* rctx
, struct r600_pipe_shader
*pipeshader
)
811 struct r600_shader
*shader
= &pipeshader
->shader
;
812 struct tgsi_token
*tokens
= pipeshader
->tokens
;
813 struct pipe_stream_output_info so
= pipeshader
->so
;
814 struct tgsi_full_immediate
*immediate
;
815 struct tgsi_full_property
*property
;
816 struct r600_shader_ctx ctx
;
817 struct r600_bytecode_output output
[32];
818 unsigned output_done
, noutput
;
821 int next_pixel_base
= 0, next_pos_base
= 60, next_param_base
= 0;
823 ctx
.bc
= &shader
->bc
;
825 r600_bytecode_init(ctx
.bc
, rctx
->chip_class
, rctx
->family
);
827 tgsi_scan_shader(tokens
, &ctx
.info
);
828 tgsi_parse_init(&ctx
.parse
, tokens
);
829 ctx
.type
= ctx
.parse
.FullHeader
.Processor
.Processor
;
830 shader
->processor_type
= ctx
.type
;
831 ctx
.bc
->type
= shader
->processor_type
;
834 ctx
.fragcoord_input
= -1;
836 ctx
.clip_vertex_write
= 0;
838 shader
->two_side
= (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
) && rctx
->two_side
;
839 shader
->nr_cbufs
= rctx
->nr_cbufs
;
841 /* register allocations */
842 /* Values [0,127] correspond to GPR[0..127].
843 * Values [128,159] correspond to constant buffer bank 0
844 * Values [160,191] correspond to constant buffer bank 1
845 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
846 * Values [256,287] correspond to constant buffer bank 2 (EG)
847 * Values [288,319] correspond to constant buffer bank 3 (EG)
848 * Other special values are shown in the list below.
849 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
850 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
851 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
852 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
853 * 248 SQ_ALU_SRC_0: special constant 0.0.
854 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
855 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
856 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
857 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
858 * 253 SQ_ALU_SRC_LITERAL: literal constant.
859 * 254 SQ_ALU_SRC_PV: previous vector result.
860 * 255 SQ_ALU_SRC_PS: previous scalar result.
862 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
863 ctx
.file_offset
[i
] = 0;
865 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
866 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
867 if (ctx
.bc
->chip_class
>= EVERGREEN
) {
868 r600_bytecode_add_cfinst(ctx
.bc
, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
);
870 r600_bytecode_add_cfinst(ctx
.bc
, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
);
873 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& ctx
.bc
->chip_class
>= EVERGREEN
) {
874 ctx
.file_offset
[TGSI_FILE_INPUT
] = evergreen_gpr_count(&ctx
);
876 ctx
.file_offset
[TGSI_FILE_OUTPUT
] = ctx
.file_offset
[TGSI_FILE_INPUT
] +
877 ctx
.info
.file_max
[TGSI_FILE_INPUT
] + 1;
878 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
879 ctx
.info
.file_max
[TGSI_FILE_OUTPUT
] + 1;
881 /* Outside the GPR range. This will be translated to one of the
882 * kcache banks later. */
883 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 512;
885 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = V_SQ_ALU_SRC_LITERAL
;
886 ctx
.bc
->ar_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
887 ctx
.info
.file_max
[TGSI_FILE_TEMPORARY
] + 1;
888 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 1;
892 shader
->fs_write_all
= FALSE
;
893 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
894 tgsi_parse_token(&ctx
.parse
);
895 switch (ctx
.parse
.FullToken
.Token
.Type
) {
896 case TGSI_TOKEN_TYPE_IMMEDIATE
:
897 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
898 ctx
.literals
= realloc(ctx
.literals
, (ctx
.nliterals
+ 1) * 16);
899 if(ctx
.literals
== NULL
) {
903 ctx
.literals
[ctx
.nliterals
* 4 + 0] = immediate
->u
[0].Uint
;
904 ctx
.literals
[ctx
.nliterals
* 4 + 1] = immediate
->u
[1].Uint
;
905 ctx
.literals
[ctx
.nliterals
* 4 + 2] = immediate
->u
[2].Uint
;
906 ctx
.literals
[ctx
.nliterals
* 4 + 3] = immediate
->u
[3].Uint
;
909 case TGSI_TOKEN_TYPE_DECLARATION
:
910 r
= tgsi_declaration(&ctx
);
914 case TGSI_TOKEN_TYPE_INSTRUCTION
:
916 case TGSI_TOKEN_TYPE_PROPERTY
:
917 property
= &ctx
.parse
.FullToken
.FullProperty
;
918 switch (property
->Property
.PropertyName
) {
919 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
:
920 if (property
->u
[0].Data
== 1)
921 shader
->fs_write_all
= TRUE
;
923 case TGSI_PROPERTY_VS_PROHIBIT_UCPS
:
924 if (property
->u
[0].Data
== 1)
925 shader
->vs_prohibit_ucps
= TRUE
;
930 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
936 if (ctx
.fragcoord_input
>= 0) {
937 if (ctx
.bc
->chip_class
== CAYMAN
) {
938 for (j
= 0 ; j
< 4; j
++) {
939 struct r600_bytecode_alu alu
;
940 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
941 alu
.inst
= BC_INST(ctx
.bc
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
942 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
945 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
947 alu
.dst
.write
= (j
== 3);
949 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
953 struct r600_bytecode_alu alu
;
954 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
955 alu
.inst
= BC_INST(ctx
.bc
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
956 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
959 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
963 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
968 if (shader
->two_side
&& ctx
.colors_used
) {
969 if ((r
= process_twoside_color_inputs(&ctx
)))
973 tgsi_parse_init(&ctx
.parse
, tokens
);
974 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
975 tgsi_parse_token(&ctx
.parse
);
976 switch (ctx
.parse
.FullToken
.Token
.Type
) {
977 case TGSI_TOKEN_TYPE_INSTRUCTION
:
978 r
= tgsi_is_supported(&ctx
);
981 ctx
.max_driver_temp_used
= 0;
982 /* reserve first tmp for everyone */
985 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
986 if ((r
= tgsi_split_constant(&ctx
)))
988 if ((r
= tgsi_split_literal_constant(&ctx
)))
990 if (ctx
.bc
->chip_class
== CAYMAN
)
991 ctx
.inst_info
= &cm_shader_tgsi_instruction
[opcode
];
992 else if (ctx
.bc
->chip_class
>= EVERGREEN
)
993 ctx
.inst_info
= &eg_shader_tgsi_instruction
[opcode
];
995 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
996 r
= ctx
.inst_info
->process(&ctx
);
1005 noutput
= shader
->noutput
;
1007 if (ctx
.clip_vertex_write
) {
1008 /* need to convert a clipvertex write into clipdistance writes and not export
1009 the clip vertex anymore */
1011 memset(&shader
->output
[noutput
], 0, 2*sizeof(struct r600_shader_io
));
1012 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
1013 shader
->output
[noutput
].gpr
= ctx
.temp_reg
;
1015 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
1016 shader
->output
[noutput
].gpr
= ctx
.temp_reg
+1;
1019 /* reset spi_sid for clipvertex output to avoid confusing spi */
1020 shader
->output
[ctx
.cv_output
].spi_sid
= 0;
1022 shader
->clip_dist_write
= 0xFF;
1024 for (i
= 0; i
< 8; i
++) {
1028 for (j
= 0; j
< 4; j
++) {
1029 struct r600_bytecode_alu alu
;
1030 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1031 alu
.inst
= BC_INST(ctx
.bc
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
);
1032 alu
.src
[0].sel
= shader
->output
[ctx
.cv_output
].gpr
;
1033 alu
.src
[0].chan
= j
;
1035 alu
.src
[1].sel
= 512 + i
;
1036 alu
.src
[1].kc_bank
= 1;
1037 alu
.src
[1].chan
= j
;
1039 alu
.dst
.sel
= ctx
.temp_reg
+ oreg
;
1041 alu
.dst
.write
= (j
== ochan
);
1044 r
= r600_bytecode_add_alu(ctx
.bc
, &alu
);
1051 /* Add stream outputs. */
1052 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
&& so
.num_outputs
) {
1053 for (i
= 0; i
< so
.num_outputs
; i
++) {
1054 struct r600_bytecode_output output
;
1056 if (so
.output
[i
].output_buffer
>= 4) {
1057 R600_ERR("exceeded the max number of stream output buffers, got: %d\n",
1058 so
.output
[i
].output_buffer
);
1062 if (so
.output
[i
].dst_offset
< so
.output
[i
].start_component
) {
1063 R600_ERR("stream_output - dst_offset cannot be less than start_component\n");
1068 memset(&output
, 0, sizeof(struct r600_bytecode_output
));
1069 output
.gpr
= shader
->output
[so
.output
[i
].register_index
].gpr
;
1070 output
.elem_size
= 0;
1071 output
.array_base
= so
.output
[i
].dst_offset
- so
.output
[i
].start_component
;
1072 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE
;
1073 output
.burst_count
= 1;
1075 /* array_size is an upper limit for the burst_count
1076 * with MEM_STREAM instructions */
1077 output
.array_size
= 0xFFF;
1078 output
.comp_mask
= ((1 << so
.output
[i
].num_components
) - 1) << so
.output
[i
].start_component
;
1079 if (ctx
.bc
->chip_class
>= EVERGREEN
) {
1080 switch (so
.output
[i
].output_buffer
) {
1082 output
.inst
= EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
;
1085 output
.inst
= EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1
;
1088 output
.inst
= EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2
;
1091 output
.inst
= EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3
;
1095 switch (so
.output
[i
].output_buffer
) {
1097 output
.inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
;
1100 output
.inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1
;
1103 output
.inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2
;
1106 output
.inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3
;
1110 r
= r600_bytecode_add_output(ctx
.bc
, &output
);
1117 for (i
= 0, j
= 0; i
< noutput
; i
++, j
++) {
1118 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
1119 output
[j
].gpr
= shader
->output
[i
].gpr
;
1120 output
[j
].elem_size
= 3;
1121 output
[j
].swizzle_x
= 0;
1122 output
[j
].swizzle_y
= 1;
1123 output
[j
].swizzle_z
= 2;
1124 output
[j
].swizzle_w
= 3;
1125 output
[j
].burst_count
= 1;
1126 output
[j
].barrier
= 1;
1127 output
[j
].type
= -1;
1128 output
[j
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
1130 case TGSI_PROCESSOR_VERTEX
:
1131 switch (shader
->output
[i
].name
) {
1132 case TGSI_SEMANTIC_POSITION
:
1133 output
[j
].array_base
= next_pos_base
++;
1134 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
1137 case TGSI_SEMANTIC_PSIZE
:
1138 output
[j
].array_base
= next_pos_base
++;
1139 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
1141 case TGSI_SEMANTIC_CLIPVERTEX
:
1144 case TGSI_SEMANTIC_CLIPDIST
:
1145 output
[j
].array_base
= next_pos_base
++;
1146 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
1147 /* spi_sid is 0 for clipdistance outputs that were generated
1148 * for clipvertex - we don't need to pass them to PS */
1149 if (shader
->output
[i
].spi_sid
) {
1151 /* duplicate it as PARAM to pass to the pixel shader */
1152 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
1153 output
[j
].array_base
= next_param_base
++;
1154 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
1157 case TGSI_SEMANTIC_FOG
:
1158 output
[j
].swizzle_y
= 4; /* 0 */
1159 output
[j
].swizzle_z
= 4; /* 0 */
1160 output
[j
].swizzle_w
= 5; /* 1 */
1164 case TGSI_PROCESSOR_FRAGMENT
:
1165 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
1166 output
[j
].array_base
= next_pixel_base
++;
1167 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
1168 if (shader
->fs_write_all
&& (rctx
->chip_class
>= EVERGREEN
)) {
1169 for (k
= 1; k
< shader
->nr_cbufs
; k
++) {
1171 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
1172 output
[j
].gpr
= shader
->output
[i
].gpr
;
1173 output
[j
].elem_size
= 3;
1174 output
[j
].swizzle_x
= 0;
1175 output
[j
].swizzle_y
= 1;
1176 output
[j
].swizzle_z
= 2;
1177 output
[j
].swizzle_w
= 3;
1178 output
[j
].burst_count
= 1;
1179 output
[j
].barrier
= 1;
1180 output
[j
].array_base
= next_pixel_base
++;
1181 output
[j
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
1182 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
1185 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
1186 output
[j
].array_base
= 61;
1187 output
[j
].swizzle_x
= 2;
1188 output
[j
].swizzle_y
= 7;
1189 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
1190 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
1191 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
1192 output
[j
].array_base
= 61;
1193 output
[j
].swizzle_x
= 7;
1194 output
[j
].swizzle_y
= 1;
1195 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
1196 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
1198 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
1204 R600_ERR("unsupported processor type %d\n", ctx
.type
);
1209 if (output
[j
].type
==-1) {
1210 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
1211 output
[j
].array_base
= next_param_base
++;
1215 /* add fake param output for vertex shader if no param is exported */
1216 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
&& next_param_base
== 0) {
1217 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
1219 output
[j
].elem_size
= 3;
1220 output
[j
].swizzle_x
= 7;
1221 output
[j
].swizzle_y
= 7;
1222 output
[j
].swizzle_z
= 7;
1223 output
[j
].swizzle_w
= 7;
1224 output
[j
].burst_count
= 1;
1225 output
[j
].barrier
= 1;
1226 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
1227 output
[j
].array_base
= 0;
1228 output
[j
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
1232 /* add fake pixel export */
1233 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& j
== 0) {
1234 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
1236 output
[j
].elem_size
= 3;
1237 output
[j
].swizzle_x
= 7;
1238 output
[j
].swizzle_y
= 7;
1239 output
[j
].swizzle_z
= 7;
1240 output
[j
].swizzle_w
= 7;
1241 output
[j
].burst_count
= 1;
1242 output
[j
].barrier
= 1;
1243 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
1244 output
[j
].array_base
= 0;
1245 output
[j
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
1251 /* set export done on last export of each type */
1252 for (i
= noutput
- 1, output_done
= 0; i
>= 0; i
--) {
1253 if (ctx
.bc
->chip_class
< CAYMAN
) {
1254 if (i
== (noutput
- 1)) {
1255 output
[i
].end_of_program
= 1;
1258 if (!(output_done
& (1 << output
[i
].type
))) {
1259 output_done
|= (1 << output
[i
].type
);
1260 output
[i
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
);
1263 /* add output to bytecode */
1264 for (i
= 0; i
< noutput
; i
++) {
1265 r
= r600_bytecode_add_output(ctx
.bc
, &output
[i
]);
1269 /* add program end */
1270 if (ctx
.bc
->chip_class
== CAYMAN
)
1271 cm_bytecode_add_cf_end(ctx
.bc
);
1274 tgsi_parse_free(&ctx
.parse
);
1278 tgsi_parse_free(&ctx
.parse
);
1282 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
1284 R600_ERR("%s tgsi opcode unsupported\n",
1285 tgsi_get_opcode_name(ctx
->inst_info
->tgsi_opcode
));
1289 static int tgsi_end(struct r600_shader_ctx
*ctx
)
1294 static void r600_bytecode_src(struct r600_bytecode_alu_src
*bc_src
,
1295 const struct r600_shader_src
*shader_src
,
1298 bc_src
->sel
= shader_src
->sel
;
1299 bc_src
->chan
= shader_src
->swizzle
[chan
];
1300 bc_src
->neg
= shader_src
->neg
;
1301 bc_src
->abs
= shader_src
->abs
;
1302 bc_src
->rel
= shader_src
->rel
;
1303 bc_src
->value
= shader_src
->value
[bc_src
->chan
];
1306 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src
*bc_src
)
1312 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src
*bc_src
)
1314 bc_src
->neg
= !bc_src
->neg
;
1317 static void tgsi_dst(struct r600_shader_ctx
*ctx
,
1318 const struct tgsi_full_dst_register
*tgsi_dst
,
1320 struct r600_bytecode_alu_dst
*r600_dst
)
1322 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1324 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
1325 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
1326 r600_dst
->chan
= swizzle
;
1327 r600_dst
->write
= 1;
1328 if (tgsi_dst
->Register
.Indirect
)
1329 r600_dst
->rel
= V_SQ_REL_RELATIVE
;
1330 if (inst
->Instruction
.Saturate
) {
1331 r600_dst
->clamp
= 1;
1335 static int tgsi_last_instruction(unsigned writemask
)
1339 for (i
= 0; i
< 4; i
++) {
1340 if (writemask
& (1 << i
)) {
1347 static int tgsi_op2_s(struct r600_shader_ctx
*ctx
, int swap
, int trans_only
)
1349 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1350 struct r600_bytecode_alu alu
;
1352 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1354 for (i
= 0; i
< lasti
+ 1; i
++) {
1355 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1358 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1359 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1361 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1363 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1364 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
1367 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
1368 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
1370 /* handle some special cases */
1371 switch (ctx
->inst_info
->tgsi_opcode
) {
1372 case TGSI_OPCODE_SUB
:
1373 r600_bytecode_src_toggle_neg(&alu
.src
[1]);
1375 case TGSI_OPCODE_ABS
:
1376 r600_bytecode_src_set_abs(&alu
.src
[0]);
1381 if (i
== lasti
|| trans_only
) {
1384 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1391 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
1393 return tgsi_op2_s(ctx
, 0, 0);
1396 static int tgsi_op2_swap(struct r600_shader_ctx
*ctx
)
1398 return tgsi_op2_s(ctx
, 1, 0);
1401 static int tgsi_op2_trans(struct r600_shader_ctx
*ctx
)
1403 return tgsi_op2_s(ctx
, 0, 1);
1406 static int tgsi_ineg(struct r600_shader_ctx
*ctx
)
1408 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1409 struct r600_bytecode_alu alu
;
1411 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1413 for (i
= 0; i
< lasti
+ 1; i
++) {
1415 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1417 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1418 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1420 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1422 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
1424 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1429 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1437 static int cayman_emit_float_instr(struct r600_shader_ctx
*ctx
)
1439 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1441 struct r600_bytecode_alu alu
;
1442 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
1444 for (i
= 0 ; i
< last_slot
; i
++) {
1445 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1446 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1447 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1448 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], 0);
1450 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1451 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1453 if (i
== last_slot
- 1)
1455 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1462 static int cayman_mul_int_instr(struct r600_shader_ctx
*ctx
)
1464 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1466 struct r600_bytecode_alu alu
;
1467 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
1468 for (k
= 0; k
< last_slot
; k
++) {
1469 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << k
)))
1472 for (i
= 0 ; i
< 4; i
++) {
1473 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1474 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1475 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1476 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], k
);
1478 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1479 alu
.dst
.write
= (i
== k
);
1482 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1491 * r600 - trunc to -PI..PI range
1492 * r700 - normalize by dividing by 2PI
1495 static int tgsi_setup_trig(struct r600_shader_ctx
*ctx
)
1497 static float half_inv_pi
= 1.0 /(3.1415926535 * 2);
1498 static float double_pi
= 3.1415926535 * 2;
1499 static float neg_pi
= -3.1415926535;
1502 struct r600_bytecode_alu alu
;
1504 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1505 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1509 alu
.dst
.sel
= ctx
->temp_reg
;
1512 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
1514 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1515 alu
.src
[1].chan
= 0;
1516 alu
.src
[1].value
= *(uint32_t *)&half_inv_pi
;
1517 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
1518 alu
.src
[2].chan
= 0;
1520 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1524 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1525 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
);
1528 alu
.dst
.sel
= ctx
->temp_reg
;
1531 alu
.src
[0].sel
= ctx
->temp_reg
;
1532 alu
.src
[0].chan
= 0;
1534 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1538 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1539 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1543 alu
.dst
.sel
= ctx
->temp_reg
;
1546 alu
.src
[0].sel
= ctx
->temp_reg
;
1547 alu
.src
[0].chan
= 0;
1549 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1550 alu
.src
[1].chan
= 0;
1551 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1552 alu
.src
[2].chan
= 0;
1554 if (ctx
->bc
->chip_class
== R600
) {
1555 alu
.src
[1].value
= *(uint32_t *)&double_pi
;
1556 alu
.src
[2].value
= *(uint32_t *)&neg_pi
;
1558 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1559 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
1564 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1570 static int cayman_trig(struct r600_shader_ctx
*ctx
)
1572 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1573 struct r600_bytecode_alu alu
;
1574 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
1577 r
= tgsi_setup_trig(ctx
);
1582 for (i
= 0; i
< last_slot
; i
++) {
1583 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1584 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1587 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1588 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1590 alu
.src
[0].sel
= ctx
->temp_reg
;
1591 alu
.src
[0].chan
= 0;
1592 if (i
== last_slot
- 1)
1594 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1601 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
1603 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1604 struct r600_bytecode_alu alu
;
1606 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1608 r
= tgsi_setup_trig(ctx
);
1612 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1613 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1615 alu
.dst
.sel
= ctx
->temp_reg
;
1618 alu
.src
[0].sel
= ctx
->temp_reg
;
1619 alu
.src
[0].chan
= 0;
1621 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1625 /* replicate result */
1626 for (i
= 0; i
< lasti
+ 1; i
++) {
1627 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1630 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1631 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1633 alu
.src
[0].sel
= ctx
->temp_reg
;
1634 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1637 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1644 static int tgsi_scs(struct r600_shader_ctx
*ctx
)
1646 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1647 struct r600_bytecode_alu alu
;
1650 /* We'll only need the trig stuff if we are going to write to the
1651 * X or Y components of the destination vector.
1653 if (likely(inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
)) {
1654 r
= tgsi_setup_trig(ctx
);
1660 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
1661 if (ctx
->bc
->chip_class
== CAYMAN
) {
1662 for (i
= 0 ; i
< 3; i
++) {
1663 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1664 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
);
1665 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1671 alu
.src
[0].sel
= ctx
->temp_reg
;
1672 alu
.src
[0].chan
= 0;
1675 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1680 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1681 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
);
1682 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
1684 alu
.src
[0].sel
= ctx
->temp_reg
;
1685 alu
.src
[0].chan
= 0;
1687 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1694 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
1695 if (ctx
->bc
->chip_class
== CAYMAN
) {
1696 for (i
= 0 ; i
< 3; i
++) {
1697 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1698 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
);
1699 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1704 alu
.src
[0].sel
= ctx
->temp_reg
;
1705 alu
.src
[0].chan
= 0;
1708 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1713 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1714 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
);
1715 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
1717 alu
.src
[0].sel
= ctx
->temp_reg
;
1718 alu
.src
[0].chan
= 0;
1720 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1727 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
1728 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1730 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1732 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1734 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1735 alu
.src
[0].chan
= 0;
1739 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1745 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
1746 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1748 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1750 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
1752 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1753 alu
.src
[0].chan
= 0;
1757 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1765 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
1767 struct r600_bytecode_alu alu
;
1770 for (i
= 0; i
< 4; i
++) {
1771 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1772 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1776 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1778 if (ctx
->inst_info
->tgsi_opcode
== TGSI_OPCODE_KILP
) {
1779 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1782 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
1787 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1792 /* kill must be last in ALU */
1793 ctx
->bc
->force_add_cf
= 1;
1794 ctx
->shader
->uses_kill
= TRUE
;
1798 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
1800 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1801 struct r600_bytecode_alu alu
;
1804 /* tmp.x = max(src.y, 0.0) */
1805 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1806 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
);
1807 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 1);
1808 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
1809 alu
.src
[1].chan
= 1;
1811 alu
.dst
.sel
= ctx
->temp_reg
;
1816 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1820 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
1826 if (ctx
->bc
->chip_class
== CAYMAN
) {
1827 for (i
= 0; i
< 3; i
++) {
1828 /* tmp.z = log(tmp.x) */
1829 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1830 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
);
1831 alu
.src
[0].sel
= ctx
->temp_reg
;
1832 alu
.src
[0].chan
= 0;
1833 alu
.dst
.sel
= ctx
->temp_reg
;
1841 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1846 /* tmp.z = log(tmp.x) */
1847 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1848 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
);
1849 alu
.src
[0].sel
= ctx
->temp_reg
;
1850 alu
.src
[0].chan
= 0;
1851 alu
.dst
.sel
= ctx
->temp_reg
;
1855 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1860 chan
= alu
.dst
.chan
;
1863 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
1864 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1865 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
);
1866 alu
.src
[0].sel
= sel
;
1867 alu
.src
[0].chan
= chan
;
1868 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], 3);
1869 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], 0);
1870 alu
.dst
.sel
= ctx
->temp_reg
;
1875 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1879 if (ctx
->bc
->chip_class
== CAYMAN
) {
1880 for (i
= 0; i
< 3; i
++) {
1881 /* dst.z = exp(tmp.x) */
1882 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1883 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
1884 alu
.src
[0].sel
= ctx
->temp_reg
;
1885 alu
.src
[0].chan
= 0;
1886 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1892 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1897 /* dst.z = exp(tmp.x) */
1898 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1899 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
1900 alu
.src
[0].sel
= ctx
->temp_reg
;
1901 alu
.src
[0].chan
= 0;
1902 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1904 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1911 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1912 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1913 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
; /*1.0*/
1914 alu
.src
[0].chan
= 0;
1915 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
1916 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
1917 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1921 /* dst.y = max(src.x, 0.0) */
1922 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1923 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
);
1924 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
1925 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
1926 alu
.src
[1].chan
= 0;
1927 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
1928 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
1929 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1934 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1935 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1936 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1937 alu
.src
[0].chan
= 0;
1938 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
1939 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
1941 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1948 static int tgsi_rsq(struct r600_shader_ctx
*ctx
)
1950 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1951 struct r600_bytecode_alu alu
;
1954 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1957 * For state trackers other than OpenGL, we'll want to use
1958 * _RECIPSQRT_IEEE instead.
1960 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED
);
1962 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1963 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
1964 r600_bytecode_src_set_abs(&alu
.src
[i
]);
1966 alu
.dst
.sel
= ctx
->temp_reg
;
1969 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1972 /* replicate result */
1973 return tgsi_helper_tempx_replicate(ctx
);
1976 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
)
1978 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1979 struct r600_bytecode_alu alu
;
1982 for (i
= 0; i
< 4; i
++) {
1983 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1984 alu
.src
[0].sel
= ctx
->temp_reg
;
1985 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1987 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1988 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1991 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1998 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
2000 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2001 struct r600_bytecode_alu alu
;
2004 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2005 alu
.inst
= ctx
->inst_info
->r600_opcode
;
2006 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
2007 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
2009 alu
.dst
.sel
= ctx
->temp_reg
;
2012 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2015 /* replicate result */
2016 return tgsi_helper_tempx_replicate(ctx
);
2019 static int cayman_pow(struct r600_shader_ctx
*ctx
)
2021 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2023 struct r600_bytecode_alu alu
;
2024 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
2026 for (i
= 0; i
< 3; i
++) {
2027 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2028 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2029 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
2030 alu
.dst
.sel
= ctx
->temp_reg
;
2035 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2041 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2042 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2043 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
2044 alu
.src
[1].sel
= ctx
->temp_reg
;
2045 alu
.dst
.sel
= ctx
->temp_reg
;
2048 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2052 for (i
= 0; i
< last_slot
; i
++) {
2053 /* POW(a,b) = EXP2(b * LOG2(a))*/
2054 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2055 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2056 alu
.src
[0].sel
= ctx
->temp_reg
;
2058 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2059 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
2060 if (i
== last_slot
- 1)
2062 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2069 static int tgsi_pow(struct r600_shader_ctx
*ctx
)
2071 struct r600_bytecode_alu alu
;
2075 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2076 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2077 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
2078 alu
.dst
.sel
= ctx
->temp_reg
;
2081 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2085 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2086 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2087 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
2088 alu
.src
[1].sel
= ctx
->temp_reg
;
2089 alu
.dst
.sel
= ctx
->temp_reg
;
2092 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2095 /* POW(a,b) = EXP2(b * LOG2(a))*/
2096 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2097 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2098 alu
.src
[0].sel
= ctx
->temp_reg
;
2099 alu
.dst
.sel
= ctx
->temp_reg
;
2102 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2105 return tgsi_helper_tempx_replicate(ctx
);
2108 static int tgsi_divmod(struct r600_shader_ctx
*ctx
, int mod
, int signed_op
)
2110 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2111 struct r600_bytecode_alu alu
;
2113 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
2114 int tmp0
= ctx
->temp_reg
;
2115 int tmp1
= r600_get_temp(ctx
);
2116 int tmp2
= r600_get_temp(ctx
);
2117 int tmp3
= r600_get_temp(ctx
);
2120 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
2122 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
2123 * 2. tmp0.z = lo (tmp0.x * src2)
2124 * 3. tmp0.w = -tmp0.z
2125 * 4. tmp0.y = hi (tmp0.x * src2)
2126 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
2127 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
2128 * 7. tmp1.x = tmp0.x - tmp0.w
2129 * 8. tmp1.y = tmp0.x + tmp0.w
2130 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
2131 * 10. tmp0.z = hi(tmp0.x * src1) = q
2132 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
2134 * 12. tmp0.w = src1 - tmp0.y = r
2135 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
2136 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
2140 * 15. tmp1.z = tmp0.z + 1 = q + 1
2141 * 16. tmp1.w = tmp0.z - 1 = q - 1
2145 * 15. tmp1.z = tmp0.w - src2 = r - src2
2146 * 16. tmp1.w = tmp0.w + src2 = r + src2
2150 * 17. tmp1.x = tmp1.x & tmp1.y
2152 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
2153 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
2155 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
2156 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
2160 * Same as unsigned, using abs values of the operands,
2161 * and fixing the sign of the result in the end.
2164 for (i
= 0; i
< 4; i
++) {
2165 if (!(write_mask
& (1<<i
)))
2170 /* tmp2.x = -src0 */
2171 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2172 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
2178 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2180 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
2183 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2186 /* tmp2.y = -src1 */
2187 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2188 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
2194 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2196 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2199 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2202 /* tmp2.z sign bit is set if src0 and src2 signs are different */
2203 /* it will be a sign of the quotient */
2206 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2207 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT
);
2213 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
2214 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2217 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2221 /* tmp2.x = |src0| */
2222 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2223 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT
);
2230 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
2231 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
2232 alu
.src
[2].sel
= tmp2
;
2233 alu
.src
[2].chan
= 0;
2236 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2239 /* tmp2.y = |src1| */
2240 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2241 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT
);
2248 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
2249 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2250 alu
.src
[2].sel
= tmp2
;
2251 alu
.src
[2].chan
= 1;
2254 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2259 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
2260 if (ctx
->bc
->chip_class
== CAYMAN
) {
2261 /* tmp3.x = u2f(src2) */
2262 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2263 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
);
2270 alu
.src
[0].sel
= tmp2
;
2271 alu
.src
[0].chan
= 1;
2273 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
2277 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2280 /* tmp0.x = recip(tmp3.x) */
2281 for (j
= 0 ; j
< 3; j
++) {
2282 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2283 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
;
2287 alu
.dst
.write
= (j
== 0);
2289 alu
.src
[0].sel
= tmp3
;
2290 alu
.src
[0].chan
= 0;
2294 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2298 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2299 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2301 alu
.src
[0].sel
= tmp0
;
2302 alu
.src
[0].chan
= 0;
2304 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2305 alu
.src
[1].value
= 0x4f800000;
2310 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2314 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2315 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
);
2321 alu
.src
[0].sel
= tmp3
;
2322 alu
.src
[0].chan
= 0;
2325 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2329 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2330 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT
);
2337 alu
.src
[0].sel
= tmp2
;
2338 alu
.src
[0].chan
= 1;
2340 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
2344 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2348 /* 2. tmp0.z = lo (tmp0.x * src2) */
2349 if (ctx
->bc
->chip_class
== CAYMAN
) {
2350 for (j
= 0 ; j
< 4; j
++) {
2351 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2352 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
);
2356 alu
.dst
.write
= (j
== 2);
2358 alu
.src
[0].sel
= tmp0
;
2359 alu
.src
[0].chan
= 0;
2361 alu
.src
[1].sel
= tmp2
;
2362 alu
.src
[1].chan
= 1;
2364 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2367 alu
.last
= (j
== 3);
2368 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2372 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2373 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
);
2379 alu
.src
[0].sel
= tmp0
;
2380 alu
.src
[0].chan
= 0;
2382 alu
.src
[1].sel
= tmp2
;
2383 alu
.src
[1].chan
= 1;
2385 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2389 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2393 /* 3. tmp0.w = -tmp0.z */
2394 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2395 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
2401 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2402 alu
.src
[1].sel
= tmp0
;
2403 alu
.src
[1].chan
= 2;
2406 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2409 /* 4. tmp0.y = hi (tmp0.x * src2) */
2410 if (ctx
->bc
->chip_class
== CAYMAN
) {
2411 for (j
= 0 ; j
< 4; j
++) {
2412 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2413 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2417 alu
.dst
.write
= (j
== 1);
2419 alu
.src
[0].sel
= tmp0
;
2420 alu
.src
[0].chan
= 0;
2423 alu
.src
[1].sel
= tmp2
;
2424 alu
.src
[1].chan
= 1;
2426 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2428 alu
.last
= (j
== 3);
2429 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2433 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2434 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2440 alu
.src
[0].sel
= tmp0
;
2441 alu
.src
[0].chan
= 0;
2444 alu
.src
[1].sel
= tmp2
;
2445 alu
.src
[1].chan
= 1;
2447 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2451 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2455 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
2456 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2457 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT
);
2464 alu
.src
[0].sel
= tmp0
;
2465 alu
.src
[0].chan
= 1;
2466 alu
.src
[1].sel
= tmp0
;
2467 alu
.src
[1].chan
= 3;
2468 alu
.src
[2].sel
= tmp0
;
2469 alu
.src
[2].chan
= 2;
2472 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2475 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
2476 if (ctx
->bc
->chip_class
== CAYMAN
) {
2477 for (j
= 0 ; j
< 4; j
++) {
2478 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2479 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2483 alu
.dst
.write
= (j
== 3);
2485 alu
.src
[0].sel
= tmp0
;
2486 alu
.src
[0].chan
= 2;
2488 alu
.src
[1].sel
= tmp0
;
2489 alu
.src
[1].chan
= 0;
2491 alu
.last
= (j
== 3);
2492 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2496 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2497 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2503 alu
.src
[0].sel
= tmp0
;
2504 alu
.src
[0].chan
= 2;
2506 alu
.src
[1].sel
= tmp0
;
2507 alu
.src
[1].chan
= 0;
2510 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2514 /* 7. tmp1.x = tmp0.x - tmp0.w */
2515 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2516 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
2522 alu
.src
[0].sel
= tmp0
;
2523 alu
.src
[0].chan
= 0;
2524 alu
.src
[1].sel
= tmp0
;
2525 alu
.src
[1].chan
= 3;
2528 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2531 /* 8. tmp1.y = tmp0.x + tmp0.w */
2532 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2533 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
2539 alu
.src
[0].sel
= tmp0
;
2540 alu
.src
[0].chan
= 0;
2541 alu
.src
[1].sel
= tmp0
;
2542 alu
.src
[1].chan
= 3;
2545 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2548 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
2549 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2550 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT
);
2557 alu
.src
[0].sel
= tmp0
;
2558 alu
.src
[0].chan
= 1;
2559 alu
.src
[1].sel
= tmp1
;
2560 alu
.src
[1].chan
= 1;
2561 alu
.src
[2].sel
= tmp1
;
2562 alu
.src
[2].chan
= 0;
2565 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2568 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
2569 if (ctx
->bc
->chip_class
== CAYMAN
) {
2570 for (j
= 0 ; j
< 4; j
++) {
2571 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2572 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2576 alu
.dst
.write
= (j
== 2);
2578 alu
.src
[0].sel
= tmp0
;
2579 alu
.src
[0].chan
= 0;
2582 alu
.src
[1].sel
= tmp2
;
2583 alu
.src
[1].chan
= 0;
2585 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
2588 alu
.last
= (j
== 3);
2589 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2593 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2594 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2600 alu
.src
[0].sel
= tmp0
;
2601 alu
.src
[0].chan
= 0;
2604 alu
.src
[1].sel
= tmp2
;
2605 alu
.src
[1].chan
= 0;
2607 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
2611 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2615 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
2616 if (ctx
->bc
->chip_class
== CAYMAN
) {
2617 for (j
= 0 ; j
< 4; j
++) {
2618 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2619 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
);
2623 alu
.dst
.write
= (j
== 1);
2626 alu
.src
[0].sel
= tmp2
;
2627 alu
.src
[0].chan
= 1;
2629 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
2632 alu
.src
[1].sel
= tmp0
;
2633 alu
.src
[1].chan
= 2;
2635 alu
.last
= (j
== 3);
2636 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2640 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2641 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
);
2648 alu
.src
[0].sel
= tmp2
;
2649 alu
.src
[0].chan
= 1;
2651 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
2654 alu
.src
[1].sel
= tmp0
;
2655 alu
.src
[1].chan
= 2;
2658 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2662 /* 12. tmp0.w = src1 - tmp0.y = r */
2663 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2664 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
2671 alu
.src
[0].sel
= tmp2
;
2672 alu
.src
[0].chan
= 0;
2674 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
2677 alu
.src
[1].sel
= tmp0
;
2678 alu
.src
[1].chan
= 1;
2681 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2684 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
2685 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2686 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
);
2692 alu
.src
[0].sel
= tmp0
;
2693 alu
.src
[0].chan
= 3;
2695 alu
.src
[1].sel
= tmp2
;
2696 alu
.src
[1].chan
= 1;
2698 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2702 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2705 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
2706 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2707 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
);
2714 alu
.src
[0].sel
= tmp2
;
2715 alu
.src
[0].chan
= 0;
2717 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
2720 alu
.src
[1].sel
= tmp0
;
2721 alu
.src
[1].chan
= 1;
2724 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2727 if (mod
) { /* UMOD */
2729 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
2730 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2731 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
2737 alu
.src
[0].sel
= tmp0
;
2738 alu
.src
[0].chan
= 3;
2741 alu
.src
[1].sel
= tmp2
;
2742 alu
.src
[1].chan
= 1;
2744 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2748 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2751 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
2752 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2753 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
2759 alu
.src
[0].sel
= tmp0
;
2760 alu
.src
[0].chan
= 3;
2762 alu
.src
[1].sel
= tmp2
;
2763 alu
.src
[1].chan
= 1;
2765 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2769 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2774 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
2775 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2776 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
2782 alu
.src
[0].sel
= tmp0
;
2783 alu
.src
[0].chan
= 2;
2784 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
2787 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2790 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
2791 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2792 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
2798 alu
.src
[0].sel
= tmp0
;
2799 alu
.src
[0].chan
= 2;
2800 alu
.src
[1].sel
= V_SQ_ALU_SRC_M_1_INT
;
2803 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2808 /* 17. tmp1.x = tmp1.x & tmp1.y */
2809 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2810 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT
);
2816 alu
.src
[0].sel
= tmp1
;
2817 alu
.src
[0].chan
= 0;
2818 alu
.src
[1].sel
= tmp1
;
2819 alu
.src
[1].chan
= 1;
2822 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2825 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
2826 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
2827 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2828 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT
);
2835 alu
.src
[0].sel
= tmp1
;
2836 alu
.src
[0].chan
= 0;
2837 alu
.src
[1].sel
= tmp0
;
2838 alu
.src
[1].chan
= mod
? 3 : 2;
2839 alu
.src
[2].sel
= tmp1
;
2840 alu
.src
[2].chan
= 2;
2843 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2846 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
2847 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2848 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT
);
2856 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2859 alu
.src
[0].sel
= tmp1
;
2860 alu
.src
[0].chan
= 1;
2861 alu
.src
[1].sel
= tmp1
;
2862 alu
.src
[1].chan
= 3;
2863 alu
.src
[2].sel
= tmp0
;
2864 alu
.src
[2].chan
= 2;
2867 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2872 /* fix the sign of the result */
2876 /* tmp0.x = -tmp0.z */
2877 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2878 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
2884 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2885 alu
.src
[1].sel
= tmp0
;
2886 alu
.src
[1].chan
= 2;
2889 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2892 /* sign of the remainder is the same as the sign of src0 */
2893 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
2894 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2895 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT
);
2898 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2900 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
2901 alu
.src
[1].sel
= tmp0
;
2902 alu
.src
[1].chan
= 2;
2903 alu
.src
[2].sel
= tmp0
;
2904 alu
.src
[2].chan
= 0;
2907 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2912 /* tmp0.x = -tmp0.z */
2913 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2914 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
2920 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2921 alu
.src
[1].sel
= tmp0
;
2922 alu
.src
[1].chan
= 2;
2925 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2928 /* fix the quotient sign (same as the sign of src0*src1) */
2929 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
2930 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2931 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT
);
2934 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2936 alu
.src
[0].sel
= tmp2
;
2937 alu
.src
[0].chan
= 2;
2938 alu
.src
[1].sel
= tmp0
;
2939 alu
.src
[1].chan
= 2;
2940 alu
.src
[2].sel
= tmp0
;
2941 alu
.src
[2].chan
= 0;
2944 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2952 static int tgsi_udiv(struct r600_shader_ctx
*ctx
)
2954 return tgsi_divmod(ctx
, 0, 0);
2957 static int tgsi_umod(struct r600_shader_ctx
*ctx
)
2959 return tgsi_divmod(ctx
, 1, 0);
2962 static int tgsi_idiv(struct r600_shader_ctx
*ctx
)
2964 return tgsi_divmod(ctx
, 0, 1);
2967 static int tgsi_imod(struct r600_shader_ctx
*ctx
)
2969 return tgsi_divmod(ctx
, 1, 1);
2972 static int tgsi_iabs(struct r600_shader_ctx
*ctx
)
2974 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2975 struct r600_bytecode_alu alu
;
2977 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
2978 int last_inst
= tgsi_last_instruction(write_mask
);
2981 for (i
= 0; i
< 4; i
++) {
2982 if (!(write_mask
& (1<<i
)))
2985 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2986 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
2988 alu
.dst
.sel
= ctx
->temp_reg
;
2992 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
2993 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2997 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3002 /* dst = (src >= 0 ? src : tmp) */
3003 for (i
= 0; i
< 4; i
++) {
3004 if (!(write_mask
& (1<<i
)))
3007 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3008 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT
);
3012 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3014 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3015 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3016 alu
.src
[2].sel
= ctx
->temp_reg
;
3017 alu
.src
[2].chan
= i
;
3021 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3028 static int tgsi_issg(struct r600_shader_ctx
*ctx
)
3030 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3031 struct r600_bytecode_alu alu
;
3033 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3034 int last_inst
= tgsi_last_instruction(write_mask
);
3036 /* tmp = (src >= 0 ? src : -1) */
3037 for (i
= 0; i
< 4; i
++) {
3038 if (!(write_mask
& (1<<i
)))
3041 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3042 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT
);
3045 alu
.dst
.sel
= ctx
->temp_reg
;
3049 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3050 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3051 alu
.src
[2].sel
= V_SQ_ALU_SRC_M_1_INT
;
3055 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3060 /* dst = (tmp > 0 ? 1 : tmp) */
3061 for (i
= 0; i
< 4; i
++) {
3062 if (!(write_mask
& (1<<i
)))
3065 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3066 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT_INT
);
3070 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3072 alu
.src
[0].sel
= ctx
->temp_reg
;
3073 alu
.src
[0].chan
= i
;
3075 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
3077 alu
.src
[2].sel
= ctx
->temp_reg
;
3078 alu
.src
[2].chan
= i
;
3082 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3091 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
3093 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3094 struct r600_bytecode_alu alu
;
3097 /* tmp = (src > 0 ? 1 : src) */
3098 for (i
= 0; i
< 4; i
++) {
3099 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3100 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
3103 alu
.dst
.sel
= ctx
->temp_reg
;
3106 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3107 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
3108 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
3112 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3117 /* dst = (-tmp > 0 ? -1 : tmp) */
3118 for (i
= 0; i
< 4; i
++) {
3119 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3120 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
3122 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3124 alu
.src
[0].sel
= ctx
->temp_reg
;
3125 alu
.src
[0].chan
= i
;
3128 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
3131 alu
.src
[2].sel
= ctx
->temp_reg
;
3132 alu
.src
[2].chan
= i
;
3136 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3143 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
3145 struct r600_bytecode_alu alu
;
3148 for (i
= 0; i
< 4; i
++) {
3149 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3150 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
3151 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
);
3154 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
3155 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3156 alu
.src
[0].sel
= ctx
->temp_reg
;
3157 alu
.src
[0].chan
= i
;
3162 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3169 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
3171 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3172 struct r600_bytecode_alu alu
;
3174 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
3176 for (i
= 0; i
< lasti
+ 1; i
++) {
3177 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
3180 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3181 alu
.inst
= ctx
->inst_info
->r600_opcode
;
3182 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
3183 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
3186 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3193 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3200 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
3202 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3203 struct r600_bytecode_alu alu
;
3206 for (i
= 0; i
< 4; i
++) {
3207 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3208 alu
.inst
= ctx
->inst_info
->r600_opcode
;
3209 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
3210 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
3213 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3215 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
3216 /* handle some special cases */
3217 switch (ctx
->inst_info
->tgsi_opcode
) {
3218 case TGSI_OPCODE_DP2
:
3220 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
3221 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
3224 case TGSI_OPCODE_DP3
:
3226 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
3227 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
3230 case TGSI_OPCODE_DPH
:
3232 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
3233 alu
.src
[0].chan
= 0;
3243 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3250 static inline boolean
tgsi_tex_src_requires_loading(struct r600_shader_ctx
*ctx
,
3253 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3254 return (inst
->Src
[index
].Register
.File
!= TGSI_FILE_TEMPORARY
&&
3255 inst
->Src
[index
].Register
.File
!= TGSI_FILE_INPUT
) ||
3256 ctx
->src
[index
].neg
|| ctx
->src
[index
].abs
;
3259 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx
*ctx
,
3262 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3263 return ctx
->file_offset
[inst
->Src
[index
].Register
.File
] + inst
->Src
[index
].Register
.Index
;
3266 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
3268 static float one_point_five
= 1.5f
;
3269 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3270 struct r600_bytecode_tex tex
;
3271 struct r600_bytecode_alu alu
;
3275 /* Texture fetch instructions can only use gprs as source.
3276 * Also they cannot negate the source or take the absolute value */
3277 const boolean src_requires_loading
= tgsi_tex_src_requires_loading(ctx
, 0);
3278 boolean src_loaded
= FALSE
;
3279 unsigned sampler_src_reg
= 1;
3280 uint8_t offset_x
= 0, offset_y
= 0, offset_z
= 0;
3282 src_gpr
= tgsi_tex_get_src_gpr(ctx
, 0);
3284 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
) {
3285 /* get offset values */
3286 if (inst
->Texture
.NumOffsets
) {
3287 assert(inst
->Texture
.NumOffsets
== 1);
3289 offset_x
= ctx
->literals
[inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleX
] << 1;
3290 offset_y
= ctx
->literals
[inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleY
] << 1;
3291 offset_z
= ctx
->literals
[inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleZ
] << 1;
3293 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
) {
3294 /* TGSI moves the sampler to src reg 3 for TXD */
3295 sampler_src_reg
= 3;
3297 for (i
= 1; i
< 3; i
++) {
3298 /* set gradients h/v */
3299 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
3300 tex
.inst
= (i
== 1) ? SQ_TEX_INST_SET_GRADIENTS_H
:
3301 SQ_TEX_INST_SET_GRADIENTS_V
;
3302 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
3303 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
3305 if (tgsi_tex_src_requires_loading(ctx
, i
)) {
3306 tex
.src_gpr
= r600_get_temp(ctx
);
3312 for (j
= 0; j
< 4; j
++) {
3313 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3314 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
3315 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[i
], j
);
3316 alu
.dst
.sel
= tex
.src_gpr
;
3321 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3327 tex
.src_gpr
= tgsi_tex_get_src_gpr(ctx
, i
);
3328 tex
.src_sel_x
= ctx
->src
[i
].swizzle
[0];
3329 tex
.src_sel_y
= ctx
->src
[i
].swizzle
[1];
3330 tex
.src_sel_z
= ctx
->src
[i
].swizzle
[2];
3331 tex
.src_sel_w
= ctx
->src
[i
].swizzle
[3];
3332 tex
.src_rel
= ctx
->src
[i
].rel
;
3334 tex
.dst_gpr
= ctx
->temp_reg
; /* just to avoid confusing the asm scheduler */
3335 tex
.dst_sel_x
= tex
.dst_sel_y
= tex
.dst_sel_z
= tex
.dst_sel_w
= 7;
3336 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
3337 tex
.coord_type_x
= 1;
3338 tex
.coord_type_y
= 1;
3339 tex
.coord_type_z
= 1;
3340 tex
.coord_type_w
= 1;
3342 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
3346 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
3348 /* Add perspective divide */
3349 if (ctx
->bc
->chip_class
== CAYMAN
) {
3351 for (i
= 0; i
< 3; i
++) {
3352 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3353 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
3354 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
3356 alu
.dst
.sel
= ctx
->temp_reg
;
3362 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3369 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3370 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
3371 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
3373 alu
.dst
.sel
= ctx
->temp_reg
;
3374 alu
.dst
.chan
= out_chan
;
3377 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3382 for (i
= 0; i
< 3; i
++) {
3383 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3384 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
3385 alu
.src
[0].sel
= ctx
->temp_reg
;
3386 alu
.src
[0].chan
= out_chan
;
3387 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3388 alu
.dst
.sel
= ctx
->temp_reg
;
3391 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3395 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3396 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
3397 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
3398 alu
.src
[0].chan
= 0;
3399 alu
.dst
.sel
= ctx
->temp_reg
;
3403 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3407 src_gpr
= ctx
->temp_reg
;
3410 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
3411 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
) &&
3412 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ
) {
3414 static const unsigned src0_swizzle
[] = {2, 2, 0, 1};
3415 static const unsigned src1_swizzle
[] = {1, 0, 2, 2};
3417 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
3418 for (i
= 0; i
< 4; i
++) {
3419 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3420 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
);
3421 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src0_swizzle
[i
]);
3422 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], src1_swizzle
[i
]);
3423 alu
.dst
.sel
= ctx
->temp_reg
;
3428 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3433 /* tmp1.z = RCP_e(|tmp1.z|) */
3434 if (ctx
->bc
->chip_class
== CAYMAN
) {
3435 for (i
= 0; i
< 3; i
++) {
3436 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3437 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
3438 alu
.src
[0].sel
= ctx
->temp_reg
;
3439 alu
.src
[0].chan
= 2;
3441 alu
.dst
.sel
= ctx
->temp_reg
;
3447 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3452 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3453 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
3454 alu
.src
[0].sel
= ctx
->temp_reg
;
3455 alu
.src
[0].chan
= 2;
3457 alu
.dst
.sel
= ctx
->temp_reg
;
3461 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3466 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
3467 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
3468 * muladd has no writemask, have to use another temp
3470 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3471 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
3474 alu
.src
[0].sel
= ctx
->temp_reg
;
3475 alu
.src
[0].chan
= 0;
3476 alu
.src
[1].sel
= ctx
->temp_reg
;
3477 alu
.src
[1].chan
= 2;
3479 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
3480 alu
.src
[2].chan
= 0;
3481 alu
.src
[2].value
= *(uint32_t *)&one_point_five
;
3483 alu
.dst
.sel
= ctx
->temp_reg
;
3487 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3491 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3492 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
3495 alu
.src
[0].sel
= ctx
->temp_reg
;
3496 alu
.src
[0].chan
= 1;
3497 alu
.src
[1].sel
= ctx
->temp_reg
;
3498 alu
.src
[1].chan
= 2;
3500 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
3501 alu
.src
[2].chan
= 0;
3502 alu
.src
[2].value
= *(uint32_t *)&one_point_five
;
3504 alu
.dst
.sel
= ctx
->temp_reg
;
3509 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3512 /* write initial W value into Z component */
3513 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
) {
3514 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3515 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
3516 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
3517 alu
.dst
.sel
= ctx
->temp_reg
;
3521 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3526 src_gpr
= ctx
->temp_reg
;
3529 if (src_requires_loading
&& !src_loaded
) {
3530 for (i
= 0; i
< 4; i
++) {
3531 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3532 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
3533 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3534 alu
.dst
.sel
= ctx
->temp_reg
;
3539 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3544 src_gpr
= ctx
->temp_reg
;
3547 opcode
= ctx
->inst_info
->r600_opcode
;
3548 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
3549 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
3550 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
3551 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
3552 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
3553 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
) {
3555 case SQ_TEX_INST_SAMPLE
:
3556 opcode
= SQ_TEX_INST_SAMPLE_C
;
3558 case SQ_TEX_INST_SAMPLE_L
:
3559 opcode
= SQ_TEX_INST_SAMPLE_C_L
;
3561 case SQ_TEX_INST_SAMPLE_LB
:
3562 opcode
= SQ_TEX_INST_SAMPLE_C_LB
;
3564 case SQ_TEX_INST_SAMPLE_G
:
3565 opcode
= SQ_TEX_INST_SAMPLE_C_G
;
3570 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
3573 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
3574 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
3575 tex
.src_gpr
= src_gpr
;
3576 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
3577 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
3578 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
3579 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
3580 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
3587 tex
.src_sel_x
= ctx
->src
[0].swizzle
[0];
3588 tex
.src_sel_y
= ctx
->src
[0].swizzle
[1];
3589 tex
.src_sel_z
= ctx
->src
[0].swizzle
[2];
3590 tex
.src_sel_w
= ctx
->src
[0].swizzle
[3];
3591 tex
.src_rel
= ctx
->src
[0].rel
;
3594 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
) {
3600 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
) {
3604 tex
.src_sel_w
= 2; /* route Z compare value into W */
3607 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
&&
3608 inst
->Texture
.Texture
!= TGSI_TEXTURE_SHADOWRECT
) {
3609 tex
.coord_type_x
= 1;
3610 tex
.coord_type_y
= 1;
3612 tex
.coord_type_z
= 1;
3613 tex
.coord_type_w
= 1;
3615 tex
.offset_x
= offset_x
;
3616 tex
.offset_y
= offset_y
;
3617 tex
.offset_z
= offset_z
;
3619 /* Put the depth for comparison in W.
3620 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
3621 * Some instructions expect the depth in Z. */
3622 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
3623 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
3624 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
3625 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) &&
3626 opcode
!= SQ_TEX_INST_SAMPLE_C_L
&&
3627 opcode
!= SQ_TEX_INST_SAMPLE_C_LB
) {
3628 tex
.src_sel_w
= tex
.src_sel_z
;
3631 if (inst
->Texture
.Texture
== TGSI_TEXTURE_1D_ARRAY
||
3632 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) {
3633 if (opcode
== SQ_TEX_INST_SAMPLE_C_L
||
3634 opcode
== SQ_TEX_INST_SAMPLE_C_LB
) {
3635 /* the array index is read from Y */
3636 tex
.coord_type_y
= 0;
3638 /* the array index is read from Z */
3639 tex
.coord_type_z
= 0;
3640 tex
.src_sel_z
= tex
.src_sel_y
;
3642 } else if (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
||
3643 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
)
3644 /* the array index is read from Z */
3645 tex
.coord_type_z
= 0;
3647 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
3651 /* add shadow ambient support - gallium doesn't do it yet */
3655 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
3657 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3658 struct r600_bytecode_alu alu
;
3659 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
3663 /* optimize if it's just an equal balance */
3664 if (ctx
->src
[0].sel
== V_SQ_ALU_SRC_0_5
) {
3665 for (i
= 0; i
< lasti
+ 1; i
++) {
3666 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
3669 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3670 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
);
3671 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
3672 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
3674 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3679 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3687 for (i
= 0; i
< lasti
+ 1; i
++) {
3688 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
3691 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3692 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
);
3693 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
3694 alu
.src
[0].chan
= 0;
3695 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3696 r600_bytecode_src_toggle_neg(&alu
.src
[1]);
3697 alu
.dst
.sel
= ctx
->temp_reg
;
3703 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3708 /* (1 - src0) * src2 */
3709 for (i
= 0; i
< lasti
+ 1; i
++) {
3710 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
3713 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3714 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
3715 alu
.src
[0].sel
= ctx
->temp_reg
;
3716 alu
.src
[0].chan
= i
;
3717 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
3718 alu
.dst
.sel
= ctx
->temp_reg
;
3724 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3729 /* src0 * src1 + (1 - src0) * src2 */
3730 for (i
= 0; i
< lasti
+ 1; i
++) {
3731 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
3734 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3735 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
3737 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3738 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
3739 alu
.src
[2].sel
= ctx
->temp_reg
;
3740 alu
.src
[2].chan
= i
;
3742 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3747 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3754 static int tgsi_cmp(struct r600_shader_ctx
*ctx
)
3756 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3757 struct r600_bytecode_alu alu
;
3759 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
3761 for (i
= 0; i
< lasti
+ 1; i
++) {
3762 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
3765 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3766 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE
);
3767 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3768 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
3769 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[1], i
);
3770 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3776 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3783 static int tgsi_xpd(struct r600_shader_ctx
*ctx
)
3785 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3786 static const unsigned int src0_swizzle
[] = {2, 0, 1};
3787 static const unsigned int src1_swizzle
[] = {1, 2, 0};
3788 struct r600_bytecode_alu alu
;
3789 uint32_t use_temp
= 0;
3792 if (inst
->Dst
[0].Register
.WriteMask
!= 0xf)
3795 for (i
= 0; i
< 4; i
++) {
3796 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3797 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
3799 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src0_swizzle
[i
]);
3800 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], src1_swizzle
[i
]);
3802 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
3803 alu
.src
[0].chan
= i
;
3804 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
3805 alu
.src
[1].chan
= i
;
3808 alu
.dst
.sel
= ctx
->temp_reg
;
3814 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3819 for (i
= 0; i
< 4; i
++) {
3820 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3821 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
3824 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src1_swizzle
[i
]);
3825 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], src0_swizzle
[i
]);
3827 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
3828 alu
.src
[0].chan
= i
;
3829 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
3830 alu
.src
[1].chan
= i
;
3833 alu
.src
[2].sel
= ctx
->temp_reg
;
3835 alu
.src
[2].chan
= i
;
3838 alu
.dst
.sel
= ctx
->temp_reg
;
3840 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3846 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3851 return tgsi_helper_copy(ctx
, inst
);
3855 static int tgsi_exp(struct r600_shader_ctx
*ctx
)
3857 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3858 struct r600_bytecode_alu alu
;
3862 /* result.x = 2^floor(src); */
3863 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
3864 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3866 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
3867 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
3869 alu
.dst
.sel
= ctx
->temp_reg
;
3873 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3877 if (ctx
->bc
->chip_class
== CAYMAN
) {
3878 for (i
= 0; i
< 3; i
++) {
3879 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
3880 alu
.src
[0].sel
= ctx
->temp_reg
;
3881 alu
.src
[0].chan
= 0;
3883 alu
.dst
.sel
= ctx
->temp_reg
;
3889 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3894 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
3895 alu
.src
[0].sel
= ctx
->temp_reg
;
3896 alu
.src
[0].chan
= 0;
3898 alu
.dst
.sel
= ctx
->temp_reg
;
3902 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3908 /* result.y = tmp - floor(tmp); */
3909 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
3910 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3912 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
);
3913 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
3915 alu
.dst
.sel
= ctx
->temp_reg
;
3917 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3926 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3931 /* result.z = RoughApprox2ToX(tmp);*/
3932 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 0x1) {
3933 if (ctx
->bc
->chip_class
== CAYMAN
) {
3934 for (i
= 0; i
< 3; i
++) {
3935 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3936 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
3937 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
3939 alu
.dst
.sel
= ctx
->temp_reg
;
3946 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3951 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3952 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
3953 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
3955 alu
.dst
.sel
= ctx
->temp_reg
;
3961 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3967 /* result.w = 1.0;*/
3968 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 0x1) {
3969 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3971 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
3972 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
3973 alu
.src
[0].chan
= 0;
3975 alu
.dst
.sel
= ctx
->temp_reg
;
3979 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3983 return tgsi_helper_copy(ctx
, inst
);
3986 static int tgsi_log(struct r600_shader_ctx
*ctx
)
3988 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3989 struct r600_bytecode_alu alu
;
3993 /* result.x = floor(log2(|src|)); */
3994 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
3995 if (ctx
->bc
->chip_class
== CAYMAN
) {
3996 for (i
= 0; i
< 3; i
++) {
3997 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3999 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
4000 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4001 r600_bytecode_src_set_abs(&alu
.src
[0]);
4003 alu
.dst
.sel
= ctx
->temp_reg
;
4009 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4015 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4017 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
4018 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4019 r600_bytecode_src_set_abs(&alu
.src
[0]);
4021 alu
.dst
.sel
= ctx
->temp_reg
;
4025 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4030 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
4031 alu
.src
[0].sel
= ctx
->temp_reg
;
4032 alu
.src
[0].chan
= 0;
4034 alu
.dst
.sel
= ctx
->temp_reg
;
4039 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4044 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
4045 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
4047 if (ctx
->bc
->chip_class
== CAYMAN
) {
4048 for (i
= 0; i
< 3; i
++) {
4049 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4051 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
4052 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4053 r600_bytecode_src_set_abs(&alu
.src
[0]);
4055 alu
.dst
.sel
= ctx
->temp_reg
;
4062 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4067 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4069 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
4070 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4071 r600_bytecode_src_set_abs(&alu
.src
[0]);
4073 alu
.dst
.sel
= ctx
->temp_reg
;
4078 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4083 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4085 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
4086 alu
.src
[0].sel
= ctx
->temp_reg
;
4087 alu
.src
[0].chan
= 1;
4089 alu
.dst
.sel
= ctx
->temp_reg
;
4094 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4098 if (ctx
->bc
->chip_class
== CAYMAN
) {
4099 for (i
= 0; i
< 3; i
++) {
4100 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4101 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
4102 alu
.src
[0].sel
= ctx
->temp_reg
;
4103 alu
.src
[0].chan
= 1;
4105 alu
.dst
.sel
= ctx
->temp_reg
;
4112 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4117 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4118 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
4119 alu
.src
[0].sel
= ctx
->temp_reg
;
4120 alu
.src
[0].chan
= 1;
4122 alu
.dst
.sel
= ctx
->temp_reg
;
4127 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4132 if (ctx
->bc
->chip_class
== CAYMAN
) {
4133 for (i
= 0; i
< 3; i
++) {
4134 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4135 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
4136 alu
.src
[0].sel
= ctx
->temp_reg
;
4137 alu
.src
[0].chan
= 1;
4139 alu
.dst
.sel
= ctx
->temp_reg
;
4146 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4151 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4152 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
4153 alu
.src
[0].sel
= ctx
->temp_reg
;
4154 alu
.src
[0].chan
= 1;
4156 alu
.dst
.sel
= ctx
->temp_reg
;
4161 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4166 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4168 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
4170 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4171 r600_bytecode_src_set_abs(&alu
.src
[0]);
4173 alu
.src
[1].sel
= ctx
->temp_reg
;
4174 alu
.src
[1].chan
= 1;
4176 alu
.dst
.sel
= ctx
->temp_reg
;
4181 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4186 /* result.z = log2(|src|);*/
4187 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 1) {
4188 if (ctx
->bc
->chip_class
== CAYMAN
) {
4189 for (i
= 0; i
< 3; i
++) {
4190 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4192 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
4193 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4194 r600_bytecode_src_set_abs(&alu
.src
[0]);
4196 alu
.dst
.sel
= ctx
->temp_reg
;
4203 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4208 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4210 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
4211 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4212 r600_bytecode_src_set_abs(&alu
.src
[0]);
4214 alu
.dst
.sel
= ctx
->temp_reg
;
4219 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4225 /* result.w = 1.0; */
4226 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 1) {
4227 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4229 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
4230 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
4231 alu
.src
[0].chan
= 0;
4233 alu
.dst
.sel
= ctx
->temp_reg
;
4238 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4243 return tgsi_helper_copy(ctx
, inst
);
4246 static int tgsi_eg_arl(struct r600_shader_ctx
*ctx
)
4248 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4249 struct r600_bytecode_alu alu
;
4252 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4254 switch (inst
->Instruction
.Opcode
) {
4255 case TGSI_OPCODE_ARL
:
4256 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR
;
4258 case TGSI_OPCODE_ARR
:
4259 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
;
4261 case TGSI_OPCODE_UARL
:
4262 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
4269 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4271 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
4273 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4277 ctx
->bc
->ar_loaded
= 0;
4280 static int tgsi_r600_arl(struct r600_shader_ctx
*ctx
)
4282 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4283 struct r600_bytecode_alu alu
;
4286 switch (inst
->Instruction
.Opcode
) {
4287 case TGSI_OPCODE_ARL
:
4288 memset(&alu
, 0, sizeof(alu
));
4289 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
;
4290 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4291 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
4295 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4298 memset(&alu
, 0, sizeof(alu
));
4299 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
;
4300 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
4301 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
4305 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4308 case TGSI_OPCODE_ARR
:
4309 memset(&alu
, 0, sizeof(alu
));
4310 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
;
4311 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4312 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
4316 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4319 case TGSI_OPCODE_UARL
:
4320 memset(&alu
, 0, sizeof(alu
));
4321 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
4322 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4323 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
4327 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4335 ctx
->bc
->ar_loaded
= 0;
4339 static int tgsi_opdst(struct r600_shader_ctx
*ctx
)
4341 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4342 struct r600_bytecode_alu alu
;
4345 for (i
= 0; i
< 4; i
++) {
4346 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4348 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
4349 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4351 if (i
== 0 || i
== 3) {
4352 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
4354 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4357 if (i
== 0 || i
== 2) {
4358 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
4360 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
4364 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4371 static int emit_logic_pred(struct r600_shader_ctx
*ctx
, int opcode
)
4373 struct r600_bytecode_alu alu
;
4376 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4380 alu
.dst
.sel
= ctx
->temp_reg
;
4384 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4385 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
4386 alu
.src
[1].chan
= 0;
4390 r
= r600_bytecode_add_alu_type(ctx
->bc
, &alu
, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
));
4396 static int pops(struct r600_shader_ctx
*ctx
, int pops
)
4398 unsigned force_pop
= ctx
->bc
->force_add_cf
;
4402 if (ctx
->bc
->cf_last
) {
4403 if (ctx
->bc
->cf_last
->inst
== CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
))
4405 else if (ctx
->bc
->cf_last
->inst
== CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
))
4410 ctx
->bc
->cf_last
->inst
= CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
);
4411 ctx
->bc
->force_add_cf
= 1;
4412 } else if (alu_pop
== 2) {
4413 ctx
->bc
->cf_last
->inst
= CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
);
4414 ctx
->bc
->force_add_cf
= 1;
4421 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP
));
4422 ctx
->bc
->cf_last
->pop_count
= pops
;
4423 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
4429 static inline void callstack_decrease_current(struct r600_shader_ctx
*ctx
, unsigned reason
)
4433 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
--;
4437 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
-= 4;
4440 /* TOODO : for 16 vp asic should -= 2; */
4441 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
--;
4446 static inline void callstack_check_depth(struct r600_shader_ctx
*ctx
, unsigned reason
, unsigned check_max_only
)
4448 if (check_max_only
) {
4461 if ((ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+ diff
) >
4462 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
) {
4463 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
=
4464 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+ diff
;
4470 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
++;
4474 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+= 4;
4477 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
++;
4481 if ((ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
) >
4482 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
) {
4483 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
=
4484 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
;
4488 static void fc_set_mid(struct r600_shader_ctx
*ctx
, int fc_sp
)
4490 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[fc_sp
];
4492 sp
->mid
= (struct r600_bytecode_cf
**)realloc((void *)sp
->mid
,
4493 sizeof(struct r600_bytecode_cf
*) * (sp
->num_mid
+ 1));
4494 sp
->mid
[sp
->num_mid
] = ctx
->bc
->cf_last
;
4498 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
)
4501 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
= type
;
4502 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
= ctx
->bc
->cf_last
;
4505 static void fc_poplevel(struct r600_shader_ctx
*ctx
)
4507 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
];
4519 static int emit_return(struct r600_shader_ctx
*ctx
)
4521 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN
));
4525 static int emit_jump_to_offset(struct r600_shader_ctx
*ctx
, int pops
, int offset
)
4528 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP
));
4529 ctx
->bc
->cf_last
->pop_count
= pops
;
4530 /* TODO work out offset */
4534 static int emit_setret_in_loop_flag(struct r600_shader_ctx
*ctx
, unsigned flag_value
)
4539 static void emit_testflag(struct r600_shader_ctx
*ctx
)
4544 static void emit_return_on_flag(struct r600_shader_ctx
*ctx
, unsigned ifidx
)
4547 emit_jump_to_offset(ctx
, 1, 4);
4548 emit_setret_in_loop_flag(ctx
, V_SQ_ALU_SRC_0
);
4549 pops(ctx
, ifidx
+ 1);
4553 static void break_loop_on_flag(struct r600_shader_ctx
*ctx
, unsigned fc_sp
)
4557 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->r600_opcode
);
4558 ctx
->bc
->cf_last
->pop_count
= 1;
4560 fc_set_mid(ctx
, fc_sp
);
4566 static int tgsi_if(struct r600_shader_ctx
*ctx
)
4568 emit_logic_pred(ctx
, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
));
4570 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP
));
4572 fc_pushlevel(ctx
, FC_IF
);
4574 callstack_check_depth(ctx
, FC_PUSH_VPM
, 0);
4578 static int tgsi_else(struct r600_shader_ctx
*ctx
)
4580 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE
));
4581 ctx
->bc
->cf_last
->pop_count
= 1;
4583 fc_set_mid(ctx
, ctx
->bc
->fc_sp
);
4584 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
;
4588 static int tgsi_endif(struct r600_shader_ctx
*ctx
)
4591 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_IF
) {
4592 R600_ERR("if/endif unbalanced in shader\n");
4596 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
== NULL
) {
4597 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
4598 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->pop_count
= 1;
4600 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[0]->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
4604 callstack_decrease_current(ctx
, FC_PUSH_VPM
);
4608 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
)
4610 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
));
4612 fc_pushlevel(ctx
, FC_LOOP
);
4614 /* check stack depth */
4615 callstack_check_depth(ctx
, FC_LOOP
, 0);
4619 static int tgsi_endloop(struct r600_shader_ctx
*ctx
)
4623 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
));
4625 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_LOOP
) {
4626 R600_ERR("loop/endloop in shader code are not paired.\n");
4630 /* fixup loop pointers - from r600isa
4631 LOOP END points to CF after LOOP START,
4632 LOOP START point to CF after LOOP END
4633 BRK/CONT point to LOOP END CF
4635 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->id
+ 2;
4637 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
4639 for (i
= 0; i
< ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].num_mid
; i
++) {
4640 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[i
]->cf_addr
= ctx
->bc
->cf_last
->id
;
4642 /* TODO add LOOPRET support */
4644 callstack_decrease_current(ctx
, FC_LOOP
);
4648 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
)
4652 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
4654 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
].type
)
4659 R600_ERR("Break not inside loop/endloop pair\n");
4663 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->r600_opcode
);
4665 fc_set_mid(ctx
, fscp
);
4667 callstack_check_depth(ctx
, FC_PUSH_VPM
, 1);
4671 static int tgsi_umad(struct r600_shader_ctx
*ctx
)
4673 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4674 struct r600_bytecode_alu alu
;
4676 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4679 for (i
= 0; i
< lasti
+ 1; i
++) {
4680 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4683 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4686 alu
.dst
.sel
= ctx
->temp_reg
;
4689 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
);
4690 for (j
= 0; j
< 2; j
++) {
4691 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
4695 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4701 for (i
= 0; i
< lasti
+ 1; i
++) {
4702 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4705 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4706 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4708 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
4710 alu
.src
[0].sel
= ctx
->temp_reg
;
4711 alu
.src
[0].chan
= i
;
4713 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
4717 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4724 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
4725 {TGSI_OPCODE_ARL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_r600_arl
},
4726 {TGSI_OPCODE_MOV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
4727 {TGSI_OPCODE_LIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
4730 * For state trackers other than OpenGL, we'll want to use
4731 * _RECIP_IEEE instead.
4733 {TGSI_OPCODE_RCP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED
, tgsi_trans_srcx_replicate
},
4735 {TGSI_OPCODE_RSQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_rsq
},
4736 {TGSI_OPCODE_EXP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
4737 {TGSI_OPCODE_LOG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_log
},
4738 {TGSI_OPCODE_MUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
4739 {TGSI_OPCODE_ADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
4740 {TGSI_OPCODE_DP3
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
4741 {TGSI_OPCODE_DP4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
4742 {TGSI_OPCODE_DST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
4743 {TGSI_OPCODE_MIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
4744 {TGSI_OPCODE_MAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
4745 {TGSI_OPCODE_SLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
4746 {TGSI_OPCODE_SGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
4747 {TGSI_OPCODE_MAD
, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
4748 {TGSI_OPCODE_SUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
4749 {TGSI_OPCODE_LRP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
4750 {TGSI_OPCODE_CND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4752 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4753 {TGSI_OPCODE_DP2A
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4755 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4756 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4757 {TGSI_OPCODE_FRC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
4758 {TGSI_OPCODE_CLAMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4759 {TGSI_OPCODE_FLR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
4760 {TGSI_OPCODE_ROUND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE
, tgsi_op2
},
4761 {TGSI_OPCODE_EX2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
4762 {TGSI_OPCODE_LG2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
4763 {TGSI_OPCODE_POW
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
4764 {TGSI_OPCODE_XPD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
4766 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4767 {TGSI_OPCODE_ABS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
4768 {TGSI_OPCODE_RCC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4769 {TGSI_OPCODE_DPH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
4770 {TGSI_OPCODE_COS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
4771 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
4772 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
4773 {TGSI_OPCODE_KILP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
4774 {TGSI_OPCODE_PK2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4775 {TGSI_OPCODE_PK2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4776 {TGSI_OPCODE_PK4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4777 {TGSI_OPCODE_PK4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4778 {TGSI_OPCODE_RFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4779 {TGSI_OPCODE_SEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
4780 {TGSI_OPCODE_SFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4781 {TGSI_OPCODE_SGT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
4782 {TGSI_OPCODE_SIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
4783 {TGSI_OPCODE_SLE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
4784 {TGSI_OPCODE_SNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
4785 {TGSI_OPCODE_STR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4786 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
4787 {TGSI_OPCODE_TXD
, 0, SQ_TEX_INST_SAMPLE_G
, tgsi_tex
},
4788 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
4789 {TGSI_OPCODE_UP2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4790 {TGSI_OPCODE_UP2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4791 {TGSI_OPCODE_UP4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4792 {TGSI_OPCODE_UP4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4793 {TGSI_OPCODE_X2D
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4794 {TGSI_OPCODE_ARA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4795 {TGSI_OPCODE_ARR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_r600_arl
},
4796 {TGSI_OPCODE_BRA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4797 {TGSI_OPCODE_CAL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4798 {TGSI_OPCODE_RET
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4799 {TGSI_OPCODE_SSG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
4800 {TGSI_OPCODE_CMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
4801 {TGSI_OPCODE_SCS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
4802 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_LB
, tgsi_tex
},
4803 {TGSI_OPCODE_NRM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4804 {TGSI_OPCODE_DIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4805 {TGSI_OPCODE_DP2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
4806 {TGSI_OPCODE_TXL
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
4807 {TGSI_OPCODE_BRK
, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
4808 {TGSI_OPCODE_IF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
4810 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4811 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4812 {TGSI_OPCODE_ELSE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
4813 {TGSI_OPCODE_ENDIF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
4815 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4816 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4817 {TGSI_OPCODE_PUSHA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4818 {TGSI_OPCODE_POPA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4819 {TGSI_OPCODE_CEIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4820 {TGSI_OPCODE_I2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
, tgsi_op2_trans
},
4821 {TGSI_OPCODE_NOT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT
, tgsi_op2
},
4822 {TGSI_OPCODE_TRUNC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_op2
},
4823 {TGSI_OPCODE_SHL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT
, tgsi_op2_trans
},
4825 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4826 {TGSI_OPCODE_AND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT
, tgsi_op2
},
4827 {TGSI_OPCODE_OR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT
, tgsi_op2
},
4828 {TGSI_OPCODE_MOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_imod
},
4829 {TGSI_OPCODE_XOR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT
, tgsi_op2
},
4830 {TGSI_OPCODE_SAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4831 {TGSI_OPCODE_TXF
, 0, SQ_TEX_INST_LD
, tgsi_tex
},
4832 {TGSI_OPCODE_TXQ
, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO
, tgsi_tex
},
4833 {TGSI_OPCODE_CONT
, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
4834 {TGSI_OPCODE_EMIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4835 {TGSI_OPCODE_ENDPRIM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4836 {TGSI_OPCODE_BGNLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
4837 {TGSI_OPCODE_BGNSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4838 {TGSI_OPCODE_ENDLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
4839 {TGSI_OPCODE_ENDSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4841 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4842 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4843 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4844 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4845 {TGSI_OPCODE_NOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4847 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4848 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4849 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4850 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4851 {TGSI_OPCODE_NRM4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4852 {TGSI_OPCODE_CALLNZ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4853 {TGSI_OPCODE_IFC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4854 {TGSI_OPCODE_BREAKC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4855 {TGSI_OPCODE_KIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
4856 {TGSI_OPCODE_END
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
4858 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4859 {TGSI_OPCODE_F2I
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
, tgsi_op2_trans
},
4860 {TGSI_OPCODE_IDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_idiv
},
4861 {TGSI_OPCODE_IMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT
, tgsi_op2
},
4862 {TGSI_OPCODE_IMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT
, tgsi_op2
},
4863 {TGSI_OPCODE_INEG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
, tgsi_ineg
},
4864 {TGSI_OPCODE_ISGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT
, tgsi_op2
},
4865 {TGSI_OPCODE_ISHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT
, tgsi_op2_trans
},
4866 {TGSI_OPCODE_ISLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT
, tgsi_op2_swap
},
4867 {TGSI_OPCODE_F2U
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
, tgsi_op2
},
4868 {TGSI_OPCODE_U2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
, tgsi_op2_trans
},
4869 {TGSI_OPCODE_UADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
, tgsi_op2
},
4870 {TGSI_OPCODE_UDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_udiv
},
4871 {TGSI_OPCODE_UMAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_umad
},
4872 {TGSI_OPCODE_UMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT
, tgsi_op2
},
4873 {TGSI_OPCODE_UMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT
, tgsi_op2
},
4874 {TGSI_OPCODE_UMOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_umod
},
4875 {TGSI_OPCODE_UMUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
, tgsi_op2_trans
},
4876 {TGSI_OPCODE_USEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT
, tgsi_op2
},
4877 {TGSI_OPCODE_USGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
, tgsi_op2
},
4878 {TGSI_OPCODE_USHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT
, tgsi_op2_trans
},
4879 {TGSI_OPCODE_USLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT
, tgsi_op2_swap
},
4880 {TGSI_OPCODE_USNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT
, tgsi_op2_swap
},
4881 {TGSI_OPCODE_SWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4882 {TGSI_OPCODE_CASE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4883 {TGSI_OPCODE_DEFAULT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4884 {TGSI_OPCODE_ENDSWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4885 {TGSI_OPCODE_LOAD
, 0, 0, tgsi_unsupported
},
4886 {TGSI_OPCODE_LOAD_MS
, 0, 0, tgsi_unsupported
},
4887 {TGSI_OPCODE_SAMPLE
, 0, 0, tgsi_unsupported
},
4888 {TGSI_OPCODE_SAMPLE_B
, 0, 0, tgsi_unsupported
},
4889 {TGSI_OPCODE_SAMPLE_C
, 0, 0, tgsi_unsupported
},
4890 {TGSI_OPCODE_SAMPLE_C_LZ
, 0, 0, tgsi_unsupported
},
4891 {TGSI_OPCODE_SAMPLE_D
, 0, 0, tgsi_unsupported
},
4892 {TGSI_OPCODE_SAMPLE_L
, 0, 0, tgsi_unsupported
},
4893 {TGSI_OPCODE_GATHER4
, 0, 0, tgsi_unsupported
},
4894 {TGSI_OPCODE_RESINFO
, 0, 0, tgsi_unsupported
},
4895 {TGSI_OPCODE_SAMPLE_POS
, 0, 0, tgsi_unsupported
},
4896 {TGSI_OPCODE_SAMPLE_INFO
, 0, 0, tgsi_unsupported
},
4897 {TGSI_OPCODE_UARL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
, tgsi_r600_arl
},
4898 {TGSI_OPCODE_UCMP
, 0, 0, tgsi_unsupported
},
4899 {TGSI_OPCODE_IABS
, 0, 0, tgsi_iabs
},
4900 {TGSI_OPCODE_ISSG
, 0, 0, tgsi_issg
},
4901 {TGSI_OPCODE_LAST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4904 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction
[] = {
4905 {TGSI_OPCODE_ARL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
4906 {TGSI_OPCODE_MOV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
4907 {TGSI_OPCODE_LIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
4908 {TGSI_OPCODE_RCP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
4909 {TGSI_OPCODE_RSQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
, tgsi_rsq
},
4910 {TGSI_OPCODE_EXP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
4911 {TGSI_OPCODE_LOG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_log
},
4912 {TGSI_OPCODE_MUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
4913 {TGSI_OPCODE_ADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
4914 {TGSI_OPCODE_DP3
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
4915 {TGSI_OPCODE_DP4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
4916 {TGSI_OPCODE_DST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
4917 {TGSI_OPCODE_MIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
4918 {TGSI_OPCODE_MAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
4919 {TGSI_OPCODE_SLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
4920 {TGSI_OPCODE_SGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
4921 {TGSI_OPCODE_MAD
, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
4922 {TGSI_OPCODE_SUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
4923 {TGSI_OPCODE_LRP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
4924 {TGSI_OPCODE_CND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4926 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4927 {TGSI_OPCODE_DP2A
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4929 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4930 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4931 {TGSI_OPCODE_FRC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
4932 {TGSI_OPCODE_CLAMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4933 {TGSI_OPCODE_FLR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
4934 {TGSI_OPCODE_ROUND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE
, tgsi_op2
},
4935 {TGSI_OPCODE_EX2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
4936 {TGSI_OPCODE_LG2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
4937 {TGSI_OPCODE_POW
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
4938 {TGSI_OPCODE_XPD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
4940 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4941 {TGSI_OPCODE_ABS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
4942 {TGSI_OPCODE_RCC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4943 {TGSI_OPCODE_DPH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
4944 {TGSI_OPCODE_COS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
4945 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
4946 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
4947 {TGSI_OPCODE_KILP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
4948 {TGSI_OPCODE_PK2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4949 {TGSI_OPCODE_PK2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4950 {TGSI_OPCODE_PK4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4951 {TGSI_OPCODE_PK4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4952 {TGSI_OPCODE_RFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4953 {TGSI_OPCODE_SEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
4954 {TGSI_OPCODE_SFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4955 {TGSI_OPCODE_SGT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
4956 {TGSI_OPCODE_SIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
4957 {TGSI_OPCODE_SLE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
4958 {TGSI_OPCODE_SNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
4959 {TGSI_OPCODE_STR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4960 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
4961 {TGSI_OPCODE_TXD
, 0, SQ_TEX_INST_SAMPLE_G
, tgsi_tex
},
4962 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
4963 {TGSI_OPCODE_UP2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4964 {TGSI_OPCODE_UP2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4965 {TGSI_OPCODE_UP4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4966 {TGSI_OPCODE_UP4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4967 {TGSI_OPCODE_X2D
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4968 {TGSI_OPCODE_ARA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4969 {TGSI_OPCODE_ARR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
4970 {TGSI_OPCODE_BRA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4971 {TGSI_OPCODE_CAL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4972 {TGSI_OPCODE_RET
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4973 {TGSI_OPCODE_SSG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
4974 {TGSI_OPCODE_CMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
4975 {TGSI_OPCODE_SCS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
4976 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_LB
, tgsi_tex
},
4977 {TGSI_OPCODE_NRM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4978 {TGSI_OPCODE_DIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4979 {TGSI_OPCODE_DP2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
4980 {TGSI_OPCODE_TXL
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
4981 {TGSI_OPCODE_BRK
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
4982 {TGSI_OPCODE_IF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
4984 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4985 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4986 {TGSI_OPCODE_ELSE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
4987 {TGSI_OPCODE_ENDIF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
4989 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4990 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4991 {TGSI_OPCODE_PUSHA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4992 {TGSI_OPCODE_POPA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4993 {TGSI_OPCODE_CEIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
4994 {TGSI_OPCODE_I2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
, tgsi_op2_trans
},
4995 {TGSI_OPCODE_NOT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT
, tgsi_op2
},
4996 {TGSI_OPCODE_TRUNC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_op2
},
4997 {TGSI_OPCODE_SHL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT
, tgsi_op2
},
4999 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5000 {TGSI_OPCODE_AND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT
, tgsi_op2
},
5001 {TGSI_OPCODE_OR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT
, tgsi_op2
},
5002 {TGSI_OPCODE_MOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_imod
},
5003 {TGSI_OPCODE_XOR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT
, tgsi_op2
},
5004 {TGSI_OPCODE_SAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5005 {TGSI_OPCODE_TXF
, 0, SQ_TEX_INST_LD
, tgsi_tex
},
5006 {TGSI_OPCODE_TXQ
, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO
, tgsi_tex
},
5007 {TGSI_OPCODE_CONT
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
5008 {TGSI_OPCODE_EMIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5009 {TGSI_OPCODE_ENDPRIM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5010 {TGSI_OPCODE_BGNLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
5011 {TGSI_OPCODE_BGNSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5012 {TGSI_OPCODE_ENDLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
5013 {TGSI_OPCODE_ENDSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5015 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5016 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5017 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5018 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5019 {TGSI_OPCODE_NOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5021 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5022 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5023 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5024 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5025 {TGSI_OPCODE_NRM4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5026 {TGSI_OPCODE_CALLNZ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5027 {TGSI_OPCODE_IFC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5028 {TGSI_OPCODE_BREAKC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5029 {TGSI_OPCODE_KIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
5030 {TGSI_OPCODE_END
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
5032 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5033 {TGSI_OPCODE_F2I
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
, tgsi_op2
},
5034 {TGSI_OPCODE_IDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_idiv
},
5035 {TGSI_OPCODE_IMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT
, tgsi_op2
},
5036 {TGSI_OPCODE_IMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT
, tgsi_op2
},
5037 {TGSI_OPCODE_INEG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
, tgsi_ineg
},
5038 {TGSI_OPCODE_ISGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT
, tgsi_op2
},
5039 {TGSI_OPCODE_ISHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT
, tgsi_op2
},
5040 {TGSI_OPCODE_ISLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT
, tgsi_op2_swap
},
5041 {TGSI_OPCODE_F2U
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
, tgsi_op2_trans
},
5042 {TGSI_OPCODE_U2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
, tgsi_op2_trans
},
5043 {TGSI_OPCODE_UADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
, tgsi_op2
},
5044 {TGSI_OPCODE_UDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_udiv
},
5045 {TGSI_OPCODE_UMAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_umad
},
5046 {TGSI_OPCODE_UMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT
, tgsi_op2
},
5047 {TGSI_OPCODE_UMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT
, tgsi_op2
},
5048 {TGSI_OPCODE_UMOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_umod
},
5049 {TGSI_OPCODE_UMUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
, tgsi_op2_trans
},
5050 {TGSI_OPCODE_USEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT
, tgsi_op2
},
5051 {TGSI_OPCODE_USGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
, tgsi_op2
},
5052 {TGSI_OPCODE_USHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT
, tgsi_op2
},
5053 {TGSI_OPCODE_USLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT
, tgsi_op2_swap
},
5054 {TGSI_OPCODE_USNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT
, tgsi_op2
},
5055 {TGSI_OPCODE_SWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5056 {TGSI_OPCODE_CASE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5057 {TGSI_OPCODE_DEFAULT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5058 {TGSI_OPCODE_ENDSWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5059 {TGSI_OPCODE_LOAD
, 0, 0, tgsi_unsupported
},
5060 {TGSI_OPCODE_LOAD_MS
, 0, 0, tgsi_unsupported
},
5061 {TGSI_OPCODE_SAMPLE
, 0, 0, tgsi_unsupported
},
5062 {TGSI_OPCODE_SAMPLE_B
, 0, 0, tgsi_unsupported
},
5063 {TGSI_OPCODE_SAMPLE_C
, 0, 0, tgsi_unsupported
},
5064 {TGSI_OPCODE_SAMPLE_C_LZ
, 0, 0, tgsi_unsupported
},
5065 {TGSI_OPCODE_SAMPLE_D
, 0, 0, tgsi_unsupported
},
5066 {TGSI_OPCODE_SAMPLE_L
, 0, 0, tgsi_unsupported
},
5067 {TGSI_OPCODE_GATHER4
, 0, 0, tgsi_unsupported
},
5068 {TGSI_OPCODE_RESINFO
, 0, 0, tgsi_unsupported
},
5069 {TGSI_OPCODE_SAMPLE_POS
, 0, 0, tgsi_unsupported
},
5070 {TGSI_OPCODE_SAMPLE_INFO
, 0, 0, tgsi_unsupported
},
5071 {TGSI_OPCODE_UARL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
, tgsi_eg_arl
},
5072 {TGSI_OPCODE_UCMP
, 0, 0, tgsi_unsupported
},
5073 {TGSI_OPCODE_IABS
, 0, 0, tgsi_iabs
},
5074 {TGSI_OPCODE_ISSG
, 0, 0, tgsi_issg
},
5075 {TGSI_OPCODE_LAST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5078 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction
[] = {
5079 {TGSI_OPCODE_ARL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
5080 {TGSI_OPCODE_MOV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
5081 {TGSI_OPCODE_LIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
5082 {TGSI_OPCODE_RCP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
, cayman_emit_float_instr
},
5083 {TGSI_OPCODE_RSQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
, cayman_emit_float_instr
},
5084 {TGSI_OPCODE_EXP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
5085 {TGSI_OPCODE_LOG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_log
},
5086 {TGSI_OPCODE_MUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
5087 {TGSI_OPCODE_ADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
5088 {TGSI_OPCODE_DP3
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5089 {TGSI_OPCODE_DP4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5090 {TGSI_OPCODE_DST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
5091 {TGSI_OPCODE_MIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
5092 {TGSI_OPCODE_MAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
5093 {TGSI_OPCODE_SLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
5094 {TGSI_OPCODE_SGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
5095 {TGSI_OPCODE_MAD
, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
5096 {TGSI_OPCODE_SUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
5097 {TGSI_OPCODE_LRP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
5098 {TGSI_OPCODE_CND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5100 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5101 {TGSI_OPCODE_DP2A
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5103 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5104 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5105 {TGSI_OPCODE_FRC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
5106 {TGSI_OPCODE_CLAMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5107 {TGSI_OPCODE_FLR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
5108 {TGSI_OPCODE_ROUND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE
, tgsi_op2
},
5109 {TGSI_OPCODE_EX2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, cayman_emit_float_instr
},
5110 {TGSI_OPCODE_LG2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, cayman_emit_float_instr
},
5111 {TGSI_OPCODE_POW
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, cayman_pow
},
5112 {TGSI_OPCODE_XPD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
5114 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5115 {TGSI_OPCODE_ABS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
5116 {TGSI_OPCODE_RCC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5117 {TGSI_OPCODE_DPH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5118 {TGSI_OPCODE_COS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, cayman_trig
},
5119 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
5120 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
5121 {TGSI_OPCODE_KILP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
5122 {TGSI_OPCODE_PK2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5123 {TGSI_OPCODE_PK2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5124 {TGSI_OPCODE_PK4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5125 {TGSI_OPCODE_PK4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5126 {TGSI_OPCODE_RFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5127 {TGSI_OPCODE_SEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
5128 {TGSI_OPCODE_SFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5129 {TGSI_OPCODE_SGT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
5130 {TGSI_OPCODE_SIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, cayman_trig
},
5131 {TGSI_OPCODE_SLE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
5132 {TGSI_OPCODE_SNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
5133 {TGSI_OPCODE_STR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5134 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
5135 {TGSI_OPCODE_TXD
, 0, SQ_TEX_INST_SAMPLE_G
, tgsi_tex
},
5136 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
5137 {TGSI_OPCODE_UP2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5138 {TGSI_OPCODE_UP2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5139 {TGSI_OPCODE_UP4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5140 {TGSI_OPCODE_UP4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5141 {TGSI_OPCODE_X2D
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5142 {TGSI_OPCODE_ARA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5143 {TGSI_OPCODE_ARR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
5144 {TGSI_OPCODE_BRA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5145 {TGSI_OPCODE_CAL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5146 {TGSI_OPCODE_RET
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5147 {TGSI_OPCODE_SSG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
5148 {TGSI_OPCODE_CMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
5149 {TGSI_OPCODE_SCS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
5150 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_LB
, tgsi_tex
},
5151 {TGSI_OPCODE_NRM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5152 {TGSI_OPCODE_DIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5153 {TGSI_OPCODE_DP2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5154 {TGSI_OPCODE_TXL
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
5155 {TGSI_OPCODE_BRK
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
5156 {TGSI_OPCODE_IF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
5158 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5159 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5160 {TGSI_OPCODE_ELSE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
5161 {TGSI_OPCODE_ENDIF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
5163 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5164 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5165 {TGSI_OPCODE_PUSHA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5166 {TGSI_OPCODE_POPA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5167 {TGSI_OPCODE_CEIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5168 {TGSI_OPCODE_I2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
, tgsi_op2
},
5169 {TGSI_OPCODE_NOT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT
, tgsi_op2
},
5170 {TGSI_OPCODE_TRUNC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_op2
},
5171 {TGSI_OPCODE_SHL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT
, tgsi_op2
},
5173 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5174 {TGSI_OPCODE_AND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT
, tgsi_op2
},
5175 {TGSI_OPCODE_OR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT
, tgsi_op2
},
5176 {TGSI_OPCODE_MOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_imod
},
5177 {TGSI_OPCODE_XOR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT
, tgsi_op2
},
5178 {TGSI_OPCODE_SAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5179 {TGSI_OPCODE_TXF
, 0, SQ_TEX_INST_LD
, tgsi_tex
},
5180 {TGSI_OPCODE_TXQ
, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO
, tgsi_tex
},
5181 {TGSI_OPCODE_CONT
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
5182 {TGSI_OPCODE_EMIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5183 {TGSI_OPCODE_ENDPRIM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5184 {TGSI_OPCODE_BGNLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
5185 {TGSI_OPCODE_BGNSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5186 {TGSI_OPCODE_ENDLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
5187 {TGSI_OPCODE_ENDSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5189 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5190 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5191 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5192 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5193 {TGSI_OPCODE_NOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5195 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5196 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5197 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5198 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5199 {TGSI_OPCODE_NRM4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5200 {TGSI_OPCODE_CALLNZ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5201 {TGSI_OPCODE_IFC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5202 {TGSI_OPCODE_BREAKC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5203 {TGSI_OPCODE_KIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
5204 {TGSI_OPCODE_END
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
5206 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5207 {TGSI_OPCODE_F2I
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
, tgsi_op2
},
5208 {TGSI_OPCODE_IDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_idiv
},
5209 {TGSI_OPCODE_IMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT
, tgsi_op2
},
5210 {TGSI_OPCODE_IMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT
, tgsi_op2
},
5211 {TGSI_OPCODE_INEG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
, tgsi_ineg
},
5212 {TGSI_OPCODE_ISGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT
, tgsi_op2
},
5213 {TGSI_OPCODE_ISHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT
, tgsi_op2
},
5214 {TGSI_OPCODE_ISLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT
, tgsi_op2_swap
},
5215 {TGSI_OPCODE_F2U
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
, tgsi_op2
},
5216 {TGSI_OPCODE_U2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
, tgsi_op2
},
5217 {TGSI_OPCODE_UADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
, tgsi_op2
},
5218 {TGSI_OPCODE_UDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_udiv
},
5219 {TGSI_OPCODE_UMAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_umad
},
5220 {TGSI_OPCODE_UMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT
, tgsi_op2
},
5221 {TGSI_OPCODE_UMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT
, tgsi_op2
},
5222 {TGSI_OPCODE_UMOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_umod
},
5223 {TGSI_OPCODE_UMUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT
, cayman_mul_int_instr
},
5224 {TGSI_OPCODE_USEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT
, tgsi_op2
},
5225 {TGSI_OPCODE_USGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
, tgsi_op2
},
5226 {TGSI_OPCODE_USHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT
, tgsi_op2
},
5227 {TGSI_OPCODE_USLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT
, tgsi_op2_swap
},
5228 {TGSI_OPCODE_USNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT
, tgsi_op2
},
5229 {TGSI_OPCODE_SWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5230 {TGSI_OPCODE_CASE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5231 {TGSI_OPCODE_DEFAULT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5232 {TGSI_OPCODE_ENDSWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5233 {TGSI_OPCODE_LOAD
, 0, 0, tgsi_unsupported
},
5234 {TGSI_OPCODE_LOAD_MS
, 0, 0, tgsi_unsupported
},
5235 {TGSI_OPCODE_SAMPLE
, 0, 0, tgsi_unsupported
},
5236 {TGSI_OPCODE_SAMPLE_B
, 0, 0, tgsi_unsupported
},
5237 {TGSI_OPCODE_SAMPLE_C
, 0, 0, tgsi_unsupported
},
5238 {TGSI_OPCODE_SAMPLE_C_LZ
, 0, 0, tgsi_unsupported
},
5239 {TGSI_OPCODE_SAMPLE_D
, 0, 0, tgsi_unsupported
},
5240 {TGSI_OPCODE_SAMPLE_L
, 0, 0, tgsi_unsupported
},
5241 {TGSI_OPCODE_GATHER4
, 0, 0, tgsi_unsupported
},
5242 {TGSI_OPCODE_RESINFO
, 0, 0, tgsi_unsupported
},
5243 {TGSI_OPCODE_SAMPLE_POS
, 0, 0, tgsi_unsupported
},
5244 {TGSI_OPCODE_SAMPLE_INFO
, 0, 0, tgsi_unsupported
},
5245 {TGSI_OPCODE_UARL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
, tgsi_eg_arl
},
5246 {TGSI_OPCODE_UCMP
, 0, 0, tgsi_unsupported
},
5247 {TGSI_OPCODE_IABS
, 0, 0, tgsi_iabs
},
5248 {TGSI_OPCODE_ISSG
, 0, 0, tgsi_issg
},
5249 {TGSI_OPCODE_LAST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},