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r600g: added literals where needed for POW instruction
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_screen.h"
29 #include "r600_context.h"
30 #include "r600_shader.h"
31 #include "r600_asm.h"
32 #include "r600_sq.h"
33 #include "r600d.h"
34 #include <stdio.h>
35 #include <errno.h>
36
37
38 struct r600_shader_tgsi_instruction;
39
40 struct r600_shader_ctx {
41 struct tgsi_shader_info info;
42 struct tgsi_parse_context parse;
43 const struct tgsi_token *tokens;
44 unsigned type;
45 unsigned file_offset[TGSI_FILE_COUNT];
46 unsigned temp_reg;
47 struct r600_shader_tgsi_instruction *inst_info;
48 struct r600_bc *bc;
49 struct r600_shader *shader;
50 u32 value[4];
51 };
52
53 struct r600_shader_tgsi_instruction {
54 unsigned tgsi_opcode;
55 unsigned is_op3;
56 unsigned r600_opcode;
57 int (*process)(struct r600_shader_ctx *ctx);
58 };
59
60 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[];
61 static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
62
63 static int r600_shader_update(struct pipe_context *ctx, struct r600_shader *shader)
64 {
65 struct r600_context *rctx = r600_context(ctx);
66 const struct util_format_description *desc;
67 enum pipe_format resource_format[160];
68 unsigned i, nresources = 0;
69 struct r600_bc *bc = &shader->bc;
70 struct r600_bc_cf *cf;
71 struct r600_bc_vtx *vtx;
72
73 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
74 return 0;
75 for (i = 0; i < rctx->vertex_elements->count; i++) {
76 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
77 }
78 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
79 switch (cf->inst) {
80 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
81 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
82 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
83 desc = util_format_description(resource_format[vtx->buffer_id]);
84 if (desc == NULL) {
85 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
86 return -EINVAL;
87 }
88 vtx->dst_sel_x = desc->swizzle[0];
89 vtx->dst_sel_y = desc->swizzle[1];
90 vtx->dst_sel_z = desc->swizzle[2];
91 vtx->dst_sel_w = desc->swizzle[3];
92 }
93 break;
94 default:
95 break;
96 }
97 }
98 return r600_bc_build(&shader->bc);
99 }
100
101 int r600_pipe_shader_create(struct pipe_context *ctx,
102 struct r600_context_state *rpshader,
103 const struct tgsi_token *tokens)
104 {
105 struct r600_screen *rscreen = r600_screen(ctx->screen);
106 int r;
107
108 //fprintf(stderr, "--------------------------------------------------------------\n");
109 //tgsi_dump(tokens, 0);
110 if (rpshader == NULL)
111 return -ENOMEM;
112 rpshader->shader.family = radeon_get_family(rscreen->rw);
113 r = r600_shader_from_tgsi(tokens, &rpshader->shader);
114 if (r) {
115 R600_ERR("translation from TGSI failed !\n");
116 return r;
117 }
118 r = r600_bc_build(&rpshader->shader.bc);
119 if (r) {
120 R600_ERR("building bytecode failed !\n");
121 return r;
122 }
123 //fprintf(stderr, "______________________________________________________________\n");
124 return 0;
125 }
126
127 static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_state *rpshader)
128 {
129 struct r600_screen *rscreen = r600_screen(ctx->screen);
130 struct r600_shader *rshader = &rpshader->shader;
131 struct radeon_state *state;
132 unsigned i, tmp;
133
134 rpshader->rstate = radeon_state_decref(rpshader->rstate);
135 state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
136 if (state == NULL)
137 return -ENOMEM;
138 for (i = 0; i < 10; i++) {
139 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
140 }
141 /* so far never got proper semantic id from tgsi */
142 for (i = 0; i < 32; i++) {
143 tmp = i << ((i & 3) * 8);
144 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp;
145 }
146 state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
147 state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
148 S_028868_STACK_SIZE(rshader->bc.nstack);
149 rpshader->rstate = state;
150 rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
151 rpshader->rstate->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
152 rpshader->rstate->nbo = 2;
153 rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
154 rpshader->rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
155 return radeon_state_pm4(state);
156 }
157
158 static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_state *rpshader)
159 {
160 const struct pipe_rasterizer_state *rasterizer;
161 struct r600_screen *rscreen = r600_screen(ctx->screen);
162 struct r600_shader *rshader = &rpshader->shader;
163 struct r600_context *rctx = r600_context(ctx);
164 struct radeon_state *state;
165 unsigned i, tmp, exports_ps, num_cout;
166
167 rasterizer = &rctx->rasterizer->state.rasterizer;
168 rpshader->rstate = radeon_state_decref(rpshader->rstate);
169 state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
170 if (state == NULL)
171 return -ENOMEM;
172 for (i = 0; i < rshader->ninput; i++) {
173 tmp = S_028644_SEMANTIC(i);
174 tmp |= S_028644_SEL_CENTROID(1);
175 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
176 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR) {
177 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
178 }
179 if (rasterizer->sprite_coord_enable & (1 << i)) {
180 tmp |= S_028644_PT_SPRITE_TEX(1);
181 }
182 state->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
183 }
184
185 exports_ps = 0;
186 num_cout = 0;
187 for (i = 0; i < rshader->noutput; i++) {
188 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
189 exports_ps |= 1;
190 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
191 exports_ps |= (1 << (num_cout+1));
192 num_cout++;
193 }
194 }
195 if (!exports_ps) {
196 /* always at least export 1 component per pixel */
197 exports_ps = 2;
198 }
199 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
200 S_0286CC_PERSP_GRADIENT_ENA(1);
201 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
202 state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
203 S_028868_STACK_SIZE(rshader->bc.nstack);
204 state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
205 rpshader->rstate = state;
206 rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
207 rpshader->rstate->nbo = 1;
208 rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
209 return radeon_state_pm4(state);
210 }
211
212 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_context_state *rpshader)
213 {
214 struct r600_screen *rscreen = r600_screen(ctx->screen);
215 struct r600_context *rctx = r600_context(ctx);
216 struct r600_shader *rshader = &rpshader->shader;
217 int r;
218
219 /* copy new shader */
220 radeon_bo_decref(rscreen->rw, rpshader->bo);
221 rpshader->bo = NULL;
222 rpshader->bo = radeon_bo(rscreen->rw, 0, rshader->bc.ndw * 4,
223 4096, NULL);
224 if (rpshader->bo == NULL) {
225 return -ENOMEM;
226 }
227 radeon_bo_map(rscreen->rw, rpshader->bo);
228 memcpy(rpshader->bo->data, rshader->bc.bytecode, rshader->bc.ndw * 4);
229 radeon_bo_unmap(rscreen->rw, rpshader->bo);
230 /* build state */
231 rshader->flat_shade = rctx->flat_shade;
232 switch (rshader->processor_type) {
233 case TGSI_PROCESSOR_VERTEX:
234 r = r600_pipe_shader_vs(ctx, rpshader);
235 break;
236 case TGSI_PROCESSOR_FRAGMENT:
237 r = r600_pipe_shader_ps(ctx, rpshader);
238 break;
239 default:
240 r = -EINVAL;
241 break;
242 }
243 return r;
244 }
245
246 int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_context_state *rpshader)
247 {
248 struct r600_context *rctx = r600_context(ctx);
249 int r;
250
251 if (rpshader == NULL)
252 return -EINVAL;
253 /* there should be enough input */
254 if (rctx->vertex_elements->count < rpshader->shader.bc.nresource) {
255 R600_ERR("%d resources provided, expecting %d\n",
256 rctx->vertex_elements->count, rpshader->shader.bc.nresource);
257 return -EINVAL;
258 }
259 r = r600_shader_update(ctx, &rpshader->shader);
260 if (r)
261 return r;
262 return r600_pipe_shader(ctx, rpshader);
263 }
264
265 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
266 {
267 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
268 int j;
269
270 if (i->Instruction.NumDstRegs > 1) {
271 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
272 return -EINVAL;
273 }
274 if (i->Instruction.Predicate) {
275 R600_ERR("predicate unsupported\n");
276 return -EINVAL;
277 }
278 #if 0
279 if (i->Instruction.Label) {
280 R600_ERR("label unsupported\n");
281 return -EINVAL;
282 }
283 #endif
284 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
285 if (i->Src[j].Register.Indirect ||
286 i->Src[j].Register.Dimension ||
287 i->Src[j].Register.Absolute) {
288 R600_ERR("unsupported src (indirect|dimension|absolute)\n");
289 return -EINVAL;
290 }
291 }
292 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
293 if (i->Dst[j].Register.Indirect || i->Dst[j].Register.Dimension) {
294 R600_ERR("unsupported dst (indirect|dimension)\n");
295 return -EINVAL;
296 }
297 }
298 return 0;
299 }
300
301 static int tgsi_declaration(struct r600_shader_ctx *ctx)
302 {
303 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
304 struct r600_bc_vtx vtx;
305 unsigned i;
306 int r;
307
308 switch (d->Declaration.File) {
309 case TGSI_FILE_INPUT:
310 i = ctx->shader->ninput++;
311 ctx->shader->input[i].name = d->Semantic.Name;
312 ctx->shader->input[i].sid = d->Semantic.Index;
313 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
314 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
315 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
316 /* turn input into fetch */
317 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
318 vtx.inst = 0;
319 vtx.fetch_type = 0;
320 vtx.buffer_id = i;
321 /* register containing the index into the buffer */
322 vtx.src_gpr = 0;
323 vtx.src_sel_x = 0;
324 vtx.mega_fetch_count = 0x1F;
325 vtx.dst_gpr = ctx->shader->input[i].gpr;
326 vtx.dst_sel_x = 0;
327 vtx.dst_sel_y = 1;
328 vtx.dst_sel_z = 2;
329 vtx.dst_sel_w = 3;
330 r = r600_bc_add_vtx(ctx->bc, &vtx);
331 if (r)
332 return r;
333 }
334 break;
335 case TGSI_FILE_OUTPUT:
336 i = ctx->shader->noutput++;
337 ctx->shader->output[i].name = d->Semantic.Name;
338 ctx->shader->output[i].sid = d->Semantic.Index;
339 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
340 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
341 break;
342 case TGSI_FILE_CONSTANT:
343 case TGSI_FILE_TEMPORARY:
344 case TGSI_FILE_SAMPLER:
345 break;
346 default:
347 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
348 return -EINVAL;
349 }
350 return 0;
351 }
352
353 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
354 {
355 struct tgsi_full_immediate *immediate;
356 struct r600_shader_ctx ctx;
357 struct r600_bc_output output[32];
358 unsigned output_done, noutput;
359 unsigned opcode;
360 int i, r = 0, pos0;
361
362 ctx.bc = &shader->bc;
363 ctx.shader = shader;
364 r = r600_bc_init(ctx.bc, shader->family);
365 if (r)
366 return r;
367 ctx.tokens = tokens;
368 tgsi_scan_shader(tokens, &ctx.info);
369 tgsi_parse_init(&ctx.parse, tokens);
370 ctx.type = ctx.parse.FullHeader.Processor.Processor;
371 shader->processor_type = ctx.type;
372
373 /* register allocations */
374 /* Values [0,127] correspond to GPR[0..127].
375 * Values [128,159] correspond to constant buffer bank 0
376 * Values [160,191] correspond to constant buffer bank 1
377 * Values [256,511] correspond to cfile constants c[0..255].
378 * Other special values are shown in the list below.
379 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
380 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
381 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
382 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
383 * 248 SQ_ALU_SRC_0: special constant 0.0.
384 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
385 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
386 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
387 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
388 * 253 SQ_ALU_SRC_LITERAL: literal constant.
389 * 254 SQ_ALU_SRC_PV: previous vector result.
390 * 255 SQ_ALU_SRC_PS: previous scalar result.
391 */
392 for (i = 0; i < TGSI_FILE_COUNT; i++) {
393 ctx.file_offset[i] = 0;
394 }
395 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
396 ctx.file_offset[TGSI_FILE_INPUT] = 1;
397 }
398 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
399 ctx.info.file_count[TGSI_FILE_INPUT];
400 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
401 ctx.info.file_count[TGSI_FILE_OUTPUT];
402 ctx.file_offset[TGSI_FILE_CONSTANT] = 256;
403 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
404 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
405 ctx.info.file_count[TGSI_FILE_TEMPORARY];
406
407 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
408 tgsi_parse_token(&ctx.parse);
409 switch (ctx.parse.FullToken.Token.Type) {
410 case TGSI_TOKEN_TYPE_IMMEDIATE:
411 immediate = &ctx.parse.FullToken.FullImmediate;
412 ctx.value[0] = immediate->u[0].Uint;
413 ctx.value[1] = immediate->u[1].Uint;
414 ctx.value[2] = immediate->u[2].Uint;
415 ctx.value[3] = immediate->u[3].Uint;
416 break;
417 case TGSI_TOKEN_TYPE_DECLARATION:
418 r = tgsi_declaration(&ctx);
419 if (r)
420 goto out_err;
421 break;
422 case TGSI_TOKEN_TYPE_INSTRUCTION:
423 r = tgsi_is_supported(&ctx);
424 if (r)
425 goto out_err;
426 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
427 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
428 r = ctx.inst_info->process(&ctx);
429 if (r)
430 goto out_err;
431 r = r600_bc_add_literal(ctx.bc, ctx.value);
432 if (r)
433 goto out_err;
434 break;
435 default:
436 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
437 r = -EINVAL;
438 goto out_err;
439 }
440 }
441 /* export output */
442 noutput = shader->noutput;
443 for (i = 0, pos0 = 0; i < noutput; i++) {
444 memset(&output[i], 0, sizeof(struct r600_bc_output));
445 output[i].gpr = shader->output[i].gpr;
446 output[i].elem_size = 3;
447 output[i].swizzle_x = 0;
448 output[i].swizzle_y = 1;
449 output[i].swizzle_z = 2;
450 output[i].swizzle_w = 3;
451 output[i].barrier = 1;
452 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
453 output[i].array_base = i - pos0;
454 output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
455 switch (ctx.type) {
456 case TGSI_PROCESSOR_VERTEX:
457 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
458 output[i].array_base = 60;
459 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
460 /* position doesn't count in array_base */
461 pos0++;
462 }
463 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
464 output[i].array_base = 61;
465 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
466 /* position doesn't count in array_base */
467 pos0++;
468 }
469 break;
470 case TGSI_PROCESSOR_FRAGMENT:
471 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
472 output[i].array_base = shader->output[i].sid;
473 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
474 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
475 output[i].array_base = 61;
476 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
477 } else {
478 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
479 r = -EINVAL;
480 goto out_err;
481 }
482 break;
483 default:
484 R600_ERR("unsupported processor type %d\n", ctx.type);
485 r = -EINVAL;
486 goto out_err;
487 }
488 }
489 /* add fake param output for vertex shader if no param is exported */
490 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
491 for (i = 0, pos0 = 0; i < noutput; i++) {
492 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
493 pos0 = 1;
494 break;
495 }
496 }
497 if (!pos0) {
498 memset(&output[i], 0, sizeof(struct r600_bc_output));
499 output[i].gpr = 0;
500 output[i].elem_size = 3;
501 output[i].swizzle_x = 0;
502 output[i].swizzle_y = 1;
503 output[i].swizzle_z = 2;
504 output[i].swizzle_w = 3;
505 output[i].barrier = 1;
506 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
507 output[i].array_base = 0;
508 output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
509 noutput++;
510 }
511 }
512 /* add fake pixel export */
513 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
514 memset(&output[0], 0, sizeof(struct r600_bc_output));
515 output[0].gpr = 0;
516 output[0].elem_size = 3;
517 output[0].swizzle_x = 7;
518 output[0].swizzle_y = 7;
519 output[0].swizzle_z = 7;
520 output[0].swizzle_w = 7;
521 output[0].barrier = 1;
522 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
523 output[0].array_base = 0;
524 output[0].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
525 noutput++;
526 }
527 /* set export done on last export of each type */
528 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
529 if (i == (noutput - 1)) {
530 output[i].end_of_program = 1;
531 }
532 if (!(output_done & (1 << output[i].type))) {
533 output_done |= (1 << output[i].type);
534 output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE;
535 }
536 }
537 /* add output to bytecode */
538 for (i = 0; i < noutput; i++) {
539 r = r600_bc_add_output(ctx.bc, &output[i]);
540 if (r)
541 goto out_err;
542 }
543 tgsi_parse_free(&ctx.parse);
544 return 0;
545 out_err:
546 tgsi_parse_free(&ctx.parse);
547 return r;
548 }
549
550 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
551 {
552 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
553 return -EINVAL;
554 }
555
556 static int tgsi_end(struct r600_shader_ctx *ctx)
557 {
558 return 0;
559 }
560
561 static int tgsi_src(struct r600_shader_ctx *ctx,
562 const struct tgsi_full_src_register *tgsi_src,
563 struct r600_bc_alu_src *r600_src)
564 {
565 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
566 r600_src->sel = tgsi_src->Register.Index;
567 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
568 r600_src->sel = 0;
569 }
570 r600_src->neg = tgsi_src->Register.Negate;
571 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
572 return 0;
573 }
574
575 static int tgsi_dst(struct r600_shader_ctx *ctx,
576 const struct tgsi_full_dst_register *tgsi_dst,
577 unsigned swizzle,
578 struct r600_bc_alu_dst *r600_dst)
579 {
580 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
581
582 r600_dst->sel = tgsi_dst->Register.Index;
583 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
584 r600_dst->chan = swizzle;
585 r600_dst->write = 1;
586 if (inst->Instruction.Saturate) {
587 r600_dst->clamp = 1;
588 }
589 return 0;
590 }
591
592 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
593 {
594 switch (swizzle) {
595 case 0:
596 return tgsi_src->Register.SwizzleX;
597 case 1:
598 return tgsi_src->Register.SwizzleY;
599 case 2:
600 return tgsi_src->Register.SwizzleZ;
601 case 3:
602 return tgsi_src->Register.SwizzleW;
603 default:
604 return 0;
605 }
606 }
607
608 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
609 {
610 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
611 struct r600_bc_alu alu;
612 int i, j, k, nconst, r;
613
614 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
615 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
616 nconst++;
617 }
618 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
619 if (r) {
620 return r;
621 }
622 }
623 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
624 if (inst->Src[j].Register.File == TGSI_FILE_CONSTANT && j > 0) {
625 for (k = 0; k < 4; k++) {
626 memset(&alu, 0, sizeof(struct r600_bc_alu));
627 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
628 alu.src[0].sel = r600_src[0].sel;
629 alu.src[0].chan = k;
630 alu.dst.sel = ctx->temp_reg + j;
631 alu.dst.chan = k;
632 alu.dst.write = 1;
633 if (k == 3)
634 alu.last = 1;
635 r = r600_bc_add_alu(ctx->bc, &alu);
636 if (r)
637 return r;
638 }
639 r600_src[0].sel = ctx->temp_reg + j;
640 j--;
641 }
642 }
643 return 0;
644 }
645
646 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
647 {
648 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
649 struct r600_bc_alu_src r600_src[3];
650 struct r600_bc_alu alu;
651 int i, j, r;
652 int lasti = 0;
653
654 for (i = 0; i < 4; i++) {
655 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
656 lasti = i;
657 }
658 }
659
660 r = tgsi_split_constant(ctx, r600_src);
661 if (r)
662 return r;
663 for (i = 0; i < lasti + 1; i++) {
664 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
665 continue;
666
667 memset(&alu, 0, sizeof(struct r600_bc_alu));
668 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
669 if (r)
670 return r;
671
672 alu.inst = ctx->inst_info->r600_opcode;
673 if (!swap) {
674 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
675 alu.src[j] = r600_src[j];
676 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
677 }
678 } else {
679 alu.src[0] = r600_src[1];
680 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
681
682 alu.src[1] = r600_src[0];
683 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
684 }
685 /* handle some special cases */
686 switch (ctx->inst_info->tgsi_opcode) {
687 case TGSI_OPCODE_SUB:
688 alu.src[1].neg = 1;
689 break;
690 case TGSI_OPCODE_ABS:
691 alu.src[0].abs = 1;
692 break;
693 default:
694 break;
695 }
696 if (i == lasti) {
697 alu.last = 1;
698 }
699 r = r600_bc_add_alu(ctx->bc, &alu);
700 if (r)
701 return r;
702 }
703 return 0;
704 }
705
706 static int tgsi_op2(struct r600_shader_ctx *ctx)
707 {
708 return tgsi_op2_s(ctx, 0);
709 }
710
711 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
712 {
713 return tgsi_op2_s(ctx, 1);
714 }
715
716 /*
717 * r600 - trunc to -PI..PI range
718 * r700 - normalize by dividing by 2PI
719 * see fdo bug 27901
720 */
721 static int tgsi_trig(struct r600_shader_ctx *ctx)
722 {
723 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
724 struct r600_bc_alu_src r600_src[3];
725 struct r600_bc_alu alu;
726 int i, r;
727 uint32_t lit_vals[4];
728
729 memset(lit_vals, 0, 4*4);
730 r = tgsi_split_constant(ctx, r600_src);
731 if (r)
732 return r;
733 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
734 lit_vals[1] = fui(0.5f);
735
736 memset(&alu, 0, sizeof(struct r600_bc_alu));
737 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
738 alu.is_op3 = 1;
739
740 alu.dst.chan = 0;
741 alu.dst.sel = ctx->temp_reg;
742 alu.dst.write = 1;
743
744 alu.src[0] = r600_src[0];
745 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
746
747 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
748 alu.src[1].chan = 0;
749 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
750 alu.src[2].chan = 1;
751 alu.last = 1;
752 r = r600_bc_add_alu(ctx->bc, &alu);
753 if (r)
754 return r;
755 r = r600_bc_add_literal(ctx->bc, lit_vals);
756 if (r)
757 return r;
758
759 memset(&alu, 0, sizeof(struct r600_bc_alu));
760 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT;
761
762 alu.dst.chan = 0;
763 alu.dst.sel = ctx->temp_reg;
764 alu.dst.write = 1;
765
766 alu.src[0].sel = ctx->temp_reg;
767 alu.src[0].chan = 0;
768 alu.last = 1;
769 r = r600_bc_add_alu(ctx->bc, &alu);
770 if (r)
771 return r;
772
773 if (ctx->bc->chiprev == 0) {
774 lit_vals[0] = fui(3.1415926535897f * 2.0f);
775 lit_vals[1] = fui(-3.1415926535897f);
776 } else {
777 lit_vals[0] = fui(1.0f);
778 lit_vals[1] = fui(-0.5f);
779 }
780
781 memset(&alu, 0, sizeof(struct r600_bc_alu));
782 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
783 alu.is_op3 = 1;
784
785 alu.dst.chan = 0;
786 alu.dst.sel = ctx->temp_reg;
787 alu.dst.write = 1;
788
789 alu.src[0].sel = ctx->temp_reg;
790 alu.src[0].chan = 0;
791
792 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
793 alu.src[1].chan = 0;
794 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
795 alu.src[2].chan = 1;
796 alu.last = 1;
797 r = r600_bc_add_alu(ctx->bc, &alu);
798 if (r)
799 return r;
800 r = r600_bc_add_literal(ctx->bc, lit_vals);
801 if (r)
802 return r;
803
804 memset(&alu, 0, sizeof(struct r600_bc_alu));
805 alu.inst = ctx->inst_info->r600_opcode;
806 alu.dst.chan = 0;
807 alu.dst.sel = ctx->temp_reg;
808 alu.dst.write = 1;
809
810 alu.src[0].sel = ctx->temp_reg;
811 alu.src[0].chan = 0;
812 alu.last = 1;
813 r = r600_bc_add_alu(ctx->bc, &alu);
814 if (r)
815 return r;
816
817 /* replicate result */
818 for (i = 0; i < 4; i++) {
819 memset(&alu, 0, sizeof(struct r600_bc_alu));
820 alu.src[0].sel = ctx->temp_reg;
821 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
822 alu.dst.chan = i;
823 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
824 if (r)
825 return r;
826 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
827 if (i == 3)
828 alu.last = 1;
829 r = r600_bc_add_alu(ctx->bc, &alu);
830 if (r)
831 return r;
832 }
833 return 0;
834 }
835
836 static int tgsi_kill(struct r600_shader_ctx *ctx)
837 {
838 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
839 struct r600_bc_alu alu;
840 int i, r;
841
842 for (i = 0; i < 4; i++) {
843 memset(&alu, 0, sizeof(struct r600_bc_alu));
844 alu.inst = ctx->inst_info->r600_opcode;
845 alu.dst.chan = i;
846 alu.src[0].sel = V_SQ_ALU_SRC_0;
847 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
848 if (r)
849 return r;
850 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
851 if (i == 3) {
852 alu.last = 1;
853 }
854 r = r600_bc_add_alu(ctx->bc, &alu);
855 if (r)
856 return r;
857 }
858 return 0;
859 }
860
861 static int tgsi_lit(struct r600_shader_ctx *ctx)
862 {
863 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
864 struct r600_bc_alu alu;
865 int r;
866
867 /* dst.x, <- 1.0 */
868 memset(&alu, 0, sizeof(struct r600_bc_alu));
869 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
870 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
871 alu.src[0].chan = 0;
872 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
873 if (r)
874 return r;
875 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
876 r = r600_bc_add_alu(ctx->bc, &alu);
877 if (r)
878 return r;
879
880 /* dst.y = max(src.x, 0.0) */
881 memset(&alu, 0, sizeof(struct r600_bc_alu));
882 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX;
883 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
884 if (r)
885 return r;
886 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
887 alu.src[1].chan = tgsi_chan(&inst->Src[0], 0);
888 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
889 if (r)
890 return r;
891 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
892 r = r600_bc_add_alu(ctx->bc, &alu);
893 if (r)
894 return r;
895
896 /* dst.z = NOP - fill Z slot */
897 memset(&alu, 0, sizeof(struct r600_bc_alu));
898 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
899 alu.dst.chan = 2;
900 r = r600_bc_add_alu(ctx->bc, &alu);
901 if (r)
902 return r;
903
904 /* dst.w, <- 1.0 */
905 memset(&alu, 0, sizeof(struct r600_bc_alu));
906 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
907 alu.src[0].sel = V_SQ_ALU_SRC_1;
908 alu.src[0].chan = 0;
909 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
910 if (r)
911 return r;
912 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
913 alu.last = 1;
914 r = r600_bc_add_alu(ctx->bc, &alu);
915 if (r)
916 return r;
917
918 if (inst->Dst[0].Register.WriteMask & (1 << 2))
919 {
920 int chan;
921 int sel;
922
923 /* dst.z = log(src.y) */
924 memset(&alu, 0, sizeof(struct r600_bc_alu));
925 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED;
926 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
927 if (r)
928 return r;
929 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
930 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
931 if (r)
932 return r;
933 alu.last = 1;
934 r = r600_bc_add_alu(ctx->bc, &alu);
935 if (r)
936 return r;
937
938 chan = alu.dst.chan;
939 sel = alu.dst.sel;
940
941 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
942 memset(&alu, 0, sizeof(struct r600_bc_alu));
943 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
944 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
945 if (r)
946 return r;
947 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
948 alu.src[1].sel = sel;
949 alu.src[1].chan = chan;
950 r = tgsi_src(ctx, &inst->Src[0], &alu.src[2]);
951 if (r)
952 return r;
953 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
954 alu.dst.sel = ctx->temp_reg;
955 alu.dst.chan = 0;
956 alu.dst.write = 1;
957 alu.is_op3 = 1;
958 alu.last = 1;
959 r = r600_bc_add_alu(ctx->bc, &alu);
960 if (r)
961 return r;
962
963 /* dst.z = exp(tmp.x) */
964 memset(&alu, 0, sizeof(struct r600_bc_alu));
965 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
966 alu.src[0].sel = ctx->temp_reg;
967 alu.src[0].chan = 0;
968 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
969 if (r)
970 return r;
971 alu.last = 1;
972 r = r600_bc_add_alu(ctx->bc, &alu);
973 if (r)
974 return r;
975 }
976 return 0;
977 }
978
979 static int tgsi_trans(struct r600_shader_ctx *ctx)
980 {
981 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
982 struct r600_bc_alu alu;
983 int i, j, r;
984
985 for (i = 0; i < 4; i++) {
986 memset(&alu, 0, sizeof(struct r600_bc_alu));
987 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
988 alu.inst = ctx->inst_info->r600_opcode;
989 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
990 r = tgsi_src(ctx, &inst->Src[j], &alu.src[j]);
991 if (r)
992 return r;
993 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
994 }
995 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
996 if (r)
997 return r;
998 alu.last = 1;
999 r = r600_bc_add_alu(ctx->bc, &alu);
1000 if (r)
1001 return r;
1002 }
1003 }
1004 return 0;
1005 }
1006
1007 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1008 {
1009 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1010 struct r600_bc_alu alu;
1011 int i, r;
1012
1013 for (i = 0; i < 4; i++) {
1014 memset(&alu, 0, sizeof(struct r600_bc_alu));
1015 alu.src[0].sel = ctx->temp_reg;
1016 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
1017 alu.dst.chan = i;
1018 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1019 if (r)
1020 return r;
1021 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1022 if (i == 3)
1023 alu.last = 1;
1024 r = r600_bc_add_alu(ctx->bc, &alu);
1025 if (r)
1026 return r;
1027 }
1028 return 0;
1029 }
1030
1031 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1032 {
1033 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1034 struct r600_bc_alu alu;
1035 int i, r;
1036
1037 memset(&alu, 0, sizeof(struct r600_bc_alu));
1038 alu.inst = ctx->inst_info->r600_opcode;
1039 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1040 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1041 if (r)
1042 return r;
1043 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1044 }
1045 alu.dst.sel = ctx->temp_reg;
1046 alu.dst.write = 1;
1047 alu.last = 1;
1048 r = r600_bc_add_alu(ctx->bc, &alu);
1049 if (r)
1050 return r;
1051 /* replicate result */
1052 return tgsi_helper_tempx_replicate(ctx);
1053 }
1054
1055 static int tgsi_pow(struct r600_shader_ctx *ctx)
1056 {
1057 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1058 struct r600_bc_alu alu;
1059 int r;
1060
1061 /* LOG2(a) */
1062 memset(&alu, 0, sizeof(struct r600_bc_alu));
1063 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE;
1064 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1065 if (r)
1066 return r;
1067 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1068 alu.dst.sel = ctx->temp_reg;
1069 alu.dst.write = 1;
1070 alu.last = 1;
1071 r = r600_bc_add_alu(ctx->bc, &alu);
1072 if (r)
1073 return r;
1074 r = r600_bc_add_literal(ctx->bc,ctx->value);
1075 if (r)
1076 return r;
1077 /* b * LOG2(a) */
1078 memset(&alu, 0, sizeof(struct r600_bc_alu));
1079 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE;
1080 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1081 if (r)
1082 return r;
1083 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1084 alu.src[1].sel = ctx->temp_reg;
1085 alu.dst.sel = ctx->temp_reg;
1086 alu.dst.write = 1;
1087 alu.last = 1;
1088 r = r600_bc_add_alu(ctx->bc, &alu);
1089 if (r)
1090 return r;
1091 r = r600_bc_add_literal(ctx->bc,ctx->value);
1092 if (r)
1093 return r;
1094 /* POW(a,b) = EXP2(b * LOG2(a))*/
1095 memset(&alu, 0, sizeof(struct r600_bc_alu));
1096 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
1097 alu.src[0].sel = ctx->temp_reg;
1098 alu.dst.sel = ctx->temp_reg;
1099 alu.dst.write = 1;
1100 alu.last = 1;
1101 r = r600_bc_add_alu(ctx->bc, &alu);
1102 if (r)
1103 return r;
1104 r = r600_bc_add_literal(ctx->bc,ctx->value);
1105 if (r)
1106 return r;
1107 return tgsi_helper_tempx_replicate(ctx);
1108 }
1109
1110 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1111 {
1112 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1113 struct r600_bc_alu alu;
1114 struct r600_bc_alu_src r600_src[3];
1115 int i, r;
1116
1117 r = tgsi_split_constant(ctx, r600_src);
1118 if (r)
1119 return r;
1120
1121 /* tmp = (src > 0 ? 1 : src) */
1122 for (i = 0; i < 4; i++) {
1123 memset(&alu, 0, sizeof(struct r600_bc_alu));
1124 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT;
1125 alu.is_op3 = 1;
1126 alu.dst.sel = ctx->temp_reg;
1127 alu.dst.write = 1;
1128
1129 alu.src[0] = r600_src[0];
1130 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1131
1132 alu.src[1].sel = V_SQ_ALU_SRC_1;
1133
1134 alu.src[2] = r600_src[0];
1135 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1136 if (i == 3)
1137 alu.last = 1;
1138 r = r600_bc_add_alu(ctx->bc, &alu);
1139 if (r)
1140 return r;
1141 }
1142
1143 /* dst = (-tmp > 0 ? -1 : tmp) */
1144 for (i = 0; i < 4; i++) {
1145 memset(&alu, 0, sizeof(struct r600_bc_alu));
1146 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT;
1147 alu.is_op3 = 1;
1148 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1149 if (r)
1150 return r;
1151
1152 alu.src[0].sel = ctx->temp_reg;
1153 alu.src[0].neg = 1;
1154
1155 alu.src[1].sel = V_SQ_ALU_SRC_1;
1156 alu.src[1].neg = 1;
1157
1158 alu.src[2].sel = ctx->temp_reg;
1159
1160 alu.dst.write = 1;
1161 if (i == 3)
1162 alu.last = 1;
1163 r = r600_bc_add_alu(ctx->bc, &alu);
1164 if (r)
1165 return r;
1166 }
1167 return 0;
1168 }
1169
1170 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1171 {
1172 struct r600_bc_alu alu;
1173 int i, r;
1174
1175 r = r600_bc_add_literal(ctx->bc, ctx->value);
1176 if (r)
1177 return r;
1178 for (i = 0; i < 4; i++) {
1179 memset(&alu, 0, sizeof(struct r600_bc_alu));
1180 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1181 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
1182 alu.dst.chan = i;
1183 } else {
1184 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
1185 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1186 if (r)
1187 return r;
1188 alu.src[0].sel = ctx->temp_reg;
1189 alu.src[0].chan = i;
1190 }
1191 if (i == 3) {
1192 alu.last = 1;
1193 }
1194 r = r600_bc_add_alu(ctx->bc, &alu);
1195 if (r)
1196 return r;
1197 }
1198 return 0;
1199 }
1200
1201 static int tgsi_op3(struct r600_shader_ctx *ctx)
1202 {
1203 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1204 struct r600_bc_alu_src r600_src[3];
1205 struct r600_bc_alu alu;
1206 int i, j, r;
1207
1208 r = tgsi_split_constant(ctx, r600_src);
1209 if (r)
1210 return r;
1211 /* do it in 2 step as op3 doesn't support writemask */
1212 for (i = 0; i < 4; i++) {
1213 memset(&alu, 0, sizeof(struct r600_bc_alu));
1214 alu.inst = ctx->inst_info->r600_opcode;
1215 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1216 alu.src[j] = r600_src[j];
1217 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1218 }
1219 alu.dst.sel = ctx->temp_reg;
1220 alu.dst.chan = i;
1221 alu.dst.write = 1;
1222 alu.is_op3 = 1;
1223 if (i == 3) {
1224 alu.last = 1;
1225 }
1226 r = r600_bc_add_alu(ctx->bc, &alu);
1227 if (r)
1228 return r;
1229 }
1230 return tgsi_helper_copy(ctx, inst);
1231 }
1232
1233 static int tgsi_dp(struct r600_shader_ctx *ctx)
1234 {
1235 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1236 struct r600_bc_alu_src r600_src[3];
1237 struct r600_bc_alu alu;
1238 int i, j, r;
1239
1240 r = tgsi_split_constant(ctx, r600_src);
1241 if (r)
1242 return r;
1243 for (i = 0; i < 4; i++) {
1244 memset(&alu, 0, sizeof(struct r600_bc_alu));
1245 alu.inst = ctx->inst_info->r600_opcode;
1246 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1247 alu.src[j] = r600_src[j];
1248 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1249 }
1250 alu.dst.sel = ctx->temp_reg;
1251 alu.dst.chan = i;
1252 alu.dst.write = 1;
1253 /* handle some special cases */
1254 switch (ctx->inst_info->tgsi_opcode) {
1255 case TGSI_OPCODE_DP2:
1256 if (i > 1) {
1257 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1258 alu.src[0].chan = alu.src[1].chan = 0;
1259 }
1260 break;
1261 case TGSI_OPCODE_DP3:
1262 if (i > 2) {
1263 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1264 alu.src[0].chan = alu.src[1].chan = 0;
1265 }
1266 break;
1267 case TGSI_OPCODE_DPH:
1268 if (i == 3) {
1269 alu.src[0].sel = V_SQ_ALU_SRC_1;
1270 alu.src[0].chan = 0;
1271 alu.src[0].neg = 0;
1272 }
1273 break;
1274 default:
1275 break;
1276 }
1277 if (i == 3) {
1278 alu.last = 1;
1279 }
1280 r = r600_bc_add_alu(ctx->bc, &alu);
1281 if (r)
1282 return r;
1283 }
1284 return tgsi_helper_copy(ctx, inst);
1285 }
1286
1287 static int tgsi_tex(struct r600_shader_ctx *ctx)
1288 {
1289 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1290 struct r600_bc_tex tex;
1291 struct r600_bc_alu alu;
1292 unsigned src_gpr;
1293 int r, i;
1294
1295 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1296
1297 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1298 /* Add perspective divide */
1299 memset(&alu, 0, sizeof(struct r600_bc_alu));
1300 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE;
1301 alu.src[0].sel = src_gpr;
1302 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1303 alu.dst.sel = ctx->temp_reg;
1304 alu.dst.chan = 3;
1305 alu.last = 1;
1306 alu.dst.write = 1;
1307 r = r600_bc_add_alu(ctx->bc, &alu);
1308 if (r)
1309 return r;
1310
1311 for (i = 0; i < 3; i++) {
1312 memset(&alu, 0, sizeof(struct r600_bc_alu));
1313 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
1314 alu.src[0].sel = ctx->temp_reg;
1315 alu.src[0].chan = 3;
1316 alu.src[1].sel = src_gpr;
1317 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1318 alu.dst.sel = ctx->temp_reg;
1319 alu.dst.chan = i;
1320 alu.dst.write = 1;
1321 r = r600_bc_add_alu(ctx->bc, &alu);
1322 if (r)
1323 return r;
1324 }
1325 memset(&alu, 0, sizeof(struct r600_bc_alu));
1326 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
1327 alu.src[0].sel = V_SQ_ALU_SRC_1;
1328 alu.src[0].chan = 0;
1329 alu.dst.sel = ctx->temp_reg;
1330 alu.dst.chan = 3;
1331 alu.last = 1;
1332 alu.dst.write = 1;
1333 r = r600_bc_add_alu(ctx->bc, &alu);
1334 if (r)
1335 return r;
1336 src_gpr = ctx->temp_reg;
1337 } else if (inst->Src[0].Register.File != TGSI_FILE_TEMPORARY) {
1338 for (i = 0; i < 4; i++) {
1339 memset(&alu, 0, sizeof(struct r600_bc_alu));
1340 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
1341 alu.src[0].sel = src_gpr;
1342 alu.src[0].chan = i;
1343 alu.dst.sel = ctx->temp_reg;
1344 alu.dst.chan = i;
1345 if (i == 3)
1346 alu.last = 1;
1347 alu.dst.write = 1;
1348 r = r600_bc_add_alu(ctx->bc, &alu);
1349 if (r)
1350 return r;
1351 }
1352 src_gpr = ctx->temp_reg;
1353 }
1354
1355 memset(&tex, 0, sizeof(struct r600_bc_tex));
1356 tex.inst = ctx->inst_info->r600_opcode;
1357 tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1358 tex.sampler_id = tex.resource_id;
1359 tex.src_gpr = src_gpr;
1360 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1361 tex.dst_sel_x = 0;
1362 tex.dst_sel_y = 1;
1363 tex.dst_sel_z = 2;
1364 tex.dst_sel_w = 3;
1365 tex.src_sel_x = 0;
1366 tex.src_sel_y = 1;
1367 tex.src_sel_z = 2;
1368 tex.src_sel_w = 3;
1369
1370 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1371 tex.coord_type_x = 1;
1372 tex.coord_type_y = 1;
1373 tex.coord_type_z = 1;
1374 tex.coord_type_w = 1;
1375 }
1376 return r600_bc_add_tex(ctx->bc, &tex);
1377 }
1378
1379 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1380 {
1381 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1382 struct r600_bc_alu_src r600_src[3];
1383 struct r600_bc_alu alu;
1384 unsigned i;
1385 int r;
1386
1387 r = tgsi_split_constant(ctx, r600_src);
1388 if (r)
1389 return r;
1390 /* 1 - src0 */
1391 for (i = 0; i < 4; i++) {
1392 memset(&alu, 0, sizeof(struct r600_bc_alu));
1393 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD;
1394 alu.src[0].sel = V_SQ_ALU_SRC_1;
1395 alu.src[0].chan = 0;
1396 alu.src[1] = r600_src[0];
1397 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1398 alu.src[1].neg = 1;
1399 alu.dst.sel = ctx->temp_reg;
1400 alu.dst.chan = i;
1401 if (i == 3) {
1402 alu.last = 1;
1403 }
1404 alu.dst.write = 1;
1405 r = r600_bc_add_alu(ctx->bc, &alu);
1406 if (r)
1407 return r;
1408 }
1409 r = r600_bc_add_literal(ctx->bc, ctx->value);
1410 if (r)
1411 return r;
1412
1413 /* (1 - src0) * src2 */
1414 for (i = 0; i < 4; i++) {
1415 memset(&alu, 0, sizeof(struct r600_bc_alu));
1416 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
1417 alu.src[0].sel = ctx->temp_reg;
1418 alu.src[0].chan = i;
1419 alu.src[1] = r600_src[2];
1420 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1421 alu.dst.sel = ctx->temp_reg;
1422 alu.dst.chan = i;
1423 if (i == 3) {
1424 alu.last = 1;
1425 }
1426 alu.dst.write = 1;
1427 r = r600_bc_add_alu(ctx->bc, &alu);
1428 if (r)
1429 return r;
1430 }
1431 r = r600_bc_add_literal(ctx->bc, ctx->value);
1432 if (r)
1433 return r;
1434
1435 /* src0 * src1 + (1 - src0) * src2 */
1436 for (i = 0; i < 4; i++) {
1437 memset(&alu, 0, sizeof(struct r600_bc_alu));
1438 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
1439 alu.is_op3 = 1;
1440 alu.src[0] = r600_src[0];
1441 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1442 alu.src[1] = r600_src[1];
1443 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1444 alu.src[2].sel = ctx->temp_reg;
1445 alu.src[2].chan = i;
1446 alu.dst.sel = ctx->temp_reg;
1447 alu.dst.chan = i;
1448 if (i == 3) {
1449 alu.last = 1;
1450 }
1451 r = r600_bc_add_alu(ctx->bc, &alu);
1452 if (r)
1453 return r;
1454 }
1455 return tgsi_helper_copy(ctx, inst);
1456 }
1457
1458 static int tgsi_cmp(struct r600_shader_ctx *ctx)
1459 {
1460 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1461 struct r600_bc_alu_src r600_src[3];
1462 struct r600_bc_alu alu;
1463 int use_temp = 0;
1464 int i, r;
1465
1466 r = tgsi_split_constant(ctx, r600_src);
1467 if (r)
1468 return r;
1469
1470 if (inst->Dst[0].Register.WriteMask != 0xf)
1471 use_temp = 1;
1472
1473 for (i = 0; i < 4; i++) {
1474 memset(&alu, 0, sizeof(struct r600_bc_alu));
1475 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE;
1476 alu.src[0] = r600_src[0];
1477 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1478
1479 alu.src[1] = r600_src[2];
1480 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1481
1482 alu.src[2] = r600_src[1];
1483 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
1484
1485 if (use_temp)
1486 alu.dst.sel = ctx->temp_reg;
1487 else {
1488 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1489 if (r)
1490 return r;
1491 }
1492 alu.dst.chan = i;
1493 alu.dst.write = 1;
1494 alu.is_op3 = 1;
1495 if (i == 3)
1496 alu.last = 1;
1497 r = r600_bc_add_alu(ctx->bc, &alu);
1498 if (r)
1499 return r;
1500 }
1501 if (use_temp)
1502 return tgsi_helper_copy(ctx, inst);
1503 return 0;
1504 }
1505
1506 static int tgsi_xpd(struct r600_shader_ctx *ctx)
1507 {
1508 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1509 struct r600_bc_alu_src r600_src[3];
1510 struct r600_bc_alu alu;
1511 uint32_t use_temp = 0;
1512 int i, r;
1513
1514 if (inst->Dst[0].Register.WriteMask != 0xf)
1515 use_temp = 1;
1516
1517 r = tgsi_split_constant(ctx, r600_src);
1518 if (r)
1519 return r;
1520
1521 for (i = 0; i < 4; i++) {
1522 memset(&alu, 0, sizeof(struct r600_bc_alu));
1523 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
1524
1525 alu.src[0] = r600_src[0];
1526 switch (i) {
1527 case 0:
1528 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
1529 break;
1530 case 1:
1531 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1532 break;
1533 case 2:
1534 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1535 break;
1536 case 3:
1537 alu.src[0].sel = V_SQ_ALU_SRC_0;
1538 alu.src[0].chan = i;
1539 }
1540
1541 alu.src[1] = r600_src[1];
1542 switch (i) {
1543 case 0:
1544 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
1545 break;
1546 case 1:
1547 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
1548 break;
1549 case 2:
1550 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
1551 break;
1552 case 3:
1553 alu.src[1].sel = V_SQ_ALU_SRC_0;
1554 alu.src[1].chan = i;
1555 }
1556
1557 alu.dst.sel = ctx->temp_reg;
1558 alu.dst.chan = i;
1559 alu.dst.write = 1;
1560
1561 if (i == 3)
1562 alu.last = 1;
1563 r = r600_bc_add_alu(ctx->bc, &alu);
1564 if (r)
1565 return r;
1566 }
1567
1568 for (i = 0; i < 4; i++) {
1569 memset(&alu, 0, sizeof(struct r600_bc_alu));
1570 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
1571
1572 alu.src[0] = r600_src[0];
1573 switch (i) {
1574 case 0:
1575 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1576 break;
1577 case 1:
1578 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
1579 break;
1580 case 2:
1581 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1582 break;
1583 case 3:
1584 alu.src[0].sel = V_SQ_ALU_SRC_0;
1585 alu.src[0].chan = i;
1586 }
1587
1588 alu.src[1] = r600_src[1];
1589 switch (i) {
1590 case 0:
1591 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
1592 break;
1593 case 1:
1594 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
1595 break;
1596 case 2:
1597 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
1598 break;
1599 case 3:
1600 alu.src[1].sel = V_SQ_ALU_SRC_0;
1601 alu.src[1].chan = i;
1602 }
1603
1604 alu.src[2].sel = ctx->temp_reg;
1605 alu.src[2].neg = 1;
1606 alu.src[2].chan = i;
1607
1608 if (use_temp)
1609 alu.dst.sel = ctx->temp_reg;
1610 else {
1611 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1612 if (r)
1613 return r;
1614 }
1615 alu.dst.chan = i;
1616 alu.dst.write = 1;
1617 alu.is_op3 = 1;
1618 if (i == 3)
1619 alu.last = 1;
1620 r = r600_bc_add_alu(ctx->bc, &alu);
1621 if (r)
1622 return r;
1623 }
1624 if (use_temp)
1625 return tgsi_helper_copy(ctx, inst);
1626 return 0;
1627 }
1628
1629 static int tgsi_exp(struct r600_shader_ctx *ctx)
1630 {
1631 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1632 struct r600_bc_alu_src r600_src[3];
1633 struct r600_bc_alu alu;
1634 uint32_t use_temp = 0;
1635 int i, r;
1636
1637 /* result.x = 2^floor(src); */
1638 if (inst->Dst[0].Register.WriteMask & 1) {
1639 memset(&alu, 0, sizeof(struct r600_bc_alu));
1640
1641 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR;
1642 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1643 if (r)
1644 return r;
1645
1646 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1647
1648 alu.dst.sel = ctx->temp_reg;
1649 alu.dst.chan = 0;
1650 alu.dst.write = 1;
1651 alu.last = 1;
1652 r = r600_bc_add_alu(ctx->bc, &alu);
1653 if (r)
1654 return r;
1655
1656 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
1657 alu.src[0].sel = ctx->temp_reg;
1658 alu.src[0].chan = 0;
1659
1660 alu.dst.sel = ctx->temp_reg;
1661 alu.dst.chan = 0;
1662 alu.dst.write = 1;
1663 alu.last = 1;
1664 r = r600_bc_add_alu(ctx->bc, &alu);
1665 if (r)
1666 return r;
1667 }
1668
1669 /* result.y = tmp - floor(tmp); */
1670 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
1671 memset(&alu, 0, sizeof(struct r600_bc_alu));
1672
1673 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT;
1674 alu.src[0] = r600_src[0];
1675 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1676 if (r)
1677 return r;
1678 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1679
1680 alu.dst.sel = ctx->temp_reg;
1681 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1682 // if (r)
1683 // return r;
1684 alu.dst.write = 1;
1685 alu.dst.chan = 1;
1686
1687 alu.last = 1;
1688
1689 r = r600_bc_add_alu(ctx->bc, &alu);
1690 if (r)
1691 return r;
1692 }
1693
1694 /* result.z = RoughApprox2ToX(tmp);*/
1695 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
1696 memset(&alu, 0, sizeof(struct r600_bc_alu));
1697 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
1698 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1699 if (r)
1700 return r;
1701 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1702
1703 alu.dst.sel = ctx->temp_reg;
1704 alu.dst.write = 1;
1705 alu.dst.chan = 2;
1706
1707 alu.last = 1;
1708
1709 r = r600_bc_add_alu(ctx->bc, &alu);
1710 if (r)
1711 return r;
1712
1713 }
1714
1715 /* result.w = 1.0;*/
1716 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
1717 memset(&alu, 0, sizeof(struct r600_bc_alu));
1718
1719 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
1720 alu.src[0].sel = V_SQ_ALU_SRC_1;
1721 alu.src[0].chan = 0;
1722
1723 alu.dst.sel = ctx->temp_reg;
1724 alu.dst.chan = 3;
1725 alu.dst.write = 1;
1726 alu.last = 1;
1727 r = r600_bc_add_alu(ctx->bc, &alu);
1728 if (r)
1729 return r;
1730 }
1731 return tgsi_helper_copy(ctx, inst);
1732 }
1733
1734 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
1735 {
1736 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1737 struct r600_bc_alu alu, *lalu;
1738 struct r600_bc_cf *last;
1739 int r;
1740
1741 memset(&alu, 0, sizeof(struct r600_bc_alu));
1742 alu.inst = opcode;
1743 alu.predicate = 1;
1744
1745 alu.dst.sel = ctx->temp_reg;
1746 alu.dst.write = 1;
1747 alu.dst.chan = 0;
1748
1749 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1750 if (r)
1751 return r;
1752 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1753 alu.src[1].sel = V_SQ_ALU_SRC_0;
1754 alu.src[1].chan = 0;
1755
1756 alu.last = 1;
1757
1758 r = r600_bc_add_alu_type(ctx->bc, &alu, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE);
1759 if (r)
1760 return r;
1761
1762 return 0;
1763 }
1764
1765 static int pops(struct r600_shader_ctx *ctx, int pops)
1766 {
1767 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_POP);
1768 ctx->bc->cf_last->pop_count = pops;
1769 return 0;
1770 }
1771
1772 static int tgsi_if(struct r600_shader_ctx *ctx)
1773 {
1774 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1775
1776 emit_logic_pred(ctx, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE);
1777
1778 ctx->bc->fc_sp++;
1779 ctx->bc->fc_stack[ctx->bc->fc_sp].type = FC_IF;
1780 ctx->bc->fc_stack[ctx->bc->fc_sp].mid = NULL;
1781 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
1782
1783 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
1784 return 0;
1785 }
1786
1787 static int tgsi_else(struct r600_shader_ctx *ctx)
1788 {
1789 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1790 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_ELSE);
1791 ctx->bc->cf_last->pop_count = 1;
1792
1793 /* fixup mid */
1794 ctx->bc->fc_stack[ctx->bc->fc_sp].mid = ctx->bc->cf_last;
1795 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
1796 return 0;
1797 }
1798
1799 static int tgsi_endif(struct r600_shader_ctx *ctx)
1800 {
1801 pops(ctx, 1);
1802 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
1803 R600_ERR("if/endif unbalanced in shader\n");
1804 return -1;
1805 }
1806
1807 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
1808 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
1809 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
1810 } else {
1811 ctx->bc->fc_stack[ctx->bc->fc_sp].mid->cf_addr = ctx->bc->cf_last->id + 2;
1812 }
1813 ctx->bc->fc_sp--;
1814
1815 return 0;
1816 }
1817
1818 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
1819 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1820 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
1821 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
1822 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
1823 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
1824 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
1825 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1826 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
1827 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
1828 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
1829 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
1830 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1831 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
1832 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
1833 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
1834 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
1835 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
1836 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
1837 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
1838 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1839 /* gap */
1840 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1841 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1842 /* gap */
1843 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1844 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1845 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
1846 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1847 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
1848 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1849 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
1850 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
1851 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
1852 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
1853 /* gap */
1854 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1855 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
1856 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1857 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
1858 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
1859 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
1860 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
1861 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* predicated kill */
1862 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1863 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1864 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1865 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1866 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1867 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
1868 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1869 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
1870 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
1871 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
1872 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
1873 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1874 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
1875 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1876 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
1877 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1878 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1879 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1880 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1881 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1882 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1883 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1884 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1885 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1886 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1887 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
1888 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
1889 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1890 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
1891 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1892 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1893 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
1894 {TGSI_OPCODE_TXL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1895 {TGSI_OPCODE_BRK, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1896 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
1897 /* gap */
1898 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1899 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1900 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
1901 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
1902 /* gap */
1903 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1904 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1905 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1906 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1907 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1908 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1909 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1910 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
1911 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1912 /* gap */
1913 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1914 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1915 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1916 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1917 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1918 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1919 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1920 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1921 {TGSI_OPCODE_CONT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1922 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1923 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1924 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1925 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1926 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1927 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1928 /* gap */
1929 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1930 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1931 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1932 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1933 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1934 /* gap */
1935 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1936 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1937 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1938 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1939 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1940 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1941 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1942 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1943 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
1944 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
1945 /* gap */
1946 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1947 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1948 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1949 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1950 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1951 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1952 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1953 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1954 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1955 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1956 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1957 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1958 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1959 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1960 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1961 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1962 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1963 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1964 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1965 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1966 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1967 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1968 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1969 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1970 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1971 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1972 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1973 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1974 };