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r600g: don't set up and don't call the fetch shader if there are no VS inputs
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
193
194 /* disable SB for shaders using doubles */
195 use_sb &= !shader->shader.uses_doubles;
196
197 /* Check if the bytecode has already been built. */
198 if (!shader->shader.bc.bytecode) {
199 r = r600_bytecode_build(&shader->shader.bc);
200 if (r) {
201 R600_ERR("building bytecode failed !\n");
202 goto error;
203 }
204 }
205
206 if (dump && !sb_disasm) {
207 fprintf(stderr, "--------------------------------------------------------------\n");
208 r600_bytecode_disasm(&shader->shader.bc);
209 fprintf(stderr, "______________________________________________________________\n");
210 } else if ((dump && sb_disasm) || use_sb) {
211 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
212 dump, use_sb);
213 if (r) {
214 R600_ERR("r600_sb_bytecode_process failed !\n");
215 goto error;
216 }
217 }
218
219 if (shader->gs_copy_shader) {
220 if (dump) {
221 // dump copy shader
222 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
223 &shader->gs_copy_shader->shader, dump, 0);
224 if (r)
225 goto error;
226 }
227
228 if ((r = store_shader(ctx, shader->gs_copy_shader)))
229 goto error;
230 }
231
232 /* Store the shader in a buffer. */
233 if ((r = store_shader(ctx, shader)))
234 goto error;
235
236 /* Build state. */
237 switch (shader->shader.processor_type) {
238 case PIPE_SHADER_TESS_CTRL:
239 evergreen_update_hs_state(ctx, shader);
240 break;
241 case PIPE_SHADER_TESS_EVAL:
242 if (key.tes.as_es)
243 evergreen_update_es_state(ctx, shader);
244 else
245 evergreen_update_vs_state(ctx, shader);
246 break;
247 case PIPE_SHADER_GEOMETRY:
248 if (rctx->b.chip_class >= EVERGREEN) {
249 evergreen_update_gs_state(ctx, shader);
250 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
251 } else {
252 r600_update_gs_state(ctx, shader);
253 r600_update_vs_state(ctx, shader->gs_copy_shader);
254 }
255 break;
256 case PIPE_SHADER_VERTEX:
257 export_shader = key.vs.as_es;
258 if (rctx->b.chip_class >= EVERGREEN) {
259 if (key.vs.as_ls)
260 evergreen_update_ls_state(ctx, shader);
261 else if (key.vs.as_es)
262 evergreen_update_es_state(ctx, shader);
263 else
264 evergreen_update_vs_state(ctx, shader);
265 } else {
266 if (export_shader)
267 r600_update_es_state(ctx, shader);
268 else
269 r600_update_vs_state(ctx, shader);
270 }
271 break;
272 case PIPE_SHADER_FRAGMENT:
273 if (rctx->b.chip_class >= EVERGREEN) {
274 evergreen_update_ps_state(ctx, shader);
275 } else {
276 r600_update_ps_state(ctx, shader);
277 }
278 break;
279 default:
280 r = -EINVAL;
281 goto error;
282 }
283 return 0;
284
285 error:
286 r600_pipe_shader_destroy(ctx, shader);
287 return r;
288 }
289
290 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
291 {
292 r600_resource_reference(&shader->bo, NULL);
293 r600_bytecode_clear(&shader->shader.bc);
294 r600_release_command_buffer(&shader->command_buffer);
295 }
296
297 /*
298 * tgsi -> r600 shader
299 */
300 struct r600_shader_tgsi_instruction;
301
302 struct r600_shader_src {
303 unsigned sel;
304 unsigned swizzle[4];
305 unsigned neg;
306 unsigned abs;
307 unsigned rel;
308 unsigned kc_bank;
309 boolean kc_rel; /* true if cache bank is indexed */
310 uint32_t value[4];
311 };
312
313 struct eg_interp {
314 boolean enabled;
315 unsigned ij_index;
316 };
317
318 struct r600_shader_ctx {
319 struct tgsi_shader_info info;
320 struct tgsi_parse_context parse;
321 const struct tgsi_token *tokens;
322 unsigned type;
323 unsigned file_offset[TGSI_FILE_COUNT];
324 unsigned temp_reg;
325 const struct r600_shader_tgsi_instruction *inst_info;
326 struct r600_bytecode *bc;
327 struct r600_shader *shader;
328 struct r600_shader_src src[4];
329 uint32_t *literals;
330 uint32_t nliterals;
331 uint32_t max_driver_temp_used;
332 /* needed for evergreen interpolation */
333 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
334 /* evergreen/cayman also store sample mask in face register */
335 int face_gpr;
336 /* sample id is .w component stored in fixed point position register */
337 int fixed_pt_position_gpr;
338 int colors_used;
339 boolean clip_vertex_write;
340 unsigned cv_output;
341 unsigned edgeflag_output;
342 int fragcoord_input;
343 int native_integers;
344 int next_ring_offset;
345 int gs_out_ring_offset;
346 int gs_next_vertex;
347 struct r600_shader *gs_for_vs;
348 int gs_export_gpr_tregs[4];
349 const struct pipe_stream_output_info *gs_stream_output_info;
350 unsigned enabled_stream_buffers_mask;
351 unsigned tess_input_info; /* temp with tess input offsets */
352 unsigned tess_output_info; /* temp with tess input offsets */
353 };
354
355 struct r600_shader_tgsi_instruction {
356 unsigned op;
357 int (*process)(struct r600_shader_ctx *ctx);
358 };
359
360 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
361 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
362 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
363 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
364 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
365 static int tgsi_else(struct r600_shader_ctx *ctx);
366 static int tgsi_endif(struct r600_shader_ctx *ctx);
367 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
368 static int tgsi_endloop(struct r600_shader_ctx *ctx);
369 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
370 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
371 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
372 unsigned int dst_reg);
373 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
374 const struct r600_shader_src *shader_src,
375 unsigned chan);
376 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
377 unsigned dst_reg);
378
379 static int tgsi_last_instruction(unsigned writemask)
380 {
381 int i, lasti = 0;
382
383 for (i = 0; i < 4; i++) {
384 if (writemask & (1 << i)) {
385 lasti = i;
386 }
387 }
388 return lasti;
389 }
390
391 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
392 {
393 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
394 unsigned j;
395
396 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
397 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
398 return -EINVAL;
399 }
400 #if 0
401 if (i->Instruction.Label) {
402 R600_ERR("label unsupported\n");
403 return -EINVAL;
404 }
405 #endif
406 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
407 if (i->Src[j].Register.Dimension) {
408 switch (i->Src[j].Register.File) {
409 case TGSI_FILE_CONSTANT:
410 break;
411 case TGSI_FILE_INPUT:
412 if (ctx->type == PIPE_SHADER_GEOMETRY ||
413 ctx->type == PIPE_SHADER_TESS_CTRL ||
414 ctx->type == PIPE_SHADER_TESS_EVAL)
415 break;
416 case TGSI_FILE_OUTPUT:
417 if (ctx->type == PIPE_SHADER_TESS_CTRL)
418 break;
419 default:
420 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
421 i->Src[j].Register.File,
422 i->Src[j].Register.Dimension);
423 return -EINVAL;
424 }
425 }
426 }
427 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
428 if (i->Dst[j].Register.Dimension) {
429 if (ctx->type == PIPE_SHADER_TESS_CTRL)
430 continue;
431 R600_ERR("unsupported dst (dimension)\n");
432 return -EINVAL;
433 }
434 }
435 return 0;
436 }
437
438 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
439 {
440 if (interpolate == TGSI_INTERPOLATE_COLOR ||
441 interpolate == TGSI_INTERPOLATE_LINEAR ||
442 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
443 {
444 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
445 int loc;
446
447 switch(location) {
448 case TGSI_INTERPOLATE_LOC_CENTER:
449 loc = 1;
450 break;
451 case TGSI_INTERPOLATE_LOC_CENTROID:
452 loc = 2;
453 break;
454 case TGSI_INTERPOLATE_LOC_SAMPLE:
455 default:
456 loc = 0; break;
457 }
458
459 return is_linear * 3 + loc;
460 }
461
462 return -1;
463 }
464
465 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
466 int input)
467 {
468 int i = eg_get_interpolator_index(
469 ctx->shader->input[input].interpolate,
470 ctx->shader->input[input].interpolate_location);
471 assert(i >= 0);
472 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
473 }
474
475 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
476 {
477 int i, r;
478 struct r600_bytecode_alu alu;
479 int gpr = 0, base_chan = 0;
480 int ij_index = ctx->shader->input[input].ij_index;
481
482 /* work out gpr and base_chan from index */
483 gpr = ij_index / 2;
484 base_chan = (2 * (ij_index % 2)) + 1;
485
486 for (i = 0; i < 8; i++) {
487 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
488
489 if (i < 4)
490 alu.op = ALU_OP2_INTERP_ZW;
491 else
492 alu.op = ALU_OP2_INTERP_XY;
493
494 if ((i > 1) && (i < 6)) {
495 alu.dst.sel = ctx->shader->input[input].gpr;
496 alu.dst.write = 1;
497 }
498
499 alu.dst.chan = i % 4;
500
501 alu.src[0].sel = gpr;
502 alu.src[0].chan = (base_chan - (i % 2));
503
504 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
505
506 alu.bank_swizzle_force = SQ_ALU_VEC_210;
507 if ((i % 4) == 3)
508 alu.last = 1;
509 r = r600_bytecode_add_alu(ctx->bc, &alu);
510 if (r)
511 return r;
512 }
513 return 0;
514 }
515
516 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
517 {
518 int i, r;
519 struct r600_bytecode_alu alu;
520
521 for (i = 0; i < 4; i++) {
522 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
523
524 alu.op = ALU_OP1_INTERP_LOAD_P0;
525
526 alu.dst.sel = ctx->shader->input[input].gpr;
527 alu.dst.write = 1;
528
529 alu.dst.chan = i;
530
531 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
532 alu.src[0].chan = i;
533
534 if (i == 3)
535 alu.last = 1;
536 r = r600_bytecode_add_alu(ctx->bc, &alu);
537 if (r)
538 return r;
539 }
540 return 0;
541 }
542
543 /*
544 * Special export handling in shaders
545 *
546 * shader export ARRAY_BASE for EXPORT_POS:
547 * 60 is position
548 * 61 is misc vector
549 * 62, 63 are clip distance vectors
550 *
551 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
552 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
553 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
554 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
555 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
556 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
557 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
558 * exclusive from render target index)
559 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
560 *
561 *
562 * shader export ARRAY_BASE for EXPORT_PIXEL:
563 * 0-7 CB targets
564 * 61 computed Z vector
565 *
566 * The use of the values exported in the computed Z vector are controlled
567 * by DB_SHADER_CONTROL:
568 * Z_EXPORT_ENABLE - Z as a float in RED
569 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
570 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
571 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
572 * DB_SOURCE_FORMAT - export control restrictions
573 *
574 */
575
576
577 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
578 static int r600_spi_sid(struct r600_shader_io * io)
579 {
580 int index, name = io->name;
581
582 /* These params are handled differently, they don't need
583 * semantic indices, so we'll use 0 for them.
584 */
585 if (name == TGSI_SEMANTIC_POSITION ||
586 name == TGSI_SEMANTIC_PSIZE ||
587 name == TGSI_SEMANTIC_EDGEFLAG ||
588 name == TGSI_SEMANTIC_FACE ||
589 name == TGSI_SEMANTIC_SAMPLEMASK)
590 index = 0;
591 else {
592 if (name == TGSI_SEMANTIC_GENERIC) {
593 /* For generic params simply use sid from tgsi */
594 index = io->sid;
595 } else {
596 /* For non-generic params - pack name and sid into 8 bits */
597 index = 0x80 | (name<<3) | (io->sid);
598 }
599
600 /* Make sure that all really used indices have nonzero value, so
601 * we can just compare it to 0 later instead of comparing the name
602 * with different values to detect special cases. */
603 index++;
604 }
605
606 return index;
607 };
608
609 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
610 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
611 {
612 switch (semantic_name) {
613 case TGSI_SEMANTIC_POSITION:
614 return 0;
615 case TGSI_SEMANTIC_PSIZE:
616 return 1;
617 case TGSI_SEMANTIC_CLIPDIST:
618 assert(index <= 1);
619 return 2 + index;
620 case TGSI_SEMANTIC_GENERIC:
621 if (index <= 63-4)
622 return 4 + index - 9;
623 else
624 /* same explanation as in the default statement,
625 * the only user hitting this is st/nine.
626 */
627 return 0;
628
629 /* patch indices are completely separate and thus start from 0 */
630 case TGSI_SEMANTIC_TESSOUTER:
631 return 0;
632 case TGSI_SEMANTIC_TESSINNER:
633 return 1;
634 case TGSI_SEMANTIC_PATCH:
635 return 2 + index;
636
637 default:
638 /* Don't fail here. The result of this function is only used
639 * for LS, TCS, TES, and GS, where legacy GL semantics can't
640 * occur, but this function is called for all vertex shaders
641 * before it's known whether LS will be compiled or not.
642 */
643 return 0;
644 }
645 }
646
647 /* turn input into interpolate on EG */
648 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
649 {
650 int r = 0;
651
652 if (ctx->shader->input[index].spi_sid) {
653 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
654 if (ctx->shader->input[index].interpolate > 0) {
655 evergreen_interp_assign_ij_index(ctx, index);
656 r = evergreen_interp_alu(ctx, index);
657 } else {
658 r = evergreen_interp_flat(ctx, index);
659 }
660 }
661 return r;
662 }
663
664 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
665 {
666 struct r600_bytecode_alu alu;
667 int i, r;
668 int gpr_front = ctx->shader->input[front].gpr;
669 int gpr_back = ctx->shader->input[back].gpr;
670
671 for (i = 0; i < 4; i++) {
672 memset(&alu, 0, sizeof(alu));
673 alu.op = ALU_OP3_CNDGT;
674 alu.is_op3 = 1;
675 alu.dst.write = 1;
676 alu.dst.sel = gpr_front;
677 alu.src[0].sel = ctx->face_gpr;
678 alu.src[1].sel = gpr_front;
679 alu.src[2].sel = gpr_back;
680
681 alu.dst.chan = i;
682 alu.src[1].chan = i;
683 alu.src[2].chan = i;
684 alu.last = (i==3);
685
686 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
687 return r;
688 }
689
690 return 0;
691 }
692
693 /* execute a single slot ALU calculation */
694 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
695 int dst_sel, int dst_chan,
696 int src0_sel, unsigned src0_chan_val,
697 int src1_sel, unsigned src1_chan_val)
698 {
699 struct r600_bytecode_alu alu;
700 int r, i;
701
702 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
703 for (i = 0; i < 4; i++) {
704 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
705 alu.op = op;
706 alu.src[0].sel = src0_sel;
707 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
708 alu.src[0].value = src0_chan_val;
709 else
710 alu.src[0].chan = src0_chan_val;
711 alu.src[1].sel = src1_sel;
712 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
713 alu.src[1].value = src1_chan_val;
714 else
715 alu.src[1].chan = src1_chan_val;
716 alu.dst.sel = dst_sel;
717 alu.dst.chan = i;
718 alu.dst.write = i == dst_chan;
719 alu.last = (i == 3);
720 r = r600_bytecode_add_alu(ctx->bc, &alu);
721 if (r)
722 return r;
723 }
724 return 0;
725 }
726
727 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
728 alu.op = op;
729 alu.src[0].sel = src0_sel;
730 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
731 alu.src[0].value = src0_chan_val;
732 else
733 alu.src[0].chan = src0_chan_val;
734 alu.src[1].sel = src1_sel;
735 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
736 alu.src[1].value = src1_chan_val;
737 else
738 alu.src[1].chan = src1_chan_val;
739 alu.dst.sel = dst_sel;
740 alu.dst.chan = dst_chan;
741 alu.dst.write = 1;
742 alu.last = 1;
743 r = r600_bytecode_add_alu(ctx->bc, &alu);
744 if (r)
745 return r;
746 return 0;
747 }
748
749 /* execute a single slot ALU calculation */
750 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
751 int dst_sel, int dst_chan,
752 int src0_sel, unsigned src0_chan_val,
753 int src1_sel, unsigned src1_chan_val,
754 int src2_sel, unsigned src2_chan_val)
755 {
756 struct r600_bytecode_alu alu;
757 int r;
758
759 /* validate this for other ops */
760 assert(op == ALU_OP3_MULADD_UINT24);
761 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
762 alu.op = op;
763 alu.src[0].sel = src0_sel;
764 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
765 alu.src[0].value = src0_chan_val;
766 else
767 alu.src[0].chan = src0_chan_val;
768 alu.src[1].sel = src1_sel;
769 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
770 alu.src[1].value = src1_chan_val;
771 else
772 alu.src[1].chan = src1_chan_val;
773 alu.src[2].sel = src2_sel;
774 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
775 alu.src[2].value = src2_chan_val;
776 else
777 alu.src[2].chan = src2_chan_val;
778 alu.dst.sel = dst_sel;
779 alu.dst.chan = dst_chan;
780 alu.is_op3 = 1;
781 alu.last = 1;
782 r = r600_bytecode_add_alu(ctx->bc, &alu);
783 if (r)
784 return r;
785 return 0;
786 }
787
788 /* put it in temp_reg.x */
789 static int get_lds_offset0(struct r600_shader_ctx *ctx,
790 int rel_patch_chan,
791 int temp_reg, bool is_patch_var)
792 {
793 int r;
794
795 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
796 /* ADD
797 Dimension - patch0_offset (input_vals.z),
798 Non-dim - patch0_data_offset (input_vals.w)
799 */
800 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
801 temp_reg, 0,
802 ctx->tess_output_info, 0,
803 0, rel_patch_chan,
804 ctx->tess_output_info, is_patch_var ? 3 : 2);
805 if (r)
806 return r;
807 return 0;
808 }
809
810 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
811 {
812 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
813 }
814
815 static int r600_get_temp(struct r600_shader_ctx *ctx)
816 {
817 return ctx->temp_reg + ctx->max_driver_temp_used++;
818 }
819
820 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
821 {
822 int i;
823 i = ctx->shader->noutput++;
824 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
825 ctx->shader->output[i].sid = 0;
826 ctx->shader->output[i].gpr = 0;
827 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
828 ctx->shader->output[i].write_mask = 0x4;
829 ctx->shader->output[i].spi_sid = prim_id_sid;
830
831 return 0;
832 }
833
834 static int tgsi_barrier(struct r600_shader_ctx *ctx)
835 {
836 struct r600_bytecode_alu alu;
837 int r;
838
839 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
840 alu.op = ctx->inst_info->op;
841 alu.last = 1;
842
843 r = r600_bytecode_add_alu(ctx->bc, &alu);
844 if (r)
845 return r;
846 return 0;
847 }
848
849 static int tgsi_declaration(struct r600_shader_ctx *ctx)
850 {
851 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
852 int r, i, j, count = d->Range.Last - d->Range.First + 1;
853
854 switch (d->Declaration.File) {
855 case TGSI_FILE_INPUT:
856 for (j = 0; j < count; j++) {
857 i = ctx->shader->ninput + j;
858 assert(i < ARRAY_SIZE(ctx->shader->input));
859 ctx->shader->input[i].name = d->Semantic.Name;
860 ctx->shader->input[i].sid = d->Semantic.Index + j;
861 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
862 ctx->shader->input[i].interpolate_location = d->Interp.Location;
863 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
864 if (ctx->type == PIPE_SHADER_FRAGMENT) {
865 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
866 switch (ctx->shader->input[i].name) {
867 case TGSI_SEMANTIC_FACE:
868 if (ctx->face_gpr != -1)
869 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
870 else
871 ctx->face_gpr = ctx->shader->input[i].gpr;
872 break;
873 case TGSI_SEMANTIC_COLOR:
874 ctx->colors_used++;
875 break;
876 case TGSI_SEMANTIC_POSITION:
877 ctx->fragcoord_input = i;
878 break;
879 case TGSI_SEMANTIC_PRIMID:
880 /* set this for now */
881 ctx->shader->gs_prim_id_input = true;
882 ctx->shader->ps_prim_id_input = i;
883 break;
884 }
885 if (ctx->bc->chip_class >= EVERGREEN) {
886 if ((r = evergreen_interp_input(ctx, i)))
887 return r;
888 }
889 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
890 /* FIXME probably skip inputs if they aren't passed in the ring */
891 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
892 ctx->next_ring_offset += 16;
893 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
894 ctx->shader->gs_prim_id_input = true;
895 }
896 }
897 ctx->shader->ninput += count;
898 break;
899 case TGSI_FILE_OUTPUT:
900 for (j = 0; j < count; j++) {
901 i = ctx->shader->noutput + j;
902 assert(i < ARRAY_SIZE(ctx->shader->output));
903 ctx->shader->output[i].name = d->Semantic.Name;
904 ctx->shader->output[i].sid = d->Semantic.Index + j;
905 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
906 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
907 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
908 if (ctx->type == PIPE_SHADER_VERTEX ||
909 ctx->type == PIPE_SHADER_GEOMETRY ||
910 ctx->type == PIPE_SHADER_TESS_EVAL) {
911 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
912 switch (d->Semantic.Name) {
913 case TGSI_SEMANTIC_CLIPDIST:
914 ctx->shader->clip_dist_write |= d->Declaration.UsageMask <<
915 ((d->Semantic.Index + j) << 2);
916 break;
917 case TGSI_SEMANTIC_PSIZE:
918 ctx->shader->vs_out_misc_write = 1;
919 ctx->shader->vs_out_point_size = 1;
920 break;
921 case TGSI_SEMANTIC_EDGEFLAG:
922 ctx->shader->vs_out_misc_write = 1;
923 ctx->shader->vs_out_edgeflag = 1;
924 ctx->edgeflag_output = i;
925 break;
926 case TGSI_SEMANTIC_VIEWPORT_INDEX:
927 ctx->shader->vs_out_misc_write = 1;
928 ctx->shader->vs_out_viewport = 1;
929 break;
930 case TGSI_SEMANTIC_LAYER:
931 ctx->shader->vs_out_misc_write = 1;
932 ctx->shader->vs_out_layer = 1;
933 break;
934 case TGSI_SEMANTIC_CLIPVERTEX:
935 ctx->clip_vertex_write = TRUE;
936 ctx->cv_output = i;
937 break;
938 }
939 if (ctx->type == PIPE_SHADER_GEOMETRY) {
940 ctx->gs_out_ring_offset += 16;
941 }
942 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
943 switch (d->Semantic.Name) {
944 case TGSI_SEMANTIC_COLOR:
945 ctx->shader->nr_ps_max_color_exports++;
946 break;
947 }
948 }
949 }
950 ctx->shader->noutput += count;
951 break;
952 case TGSI_FILE_TEMPORARY:
953 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
954 if (d->Array.ArrayID) {
955 r600_add_gpr_array(ctx->shader,
956 ctx->file_offset[TGSI_FILE_TEMPORARY] +
957 d->Range.First,
958 d->Range.Last - d->Range.First + 1, 0x0F);
959 }
960 }
961 break;
962
963 case TGSI_FILE_CONSTANT:
964 case TGSI_FILE_SAMPLER:
965 case TGSI_FILE_SAMPLER_VIEW:
966 case TGSI_FILE_ADDRESS:
967 break;
968
969 case TGSI_FILE_SYSTEM_VALUE:
970 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
971 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
972 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
973 break; /* Already handled from allocate_system_value_inputs */
974 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
975 if (!ctx->native_integers) {
976 struct r600_bytecode_alu alu;
977 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
978
979 alu.op = ALU_OP1_INT_TO_FLT;
980 alu.src[0].sel = 0;
981 alu.src[0].chan = 3;
982
983 alu.dst.sel = 0;
984 alu.dst.chan = 3;
985 alu.dst.write = 1;
986 alu.last = 1;
987
988 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
989 return r;
990 }
991 break;
992 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
993 break;
994 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
995 break;
996 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
997 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
998 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
999 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1000 unsigned temp_reg = r600_get_temp(ctx);
1001
1002 r = get_lds_offset0(ctx, 2, temp_reg, true);
1003 if (r)
1004 return r;
1005
1006 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1007 temp_reg, 0,
1008 temp_reg, 0,
1009 V_SQ_ALU_SRC_LITERAL, param * 16);
1010 if (r)
1011 return r;
1012
1013 do_lds_fetch_values(ctx, temp_reg, dreg);
1014 }
1015 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1016 /* MOV r1.x, r0.x;
1017 MOV r1.y, r0.y;
1018 */
1019 for (i = 0; i < 2; i++) {
1020 struct r600_bytecode_alu alu;
1021 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1022 alu.op = ALU_OP1_MOV;
1023 alu.src[0].sel = 0;
1024 alu.src[0].chan = 0 + i;
1025 alu.dst.sel = 1;
1026 alu.dst.chan = 0 + i;
1027 alu.dst.write = 1;
1028 alu.last = (i == 1) ? 1 : 0;
1029 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1030 return r;
1031 }
1032 /* ADD r1.z, 1.0f, -r0.x */
1033 struct r600_bytecode_alu alu;
1034 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1035 alu.op = ALU_OP2_ADD;
1036 alu.src[0].sel = V_SQ_ALU_SRC_1;
1037 alu.src[1].sel = 1;
1038 alu.src[1].chan = 0;
1039 alu.src[1].neg = 1;
1040 alu.dst.sel = 1;
1041 alu.dst.chan = 2;
1042 alu.dst.write = 1;
1043 alu.last = 1;
1044 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1045 return r;
1046
1047 /* ADD r1.z, r1.z, -r1.y */
1048 alu.op = ALU_OP2_ADD;
1049 alu.src[0].sel = 1;
1050 alu.src[0].chan = 2;
1051 alu.src[1].sel = 1;
1052 alu.src[1].chan = 1;
1053 alu.src[1].neg = 1;
1054 alu.dst.sel = 1;
1055 alu.dst.chan = 2;
1056 alu.dst.write = 1;
1057 alu.last = 1;
1058 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1059 return r;
1060 break;
1061 }
1062 break;
1063 default:
1064 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1065 return -EINVAL;
1066 }
1067 return 0;
1068 }
1069
1070 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1071 {
1072 struct tgsi_parse_context parse;
1073 struct {
1074 boolean enabled;
1075 int *reg;
1076 unsigned name, alternate_name;
1077 } inputs[2] = {
1078 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1079
1080 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1081 };
1082 int i, k, num_regs = 0;
1083
1084 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1085 return 0;
1086 }
1087
1088 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1089 while (!tgsi_parse_end_of_tokens(&parse)) {
1090 tgsi_parse_token(&parse);
1091
1092 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1093 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1094 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1095 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1096 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1097 {
1098 int interpolate, location, k;
1099
1100 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1101 location = TGSI_INTERPOLATE_LOC_CENTER;
1102 inputs[1].enabled = true; /* needs SAMPLEID */
1103 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1104 location = TGSI_INTERPOLATE_LOC_CENTER;
1105 /* Needs sample positions, currently those are always available */
1106 } else {
1107 location = TGSI_INTERPOLATE_LOC_CENTROID;
1108 }
1109
1110 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1111 k = eg_get_interpolator_index(interpolate, location);
1112 if (k >= 0)
1113 ctx->eg_interpolators[k].enabled = true;
1114 }
1115 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1116 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1117 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1118 for (k = 0; k < ARRAY_SIZE(inputs); k++) {
1119 if (d->Semantic.Name == inputs[k].name ||
1120 d->Semantic.Name == inputs[k].alternate_name) {
1121 inputs[k].enabled = true;
1122 }
1123 }
1124 }
1125 }
1126 }
1127
1128 tgsi_parse_free(&parse);
1129
1130 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
1131 boolean enabled = inputs[i].enabled;
1132 int *reg = inputs[i].reg;
1133 unsigned name = inputs[i].name;
1134
1135 if (enabled) {
1136 int gpr = gpr_offset + num_regs++;
1137 ctx->shader->nsys_inputs++;
1138
1139 // add to inputs, allocate a gpr
1140 k = ctx->shader->ninput++;
1141 ctx->shader->input[k].name = name;
1142 ctx->shader->input[k].sid = 0;
1143 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1144 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1145 *reg = ctx->shader->input[k].gpr = gpr;
1146 }
1147 }
1148
1149 return gpr_offset + num_regs;
1150 }
1151
1152 /*
1153 * for evergreen we need to scan the shader to find the number of GPRs we need to
1154 * reserve for interpolation and system values
1155 *
1156 * we need to know if we are going to emit
1157 * any sample or centroid inputs
1158 * if perspective and linear are required
1159 */
1160 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1161 {
1162 unsigned i;
1163 int num_baryc;
1164 struct tgsi_parse_context parse;
1165
1166 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1167
1168 for (i = 0; i < ctx->info.num_inputs; i++) {
1169 int k;
1170 /* skip position/face/mask/sampleid */
1171 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1172 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1173 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1174 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1175 continue;
1176
1177 k = eg_get_interpolator_index(
1178 ctx->info.input_interpolate[i],
1179 ctx->info.input_interpolate_loc[i]);
1180 if (k >= 0)
1181 ctx->eg_interpolators[k].enabled = TRUE;
1182 }
1183
1184 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1185 return 0;
1186 }
1187
1188 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1189 while (!tgsi_parse_end_of_tokens(&parse)) {
1190 tgsi_parse_token(&parse);
1191
1192 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1193 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1194 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1195 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1196 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1197 {
1198 int interpolate, location, k;
1199
1200 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1201 location = TGSI_INTERPOLATE_LOC_CENTER;
1202 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1203 location = TGSI_INTERPOLATE_LOC_CENTER;
1204 } else {
1205 location = TGSI_INTERPOLATE_LOC_CENTROID;
1206 }
1207
1208 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1209 k = eg_get_interpolator_index(interpolate, location);
1210 if (k >= 0)
1211 ctx->eg_interpolators[k].enabled = true;
1212 }
1213 }
1214 }
1215
1216 tgsi_parse_free(&parse);
1217
1218 /* assign gpr to each interpolator according to priority */
1219 num_baryc = 0;
1220 for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
1221 if (ctx->eg_interpolators[i].enabled) {
1222 ctx->eg_interpolators[i].ij_index = num_baryc;
1223 num_baryc ++;
1224 }
1225 }
1226
1227 /* XXX PULL MODEL and LINE STIPPLE */
1228
1229 num_baryc = (num_baryc + 1) >> 1;
1230 return allocate_system_value_inputs(ctx, num_baryc);
1231 }
1232
1233 /* sample_id_sel == NULL means fetch for current sample */
1234 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1235 {
1236 struct r600_bytecode_vtx vtx;
1237 int r, t1;
1238
1239 assert(ctx->fixed_pt_position_gpr != -1);
1240
1241 t1 = r600_get_temp(ctx);
1242
1243 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1244 vtx.op = FETCH_OP_VFETCH;
1245 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1246 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1247 if (sample_id == NULL) {
1248 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1249 vtx.src_sel_x = 3;
1250 }
1251 else {
1252 struct r600_bytecode_alu alu;
1253
1254 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1255 alu.op = ALU_OP1_MOV;
1256 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1257 alu.dst.sel = t1;
1258 alu.dst.write = 1;
1259 alu.last = 1;
1260 r = r600_bytecode_add_alu(ctx->bc, &alu);
1261 if (r)
1262 return r;
1263
1264 vtx.src_gpr = t1;
1265 vtx.src_sel_x = 0;
1266 }
1267 vtx.mega_fetch_count = 16;
1268 vtx.dst_gpr = t1;
1269 vtx.dst_sel_x = 0;
1270 vtx.dst_sel_y = 1;
1271 vtx.dst_sel_z = 2;
1272 vtx.dst_sel_w = 3;
1273 vtx.data_format = FMT_32_32_32_32_FLOAT;
1274 vtx.num_format_all = 2;
1275 vtx.format_comp_all = 1;
1276 vtx.use_const_fields = 0;
1277 vtx.offset = 1; // first element is size of buffer
1278 vtx.endian = r600_endian_swap(32);
1279 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1280
1281 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1282 if (r)
1283 return r;
1284
1285 return t1;
1286 }
1287
1288 static void tgsi_src(struct r600_shader_ctx *ctx,
1289 const struct tgsi_full_src_register *tgsi_src,
1290 struct r600_shader_src *r600_src)
1291 {
1292 memset(r600_src, 0, sizeof(*r600_src));
1293 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1294 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1295 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1296 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1297 r600_src->neg = tgsi_src->Register.Negate;
1298 r600_src->abs = tgsi_src->Register.Absolute;
1299
1300 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1301 int index;
1302 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1303 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1304 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1305
1306 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1307 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1308 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1309 return;
1310 }
1311 index = tgsi_src->Register.Index;
1312 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1313 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1314 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1315 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1316 r600_src->swizzle[0] = 2; // Z value
1317 r600_src->swizzle[1] = 2;
1318 r600_src->swizzle[2] = 2;
1319 r600_src->swizzle[3] = 2;
1320 r600_src->sel = ctx->face_gpr;
1321 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1322 r600_src->swizzle[0] = 3; // W value
1323 r600_src->swizzle[1] = 3;
1324 r600_src->swizzle[2] = 3;
1325 r600_src->swizzle[3] = 3;
1326 r600_src->sel = ctx->fixed_pt_position_gpr;
1327 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1328 r600_src->swizzle[0] = 0;
1329 r600_src->swizzle[1] = 1;
1330 r600_src->swizzle[2] = 4;
1331 r600_src->swizzle[3] = 4;
1332 r600_src->sel = load_sample_position(ctx, NULL, -1);
1333 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1334 r600_src->swizzle[0] = 3;
1335 r600_src->swizzle[1] = 3;
1336 r600_src->swizzle[2] = 3;
1337 r600_src->swizzle[3] = 3;
1338 r600_src->sel = 0;
1339 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1340 r600_src->swizzle[0] = 0;
1341 r600_src->swizzle[1] = 0;
1342 r600_src->swizzle[2] = 0;
1343 r600_src->swizzle[3] = 0;
1344 r600_src->sel = 0;
1345 } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1346 r600_src->swizzle[0] = 3;
1347 r600_src->swizzle[1] = 3;
1348 r600_src->swizzle[2] = 3;
1349 r600_src->swizzle[3] = 3;
1350 r600_src->sel = 1;
1351 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1352 r600_src->swizzle[0] = 2;
1353 r600_src->swizzle[1] = 2;
1354 r600_src->swizzle[2] = 2;
1355 r600_src->swizzle[3] = 2;
1356 r600_src->sel = 0;
1357 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1358 r600_src->sel = 1;
1359 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1360 r600_src->sel = 3;
1361 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1362 r600_src->sel = 2;
1363 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1364 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
1365 r600_src->sel = ctx->tess_input_info;
1366 r600_src->swizzle[0] = 2;
1367 r600_src->swizzle[1] = 2;
1368 r600_src->swizzle[2] = 2;
1369 r600_src->swizzle[3] = 2;
1370 } else {
1371 r600_src->sel = ctx->tess_input_info;
1372 r600_src->swizzle[0] = 3;
1373 r600_src->swizzle[1] = 3;
1374 r600_src->swizzle[2] = 3;
1375 r600_src->swizzle[3] = 3;
1376 }
1377 } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1378 r600_src->sel = 0;
1379 r600_src->swizzle[0] = 0;
1380 r600_src->swizzle[1] = 0;
1381 r600_src->swizzle[2] = 0;
1382 r600_src->swizzle[3] = 0;
1383 } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1384 r600_src->sel = 0;
1385 r600_src->swizzle[0] = 3;
1386 r600_src->swizzle[1] = 3;
1387 r600_src->swizzle[2] = 3;
1388 r600_src->swizzle[3] = 3;
1389 }
1390 } else {
1391 if (tgsi_src->Register.Indirect)
1392 r600_src->rel = V_SQ_REL_RELATIVE;
1393 r600_src->sel = tgsi_src->Register.Index;
1394 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1395 }
1396 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1397 if (tgsi_src->Register.Dimension) {
1398 r600_src->kc_bank = tgsi_src->Dimension.Index;
1399 if (tgsi_src->Dimension.Indirect) {
1400 r600_src->kc_rel = 1;
1401 }
1402 }
1403 }
1404 }
1405
1406 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1407 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1408 unsigned int dst_reg)
1409 {
1410 struct r600_bytecode_vtx vtx;
1411 unsigned int ar_reg;
1412 int r;
1413
1414 if (offset) {
1415 struct r600_bytecode_alu alu;
1416
1417 memset(&alu, 0, sizeof(alu));
1418
1419 alu.op = ALU_OP2_ADD_INT;
1420 alu.src[0].sel = ctx->bc->ar_reg;
1421 alu.src[0].chan = ar_chan;
1422
1423 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1424 alu.src[1].value = offset;
1425
1426 alu.dst.sel = dst_reg;
1427 alu.dst.chan = ar_chan;
1428 alu.dst.write = 1;
1429 alu.last = 1;
1430
1431 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1432 return r;
1433
1434 ar_reg = dst_reg;
1435 } else {
1436 ar_reg = ctx->bc->ar_reg;
1437 }
1438
1439 memset(&vtx, 0, sizeof(vtx));
1440 vtx.buffer_id = cb_idx;
1441 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1442 vtx.src_gpr = ar_reg;
1443 vtx.src_sel_x = ar_chan;
1444 vtx.mega_fetch_count = 16;
1445 vtx.dst_gpr = dst_reg;
1446 vtx.dst_sel_x = 0; /* SEL_X */
1447 vtx.dst_sel_y = 1; /* SEL_Y */
1448 vtx.dst_sel_z = 2; /* SEL_Z */
1449 vtx.dst_sel_w = 3; /* SEL_W */
1450 vtx.data_format = FMT_32_32_32_32_FLOAT;
1451 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1452 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1453 vtx.endian = r600_endian_swap(32);
1454 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1455
1456 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1457 return r;
1458
1459 return 0;
1460 }
1461
1462 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1463 {
1464 struct r600_bytecode_vtx vtx;
1465 int r;
1466 unsigned index = src->Register.Index;
1467 unsigned vtx_id = src->Dimension.Index;
1468 int offset_reg = vtx_id / 3;
1469 int offset_chan = vtx_id % 3;
1470 int t2 = 0;
1471
1472 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1473 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1474
1475 if (offset_reg == 0 && offset_chan == 2)
1476 offset_chan = 3;
1477
1478 if (src->Dimension.Indirect || src->Register.Indirect)
1479 t2 = r600_get_temp(ctx);
1480
1481 if (src->Dimension.Indirect) {
1482 int treg[3];
1483 struct r600_bytecode_alu alu;
1484 int r, i;
1485 unsigned addr_reg;
1486 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1487 if (src->DimIndirect.Index > 0) {
1488 r = single_alu_op2(ctx, ALU_OP1_MOV,
1489 ctx->bc->ar_reg, 0,
1490 addr_reg, 0,
1491 0, 0);
1492 if (r)
1493 return r;
1494 }
1495 /*
1496 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1497 at least this is what fglrx seems to do. */
1498 for (i = 0; i < 3; i++) {
1499 treg[i] = r600_get_temp(ctx);
1500 }
1501 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1502
1503 for (i = 0; i < 3; i++) {
1504 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1505 alu.op = ALU_OP1_MOV;
1506 alu.src[0].sel = 0;
1507 alu.src[0].chan = i == 2 ? 3 : i;
1508 alu.dst.sel = treg[i];
1509 alu.dst.chan = 0;
1510 alu.dst.write = 1;
1511 alu.last = 1;
1512 r = r600_bytecode_add_alu(ctx->bc, &alu);
1513 if (r)
1514 return r;
1515 }
1516 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1517 alu.op = ALU_OP1_MOV;
1518 alu.src[0].sel = treg[0];
1519 alu.src[0].rel = 1;
1520 alu.dst.sel = t2;
1521 alu.dst.write = 1;
1522 alu.last = 1;
1523 r = r600_bytecode_add_alu(ctx->bc, &alu);
1524 if (r)
1525 return r;
1526 offset_reg = t2;
1527 offset_chan = 0;
1528 }
1529
1530 if (src->Register.Indirect) {
1531 int addr_reg;
1532 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1533
1534 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1535
1536 /* pull the value from index_reg */
1537 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1538 t2, 1,
1539 addr_reg, 0,
1540 V_SQ_ALU_SRC_LITERAL, first);
1541 if (r)
1542 return r;
1543 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1544 t2, 0,
1545 t2, 1,
1546 V_SQ_ALU_SRC_LITERAL, 4,
1547 offset_reg, offset_chan);
1548 if (r)
1549 return r;
1550 offset_reg = t2;
1551 offset_chan = 0;
1552 index = src->Register.Index - first;
1553 }
1554
1555 memset(&vtx, 0, sizeof(vtx));
1556 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1557 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1558 vtx.src_gpr = offset_reg;
1559 vtx.src_sel_x = offset_chan;
1560 vtx.offset = index * 16; /*bytes*/
1561 vtx.mega_fetch_count = 16;
1562 vtx.dst_gpr = dst_reg;
1563 vtx.dst_sel_x = 0; /* SEL_X */
1564 vtx.dst_sel_y = 1; /* SEL_Y */
1565 vtx.dst_sel_z = 2; /* SEL_Z */
1566 vtx.dst_sel_w = 3; /* SEL_W */
1567 if (ctx->bc->chip_class >= EVERGREEN) {
1568 vtx.use_const_fields = 1;
1569 } else {
1570 vtx.data_format = FMT_32_32_32_32_FLOAT;
1571 }
1572
1573 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1574 return r;
1575
1576 return 0;
1577 }
1578
1579 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1580 {
1581 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1582 unsigned i;
1583
1584 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1585 struct tgsi_full_src_register *src = &inst->Src[i];
1586
1587 if (src->Register.File == TGSI_FILE_INPUT) {
1588 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1589 /* primitive id is in R0.z */
1590 ctx->src[i].sel = 0;
1591 ctx->src[i].swizzle[0] = 2;
1592 }
1593 }
1594 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1595 int treg = r600_get_temp(ctx);
1596
1597 fetch_gs_input(ctx, src, treg);
1598 ctx->src[i].sel = treg;
1599 ctx->src[i].rel = 0;
1600 }
1601 }
1602 return 0;
1603 }
1604
1605
1606 /* Tessellation shaders pass outputs to the next shader using LDS.
1607 *
1608 * LS outputs = TCS(HS) inputs
1609 * TCS(HS) outputs = TES(DS) inputs
1610 *
1611 * The LDS layout is:
1612 * - TCS inputs for patch 0
1613 * - TCS inputs for patch 1
1614 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1615 * - ...
1616 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1617 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1618 * - TCS outputs for patch 1
1619 * - Per-patch TCS outputs for patch 1
1620 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1621 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1622 * - ...
1623 *
1624 * All three shaders VS(LS), TCS, TES share the same LDS space.
1625 */
1626 /* this will return with the dw address in temp_reg.x */
1627 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1628 const struct tgsi_full_dst_register *dst,
1629 const struct tgsi_full_src_register *src,
1630 int stride_bytes_reg, int stride_bytes_chan)
1631 {
1632 struct tgsi_full_dst_register reg;
1633 ubyte *name, *index, *array_first;
1634 int r;
1635 int param;
1636 struct tgsi_shader_info *info = &ctx->info;
1637 /* Set the register description. The address computation is the same
1638 * for sources and destinations. */
1639 if (src) {
1640 reg.Register.File = src->Register.File;
1641 reg.Register.Index = src->Register.Index;
1642 reg.Register.Indirect = src->Register.Indirect;
1643 reg.Register.Dimension = src->Register.Dimension;
1644 reg.Indirect = src->Indirect;
1645 reg.Dimension = src->Dimension;
1646 reg.DimIndirect = src->DimIndirect;
1647 } else
1648 reg = *dst;
1649
1650 /* If the register is 2-dimensional (e.g. an array of vertices
1651 * in a primitive), calculate the base address of the vertex. */
1652 if (reg.Register.Dimension) {
1653 int sel, chan;
1654 if (reg.Dimension.Indirect) {
1655 unsigned addr_reg;
1656 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1657
1658 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1659 /* pull the value from index_reg */
1660 sel = addr_reg;
1661 chan = 0;
1662 } else {
1663 sel = V_SQ_ALU_SRC_LITERAL;
1664 chan = reg.Dimension.Index;
1665 }
1666
1667 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1668 temp_reg, 0,
1669 stride_bytes_reg, stride_bytes_chan,
1670 sel, chan,
1671 temp_reg, 0);
1672 if (r)
1673 return r;
1674 }
1675
1676 if (reg.Register.File == TGSI_FILE_INPUT) {
1677 name = info->input_semantic_name;
1678 index = info->input_semantic_index;
1679 array_first = info->input_array_first;
1680 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1681 name = info->output_semantic_name;
1682 index = info->output_semantic_index;
1683 array_first = info->output_array_first;
1684 } else {
1685 assert(0);
1686 return -1;
1687 }
1688 if (reg.Register.Indirect) {
1689 int addr_reg;
1690 int first;
1691 /* Add the relative address of the element. */
1692 if (reg.Indirect.ArrayID)
1693 first = array_first[reg.Indirect.ArrayID];
1694 else
1695 first = reg.Register.Index;
1696
1697 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
1698
1699 /* pull the value from index_reg */
1700 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1701 temp_reg, 0,
1702 V_SQ_ALU_SRC_LITERAL, 16,
1703 addr_reg, 0,
1704 temp_reg, 0);
1705 if (r)
1706 return r;
1707
1708 param = r600_get_lds_unique_index(name[first],
1709 index[first]);
1710
1711 } else {
1712 param = r600_get_lds_unique_index(name[reg.Register.Index],
1713 index[reg.Register.Index]);
1714 }
1715
1716 /* add to base_addr - passed in temp_reg.x */
1717 if (param) {
1718 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1719 temp_reg, 0,
1720 temp_reg, 0,
1721 V_SQ_ALU_SRC_LITERAL, param * 16);
1722 if (r)
1723 return r;
1724
1725 }
1726 return 0;
1727 }
1728
1729 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
1730 unsigned dst_reg)
1731 {
1732 struct r600_bytecode_alu alu;
1733 int r, i;
1734
1735 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
1736 ctx->bc->force_add_cf = 1;
1737 for (i = 1; i < 4; i++) {
1738 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1739 temp_reg, i,
1740 temp_reg, 0,
1741 V_SQ_ALU_SRC_LITERAL, 4 * i);
1742 if (r)
1743 return r;
1744 }
1745 for (i = 0; i < 4; i++) {
1746 /* emit an LDS_READ_RET */
1747 memset(&alu, 0, sizeof(alu));
1748 alu.op = LDS_OP1_LDS_READ_RET;
1749 alu.src[0].sel = temp_reg;
1750 alu.src[0].chan = i;
1751 alu.src[1].sel = V_SQ_ALU_SRC_0;
1752 alu.src[2].sel = V_SQ_ALU_SRC_0;
1753 alu.dst.chan = 0;
1754 alu.is_lds_idx_op = true;
1755 alu.last = 1;
1756 r = r600_bytecode_add_alu(ctx->bc, &alu);
1757 if (r)
1758 return r;
1759 }
1760 for (i = 0; i < 4; i++) {
1761 /* then read from LDS_OQ_A_POP */
1762 memset(&alu, 0, sizeof(alu));
1763
1764 alu.op = ALU_OP1_MOV;
1765 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
1766 alu.src[0].chan = 0;
1767 alu.dst.sel = dst_reg;
1768 alu.dst.chan = i;
1769 alu.dst.write = 1;
1770 alu.last = 1;
1771 r = r600_bytecode_add_alu(ctx->bc, &alu);
1772 if (r)
1773 return r;
1774 }
1775 return 0;
1776 }
1777
1778 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1779 {
1780 int r;
1781 unsigned temp_reg = r600_get_temp(ctx);
1782
1783 r = get_lds_offset0(ctx, 2, temp_reg,
1784 src->Register.Dimension ? false : true);
1785 if (r)
1786 return r;
1787
1788 /* the base address is now in temp.x */
1789 r = r600_get_byte_address(ctx, temp_reg,
1790 NULL, src, ctx->tess_output_info, 1);
1791 if (r)
1792 return r;
1793
1794 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1795 if (r)
1796 return r;
1797 return 0;
1798 }
1799
1800 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1801 {
1802 int r;
1803 unsigned temp_reg = r600_get_temp(ctx);
1804
1805 /* t.x = ips * r0.y */
1806 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
1807 temp_reg, 0,
1808 ctx->tess_input_info, 0,
1809 0, 1);
1810
1811 if (r)
1812 return r;
1813
1814 /* the base address is now in temp.x */
1815 r = r600_get_byte_address(ctx, temp_reg,
1816 NULL, src, ctx->tess_input_info, 1);
1817 if (r)
1818 return r;
1819
1820 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1821 if (r)
1822 return r;
1823 return 0;
1824 }
1825
1826 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1827 {
1828 int r;
1829 unsigned temp_reg = r600_get_temp(ctx);
1830
1831 r = get_lds_offset0(ctx, 1, temp_reg,
1832 src->Register.Dimension ? false : true);
1833 if (r)
1834 return r;
1835 /* the base address is now in temp.x */
1836 r = r600_get_byte_address(ctx, temp_reg,
1837 NULL, src,
1838 ctx->tess_output_info, 1);
1839 if (r)
1840 return r;
1841
1842 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1843 if (r)
1844 return r;
1845 return 0;
1846 }
1847
1848 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
1849 {
1850 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1851 unsigned i;
1852
1853 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1854 struct tgsi_full_src_register *src = &inst->Src[i];
1855
1856 if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
1857 int treg = r600_get_temp(ctx);
1858 fetch_tes_input(ctx, src, treg);
1859 ctx->src[i].sel = treg;
1860 ctx->src[i].rel = 0;
1861 }
1862 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
1863 int treg = r600_get_temp(ctx);
1864 fetch_tcs_input(ctx, src, treg);
1865 ctx->src[i].sel = treg;
1866 ctx->src[i].rel = 0;
1867 }
1868 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
1869 int treg = r600_get_temp(ctx);
1870 fetch_tcs_output(ctx, src, treg);
1871 ctx->src[i].sel = treg;
1872 ctx->src[i].rel = 0;
1873 }
1874 }
1875 return 0;
1876 }
1877
1878 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1879 {
1880 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1881 struct r600_bytecode_alu alu;
1882 int i, j, k, nconst, r;
1883
1884 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1885 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1886 nconst++;
1887 }
1888 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1889 }
1890 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1891 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1892 continue;
1893 }
1894
1895 if (ctx->src[i].rel) {
1896 int chan = inst->Src[i].Indirect.Swizzle;
1897 int treg = r600_get_temp(ctx);
1898 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1899 return r;
1900
1901 ctx->src[i].kc_bank = 0;
1902 ctx->src[i].kc_rel = 0;
1903 ctx->src[i].sel = treg;
1904 ctx->src[i].rel = 0;
1905 j--;
1906 } else if (j > 0) {
1907 int treg = r600_get_temp(ctx);
1908 for (k = 0; k < 4; k++) {
1909 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1910 alu.op = ALU_OP1_MOV;
1911 alu.src[0].sel = ctx->src[i].sel;
1912 alu.src[0].chan = k;
1913 alu.src[0].rel = ctx->src[i].rel;
1914 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1915 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1916 alu.dst.sel = treg;
1917 alu.dst.chan = k;
1918 alu.dst.write = 1;
1919 if (k == 3)
1920 alu.last = 1;
1921 r = r600_bytecode_add_alu(ctx->bc, &alu);
1922 if (r)
1923 return r;
1924 }
1925 ctx->src[i].sel = treg;
1926 ctx->src[i].rel =0;
1927 j--;
1928 }
1929 }
1930 return 0;
1931 }
1932
1933 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1934 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1935 {
1936 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1937 struct r600_bytecode_alu alu;
1938 int i, j, k, nliteral, r;
1939
1940 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1941 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1942 nliteral++;
1943 }
1944 }
1945 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1946 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1947 int treg = r600_get_temp(ctx);
1948 for (k = 0; k < 4; k++) {
1949 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1950 alu.op = ALU_OP1_MOV;
1951 alu.src[0].sel = ctx->src[i].sel;
1952 alu.src[0].chan = k;
1953 alu.src[0].value = ctx->src[i].value[k];
1954 alu.dst.sel = treg;
1955 alu.dst.chan = k;
1956 alu.dst.write = 1;
1957 if (k == 3)
1958 alu.last = 1;
1959 r = r600_bytecode_add_alu(ctx->bc, &alu);
1960 if (r)
1961 return r;
1962 }
1963 ctx->src[i].sel = treg;
1964 j--;
1965 }
1966 }
1967 return 0;
1968 }
1969
1970 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1971 {
1972 int i, r, count = ctx->shader->ninput;
1973
1974 for (i = 0; i < count; i++) {
1975 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1976 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1977 if (r)
1978 return r;
1979 }
1980 }
1981 return 0;
1982 }
1983
1984 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
1985 int stream, unsigned *stream_item_size)
1986 {
1987 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1988 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
1989 int i, j, r;
1990
1991 /* Sanity checking. */
1992 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
1993 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
1994 r = -EINVAL;
1995 goto out_err;
1996 }
1997 for (i = 0; i < so->num_outputs; i++) {
1998 if (so->output[i].output_buffer >= 4) {
1999 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2000 so->output[i].output_buffer);
2001 r = -EINVAL;
2002 goto out_err;
2003 }
2004 }
2005
2006 /* Initialize locations where the outputs are stored. */
2007 for (i = 0; i < so->num_outputs; i++) {
2008
2009 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2010 start_comp[i] = so->output[i].start_component;
2011 /* Lower outputs with dst_offset < start_component.
2012 *
2013 * We can only output 4D vectors with a write mask, e.g. we can
2014 * only output the W component at offset 3, etc. If we want
2015 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2016 * to move it to X and output X. */
2017 if (so->output[i].dst_offset < so->output[i].start_component) {
2018 unsigned tmp = r600_get_temp(ctx);
2019
2020 for (j = 0; j < so->output[i].num_components; j++) {
2021 struct r600_bytecode_alu alu;
2022 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2023 alu.op = ALU_OP1_MOV;
2024 alu.src[0].sel = so_gpr[i];
2025 alu.src[0].chan = so->output[i].start_component + j;
2026
2027 alu.dst.sel = tmp;
2028 alu.dst.chan = j;
2029 alu.dst.write = 1;
2030 if (j == so->output[i].num_components - 1)
2031 alu.last = 1;
2032 r = r600_bytecode_add_alu(ctx->bc, &alu);
2033 if (r)
2034 return r;
2035 }
2036 start_comp[i] = 0;
2037 so_gpr[i] = tmp;
2038 }
2039 }
2040
2041 /* Write outputs to buffers. */
2042 for (i = 0; i < so->num_outputs; i++) {
2043 struct r600_bytecode_output output;
2044
2045 if (stream != -1 && stream != so->output[i].output_buffer)
2046 continue;
2047
2048 memset(&output, 0, sizeof(struct r600_bytecode_output));
2049 output.gpr = so_gpr[i];
2050 output.elem_size = so->output[i].num_components - 1;
2051 if (output.elem_size == 2)
2052 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2053 output.array_base = so->output[i].dst_offset - start_comp[i];
2054 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2055 output.burst_count = 1;
2056 /* array_size is an upper limit for the burst_count
2057 * with MEM_STREAM instructions */
2058 output.array_size = 0xFFF;
2059 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2060
2061 if (ctx->bc->chip_class >= EVERGREEN) {
2062 switch (so->output[i].output_buffer) {
2063 case 0:
2064 output.op = CF_OP_MEM_STREAM0_BUF0;
2065 break;
2066 case 1:
2067 output.op = CF_OP_MEM_STREAM0_BUF1;
2068 break;
2069 case 2:
2070 output.op = CF_OP_MEM_STREAM0_BUF2;
2071 break;
2072 case 3:
2073 output.op = CF_OP_MEM_STREAM0_BUF3;
2074 break;
2075 }
2076 output.op += so->output[i].stream * 4;
2077 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2078 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2079 } else {
2080 switch (so->output[i].output_buffer) {
2081 case 0:
2082 output.op = CF_OP_MEM_STREAM0;
2083 break;
2084 case 1:
2085 output.op = CF_OP_MEM_STREAM1;
2086 break;
2087 case 2:
2088 output.op = CF_OP_MEM_STREAM2;
2089 break;
2090 case 3:
2091 output.op = CF_OP_MEM_STREAM3;
2092 break;
2093 }
2094 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2095 }
2096 r = r600_bytecode_add_output(ctx->bc, &output);
2097 if (r)
2098 goto out_err;
2099 }
2100 return 0;
2101 out_err:
2102 return r;
2103 }
2104
2105 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2106 {
2107 struct r600_bytecode_alu alu;
2108 unsigned reg;
2109
2110 if (!ctx->shader->vs_out_edgeflag)
2111 return;
2112
2113 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2114
2115 /* clamp(x, 0, 1) */
2116 memset(&alu, 0, sizeof(alu));
2117 alu.op = ALU_OP1_MOV;
2118 alu.src[0].sel = reg;
2119 alu.dst.sel = reg;
2120 alu.dst.write = 1;
2121 alu.dst.clamp = 1;
2122 alu.last = 1;
2123 r600_bytecode_add_alu(ctx->bc, &alu);
2124
2125 memset(&alu, 0, sizeof(alu));
2126 alu.op = ALU_OP1_FLT_TO_INT;
2127 alu.src[0].sel = reg;
2128 alu.dst.sel = reg;
2129 alu.dst.write = 1;
2130 alu.last = 1;
2131 r600_bytecode_add_alu(ctx->bc, &alu);
2132 }
2133
2134 static int generate_gs_copy_shader(struct r600_context *rctx,
2135 struct r600_pipe_shader *gs,
2136 struct pipe_stream_output_info *so)
2137 {
2138 struct r600_shader_ctx ctx = {};
2139 struct r600_shader *gs_shader = &gs->shader;
2140 struct r600_pipe_shader *cshader;
2141 int ocnt = gs_shader->noutput;
2142 struct r600_bytecode_alu alu;
2143 struct r600_bytecode_vtx vtx;
2144 struct r600_bytecode_output output;
2145 struct r600_bytecode_cf *cf_jump, *cf_pop,
2146 *last_exp_pos = NULL, *last_exp_param = NULL;
2147 int i, j, next_clip_pos = 61, next_param = 0;
2148 int ring;
2149 bool only_ring_0 = true;
2150 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2151 if (!cshader)
2152 return 0;
2153
2154 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2155 sizeof(struct r600_shader_io));
2156
2157 cshader->shader.noutput = ocnt;
2158
2159 ctx.shader = &cshader->shader;
2160 ctx.bc = &ctx.shader->bc;
2161 ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
2162
2163 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2164 rctx->screen->has_compressed_msaa_texturing);
2165
2166 ctx.bc->isa = rctx->isa;
2167
2168 cf_jump = NULL;
2169 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2170
2171 /* R0.x = R0.x & 0x3fffffff */
2172 memset(&alu, 0, sizeof(alu));
2173 alu.op = ALU_OP2_AND_INT;
2174 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2175 alu.src[1].value = 0x3fffffff;
2176 alu.dst.write = 1;
2177 r600_bytecode_add_alu(ctx.bc, &alu);
2178
2179 /* R0.y = R0.x >> 30 */
2180 memset(&alu, 0, sizeof(alu));
2181 alu.op = ALU_OP2_LSHR_INT;
2182 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2183 alu.src[1].value = 0x1e;
2184 alu.dst.chan = 1;
2185 alu.dst.write = 1;
2186 alu.last = 1;
2187 r600_bytecode_add_alu(ctx.bc, &alu);
2188
2189 /* fetch vertex data from GSVS ring */
2190 for (i = 0; i < ocnt; ++i) {
2191 struct r600_shader_io *out = &ctx.shader->output[i];
2192
2193 out->gpr = i + 1;
2194 out->ring_offset = i * 16;
2195
2196 memset(&vtx, 0, sizeof(vtx));
2197 vtx.op = FETCH_OP_VFETCH;
2198 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2199 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2200 vtx.mega_fetch_count = 16;
2201 vtx.offset = out->ring_offset;
2202 vtx.dst_gpr = out->gpr;
2203 vtx.src_gpr = 0;
2204 vtx.dst_sel_x = 0;
2205 vtx.dst_sel_y = 1;
2206 vtx.dst_sel_z = 2;
2207 vtx.dst_sel_w = 3;
2208 if (rctx->b.chip_class >= EVERGREEN) {
2209 vtx.use_const_fields = 1;
2210 } else {
2211 vtx.data_format = FMT_32_32_32_32_FLOAT;
2212 }
2213
2214 r600_bytecode_add_vtx(ctx.bc, &vtx);
2215 }
2216 ctx.temp_reg = i + 1;
2217 for (ring = 3; ring >= 0; --ring) {
2218 bool enabled = false;
2219 for (i = 0; i < so->num_outputs; i++) {
2220 if (so->output[i].stream == ring) {
2221 enabled = true;
2222 if (ring > 0)
2223 only_ring_0 = false;
2224 break;
2225 }
2226 }
2227 if (ring != 0 && !enabled) {
2228 cshader->shader.ring_item_sizes[ring] = 0;
2229 continue;
2230 }
2231
2232 if (cf_jump) {
2233 // Patch up jump label
2234 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2235 cf_pop = ctx.bc->cf_last;
2236
2237 cf_jump->cf_addr = cf_pop->id + 2;
2238 cf_jump->pop_count = 1;
2239 cf_pop->cf_addr = cf_pop->id + 2;
2240 cf_pop->pop_count = 1;
2241 }
2242
2243 /* PRED_SETE_INT __, R0.y, ring */
2244 memset(&alu, 0, sizeof(alu));
2245 alu.op = ALU_OP2_PRED_SETE_INT;
2246 alu.src[0].chan = 1;
2247 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2248 alu.src[1].value = ring;
2249 alu.execute_mask = 1;
2250 alu.update_pred = 1;
2251 alu.last = 1;
2252 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2253
2254 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2255 cf_jump = ctx.bc->cf_last;
2256
2257 if (enabled)
2258 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2259 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2260 }
2261
2262 /* bc adds nops - copy it */
2263 if (ctx.bc->chip_class == R600) {
2264 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2265 alu.op = ALU_OP0_NOP;
2266 alu.last = 1;
2267 r600_bytecode_add_alu(ctx.bc, &alu);
2268
2269 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2270 }
2271
2272 /* export vertex data */
2273 /* XXX factor out common code with r600_shader_from_tgsi ? */
2274 for (i = 0; i < ocnt; ++i) {
2275 struct r600_shader_io *out = &ctx.shader->output[i];
2276 bool instream0 = true;
2277 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2278 continue;
2279
2280 for (j = 0; j < so->num_outputs; j++) {
2281 if (so->output[j].register_index == i) {
2282 if (so->output[j].stream == 0)
2283 break;
2284 if (so->output[j].stream > 0)
2285 instream0 = false;
2286 }
2287 }
2288 if (!instream0)
2289 continue;
2290 memset(&output, 0, sizeof(output));
2291 output.gpr = out->gpr;
2292 output.elem_size = 3;
2293 output.swizzle_x = 0;
2294 output.swizzle_y = 1;
2295 output.swizzle_z = 2;
2296 output.swizzle_w = 3;
2297 output.burst_count = 1;
2298 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2299 output.op = CF_OP_EXPORT;
2300 switch (out->name) {
2301 case TGSI_SEMANTIC_POSITION:
2302 output.array_base = 60;
2303 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2304 break;
2305
2306 case TGSI_SEMANTIC_PSIZE:
2307 output.array_base = 61;
2308 if (next_clip_pos == 61)
2309 next_clip_pos = 62;
2310 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2311 output.swizzle_y = 7;
2312 output.swizzle_z = 7;
2313 output.swizzle_w = 7;
2314 ctx.shader->vs_out_misc_write = 1;
2315 ctx.shader->vs_out_point_size = 1;
2316 break;
2317 case TGSI_SEMANTIC_LAYER:
2318 if (out->spi_sid) {
2319 /* duplicate it as PARAM to pass to the pixel shader */
2320 output.array_base = next_param++;
2321 r600_bytecode_add_output(ctx.bc, &output);
2322 last_exp_param = ctx.bc->cf_last;
2323 }
2324 output.array_base = 61;
2325 if (next_clip_pos == 61)
2326 next_clip_pos = 62;
2327 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2328 output.swizzle_x = 7;
2329 output.swizzle_y = 7;
2330 output.swizzle_z = 0;
2331 output.swizzle_w = 7;
2332 ctx.shader->vs_out_misc_write = 1;
2333 ctx.shader->vs_out_layer = 1;
2334 break;
2335 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2336 if (out->spi_sid) {
2337 /* duplicate it as PARAM to pass to the pixel shader */
2338 output.array_base = next_param++;
2339 r600_bytecode_add_output(ctx.bc, &output);
2340 last_exp_param = ctx.bc->cf_last;
2341 }
2342 output.array_base = 61;
2343 if (next_clip_pos == 61)
2344 next_clip_pos = 62;
2345 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2346 ctx.shader->vs_out_misc_write = 1;
2347 ctx.shader->vs_out_viewport = 1;
2348 output.swizzle_x = 7;
2349 output.swizzle_y = 7;
2350 output.swizzle_z = 7;
2351 output.swizzle_w = 0;
2352 break;
2353 case TGSI_SEMANTIC_CLIPDIST:
2354 /* spi_sid is 0 for clipdistance outputs that were generated
2355 * for clipvertex - we don't need to pass them to PS */
2356 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2357 if (out->spi_sid) {
2358 /* duplicate it as PARAM to pass to the pixel shader */
2359 output.array_base = next_param++;
2360 r600_bytecode_add_output(ctx.bc, &output);
2361 last_exp_param = ctx.bc->cf_last;
2362 }
2363 output.array_base = next_clip_pos++;
2364 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2365 break;
2366 case TGSI_SEMANTIC_FOG:
2367 output.swizzle_y = 4; /* 0 */
2368 output.swizzle_z = 4; /* 0 */
2369 output.swizzle_w = 5; /* 1 */
2370 break;
2371 default:
2372 output.array_base = next_param++;
2373 break;
2374 }
2375 r600_bytecode_add_output(ctx.bc, &output);
2376 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2377 last_exp_param = ctx.bc->cf_last;
2378 else
2379 last_exp_pos = ctx.bc->cf_last;
2380 }
2381
2382 if (!last_exp_pos) {
2383 memset(&output, 0, sizeof(output));
2384 output.gpr = 0;
2385 output.elem_size = 3;
2386 output.swizzle_x = 7;
2387 output.swizzle_y = 7;
2388 output.swizzle_z = 7;
2389 output.swizzle_w = 7;
2390 output.burst_count = 1;
2391 output.type = 2;
2392 output.op = CF_OP_EXPORT;
2393 output.array_base = 60;
2394 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2395 r600_bytecode_add_output(ctx.bc, &output);
2396 last_exp_pos = ctx.bc->cf_last;
2397 }
2398
2399 if (!last_exp_param) {
2400 memset(&output, 0, sizeof(output));
2401 output.gpr = 0;
2402 output.elem_size = 3;
2403 output.swizzle_x = 7;
2404 output.swizzle_y = 7;
2405 output.swizzle_z = 7;
2406 output.swizzle_w = 7;
2407 output.burst_count = 1;
2408 output.type = 2;
2409 output.op = CF_OP_EXPORT;
2410 output.array_base = next_param++;
2411 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2412 r600_bytecode_add_output(ctx.bc, &output);
2413 last_exp_param = ctx.bc->cf_last;
2414 }
2415
2416 last_exp_pos->op = CF_OP_EXPORT_DONE;
2417 last_exp_param->op = CF_OP_EXPORT_DONE;
2418
2419 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2420 cf_pop = ctx.bc->cf_last;
2421
2422 cf_jump->cf_addr = cf_pop->id + 2;
2423 cf_jump->pop_count = 1;
2424 cf_pop->cf_addr = cf_pop->id + 2;
2425 cf_pop->pop_count = 1;
2426
2427 if (ctx.bc->chip_class == CAYMAN)
2428 cm_bytecode_add_cf_end(ctx.bc);
2429 else {
2430 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2431 ctx.bc->cf_last->end_of_program = 1;
2432 }
2433
2434 gs->gs_copy_shader = cshader;
2435 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2436
2437 ctx.bc->nstack = 1;
2438
2439 return r600_bytecode_build(ctx.bc);
2440 }
2441
2442 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2443 {
2444 if (ind) {
2445 struct r600_bytecode_alu alu;
2446 int r;
2447
2448 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2449 alu.op = ALU_OP2_ADD_INT;
2450 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2451 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2452 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2453 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2454 alu.dst.write = 1;
2455 alu.last = 1;
2456 r = r600_bytecode_add_alu(ctx->bc, &alu);
2457 if (r)
2458 return r;
2459 }
2460 return 0;
2461 }
2462
2463 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind)
2464 {
2465 struct r600_bytecode_output output;
2466 int i, k, ring_offset;
2467 int effective_stream = stream == -1 ? 0 : stream;
2468 int idx = 0;
2469
2470 for (i = 0; i < ctx->shader->noutput; i++) {
2471 if (ctx->gs_for_vs) {
2472 /* for ES we need to lookup corresponding ring offset expected by GS
2473 * (map this output to GS input by name and sid) */
2474 /* FIXME precompute offsets */
2475 ring_offset = -1;
2476 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2477 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2478 struct r600_shader_io *out = &ctx->shader->output[i];
2479 if (in->name == out->name && in->sid == out->sid)
2480 ring_offset = in->ring_offset;
2481 }
2482
2483 if (ring_offset == -1)
2484 continue;
2485 } else {
2486 ring_offset = idx * 16;
2487 idx++;
2488 }
2489
2490 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2491 continue;
2492 /* next_ring_offset after parsing input decls contains total size of
2493 * single vertex data, gs_next_vertex - current vertex index */
2494 if (!ind)
2495 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2496
2497 memset(&output, 0, sizeof(struct r600_bytecode_output));
2498 output.gpr = ctx->shader->output[i].gpr;
2499 output.elem_size = 3;
2500 output.comp_mask = 0xF;
2501 output.burst_count = 1;
2502
2503 if (ind)
2504 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2505 else
2506 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2507
2508 switch (stream) {
2509 default:
2510 case 0:
2511 output.op = CF_OP_MEM_RING; break;
2512 case 1:
2513 output.op = CF_OP_MEM_RING1; break;
2514 case 2:
2515 output.op = CF_OP_MEM_RING2; break;
2516 case 3:
2517 output.op = CF_OP_MEM_RING3; break;
2518 }
2519
2520 if (ind) {
2521 output.array_base = ring_offset >> 2; /* in dwords */
2522 output.array_size = 0xfff;
2523 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2524 } else
2525 output.array_base = ring_offset >> 2; /* in dwords */
2526 r600_bytecode_add_output(ctx->bc, &output);
2527 }
2528
2529 ++ctx->gs_next_vertex;
2530 return 0;
2531 }
2532
2533
2534 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2535 {
2536 int r;
2537 struct r600_bytecode_vtx vtx;
2538 int temp_val = ctx->temp_reg;
2539 /* need to store the TCS output somewhere */
2540 r = single_alu_op2(ctx, ALU_OP1_MOV,
2541 temp_val, 0,
2542 V_SQ_ALU_SRC_LITERAL, 0,
2543 0, 0);
2544 if (r)
2545 return r;
2546
2547 /* used by VS/TCS */
2548 if (ctx->tess_input_info) {
2549 /* fetch tcs input values into resv space */
2550 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2551 vtx.op = FETCH_OP_VFETCH;
2552 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2553 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2554 vtx.mega_fetch_count = 16;
2555 vtx.data_format = FMT_32_32_32_32;
2556 vtx.num_format_all = 2;
2557 vtx.format_comp_all = 1;
2558 vtx.use_const_fields = 0;
2559 vtx.endian = r600_endian_swap(32);
2560 vtx.srf_mode_all = 1;
2561 vtx.offset = 0;
2562 vtx.dst_gpr = ctx->tess_input_info;
2563 vtx.dst_sel_x = 0;
2564 vtx.dst_sel_y = 1;
2565 vtx.dst_sel_z = 2;
2566 vtx.dst_sel_w = 3;
2567 vtx.src_gpr = temp_val;
2568 vtx.src_sel_x = 0;
2569
2570 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2571 if (r)
2572 return r;
2573 }
2574
2575 /* used by TCS/TES */
2576 if (ctx->tess_output_info) {
2577 /* fetch tcs output values into resv space */
2578 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2579 vtx.op = FETCH_OP_VFETCH;
2580 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2581 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2582 vtx.mega_fetch_count = 16;
2583 vtx.data_format = FMT_32_32_32_32;
2584 vtx.num_format_all = 2;
2585 vtx.format_comp_all = 1;
2586 vtx.use_const_fields = 0;
2587 vtx.endian = r600_endian_swap(32);
2588 vtx.srf_mode_all = 1;
2589 vtx.offset = 16;
2590 vtx.dst_gpr = ctx->tess_output_info;
2591 vtx.dst_sel_x = 0;
2592 vtx.dst_sel_y = 1;
2593 vtx.dst_sel_z = 2;
2594 vtx.dst_sel_w = 3;
2595 vtx.src_gpr = temp_val;
2596 vtx.src_sel_x = 0;
2597
2598 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2599 if (r)
2600 return r;
2601 }
2602 return 0;
2603 }
2604
2605 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2606 {
2607 int i, j, r;
2608 int temp_reg;
2609
2610 /* fetch tcs input values into input_vals */
2611 ctx->tess_input_info = r600_get_temp(ctx);
2612 ctx->tess_output_info = 0;
2613 r = r600_fetch_tess_io_info(ctx);
2614 if (r)
2615 return r;
2616
2617 temp_reg = r600_get_temp(ctx);
2618 /* dst reg contains LDS address stride * idx */
2619 /* MUL vertexID, vertex_dw_stride */
2620 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2621 temp_reg, 0,
2622 ctx->tess_input_info, 1,
2623 0, 1); /* rel id in r0.y? */
2624 if (r)
2625 return r;
2626
2627 for (i = 0; i < ctx->shader->noutput; i++) {
2628 struct r600_bytecode_alu alu;
2629 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2630
2631 if (param) {
2632 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2633 temp_reg, 1,
2634 temp_reg, 0,
2635 V_SQ_ALU_SRC_LITERAL, param * 16);
2636 if (r)
2637 return r;
2638 }
2639
2640 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2641 temp_reg, 2,
2642 temp_reg, param ? 1 : 0,
2643 V_SQ_ALU_SRC_LITERAL, 8);
2644 if (r)
2645 return r;
2646
2647
2648 for (j = 0; j < 2; j++) {
2649 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2650 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2651 alu.op = LDS_OP3_LDS_WRITE_REL;
2652 alu.src[0].sel = temp_reg;
2653 alu.src[0].chan = chan;
2654 alu.src[1].sel = ctx->shader->output[i].gpr;
2655 alu.src[1].chan = j * 2;
2656 alu.src[2].sel = ctx->shader->output[i].gpr;
2657 alu.src[2].chan = (j * 2) + 1;
2658 alu.last = 1;
2659 alu.dst.chan = 0;
2660 alu.lds_idx = 1;
2661 alu.is_lds_idx_op = true;
2662 r = r600_bytecode_add_alu(ctx->bc, &alu);
2663 if (r)
2664 return r;
2665 }
2666 }
2667 return 0;
2668 }
2669
2670 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
2671 {
2672 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2673 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
2674 int i, r, lasti;
2675 int temp_reg = r600_get_temp(ctx);
2676 struct r600_bytecode_alu alu;
2677 unsigned write_mask = dst->Register.WriteMask;
2678
2679 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
2680 return 0;
2681
2682 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
2683 if (r)
2684 return r;
2685
2686 /* the base address is now in temp.x */
2687 r = r600_get_byte_address(ctx, temp_reg,
2688 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
2689 if (r)
2690 return r;
2691
2692 /* LDS write */
2693 lasti = tgsi_last_instruction(write_mask);
2694 for (i = 1; i <= lasti; i++) {
2695
2696 if (!(write_mask & (1 << i)))
2697 continue;
2698 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2699 temp_reg, i,
2700 temp_reg, 0,
2701 V_SQ_ALU_SRC_LITERAL, 4 * i);
2702 if (r)
2703 return r;
2704 }
2705
2706 for (i = 0; i <= lasti; i++) {
2707 if (!(write_mask & (1 << i)))
2708 continue;
2709
2710 if ((i == 0 && ((write_mask & 3) == 3)) ||
2711 (i == 2 && ((write_mask & 0xc) == 0xc))) {
2712 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2713 alu.op = LDS_OP3_LDS_WRITE_REL;
2714 alu.src[0].sel = temp_reg;
2715 alu.src[0].chan = i;
2716
2717 alu.src[1].sel = dst->Register.Index;
2718 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2719 alu.src[1].chan = i;
2720
2721 alu.src[2].sel = dst->Register.Index;
2722 alu.src[2].sel += ctx->file_offset[dst->Register.File];
2723 alu.src[2].chan = i + 1;
2724 alu.lds_idx = 1;
2725 alu.dst.chan = 0;
2726 alu.last = 1;
2727 alu.is_lds_idx_op = true;
2728 r = r600_bytecode_add_alu(ctx->bc, &alu);
2729 if (r)
2730 return r;
2731 i += 1;
2732 continue;
2733 }
2734 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2735 alu.op = LDS_OP2_LDS_WRITE;
2736 alu.src[0].sel = temp_reg;
2737 alu.src[0].chan = i;
2738
2739 alu.src[1].sel = dst->Register.Index;
2740 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2741 alu.src[1].chan = i;
2742
2743 alu.src[2].sel = V_SQ_ALU_SRC_0;
2744 alu.dst.chan = 0;
2745 alu.last = 1;
2746 alu.is_lds_idx_op = true;
2747 r = r600_bytecode_add_alu(ctx->bc, &alu);
2748 if (r)
2749 return r;
2750 }
2751 return 0;
2752 }
2753
2754 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
2755 int output_idx)
2756 {
2757 int param;
2758 unsigned temp_reg = r600_get_temp(ctx);
2759 unsigned name = ctx->shader->output[output_idx].name;
2760 int dreg = ctx->shader->output[output_idx].gpr;
2761 int r;
2762
2763 param = r600_get_lds_unique_index(name, 0);
2764 r = get_lds_offset0(ctx, 1, temp_reg, true);
2765 if (r)
2766 return r;
2767
2768 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2769 temp_reg, 0,
2770 temp_reg, 0,
2771 V_SQ_ALU_SRC_LITERAL, param * 16);
2772 if (r)
2773 return r;
2774
2775 do_lds_fetch_values(ctx, temp_reg, dreg);
2776 return 0;
2777 }
2778
2779 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
2780 {
2781 unsigned i;
2782 int stride, outer_comps, inner_comps;
2783 int tessinner_idx = -1, tessouter_idx = -1;
2784 int r;
2785 int temp_reg = r600_get_temp(ctx);
2786 int treg[3] = {-1, -1, -1};
2787 struct r600_bytecode_alu alu;
2788 struct r600_bytecode_cf *cf_jump, *cf_pop;
2789
2790 /* only execute factor emission for invocation 0 */
2791 /* PRED_SETE_INT __, R0.x, 0 */
2792 memset(&alu, 0, sizeof(alu));
2793 alu.op = ALU_OP2_PRED_SETE_INT;
2794 alu.src[0].chan = 2;
2795 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2796 alu.execute_mask = 1;
2797 alu.update_pred = 1;
2798 alu.last = 1;
2799 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2800
2801 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
2802 cf_jump = ctx->bc->cf_last;
2803
2804 treg[0] = r600_get_temp(ctx);
2805 switch (ctx->shader->tcs_prim_mode) {
2806 case PIPE_PRIM_LINES:
2807 stride = 8; /* 2 dwords, 1 vec2 store */
2808 outer_comps = 2;
2809 inner_comps = 0;
2810 break;
2811 case PIPE_PRIM_TRIANGLES:
2812 stride = 16; /* 4 dwords, 1 vec4 store */
2813 outer_comps = 3;
2814 inner_comps = 1;
2815 treg[1] = r600_get_temp(ctx);
2816 break;
2817 case PIPE_PRIM_QUADS:
2818 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2819 outer_comps = 4;
2820 inner_comps = 2;
2821 treg[1] = r600_get_temp(ctx);
2822 treg[2] = r600_get_temp(ctx);
2823 break;
2824 default:
2825 assert(0);
2826 return -1;
2827 }
2828
2829 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2830 /* TF_WRITE takes index in R.x, value in R.y */
2831 for (i = 0; i < ctx->shader->noutput; i++) {
2832 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSINNER)
2833 tessinner_idx = i;
2834 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSOUTER)
2835 tessouter_idx = i;
2836 }
2837
2838 if (tessouter_idx == -1)
2839 return -1;
2840
2841 if (tessinner_idx == -1 && inner_comps)
2842 return -1;
2843
2844 if (tessouter_idx != -1) {
2845 r = r600_tess_factor_read(ctx, tessouter_idx);
2846 if (r)
2847 return r;
2848 }
2849
2850 if (tessinner_idx != -1) {
2851 r = r600_tess_factor_read(ctx, tessinner_idx);
2852 if (r)
2853 return r;
2854 }
2855
2856 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2857 /* r.x = relpatchid(r0.y) * tf_stride */
2858
2859 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2860 /* add incoming r0.w to it: t.x = t.x + r0.w */
2861 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2862 temp_reg, 0,
2863 0, 1,
2864 V_SQ_ALU_SRC_LITERAL, stride,
2865 0, 3);
2866 if (r)
2867 return r;
2868
2869 for (i = 0; i < outer_comps + inner_comps; i++) {
2870 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
2871 int out_comp = i >= outer_comps ? i - outer_comps : i;
2872
2873 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2874 treg[i / 2], (2 * (i % 2)),
2875 temp_reg, 0,
2876 V_SQ_ALU_SRC_LITERAL, 4 * i);
2877 if (r)
2878 return r;
2879 r = single_alu_op2(ctx, ALU_OP1_MOV,
2880 treg[i / 2], 1 + (2 * (i%2)),
2881 ctx->shader->output[out_idx].gpr, out_comp,
2882 0, 0);
2883 if (r)
2884 return r;
2885 }
2886 for (i = 0; i < outer_comps + inner_comps; i++) {
2887 struct r600_bytecode_gds gds;
2888
2889 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
2890 gds.src_gpr = treg[i / 2];
2891 gds.src_sel_x = 2 * (i % 2);
2892 gds.src_sel_y = 1 + (2 * (i % 2));
2893 gds.src_sel_z = 4;
2894 gds.dst_sel_x = 7;
2895 gds.dst_sel_y = 7;
2896 gds.dst_sel_z = 7;
2897 gds.dst_sel_w = 7;
2898 gds.op = FETCH_OP_TF_WRITE;
2899 r = r600_bytecode_add_gds(ctx->bc, &gds);
2900 if (r)
2901 return r;
2902 }
2903
2904 // Patch up jump label
2905 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
2906 cf_pop = ctx->bc->cf_last;
2907
2908 cf_jump->cf_addr = cf_pop->id + 2;
2909 cf_jump->pop_count = 1;
2910 cf_pop->cf_addr = cf_pop->id + 2;
2911 cf_pop->pop_count = 1;
2912
2913 return 0;
2914 }
2915
2916 static int r600_shader_from_tgsi(struct r600_context *rctx,
2917 struct r600_pipe_shader *pipeshader,
2918 union r600_shader_key key)
2919 {
2920 struct r600_screen *rscreen = rctx->screen;
2921 struct r600_shader *shader = &pipeshader->shader;
2922 struct tgsi_token *tokens = pipeshader->selector->tokens;
2923 struct pipe_stream_output_info so = pipeshader->selector->so;
2924 struct tgsi_full_immediate *immediate;
2925 struct r600_shader_ctx ctx;
2926 struct r600_bytecode_output output[ARRAY_SIZE(shader->output)];
2927 unsigned output_done, noutput;
2928 unsigned opcode;
2929 int i, j, k, r = 0;
2930 int next_param_base = 0, next_clip_base;
2931 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
2932 bool indirect_gprs;
2933 bool ring_outputs = false;
2934 bool lds_outputs = false;
2935 bool lds_inputs = false;
2936 bool pos_emitted = false;
2937
2938 ctx.bc = &shader->bc;
2939 ctx.shader = shader;
2940 ctx.native_integers = true;
2941
2942 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
2943 rscreen->has_compressed_msaa_texturing);
2944 ctx.tokens = tokens;
2945 tgsi_scan_shader(tokens, &ctx.info);
2946 shader->indirect_files = ctx.info.indirect_files;
2947
2948 shader->uses_doubles = ctx.info.uses_doubles;
2949 shader->nsys_inputs = 0;
2950
2951 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
2952 tgsi_parse_init(&ctx.parse, tokens);
2953 ctx.type = ctx.info.processor;
2954 shader->processor_type = ctx.type;
2955 ctx.bc->type = shader->processor_type;
2956
2957 switch (ctx.type) {
2958 case PIPE_SHADER_VERTEX:
2959 shader->vs_as_gs_a = key.vs.as_gs_a;
2960 shader->vs_as_es = key.vs.as_es;
2961 shader->vs_as_ls = key.vs.as_ls;
2962 if (shader->vs_as_es)
2963 ring_outputs = true;
2964 if (shader->vs_as_ls)
2965 lds_outputs = true;
2966 break;
2967 case PIPE_SHADER_GEOMETRY:
2968 ring_outputs = true;
2969 break;
2970 case PIPE_SHADER_TESS_CTRL:
2971 shader->tcs_prim_mode = key.tcs.prim_mode;
2972 lds_outputs = true;
2973 lds_inputs = true;
2974 break;
2975 case PIPE_SHADER_TESS_EVAL:
2976 shader->tes_as_es = key.tes.as_es;
2977 lds_inputs = true;
2978 if (shader->tes_as_es)
2979 ring_outputs = true;
2980 break;
2981 case PIPE_SHADER_FRAGMENT:
2982 shader->two_side = key.ps.color_two_side;
2983 break;
2984 default:
2985 break;
2986 }
2987
2988 if (shader->vs_as_es || shader->tes_as_es) {
2989 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
2990 } else {
2991 ctx.gs_for_vs = NULL;
2992 }
2993
2994 ctx.next_ring_offset = 0;
2995 ctx.gs_out_ring_offset = 0;
2996 ctx.gs_next_vertex = 0;
2997 ctx.gs_stream_output_info = &so;
2998
2999 ctx.face_gpr = -1;
3000 ctx.fixed_pt_position_gpr = -1;
3001 ctx.fragcoord_input = -1;
3002 ctx.colors_used = 0;
3003 ctx.clip_vertex_write = 0;
3004
3005 shader->nr_ps_color_exports = 0;
3006 shader->nr_ps_max_color_exports = 0;
3007
3008
3009 /* register allocations */
3010 /* Values [0,127] correspond to GPR[0..127].
3011 * Values [128,159] correspond to constant buffer bank 0
3012 * Values [160,191] correspond to constant buffer bank 1
3013 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3014 * Values [256,287] correspond to constant buffer bank 2 (EG)
3015 * Values [288,319] correspond to constant buffer bank 3 (EG)
3016 * Other special values are shown in the list below.
3017 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3018 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3019 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3020 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3021 * 248 SQ_ALU_SRC_0: special constant 0.0.
3022 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3023 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3024 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3025 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3026 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3027 * 254 SQ_ALU_SRC_PV: previous vector result.
3028 * 255 SQ_ALU_SRC_PS: previous scalar result.
3029 */
3030 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3031 ctx.file_offset[i] = 0;
3032 }
3033
3034 if (ctx.type == PIPE_SHADER_VERTEX && ctx.info.num_inputs) {
3035 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3036 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3037 }
3038 if (ctx.type == PIPE_SHADER_FRAGMENT) {
3039 if (ctx.bc->chip_class >= EVERGREEN)
3040 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3041 else
3042 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3043 }
3044 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3045 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3046 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3047 }
3048 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3049 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3050 if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3051 bool add_tesscoord = false, add_tess_inout = false;
3052 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3053 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3054 /* if we have tesscoord save one reg */
3055 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3056 add_tesscoord = true;
3057 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3058 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3059 add_tess_inout = true;
3060 }
3061 if (add_tesscoord || add_tess_inout)
3062 ctx.file_offset[TGSI_FILE_INPUT]++;
3063 if (add_tess_inout)
3064 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3065 }
3066
3067 ctx.file_offset[TGSI_FILE_OUTPUT] =
3068 ctx.file_offset[TGSI_FILE_INPUT] +
3069 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3070 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3071 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3072
3073 /* Outside the GPR range. This will be translated to one of the
3074 * kcache banks later. */
3075 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3076
3077 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3078 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3079 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
3080 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
3081 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
3082
3083 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3084 ctx.tess_input_info = ctx.bc->ar_reg + 3;
3085 ctx.tess_output_info = ctx.bc->ar_reg + 4;
3086 ctx.temp_reg = ctx.bc->ar_reg + 5;
3087 } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3088 ctx.tess_input_info = 0;
3089 ctx.tess_output_info = ctx.bc->ar_reg + 3;
3090 ctx.temp_reg = ctx.bc->ar_reg + 4;
3091 } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
3092 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
3093 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
3094 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
3095 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
3096 ctx.temp_reg = ctx.bc->ar_reg + 7;
3097 } else {
3098 ctx.temp_reg = ctx.bc->ar_reg + 3;
3099 }
3100
3101 shader->max_arrays = 0;
3102 shader->num_arrays = 0;
3103 if (indirect_gprs) {
3104
3105 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3106 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3107 ctx.file_offset[TGSI_FILE_OUTPUT] -
3108 ctx.file_offset[TGSI_FILE_INPUT],
3109 0x0F);
3110 }
3111 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3112 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3113 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3114 ctx.file_offset[TGSI_FILE_OUTPUT],
3115 0x0F);
3116 }
3117 }
3118
3119 ctx.nliterals = 0;
3120 ctx.literals = NULL;
3121
3122 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3123 ctx.info.colors_written == 1;
3124 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3125 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3126
3127 if (shader->vs_as_gs_a)
3128 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3129
3130 if (ctx.type == PIPE_SHADER_TESS_EVAL)
3131 r600_fetch_tess_io_info(&ctx);
3132
3133 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3134 tgsi_parse_token(&ctx.parse);
3135 switch (ctx.parse.FullToken.Token.Type) {
3136 case TGSI_TOKEN_TYPE_IMMEDIATE:
3137 immediate = &ctx.parse.FullToken.FullImmediate;
3138 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3139 if(ctx.literals == NULL) {
3140 r = -ENOMEM;
3141 goto out_err;
3142 }
3143 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3144 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3145 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3146 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3147 ctx.nliterals++;
3148 break;
3149 case TGSI_TOKEN_TYPE_DECLARATION:
3150 r = tgsi_declaration(&ctx);
3151 if (r)
3152 goto out_err;
3153 break;
3154 case TGSI_TOKEN_TYPE_INSTRUCTION:
3155 case TGSI_TOKEN_TYPE_PROPERTY:
3156 break;
3157 default:
3158 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3159 r = -EINVAL;
3160 goto out_err;
3161 }
3162 }
3163
3164 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3165 shader->ring_item_sizes[1] = 0;
3166 shader->ring_item_sizes[2] = 0;
3167 shader->ring_item_sizes[3] = 0;
3168
3169 /* Process two side if needed */
3170 if (shader->two_side && ctx.colors_used) {
3171 int i, count = ctx.shader->ninput;
3172 unsigned next_lds_loc = ctx.shader->nlds;
3173
3174 /* additional inputs will be allocated right after the existing inputs,
3175 * we won't need them after the color selection, so we don't need to
3176 * reserve these gprs for the rest of the shader code and to adjust
3177 * output offsets etc. */
3178 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3179 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3180
3181 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3182 if (ctx.face_gpr == -1) {
3183 i = ctx.shader->ninput++;
3184 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3185 ctx.shader->input[i].spi_sid = 0;
3186 ctx.shader->input[i].gpr = gpr++;
3187 ctx.face_gpr = ctx.shader->input[i].gpr;
3188 }
3189
3190 for (i = 0; i < count; i++) {
3191 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3192 int ni = ctx.shader->ninput++;
3193 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3194 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3195 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3196 ctx.shader->input[ni].gpr = gpr++;
3197 // TGSI to LLVM needs to know the lds position of inputs.
3198 // Non LLVM path computes it later (in process_twoside_color)
3199 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3200 ctx.shader->input[i].back_color_input = ni;
3201 if (ctx.bc->chip_class >= EVERGREEN) {
3202 if ((r = evergreen_interp_input(&ctx, ni)))
3203 return r;
3204 }
3205 }
3206 }
3207 }
3208
3209 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3210 shader->nr_ps_max_color_exports = 8;
3211
3212 if (ctx.fragcoord_input >= 0) {
3213 if (ctx.bc->chip_class == CAYMAN) {
3214 for (j = 0 ; j < 4; j++) {
3215 struct r600_bytecode_alu alu;
3216 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3217 alu.op = ALU_OP1_RECIP_IEEE;
3218 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3219 alu.src[0].chan = 3;
3220
3221 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3222 alu.dst.chan = j;
3223 alu.dst.write = (j == 3);
3224 alu.last = 1;
3225 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3226 return r;
3227 }
3228 } else {
3229 struct r600_bytecode_alu alu;
3230 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3231 alu.op = ALU_OP1_RECIP_IEEE;
3232 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3233 alu.src[0].chan = 3;
3234
3235 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3236 alu.dst.chan = 3;
3237 alu.dst.write = 1;
3238 alu.last = 1;
3239 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3240 return r;
3241 }
3242 }
3243
3244 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3245 struct r600_bytecode_alu alu;
3246 int r;
3247
3248 /* GS thread with no output workaround - emit a cut at start of GS */
3249 if (ctx.bc->chip_class == R600)
3250 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3251
3252 for (j = 0; j < 4; j++) {
3253 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3254 alu.op = ALU_OP1_MOV;
3255 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3256 alu.src[0].value = 0;
3257 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3258 alu.dst.write = 1;
3259 alu.last = 1;
3260 r = r600_bytecode_add_alu(ctx.bc, &alu);
3261 if (r)
3262 return r;
3263 }
3264 }
3265
3266 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3267 r600_fetch_tess_io_info(&ctx);
3268
3269 if (shader->two_side && ctx.colors_used) {
3270 if ((r = process_twoside_color_inputs(&ctx)))
3271 return r;
3272 }
3273
3274 tgsi_parse_init(&ctx.parse, tokens);
3275 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3276 tgsi_parse_token(&ctx.parse);
3277 switch (ctx.parse.FullToken.Token.Type) {
3278 case TGSI_TOKEN_TYPE_INSTRUCTION:
3279 r = tgsi_is_supported(&ctx);
3280 if (r)
3281 goto out_err;
3282 ctx.max_driver_temp_used = 0;
3283 /* reserve first tmp for everyone */
3284 r600_get_temp(&ctx);
3285
3286 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3287 if ((r = tgsi_split_constant(&ctx)))
3288 goto out_err;
3289 if ((r = tgsi_split_literal_constant(&ctx)))
3290 goto out_err;
3291 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3292 if ((r = tgsi_split_gs_inputs(&ctx)))
3293 goto out_err;
3294 } else if (lds_inputs) {
3295 if ((r = tgsi_split_lds_inputs(&ctx)))
3296 goto out_err;
3297 }
3298 if (ctx.bc->chip_class == CAYMAN)
3299 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3300 else if (ctx.bc->chip_class >= EVERGREEN)
3301 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3302 else
3303 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3304 r = ctx.inst_info->process(&ctx);
3305 if (r)
3306 goto out_err;
3307
3308 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3309 r = r600_store_tcs_output(&ctx);
3310 if (r)
3311 goto out_err;
3312 }
3313 break;
3314 default:
3315 break;
3316 }
3317 }
3318
3319 /* Reset the temporary register counter. */
3320 ctx.max_driver_temp_used = 0;
3321
3322 noutput = shader->noutput;
3323
3324 if (!ring_outputs && ctx.clip_vertex_write) {
3325 unsigned clipdist_temp[2];
3326
3327 clipdist_temp[0] = r600_get_temp(&ctx);
3328 clipdist_temp[1] = r600_get_temp(&ctx);
3329
3330 /* need to convert a clipvertex write into clipdistance writes and not export
3331 the clip vertex anymore */
3332
3333 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3334 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3335 shader->output[noutput].gpr = clipdist_temp[0];
3336 noutput++;
3337 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3338 shader->output[noutput].gpr = clipdist_temp[1];
3339 noutput++;
3340
3341 /* reset spi_sid for clipvertex output to avoid confusing spi */
3342 shader->output[ctx.cv_output].spi_sid = 0;
3343
3344 shader->clip_dist_write = 0xFF;
3345
3346 for (i = 0; i < 8; i++) {
3347 int oreg = i >> 2;
3348 int ochan = i & 3;
3349
3350 for (j = 0; j < 4; j++) {
3351 struct r600_bytecode_alu alu;
3352 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3353 alu.op = ALU_OP2_DOT4;
3354 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3355 alu.src[0].chan = j;
3356
3357 alu.src[1].sel = 512 + i;
3358 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3359 alu.src[1].chan = j;
3360
3361 alu.dst.sel = clipdist_temp[oreg];
3362 alu.dst.chan = j;
3363 alu.dst.write = (j == ochan);
3364 if (j == 3)
3365 alu.last = 1;
3366 r = r600_bytecode_add_alu(ctx.bc, &alu);
3367 if (r)
3368 return r;
3369 }
3370 }
3371 }
3372
3373 /* Add stream outputs. */
3374 if (so.num_outputs) {
3375 bool emit = false;
3376 if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
3377 emit = true;
3378 if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
3379 emit = true;
3380 if (emit)
3381 emit_streamout(&ctx, &so, -1, NULL);
3382 }
3383 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3384 convert_edgeflag_to_int(&ctx);
3385
3386 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3387 r600_emit_tess_factor(&ctx);
3388
3389 if (lds_outputs) {
3390 if (ctx.type == PIPE_SHADER_VERTEX) {
3391 if (ctx.shader->noutput)
3392 emit_lds_vs_writes(&ctx);
3393 }
3394 } else if (ring_outputs) {
3395 if (shader->vs_as_es || shader->tes_as_es) {
3396 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3397 ctx.gs_export_gpr_tregs[1] = -1;
3398 ctx.gs_export_gpr_tregs[2] = -1;
3399 ctx.gs_export_gpr_tregs[3] = -1;
3400
3401 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3402 }
3403 } else {
3404 /* Export output */
3405 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3406
3407 for (i = 0, j = 0; i < noutput; i++, j++) {
3408 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3409 output[j].gpr = shader->output[i].gpr;
3410 output[j].elem_size = 3;
3411 output[j].swizzle_x = 0;
3412 output[j].swizzle_y = 1;
3413 output[j].swizzle_z = 2;
3414 output[j].swizzle_w = 3;
3415 output[j].burst_count = 1;
3416 output[j].type = -1;
3417 output[j].op = CF_OP_EXPORT;
3418 switch (ctx.type) {
3419 case PIPE_SHADER_VERTEX:
3420 case PIPE_SHADER_TESS_EVAL:
3421 switch (shader->output[i].name) {
3422 case TGSI_SEMANTIC_POSITION:
3423 output[j].array_base = 60;
3424 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3425 pos_emitted = true;
3426 break;
3427
3428 case TGSI_SEMANTIC_PSIZE:
3429 output[j].array_base = 61;
3430 output[j].swizzle_y = 7;
3431 output[j].swizzle_z = 7;
3432 output[j].swizzle_w = 7;
3433 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3434 pos_emitted = true;
3435 break;
3436 case TGSI_SEMANTIC_EDGEFLAG:
3437 output[j].array_base = 61;
3438 output[j].swizzle_x = 7;
3439 output[j].swizzle_y = 0;
3440 output[j].swizzle_z = 7;
3441 output[j].swizzle_w = 7;
3442 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3443 pos_emitted = true;
3444 break;
3445 case TGSI_SEMANTIC_LAYER:
3446 /* spi_sid is 0 for outputs that are
3447 * not consumed by PS */
3448 if (shader->output[i].spi_sid) {
3449 output[j].array_base = next_param_base++;
3450 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3451 j++;
3452 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3453 }
3454 output[j].array_base = 61;
3455 output[j].swizzle_x = 7;
3456 output[j].swizzle_y = 7;
3457 output[j].swizzle_z = 0;
3458 output[j].swizzle_w = 7;
3459 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3460 pos_emitted = true;
3461 break;
3462 case TGSI_SEMANTIC_VIEWPORT_INDEX:
3463 /* spi_sid is 0 for outputs that are
3464 * not consumed by PS */
3465 if (shader->output[i].spi_sid) {
3466 output[j].array_base = next_param_base++;
3467 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3468 j++;
3469 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3470 }
3471 output[j].array_base = 61;
3472 output[j].swizzle_x = 7;
3473 output[j].swizzle_y = 7;
3474 output[j].swizzle_z = 7;
3475 output[j].swizzle_w = 0;
3476 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3477 pos_emitted = true;
3478 break;
3479 case TGSI_SEMANTIC_CLIPVERTEX:
3480 j--;
3481 break;
3482 case TGSI_SEMANTIC_CLIPDIST:
3483 output[j].array_base = next_clip_base++;
3484 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3485 pos_emitted = true;
3486 /* spi_sid is 0 for clipdistance outputs that were generated
3487 * for clipvertex - we don't need to pass them to PS */
3488 if (shader->output[i].spi_sid) {
3489 j++;
3490 /* duplicate it as PARAM to pass to the pixel shader */
3491 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3492 output[j].array_base = next_param_base++;
3493 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3494 }
3495 break;
3496 case TGSI_SEMANTIC_FOG:
3497 output[j].swizzle_y = 4; /* 0 */
3498 output[j].swizzle_z = 4; /* 0 */
3499 output[j].swizzle_w = 5; /* 1 */
3500 break;
3501 case TGSI_SEMANTIC_PRIMID:
3502 output[j].swizzle_x = 2;
3503 output[j].swizzle_y = 4; /* 0 */
3504 output[j].swizzle_z = 4; /* 0 */
3505 output[j].swizzle_w = 4; /* 0 */
3506 break;
3507 }
3508
3509 break;
3510 case PIPE_SHADER_FRAGMENT:
3511 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
3512 /* never export more colors than the number of CBs */
3513 if (shader->output[i].sid >= max_color_exports) {
3514 /* skip export */
3515 j--;
3516 continue;
3517 }
3518 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3519 output[j].array_base = shader->output[i].sid;
3520 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3521 shader->nr_ps_color_exports++;
3522 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
3523 for (k = 1; k < max_color_exports; k++) {
3524 j++;
3525 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3526 output[j].gpr = shader->output[i].gpr;
3527 output[j].elem_size = 3;
3528 output[j].swizzle_x = 0;
3529 output[j].swizzle_y = 1;
3530 output[j].swizzle_z = 2;
3531 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3532 output[j].burst_count = 1;
3533 output[j].array_base = k;
3534 output[j].op = CF_OP_EXPORT;
3535 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3536 shader->nr_ps_color_exports++;
3537 }
3538 }
3539 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
3540 output[j].array_base = 61;
3541 output[j].swizzle_x = 2;
3542 output[j].swizzle_y = 7;
3543 output[j].swizzle_z = output[j].swizzle_w = 7;
3544 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3545 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
3546 output[j].array_base = 61;
3547 output[j].swizzle_x = 7;
3548 output[j].swizzle_y = 1;
3549 output[j].swizzle_z = output[j].swizzle_w = 7;
3550 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3551 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3552 output[j].array_base = 61;
3553 output[j].swizzle_x = 7;
3554 output[j].swizzle_y = 7;
3555 output[j].swizzle_z = 0;
3556 output[j].swizzle_w = 7;
3557 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3558 } else {
3559 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
3560 r = -EINVAL;
3561 goto out_err;
3562 }
3563 break;
3564 case PIPE_SHADER_TESS_CTRL:
3565 break;
3566 default:
3567 R600_ERR("unsupported processor type %d\n", ctx.type);
3568 r = -EINVAL;
3569 goto out_err;
3570 }
3571
3572 if (output[j].type==-1) {
3573 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3574 output[j].array_base = next_param_base++;
3575 }
3576 }
3577
3578 /* add fake position export */
3579 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
3580 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3581 output[j].gpr = 0;
3582 output[j].elem_size = 3;
3583 output[j].swizzle_x = 7;
3584 output[j].swizzle_y = 7;
3585 output[j].swizzle_z = 7;
3586 output[j].swizzle_w = 7;
3587 output[j].burst_count = 1;
3588 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3589 output[j].array_base = 60;
3590 output[j].op = CF_OP_EXPORT;
3591 j++;
3592 }
3593
3594 /* add fake param output for vertex shader if no param is exported */
3595 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
3596 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3597 output[j].gpr = 0;
3598 output[j].elem_size = 3;
3599 output[j].swizzle_x = 7;
3600 output[j].swizzle_y = 7;
3601 output[j].swizzle_z = 7;
3602 output[j].swizzle_w = 7;
3603 output[j].burst_count = 1;
3604 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3605 output[j].array_base = 0;
3606 output[j].op = CF_OP_EXPORT;
3607 j++;
3608 }
3609
3610 /* add fake pixel export */
3611 if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
3612 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3613 output[j].gpr = 0;
3614 output[j].elem_size = 3;
3615 output[j].swizzle_x = 7;
3616 output[j].swizzle_y = 7;
3617 output[j].swizzle_z = 7;
3618 output[j].swizzle_w = 7;
3619 output[j].burst_count = 1;
3620 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3621 output[j].array_base = 0;
3622 output[j].op = CF_OP_EXPORT;
3623 j++;
3624 shader->nr_ps_color_exports++;
3625 }
3626
3627 noutput = j;
3628
3629 /* set export done on last export of each type */
3630 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
3631 if (!(output_done & (1 << output[i].type))) {
3632 output_done |= (1 << output[i].type);
3633 output[i].op = CF_OP_EXPORT_DONE;
3634 }
3635 }
3636 /* add output to bytecode */
3637 for (i = 0; i < noutput; i++) {
3638 r = r600_bytecode_add_output(ctx.bc, &output[i]);
3639 if (r)
3640 goto out_err;
3641 }
3642 }
3643
3644 /* add program end */
3645 if (ctx.bc->chip_class == CAYMAN)
3646 cm_bytecode_add_cf_end(ctx.bc);
3647 else {
3648 const struct cf_op_info *last = NULL;
3649
3650 if (ctx.bc->cf_last)
3651 last = r600_isa_cf(ctx.bc->cf_last->op);
3652
3653 /* alu clause instructions don't have EOP bit, so add NOP */
3654 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS || ctx.bc->cf_last->op == CF_OP_POP || ctx.bc->cf_last->op == CF_OP_GDS)
3655 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
3656
3657 ctx.bc->cf_last->end_of_program = 1;
3658 }
3659
3660 /* check GPR limit - we have 124 = 128 - 4
3661 * (4 are reserved as alu clause temporary registers) */
3662 if (ctx.bc->ngpr > 124) {
3663 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
3664 r = -ENOMEM;
3665 goto out_err;
3666 }
3667
3668 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3669 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
3670 return r;
3671 }
3672
3673 free(ctx.literals);
3674 tgsi_parse_free(&ctx.parse);
3675 return 0;
3676 out_err:
3677 free(ctx.literals);
3678 tgsi_parse_free(&ctx.parse);
3679 return r;
3680 }
3681
3682 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
3683 {
3684 const unsigned tgsi_opcode =
3685 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
3686 R600_ERR("%s tgsi opcode unsupported\n",
3687 tgsi_get_opcode_name(tgsi_opcode));
3688 return -EINVAL;
3689 }
3690
3691 static int tgsi_end(struct r600_shader_ctx *ctx)
3692 {
3693 return 0;
3694 }
3695
3696 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
3697 const struct r600_shader_src *shader_src,
3698 unsigned chan)
3699 {
3700 bc_src->sel = shader_src->sel;
3701 bc_src->chan = shader_src->swizzle[chan];
3702 bc_src->neg = shader_src->neg;
3703 bc_src->abs = shader_src->abs;
3704 bc_src->rel = shader_src->rel;
3705 bc_src->value = shader_src->value[bc_src->chan];
3706 bc_src->kc_bank = shader_src->kc_bank;
3707 bc_src->kc_rel = shader_src->kc_rel;
3708 }
3709
3710 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
3711 {
3712 bc_src->abs = 1;
3713 bc_src->neg = 0;
3714 }
3715
3716 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
3717 {
3718 bc_src->neg = !bc_src->neg;
3719 }
3720
3721 static void tgsi_dst(struct r600_shader_ctx *ctx,
3722 const struct tgsi_full_dst_register *tgsi_dst,
3723 unsigned swizzle,
3724 struct r600_bytecode_alu_dst *r600_dst)
3725 {
3726 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3727
3728 r600_dst->sel = tgsi_dst->Register.Index;
3729 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
3730 r600_dst->chan = swizzle;
3731 r600_dst->write = 1;
3732 if (inst->Instruction.Saturate) {
3733 r600_dst->clamp = 1;
3734 }
3735 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
3736 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
3737 return;
3738 }
3739 }
3740 if (tgsi_dst->Register.Indirect)
3741 r600_dst->rel = V_SQ_REL_RELATIVE;
3742
3743 }
3744
3745 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
3746 {
3747 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3748 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3749 struct r600_bytecode_alu alu;
3750 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3751 int use_tmp = 0;
3752
3753 if (singledest) {
3754 switch (write_mask) {
3755 case 0x1:
3756 write_mask = 0x3;
3757 break;
3758 case 0x2:
3759 use_tmp = 1;
3760 write_mask = 0x3;
3761 break;
3762 case 0x4:
3763 write_mask = 0xc;
3764 break;
3765 case 0x8:
3766 write_mask = 0xc;
3767 use_tmp = 3;
3768 break;
3769 }
3770 }
3771
3772 lasti = tgsi_last_instruction(write_mask);
3773 for (i = 0; i <= lasti; i++) {
3774
3775 if (!(write_mask & (1 << i)))
3776 continue;
3777
3778 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3779
3780 if (singledest) {
3781 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3782 if (use_tmp) {
3783 alu.dst.sel = ctx->temp_reg;
3784 alu.dst.chan = i;
3785 alu.dst.write = 1;
3786 }
3787 if (i == 1 || i == 3)
3788 alu.dst.write = 0;
3789 } else
3790 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3791
3792 alu.op = ctx->inst_info->op;
3793 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
3794 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3795 } else if (!swap) {
3796 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3797 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
3798 }
3799 } else {
3800 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
3801 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
3802 }
3803
3804 /* handle some special cases */
3805 if (i == 1 || i == 3) {
3806 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
3807 case TGSI_OPCODE_DABS:
3808 r600_bytecode_src_set_abs(&alu.src[0]);
3809 break;
3810 default:
3811 break;
3812 }
3813 }
3814 if (i == lasti) {
3815 alu.last = 1;
3816 }
3817 r = r600_bytecode_add_alu(ctx->bc, &alu);
3818 if (r)
3819 return r;
3820 }
3821
3822 if (use_tmp) {
3823 write_mask = inst->Dst[0].Register.WriteMask;
3824
3825 /* move result from temp to dst */
3826 for (i = 0; i <= lasti; i++) {
3827 if (!(write_mask & (1 << i)))
3828 continue;
3829
3830 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3831 alu.op = ALU_OP1_MOV;
3832 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3833 alu.src[0].sel = ctx->temp_reg;
3834 alu.src[0].chan = use_tmp - 1;
3835 alu.last = (i == lasti);
3836
3837 r = r600_bytecode_add_alu(ctx->bc, &alu);
3838 if (r)
3839 return r;
3840 }
3841 }
3842 return 0;
3843 }
3844
3845 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
3846 {
3847 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3848 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3849 /* confirm writemasking */
3850 if ((write_mask & 0x3) != 0x3 &&
3851 (write_mask & 0xc) != 0xc) {
3852 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
3853 return -1;
3854 }
3855 return tgsi_op2_64_params(ctx, false, false);
3856 }
3857
3858 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
3859 {
3860 return tgsi_op2_64_params(ctx, true, false);
3861 }
3862
3863 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
3864 {
3865 return tgsi_op2_64_params(ctx, true, true);
3866 }
3867
3868 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
3869 {
3870 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3871 struct r600_bytecode_alu alu;
3872 int i, j, r;
3873 int lasti = 3;
3874 int tmp = r600_get_temp(ctx);
3875
3876 for (i = 0; i < lasti + 1; i++) {
3877
3878 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3879 alu.op = ctx->inst_info->op;
3880 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3881 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
3882 }
3883
3884 if (inst->Dst[0].Register.WriteMask & (1 << i))
3885 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3886 else
3887 alu.dst.sel = tmp;
3888
3889 alu.dst.chan = i;
3890 alu.is_op3 = 1;
3891 if (i == lasti) {
3892 alu.last = 1;
3893 }
3894 r = r600_bytecode_add_alu(ctx->bc, &alu);
3895 if (r)
3896 return r;
3897 }
3898 return 0;
3899 }
3900
3901 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
3902 {
3903 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3904 struct r600_bytecode_alu alu;
3905 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3906 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3907 /* use temp register if trans_only and more than one dst component */
3908 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
3909 unsigned op = ctx->inst_info->op;
3910
3911 if (op == ALU_OP2_MUL_IEEE &&
3912 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
3913 op = ALU_OP2_MUL;
3914
3915 for (i = 0; i <= lasti; i++) {
3916 if (!(write_mask & (1 << i)))
3917 continue;
3918
3919 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3920 if (use_tmp) {
3921 alu.dst.sel = ctx->temp_reg;
3922 alu.dst.chan = i;
3923 alu.dst.write = 1;
3924 } else
3925 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3926
3927 alu.op = op;
3928 if (!swap) {
3929 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3930 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3931 }
3932 } else {
3933 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3934 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3935 }
3936 if (i == lasti || trans_only) {
3937 alu.last = 1;
3938 }
3939 r = r600_bytecode_add_alu(ctx->bc, &alu);
3940 if (r)
3941 return r;
3942 }
3943
3944 if (use_tmp) {
3945 /* move result from temp to dst */
3946 for (i = 0; i <= lasti; i++) {
3947 if (!(write_mask & (1 << i)))
3948 continue;
3949
3950 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3951 alu.op = ALU_OP1_MOV;
3952 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3953 alu.src[0].sel = ctx->temp_reg;
3954 alu.src[0].chan = i;
3955 alu.last = (i == lasti);
3956
3957 r = r600_bytecode_add_alu(ctx->bc, &alu);
3958 if (r)
3959 return r;
3960 }
3961 }
3962 return 0;
3963 }
3964
3965 static int tgsi_op2(struct r600_shader_ctx *ctx)
3966 {
3967 return tgsi_op2_s(ctx, 0, 0);
3968 }
3969
3970 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
3971 {
3972 return tgsi_op2_s(ctx, 1, 0);
3973 }
3974
3975 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
3976 {
3977 return tgsi_op2_s(ctx, 0, 1);
3978 }
3979
3980 static int tgsi_ineg(struct r600_shader_ctx *ctx)
3981 {
3982 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3983 struct r600_bytecode_alu alu;
3984 int i, r;
3985 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3986
3987 for (i = 0; i < lasti + 1; i++) {
3988
3989 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3990 continue;
3991 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3992 alu.op = ctx->inst_info->op;
3993
3994 alu.src[0].sel = V_SQ_ALU_SRC_0;
3995
3996 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3997
3998 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3999
4000 if (i == lasti) {
4001 alu.last = 1;
4002 }
4003 r = r600_bytecode_add_alu(ctx->bc, &alu);
4004 if (r)
4005 return r;
4006 }
4007 return 0;
4008
4009 }
4010
4011 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4012 {
4013 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4014 struct r600_bytecode_alu alu;
4015 int i, r;
4016 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4017
4018 for (i = 0; i < lasti + 1; i++) {
4019
4020 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4021 continue;
4022 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4023 alu.op = ALU_OP1_MOV;
4024
4025 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4026
4027 if (i == 1 || i == 3)
4028 r600_bytecode_src_toggle_neg(&alu.src[0]);
4029 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4030
4031 if (i == lasti) {
4032 alu.last = 1;
4033 }
4034 r = r600_bytecode_add_alu(ctx->bc, &alu);
4035 if (r)
4036 return r;
4037 }
4038 return 0;
4039
4040 }
4041
4042 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4043 {
4044 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4045 struct r600_bytecode_alu alu;
4046 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4047 int i, j, r;
4048 int firsti = write_mask == 0xc ? 2 : 0;
4049
4050 for (i = 0; i <= 3; i++) {
4051 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4052 alu.op = ctx->inst_info->op;
4053
4054 alu.dst.sel = ctx->temp_reg;
4055 alu.dst.chan = i;
4056 alu.dst.write = 1;
4057 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4058 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4059 }
4060
4061 if (i == 3)
4062 alu.last = 1;
4063
4064 r = r600_bytecode_add_alu(ctx->bc, &alu);
4065 if (r)
4066 return r;
4067 }
4068
4069 /* MOV first two channels to writemask dst0 */
4070 for (i = 0; i <= 1; i++) {
4071 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4072 alu.op = ALU_OP1_MOV;
4073 alu.src[0].chan = i + 2;
4074 alu.src[0].sel = ctx->temp_reg;
4075
4076 tgsi_dst(ctx, &inst->Dst[0], firsti + i, &alu.dst);
4077 alu.dst.write = (inst->Dst[0].Register.WriteMask >> (firsti + i)) & 1;
4078 alu.last = 1;
4079 r = r600_bytecode_add_alu(ctx->bc, &alu);
4080 if (r)
4081 return r;
4082 }
4083
4084 for (i = 0; i <= 3; i++) {
4085 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4086 /* MOV third channels to writemask dst1 */
4087 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4088 alu.op = ALU_OP1_MOV;
4089 alu.src[0].chan = 1;
4090 alu.src[0].sel = ctx->temp_reg;
4091
4092 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4093 alu.last = 1;
4094 r = r600_bytecode_add_alu(ctx->bc, &alu);
4095 if (r)
4096 return r;
4097 break;
4098 }
4099 }
4100 return 0;
4101 }
4102
4103
4104 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4105 {
4106 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4107 struct r600_bytecode_alu alu;
4108 int i, r;
4109 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4110
4111 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4112 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4113
4114 for (i = 0; i <= (lasti+1)/2; i++) {
4115 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4116 alu.op = ctx->inst_info->op;
4117
4118 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4119 alu.dst.sel = ctx->temp_reg;
4120 alu.dst.chan = i;
4121 alu.dst.write = 1;
4122 alu.last = 1;
4123
4124 r = r600_bytecode_add_alu(ctx->bc, &alu);
4125 if (r)
4126 return r;
4127 }
4128
4129 for (i = 0; i <= lasti; i++) {
4130 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4131 alu.op = ALU_OP1_FLT32_TO_FLT64;
4132
4133 alu.src[0].chan = i/2;
4134 if (i%2 == 0)
4135 alu.src[0].sel = ctx->temp_reg;
4136 else {
4137 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4138 alu.src[0].value = 0x0;
4139 }
4140 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4141 alu.last = i == lasti;
4142
4143 r = r600_bytecode_add_alu(ctx->bc, &alu);
4144 if (r)
4145 return r;
4146 }
4147
4148 return 0;
4149 }
4150
4151 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4152 {
4153 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4154 struct r600_bytecode_alu alu;
4155 int i, r;
4156 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4157
4158 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4159 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4160
4161 for (i = 0; i <= lasti; i++) {
4162 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4163 alu.op = ALU_OP1_FLT64_TO_FLT32;
4164
4165 r600_bytecode_src(&alu.src[0], &ctx->src[0], fp64_switch(i));
4166 alu.dst.chan = i;
4167 alu.dst.sel = ctx->temp_reg;
4168 alu.dst.write = i%2 == 0;
4169 alu.last = i == lasti;
4170
4171 r = r600_bytecode_add_alu(ctx->bc, &alu);
4172 if (r)
4173 return r;
4174 }
4175
4176 for (i = 0; i <= (lasti+1)/2; i++) {
4177 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4178 alu.op = ctx->inst_info->op;
4179
4180 alu.src[0].chan = i*2;
4181 alu.src[0].sel = ctx->temp_reg;
4182 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4183 alu.last = 1;
4184
4185 r = r600_bytecode_add_alu(ctx->bc, &alu);
4186 if (r)
4187 return r;
4188 }
4189
4190 return 0;
4191 }
4192
4193 static int cayman_emit_unary_double_raw(struct r600_bytecode *bc,
4194 unsigned op,
4195 int dst_reg,
4196 struct r600_shader_src *src,
4197 bool abs)
4198 {
4199 struct r600_bytecode_alu alu;
4200 const int last_slot = 3;
4201 int r;
4202
4203 /* these have to write the result to X/Y by the looks of it */
4204 for (int i = 0 ; i < last_slot; i++) {
4205 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4206 alu.op = op;
4207
4208 r600_bytecode_src(&alu.src[0], src, 1);
4209 r600_bytecode_src(&alu.src[1], src, 0);
4210
4211 if (abs)
4212 r600_bytecode_src_set_abs(&alu.src[1]);
4213
4214 alu.dst.sel = dst_reg;
4215 alu.dst.chan = i;
4216 alu.dst.write = (i == 0 || i == 1);
4217
4218 if (bc->chip_class != CAYMAN || i == last_slot - 1)
4219 alu.last = 1;
4220 r = r600_bytecode_add_alu(bc, &alu);
4221 if (r)
4222 return r;
4223 }
4224
4225 return 0;
4226 }
4227
4228 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4229 {
4230 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4231 int i, r;
4232 struct r600_bytecode_alu alu;
4233 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4234 int t1 = ctx->temp_reg;
4235
4236 /* should only be one src regs */
4237 assert(inst->Instruction.NumSrcRegs == 1);
4238
4239 /* only support one double at a time */
4240 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4241 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4242
4243 r = cayman_emit_unary_double_raw(
4244 ctx->bc, ctx->inst_info->op, t1,
4245 &ctx->src[0],
4246 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4247 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT);
4248 if (r)
4249 return r;
4250
4251 for (i = 0 ; i <= lasti; i++) {
4252 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4253 continue;
4254 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4255 alu.op = ALU_OP1_MOV;
4256 alu.src[0].sel = t1;
4257 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
4258 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4259 alu.dst.write = 1;
4260 if (i == lasti)
4261 alu.last = 1;
4262 r = r600_bytecode_add_alu(ctx->bc, &alu);
4263 if (r)
4264 return r;
4265 }
4266 return 0;
4267 }
4268
4269 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
4270 {
4271 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4272 int i, j, r;
4273 struct r600_bytecode_alu alu;
4274 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4275
4276 for (i = 0 ; i < last_slot; i++) {
4277 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4278 alu.op = ctx->inst_info->op;
4279 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4280 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
4281
4282 /* RSQ should take the absolute value of src */
4283 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
4284 r600_bytecode_src_set_abs(&alu.src[j]);
4285 }
4286 }
4287 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4288 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4289
4290 if (i == last_slot - 1)
4291 alu.last = 1;
4292 r = r600_bytecode_add_alu(ctx->bc, &alu);
4293 if (r)
4294 return r;
4295 }
4296 return 0;
4297 }
4298
4299 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
4300 {
4301 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4302 int i, j, k, r;
4303 struct r600_bytecode_alu alu;
4304 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4305 int t1 = ctx->temp_reg;
4306
4307 for (k = 0; k <= lasti; k++) {
4308 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
4309 continue;
4310
4311 for (i = 0 ; i < 4; i++) {
4312 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4313 alu.op = ctx->inst_info->op;
4314 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4315 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
4316 }
4317 alu.dst.sel = t1;
4318 alu.dst.chan = i;
4319 alu.dst.write = (i == k);
4320 if (i == 3)
4321 alu.last = 1;
4322 r = r600_bytecode_add_alu(ctx->bc, &alu);
4323 if (r)
4324 return r;
4325 }
4326 }
4327
4328 for (i = 0 ; i <= lasti; i++) {
4329 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4330 continue;
4331 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4332 alu.op = ALU_OP1_MOV;
4333 alu.src[0].sel = t1;
4334 alu.src[0].chan = i;
4335 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4336 alu.dst.write = 1;
4337 if (i == lasti)
4338 alu.last = 1;
4339 r = r600_bytecode_add_alu(ctx->bc, &alu);
4340 if (r)
4341 return r;
4342 }
4343
4344 return 0;
4345 }
4346
4347
4348 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
4349 {
4350 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4351 int i, j, k, r;
4352 struct r600_bytecode_alu alu;
4353 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4354 int t1 = ctx->temp_reg;
4355
4356 /* t1 would get overwritten below if we actually tried to
4357 * multiply two pairs of doubles at a time. */
4358 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4359 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4360
4361 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4362
4363 for (i = 0; i < 4; i++) {
4364 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4365 alu.op = ctx->inst_info->op;
4366 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4367 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));
4368 }
4369 alu.dst.sel = t1;
4370 alu.dst.chan = i;
4371 alu.dst.write = 1;
4372 if (i == 3)
4373 alu.last = 1;
4374 r = r600_bytecode_add_alu(ctx->bc, &alu);
4375 if (r)
4376 return r;
4377 }
4378
4379 for (i = 0; i <= lasti; i++) {
4380 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4381 continue;
4382 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4383 alu.op = ALU_OP1_MOV;
4384 alu.src[0].sel = t1;
4385 alu.src[0].chan = i;
4386 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4387 alu.dst.write = 1;
4388 if (i == lasti)
4389 alu.last = 1;
4390 r = r600_bytecode_add_alu(ctx->bc, &alu);
4391 if (r)
4392 return r;
4393 }
4394
4395 return 0;
4396 }
4397
4398 /*
4399 * Emit RECIP_64 + MUL_64 to implement division.
4400 */
4401 static int cayman_ddiv_instr(struct r600_shader_ctx *ctx)
4402 {
4403 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4404 int r;
4405 struct r600_bytecode_alu alu;
4406 int t1 = ctx->temp_reg;
4407 int k;
4408
4409 /* Only support one double at a time. This is the same constraint as
4410 * in DMUL lowering. */
4411 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4412 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4413
4414 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4415
4416 r = cayman_emit_unary_double_raw(ctx->bc, ALU_OP2_RECIP_64, t1, &ctx->src[1], false);
4417 if (r)
4418 return r;
4419
4420 for (int i = 0; i < 4; i++) {
4421 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4422 alu.op = ALU_OP2_MUL_64;
4423
4424 r600_bytecode_src(&alu.src[0], &ctx->src[0], k * 2 + ((i == 3) ? 0 : 1));
4425
4426 alu.src[1].sel = t1;
4427 alu.src[1].chan = (i == 3) ? 0 : 1;
4428
4429 alu.dst.sel = t1;
4430 alu.dst.chan = i;
4431 alu.dst.write = 1;
4432 if (i == 3)
4433 alu.last = 1;
4434 r = r600_bytecode_add_alu(ctx->bc, &alu);
4435 if (r)
4436 return r;
4437 }
4438
4439 for (int i = 0; i < 2; i++) {
4440 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4441 alu.op = ALU_OP1_MOV;
4442 alu.src[0].sel = t1;
4443 alu.src[0].chan = i;
4444 tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
4445 alu.dst.write = 1;
4446 if (i == 1)
4447 alu.last = 1;
4448 r = r600_bytecode_add_alu(ctx->bc, &alu);
4449 if (r)
4450 return r;
4451 }
4452 return 0;
4453 }
4454
4455 /*
4456 * r600 - trunc to -PI..PI range
4457 * r700 - normalize by dividing by 2PI
4458 * see fdo bug 27901
4459 */
4460 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
4461 {
4462 int r;
4463 struct r600_bytecode_alu alu;
4464
4465 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4466 alu.op = ALU_OP3_MULADD;
4467 alu.is_op3 = 1;
4468
4469 alu.dst.chan = 0;
4470 alu.dst.sel = ctx->temp_reg;
4471 alu.dst.write = 1;
4472
4473 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4474
4475 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4476 alu.src[1].chan = 0;
4477 alu.src[1].value = u_bitcast_f2u(0.5f * M_1_PI);
4478 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4479 alu.src[2].chan = 0;
4480 alu.last = 1;
4481 r = r600_bytecode_add_alu(ctx->bc, &alu);
4482 if (r)
4483 return r;
4484
4485 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4486 alu.op = ALU_OP1_FRACT;
4487
4488 alu.dst.chan = 0;
4489 alu.dst.sel = ctx->temp_reg;
4490 alu.dst.write = 1;
4491
4492 alu.src[0].sel = ctx->temp_reg;
4493 alu.src[0].chan = 0;
4494 alu.last = 1;
4495 r = r600_bytecode_add_alu(ctx->bc, &alu);
4496 if (r)
4497 return r;
4498
4499 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4500 alu.op = ALU_OP3_MULADD;
4501 alu.is_op3 = 1;
4502
4503 alu.dst.chan = 0;
4504 alu.dst.sel = ctx->temp_reg;
4505 alu.dst.write = 1;
4506
4507 alu.src[0].sel = ctx->temp_reg;
4508 alu.src[0].chan = 0;
4509
4510 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4511 alu.src[1].chan = 0;
4512 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4513 alu.src[2].chan = 0;
4514
4515 if (ctx->bc->chip_class == R600) {
4516 alu.src[1].value = u_bitcast_f2u(2.0f * M_PI);
4517 alu.src[2].value = u_bitcast_f2u(-M_PI);
4518 } else {
4519 alu.src[1].sel = V_SQ_ALU_SRC_1;
4520 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4521 alu.src[2].neg = 1;
4522 }
4523
4524 alu.last = 1;
4525 r = r600_bytecode_add_alu(ctx->bc, &alu);
4526 if (r)
4527 return r;
4528 return 0;
4529 }
4530
4531 static int cayman_trig(struct r600_shader_ctx *ctx)
4532 {
4533 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4534 struct r600_bytecode_alu alu;
4535 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4536 int i, r;
4537
4538 r = tgsi_setup_trig(ctx);
4539 if (r)
4540 return r;
4541
4542
4543 for (i = 0; i < last_slot; i++) {
4544 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4545 alu.op = ctx->inst_info->op;
4546 alu.dst.chan = i;
4547
4548 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4549 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4550
4551 alu.src[0].sel = ctx->temp_reg;
4552 alu.src[0].chan = 0;
4553 if (i == last_slot - 1)
4554 alu.last = 1;
4555 r = r600_bytecode_add_alu(ctx->bc, &alu);
4556 if (r)
4557 return r;
4558 }
4559 return 0;
4560 }
4561
4562 static int tgsi_trig(struct r600_shader_ctx *ctx)
4563 {
4564 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4565 struct r600_bytecode_alu alu;
4566 int i, r;
4567 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4568
4569 r = tgsi_setup_trig(ctx);
4570 if (r)
4571 return r;
4572
4573 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4574 alu.op = ctx->inst_info->op;
4575 alu.dst.chan = 0;
4576 alu.dst.sel = ctx->temp_reg;
4577 alu.dst.write = 1;
4578
4579 alu.src[0].sel = ctx->temp_reg;
4580 alu.src[0].chan = 0;
4581 alu.last = 1;
4582 r = r600_bytecode_add_alu(ctx->bc, &alu);
4583 if (r)
4584 return r;
4585
4586 /* replicate result */
4587 for (i = 0; i < lasti + 1; i++) {
4588 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4589 continue;
4590
4591 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4592 alu.op = ALU_OP1_MOV;
4593
4594 alu.src[0].sel = ctx->temp_reg;
4595 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4596 if (i == lasti)
4597 alu.last = 1;
4598 r = r600_bytecode_add_alu(ctx->bc, &alu);
4599 if (r)
4600 return r;
4601 }
4602 return 0;
4603 }
4604
4605 static int tgsi_scs(struct r600_shader_ctx *ctx)
4606 {
4607 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4608 struct r600_bytecode_alu alu;
4609 int i, r;
4610
4611 /* We'll only need the trig stuff if we are going to write to the
4612 * X or Y components of the destination vector.
4613 */
4614 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
4615 r = tgsi_setup_trig(ctx);
4616 if (r)
4617 return r;
4618 }
4619
4620 /* dst.x = COS */
4621 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
4622 if (ctx->bc->chip_class == CAYMAN) {
4623 for (i = 0 ; i < 3; i++) {
4624 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4625 alu.op = ALU_OP1_COS;
4626 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4627
4628 if (i == 0)
4629 alu.dst.write = 1;
4630 else
4631 alu.dst.write = 0;
4632 alu.src[0].sel = ctx->temp_reg;
4633 alu.src[0].chan = 0;
4634 if (i == 2)
4635 alu.last = 1;
4636 r = r600_bytecode_add_alu(ctx->bc, &alu);
4637 if (r)
4638 return r;
4639 }
4640 } else {
4641 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4642 alu.op = ALU_OP1_COS;
4643 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4644
4645 alu.src[0].sel = ctx->temp_reg;
4646 alu.src[0].chan = 0;
4647 alu.last = 1;
4648 r = r600_bytecode_add_alu(ctx->bc, &alu);
4649 if (r)
4650 return r;
4651 }
4652 }
4653
4654 /* dst.y = SIN */
4655 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
4656 if (ctx->bc->chip_class == CAYMAN) {
4657 for (i = 0 ; i < 3; i++) {
4658 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4659 alu.op = ALU_OP1_SIN;
4660 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4661 if (i == 1)
4662 alu.dst.write = 1;
4663 else
4664 alu.dst.write = 0;
4665 alu.src[0].sel = ctx->temp_reg;
4666 alu.src[0].chan = 0;
4667 if (i == 2)
4668 alu.last = 1;
4669 r = r600_bytecode_add_alu(ctx->bc, &alu);
4670 if (r)
4671 return r;
4672 }
4673 } else {
4674 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4675 alu.op = ALU_OP1_SIN;
4676 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4677
4678 alu.src[0].sel = ctx->temp_reg;
4679 alu.src[0].chan = 0;
4680 alu.last = 1;
4681 r = r600_bytecode_add_alu(ctx->bc, &alu);
4682 if (r)
4683 return r;
4684 }
4685 }
4686
4687 /* dst.z = 0.0; */
4688 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
4689 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4690
4691 alu.op = ALU_OP1_MOV;
4692
4693 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4694
4695 alu.src[0].sel = V_SQ_ALU_SRC_0;
4696 alu.src[0].chan = 0;
4697
4698 alu.last = 1;
4699
4700 r = r600_bytecode_add_alu(ctx->bc, &alu);
4701 if (r)
4702 return r;
4703 }
4704
4705 /* dst.w = 1.0; */
4706 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
4707 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4708
4709 alu.op = ALU_OP1_MOV;
4710
4711 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4712
4713 alu.src[0].sel = V_SQ_ALU_SRC_1;
4714 alu.src[0].chan = 0;
4715
4716 alu.last = 1;
4717
4718 r = r600_bytecode_add_alu(ctx->bc, &alu);
4719 if (r)
4720 return r;
4721 }
4722
4723 return 0;
4724 }
4725
4726 static int tgsi_kill(struct r600_shader_ctx *ctx)
4727 {
4728 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4729 struct r600_bytecode_alu alu;
4730 int i, r;
4731
4732 for (i = 0; i < 4; i++) {
4733 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4734 alu.op = ctx->inst_info->op;
4735
4736 alu.dst.chan = i;
4737
4738 alu.src[0].sel = V_SQ_ALU_SRC_0;
4739
4740 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
4741 alu.src[1].sel = V_SQ_ALU_SRC_1;
4742 alu.src[1].neg = 1;
4743 } else {
4744 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4745 }
4746 if (i == 3) {
4747 alu.last = 1;
4748 }
4749 r = r600_bytecode_add_alu(ctx->bc, &alu);
4750 if (r)
4751 return r;
4752 }
4753
4754 /* kill must be last in ALU */
4755 ctx->bc->force_add_cf = 1;
4756 ctx->shader->uses_kill = TRUE;
4757 return 0;
4758 }
4759
4760 static int tgsi_lit(struct r600_shader_ctx *ctx)
4761 {
4762 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4763 struct r600_bytecode_alu alu;
4764 int r;
4765
4766 /* tmp.x = max(src.y, 0.0) */
4767 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4768 alu.op = ALU_OP2_MAX;
4769 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4770 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4771 alu.src[1].chan = 1;
4772
4773 alu.dst.sel = ctx->temp_reg;
4774 alu.dst.chan = 0;
4775 alu.dst.write = 1;
4776
4777 alu.last = 1;
4778 r = r600_bytecode_add_alu(ctx->bc, &alu);
4779 if (r)
4780 return r;
4781
4782 if (inst->Dst[0].Register.WriteMask & (1 << 2))
4783 {
4784 int chan;
4785 int sel;
4786 unsigned i;
4787
4788 if (ctx->bc->chip_class == CAYMAN) {
4789 for (i = 0; i < 3; i++) {
4790 /* tmp.z = log(tmp.x) */
4791 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4792 alu.op = ALU_OP1_LOG_CLAMPED;
4793 alu.src[0].sel = ctx->temp_reg;
4794 alu.src[0].chan = 0;
4795 alu.dst.sel = ctx->temp_reg;
4796 alu.dst.chan = i;
4797 if (i == 2) {
4798 alu.dst.write = 1;
4799 alu.last = 1;
4800 } else
4801 alu.dst.write = 0;
4802
4803 r = r600_bytecode_add_alu(ctx->bc, &alu);
4804 if (r)
4805 return r;
4806 }
4807 } else {
4808 /* tmp.z = log(tmp.x) */
4809 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4810 alu.op = ALU_OP1_LOG_CLAMPED;
4811 alu.src[0].sel = ctx->temp_reg;
4812 alu.src[0].chan = 0;
4813 alu.dst.sel = ctx->temp_reg;
4814 alu.dst.chan = 2;
4815 alu.dst.write = 1;
4816 alu.last = 1;
4817 r = r600_bytecode_add_alu(ctx->bc, &alu);
4818 if (r)
4819 return r;
4820 }
4821
4822 chan = alu.dst.chan;
4823 sel = alu.dst.sel;
4824
4825 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4826 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4827 alu.op = ALU_OP3_MUL_LIT;
4828 alu.src[0].sel = sel;
4829 alu.src[0].chan = chan;
4830 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
4831 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
4832 alu.dst.sel = ctx->temp_reg;
4833 alu.dst.chan = 0;
4834 alu.dst.write = 1;
4835 alu.is_op3 = 1;
4836 alu.last = 1;
4837 r = r600_bytecode_add_alu(ctx->bc, &alu);
4838 if (r)
4839 return r;
4840
4841 if (ctx->bc->chip_class == CAYMAN) {
4842 for (i = 0; i < 3; i++) {
4843 /* dst.z = exp(tmp.x) */
4844 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4845 alu.op = ALU_OP1_EXP_IEEE;
4846 alu.src[0].sel = ctx->temp_reg;
4847 alu.src[0].chan = 0;
4848 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4849 if (i == 2) {
4850 alu.dst.write = 1;
4851 alu.last = 1;
4852 } else
4853 alu.dst.write = 0;
4854 r = r600_bytecode_add_alu(ctx->bc, &alu);
4855 if (r)
4856 return r;
4857 }
4858 } else {
4859 /* dst.z = exp(tmp.x) */
4860 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4861 alu.op = ALU_OP1_EXP_IEEE;
4862 alu.src[0].sel = ctx->temp_reg;
4863 alu.src[0].chan = 0;
4864 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4865 alu.last = 1;
4866 r = r600_bytecode_add_alu(ctx->bc, &alu);
4867 if (r)
4868 return r;
4869 }
4870 }
4871
4872 /* dst.x, <- 1.0 */
4873 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4874 alu.op = ALU_OP1_MOV;
4875 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
4876 alu.src[0].chan = 0;
4877 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4878 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
4879 r = r600_bytecode_add_alu(ctx->bc, &alu);
4880 if (r)
4881 return r;
4882
4883 /* dst.y = max(src.x, 0.0) */
4884 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4885 alu.op = ALU_OP2_MAX;
4886 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4887 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4888 alu.src[1].chan = 0;
4889 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4890 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
4891 r = r600_bytecode_add_alu(ctx->bc, &alu);
4892 if (r)
4893 return r;
4894
4895 /* dst.w, <- 1.0 */
4896 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4897 alu.op = ALU_OP1_MOV;
4898 alu.src[0].sel = V_SQ_ALU_SRC_1;
4899 alu.src[0].chan = 0;
4900 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4901 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
4902 alu.last = 1;
4903 r = r600_bytecode_add_alu(ctx->bc, &alu);
4904 if (r)
4905 return r;
4906
4907 return 0;
4908 }
4909
4910 static int tgsi_rsq(struct r600_shader_ctx *ctx)
4911 {
4912 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4913 struct r600_bytecode_alu alu;
4914 int i, r;
4915
4916 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4917
4918 /* XXX:
4919 * For state trackers other than OpenGL, we'll want to use
4920 * _RECIPSQRT_IEEE instead.
4921 */
4922 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
4923
4924 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4925 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4926 r600_bytecode_src_set_abs(&alu.src[i]);
4927 }
4928 alu.dst.sel = ctx->temp_reg;
4929 alu.dst.write = 1;
4930 alu.last = 1;
4931 r = r600_bytecode_add_alu(ctx->bc, &alu);
4932 if (r)
4933 return r;
4934 /* replicate result */
4935 return tgsi_helper_tempx_replicate(ctx);
4936 }
4937
4938 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
4939 {
4940 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4941 struct r600_bytecode_alu alu;
4942 int i, r;
4943
4944 for (i = 0; i < 4; i++) {
4945 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4946 alu.src[0].sel = ctx->temp_reg;
4947 alu.op = ALU_OP1_MOV;
4948 alu.dst.chan = i;
4949 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4950 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4951 if (i == 3)
4952 alu.last = 1;
4953 r = r600_bytecode_add_alu(ctx->bc, &alu);
4954 if (r)
4955 return r;
4956 }
4957 return 0;
4958 }
4959
4960 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
4961 {
4962 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4963 struct r600_bytecode_alu alu;
4964 int i, r;
4965
4966 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4967 alu.op = ctx->inst_info->op;
4968 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4969 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4970 }
4971 alu.dst.sel = ctx->temp_reg;
4972 alu.dst.write = 1;
4973 alu.last = 1;
4974 r = r600_bytecode_add_alu(ctx->bc, &alu);
4975 if (r)
4976 return r;
4977 /* replicate result */
4978 return tgsi_helper_tempx_replicate(ctx);
4979 }
4980
4981 static int cayman_pow(struct r600_shader_ctx *ctx)
4982 {
4983 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4984 int i, r;
4985 struct r600_bytecode_alu alu;
4986 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4987
4988 for (i = 0; i < 3; i++) {
4989 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4990 alu.op = ALU_OP1_LOG_IEEE;
4991 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4992 alu.dst.sel = ctx->temp_reg;
4993 alu.dst.chan = i;
4994 alu.dst.write = 1;
4995 if (i == 2)
4996 alu.last = 1;
4997 r = r600_bytecode_add_alu(ctx->bc, &alu);
4998 if (r)
4999 return r;
5000 }
5001
5002 /* b * LOG2(a) */
5003 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5004 alu.op = ALU_OP2_MUL;
5005 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5006 alu.src[1].sel = ctx->temp_reg;
5007 alu.dst.sel = ctx->temp_reg;
5008 alu.dst.write = 1;
5009 alu.last = 1;
5010 r = r600_bytecode_add_alu(ctx->bc, &alu);
5011 if (r)
5012 return r;
5013
5014 for (i = 0; i < last_slot; i++) {
5015 /* POW(a,b) = EXP2(b * LOG2(a))*/
5016 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5017 alu.op = ALU_OP1_EXP_IEEE;
5018 alu.src[0].sel = ctx->temp_reg;
5019
5020 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5021 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5022 if (i == last_slot - 1)
5023 alu.last = 1;
5024 r = r600_bytecode_add_alu(ctx->bc, &alu);
5025 if (r)
5026 return r;
5027 }
5028 return 0;
5029 }
5030
5031 static int tgsi_pow(struct r600_shader_ctx *ctx)
5032 {
5033 struct r600_bytecode_alu alu;
5034 int r;
5035
5036 /* LOG2(a) */
5037 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5038 alu.op = ALU_OP1_LOG_IEEE;
5039 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5040 alu.dst.sel = ctx->temp_reg;
5041 alu.dst.write = 1;
5042 alu.last = 1;
5043 r = r600_bytecode_add_alu(ctx->bc, &alu);
5044 if (r)
5045 return r;
5046 /* b * LOG2(a) */
5047 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5048 alu.op = ALU_OP2_MUL;
5049 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5050 alu.src[1].sel = ctx->temp_reg;
5051 alu.dst.sel = ctx->temp_reg;
5052 alu.dst.write = 1;
5053 alu.last = 1;
5054 r = r600_bytecode_add_alu(ctx->bc, &alu);
5055 if (r)
5056 return r;
5057 /* POW(a,b) = EXP2(b * LOG2(a))*/
5058 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5059 alu.op = ALU_OP1_EXP_IEEE;
5060 alu.src[0].sel = ctx->temp_reg;
5061 alu.dst.sel = ctx->temp_reg;
5062 alu.dst.write = 1;
5063 alu.last = 1;
5064 r = r600_bytecode_add_alu(ctx->bc, &alu);
5065 if (r)
5066 return r;
5067 return tgsi_helper_tempx_replicate(ctx);
5068 }
5069
5070 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5071 {
5072 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5073 struct r600_bytecode_alu alu;
5074 int i, r, j;
5075 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5076 int tmp0 = ctx->temp_reg;
5077 int tmp1 = r600_get_temp(ctx);
5078 int tmp2 = r600_get_temp(ctx);
5079 int tmp3 = r600_get_temp(ctx);
5080 /* Unsigned path:
5081 *
5082 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5083 *
5084 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5085 * 2. tmp0.z = lo (tmp0.x * src2)
5086 * 3. tmp0.w = -tmp0.z
5087 * 4. tmp0.y = hi (tmp0.x * src2)
5088 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5089 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5090 * 7. tmp1.x = tmp0.x - tmp0.w
5091 * 8. tmp1.y = tmp0.x + tmp0.w
5092 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5093 * 10. tmp0.z = hi(tmp0.x * src1) = q
5094 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5095 *
5096 * 12. tmp0.w = src1 - tmp0.y = r
5097 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5098 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5099 *
5100 * if DIV
5101 *
5102 * 15. tmp1.z = tmp0.z + 1 = q + 1
5103 * 16. tmp1.w = tmp0.z - 1 = q - 1
5104 *
5105 * else MOD
5106 *
5107 * 15. tmp1.z = tmp0.w - src2 = r - src2
5108 * 16. tmp1.w = tmp0.w + src2 = r + src2
5109 *
5110 * endif
5111 *
5112 * 17. tmp1.x = tmp1.x & tmp1.y
5113 *
5114 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5115 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5116 *
5117 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5118 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5119 *
5120 * Signed path:
5121 *
5122 * Same as unsigned, using abs values of the operands,
5123 * and fixing the sign of the result in the end.
5124 */
5125
5126 for (i = 0; i < 4; i++) {
5127 if (!(write_mask & (1<<i)))
5128 continue;
5129
5130 if (signed_op) {
5131
5132 /* tmp2.x = -src0 */
5133 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5134 alu.op = ALU_OP2_SUB_INT;
5135
5136 alu.dst.sel = tmp2;
5137 alu.dst.chan = 0;
5138 alu.dst.write = 1;
5139
5140 alu.src[0].sel = V_SQ_ALU_SRC_0;
5141
5142 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5143
5144 alu.last = 1;
5145 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5146 return r;
5147
5148 /* tmp2.y = -src1 */
5149 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5150 alu.op = ALU_OP2_SUB_INT;
5151
5152 alu.dst.sel = tmp2;
5153 alu.dst.chan = 1;
5154 alu.dst.write = 1;
5155
5156 alu.src[0].sel = V_SQ_ALU_SRC_0;
5157
5158 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5159
5160 alu.last = 1;
5161 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5162 return r;
5163
5164 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5165 /* it will be a sign of the quotient */
5166 if (!mod) {
5167
5168 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5169 alu.op = ALU_OP2_XOR_INT;
5170
5171 alu.dst.sel = tmp2;
5172 alu.dst.chan = 2;
5173 alu.dst.write = 1;
5174
5175 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5176 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5177
5178 alu.last = 1;
5179 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5180 return r;
5181 }
5182
5183 /* tmp2.x = |src0| */
5184 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5185 alu.op = ALU_OP3_CNDGE_INT;
5186 alu.is_op3 = 1;
5187
5188 alu.dst.sel = tmp2;
5189 alu.dst.chan = 0;
5190 alu.dst.write = 1;
5191
5192 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5193 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5194 alu.src[2].sel = tmp2;
5195 alu.src[2].chan = 0;
5196
5197 alu.last = 1;
5198 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5199 return r;
5200
5201 /* tmp2.y = |src1| */
5202 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5203 alu.op = ALU_OP3_CNDGE_INT;
5204 alu.is_op3 = 1;
5205
5206 alu.dst.sel = tmp2;
5207 alu.dst.chan = 1;
5208 alu.dst.write = 1;
5209
5210 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5211 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5212 alu.src[2].sel = tmp2;
5213 alu.src[2].chan = 1;
5214
5215 alu.last = 1;
5216 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5217 return r;
5218
5219 }
5220
5221 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5222 if (ctx->bc->chip_class == CAYMAN) {
5223 /* tmp3.x = u2f(src2) */
5224 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5225 alu.op = ALU_OP1_UINT_TO_FLT;
5226
5227 alu.dst.sel = tmp3;
5228 alu.dst.chan = 0;
5229 alu.dst.write = 1;
5230
5231 if (signed_op) {
5232 alu.src[0].sel = tmp2;
5233 alu.src[0].chan = 1;
5234 } else {
5235 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5236 }
5237
5238 alu.last = 1;
5239 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5240 return r;
5241
5242 /* tmp0.x = recip(tmp3.x) */
5243 for (j = 0 ; j < 3; j++) {
5244 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5245 alu.op = ALU_OP1_RECIP_IEEE;
5246
5247 alu.dst.sel = tmp0;
5248 alu.dst.chan = j;
5249 alu.dst.write = (j == 0);
5250
5251 alu.src[0].sel = tmp3;
5252 alu.src[0].chan = 0;
5253
5254 if (j == 2)
5255 alu.last = 1;
5256 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5257 return r;
5258 }
5259
5260 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5261 alu.op = ALU_OP2_MUL;
5262
5263 alu.src[0].sel = tmp0;
5264 alu.src[0].chan = 0;
5265
5266 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5267 alu.src[1].value = 0x4f800000;
5268
5269 alu.dst.sel = tmp3;
5270 alu.dst.write = 1;
5271 alu.last = 1;
5272 r = r600_bytecode_add_alu(ctx->bc, &alu);
5273 if (r)
5274 return r;
5275
5276 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5277 alu.op = ALU_OP1_FLT_TO_UINT;
5278
5279 alu.dst.sel = tmp0;
5280 alu.dst.chan = 0;
5281 alu.dst.write = 1;
5282
5283 alu.src[0].sel = tmp3;
5284 alu.src[0].chan = 0;
5285
5286 alu.last = 1;
5287 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5288 return r;
5289
5290 } else {
5291 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5292 alu.op = ALU_OP1_RECIP_UINT;
5293
5294 alu.dst.sel = tmp0;
5295 alu.dst.chan = 0;
5296 alu.dst.write = 1;
5297
5298 if (signed_op) {
5299 alu.src[0].sel = tmp2;
5300 alu.src[0].chan = 1;
5301 } else {
5302 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5303 }
5304
5305 alu.last = 1;
5306 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5307 return r;
5308 }
5309
5310 /* 2. tmp0.z = lo (tmp0.x * src2) */
5311 if (ctx->bc->chip_class == CAYMAN) {
5312 for (j = 0 ; j < 4; j++) {
5313 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5314 alu.op = ALU_OP2_MULLO_UINT;
5315
5316 alu.dst.sel = tmp0;
5317 alu.dst.chan = j;
5318 alu.dst.write = (j == 2);
5319
5320 alu.src[0].sel = tmp0;
5321 alu.src[0].chan = 0;
5322 if (signed_op) {
5323 alu.src[1].sel = tmp2;
5324 alu.src[1].chan = 1;
5325 } else {
5326 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5327 }
5328
5329 alu.last = (j == 3);
5330 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5331 return r;
5332 }
5333 } else {
5334 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5335 alu.op = ALU_OP2_MULLO_UINT;
5336
5337 alu.dst.sel = tmp0;
5338 alu.dst.chan = 2;
5339 alu.dst.write = 1;
5340
5341 alu.src[0].sel = tmp0;
5342 alu.src[0].chan = 0;
5343 if (signed_op) {
5344 alu.src[1].sel = tmp2;
5345 alu.src[1].chan = 1;
5346 } else {
5347 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5348 }
5349
5350 alu.last = 1;
5351 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5352 return r;
5353 }
5354
5355 /* 3. tmp0.w = -tmp0.z */
5356 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5357 alu.op = ALU_OP2_SUB_INT;
5358
5359 alu.dst.sel = tmp0;
5360 alu.dst.chan = 3;
5361 alu.dst.write = 1;
5362
5363 alu.src[0].sel = V_SQ_ALU_SRC_0;
5364 alu.src[1].sel = tmp0;
5365 alu.src[1].chan = 2;
5366
5367 alu.last = 1;
5368 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5369 return r;
5370
5371 /* 4. tmp0.y = hi (tmp0.x * src2) */
5372 if (ctx->bc->chip_class == CAYMAN) {
5373 for (j = 0 ; j < 4; j++) {
5374 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5375 alu.op = ALU_OP2_MULHI_UINT;
5376
5377 alu.dst.sel = tmp0;
5378 alu.dst.chan = j;
5379 alu.dst.write = (j == 1);
5380
5381 alu.src[0].sel = tmp0;
5382 alu.src[0].chan = 0;
5383
5384 if (signed_op) {
5385 alu.src[1].sel = tmp2;
5386 alu.src[1].chan = 1;
5387 } else {
5388 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5389 }
5390 alu.last = (j == 3);
5391 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5392 return r;
5393 }
5394 } else {
5395 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5396 alu.op = ALU_OP2_MULHI_UINT;
5397
5398 alu.dst.sel = tmp0;
5399 alu.dst.chan = 1;
5400 alu.dst.write = 1;
5401
5402 alu.src[0].sel = tmp0;
5403 alu.src[0].chan = 0;
5404
5405 if (signed_op) {
5406 alu.src[1].sel = tmp2;
5407 alu.src[1].chan = 1;
5408 } else {
5409 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5410 }
5411
5412 alu.last = 1;
5413 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5414 return r;
5415 }
5416
5417 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5418 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5419 alu.op = ALU_OP3_CNDE_INT;
5420 alu.is_op3 = 1;
5421
5422 alu.dst.sel = tmp0;
5423 alu.dst.chan = 2;
5424 alu.dst.write = 1;
5425
5426 alu.src[0].sel = tmp0;
5427 alu.src[0].chan = 1;
5428 alu.src[1].sel = tmp0;
5429 alu.src[1].chan = 3;
5430 alu.src[2].sel = tmp0;
5431 alu.src[2].chan = 2;
5432
5433 alu.last = 1;
5434 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5435 return r;
5436
5437 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5438 if (ctx->bc->chip_class == CAYMAN) {
5439 for (j = 0 ; j < 4; j++) {
5440 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5441 alu.op = ALU_OP2_MULHI_UINT;
5442
5443 alu.dst.sel = tmp0;
5444 alu.dst.chan = j;
5445 alu.dst.write = (j == 3);
5446
5447 alu.src[0].sel = tmp0;
5448 alu.src[0].chan = 2;
5449
5450 alu.src[1].sel = tmp0;
5451 alu.src[1].chan = 0;
5452
5453 alu.last = (j == 3);
5454 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5455 return r;
5456 }
5457 } else {
5458 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5459 alu.op = ALU_OP2_MULHI_UINT;
5460
5461 alu.dst.sel = tmp0;
5462 alu.dst.chan = 3;
5463 alu.dst.write = 1;
5464
5465 alu.src[0].sel = tmp0;
5466 alu.src[0].chan = 2;
5467
5468 alu.src[1].sel = tmp0;
5469 alu.src[1].chan = 0;
5470
5471 alu.last = 1;
5472 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5473 return r;
5474 }
5475
5476 /* 7. tmp1.x = tmp0.x - tmp0.w */
5477 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5478 alu.op = ALU_OP2_SUB_INT;
5479
5480 alu.dst.sel = tmp1;
5481 alu.dst.chan = 0;
5482 alu.dst.write = 1;
5483
5484 alu.src[0].sel = tmp0;
5485 alu.src[0].chan = 0;
5486 alu.src[1].sel = tmp0;
5487 alu.src[1].chan = 3;
5488
5489 alu.last = 1;
5490 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5491 return r;
5492
5493 /* 8. tmp1.y = tmp0.x + tmp0.w */
5494 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5495 alu.op = ALU_OP2_ADD_INT;
5496
5497 alu.dst.sel = tmp1;
5498 alu.dst.chan = 1;
5499 alu.dst.write = 1;
5500
5501 alu.src[0].sel = tmp0;
5502 alu.src[0].chan = 0;
5503 alu.src[1].sel = tmp0;
5504 alu.src[1].chan = 3;
5505
5506 alu.last = 1;
5507 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5508 return r;
5509
5510 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5511 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5512 alu.op = ALU_OP3_CNDE_INT;
5513 alu.is_op3 = 1;
5514
5515 alu.dst.sel = tmp0;
5516 alu.dst.chan = 0;
5517 alu.dst.write = 1;
5518
5519 alu.src[0].sel = tmp0;
5520 alu.src[0].chan = 1;
5521 alu.src[1].sel = tmp1;
5522 alu.src[1].chan = 1;
5523 alu.src[2].sel = tmp1;
5524 alu.src[2].chan = 0;
5525
5526 alu.last = 1;
5527 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5528 return r;
5529
5530 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5531 if (ctx->bc->chip_class == CAYMAN) {
5532 for (j = 0 ; j < 4; j++) {
5533 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5534 alu.op = ALU_OP2_MULHI_UINT;
5535
5536 alu.dst.sel = tmp0;
5537 alu.dst.chan = j;
5538 alu.dst.write = (j == 2);
5539
5540 alu.src[0].sel = tmp0;
5541 alu.src[0].chan = 0;
5542
5543 if (signed_op) {
5544 alu.src[1].sel = tmp2;
5545 alu.src[1].chan = 0;
5546 } else {
5547 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5548 }
5549
5550 alu.last = (j == 3);
5551 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5552 return r;
5553 }
5554 } else {
5555 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5556 alu.op = ALU_OP2_MULHI_UINT;
5557
5558 alu.dst.sel = tmp0;
5559 alu.dst.chan = 2;
5560 alu.dst.write = 1;
5561
5562 alu.src[0].sel = tmp0;
5563 alu.src[0].chan = 0;
5564
5565 if (signed_op) {
5566 alu.src[1].sel = tmp2;
5567 alu.src[1].chan = 0;
5568 } else {
5569 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5570 }
5571
5572 alu.last = 1;
5573 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5574 return r;
5575 }
5576
5577 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5578 if (ctx->bc->chip_class == CAYMAN) {
5579 for (j = 0 ; j < 4; j++) {
5580 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5581 alu.op = ALU_OP2_MULLO_UINT;
5582
5583 alu.dst.sel = tmp0;
5584 alu.dst.chan = j;
5585 alu.dst.write = (j == 1);
5586
5587 if (signed_op) {
5588 alu.src[0].sel = tmp2;
5589 alu.src[0].chan = 1;
5590 } else {
5591 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5592 }
5593
5594 alu.src[1].sel = tmp0;
5595 alu.src[1].chan = 2;
5596
5597 alu.last = (j == 3);
5598 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5599 return r;
5600 }
5601 } else {
5602 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5603 alu.op = ALU_OP2_MULLO_UINT;
5604
5605 alu.dst.sel = tmp0;
5606 alu.dst.chan = 1;
5607 alu.dst.write = 1;
5608
5609 if (signed_op) {
5610 alu.src[0].sel = tmp2;
5611 alu.src[0].chan = 1;
5612 } else {
5613 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5614 }
5615
5616 alu.src[1].sel = tmp0;
5617 alu.src[1].chan = 2;
5618
5619 alu.last = 1;
5620 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5621 return r;
5622 }
5623
5624 /* 12. tmp0.w = src1 - tmp0.y = r */
5625 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5626 alu.op = ALU_OP2_SUB_INT;
5627
5628 alu.dst.sel = tmp0;
5629 alu.dst.chan = 3;
5630 alu.dst.write = 1;
5631
5632 if (signed_op) {
5633 alu.src[0].sel = tmp2;
5634 alu.src[0].chan = 0;
5635 } else {
5636 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5637 }
5638
5639 alu.src[1].sel = tmp0;
5640 alu.src[1].chan = 1;
5641
5642 alu.last = 1;
5643 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5644 return r;
5645
5646 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5647 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5648 alu.op = ALU_OP2_SETGE_UINT;
5649
5650 alu.dst.sel = tmp1;
5651 alu.dst.chan = 0;
5652 alu.dst.write = 1;
5653
5654 alu.src[0].sel = tmp0;
5655 alu.src[0].chan = 3;
5656 if (signed_op) {
5657 alu.src[1].sel = tmp2;
5658 alu.src[1].chan = 1;
5659 } else {
5660 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5661 }
5662
5663 alu.last = 1;
5664 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5665 return r;
5666
5667 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5668 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5669 alu.op = ALU_OP2_SETGE_UINT;
5670
5671 alu.dst.sel = tmp1;
5672 alu.dst.chan = 1;
5673 alu.dst.write = 1;
5674
5675 if (signed_op) {
5676 alu.src[0].sel = tmp2;
5677 alu.src[0].chan = 0;
5678 } else {
5679 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5680 }
5681
5682 alu.src[1].sel = tmp0;
5683 alu.src[1].chan = 1;
5684
5685 alu.last = 1;
5686 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5687 return r;
5688
5689 if (mod) { /* UMOD */
5690
5691 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5692 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5693 alu.op = ALU_OP2_SUB_INT;
5694
5695 alu.dst.sel = tmp1;
5696 alu.dst.chan = 2;
5697 alu.dst.write = 1;
5698
5699 alu.src[0].sel = tmp0;
5700 alu.src[0].chan = 3;
5701
5702 if (signed_op) {
5703 alu.src[1].sel = tmp2;
5704 alu.src[1].chan = 1;
5705 } else {
5706 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5707 }
5708
5709 alu.last = 1;
5710 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5711 return r;
5712
5713 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5714 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5715 alu.op = ALU_OP2_ADD_INT;
5716
5717 alu.dst.sel = tmp1;
5718 alu.dst.chan = 3;
5719 alu.dst.write = 1;
5720
5721 alu.src[0].sel = tmp0;
5722 alu.src[0].chan = 3;
5723 if (signed_op) {
5724 alu.src[1].sel = tmp2;
5725 alu.src[1].chan = 1;
5726 } else {
5727 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5728 }
5729
5730 alu.last = 1;
5731 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5732 return r;
5733
5734 } else { /* UDIV */
5735
5736 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5737 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5738 alu.op = ALU_OP2_ADD_INT;
5739
5740 alu.dst.sel = tmp1;
5741 alu.dst.chan = 2;
5742 alu.dst.write = 1;
5743
5744 alu.src[0].sel = tmp0;
5745 alu.src[0].chan = 2;
5746 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5747
5748 alu.last = 1;
5749 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5750 return r;
5751
5752 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5753 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5754 alu.op = ALU_OP2_ADD_INT;
5755
5756 alu.dst.sel = tmp1;
5757 alu.dst.chan = 3;
5758 alu.dst.write = 1;
5759
5760 alu.src[0].sel = tmp0;
5761 alu.src[0].chan = 2;
5762 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
5763
5764 alu.last = 1;
5765 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5766 return r;
5767
5768 }
5769
5770 /* 17. tmp1.x = tmp1.x & tmp1.y */
5771 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5772 alu.op = ALU_OP2_AND_INT;
5773
5774 alu.dst.sel = tmp1;
5775 alu.dst.chan = 0;
5776 alu.dst.write = 1;
5777
5778 alu.src[0].sel = tmp1;
5779 alu.src[0].chan = 0;
5780 alu.src[1].sel = tmp1;
5781 alu.src[1].chan = 1;
5782
5783 alu.last = 1;
5784 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5785 return r;
5786
5787 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5788 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5789 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5790 alu.op = ALU_OP3_CNDE_INT;
5791 alu.is_op3 = 1;
5792
5793 alu.dst.sel = tmp0;
5794 alu.dst.chan = 2;
5795 alu.dst.write = 1;
5796
5797 alu.src[0].sel = tmp1;
5798 alu.src[0].chan = 0;
5799 alu.src[1].sel = tmp0;
5800 alu.src[1].chan = mod ? 3 : 2;
5801 alu.src[2].sel = tmp1;
5802 alu.src[2].chan = 2;
5803
5804 alu.last = 1;
5805 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5806 return r;
5807
5808 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5809 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5810 alu.op = ALU_OP3_CNDE_INT;
5811 alu.is_op3 = 1;
5812
5813 if (signed_op) {
5814 alu.dst.sel = tmp0;
5815 alu.dst.chan = 2;
5816 alu.dst.write = 1;
5817 } else {
5818 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5819 }
5820
5821 alu.src[0].sel = tmp1;
5822 alu.src[0].chan = 1;
5823 alu.src[1].sel = tmp1;
5824 alu.src[1].chan = 3;
5825 alu.src[2].sel = tmp0;
5826 alu.src[2].chan = 2;
5827
5828 alu.last = 1;
5829 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5830 return r;
5831
5832 if (signed_op) {
5833
5834 /* fix the sign of the result */
5835
5836 if (mod) {
5837
5838 /* tmp0.x = -tmp0.z */
5839 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5840 alu.op = ALU_OP2_SUB_INT;
5841
5842 alu.dst.sel = tmp0;
5843 alu.dst.chan = 0;
5844 alu.dst.write = 1;
5845
5846 alu.src[0].sel = V_SQ_ALU_SRC_0;
5847 alu.src[1].sel = tmp0;
5848 alu.src[1].chan = 2;
5849
5850 alu.last = 1;
5851 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5852 return r;
5853
5854 /* sign of the remainder is the same as the sign of src0 */
5855 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5856 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5857 alu.op = ALU_OP3_CNDGE_INT;
5858 alu.is_op3 = 1;
5859
5860 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5861
5862 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5863 alu.src[1].sel = tmp0;
5864 alu.src[1].chan = 2;
5865 alu.src[2].sel = tmp0;
5866 alu.src[2].chan = 0;
5867
5868 alu.last = 1;
5869 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5870 return r;
5871
5872 } else {
5873
5874 /* tmp0.x = -tmp0.z */
5875 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5876 alu.op = ALU_OP2_SUB_INT;
5877
5878 alu.dst.sel = tmp0;
5879 alu.dst.chan = 0;
5880 alu.dst.write = 1;
5881
5882 alu.src[0].sel = V_SQ_ALU_SRC_0;
5883 alu.src[1].sel = tmp0;
5884 alu.src[1].chan = 2;
5885
5886 alu.last = 1;
5887 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5888 return r;
5889
5890 /* fix the quotient sign (same as the sign of src0*src1) */
5891 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5892 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5893 alu.op = ALU_OP3_CNDGE_INT;
5894 alu.is_op3 = 1;
5895
5896 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5897
5898 alu.src[0].sel = tmp2;
5899 alu.src[0].chan = 2;
5900 alu.src[1].sel = tmp0;
5901 alu.src[1].chan = 2;
5902 alu.src[2].sel = tmp0;
5903 alu.src[2].chan = 0;
5904
5905 alu.last = 1;
5906 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5907 return r;
5908 }
5909 }
5910 }
5911 return 0;
5912 }
5913
5914 static int tgsi_udiv(struct r600_shader_ctx *ctx)
5915 {
5916 return tgsi_divmod(ctx, 0, 0);
5917 }
5918
5919 static int tgsi_umod(struct r600_shader_ctx *ctx)
5920 {
5921 return tgsi_divmod(ctx, 1, 0);
5922 }
5923
5924 static int tgsi_idiv(struct r600_shader_ctx *ctx)
5925 {
5926 return tgsi_divmod(ctx, 0, 1);
5927 }
5928
5929 static int tgsi_imod(struct r600_shader_ctx *ctx)
5930 {
5931 return tgsi_divmod(ctx, 1, 1);
5932 }
5933
5934
5935 static int tgsi_f2i(struct r600_shader_ctx *ctx)
5936 {
5937 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5938 struct r600_bytecode_alu alu;
5939 int i, r;
5940 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5941 int last_inst = tgsi_last_instruction(write_mask);
5942
5943 for (i = 0; i < 4; i++) {
5944 if (!(write_mask & (1<<i)))
5945 continue;
5946
5947 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5948 alu.op = ALU_OP1_TRUNC;
5949
5950 alu.dst.sel = ctx->temp_reg;
5951 alu.dst.chan = i;
5952 alu.dst.write = 1;
5953
5954 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5955 if (i == last_inst)
5956 alu.last = 1;
5957 r = r600_bytecode_add_alu(ctx->bc, &alu);
5958 if (r)
5959 return r;
5960 }
5961
5962 for (i = 0; i < 4; i++) {
5963 if (!(write_mask & (1<<i)))
5964 continue;
5965
5966 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5967 alu.op = ctx->inst_info->op;
5968
5969 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5970
5971 alu.src[0].sel = ctx->temp_reg;
5972 alu.src[0].chan = i;
5973
5974 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
5975 alu.last = 1;
5976 r = r600_bytecode_add_alu(ctx->bc, &alu);
5977 if (r)
5978 return r;
5979 }
5980
5981 return 0;
5982 }
5983
5984 static int tgsi_iabs(struct r600_shader_ctx *ctx)
5985 {
5986 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5987 struct r600_bytecode_alu alu;
5988 int i, r;
5989 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5990 int last_inst = tgsi_last_instruction(write_mask);
5991
5992 /* tmp = -src */
5993 for (i = 0; i < 4; i++) {
5994 if (!(write_mask & (1<<i)))
5995 continue;
5996
5997 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5998 alu.op = ALU_OP2_SUB_INT;
5999
6000 alu.dst.sel = ctx->temp_reg;
6001 alu.dst.chan = i;
6002 alu.dst.write = 1;
6003
6004 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6005 alu.src[0].sel = V_SQ_ALU_SRC_0;
6006
6007 if (i == last_inst)
6008 alu.last = 1;
6009 r = r600_bytecode_add_alu(ctx->bc, &alu);
6010 if (r)
6011 return r;
6012 }
6013
6014 /* dst = (src >= 0 ? src : tmp) */
6015 for (i = 0; i < 4; i++) {
6016 if (!(write_mask & (1<<i)))
6017 continue;
6018
6019 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6020 alu.op = ALU_OP3_CNDGE_INT;
6021 alu.is_op3 = 1;
6022 alu.dst.write = 1;
6023
6024 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6025
6026 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6027 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6028 alu.src[2].sel = ctx->temp_reg;
6029 alu.src[2].chan = i;
6030
6031 if (i == last_inst)
6032 alu.last = 1;
6033 r = r600_bytecode_add_alu(ctx->bc, &alu);
6034 if (r)
6035 return r;
6036 }
6037 return 0;
6038 }
6039
6040 static int tgsi_issg(struct r600_shader_ctx *ctx)
6041 {
6042 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6043 struct r600_bytecode_alu alu;
6044 int i, r;
6045 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6046 int last_inst = tgsi_last_instruction(write_mask);
6047
6048 /* tmp = (src >= 0 ? src : -1) */
6049 for (i = 0; i < 4; i++) {
6050 if (!(write_mask & (1<<i)))
6051 continue;
6052
6053 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6054 alu.op = ALU_OP3_CNDGE_INT;
6055 alu.is_op3 = 1;
6056
6057 alu.dst.sel = ctx->temp_reg;
6058 alu.dst.chan = i;
6059 alu.dst.write = 1;
6060
6061 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6062 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6063 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6064
6065 if (i == last_inst)
6066 alu.last = 1;
6067 r = r600_bytecode_add_alu(ctx->bc, &alu);
6068 if (r)
6069 return r;
6070 }
6071
6072 /* dst = (tmp > 0 ? 1 : tmp) */
6073 for (i = 0; i < 4; i++) {
6074 if (!(write_mask & (1<<i)))
6075 continue;
6076
6077 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6078 alu.op = ALU_OP3_CNDGT_INT;
6079 alu.is_op3 = 1;
6080 alu.dst.write = 1;
6081
6082 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6083
6084 alu.src[0].sel = ctx->temp_reg;
6085 alu.src[0].chan = i;
6086
6087 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6088
6089 alu.src[2].sel = ctx->temp_reg;
6090 alu.src[2].chan = i;
6091
6092 if (i == last_inst)
6093 alu.last = 1;
6094 r = r600_bytecode_add_alu(ctx->bc, &alu);
6095 if (r)
6096 return r;
6097 }
6098 return 0;
6099 }
6100
6101
6102
6103 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6104 {
6105 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6106 struct r600_bytecode_alu alu;
6107 int i, r;
6108
6109 /* tmp = (src > 0 ? 1 : src) */
6110 for (i = 0; i < 4; i++) {
6111 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6112 alu.op = ALU_OP3_CNDGT;
6113 alu.is_op3 = 1;
6114
6115 alu.dst.sel = ctx->temp_reg;
6116 alu.dst.chan = i;
6117
6118 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6119 alu.src[1].sel = V_SQ_ALU_SRC_1;
6120 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6121
6122 if (i == 3)
6123 alu.last = 1;
6124 r = r600_bytecode_add_alu(ctx->bc, &alu);
6125 if (r)
6126 return r;
6127 }
6128
6129 /* dst = (-tmp > 0 ? -1 : tmp) */
6130 for (i = 0; i < 4; i++) {
6131 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6132 alu.op = ALU_OP3_CNDGT;
6133 alu.is_op3 = 1;
6134 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6135
6136 alu.src[0].sel = ctx->temp_reg;
6137 alu.src[0].chan = i;
6138 alu.src[0].neg = 1;
6139
6140 alu.src[1].sel = V_SQ_ALU_SRC_1;
6141 alu.src[1].neg = 1;
6142
6143 alu.src[2].sel = ctx->temp_reg;
6144 alu.src[2].chan = i;
6145
6146 if (i == 3)
6147 alu.last = 1;
6148 r = r600_bytecode_add_alu(ctx->bc, &alu);
6149 if (r)
6150 return r;
6151 }
6152 return 0;
6153 }
6154
6155 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6156 {
6157 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6158 struct r600_bytecode_alu alu;
6159 int i, r, t1, t2;
6160
6161 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6162 int last_inst = tgsi_last_instruction(write_mask);
6163
6164 t1 = ctx->temp_reg;
6165
6166 for (i = 0; i < 4; i++) {
6167 if (!(write_mask & (1<<i)))
6168 continue;
6169
6170 /* create mask tmp */
6171 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6172 alu.op = ALU_OP2_BFM_INT;
6173 alu.dst.sel = t1;
6174 alu.dst.chan = i;
6175 alu.dst.write = 1;
6176 alu.last = i == last_inst;
6177
6178 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6179 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6180
6181 r = r600_bytecode_add_alu(ctx->bc, &alu);
6182 if (r)
6183 return r;
6184 }
6185
6186 t2 = r600_get_temp(ctx);
6187
6188 for (i = 0; i < 4; i++) {
6189 if (!(write_mask & (1<<i)))
6190 continue;
6191
6192 /* shift insert left */
6193 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6194 alu.op = ALU_OP2_LSHL_INT;
6195 alu.dst.sel = t2;
6196 alu.dst.chan = i;
6197 alu.dst.write = 1;
6198 alu.last = i == last_inst;
6199
6200 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6201 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6202
6203 r = r600_bytecode_add_alu(ctx->bc, &alu);
6204 if (r)
6205 return r;
6206 }
6207
6208 for (i = 0; i < 4; i++) {
6209 if (!(write_mask & (1<<i)))
6210 continue;
6211
6212 /* actual bitfield insert */
6213 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6214 alu.op = ALU_OP3_BFI_INT;
6215 alu.is_op3 = 1;
6216 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6217 alu.dst.chan = i;
6218 alu.dst.write = 1;
6219 alu.last = i == last_inst;
6220
6221 alu.src[0].sel = t1;
6222 alu.src[0].chan = i;
6223 alu.src[1].sel = t2;
6224 alu.src[1].chan = i;
6225 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6226
6227 r = r600_bytecode_add_alu(ctx->bc, &alu);
6228 if (r)
6229 return r;
6230 }
6231
6232 return 0;
6233 }
6234
6235 static int tgsi_msb(struct r600_shader_ctx *ctx)
6236 {
6237 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6238 struct r600_bytecode_alu alu;
6239 int i, r, t1, t2;
6240
6241 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6242 int last_inst = tgsi_last_instruction(write_mask);
6243
6244 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6245 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6246
6247 t1 = ctx->temp_reg;
6248
6249 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6250 for (i = 0; i < 4; i++) {
6251 if (!(write_mask & (1<<i)))
6252 continue;
6253
6254 /* t1 = FFBH_INT / FFBH_UINT */
6255 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6256 alu.op = ctx->inst_info->op;
6257 alu.dst.sel = t1;
6258 alu.dst.chan = i;
6259 alu.dst.write = 1;
6260 alu.last = i == last_inst;
6261
6262 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6263
6264 r = r600_bytecode_add_alu(ctx->bc, &alu);
6265 if (r)
6266 return r;
6267 }
6268
6269 t2 = r600_get_temp(ctx);
6270
6271 for (i = 0; i < 4; i++) {
6272 if (!(write_mask & (1<<i)))
6273 continue;
6274
6275 /* t2 = 31 - t1 */
6276 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6277 alu.op = ALU_OP2_SUB_INT;
6278 alu.dst.sel = t2;
6279 alu.dst.chan = i;
6280 alu.dst.write = 1;
6281 alu.last = i == last_inst;
6282
6283 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6284 alu.src[0].value = 31;
6285 alu.src[1].sel = t1;
6286 alu.src[1].chan = i;
6287
6288 r = r600_bytecode_add_alu(ctx->bc, &alu);
6289 if (r)
6290 return r;
6291 }
6292
6293 for (i = 0; i < 4; i++) {
6294 if (!(write_mask & (1<<i)))
6295 continue;
6296
6297 /* result = t1 >= 0 ? t2 : t1 */
6298 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6299 alu.op = ALU_OP3_CNDGE_INT;
6300 alu.is_op3 = 1;
6301 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6302 alu.dst.chan = i;
6303 alu.dst.write = 1;
6304 alu.last = i == last_inst;
6305
6306 alu.src[0].sel = t1;
6307 alu.src[0].chan = i;
6308 alu.src[1].sel = t2;
6309 alu.src[1].chan = i;
6310 alu.src[2].sel = t1;
6311 alu.src[2].chan = i;
6312
6313 r = r600_bytecode_add_alu(ctx->bc, &alu);
6314 if (r)
6315 return r;
6316 }
6317
6318 return 0;
6319 }
6320
6321 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6322 {
6323 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6324 struct r600_bytecode_alu alu;
6325 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6326 unsigned location;
6327 const int input = inst->Src[0].Register.Index + ctx->shader->nsys_inputs;
6328
6329 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6330
6331 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6332 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6333 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6334 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6335 }
6336 else {
6337 location = TGSI_INTERPOLATE_LOC_CENTROID;
6338 }
6339
6340 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6341 if (k < 0)
6342 k = 0;
6343 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6344 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6345
6346 /* NOTE: currently offset is not perspective correct */
6347 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6348 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6349 int sample_gpr = -1;
6350 int gradientsH, gradientsV;
6351 struct r600_bytecode_tex tex;
6352
6353 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6354 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6355 }
6356
6357 gradientsH = r600_get_temp(ctx);
6358 gradientsV = r600_get_temp(ctx);
6359 for (i = 0; i < 2; i++) {
6360 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6361 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6362 tex.src_gpr = interp_gpr;
6363 tex.src_sel_x = interp_base_chan + 0;
6364 tex.src_sel_y = interp_base_chan + 1;
6365 tex.src_sel_z = 0;
6366 tex.src_sel_w = 0;
6367 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6368 tex.dst_sel_x = 0;
6369 tex.dst_sel_y = 1;
6370 tex.dst_sel_z = 7;
6371 tex.dst_sel_w = 7;
6372 tex.inst_mod = 1; // Use per pixel gradient calculation
6373 tex.sampler_id = 0;
6374 tex.resource_id = tex.sampler_id;
6375 r = r600_bytecode_add_tex(ctx->bc, &tex);
6376 if (r)
6377 return r;
6378 }
6379
6380 for (i = 0; i < 2; i++) {
6381 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6382 alu.op = ALU_OP3_MULADD;
6383 alu.is_op3 = 1;
6384 alu.src[0].sel = gradientsH;
6385 alu.src[0].chan = i;
6386 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6387 alu.src[1].sel = sample_gpr;
6388 alu.src[1].chan = 2;
6389 }
6390 else {
6391 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6392 }
6393 alu.src[2].sel = interp_gpr;
6394 alu.src[2].chan = interp_base_chan + i;
6395 alu.dst.sel = ctx->temp_reg;
6396 alu.dst.chan = i;
6397 alu.last = i == 1;
6398
6399 r = r600_bytecode_add_alu(ctx->bc, &alu);
6400 if (r)
6401 return r;
6402 }
6403
6404 for (i = 0; i < 2; i++) {
6405 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6406 alu.op = ALU_OP3_MULADD;
6407 alu.is_op3 = 1;
6408 alu.src[0].sel = gradientsV;
6409 alu.src[0].chan = i;
6410 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6411 alu.src[1].sel = sample_gpr;
6412 alu.src[1].chan = 3;
6413 }
6414 else {
6415 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6416 }
6417 alu.src[2].sel = ctx->temp_reg;
6418 alu.src[2].chan = i;
6419 alu.dst.sel = ctx->temp_reg;
6420 alu.dst.chan = i;
6421 alu.last = i == 1;
6422
6423 r = r600_bytecode_add_alu(ctx->bc, &alu);
6424 if (r)
6425 return r;
6426 }
6427 }
6428
6429 tmp = r600_get_temp(ctx);
6430 for (i = 0; i < 8; i++) {
6431 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6432 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6433
6434 alu.dst.sel = tmp;
6435 if ((i > 1 && i < 6)) {
6436 alu.dst.write = 1;
6437 }
6438 else {
6439 alu.dst.write = 0;
6440 }
6441 alu.dst.chan = i % 4;
6442
6443 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6444 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6445 alu.src[0].sel = ctx->temp_reg;
6446 alu.src[0].chan = 1 - (i % 2);
6447 } else {
6448 alu.src[0].sel = interp_gpr;
6449 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
6450 }
6451 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
6452 alu.src[1].chan = 0;
6453
6454 alu.last = i % 4 == 3;
6455 alu.bank_swizzle_force = SQ_ALU_VEC_210;
6456
6457 r = r600_bytecode_add_alu(ctx->bc, &alu);
6458 if (r)
6459 return r;
6460 }
6461
6462 // INTERP can't swizzle dst
6463 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6464 for (i = 0; i <= lasti; i++) {
6465 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6466 continue;
6467
6468 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6469 alu.op = ALU_OP1_MOV;
6470 alu.src[0].sel = tmp;
6471 alu.src[0].chan = ctx->src[0].swizzle[i];
6472 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6473 alu.dst.write = 1;
6474 alu.last = i == lasti;
6475 r = r600_bytecode_add_alu(ctx->bc, &alu);
6476 if (r)
6477 return r;
6478 }
6479
6480 return 0;
6481 }
6482
6483
6484 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
6485 {
6486 struct r600_bytecode_alu alu;
6487 int i, r;
6488
6489 for (i = 0; i < 4; i++) {
6490 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6491 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
6492 alu.op = ALU_OP0_NOP;
6493 alu.dst.chan = i;
6494 } else {
6495 alu.op = ALU_OP1_MOV;
6496 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6497 alu.src[0].sel = ctx->temp_reg;
6498 alu.src[0].chan = i;
6499 }
6500 if (i == 3) {
6501 alu.last = 1;
6502 }
6503 r = r600_bytecode_add_alu(ctx->bc, &alu);
6504 if (r)
6505 return r;
6506 }
6507 return 0;
6508 }
6509
6510 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
6511 unsigned temp, int chan,
6512 struct r600_bytecode_alu_src *bc_src,
6513 const struct r600_shader_src *shader_src)
6514 {
6515 struct r600_bytecode_alu alu;
6516 int r;
6517
6518 r600_bytecode_src(bc_src, shader_src, chan);
6519
6520 /* op3 operands don't support abs modifier */
6521 if (bc_src->abs) {
6522 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
6523 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6524 alu.op = ALU_OP1_MOV;
6525 alu.dst.sel = temp;
6526 alu.dst.chan = chan;
6527 alu.dst.write = 1;
6528
6529 alu.src[0] = *bc_src;
6530 alu.last = true; // sufficient?
6531 r = r600_bytecode_add_alu(ctx->bc, &alu);
6532 if (r)
6533 return r;
6534
6535 memset(bc_src, 0, sizeof(*bc_src));
6536 bc_src->sel = temp;
6537 bc_src->chan = chan;
6538 }
6539 return 0;
6540 }
6541
6542 static int tgsi_op3(struct r600_shader_ctx *ctx)
6543 {
6544 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6545 struct r600_bytecode_alu alu;
6546 int i, j, r;
6547 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6548 int temp_regs[4];
6549 unsigned op = ctx->inst_info->op;
6550
6551 if (op == ALU_OP3_MULADD_IEEE &&
6552 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6553 op = ALU_OP3_MULADD;
6554
6555 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6556 temp_regs[j] = 0;
6557 if (ctx->src[j].abs)
6558 temp_regs[j] = r600_get_temp(ctx);
6559 }
6560 for (i = 0; i < lasti + 1; i++) {
6561 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6562 continue;
6563
6564 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6565 alu.op = op;
6566 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6567 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
6568 if (r)
6569 return r;
6570 }
6571
6572 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6573 alu.dst.chan = i;
6574 alu.dst.write = 1;
6575 alu.is_op3 = 1;
6576 if (i == lasti) {
6577 alu.last = 1;
6578 }
6579 r = r600_bytecode_add_alu(ctx->bc, &alu);
6580 if (r)
6581 return r;
6582 }
6583 return 0;
6584 }
6585
6586 static int tgsi_dp(struct r600_shader_ctx *ctx)
6587 {
6588 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6589 struct r600_bytecode_alu alu;
6590 int i, j, r;
6591 unsigned op = ctx->inst_info->op;
6592 if (op == ALU_OP2_DOT4_IEEE &&
6593 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6594 op = ALU_OP2_DOT4;
6595
6596 for (i = 0; i < 4; i++) {
6597 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6598 alu.op = op;
6599 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6600 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6601 }
6602
6603 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6604 alu.dst.chan = i;
6605 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
6606 /* handle some special cases */
6607 switch (inst->Instruction.Opcode) {
6608 case TGSI_OPCODE_DP2:
6609 if (i > 1) {
6610 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6611 alu.src[0].chan = alu.src[1].chan = 0;
6612 }
6613 break;
6614 case TGSI_OPCODE_DP3:
6615 if (i > 2) {
6616 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6617 alu.src[0].chan = alu.src[1].chan = 0;
6618 }
6619 break;
6620 case TGSI_OPCODE_DPH:
6621 if (i == 3) {
6622 alu.src[0].sel = V_SQ_ALU_SRC_1;
6623 alu.src[0].chan = 0;
6624 alu.src[0].neg = 0;
6625 }
6626 break;
6627 default:
6628 break;
6629 }
6630 if (i == 3) {
6631 alu.last = 1;
6632 }
6633 r = r600_bytecode_add_alu(ctx->bc, &alu);
6634 if (r)
6635 return r;
6636 }
6637 return 0;
6638 }
6639
6640 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
6641 unsigned index)
6642 {
6643 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6644 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
6645 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
6646 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
6647 ctx->src[index].neg || ctx->src[index].abs ||
6648 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
6649 }
6650
6651 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
6652 unsigned index)
6653 {
6654 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6655 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
6656 }
6657
6658 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
6659 {
6660 struct r600_bytecode_vtx vtx;
6661 struct r600_bytecode_alu alu;
6662 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6663 int src_gpr, r, i;
6664 int id = tgsi_tex_get_src_gpr(ctx, 1);
6665
6666 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6667 if (src_requires_loading) {
6668 for (i = 0; i < 4; i++) {
6669 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6670 alu.op = ALU_OP1_MOV;
6671 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6672 alu.dst.sel = ctx->temp_reg;
6673 alu.dst.chan = i;
6674 if (i == 3)
6675 alu.last = 1;
6676 alu.dst.write = 1;
6677 r = r600_bytecode_add_alu(ctx->bc, &alu);
6678 if (r)
6679 return r;
6680 }
6681 src_gpr = ctx->temp_reg;
6682 }
6683
6684 memset(&vtx, 0, sizeof(vtx));
6685 vtx.op = FETCH_OP_VFETCH;
6686 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6687 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6688 vtx.src_gpr = src_gpr;
6689 vtx.mega_fetch_count = 16;
6690 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6691 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6692 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
6693 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
6694 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
6695 vtx.use_const_fields = 1;
6696
6697 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
6698 return r;
6699
6700 if (ctx->bc->chip_class >= EVERGREEN)
6701 return 0;
6702
6703 for (i = 0; i < 4; i++) {
6704 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6705 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6706 continue;
6707
6708 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6709 alu.op = ALU_OP2_AND_INT;
6710
6711 alu.dst.chan = i;
6712 alu.dst.sel = vtx.dst_gpr;
6713 alu.dst.write = 1;
6714
6715 alu.src[0].sel = vtx.dst_gpr;
6716 alu.src[0].chan = i;
6717
6718 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
6719 alu.src[1].sel += (id * 2);
6720 alu.src[1].chan = i % 4;
6721 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6722
6723 if (i == lasti)
6724 alu.last = 1;
6725 r = r600_bytecode_add_alu(ctx->bc, &alu);
6726 if (r)
6727 return r;
6728 }
6729
6730 if (inst->Dst[0].Register.WriteMask & 3) {
6731 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6732 alu.op = ALU_OP2_OR_INT;
6733
6734 alu.dst.chan = 3;
6735 alu.dst.sel = vtx.dst_gpr;
6736 alu.dst.write = 1;
6737
6738 alu.src[0].sel = vtx.dst_gpr;
6739 alu.src[0].chan = 3;
6740
6741 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
6742 alu.src[1].chan = 0;
6743 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6744
6745 alu.last = 1;
6746 r = r600_bytecode_add_alu(ctx->bc, &alu);
6747 if (r)
6748 return r;
6749 }
6750 return 0;
6751 }
6752
6753 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
6754 {
6755 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6756 struct r600_bytecode_alu alu;
6757 int r;
6758 int id = tgsi_tex_get_src_gpr(ctx, 1);
6759
6760 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6761 alu.op = ALU_OP1_MOV;
6762 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6763 if (ctx->bc->chip_class >= EVERGREEN) {
6764 /* channel 0 or 2 of each word */
6765 alu.src[0].sel += (id / 2);
6766 alu.src[0].chan = (id % 2) * 2;
6767 } else {
6768 /* r600 we have them at channel 2 of the second dword */
6769 alu.src[0].sel += (id * 2) + 1;
6770 alu.src[0].chan = 1;
6771 }
6772 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6773 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
6774 alu.last = 1;
6775 r = r600_bytecode_add_alu(ctx->bc, &alu);
6776 if (r)
6777 return r;
6778 return 0;
6779 }
6780
6781 static int tgsi_tex(struct r600_shader_ctx *ctx)
6782 {
6783 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6784 struct r600_bytecode_tex tex;
6785 struct r600_bytecode_alu alu;
6786 unsigned src_gpr;
6787 int r, i, j;
6788 int opcode;
6789 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
6790 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6791 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
6792 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
6793
6794 bool txf_add_offsets = inst->Texture.NumOffsets &&
6795 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6796 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
6797
6798 /* Texture fetch instructions can only use gprs as source.
6799 * Also they cannot negate the source or take the absolute value */
6800 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
6801 inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
6802 tgsi_tex_src_requires_loading(ctx, 0)) ||
6803 read_compressed_msaa || txf_add_offsets;
6804
6805 boolean src_loaded = FALSE;
6806 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
6807 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
6808 boolean has_txq_cube_array_z = false;
6809 unsigned sampler_index_mode;
6810
6811 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
6812 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6813 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
6814 if (inst->Dst[0].Register.WriteMask & 4) {
6815 ctx->shader->has_txq_cube_array_z_comp = true;
6816 has_txq_cube_array_z = true;
6817 }
6818
6819 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
6820 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
6821 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
6822 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
6823 sampler_src_reg = 2;
6824
6825 /* TGSI moves the sampler to src reg 3 for TXD */
6826 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
6827 sampler_src_reg = 3;
6828
6829 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6830
6831 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6832
6833 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
6834 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
6835 ctx->shader->uses_tex_buffers = true;
6836 return r600_do_buffer_txq(ctx);
6837 }
6838 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
6839 if (ctx->bc->chip_class < EVERGREEN)
6840 ctx->shader->uses_tex_buffers = true;
6841 return do_vtx_fetch_inst(ctx, src_requires_loading);
6842 }
6843 }
6844
6845 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
6846 int out_chan;
6847 /* Add perspective divide */
6848 if (ctx->bc->chip_class == CAYMAN) {
6849 out_chan = 2;
6850 for (i = 0; i < 3; i++) {
6851 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6852 alu.op = ALU_OP1_RECIP_IEEE;
6853 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6854
6855 alu.dst.sel = ctx->temp_reg;
6856 alu.dst.chan = i;
6857 if (i == 2)
6858 alu.last = 1;
6859 if (out_chan == i)
6860 alu.dst.write = 1;
6861 r = r600_bytecode_add_alu(ctx->bc, &alu);
6862 if (r)
6863 return r;
6864 }
6865
6866 } else {
6867 out_chan = 3;
6868 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6869 alu.op = ALU_OP1_RECIP_IEEE;
6870 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6871
6872 alu.dst.sel = ctx->temp_reg;
6873 alu.dst.chan = out_chan;
6874 alu.last = 1;
6875 alu.dst.write = 1;
6876 r = r600_bytecode_add_alu(ctx->bc, &alu);
6877 if (r)
6878 return r;
6879 }
6880
6881 for (i = 0; i < 3; i++) {
6882 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6883 alu.op = ALU_OP2_MUL;
6884 alu.src[0].sel = ctx->temp_reg;
6885 alu.src[0].chan = out_chan;
6886 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6887 alu.dst.sel = ctx->temp_reg;
6888 alu.dst.chan = i;
6889 alu.dst.write = 1;
6890 r = r600_bytecode_add_alu(ctx->bc, &alu);
6891 if (r)
6892 return r;
6893 }
6894 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6895 alu.op = ALU_OP1_MOV;
6896 alu.src[0].sel = V_SQ_ALU_SRC_1;
6897 alu.src[0].chan = 0;
6898 alu.dst.sel = ctx->temp_reg;
6899 alu.dst.chan = 3;
6900 alu.last = 1;
6901 alu.dst.write = 1;
6902 r = r600_bytecode_add_alu(ctx->bc, &alu);
6903 if (r)
6904 return r;
6905 src_loaded = TRUE;
6906 src_gpr = ctx->temp_reg;
6907 }
6908
6909
6910 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
6911 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6912 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6913 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
6914 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
6915 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
6916
6917 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
6918 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
6919
6920 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
6921 for (i = 0; i < 4; i++) {
6922 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6923 alu.op = ALU_OP2_CUBE;
6924 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6925 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
6926 alu.dst.sel = ctx->temp_reg;
6927 alu.dst.chan = i;
6928 if (i == 3)
6929 alu.last = 1;
6930 alu.dst.write = 1;
6931 r = r600_bytecode_add_alu(ctx->bc, &alu);
6932 if (r)
6933 return r;
6934 }
6935
6936 /* tmp1.z = RCP_e(|tmp1.z|) */
6937 if (ctx->bc->chip_class == CAYMAN) {
6938 for (i = 0; i < 3; i++) {
6939 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6940 alu.op = ALU_OP1_RECIP_IEEE;
6941 alu.src[0].sel = ctx->temp_reg;
6942 alu.src[0].chan = 2;
6943 alu.src[0].abs = 1;
6944 alu.dst.sel = ctx->temp_reg;
6945 alu.dst.chan = i;
6946 if (i == 2)
6947 alu.dst.write = 1;
6948 if (i == 2)
6949 alu.last = 1;
6950 r = r600_bytecode_add_alu(ctx->bc, &alu);
6951 if (r)
6952 return r;
6953 }
6954 } else {
6955 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6956 alu.op = ALU_OP1_RECIP_IEEE;
6957 alu.src[0].sel = ctx->temp_reg;
6958 alu.src[0].chan = 2;
6959 alu.src[0].abs = 1;
6960 alu.dst.sel = ctx->temp_reg;
6961 alu.dst.chan = 2;
6962 alu.dst.write = 1;
6963 alu.last = 1;
6964 r = r600_bytecode_add_alu(ctx->bc, &alu);
6965 if (r)
6966 return r;
6967 }
6968
6969 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
6970 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
6971 * muladd has no writemask, have to use another temp
6972 */
6973 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6974 alu.op = ALU_OP3_MULADD;
6975 alu.is_op3 = 1;
6976
6977 alu.src[0].sel = ctx->temp_reg;
6978 alu.src[0].chan = 0;
6979 alu.src[1].sel = ctx->temp_reg;
6980 alu.src[1].chan = 2;
6981
6982 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
6983 alu.src[2].chan = 0;
6984 alu.src[2].value = u_bitcast_f2u(1.5f);
6985
6986 alu.dst.sel = ctx->temp_reg;
6987 alu.dst.chan = 0;
6988 alu.dst.write = 1;
6989
6990 r = r600_bytecode_add_alu(ctx->bc, &alu);
6991 if (r)
6992 return r;
6993
6994 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6995 alu.op = ALU_OP3_MULADD;
6996 alu.is_op3 = 1;
6997
6998 alu.src[0].sel = ctx->temp_reg;
6999 alu.src[0].chan = 1;
7000 alu.src[1].sel = ctx->temp_reg;
7001 alu.src[1].chan = 2;
7002
7003 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7004 alu.src[2].chan = 0;
7005 alu.src[2].value = u_bitcast_f2u(1.5f);
7006
7007 alu.dst.sel = ctx->temp_reg;
7008 alu.dst.chan = 1;
7009 alu.dst.write = 1;
7010
7011 alu.last = 1;
7012 r = r600_bytecode_add_alu(ctx->bc, &alu);
7013 if (r)
7014 return r;
7015 /* write initial compare value into Z component
7016 - W src 0 for shadow cube
7017 - X src 1 for shadow cube array */
7018 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7019 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7020 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7021 alu.op = ALU_OP1_MOV;
7022 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
7023 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7024 else
7025 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7026 alu.dst.sel = ctx->temp_reg;
7027 alu.dst.chan = 2;
7028 alu.dst.write = 1;
7029 alu.last = 1;
7030 r = r600_bytecode_add_alu(ctx->bc, &alu);
7031 if (r)
7032 return r;
7033 }
7034
7035 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7036 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7037 if (ctx->bc->chip_class >= EVERGREEN) {
7038 int mytmp = r600_get_temp(ctx);
7039 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7040 alu.op = ALU_OP1_MOV;
7041 alu.src[0].sel = ctx->temp_reg;
7042 alu.src[0].chan = 3;
7043 alu.dst.sel = mytmp;
7044 alu.dst.chan = 0;
7045 alu.dst.write = 1;
7046 alu.last = 1;
7047 r = r600_bytecode_add_alu(ctx->bc, &alu);
7048 if (r)
7049 return r;
7050
7051 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7052 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7053 alu.op = ALU_OP3_MULADD;
7054 alu.is_op3 = 1;
7055 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7056 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7057 alu.src[1].chan = 0;
7058 alu.src[1].value = u_bitcast_f2u(8.0f);
7059 alu.src[2].sel = mytmp;
7060 alu.src[2].chan = 0;
7061 alu.dst.sel = ctx->temp_reg;
7062 alu.dst.chan = 3;
7063 alu.dst.write = 1;
7064 alu.last = 1;
7065 r = r600_bytecode_add_alu(ctx->bc, &alu);
7066 if (r)
7067 return r;
7068 } else if (ctx->bc->chip_class < EVERGREEN) {
7069 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7070 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7071 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7072 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7073 tex.src_gpr = r600_get_temp(ctx);
7074 tex.src_sel_x = 0;
7075 tex.src_sel_y = 0;
7076 tex.src_sel_z = 0;
7077 tex.src_sel_w = 0;
7078 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7079 tex.coord_type_x = 1;
7080 tex.coord_type_y = 1;
7081 tex.coord_type_z = 1;
7082 tex.coord_type_w = 1;
7083 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7084 alu.op = ALU_OP1_MOV;
7085 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7086 alu.dst.sel = tex.src_gpr;
7087 alu.dst.chan = 0;
7088 alu.last = 1;
7089 alu.dst.write = 1;
7090 r = r600_bytecode_add_alu(ctx->bc, &alu);
7091 if (r)
7092 return r;
7093
7094 r = r600_bytecode_add_tex(ctx->bc, &tex);
7095 if (r)
7096 return r;
7097 }
7098
7099 }
7100
7101 /* for cube forms of lod and bias we need to route things */
7102 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7103 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7104 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7105 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7106 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7107 alu.op = ALU_OP1_MOV;
7108 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7109 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7110 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7111 else
7112 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7113 alu.dst.sel = ctx->temp_reg;
7114 alu.dst.chan = 2;
7115 alu.last = 1;
7116 alu.dst.write = 1;
7117 r = r600_bytecode_add_alu(ctx->bc, &alu);
7118 if (r)
7119 return r;
7120 }
7121
7122 src_loaded = TRUE;
7123 src_gpr = ctx->temp_reg;
7124 }
7125
7126 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7127 int temp_h = 0, temp_v = 0;
7128 int start_val = 0;
7129
7130 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7131 if (src_loaded == TRUE)
7132 start_val = 1;
7133 else
7134 src_loaded = TRUE;
7135 for (i = start_val; i < 3; i++) {
7136 int treg = r600_get_temp(ctx);
7137
7138 if (i == 0)
7139 src_gpr = treg;
7140 else if (i == 1)
7141 temp_h = treg;
7142 else
7143 temp_v = treg;
7144
7145 for (j = 0; j < 4; j++) {
7146 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7147 alu.op = ALU_OP1_MOV;
7148 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7149 alu.dst.sel = treg;
7150 alu.dst.chan = j;
7151 if (j == 3)
7152 alu.last = 1;
7153 alu.dst.write = 1;
7154 r = r600_bytecode_add_alu(ctx->bc, &alu);
7155 if (r)
7156 return r;
7157 }
7158 }
7159 for (i = 1; i < 3; i++) {
7160 /* set gradients h/v */
7161 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7162 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7163 FETCH_OP_SET_GRADIENTS_V;
7164 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7165 tex.sampler_index_mode = sampler_index_mode;
7166 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7167 tex.resource_index_mode = sampler_index_mode;
7168
7169 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7170 tex.src_sel_x = 0;
7171 tex.src_sel_y = 1;
7172 tex.src_sel_z = 2;
7173 tex.src_sel_w = 3;
7174
7175 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7176 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7177 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7178 tex.coord_type_x = 1;
7179 tex.coord_type_y = 1;
7180 tex.coord_type_z = 1;
7181 tex.coord_type_w = 1;
7182 }
7183 r = r600_bytecode_add_tex(ctx->bc, &tex);
7184 if (r)
7185 return r;
7186 }
7187 }
7188
7189 if (src_requires_loading && !src_loaded) {
7190 for (i = 0; i < 4; i++) {
7191 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7192 alu.op = ALU_OP1_MOV;
7193 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7194 alu.dst.sel = ctx->temp_reg;
7195 alu.dst.chan = i;
7196 if (i == 3)
7197 alu.last = 1;
7198 alu.dst.write = 1;
7199 r = r600_bytecode_add_alu(ctx->bc, &alu);
7200 if (r)
7201 return r;
7202 }
7203 src_loaded = TRUE;
7204 src_gpr = ctx->temp_reg;
7205 }
7206
7207 /* get offset values */
7208 if (inst->Texture.NumOffsets) {
7209 assert(inst->Texture.NumOffsets == 1);
7210
7211 /* The texture offset feature doesn't work with the TXF instruction
7212 * and must be emulated by adding the offset to the texture coordinates. */
7213 if (txf_add_offsets) {
7214 const struct tgsi_texture_offset *off = inst->TexOffsets;
7215
7216 switch (inst->Texture.Texture) {
7217 case TGSI_TEXTURE_3D:
7218 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7219 alu.op = ALU_OP2_ADD_INT;
7220 alu.src[0].sel = src_gpr;
7221 alu.src[0].chan = 2;
7222 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7223 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7224 alu.dst.sel = src_gpr;
7225 alu.dst.chan = 2;
7226 alu.dst.write = 1;
7227 alu.last = 1;
7228 r = r600_bytecode_add_alu(ctx->bc, &alu);
7229 if (r)
7230 return r;
7231 /* fall through */
7232
7233 case TGSI_TEXTURE_2D:
7234 case TGSI_TEXTURE_SHADOW2D:
7235 case TGSI_TEXTURE_RECT:
7236 case TGSI_TEXTURE_SHADOWRECT:
7237 case TGSI_TEXTURE_2D_ARRAY:
7238 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7239 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7240 alu.op = ALU_OP2_ADD_INT;
7241 alu.src[0].sel = src_gpr;
7242 alu.src[0].chan = 1;
7243 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7244 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7245 alu.dst.sel = src_gpr;
7246 alu.dst.chan = 1;
7247 alu.dst.write = 1;
7248 alu.last = 1;
7249 r = r600_bytecode_add_alu(ctx->bc, &alu);
7250 if (r)
7251 return r;
7252 /* fall through */
7253
7254 case TGSI_TEXTURE_1D:
7255 case TGSI_TEXTURE_SHADOW1D:
7256 case TGSI_TEXTURE_1D_ARRAY:
7257 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7258 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7259 alu.op = ALU_OP2_ADD_INT;
7260 alu.src[0].sel = src_gpr;
7261 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7262 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
7263 alu.dst.sel = src_gpr;
7264 alu.dst.write = 1;
7265 alu.last = 1;
7266 r = r600_bytecode_add_alu(ctx->bc, &alu);
7267 if (r)
7268 return r;
7269 break;
7270 /* texture offsets do not apply to other texture targets */
7271 }
7272 } else {
7273 switch (inst->Texture.Texture) {
7274 case TGSI_TEXTURE_3D:
7275 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
7276 /* fallthrough */
7277 case TGSI_TEXTURE_2D:
7278 case TGSI_TEXTURE_SHADOW2D:
7279 case TGSI_TEXTURE_RECT:
7280 case TGSI_TEXTURE_SHADOWRECT:
7281 case TGSI_TEXTURE_2D_ARRAY:
7282 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7283 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
7284 /* fallthrough */
7285 case TGSI_TEXTURE_1D:
7286 case TGSI_TEXTURE_SHADOW1D:
7287 case TGSI_TEXTURE_1D_ARRAY:
7288 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7289 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
7290 }
7291 }
7292 }
7293
7294 /* Obtain the sample index for reading a compressed MSAA color texture.
7295 * To read the FMASK, we use the ldfptr instruction, which tells us
7296 * where the samples are stored.
7297 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7298 * which is the identity mapping. Each nibble says which physical sample
7299 * should be fetched to get that sample.
7300 *
7301 * Assume src.z contains the sample index. It should be modified like this:
7302 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7303 * Then fetch the texel with src.
7304 */
7305 if (read_compressed_msaa) {
7306 unsigned sample_chan = 3;
7307 unsigned temp = r600_get_temp(ctx);
7308 assert(src_loaded);
7309
7310 /* temp.w = ldfptr() */
7311 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7312 tex.op = FETCH_OP_LD;
7313 tex.inst_mod = 1; /* to indicate this is ldfptr */
7314 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7315 tex.sampler_index_mode = sampler_index_mode;
7316 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7317 tex.resource_index_mode = sampler_index_mode;
7318 tex.src_gpr = src_gpr;
7319 tex.dst_gpr = temp;
7320 tex.dst_sel_x = 7; /* mask out these components */
7321 tex.dst_sel_y = 7;
7322 tex.dst_sel_z = 7;
7323 tex.dst_sel_w = 0; /* store X */
7324 tex.src_sel_x = 0;
7325 tex.src_sel_y = 1;
7326 tex.src_sel_z = 2;
7327 tex.src_sel_w = 3;
7328 tex.offset_x = offset_x;
7329 tex.offset_y = offset_y;
7330 tex.offset_z = offset_z;
7331 r = r600_bytecode_add_tex(ctx->bc, &tex);
7332 if (r)
7333 return r;
7334
7335 /* temp.x = sample_index*4 */
7336 if (ctx->bc->chip_class == CAYMAN) {
7337 for (i = 0 ; i < 4; i++) {
7338 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7339 alu.op = ALU_OP2_MULLO_INT;
7340 alu.src[0].sel = src_gpr;
7341 alu.src[0].chan = sample_chan;
7342 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7343 alu.src[1].value = 4;
7344 alu.dst.sel = temp;
7345 alu.dst.chan = i;
7346 alu.dst.write = i == 0;
7347 if (i == 3)
7348 alu.last = 1;
7349 r = r600_bytecode_add_alu(ctx->bc, &alu);
7350 if (r)
7351 return r;
7352 }
7353 } else {
7354 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7355 alu.op = ALU_OP2_MULLO_INT;
7356 alu.src[0].sel = src_gpr;
7357 alu.src[0].chan = sample_chan;
7358 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7359 alu.src[1].value = 4;
7360 alu.dst.sel = temp;
7361 alu.dst.chan = 0;
7362 alu.dst.write = 1;
7363 alu.last = 1;
7364 r = r600_bytecode_add_alu(ctx->bc, &alu);
7365 if (r)
7366 return r;
7367 }
7368
7369 /* sample_index = temp.w >> temp.x */
7370 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7371 alu.op = ALU_OP2_LSHR_INT;
7372 alu.src[0].sel = temp;
7373 alu.src[0].chan = 3;
7374 alu.src[1].sel = temp;
7375 alu.src[1].chan = 0;
7376 alu.dst.sel = src_gpr;
7377 alu.dst.chan = sample_chan;
7378 alu.dst.write = 1;
7379 alu.last = 1;
7380 r = r600_bytecode_add_alu(ctx->bc, &alu);
7381 if (r)
7382 return r;
7383
7384 /* sample_index & 0xF */
7385 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7386 alu.op = ALU_OP2_AND_INT;
7387 alu.src[0].sel = src_gpr;
7388 alu.src[0].chan = sample_chan;
7389 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7390 alu.src[1].value = 0xF;
7391 alu.dst.sel = src_gpr;
7392 alu.dst.chan = sample_chan;
7393 alu.dst.write = 1;
7394 alu.last = 1;
7395 r = r600_bytecode_add_alu(ctx->bc, &alu);
7396 if (r)
7397 return r;
7398 #if 0
7399 /* visualize the FMASK */
7400 for (i = 0; i < 4; i++) {
7401 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7402 alu.op = ALU_OP1_INT_TO_FLT;
7403 alu.src[0].sel = src_gpr;
7404 alu.src[0].chan = sample_chan;
7405 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7406 alu.dst.chan = i;
7407 alu.dst.write = 1;
7408 alu.last = 1;
7409 r = r600_bytecode_add_alu(ctx->bc, &alu);
7410 if (r)
7411 return r;
7412 }
7413 return 0;
7414 #endif
7415 }
7416
7417 /* does this shader want a num layers from TXQ for a cube array? */
7418 if (has_txq_cube_array_z) {
7419 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7420
7421 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7422 alu.op = ALU_OP1_MOV;
7423
7424 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7425 if (ctx->bc->chip_class >= EVERGREEN) {
7426 /* channel 1 or 3 of each word */
7427 alu.src[0].sel += (id / 2);
7428 alu.src[0].chan = ((id % 2) * 2) + 1;
7429 } else {
7430 /* r600 we have them at channel 2 of the second dword */
7431 alu.src[0].sel += (id * 2) + 1;
7432 alu.src[0].chan = 2;
7433 }
7434 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7435 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
7436 alu.last = 1;
7437 r = r600_bytecode_add_alu(ctx->bc, &alu);
7438 if (r)
7439 return r;
7440 /* disable writemask from texture instruction */
7441 inst->Dst[0].Register.WriteMask &= ~4;
7442 }
7443
7444 opcode = ctx->inst_info->op;
7445 if (opcode == FETCH_OP_GATHER4 &&
7446 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
7447 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
7448 opcode = FETCH_OP_GATHER4_O;
7449
7450 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7451 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7452 encoded in the instruction are ignored. */
7453 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7454 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
7455 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7456 tex.sampler_index_mode = sampler_index_mode;
7457 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7458 tex.resource_index_mode = sampler_index_mode;
7459
7460 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
7461 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
7462 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
7463 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
7464 tex.src_sel_w = 4;
7465
7466 tex.dst_sel_x = 7;
7467 tex.dst_sel_y = 7;
7468 tex.dst_sel_z = 7;
7469 tex.dst_sel_w = 7;
7470
7471 r = r600_bytecode_add_tex(ctx->bc, &tex);
7472 if (r)
7473 return r;
7474 }
7475
7476 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7477 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7478 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7479 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7480 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
7481 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7482 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7483 switch (opcode) {
7484 case FETCH_OP_SAMPLE:
7485 opcode = FETCH_OP_SAMPLE_C;
7486 break;
7487 case FETCH_OP_SAMPLE_L:
7488 opcode = FETCH_OP_SAMPLE_C_L;
7489 break;
7490 case FETCH_OP_SAMPLE_LB:
7491 opcode = FETCH_OP_SAMPLE_C_LB;
7492 break;
7493 case FETCH_OP_SAMPLE_G:
7494 opcode = FETCH_OP_SAMPLE_C_G;
7495 break;
7496 /* Texture gather variants */
7497 case FETCH_OP_GATHER4:
7498 opcode = FETCH_OP_GATHER4_C;
7499 break;
7500 case FETCH_OP_GATHER4_O:
7501 opcode = FETCH_OP_GATHER4_C_O;
7502 break;
7503 }
7504 }
7505
7506 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7507 tex.op = opcode;
7508
7509 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7510 tex.sampler_index_mode = sampler_index_mode;
7511 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7512 tex.resource_index_mode = sampler_index_mode;
7513 tex.src_gpr = src_gpr;
7514 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7515
7516 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
7517 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
7518 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
7519 }
7520
7521 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7522 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
7523 tex.inst_mod = texture_component_select;
7524
7525 if (ctx->bc->chip_class == CAYMAN) {
7526 /* GATHER4 result order is different from TGSI TG4 */
7527 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
7528 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
7529 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
7530 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7531 } else {
7532 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7533 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7534 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7535 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7536 }
7537 }
7538 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
7539 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7540 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7541 tex.dst_sel_z = 7;
7542 tex.dst_sel_w = 7;
7543 }
7544 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7545 tex.dst_sel_x = 3;
7546 tex.dst_sel_y = 7;
7547 tex.dst_sel_z = 7;
7548 tex.dst_sel_w = 7;
7549 }
7550 else {
7551 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7552 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7553 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7554 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7555 }
7556
7557
7558 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ||
7559 inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7560 tex.src_sel_x = 4;
7561 tex.src_sel_y = 4;
7562 tex.src_sel_z = 4;
7563 tex.src_sel_w = 4;
7564 } else if (src_loaded) {
7565 tex.src_sel_x = 0;
7566 tex.src_sel_y = 1;
7567 tex.src_sel_z = 2;
7568 tex.src_sel_w = 3;
7569 } else {
7570 tex.src_sel_x = ctx->src[0].swizzle[0];
7571 tex.src_sel_y = ctx->src[0].swizzle[1];
7572 tex.src_sel_z = ctx->src[0].swizzle[2];
7573 tex.src_sel_w = ctx->src[0].swizzle[3];
7574 tex.src_rel = ctx->src[0].rel;
7575 }
7576
7577 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7578 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7579 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7580 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7581 tex.src_sel_x = 1;
7582 tex.src_sel_y = 0;
7583 tex.src_sel_z = 3;
7584 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
7585 }
7586
7587 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
7588 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
7589 tex.coord_type_x = 1;
7590 tex.coord_type_y = 1;
7591 }
7592 tex.coord_type_z = 1;
7593 tex.coord_type_w = 1;
7594
7595 tex.offset_x = offset_x;
7596 tex.offset_y = offset_y;
7597 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
7598 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7599 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
7600 tex.offset_z = 0;
7601 }
7602 else {
7603 tex.offset_z = offset_z;
7604 }
7605
7606 /* Put the depth for comparison in W.
7607 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7608 * Some instructions expect the depth in Z. */
7609 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7610 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7611 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7612 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
7613 opcode != FETCH_OP_SAMPLE_C_L &&
7614 opcode != FETCH_OP_SAMPLE_C_LB) {
7615 tex.src_sel_w = tex.src_sel_z;
7616 }
7617
7618 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
7619 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
7620 if (opcode == FETCH_OP_SAMPLE_C_L ||
7621 opcode == FETCH_OP_SAMPLE_C_LB) {
7622 /* the array index is read from Y */
7623 tex.coord_type_y = 0;
7624 } else {
7625 /* the array index is read from Z */
7626 tex.coord_type_z = 0;
7627 tex.src_sel_z = tex.src_sel_y;
7628 }
7629 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7630 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7631 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7632 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7633 (ctx->bc->chip_class >= EVERGREEN)))
7634 /* the array index is read from Z */
7635 tex.coord_type_z = 0;
7636
7637 /* mask unused source components */
7638 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
7639 switch (inst->Texture.Texture) {
7640 case TGSI_TEXTURE_2D:
7641 case TGSI_TEXTURE_RECT:
7642 tex.src_sel_z = 7;
7643 tex.src_sel_w = 7;
7644 break;
7645 case TGSI_TEXTURE_1D_ARRAY:
7646 tex.src_sel_y = 7;
7647 tex.src_sel_w = 7;
7648 break;
7649 case TGSI_TEXTURE_1D:
7650 tex.src_sel_y = 7;
7651 tex.src_sel_z = 7;
7652 tex.src_sel_w = 7;
7653 break;
7654 }
7655 }
7656
7657 r = r600_bytecode_add_tex(ctx->bc, &tex);
7658 if (r)
7659 return r;
7660
7661 /* add shadow ambient support - gallium doesn't do it yet */
7662 return 0;
7663 }
7664
7665 static int tgsi_lrp(struct r600_shader_ctx *ctx)
7666 {
7667 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7668 struct r600_bytecode_alu alu;
7669 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7670 unsigned i, temp_regs[2];
7671 int r;
7672
7673 /* optimize if it's just an equal balance */
7674 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
7675 for (i = 0; i < lasti + 1; i++) {
7676 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7677 continue;
7678
7679 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7680 alu.op = ALU_OP2_ADD;
7681 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
7682 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7683 alu.omod = 3;
7684 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7685 alu.dst.chan = i;
7686 if (i == lasti) {
7687 alu.last = 1;
7688 }
7689 r = r600_bytecode_add_alu(ctx->bc, &alu);
7690 if (r)
7691 return r;
7692 }
7693 return 0;
7694 }
7695
7696 /* 1 - src0 */
7697 for (i = 0; i < lasti + 1; i++) {
7698 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7699 continue;
7700
7701 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7702 alu.op = ALU_OP2_ADD;
7703 alu.src[0].sel = V_SQ_ALU_SRC_1;
7704 alu.src[0].chan = 0;
7705 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
7706 r600_bytecode_src_toggle_neg(&alu.src[1]);
7707 alu.dst.sel = ctx->temp_reg;
7708 alu.dst.chan = i;
7709 if (i == lasti) {
7710 alu.last = 1;
7711 }
7712 alu.dst.write = 1;
7713 r = r600_bytecode_add_alu(ctx->bc, &alu);
7714 if (r)
7715 return r;
7716 }
7717
7718 /* (1 - src0) * src2 */
7719 for (i = 0; i < lasti + 1; i++) {
7720 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7721 continue;
7722
7723 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7724 alu.op = ALU_OP2_MUL;
7725 alu.src[0].sel = ctx->temp_reg;
7726 alu.src[0].chan = i;
7727 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7728 alu.dst.sel = ctx->temp_reg;
7729 alu.dst.chan = i;
7730 if (i == lasti) {
7731 alu.last = 1;
7732 }
7733 alu.dst.write = 1;
7734 r = r600_bytecode_add_alu(ctx->bc, &alu);
7735 if (r)
7736 return r;
7737 }
7738
7739 /* src0 * src1 + (1 - src0) * src2 */
7740 if (ctx->src[0].abs)
7741 temp_regs[0] = r600_get_temp(ctx);
7742 else
7743 temp_regs[0] = 0;
7744 if (ctx->src[1].abs)
7745 temp_regs[1] = r600_get_temp(ctx);
7746 else
7747 temp_regs[1] = 0;
7748
7749 for (i = 0; i < lasti + 1; i++) {
7750 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7751 continue;
7752
7753 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7754 alu.op = ALU_OP3_MULADD;
7755 alu.is_op3 = 1;
7756 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7757 if (r)
7758 return r;
7759 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
7760 if (r)
7761 return r;
7762 alu.src[2].sel = ctx->temp_reg;
7763 alu.src[2].chan = i;
7764
7765 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7766 alu.dst.chan = i;
7767 if (i == lasti) {
7768 alu.last = 1;
7769 }
7770 r = r600_bytecode_add_alu(ctx->bc, &alu);
7771 if (r)
7772 return r;
7773 }
7774 return 0;
7775 }
7776
7777 static int tgsi_cmp(struct r600_shader_ctx *ctx)
7778 {
7779 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7780 struct r600_bytecode_alu alu;
7781 int i, r, j;
7782 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7783 int temp_regs[3];
7784 unsigned op;
7785
7786 if (ctx->src[0].abs && ctx->src[0].neg) {
7787 op = ALU_OP3_CNDE;
7788 ctx->src[0].abs = 0;
7789 ctx->src[0].neg = 0;
7790 } else {
7791 op = ALU_OP3_CNDGE;
7792 }
7793
7794 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7795 temp_regs[j] = 0;
7796 if (ctx->src[j].abs)
7797 temp_regs[j] = r600_get_temp(ctx);
7798 }
7799
7800 for (i = 0; i < lasti + 1; i++) {
7801 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7802 continue;
7803
7804 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7805 alu.op = op;
7806 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7807 if (r)
7808 return r;
7809 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
7810 if (r)
7811 return r;
7812 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
7813 if (r)
7814 return r;
7815 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7816 alu.dst.chan = i;
7817 alu.dst.write = 1;
7818 alu.is_op3 = 1;
7819 if (i == lasti)
7820 alu.last = 1;
7821 r = r600_bytecode_add_alu(ctx->bc, &alu);
7822 if (r)
7823 return r;
7824 }
7825 return 0;
7826 }
7827
7828 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
7829 {
7830 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7831 struct r600_bytecode_alu alu;
7832 int i, r;
7833 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7834
7835 for (i = 0; i < lasti + 1; i++) {
7836 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7837 continue;
7838
7839 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7840 alu.op = ALU_OP3_CNDE_INT;
7841 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7842 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7843 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
7844 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7845 alu.dst.chan = i;
7846 alu.dst.write = 1;
7847 alu.is_op3 = 1;
7848 if (i == lasti)
7849 alu.last = 1;
7850 r = r600_bytecode_add_alu(ctx->bc, &alu);
7851 if (r)
7852 return r;
7853 }
7854 return 0;
7855 }
7856
7857 static int tgsi_xpd(struct r600_shader_ctx *ctx)
7858 {
7859 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7860 static const unsigned int src0_swizzle[] = {2, 0, 1};
7861 static const unsigned int src1_swizzle[] = {1, 2, 0};
7862 struct r600_bytecode_alu alu;
7863 uint32_t use_temp = 0;
7864 int i, r;
7865
7866 if (inst->Dst[0].Register.WriteMask != 0xf)
7867 use_temp = 1;
7868
7869 for (i = 0; i < 4; i++) {
7870 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7871 alu.op = ALU_OP2_MUL;
7872 if (i < 3) {
7873 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
7874 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
7875 } else {
7876 alu.src[0].sel = V_SQ_ALU_SRC_0;
7877 alu.src[0].chan = i;
7878 alu.src[1].sel = V_SQ_ALU_SRC_0;
7879 alu.src[1].chan = i;
7880 }
7881
7882 alu.dst.sel = ctx->temp_reg;
7883 alu.dst.chan = i;
7884 alu.dst.write = 1;
7885
7886 if (i == 3)
7887 alu.last = 1;
7888 r = r600_bytecode_add_alu(ctx->bc, &alu);
7889 if (r)
7890 return r;
7891 }
7892
7893 for (i = 0; i < 4; i++) {
7894 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7895 alu.op = ALU_OP3_MULADD;
7896
7897 if (i < 3) {
7898 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
7899 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
7900 } else {
7901 alu.src[0].sel = V_SQ_ALU_SRC_0;
7902 alu.src[0].chan = i;
7903 alu.src[1].sel = V_SQ_ALU_SRC_0;
7904 alu.src[1].chan = i;
7905 }
7906
7907 alu.src[2].sel = ctx->temp_reg;
7908 alu.src[2].neg = 1;
7909 alu.src[2].chan = i;
7910
7911 if (use_temp)
7912 alu.dst.sel = ctx->temp_reg;
7913 else
7914 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7915 alu.dst.chan = i;
7916 alu.dst.write = 1;
7917 alu.is_op3 = 1;
7918 if (i == 3)
7919 alu.last = 1;
7920 r = r600_bytecode_add_alu(ctx->bc, &alu);
7921 if (r)
7922 return r;
7923 }
7924 if (use_temp)
7925 return tgsi_helper_copy(ctx, inst);
7926 return 0;
7927 }
7928
7929 static int tgsi_exp(struct r600_shader_ctx *ctx)
7930 {
7931 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7932 struct r600_bytecode_alu alu;
7933 int r;
7934 unsigned i;
7935
7936 /* result.x = 2^floor(src); */
7937 if (inst->Dst[0].Register.WriteMask & 1) {
7938 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7939
7940 alu.op = ALU_OP1_FLOOR;
7941 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7942
7943 alu.dst.sel = ctx->temp_reg;
7944 alu.dst.chan = 0;
7945 alu.dst.write = 1;
7946 alu.last = 1;
7947 r = r600_bytecode_add_alu(ctx->bc, &alu);
7948 if (r)
7949 return r;
7950
7951 if (ctx->bc->chip_class == CAYMAN) {
7952 for (i = 0; i < 3; i++) {
7953 alu.op = ALU_OP1_EXP_IEEE;
7954 alu.src[0].sel = ctx->temp_reg;
7955 alu.src[0].chan = 0;
7956
7957 alu.dst.sel = ctx->temp_reg;
7958 alu.dst.chan = i;
7959 alu.dst.write = i == 0;
7960 alu.last = i == 2;
7961 r = r600_bytecode_add_alu(ctx->bc, &alu);
7962 if (r)
7963 return r;
7964 }
7965 } else {
7966 alu.op = ALU_OP1_EXP_IEEE;
7967 alu.src[0].sel = ctx->temp_reg;
7968 alu.src[0].chan = 0;
7969
7970 alu.dst.sel = ctx->temp_reg;
7971 alu.dst.chan = 0;
7972 alu.dst.write = 1;
7973 alu.last = 1;
7974 r = r600_bytecode_add_alu(ctx->bc, &alu);
7975 if (r)
7976 return r;
7977 }
7978 }
7979
7980 /* result.y = tmp - floor(tmp); */
7981 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
7982 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7983
7984 alu.op = ALU_OP1_FRACT;
7985 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7986
7987 alu.dst.sel = ctx->temp_reg;
7988 #if 0
7989 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7990 if (r)
7991 return r;
7992 #endif
7993 alu.dst.write = 1;
7994 alu.dst.chan = 1;
7995
7996 alu.last = 1;
7997
7998 r = r600_bytecode_add_alu(ctx->bc, &alu);
7999 if (r)
8000 return r;
8001 }
8002
8003 /* result.z = RoughApprox2ToX(tmp);*/
8004 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
8005 if (ctx->bc->chip_class == CAYMAN) {
8006 for (i = 0; i < 3; i++) {
8007 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8008 alu.op = ALU_OP1_EXP_IEEE;
8009 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8010
8011 alu.dst.sel = ctx->temp_reg;
8012 alu.dst.chan = i;
8013 if (i == 2) {
8014 alu.dst.write = 1;
8015 alu.last = 1;
8016 }
8017
8018 r = r600_bytecode_add_alu(ctx->bc, &alu);
8019 if (r)
8020 return r;
8021 }
8022 } else {
8023 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8024 alu.op = ALU_OP1_EXP_IEEE;
8025 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8026
8027 alu.dst.sel = ctx->temp_reg;
8028 alu.dst.write = 1;
8029 alu.dst.chan = 2;
8030
8031 alu.last = 1;
8032
8033 r = r600_bytecode_add_alu(ctx->bc, &alu);
8034 if (r)
8035 return r;
8036 }
8037 }
8038
8039 /* result.w = 1.0;*/
8040 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
8041 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8042
8043 alu.op = ALU_OP1_MOV;
8044 alu.src[0].sel = V_SQ_ALU_SRC_1;
8045 alu.src[0].chan = 0;
8046
8047 alu.dst.sel = ctx->temp_reg;
8048 alu.dst.chan = 3;
8049 alu.dst.write = 1;
8050 alu.last = 1;
8051 r = r600_bytecode_add_alu(ctx->bc, &alu);
8052 if (r)
8053 return r;
8054 }
8055 return tgsi_helper_copy(ctx, inst);
8056 }
8057
8058 static int tgsi_log(struct r600_shader_ctx *ctx)
8059 {
8060 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8061 struct r600_bytecode_alu alu;
8062 int r;
8063 unsigned i;
8064
8065 /* result.x = floor(log2(|src|)); */
8066 if (inst->Dst[0].Register.WriteMask & 1) {
8067 if (ctx->bc->chip_class == CAYMAN) {
8068 for (i = 0; i < 3; i++) {
8069 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8070
8071 alu.op = ALU_OP1_LOG_IEEE;
8072 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8073 r600_bytecode_src_set_abs(&alu.src[0]);
8074
8075 alu.dst.sel = ctx->temp_reg;
8076 alu.dst.chan = i;
8077 if (i == 0)
8078 alu.dst.write = 1;
8079 if (i == 2)
8080 alu.last = 1;
8081 r = r600_bytecode_add_alu(ctx->bc, &alu);
8082 if (r)
8083 return r;
8084 }
8085
8086 } else {
8087 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8088
8089 alu.op = ALU_OP1_LOG_IEEE;
8090 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8091 r600_bytecode_src_set_abs(&alu.src[0]);
8092
8093 alu.dst.sel = ctx->temp_reg;
8094 alu.dst.chan = 0;
8095 alu.dst.write = 1;
8096 alu.last = 1;
8097 r = r600_bytecode_add_alu(ctx->bc, &alu);
8098 if (r)
8099 return r;
8100 }
8101
8102 alu.op = ALU_OP1_FLOOR;
8103 alu.src[0].sel = ctx->temp_reg;
8104 alu.src[0].chan = 0;
8105
8106 alu.dst.sel = ctx->temp_reg;
8107 alu.dst.chan = 0;
8108 alu.dst.write = 1;
8109 alu.last = 1;
8110
8111 r = r600_bytecode_add_alu(ctx->bc, &alu);
8112 if (r)
8113 return r;
8114 }
8115
8116 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
8117 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8118
8119 if (ctx->bc->chip_class == CAYMAN) {
8120 for (i = 0; i < 3; i++) {
8121 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8122
8123 alu.op = ALU_OP1_LOG_IEEE;
8124 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8125 r600_bytecode_src_set_abs(&alu.src[0]);
8126
8127 alu.dst.sel = ctx->temp_reg;
8128 alu.dst.chan = i;
8129 if (i == 1)
8130 alu.dst.write = 1;
8131 if (i == 2)
8132 alu.last = 1;
8133
8134 r = r600_bytecode_add_alu(ctx->bc, &alu);
8135 if (r)
8136 return r;
8137 }
8138 } else {
8139 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8140
8141 alu.op = ALU_OP1_LOG_IEEE;
8142 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8143 r600_bytecode_src_set_abs(&alu.src[0]);
8144
8145 alu.dst.sel = ctx->temp_reg;
8146 alu.dst.chan = 1;
8147 alu.dst.write = 1;
8148 alu.last = 1;
8149
8150 r = r600_bytecode_add_alu(ctx->bc, &alu);
8151 if (r)
8152 return r;
8153 }
8154
8155 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8156
8157 alu.op = ALU_OP1_FLOOR;
8158 alu.src[0].sel = ctx->temp_reg;
8159 alu.src[0].chan = 1;
8160
8161 alu.dst.sel = ctx->temp_reg;
8162 alu.dst.chan = 1;
8163 alu.dst.write = 1;
8164 alu.last = 1;
8165
8166 r = r600_bytecode_add_alu(ctx->bc, &alu);
8167 if (r)
8168 return r;
8169
8170 if (ctx->bc->chip_class == CAYMAN) {
8171 for (i = 0; i < 3; i++) {
8172 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8173 alu.op = ALU_OP1_EXP_IEEE;
8174 alu.src[0].sel = ctx->temp_reg;
8175 alu.src[0].chan = 1;
8176
8177 alu.dst.sel = ctx->temp_reg;
8178 alu.dst.chan = i;
8179 if (i == 1)
8180 alu.dst.write = 1;
8181 if (i == 2)
8182 alu.last = 1;
8183
8184 r = r600_bytecode_add_alu(ctx->bc, &alu);
8185 if (r)
8186 return r;
8187 }
8188 } else {
8189 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8190 alu.op = ALU_OP1_EXP_IEEE;
8191 alu.src[0].sel = ctx->temp_reg;
8192 alu.src[0].chan = 1;
8193
8194 alu.dst.sel = ctx->temp_reg;
8195 alu.dst.chan = 1;
8196 alu.dst.write = 1;
8197 alu.last = 1;
8198
8199 r = r600_bytecode_add_alu(ctx->bc, &alu);
8200 if (r)
8201 return r;
8202 }
8203
8204 if (ctx->bc->chip_class == CAYMAN) {
8205 for (i = 0; i < 3; i++) {
8206 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8207 alu.op = ALU_OP1_RECIP_IEEE;
8208 alu.src[0].sel = ctx->temp_reg;
8209 alu.src[0].chan = 1;
8210
8211 alu.dst.sel = ctx->temp_reg;
8212 alu.dst.chan = i;
8213 if (i == 1)
8214 alu.dst.write = 1;
8215 if (i == 2)
8216 alu.last = 1;
8217
8218 r = r600_bytecode_add_alu(ctx->bc, &alu);
8219 if (r)
8220 return r;
8221 }
8222 } else {
8223 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8224 alu.op = ALU_OP1_RECIP_IEEE;
8225 alu.src[0].sel = ctx->temp_reg;
8226 alu.src[0].chan = 1;
8227
8228 alu.dst.sel = ctx->temp_reg;
8229 alu.dst.chan = 1;
8230 alu.dst.write = 1;
8231 alu.last = 1;
8232
8233 r = r600_bytecode_add_alu(ctx->bc, &alu);
8234 if (r)
8235 return r;
8236 }
8237
8238 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8239
8240 alu.op = ALU_OP2_MUL;
8241
8242 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8243 r600_bytecode_src_set_abs(&alu.src[0]);
8244
8245 alu.src[1].sel = ctx->temp_reg;
8246 alu.src[1].chan = 1;
8247
8248 alu.dst.sel = ctx->temp_reg;
8249 alu.dst.chan = 1;
8250 alu.dst.write = 1;
8251 alu.last = 1;
8252
8253 r = r600_bytecode_add_alu(ctx->bc, &alu);
8254 if (r)
8255 return r;
8256 }
8257
8258 /* result.z = log2(|src|);*/
8259 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
8260 if (ctx->bc->chip_class == CAYMAN) {
8261 for (i = 0; i < 3; i++) {
8262 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8263
8264 alu.op = ALU_OP1_LOG_IEEE;
8265 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8266 r600_bytecode_src_set_abs(&alu.src[0]);
8267
8268 alu.dst.sel = ctx->temp_reg;
8269 if (i == 2)
8270 alu.dst.write = 1;
8271 alu.dst.chan = i;
8272 if (i == 2)
8273 alu.last = 1;
8274
8275 r = r600_bytecode_add_alu(ctx->bc, &alu);
8276 if (r)
8277 return r;
8278 }
8279 } else {
8280 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8281
8282 alu.op = ALU_OP1_LOG_IEEE;
8283 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8284 r600_bytecode_src_set_abs(&alu.src[0]);
8285
8286 alu.dst.sel = ctx->temp_reg;
8287 alu.dst.write = 1;
8288 alu.dst.chan = 2;
8289 alu.last = 1;
8290
8291 r = r600_bytecode_add_alu(ctx->bc, &alu);
8292 if (r)
8293 return r;
8294 }
8295 }
8296
8297 /* result.w = 1.0; */
8298 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
8299 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8300
8301 alu.op = ALU_OP1_MOV;
8302 alu.src[0].sel = V_SQ_ALU_SRC_1;
8303 alu.src[0].chan = 0;
8304
8305 alu.dst.sel = ctx->temp_reg;
8306 alu.dst.chan = 3;
8307 alu.dst.write = 1;
8308 alu.last = 1;
8309
8310 r = r600_bytecode_add_alu(ctx->bc, &alu);
8311 if (r)
8312 return r;
8313 }
8314
8315 return tgsi_helper_copy(ctx, inst);
8316 }
8317
8318 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
8319 {
8320 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8321 struct r600_bytecode_alu alu;
8322 int r;
8323 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8324 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
8325
8326 assert(inst->Dst[0].Register.Index < 3);
8327 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8328
8329 switch (inst->Instruction.Opcode) {
8330 case TGSI_OPCODE_ARL:
8331 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
8332 break;
8333 case TGSI_OPCODE_ARR:
8334 alu.op = ALU_OP1_FLT_TO_INT;
8335 break;
8336 case TGSI_OPCODE_UARL:
8337 alu.op = ALU_OP1_MOV;
8338 break;
8339 default:
8340 assert(0);
8341 return -1;
8342 }
8343
8344 for (i = 0; i <= lasti; ++i) {
8345 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8346 continue;
8347 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8348 alu.last = i == lasti;
8349 alu.dst.sel = reg;
8350 alu.dst.chan = i;
8351 alu.dst.write = 1;
8352 r = r600_bytecode_add_alu(ctx->bc, &alu);
8353 if (r)
8354 return r;
8355 }
8356
8357 if (inst->Dst[0].Register.Index > 0)
8358 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
8359 else
8360 ctx->bc->ar_loaded = 0;
8361
8362 return 0;
8363 }
8364 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
8365 {
8366 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8367 struct r600_bytecode_alu alu;
8368 int r;
8369 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8370
8371 switch (inst->Instruction.Opcode) {
8372 case TGSI_OPCODE_ARL:
8373 memset(&alu, 0, sizeof(alu));
8374 alu.op = ALU_OP1_FLOOR;
8375 alu.dst.sel = ctx->bc->ar_reg;
8376 alu.dst.write = 1;
8377 for (i = 0; i <= lasti; ++i) {
8378 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8379 alu.dst.chan = i;
8380 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8381 alu.last = i == lasti;
8382 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8383 return r;
8384 }
8385 }
8386
8387 memset(&alu, 0, sizeof(alu));
8388 alu.op = ALU_OP1_FLT_TO_INT;
8389 alu.src[0].sel = ctx->bc->ar_reg;
8390 alu.dst.sel = ctx->bc->ar_reg;
8391 alu.dst.write = 1;
8392 /* FLT_TO_INT is trans-only on r600/r700 */
8393 alu.last = TRUE;
8394 for (i = 0; i <= lasti; ++i) {
8395 alu.dst.chan = i;
8396 alu.src[0].chan = i;
8397 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8398 return r;
8399 }
8400 break;
8401 case TGSI_OPCODE_ARR:
8402 memset(&alu, 0, sizeof(alu));
8403 alu.op = ALU_OP1_FLT_TO_INT;
8404 alu.dst.sel = ctx->bc->ar_reg;
8405 alu.dst.write = 1;
8406 /* FLT_TO_INT is trans-only on r600/r700 */
8407 alu.last = TRUE;
8408 for (i = 0; i <= lasti; ++i) {
8409 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8410 alu.dst.chan = i;
8411 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8412 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8413 return r;
8414 }
8415 }
8416 break;
8417 case TGSI_OPCODE_UARL:
8418 memset(&alu, 0, sizeof(alu));
8419 alu.op = ALU_OP1_MOV;
8420 alu.dst.sel = ctx->bc->ar_reg;
8421 alu.dst.write = 1;
8422 for (i = 0; i <= lasti; ++i) {
8423 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8424 alu.dst.chan = i;
8425 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8426 alu.last = i == lasti;
8427 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8428 return r;
8429 }
8430 }
8431 break;
8432 default:
8433 assert(0);
8434 return -1;
8435 }
8436
8437 ctx->bc->ar_loaded = 0;
8438 return 0;
8439 }
8440
8441 static int tgsi_opdst(struct r600_shader_ctx *ctx)
8442 {
8443 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8444 struct r600_bytecode_alu alu;
8445 int i, r = 0;
8446
8447 for (i = 0; i < 4; i++) {
8448 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8449
8450 alu.op = ALU_OP2_MUL;
8451 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8452
8453 if (i == 0 || i == 3) {
8454 alu.src[0].sel = V_SQ_ALU_SRC_1;
8455 } else {
8456 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8457 }
8458
8459 if (i == 0 || i == 2) {
8460 alu.src[1].sel = V_SQ_ALU_SRC_1;
8461 } else {
8462 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8463 }
8464 if (i == 3)
8465 alu.last = 1;
8466 r = r600_bytecode_add_alu(ctx->bc, &alu);
8467 if (r)
8468 return r;
8469 }
8470 return 0;
8471 }
8472
8473 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
8474 {
8475 struct r600_bytecode_alu alu;
8476 int r;
8477
8478 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8479 alu.op = opcode;
8480 alu.execute_mask = 1;
8481 alu.update_pred = 1;
8482
8483 alu.dst.sel = ctx->temp_reg;
8484 alu.dst.write = 1;
8485 alu.dst.chan = 0;
8486
8487 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8488 alu.src[1].sel = V_SQ_ALU_SRC_0;
8489 alu.src[1].chan = 0;
8490
8491 alu.last = 1;
8492
8493 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
8494 if (r)
8495 return r;
8496 return 0;
8497 }
8498
8499 static int pops(struct r600_shader_ctx *ctx, int pops)
8500 {
8501 unsigned force_pop = ctx->bc->force_add_cf;
8502
8503 if (!force_pop) {
8504 int alu_pop = 3;
8505 if (ctx->bc->cf_last) {
8506 if (ctx->bc->cf_last->op == CF_OP_ALU)
8507 alu_pop = 0;
8508 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
8509 alu_pop = 1;
8510 }
8511 alu_pop += pops;
8512 if (alu_pop == 1) {
8513 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
8514 ctx->bc->force_add_cf = 1;
8515 } else if (alu_pop == 2) {
8516 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
8517 ctx->bc->force_add_cf = 1;
8518 } else {
8519 force_pop = 1;
8520 }
8521 }
8522
8523 if (force_pop) {
8524 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
8525 ctx->bc->cf_last->pop_count = pops;
8526 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8527 }
8528
8529 return 0;
8530 }
8531
8532 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
8533 unsigned reason)
8534 {
8535 struct r600_stack_info *stack = &ctx->bc->stack;
8536 unsigned elements, entries;
8537
8538 unsigned entry_size = stack->entry_size;
8539
8540 elements = (stack->loop + stack->push_wqm ) * entry_size;
8541 elements += stack->push;
8542
8543 switch (ctx->bc->chip_class) {
8544 case R600:
8545 case R700:
8546 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
8547 * the stack must be reserved to hold the current active/continue
8548 * masks */
8549 if (reason == FC_PUSH_VPM) {
8550 elements += 2;
8551 }
8552 break;
8553
8554 case CAYMAN:
8555 /* r9xx: any stack operation on empty stack consumes 2 additional
8556 * elements */
8557 elements += 2;
8558
8559 /* fallthrough */
8560 /* FIXME: do the two elements added above cover the cases for the
8561 * r8xx+ below? */
8562
8563 case EVERGREEN:
8564 /* r8xx+: 2 extra elements are not always required, but one extra
8565 * element must be added for each of the following cases:
8566 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
8567 * stack usage.
8568 * (Currently we don't use ALU_ELSE_AFTER.)
8569 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
8570 * PUSH instruction executed.
8571 *
8572 * NOTE: it seems we also need to reserve additional element in some
8573 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
8574 * then STACK_SIZE should be 2 instead of 1 */
8575 if (reason == FC_PUSH_VPM) {
8576 elements += 1;
8577 }
8578 break;
8579
8580 default:
8581 assert(0);
8582 break;
8583 }
8584
8585 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
8586 * for all chips, so we use 4 in the final formula, not the real entry_size
8587 * for the chip */
8588 entry_size = 4;
8589
8590 entries = (elements + (entry_size - 1)) / entry_size;
8591
8592 if (entries > stack->max_entries)
8593 stack->max_entries = entries;
8594 }
8595
8596 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
8597 {
8598 switch(reason) {
8599 case FC_PUSH_VPM:
8600 --ctx->bc->stack.push;
8601 assert(ctx->bc->stack.push >= 0);
8602 break;
8603 case FC_PUSH_WQM:
8604 --ctx->bc->stack.push_wqm;
8605 assert(ctx->bc->stack.push_wqm >= 0);
8606 break;
8607 case FC_LOOP:
8608 --ctx->bc->stack.loop;
8609 assert(ctx->bc->stack.loop >= 0);
8610 break;
8611 default:
8612 assert(0);
8613 break;
8614 }
8615 }
8616
8617 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
8618 {
8619 switch (reason) {
8620 case FC_PUSH_VPM:
8621 ++ctx->bc->stack.push;
8622 break;
8623 case FC_PUSH_WQM:
8624 ++ctx->bc->stack.push_wqm;
8625 case FC_LOOP:
8626 ++ctx->bc->stack.loop;
8627 break;
8628 default:
8629 assert(0);
8630 }
8631
8632 callstack_update_max_depth(ctx, reason);
8633 }
8634
8635 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
8636 {
8637 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
8638
8639 sp->mid = realloc((void *)sp->mid,
8640 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
8641 sp->mid[sp->num_mid] = ctx->bc->cf_last;
8642 sp->num_mid++;
8643 }
8644
8645 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
8646 {
8647 assert(ctx->bc->fc_sp < ARRAY_SIZE(ctx->bc->fc_stack));
8648 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
8649 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
8650 ctx->bc->fc_sp++;
8651 }
8652
8653 static void fc_poplevel(struct r600_shader_ctx *ctx)
8654 {
8655 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp - 1];
8656 free(sp->mid);
8657 sp->mid = NULL;
8658 sp->num_mid = 0;
8659 sp->start = NULL;
8660 sp->type = 0;
8661 ctx->bc->fc_sp--;
8662 }
8663
8664 #if 0
8665 static int emit_return(struct r600_shader_ctx *ctx)
8666 {
8667 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
8668 return 0;
8669 }
8670
8671 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
8672 {
8673
8674 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
8675 ctx->bc->cf_last->pop_count = pops;
8676 /* XXX work out offset */
8677 return 0;
8678 }
8679
8680 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
8681 {
8682 return 0;
8683 }
8684
8685 static void emit_testflag(struct r600_shader_ctx *ctx)
8686 {
8687
8688 }
8689
8690 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
8691 {
8692 emit_testflag(ctx);
8693 emit_jump_to_offset(ctx, 1, 4);
8694 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
8695 pops(ctx, ifidx + 1);
8696 emit_return(ctx);
8697 }
8698
8699 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
8700 {
8701 emit_testflag(ctx);
8702
8703 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8704 ctx->bc->cf_last->pop_count = 1;
8705
8706 fc_set_mid(ctx, fc_sp);
8707
8708 pops(ctx, 1);
8709 }
8710 #endif
8711
8712 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
8713 {
8714 int alu_type = CF_OP_ALU_PUSH_BEFORE;
8715
8716 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
8717 * LOOP_STARTxxx for nested loops may put the branch stack into a state
8718 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
8719 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
8720 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
8721 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
8722 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8723 alu_type = CF_OP_ALU;
8724 }
8725
8726 emit_logic_pred(ctx, opcode, alu_type);
8727
8728 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
8729
8730 fc_pushlevel(ctx, FC_IF);
8731
8732 callstack_push(ctx, FC_PUSH_VPM);
8733 return 0;
8734 }
8735
8736 static int tgsi_if(struct r600_shader_ctx *ctx)
8737 {
8738 return emit_if(ctx, ALU_OP2_PRED_SETNE);
8739 }
8740
8741 static int tgsi_uif(struct r600_shader_ctx *ctx)
8742 {
8743 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
8744 }
8745
8746 static int tgsi_else(struct r600_shader_ctx *ctx)
8747 {
8748 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
8749 ctx->bc->cf_last->pop_count = 1;
8750
8751 fc_set_mid(ctx, ctx->bc->fc_sp - 1);
8752 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id;
8753 return 0;
8754 }
8755
8756 static int tgsi_endif(struct r600_shader_ctx *ctx)
8757 {
8758 pops(ctx, 1);
8759 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_IF) {
8760 R600_ERR("if/endif unbalanced in shader\n");
8761 return -1;
8762 }
8763
8764 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid == NULL) {
8765 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
8766 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->pop_count = 1;
8767 } else {
8768 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
8769 }
8770 fc_poplevel(ctx);
8771
8772 callstack_pop(ctx, FC_PUSH_VPM);
8773 return 0;
8774 }
8775
8776 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
8777 {
8778 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
8779 * limited to 4096 iterations, like the other LOOP_* instructions. */
8780 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
8781
8782 fc_pushlevel(ctx, FC_LOOP);
8783
8784 /* check stack depth */
8785 callstack_push(ctx, FC_LOOP);
8786 return 0;
8787 }
8788
8789 static int tgsi_endloop(struct r600_shader_ctx *ctx)
8790 {
8791 unsigned i;
8792
8793 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
8794
8795 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_LOOP) {
8796 R600_ERR("loop/endloop in shader code are not paired.\n");
8797 return -EINVAL;
8798 }
8799
8800 /* fixup loop pointers - from r600isa
8801 LOOP END points to CF after LOOP START,
8802 LOOP START point to CF after LOOP END
8803 BRK/CONT point to LOOP END CF
8804 */
8805 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->id + 2;
8806
8807 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
8808
8809 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp - 1].num_mid; i++) {
8810 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[i]->cf_addr = ctx->bc->cf_last->id;
8811 }
8812 /* XXX add LOOPRET support */
8813 fc_poplevel(ctx);
8814 callstack_pop(ctx, FC_LOOP);
8815 return 0;
8816 }
8817
8818 static int tgsi_loop_breakc(struct r600_shader_ctx *ctx)
8819 {
8820 int r;
8821 unsigned int fscp;
8822
8823 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
8824 {
8825 if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
8826 break;
8827 }
8828 if (fscp == 0) {
8829 R600_ERR("BREAKC not inside loop/endloop pair\n");
8830 return -EINVAL;
8831 }
8832
8833 if (ctx->bc->chip_class == EVERGREEN &&
8834 ctx->bc->family != CHIP_CYPRESS &&
8835 ctx->bc->family != CHIP_JUNIPER) {
8836 /* HW bug: ALU_BREAK does not save the active mask correctly */
8837 r = tgsi_uif(ctx);
8838 if (r)
8839 return r;
8840
8841 r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_BREAK);
8842 if (r)
8843 return r;
8844 fc_set_mid(ctx, fscp - 1);
8845
8846 return tgsi_endif(ctx);
8847 } else {
8848 r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
8849 if (r)
8850 return r;
8851 fc_set_mid(ctx, fscp - 1);
8852 }
8853
8854 return 0;
8855 }
8856
8857 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
8858 {
8859 unsigned int fscp;
8860
8861 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
8862 {
8863 if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
8864 break;
8865 }
8866
8867 if (fscp == 0) {
8868 R600_ERR("Break not inside loop/endloop pair\n");
8869 return -EINVAL;
8870 }
8871
8872 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8873
8874 fc_set_mid(ctx, fscp - 1);
8875
8876 return 0;
8877 }
8878
8879 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
8880 {
8881 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8882 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
8883 int r;
8884
8885 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8886 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
8887
8888 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8889 if (!r) {
8890 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
8891 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8892 return emit_inc_ring_offset(ctx, stream, TRUE);
8893 }
8894 return r;
8895 }
8896
8897 static int tgsi_umad(struct r600_shader_ctx *ctx)
8898 {
8899 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8900 struct r600_bytecode_alu alu;
8901 int i, j, k, r;
8902 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8903
8904 /* src0 * src1 */
8905 for (i = 0; i < lasti + 1; i++) {
8906 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8907 continue;
8908
8909 if (ctx->bc->chip_class == CAYMAN) {
8910 for (j = 0 ; j < 4; j++) {
8911 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8912
8913 alu.op = ALU_OP2_MULLO_UINT;
8914 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
8915 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
8916 }
8917 alu.dst.chan = j;
8918 alu.dst.sel = ctx->temp_reg;
8919 alu.dst.write = (j == i);
8920 if (j == 3)
8921 alu.last = 1;
8922 r = r600_bytecode_add_alu(ctx->bc, &alu);
8923 if (r)
8924 return r;
8925 }
8926 } else {
8927 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8928
8929 alu.dst.chan = i;
8930 alu.dst.sel = ctx->temp_reg;
8931 alu.dst.write = 1;
8932
8933 alu.op = ALU_OP2_MULLO_UINT;
8934 for (j = 0; j < 2; j++) {
8935 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
8936 }
8937
8938 alu.last = 1;
8939 r = r600_bytecode_add_alu(ctx->bc, &alu);
8940 if (r)
8941 return r;
8942 }
8943 }
8944
8945
8946 for (i = 0; i < lasti + 1; i++) {
8947 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8948 continue;
8949
8950 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8951 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8952
8953 alu.op = ALU_OP2_ADD_INT;
8954
8955 alu.src[0].sel = ctx->temp_reg;
8956 alu.src[0].chan = i;
8957
8958 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8959 if (i == lasti) {
8960 alu.last = 1;
8961 }
8962 r = r600_bytecode_add_alu(ctx->bc, &alu);
8963 if (r)
8964 return r;
8965 }
8966 return 0;
8967 }
8968
8969 static int tgsi_pk2h(struct r600_shader_ctx *ctx)
8970 {
8971 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8972 struct r600_bytecode_alu alu;
8973 int r, i;
8974 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8975
8976 /* temp.xy = f32_to_f16(src) */
8977 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8978 alu.op = ALU_OP1_FLT32_TO_FLT16;
8979 alu.dst.chan = 0;
8980 alu.dst.sel = ctx->temp_reg;
8981 alu.dst.write = 1;
8982 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8983 r = r600_bytecode_add_alu(ctx->bc, &alu);
8984 if (r)
8985 return r;
8986 alu.dst.chan = 1;
8987 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
8988 alu.last = 1;
8989 r = r600_bytecode_add_alu(ctx->bc, &alu);
8990 if (r)
8991 return r;
8992
8993 /* dst.x = temp.y * 0x10000 + temp.x */
8994 for (i = 0; i < lasti + 1; i++) {
8995 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8996 continue;
8997
8998 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8999 alu.op = ALU_OP3_MULADD_UINT24;
9000 alu.is_op3 = 1;
9001 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9002 alu.last = i == lasti;
9003 alu.src[0].sel = ctx->temp_reg;
9004 alu.src[0].chan = 1;
9005 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9006 alu.src[1].value = 0x10000;
9007 alu.src[2].sel = ctx->temp_reg;
9008 alu.src[2].chan = 0;
9009 r = r600_bytecode_add_alu(ctx->bc, &alu);
9010 if (r)
9011 return r;
9012 }
9013
9014 return 0;
9015 }
9016
9017 static int tgsi_up2h(struct r600_shader_ctx *ctx)
9018 {
9019 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9020 struct r600_bytecode_alu alu;
9021 int r, i;
9022 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9023
9024 /* temp.x = src.x */
9025 /* note: no need to mask out the high bits */
9026 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9027 alu.op = ALU_OP1_MOV;
9028 alu.dst.chan = 0;
9029 alu.dst.sel = ctx->temp_reg;
9030 alu.dst.write = 1;
9031 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9032 r = r600_bytecode_add_alu(ctx->bc, &alu);
9033 if (r)
9034 return r;
9035
9036 /* temp.y = src.x >> 16 */
9037 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9038 alu.op = ALU_OP2_LSHR_INT;
9039 alu.dst.chan = 1;
9040 alu.dst.sel = ctx->temp_reg;
9041 alu.dst.write = 1;
9042 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9043 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9044 alu.src[1].value = 16;
9045 alu.last = 1;
9046 r = r600_bytecode_add_alu(ctx->bc, &alu);
9047 if (r)
9048 return r;
9049
9050 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
9051 for (i = 0; i < lasti + 1; i++) {
9052 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9053 continue;
9054 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9055 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9056 alu.op = ALU_OP1_FLT16_TO_FLT32;
9057 alu.src[0].sel = ctx->temp_reg;
9058 alu.src[0].chan = i % 2;
9059 alu.last = i == lasti;
9060 r = r600_bytecode_add_alu(ctx->bc, &alu);
9061 if (r)
9062 return r;
9063 }
9064
9065 return 0;
9066 }
9067
9068 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
9069 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
9070 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9071 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9072
9073 /* XXX:
9074 * For state trackers other than OpenGL, we'll want to use
9075 * _RECIP_IEEE instead.
9076 */
9077 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
9078
9079 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
9080 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9081 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9082 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9083 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9084 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9085 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9086 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9087 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9088 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9089 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9090 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9091 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9092 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9093 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
9094 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9095 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
9096 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9097 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9098 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9099 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9100 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9101 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9102 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9103 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9104 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9105 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
9106 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9107 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9108 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9109 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9110 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9111 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9112 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9113 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9114 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
9115 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9116 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9117 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9118 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9119 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9120 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9121 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9122 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9123 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9124 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9125 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9126 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9127 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9128 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9129 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9130 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9131 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9132 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9133 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9134 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9135 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
9136 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9137 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9138 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9139 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9140 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9141 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
9142 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9143 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9144 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9145 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9146 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9147 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9148 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9149 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9150 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9151 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9152 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9153 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9154 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9155 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
9156 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
9157 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9158 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9159 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9160 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9161 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
9162 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9163 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9164 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9165 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9166 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9167 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
9168 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9169 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9170 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9171 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9172 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9173 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9174 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9175 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9176 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9177 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9178 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9179 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9180 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9181 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9182 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9183 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9184 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9185 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9186 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9187 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
9188 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9189 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_loop_breakc},
9190 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9191 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9192 [TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
9193 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
9194 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9195 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9196 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9197 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9198 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9199 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
9200 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9201 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
9202 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9203 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9204 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9205 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9206 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9207 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9208 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9209 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9210 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9211 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9212 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
9213 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9214 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
9215 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9216 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9217 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9218 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9219 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9220 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9221 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9222 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9223 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9224 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9225 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9226 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9227 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9228 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9229 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9230 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9231 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
9232 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9233 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9234 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9235 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9236 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9237 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9238 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9239 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9240 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
9241 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9242 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9243 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9244 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9245 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9246 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9247 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9248 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9249 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9250 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9251 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9252 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9253 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9254 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9255 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9256 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
9257 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
9258 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
9259 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
9260 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
9261 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
9262 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
9263 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
9264 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
9265 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
9266 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
9267 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
9268 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
9269 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9270 };
9271
9272 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
9273 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9274 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9275 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9276 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
9277 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
9278 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9279 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9280 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9281 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9282 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9283 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9284 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9285 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9286 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9287 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9288 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9289 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9290 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9291 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
9292 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9293 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
9294 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9295 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9296 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9297 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9298 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9299 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9300 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9301 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9302 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9303 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
9304 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9305 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9306 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9307 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9308 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9309 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9310 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9311 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9312 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
9313 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9314 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9315 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9316 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9317 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9318 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9319 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9320 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9321 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9322 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9323 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9324 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9325 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9326 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9327 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
9328 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9329 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9330 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9331 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9332 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9333 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9334 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9335 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9336 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9337 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9338 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9339 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
9340 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9341 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9342 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9343 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9344 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9345 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9346 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9347 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9348 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9349 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9350 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9351 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9352 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9353 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
9354 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
9355 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9356 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9357 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9358 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9359 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9360 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9361 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9362 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9363 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9364 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9365 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
9366 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9367 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9368 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9369 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9370 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9371 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9372 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9373 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9374 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9375 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9376 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9377 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9378 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9379 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9380 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9381 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9382 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9383 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9384 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9385 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
9386 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9387 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
9388 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9389 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9390 /* Refer below for TGSI_OPCODE_DFMA */
9391 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
9392 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9393 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9394 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9395 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9396 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9397 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9398 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9399 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
9400 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9401 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9402 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9403 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9404 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9405 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9406 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9407 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9408 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9409 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9410 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9411 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9412 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9413 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9414 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9415 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9416 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9417 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9418 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9419 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9420 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9421 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9422 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9423 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9424 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9425 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9426 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9427 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9428 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9429 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9430 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9431 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9432 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9433 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9434 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9435 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9436 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9437 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9438 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9439 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9440 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9441 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9442 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9443 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9444 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9445 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9446 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9447 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9448 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9449 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9450 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9451 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9452 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9453 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9454 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9455 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9456 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
9457 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
9458 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9459 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9460 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9461 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9462 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9463 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9464 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9465 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9466 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9467 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9468 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9469 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9470 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9471 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9472 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9473 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
9474 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9475 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9476 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9477 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9478 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9479 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9480 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9481 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9482 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9483 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
9484 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9485 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9486 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9487 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9488 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9489 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9490 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9491 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9492 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9493 };
9494
9495 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
9496 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9497 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9498 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9499 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
9500 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
9501 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9502 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9503 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9504 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9505 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9506 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9507 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9508 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9509 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9510 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9511 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9512 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9513 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9514 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
9515 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
9516 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
9517 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9518 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9519 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9520 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9521 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9522 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9523 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
9524 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
9525 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
9526 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
9527 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9528 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9529 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9530 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9531 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
9532 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9533 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9534 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9535 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
9536 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9537 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9538 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9539 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9540 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9541 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9542 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9543 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
9544 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9545 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9546 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9547 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9548 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9549 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9550 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
9551 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9552 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9553 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9554 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9555 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9556 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9557 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9558 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9559 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9560 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9561 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9562 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
9563 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9564 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9565 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9566 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9567 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9568 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9569 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9570 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9571 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9572 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9573 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9574 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9575 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9576 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
9577 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
9578 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9579 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
9580 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9581 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9582 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9583 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9584 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9585 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9586 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9587 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9588 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
9589 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9590 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9591 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9592 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9593 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9594 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9595 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9596 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9597 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9598 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9599 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9600 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9601 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9602 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9603 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9604 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9605 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9606 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9607 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9608 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
9609 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9610 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
9611 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9612 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9613 /* Refer below for TGSI_OPCODE_DFMA */
9614 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
9615 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9616 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9617 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9618 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9619 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9620 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9621 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9622 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
9623 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
9624 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9625 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9626 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9627 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9628 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9629 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9630 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
9631 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9632 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9633 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9634 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9635 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9636 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9637 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9638 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9639 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9640 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9641 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9642 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9643 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9644 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9645 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9646 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9647 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9648 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9649 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9650 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9651 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9652 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9653 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9654 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9655 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9656 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9657 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9658 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9659 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9660 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9661 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9662 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9663 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9664 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9665 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9666 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9667 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9668 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9669 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9670 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9671 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9672 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9673 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9674 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9675 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
9676 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
9677 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9678 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9679 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
9680 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
9681 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9682 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9683 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9684 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9685 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9686 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9687 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9688 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9689 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9690 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9691 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9692 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9693 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9694 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9695 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9696 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
9697 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9698 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9699 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9700 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9701 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9702 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9703 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9704 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9705 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9706 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
9707 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9708 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9709 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9710 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9711 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9712 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9713 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9714 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9715 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9716 };