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r600g: use special constants for 0, 1, -1, 1.0f, 0.5f etc
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
37 {
38 struct r600_pipe_state *rstate = &shader->rstate;
39 struct r600_shader *rshader = &shader->shader;
40 unsigned spi_vs_out_id[10];
41 unsigned i, tmp;
42
43 /* clear previous register */
44 rstate->nregs = 0;
45
46 /* so far never got proper semantic id from tgsi */
47 /* FIXME better to move this in config things so they get emited
48 * only one time per cs
49 */
50 for (i = 0; i < 10; i++) {
51 spi_vs_out_id[i] = 0;
52 }
53 for (i = 0; i < 32; i++) {
54 tmp = i << ((i & 3) * 8);
55 spi_vs_out_id[i / 4] |= tmp;
56 }
57 for (i = 0; i < 10; i++) {
58 r600_pipe_state_add_reg(rstate,
59 R_028614_SPI_VS_OUT_ID_0 + i * 4,
60 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
61 }
62
63 r600_pipe_state_add_reg(rstate,
64 R_0286C4_SPI_VS_OUT_CONFIG,
65 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
66 0xFFFFFFFF, NULL);
67 r600_pipe_state_add_reg(rstate,
68 R_028868_SQ_PGM_RESOURCES_VS,
69 S_028868_NUM_GPRS(rshader->bc.ngpr) |
70 S_028868_STACK_SIZE(rshader->bc.nstack),
71 0xFFFFFFFF, NULL);
72 r600_pipe_state_add_reg(rstate,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS,
74 0x00000000, 0xFFFFFFFF, NULL);
75 r600_pipe_state_add_reg(rstate,
76 R_028858_SQ_PGM_START_VS,
77 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
78
79 r600_pipe_state_add_reg(rstate,
80 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
81 0xFFFFFFFF, NULL);
82
83 }
84
85 int r600_find_vs_semantic_index(struct r600_shader *vs,
86 struct r600_shader *ps, int id)
87 {
88 struct r600_shader_io *input = &ps->input[id];
89
90 for (int i = 0; i < vs->noutput; i++) {
91 if (input->name == vs->output[i].name &&
92 input->sid == vs->output[i].sid) {
93 return i - 1;
94 }
95 }
96 return 0;
97 }
98
99 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
100 {
101 struct r600_pipe_state *rstate = &shader->rstate;
102 struct r600_shader *rshader = &shader->shader;
103 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
104 int pos_index = -1, face_index = -1;
105
106 rstate->nregs = 0;
107
108 for (i = 0; i < rshader->ninput; i++) {
109 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
110 pos_index = i;
111 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
112 face_index = i;
113 }
114
115 for (i = 0; i < rshader->noutput; i++) {
116 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
117 r600_pipe_state_add_reg(rstate,
118 R_02880C_DB_SHADER_CONTROL,
119 S_02880C_Z_EXPORT_ENABLE(1),
120 S_02880C_Z_EXPORT_ENABLE(1), NULL);
121 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
122 r600_pipe_state_add_reg(rstate,
123 R_02880C_DB_SHADER_CONTROL,
124 S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
125 S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL);
126 }
127
128 exports_ps = 0;
129 num_cout = 0;
130 for (i = 0; i < rshader->noutput; i++) {
131 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
132 exports_ps |= 1;
133 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
134 num_cout++;
135 }
136 }
137 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
138 if (!exports_ps) {
139 /* always at least export 1 component per pixel */
140 exports_ps = 2;
141 }
142
143 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
144 S_0286CC_PERSP_GRADIENT_ENA(1);
145 spi_input_z = 0;
146 if (pos_index != -1) {
147 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
148 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
149 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
150 S_0286CC_BARYC_SAMPLE_CNTL(1));
151 spi_input_z |= 1;
152 }
153
154 spi_ps_in_control_1 = 0;
155 if (face_index != -1) {
156 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
157 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
158 }
159
160 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
161 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
162 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
163 r600_pipe_state_add_reg(rstate,
164 R_028840_SQ_PGM_START_PS,
165 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
166 r600_pipe_state_add_reg(rstate,
167 R_028850_SQ_PGM_RESOURCES_PS,
168 S_028868_NUM_GPRS(rshader->bc.ngpr) |
169 S_028868_STACK_SIZE(rshader->bc.nstack),
170 0xFFFFFFFF, NULL);
171 r600_pipe_state_add_reg(rstate,
172 R_028854_SQ_PGM_EXPORTS_PS,
173 exports_ps, 0xFFFFFFFF, NULL);
174 r600_pipe_state_add_reg(rstate,
175 R_0288CC_SQ_PGM_CF_OFFSET_PS,
176 0x00000000, 0xFFFFFFFF, NULL);
177
178 if (rshader->uses_kill) {
179 /* only set some bits here, the other bits are set in the dsa state */
180 r600_pipe_state_add_reg(rstate,
181 R_02880C_DB_SHADER_CONTROL,
182 S_02880C_KILL_ENABLE(1),
183 S_02880C_KILL_ENABLE(1), NULL);
184 }
185 r600_pipe_state_add_reg(rstate,
186 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
187 0xFFFFFFFF, NULL);
188 }
189
190 int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
191 {
192 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
193 struct r600_shader *rshader = &shader->shader;
194 void *ptr;
195
196 /* copy new shader */
197 if (shader->bo == NULL) {
198 shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0, 0);
199 if (shader->bo == NULL) {
200 return -ENOMEM;
201 }
202 ptr = r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
203 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
204 r600_bo_unmap(rctx->radeon, shader->bo);
205 }
206 /* build state */
207 switch (rshader->processor_type) {
208 case TGSI_PROCESSOR_VERTEX:
209 if (rshader->family >= CHIP_CEDAR) {
210 evergreen_pipe_shader_vs(ctx, shader);
211 } else {
212 r600_pipe_shader_vs(ctx, shader);
213 }
214 break;
215 case TGSI_PROCESSOR_FRAGMENT:
216 if (rshader->family >= CHIP_CEDAR) {
217 evergreen_pipe_shader_ps(ctx, shader);
218 } else {
219 r600_pipe_shader_ps(ctx, shader);
220 }
221 break;
222 default:
223 return -EINVAL;
224 }
225 return 0;
226 }
227
228 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
229 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
230 {
231 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
232 int r;
233
234 //fprintf(stderr, "--------------------------------------------------------------\n");
235 //tgsi_dump(tokens, 0);
236 shader->shader.family = r600_get_family(rctx->radeon);
237 r = r600_shader_from_tgsi(tokens, &shader->shader);
238 if (r) {
239 R600_ERR("translation from TGSI failed !\n");
240 return r;
241 }
242 r = r600_bc_build(&shader->shader.bc);
243 if (r) {
244 R600_ERR("building bytecode failed !\n");
245 return r;
246 }
247 //r600_bc_dump(&shader->shader.bc);
248 //fprintf(stderr, "______________________________________________________________\n");
249 return r600_pipe_shader(ctx, shader);
250 }
251
252 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
253 {
254 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
255
256 r600_bo_reference(rctx->radeon, &shader->bo, NULL);
257 r600_bc_clear(&shader->shader.bc);
258 }
259
260 /*
261 * tgsi -> r600 shader
262 */
263 struct r600_shader_tgsi_instruction;
264
265 struct r600_shader_ctx {
266 struct tgsi_shader_info info;
267 struct tgsi_parse_context parse;
268 const struct tgsi_token *tokens;
269 unsigned type;
270 unsigned file_offset[TGSI_FILE_COUNT];
271 unsigned temp_reg;
272 struct r600_shader_tgsi_instruction *inst_info;
273 struct r600_bc *bc;
274 struct r600_shader *shader;
275 u32 value[4];
276 u32 *literals;
277 u32 nliterals;
278 u32 max_driver_temp_used;
279 /* needed for evergreen interpolation */
280 boolean input_centroid;
281 boolean input_linear;
282 boolean input_perspective;
283 int num_interp_gpr;
284 };
285
286 struct r600_shader_tgsi_instruction {
287 unsigned tgsi_opcode;
288 unsigned is_op3;
289 unsigned r600_opcode;
290 int (*process)(struct r600_shader_ctx *ctx);
291 };
292
293 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
294 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
295
296 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
297 {
298 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
299 int j;
300
301 if (i->Instruction.NumDstRegs > 1) {
302 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
303 return -EINVAL;
304 }
305 if (i->Instruction.Predicate) {
306 R600_ERR("predicate unsupported\n");
307 return -EINVAL;
308 }
309 #if 0
310 if (i->Instruction.Label) {
311 R600_ERR("label unsupported\n");
312 return -EINVAL;
313 }
314 #endif
315 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
316 if (i->Src[j].Register.Dimension) {
317 R600_ERR("unsupported src %d (dimension %d)\n", j,
318 i->Src[j].Register.Dimension);
319 return -EINVAL;
320 }
321 }
322 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
323 if (i->Dst[j].Register.Dimension) {
324 R600_ERR("unsupported dst (dimension)\n");
325 return -EINVAL;
326 }
327 }
328 return 0;
329 }
330
331 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
332 {
333 int i, r;
334 struct r600_bc_alu alu;
335 int gpr = 0, base_chan = 0;
336 int ij_index = 0;
337
338 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
339 ij_index = 0;
340 if (ctx->shader->input[input].centroid)
341 ij_index++;
342 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
343 ij_index = 0;
344 /* if we have perspective add one */
345 if (ctx->input_perspective) {
346 ij_index++;
347 /* if we have perspective centroid */
348 if (ctx->input_centroid)
349 ij_index++;
350 }
351 if (ctx->shader->input[input].centroid)
352 ij_index++;
353 }
354
355 /* work out gpr and base_chan from index */
356 gpr = ij_index / 2;
357 base_chan = (2 * (ij_index % 2)) + 1;
358
359 for (i = 0; i < 8; i++) {
360 memset(&alu, 0, sizeof(struct r600_bc_alu));
361
362 if (i < 4)
363 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
364 else
365 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
366
367 if ((i > 1) && (i < 6)) {
368 alu.dst.sel = ctx->shader->input[input].gpr;
369 alu.dst.write = 1;
370 }
371
372 alu.dst.chan = i % 4;
373
374 alu.src[0].sel = gpr;
375 alu.src[0].chan = (base_chan - (i % 2));
376
377 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
378
379 alu.bank_swizzle_force = SQ_ALU_VEC_210;
380 if ((i % 4) == 3)
381 alu.last = 1;
382 r = r600_bc_add_alu(ctx->bc, &alu);
383 if (r)
384 return r;
385 }
386 return 0;
387 }
388
389
390 static int tgsi_declaration(struct r600_shader_ctx *ctx)
391 {
392 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
393 unsigned i;
394
395 switch (d->Declaration.File) {
396 case TGSI_FILE_INPUT:
397 i = ctx->shader->ninput++;
398 ctx->shader->input[i].name = d->Semantic.Name;
399 ctx->shader->input[i].sid = d->Semantic.Index;
400 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
401 ctx->shader->input[i].centroid = d->Declaration.Centroid;
402 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
403 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == CHIPREV_EVERGREEN) {
404 /* turn input into interpolate on EG */
405 if (ctx->shader->input[i].name != TGSI_SEMANTIC_POSITION) {
406 if (ctx->shader->input[i].interpolate > 0) {
407 ctx->shader->input[i].lds_pos = ctx->shader->nlds++;
408 evergreen_interp_alu(ctx, i);
409 }
410 }
411 }
412 break;
413 case TGSI_FILE_OUTPUT:
414 i = ctx->shader->noutput++;
415 ctx->shader->output[i].name = d->Semantic.Name;
416 ctx->shader->output[i].sid = d->Semantic.Index;
417 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
418 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
419 break;
420 case TGSI_FILE_CONSTANT:
421 case TGSI_FILE_TEMPORARY:
422 case TGSI_FILE_SAMPLER:
423 case TGSI_FILE_ADDRESS:
424 break;
425 default:
426 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
427 return -EINVAL;
428 }
429 return 0;
430 }
431
432 static int r600_get_temp(struct r600_shader_ctx *ctx)
433 {
434 return ctx->temp_reg + ctx->max_driver_temp_used++;
435 }
436
437 /*
438 * for evergreen we need to scan the shader to find the number of GPRs we need to
439 * reserve for interpolation.
440 *
441 * we need to know if we are going to emit
442 * any centroid inputs
443 * if perspective and linear are required
444 */
445 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
446 {
447 int i;
448 int num_baryc;
449
450 ctx->input_linear = FALSE;
451 ctx->input_perspective = FALSE;
452 ctx->input_centroid = FALSE;
453 ctx->num_interp_gpr = 1;
454
455 /* any centroid inputs */
456 for (i = 0; i < ctx->info.num_inputs; i++) {
457 /* skip position/face */
458 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
459 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
460 continue;
461 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
462 ctx->input_linear = TRUE;
463 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
464 ctx->input_perspective = TRUE;
465 if (ctx->info.input_centroid[i])
466 ctx->input_centroid = TRUE;
467 }
468
469 num_baryc = 0;
470 /* ignoring sample for now */
471 if (ctx->input_perspective)
472 num_baryc++;
473 if (ctx->input_linear)
474 num_baryc++;
475 if (ctx->input_centroid)
476 num_baryc *= 2;
477
478 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
479
480 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
481 return ctx->num_interp_gpr;
482 }
483
484 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
485 {
486 struct tgsi_full_immediate *immediate;
487 struct r600_shader_ctx ctx;
488 struct r600_bc_output output[32];
489 unsigned output_done, noutput;
490 unsigned opcode;
491 int i, r = 0, pos0;
492
493 ctx.bc = &shader->bc;
494 ctx.shader = shader;
495 r = r600_bc_init(ctx.bc, shader->family);
496 if (r)
497 return r;
498 ctx.tokens = tokens;
499 tgsi_scan_shader(tokens, &ctx.info);
500 tgsi_parse_init(&ctx.parse, tokens);
501 ctx.type = ctx.parse.FullHeader.Processor.Processor;
502 shader->processor_type = ctx.type;
503 ctx.bc->type = shader->processor_type;
504
505 /* register allocations */
506 /* Values [0,127] correspond to GPR[0..127].
507 * Values [128,159] correspond to constant buffer bank 0
508 * Values [160,191] correspond to constant buffer bank 1
509 * Values [256,511] correspond to cfile constants c[0..255].
510 * Other special values are shown in the list below.
511 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
512 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
513 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
514 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
515 * 248 SQ_ALU_SRC_0: special constant 0.0.
516 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
517 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
518 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
519 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
520 * 253 SQ_ALU_SRC_LITERAL: literal constant.
521 * 254 SQ_ALU_SRC_PV: previous vector result.
522 * 255 SQ_ALU_SRC_PS: previous scalar result.
523 */
524 for (i = 0; i < TGSI_FILE_COUNT; i++) {
525 ctx.file_offset[i] = 0;
526 }
527 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
528 ctx.file_offset[TGSI_FILE_INPUT] = 1;
529 if (ctx.bc->chiprev == CHIPREV_EVERGREEN) {
530 r600_bc_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
531 } else {
532 r600_bc_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
533 }
534 }
535 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev == CHIPREV_EVERGREEN) {
536 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
537 }
538 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
539 ctx.info.file_count[TGSI_FILE_INPUT];
540 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
541 ctx.info.file_count[TGSI_FILE_OUTPUT];
542
543 ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
544
545 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
546 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
547 ctx.info.file_count[TGSI_FILE_TEMPORARY];
548
549 ctx.nliterals = 0;
550 ctx.literals = NULL;
551
552 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
553 tgsi_parse_token(&ctx.parse);
554 switch (ctx.parse.FullToken.Token.Type) {
555 case TGSI_TOKEN_TYPE_IMMEDIATE:
556 immediate = &ctx.parse.FullToken.FullImmediate;
557 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
558 if(ctx.literals == NULL) {
559 r = -ENOMEM;
560 goto out_err;
561 }
562 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
563 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
564 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
565 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
566 ctx.nliterals++;
567 break;
568 case TGSI_TOKEN_TYPE_DECLARATION:
569 r = tgsi_declaration(&ctx);
570 if (r)
571 goto out_err;
572 break;
573 case TGSI_TOKEN_TYPE_INSTRUCTION:
574 r = tgsi_is_supported(&ctx);
575 if (r)
576 goto out_err;
577 ctx.max_driver_temp_used = 0;
578 /* reserve first tmp for everyone */
579 r600_get_temp(&ctx);
580 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
581 if (ctx.bc->chiprev == CHIPREV_EVERGREEN)
582 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
583 else
584 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
585 r = ctx.inst_info->process(&ctx);
586 if (r)
587 goto out_err;
588 r = r600_bc_add_literal(ctx.bc, ctx.value);
589 if (r)
590 goto out_err;
591 break;
592 default:
593 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
594 r = -EINVAL;
595 goto out_err;
596 }
597 }
598 /* export output */
599 noutput = shader->noutput;
600 for (i = 0, pos0 = 0; i < noutput; i++) {
601 memset(&output[i], 0, sizeof(struct r600_bc_output));
602 output[i].gpr = shader->output[i].gpr;
603 output[i].elem_size = 3;
604 output[i].swizzle_x = 0;
605 output[i].swizzle_y = 1;
606 output[i].swizzle_z = 2;
607 output[i].swizzle_w = 3;
608 output[i].barrier = 1;
609 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
610 output[i].array_base = i - pos0;
611 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
612 switch (ctx.type) {
613 case TGSI_PROCESSOR_VERTEX:
614 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
615 output[i].array_base = 60;
616 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
617 /* position doesn't count in array_base */
618 pos0++;
619 }
620 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
621 output[i].array_base = 61;
622 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
623 /* position doesn't count in array_base */
624 pos0++;
625 }
626 break;
627 case TGSI_PROCESSOR_FRAGMENT:
628 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
629 output[i].array_base = shader->output[i].sid;
630 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
631 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
632 output[i].array_base = 61;
633 output[i].swizzle_x = 2;
634 output[i].swizzle_y = 7;
635 output[i].swizzle_z = output[i].swizzle_w = 7;
636 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
637 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
638 output[i].array_base = 61;
639 output[i].swizzle_x = 7;
640 output[i].swizzle_y = 1;
641 output[i].swizzle_z = output[i].swizzle_w = 7;
642 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
643 } else {
644 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
645 r = -EINVAL;
646 goto out_err;
647 }
648 break;
649 default:
650 R600_ERR("unsupported processor type %d\n", ctx.type);
651 r = -EINVAL;
652 goto out_err;
653 }
654 }
655 /* add fake param output for vertex shader if no param is exported */
656 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
657 for (i = 0, pos0 = 0; i < noutput; i++) {
658 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
659 pos0 = 1;
660 break;
661 }
662 }
663 if (!pos0) {
664 memset(&output[i], 0, sizeof(struct r600_bc_output));
665 output[i].gpr = 0;
666 output[i].elem_size = 3;
667 output[i].swizzle_x = 0;
668 output[i].swizzle_y = 1;
669 output[i].swizzle_z = 2;
670 output[i].swizzle_w = 3;
671 output[i].barrier = 1;
672 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
673 output[i].array_base = 0;
674 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
675 noutput++;
676 }
677 }
678 /* add fake pixel export */
679 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
680 memset(&output[0], 0, sizeof(struct r600_bc_output));
681 output[0].gpr = 0;
682 output[0].elem_size = 3;
683 output[0].swizzle_x = 7;
684 output[0].swizzle_y = 7;
685 output[0].swizzle_z = 7;
686 output[0].swizzle_w = 7;
687 output[0].barrier = 1;
688 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
689 output[0].array_base = 0;
690 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
691 noutput++;
692 }
693 /* set export done on last export of each type */
694 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
695 if (i == (noutput - 1)) {
696 output[i].end_of_program = 1;
697 }
698 if (!(output_done & (1 << output[i].type))) {
699 output_done |= (1 << output[i].type);
700 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
701 }
702 }
703 /* add output to bytecode */
704 for (i = 0; i < noutput; i++) {
705 r = r600_bc_add_output(ctx.bc, &output[i]);
706 if (r)
707 goto out_err;
708 }
709 free(ctx.literals);
710 tgsi_parse_free(&ctx.parse);
711 return 0;
712 out_err:
713 free(ctx.literals);
714 tgsi_parse_free(&ctx.parse);
715 return r;
716 }
717
718 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
719 {
720 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
721 return -EINVAL;
722 }
723
724 static int tgsi_end(struct r600_shader_ctx *ctx)
725 {
726 return 0;
727 }
728
729 static int tgsi_src(struct r600_shader_ctx *ctx,
730 const struct tgsi_full_src_register *tgsi_src,
731 struct r600_bc_alu_src *r600_src)
732 {
733 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
734 r600_src->neg = tgsi_src->Register.Negate;
735 r600_src->abs = tgsi_src->Register.Absolute;
736 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
737 int index;
738 if((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
739 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
740 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
741
742 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
743 switch(ctx->literals[index]) {
744 case 0:
745 r600_src->sel = V_SQ_ALU_SRC_0;
746 return 0;
747 case 1:
748 r600_src->sel = V_SQ_ALU_SRC_1_INT;
749 return 0;
750 case -1:
751 r600_src->sel = V_SQ_ALU_SRC_M_1_INT;
752 return 0;
753 case 0x3F800000: // 1.0f
754 r600_src->sel = V_SQ_ALU_SRC_1;
755 return 0;
756 case 0x3F000000: // 0.5f
757 r600_src->sel = V_SQ_ALU_SRC_0_5;
758 return 0;
759 case 0xBF800000: // -1.0f
760 r600_src->sel = V_SQ_ALU_SRC_1;
761 r600_src->neg ^= 1;
762 return 0;
763 case 0xBF000000: // -0.5f
764 r600_src->sel = V_SQ_ALU_SRC_0_5;
765 r600_src->neg ^= 1;
766 return 0;
767 }
768 }
769 index = tgsi_src->Register.Index;
770 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
771 ctx->value[0] = ctx->literals[index * 4 + 0];
772 ctx->value[1] = ctx->literals[index * 4 + 1];
773 ctx->value[2] = ctx->literals[index * 4 + 2];
774 ctx->value[3] = ctx->literals[index * 4 + 3];
775 } else {
776 if (tgsi_src->Register.Indirect)
777 r600_src->rel = V_SQ_REL_RELATIVE;
778 r600_src->sel = tgsi_src->Register.Index;
779 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
780 }
781 return 0;
782 }
783
784 static int tgsi_dst(struct r600_shader_ctx *ctx,
785 const struct tgsi_full_dst_register *tgsi_dst,
786 unsigned swizzle,
787 struct r600_bc_alu_dst *r600_dst)
788 {
789 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
790
791 r600_dst->sel = tgsi_dst->Register.Index;
792 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
793 r600_dst->chan = swizzle;
794 r600_dst->write = 1;
795 if (tgsi_dst->Register.Indirect)
796 r600_dst->rel = V_SQ_REL_RELATIVE;
797 if (inst->Instruction.Saturate) {
798 r600_dst->clamp = 1;
799 }
800 return 0;
801 }
802
803 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
804 {
805 switch (swizzle) {
806 case 0:
807 return tgsi_src->Register.SwizzleX;
808 case 1:
809 return tgsi_src->Register.SwizzleY;
810 case 2:
811 return tgsi_src->Register.SwizzleZ;
812 case 3:
813 return tgsi_src->Register.SwizzleW;
814 default:
815 return 0;
816 }
817 }
818
819 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
820 {
821 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
822 struct r600_bc_alu alu;
823 int i, j, k, nconst, r;
824
825 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
826 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
827 nconst++;
828 }
829 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
830 if (r) {
831 return r;
832 }
833 }
834 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
835 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
836 int treg = r600_get_temp(ctx);
837 for (k = 0; k < 4; k++) {
838 memset(&alu, 0, sizeof(struct r600_bc_alu));
839 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
840 alu.src[0].sel = r600_src[i].sel;
841 alu.src[0].chan = k;
842 alu.src[0].rel = r600_src[i].rel;
843 alu.dst.sel = treg;
844 alu.dst.chan = k;
845 alu.dst.write = 1;
846 if (k == 3)
847 alu.last = 1;
848 r = r600_bc_add_alu(ctx->bc, &alu);
849 if (r)
850 return r;
851 }
852 r600_src[i].sel = treg;
853 r600_src[i].rel =0;
854 j--;
855 }
856 }
857 return 0;
858 }
859
860 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
861 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
862 {
863 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
864 struct r600_bc_alu alu;
865 int i, j, k, nliteral, r;
866
867 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
868 if (r600_src[i].sel == V_SQ_ALU_SRC_LITERAL) {
869 nliteral++;
870 }
871 }
872 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
873 if (j > 0 && r600_src[i].sel == V_SQ_ALU_SRC_LITERAL) {
874 int treg = r600_get_temp(ctx);
875 for (k = 0; k < 4; k++) {
876 memset(&alu, 0, sizeof(struct r600_bc_alu));
877 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
878 alu.src[0].sel = r600_src[i].sel;
879 alu.src[0].chan = k;
880 alu.dst.sel = treg;
881 alu.dst.chan = k;
882 alu.dst.write = 1;
883 if (k == 3)
884 alu.last = 1;
885 r = r600_bc_add_alu(ctx->bc, &alu);
886 if (r)
887 return r;
888 }
889 r = r600_bc_add_literal(ctx->bc, &ctx->literals[inst->Src[i].Register.Index * 4]);
890 if (r)
891 return r;
892 r600_src[i].sel = treg;
893 j--;
894 }
895 }
896 return 0;
897 }
898
899 static int tgsi_last_instruction(unsigned writemask)
900 {
901 int i, lasti = 0;
902
903 for (i = 0; i < 4; i++) {
904 if (writemask & (1 << i)) {
905 lasti = i;
906 }
907 }
908 return lasti;
909 }
910
911 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
912 {
913 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
914 struct r600_bc_alu_src r600_src[3];
915 struct r600_bc_alu alu;
916 int i, j, r;
917 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
918
919 r = tgsi_split_constant(ctx, r600_src);
920 if (r)
921 return r;
922 r = tgsi_split_literal_constant(ctx, r600_src);
923 if (r)
924 return r;
925 for (i = 0; i < lasti + 1; i++) {
926 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
927 continue;
928
929 memset(&alu, 0, sizeof(struct r600_bc_alu));
930 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
931 if (r)
932 return r;
933
934 alu.inst = ctx->inst_info->r600_opcode;
935 if (!swap) {
936 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
937 alu.src[j] = r600_src[j];
938 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
939 }
940 } else {
941 alu.src[0] = r600_src[1];
942 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
943
944 alu.src[1] = r600_src[0];
945 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
946 }
947 /* handle some special cases */
948 switch (ctx->inst_info->tgsi_opcode) {
949 case TGSI_OPCODE_SUB:
950 alu.src[1].neg = 1;
951 break;
952 case TGSI_OPCODE_ABS:
953 alu.src[0].abs = 1;
954 break;
955 default:
956 break;
957 }
958 if (i == lasti) {
959 alu.last = 1;
960 }
961 r = r600_bc_add_alu(ctx->bc, &alu);
962 if (r)
963 return r;
964 }
965 return 0;
966 }
967
968 static int tgsi_op2(struct r600_shader_ctx *ctx)
969 {
970 return tgsi_op2_s(ctx, 0);
971 }
972
973 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
974 {
975 return tgsi_op2_s(ctx, 1);
976 }
977
978 /*
979 * r600 - trunc to -PI..PI range
980 * r700 - normalize by dividing by 2PI
981 * see fdo bug 27901
982 */
983 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
984 struct r600_bc_alu_src r600_src[3])
985 {
986 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
987 int r;
988 uint32_t lit_vals[4];
989 struct r600_bc_alu alu;
990
991 memset(lit_vals, 0, 4*4);
992 r = tgsi_split_constant(ctx, r600_src);
993 if (r)
994 return r;
995 r = tgsi_split_literal_constant(ctx, r600_src);
996 if (r)
997 return r;
998
999 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
1000 lit_vals[1] = fui(0.5f);
1001
1002 memset(&alu, 0, sizeof(struct r600_bc_alu));
1003 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1004 alu.is_op3 = 1;
1005
1006 alu.dst.chan = 0;
1007 alu.dst.sel = ctx->temp_reg;
1008 alu.dst.write = 1;
1009
1010 alu.src[0] = r600_src[0];
1011 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1012
1013 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1014 alu.src[1].chan = 0;
1015 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1016 alu.src[2].chan = 1;
1017 alu.last = 1;
1018 r = r600_bc_add_alu(ctx->bc, &alu);
1019 if (r)
1020 return r;
1021 r = r600_bc_add_literal(ctx->bc, lit_vals);
1022 if (r)
1023 return r;
1024
1025 memset(&alu, 0, sizeof(struct r600_bc_alu));
1026 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
1027
1028 alu.dst.chan = 0;
1029 alu.dst.sel = ctx->temp_reg;
1030 alu.dst.write = 1;
1031
1032 alu.src[0].sel = ctx->temp_reg;
1033 alu.src[0].chan = 0;
1034 alu.last = 1;
1035 r = r600_bc_add_alu(ctx->bc, &alu);
1036 if (r)
1037 return r;
1038
1039 if (ctx->bc->chiprev == CHIPREV_R600) {
1040 lit_vals[0] = fui(3.1415926535897f * 2.0f);
1041 lit_vals[1] = fui(-3.1415926535897f);
1042 } else {
1043 lit_vals[0] = fui(1.0f);
1044 lit_vals[1] = fui(-0.5f);
1045 }
1046
1047 memset(&alu, 0, sizeof(struct r600_bc_alu));
1048 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1049 alu.is_op3 = 1;
1050
1051 alu.dst.chan = 0;
1052 alu.dst.sel = ctx->temp_reg;
1053 alu.dst.write = 1;
1054
1055 alu.src[0].sel = ctx->temp_reg;
1056 alu.src[0].chan = 0;
1057
1058 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1059 alu.src[1].chan = 0;
1060 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1061 alu.src[2].chan = 1;
1062 alu.last = 1;
1063 r = r600_bc_add_alu(ctx->bc, &alu);
1064 if (r)
1065 return r;
1066 r = r600_bc_add_literal(ctx->bc, lit_vals);
1067 if (r)
1068 return r;
1069 return 0;
1070 }
1071
1072 static int tgsi_trig(struct r600_shader_ctx *ctx)
1073 {
1074 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1075 struct r600_bc_alu_src r600_src[3];
1076 struct r600_bc_alu alu;
1077 int i, r;
1078 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1079
1080 r = tgsi_setup_trig(ctx, r600_src);
1081 if (r)
1082 return r;
1083
1084 memset(&alu, 0, sizeof(struct r600_bc_alu));
1085 alu.inst = ctx->inst_info->r600_opcode;
1086 alu.dst.chan = 0;
1087 alu.dst.sel = ctx->temp_reg;
1088 alu.dst.write = 1;
1089
1090 alu.src[0].sel = ctx->temp_reg;
1091 alu.src[0].chan = 0;
1092 alu.last = 1;
1093 r = r600_bc_add_alu(ctx->bc, &alu);
1094 if (r)
1095 return r;
1096
1097 /* replicate result */
1098 for (i = 0; i < lasti + 1; i++) {
1099 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1100 continue;
1101
1102 memset(&alu, 0, sizeof(struct r600_bc_alu));
1103 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1104
1105 alu.src[0].sel = ctx->temp_reg;
1106 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1107 if (r)
1108 return r;
1109 if (i == lasti)
1110 alu.last = 1;
1111 r = r600_bc_add_alu(ctx->bc, &alu);
1112 if (r)
1113 return r;
1114 }
1115 return 0;
1116 }
1117
1118 static int tgsi_scs(struct r600_shader_ctx *ctx)
1119 {
1120 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1121 struct r600_bc_alu_src r600_src[3];
1122 struct r600_bc_alu alu;
1123 int r;
1124
1125 /* We'll only need the trig stuff if we are going to write to the
1126 * X or Y components of the destination vector.
1127 */
1128 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1129 r = tgsi_setup_trig(ctx, r600_src);
1130 if (r)
1131 return r;
1132 }
1133
1134 /* dst.x = COS */
1135 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1136 memset(&alu, 0, sizeof(struct r600_bc_alu));
1137 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1138 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1139 if (r)
1140 return r;
1141
1142 alu.src[0].sel = ctx->temp_reg;
1143 alu.src[0].chan = 0;
1144 alu.last = 1;
1145 r = r600_bc_add_alu(ctx->bc, &alu);
1146 if (r)
1147 return r;
1148 }
1149
1150 /* dst.y = SIN */
1151 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1152 memset(&alu, 0, sizeof(struct r600_bc_alu));
1153 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1154 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1155 if (r)
1156 return r;
1157
1158 alu.src[0].sel = ctx->temp_reg;
1159 alu.src[0].chan = 0;
1160 alu.last = 1;
1161 r = r600_bc_add_alu(ctx->bc, &alu);
1162 if (r)
1163 return r;
1164 }
1165
1166 /* dst.z = 0.0; */
1167 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1168 memset(&alu, 0, sizeof(struct r600_bc_alu));
1169
1170 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1171
1172 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1173 if (r)
1174 return r;
1175
1176 alu.src[0].sel = V_SQ_ALU_SRC_0;
1177 alu.src[0].chan = 0;
1178
1179 alu.last = 1;
1180
1181 r = r600_bc_add_alu(ctx->bc, &alu);
1182 if (r)
1183 return r;
1184
1185 r = r600_bc_add_literal(ctx->bc, ctx->value);
1186 if (r)
1187 return r;
1188 }
1189
1190 /* dst.w = 1.0; */
1191 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1192 memset(&alu, 0, sizeof(struct r600_bc_alu));
1193
1194 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1195
1196 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1197 if (r)
1198 return r;
1199
1200 alu.src[0].sel = V_SQ_ALU_SRC_1;
1201 alu.src[0].chan = 0;
1202
1203 alu.last = 1;
1204
1205 r = r600_bc_add_alu(ctx->bc, &alu);
1206 if (r)
1207 return r;
1208
1209 r = r600_bc_add_literal(ctx->bc, ctx->value);
1210 if (r)
1211 return r;
1212 }
1213
1214 return 0;
1215 }
1216
1217 static int tgsi_kill(struct r600_shader_ctx *ctx)
1218 {
1219 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1220 struct r600_bc_alu alu;
1221 int i, r;
1222
1223 for (i = 0; i < 4; i++) {
1224 memset(&alu, 0, sizeof(struct r600_bc_alu));
1225 alu.inst = ctx->inst_info->r600_opcode;
1226
1227 alu.dst.chan = i;
1228
1229 alu.src[0].sel = V_SQ_ALU_SRC_0;
1230
1231 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1232 alu.src[1].sel = V_SQ_ALU_SRC_1;
1233 alu.src[1].neg = 1;
1234 } else {
1235 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1236 if (r)
1237 return r;
1238 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1239 }
1240 if (i == 3) {
1241 alu.last = 1;
1242 }
1243 r = r600_bc_add_alu(ctx->bc, &alu);
1244 if (r)
1245 return r;
1246 }
1247 r = r600_bc_add_literal(ctx->bc, ctx->value);
1248 if (r)
1249 return r;
1250
1251 /* kill must be last in ALU */
1252 ctx->bc->force_add_cf = 1;
1253 ctx->shader->uses_kill = TRUE;
1254 return 0;
1255 }
1256
1257 static int tgsi_lit(struct r600_shader_ctx *ctx)
1258 {
1259 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1260 struct r600_bc_alu alu;
1261 struct r600_bc_alu_src r600_src[3];
1262 int r;
1263
1264 r = tgsi_split_constant(ctx, r600_src);
1265 if (r)
1266 return r;
1267 r = tgsi_split_literal_constant(ctx, r600_src);
1268 if (r)
1269 return r;
1270
1271 /* dst.x, <- 1.0 */
1272 memset(&alu, 0, sizeof(struct r600_bc_alu));
1273 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1274 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1275 alu.src[0].chan = 0;
1276 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1277 if (r)
1278 return r;
1279 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1280 r = r600_bc_add_alu(ctx->bc, &alu);
1281 if (r)
1282 return r;
1283
1284 /* dst.y = max(src.x, 0.0) */
1285 memset(&alu, 0, sizeof(struct r600_bc_alu));
1286 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1287 alu.src[0] = r600_src[0];
1288 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1289 alu.src[1].chan = 0;
1290 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1291 if (r)
1292 return r;
1293 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1294 r = r600_bc_add_alu(ctx->bc, &alu);
1295 if (r)
1296 return r;
1297
1298 /* dst.w, <- 1.0 */
1299 memset(&alu, 0, sizeof(struct r600_bc_alu));
1300 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1301 alu.src[0].sel = V_SQ_ALU_SRC_1;
1302 alu.src[0].chan = 0;
1303 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1304 if (r)
1305 return r;
1306 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1307 alu.last = 1;
1308 r = r600_bc_add_alu(ctx->bc, &alu);
1309 if (r)
1310 return r;
1311
1312 r = r600_bc_add_literal(ctx->bc, ctx->value);
1313 if (r)
1314 return r;
1315
1316 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1317 {
1318 int chan;
1319 int sel;
1320
1321 /* dst.z = log(src.y) */
1322 memset(&alu, 0, sizeof(struct r600_bc_alu));
1323 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1324 alu.src[0] = r600_src[0];
1325 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1326 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1327 if (r)
1328 return r;
1329 alu.last = 1;
1330 r = r600_bc_add_alu(ctx->bc, &alu);
1331 if (r)
1332 return r;
1333
1334 r = r600_bc_add_literal(ctx->bc, ctx->value);
1335 if (r)
1336 return r;
1337
1338 chan = alu.dst.chan;
1339 sel = alu.dst.sel;
1340
1341 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1342 memset(&alu, 0, sizeof(struct r600_bc_alu));
1343 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1344 alu.src[0] = r600_src[0];
1345 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1346 alu.src[1].sel = sel;
1347 alu.src[1].chan = chan;
1348
1349 alu.src[2] = r600_src[0];
1350 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1351 alu.dst.sel = ctx->temp_reg;
1352 alu.dst.chan = 0;
1353 alu.dst.write = 1;
1354 alu.is_op3 = 1;
1355 alu.last = 1;
1356 r = r600_bc_add_alu(ctx->bc, &alu);
1357 if (r)
1358 return r;
1359
1360 r = r600_bc_add_literal(ctx->bc, ctx->value);
1361 if (r)
1362 return r;
1363 /* dst.z = exp(tmp.x) */
1364 memset(&alu, 0, sizeof(struct r600_bc_alu));
1365 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1366 alu.src[0].sel = ctx->temp_reg;
1367 alu.src[0].chan = 0;
1368 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1369 if (r)
1370 return r;
1371 alu.last = 1;
1372 r = r600_bc_add_alu(ctx->bc, &alu);
1373 if (r)
1374 return r;
1375 }
1376 return 0;
1377 }
1378
1379 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1380 {
1381 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1382 struct r600_bc_alu alu;
1383 int i, r;
1384
1385 memset(&alu, 0, sizeof(struct r600_bc_alu));
1386
1387 /* FIXME:
1388 * For state trackers other than OpenGL, we'll want to use
1389 * _RECIPSQRT_IEEE instead.
1390 */
1391 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1392
1393 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1394 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1395 if (r)
1396 return r;
1397 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1398 alu.src[i].abs = 1;
1399 }
1400 alu.dst.sel = ctx->temp_reg;
1401 alu.dst.write = 1;
1402 alu.last = 1;
1403 r = r600_bc_add_alu(ctx->bc, &alu);
1404 if (r)
1405 return r;
1406 r = r600_bc_add_literal(ctx->bc, ctx->value);
1407 if (r)
1408 return r;
1409 /* replicate result */
1410 return tgsi_helper_tempx_replicate(ctx);
1411 }
1412
1413 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1414 {
1415 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1416 struct r600_bc_alu alu;
1417 int i, r;
1418
1419 for (i = 0; i < 4; i++) {
1420 memset(&alu, 0, sizeof(struct r600_bc_alu));
1421 alu.src[0].sel = ctx->temp_reg;
1422 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1423 alu.dst.chan = i;
1424 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1425 if (r)
1426 return r;
1427 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1428 if (i == 3)
1429 alu.last = 1;
1430 r = r600_bc_add_alu(ctx->bc, &alu);
1431 if (r)
1432 return r;
1433 }
1434 return 0;
1435 }
1436
1437 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1438 {
1439 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1440 struct r600_bc_alu alu;
1441 int i, r;
1442
1443 memset(&alu, 0, sizeof(struct r600_bc_alu));
1444 alu.inst = ctx->inst_info->r600_opcode;
1445 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1446 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1447 if (r)
1448 return r;
1449 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1450 }
1451 alu.dst.sel = ctx->temp_reg;
1452 alu.dst.write = 1;
1453 alu.last = 1;
1454 r = r600_bc_add_alu(ctx->bc, &alu);
1455 if (r)
1456 return r;
1457 r = r600_bc_add_literal(ctx->bc, ctx->value);
1458 if (r)
1459 return r;
1460 /* replicate result */
1461 return tgsi_helper_tempx_replicate(ctx);
1462 }
1463
1464 static int tgsi_pow(struct r600_shader_ctx *ctx)
1465 {
1466 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1467 struct r600_bc_alu alu;
1468 int r;
1469
1470 /* LOG2(a) */
1471 memset(&alu, 0, sizeof(struct r600_bc_alu));
1472 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1473 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1474 if (r)
1475 return r;
1476 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1477 alu.dst.sel = ctx->temp_reg;
1478 alu.dst.write = 1;
1479 alu.last = 1;
1480 r = r600_bc_add_alu(ctx->bc, &alu);
1481 if (r)
1482 return r;
1483 r = r600_bc_add_literal(ctx->bc,ctx->value);
1484 if (r)
1485 return r;
1486 /* b * LOG2(a) */
1487 memset(&alu, 0, sizeof(struct r600_bc_alu));
1488 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE);
1489 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1490 if (r)
1491 return r;
1492 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1493 alu.src[1].sel = ctx->temp_reg;
1494 alu.dst.sel = ctx->temp_reg;
1495 alu.dst.write = 1;
1496 alu.last = 1;
1497 r = r600_bc_add_alu(ctx->bc, &alu);
1498 if (r)
1499 return r;
1500 r = r600_bc_add_literal(ctx->bc,ctx->value);
1501 if (r)
1502 return r;
1503 /* POW(a,b) = EXP2(b * LOG2(a))*/
1504 memset(&alu, 0, sizeof(struct r600_bc_alu));
1505 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1506 alu.src[0].sel = ctx->temp_reg;
1507 alu.dst.sel = ctx->temp_reg;
1508 alu.dst.write = 1;
1509 alu.last = 1;
1510 r = r600_bc_add_alu(ctx->bc, &alu);
1511 if (r)
1512 return r;
1513 r = r600_bc_add_literal(ctx->bc,ctx->value);
1514 if (r)
1515 return r;
1516 return tgsi_helper_tempx_replicate(ctx);
1517 }
1518
1519 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1520 {
1521 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1522 struct r600_bc_alu alu;
1523 struct r600_bc_alu_src r600_src[3];
1524 int i, r;
1525
1526 r = tgsi_split_constant(ctx, r600_src);
1527 if (r)
1528 return r;
1529 r = tgsi_split_literal_constant(ctx, r600_src);
1530 if (r)
1531 return r;
1532
1533 /* tmp = (src > 0 ? 1 : src) */
1534 for (i = 0; i < 4; i++) {
1535 memset(&alu, 0, sizeof(struct r600_bc_alu));
1536 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1537 alu.is_op3 = 1;
1538
1539 alu.dst.sel = ctx->temp_reg;
1540 alu.dst.chan = i;
1541
1542 alu.src[0] = r600_src[0];
1543 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1544
1545 alu.src[1].sel = V_SQ_ALU_SRC_1;
1546
1547 alu.src[2] = r600_src[0];
1548 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1549 if (i == 3)
1550 alu.last = 1;
1551 r = r600_bc_add_alu(ctx->bc, &alu);
1552 if (r)
1553 return r;
1554 }
1555 r = r600_bc_add_literal(ctx->bc, ctx->value);
1556 if (r)
1557 return r;
1558
1559 /* dst = (-tmp > 0 ? -1 : tmp) */
1560 for (i = 0; i < 4; i++) {
1561 memset(&alu, 0, sizeof(struct r600_bc_alu));
1562 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1563 alu.is_op3 = 1;
1564 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1565 if (r)
1566 return r;
1567
1568 alu.src[0].sel = ctx->temp_reg;
1569 alu.src[0].chan = i;
1570 alu.src[0].neg = 1;
1571
1572 alu.src[1].sel = V_SQ_ALU_SRC_1;
1573 alu.src[1].neg = 1;
1574
1575 alu.src[2].sel = ctx->temp_reg;
1576 alu.src[2].chan = i;
1577
1578 if (i == 3)
1579 alu.last = 1;
1580 r = r600_bc_add_alu(ctx->bc, &alu);
1581 if (r)
1582 return r;
1583 }
1584 return 0;
1585 }
1586
1587 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1588 {
1589 struct r600_bc_alu alu;
1590 int i, r;
1591
1592 r = r600_bc_add_literal(ctx->bc, ctx->value);
1593 if (r)
1594 return r;
1595 for (i = 0; i < 4; i++) {
1596 memset(&alu, 0, sizeof(struct r600_bc_alu));
1597 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1598 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1599 alu.dst.chan = i;
1600 } else {
1601 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1602 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1603 if (r)
1604 return r;
1605 alu.src[0].sel = ctx->temp_reg;
1606 alu.src[0].chan = i;
1607 }
1608 if (i == 3) {
1609 alu.last = 1;
1610 }
1611 r = r600_bc_add_alu(ctx->bc, &alu);
1612 if (r)
1613 return r;
1614 }
1615 return 0;
1616 }
1617
1618 static int tgsi_op3(struct r600_shader_ctx *ctx)
1619 {
1620 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1621 struct r600_bc_alu_src r600_src[3];
1622 struct r600_bc_alu alu;
1623 int i, j, r;
1624 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1625
1626 r = tgsi_split_constant(ctx, r600_src);
1627 if (r)
1628 return r;
1629 r = tgsi_split_literal_constant(ctx, r600_src);
1630 if (r)
1631 return r;
1632 for (i = 0; i < lasti + 1; i++) {
1633 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1634 continue;
1635
1636 memset(&alu, 0, sizeof(struct r600_bc_alu));
1637 alu.inst = ctx->inst_info->r600_opcode;
1638 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1639 alu.src[j] = r600_src[j];
1640 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1641 }
1642
1643 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1644 if (r)
1645 return r;
1646
1647 alu.dst.chan = i;
1648 alu.dst.write = 1;
1649 alu.is_op3 = 1;
1650 if (i == lasti) {
1651 alu.last = 1;
1652 }
1653 r = r600_bc_add_alu(ctx->bc, &alu);
1654 if (r)
1655 return r;
1656 }
1657 return 0;
1658 }
1659
1660 static int tgsi_dp(struct r600_shader_ctx *ctx)
1661 {
1662 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1663 struct r600_bc_alu_src r600_src[3];
1664 struct r600_bc_alu alu;
1665 int i, j, r;
1666
1667 r = tgsi_split_constant(ctx, r600_src);
1668 if (r)
1669 return r;
1670 r = tgsi_split_literal_constant(ctx, r600_src);
1671 if (r)
1672 return r;
1673 for (i = 0; i < 4; i++) {
1674 memset(&alu, 0, sizeof(struct r600_bc_alu));
1675 alu.inst = ctx->inst_info->r600_opcode;
1676 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1677 alu.src[j] = r600_src[j];
1678 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1679 }
1680
1681 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1682 if (r)
1683 return r;
1684
1685 alu.dst.chan = i;
1686 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1687 /* handle some special cases */
1688 switch (ctx->inst_info->tgsi_opcode) {
1689 case TGSI_OPCODE_DP2:
1690 if (i > 1) {
1691 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1692 alu.src[0].chan = alu.src[1].chan = 0;
1693 }
1694 break;
1695 case TGSI_OPCODE_DP3:
1696 if (i > 2) {
1697 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1698 alu.src[0].chan = alu.src[1].chan = 0;
1699 }
1700 break;
1701 case TGSI_OPCODE_DPH:
1702 if (i == 3) {
1703 alu.src[0].sel = V_SQ_ALU_SRC_1;
1704 alu.src[0].chan = 0;
1705 alu.src[0].neg = 0;
1706 }
1707 break;
1708 default:
1709 break;
1710 }
1711 if (i == 3) {
1712 alu.last = 1;
1713 }
1714 r = r600_bc_add_alu(ctx->bc, &alu);
1715 if (r)
1716 return r;
1717 }
1718 return 0;
1719 }
1720
1721 static int tgsi_tex(struct r600_shader_ctx *ctx)
1722 {
1723 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1724 struct r600_bc_tex tex;
1725 struct r600_bc_alu alu;
1726 unsigned src_gpr;
1727 int r, i;
1728 int opcode;
1729 boolean src_not_temp =
1730 inst->Src[0].Register.File != TGSI_FILE_TEMPORARY &&
1731 inst->Src[0].Register.File != TGSI_FILE_INPUT;
1732 uint32_t lit_vals[4];
1733
1734 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1735
1736 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1737 /* Add perspective divide */
1738 memset(&alu, 0, sizeof(struct r600_bc_alu));
1739 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1740 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1741 if (r)
1742 return r;
1743
1744 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1745 alu.dst.sel = ctx->temp_reg;
1746 alu.dst.chan = 3;
1747 alu.last = 1;
1748 alu.dst.write = 1;
1749 r = r600_bc_add_alu(ctx->bc, &alu);
1750 if (r)
1751 return r;
1752
1753 for (i = 0; i < 3; i++) {
1754 memset(&alu, 0, sizeof(struct r600_bc_alu));
1755 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1756 alu.src[0].sel = ctx->temp_reg;
1757 alu.src[0].chan = 3;
1758 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1759 if (r)
1760 return r;
1761 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1762 alu.dst.sel = ctx->temp_reg;
1763 alu.dst.chan = i;
1764 alu.dst.write = 1;
1765 r = r600_bc_add_alu(ctx->bc, &alu);
1766 if (r)
1767 return r;
1768 }
1769 memset(&alu, 0, sizeof(struct r600_bc_alu));
1770 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1771 alu.src[0].sel = V_SQ_ALU_SRC_1;
1772 alu.src[0].chan = 0;
1773 alu.dst.sel = ctx->temp_reg;
1774 alu.dst.chan = 3;
1775 alu.last = 1;
1776 alu.dst.write = 1;
1777 r = r600_bc_add_alu(ctx->bc, &alu);
1778 if (r)
1779 return r;
1780 src_not_temp = FALSE;
1781 src_gpr = ctx->temp_reg;
1782 }
1783
1784 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1785 int src_chan, src2_chan;
1786
1787 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1788 for (i = 0; i < 4; i++) {
1789 memset(&alu, 0, sizeof(struct r600_bc_alu));
1790 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1791 switch (i) {
1792 case 0:
1793 src_chan = 2;
1794 src2_chan = 1;
1795 break;
1796 case 1:
1797 src_chan = 2;
1798 src2_chan = 0;
1799 break;
1800 case 2:
1801 src_chan = 0;
1802 src2_chan = 2;
1803 break;
1804 case 3:
1805 src_chan = 1;
1806 src2_chan = 2;
1807 break;
1808 default:
1809 assert(0);
1810 src_chan = 0;
1811 src2_chan = 0;
1812 break;
1813 }
1814 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1815 if (r)
1816 return r;
1817 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1818 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1819 if (r)
1820 return r;
1821 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1822 alu.dst.sel = ctx->temp_reg;
1823 alu.dst.chan = i;
1824 if (i == 3)
1825 alu.last = 1;
1826 alu.dst.write = 1;
1827 r = r600_bc_add_alu(ctx->bc, &alu);
1828 if (r)
1829 return r;
1830 }
1831
1832 /* tmp1.z = RCP_e(|tmp1.z|) */
1833 memset(&alu, 0, sizeof(struct r600_bc_alu));
1834 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1835 alu.src[0].sel = ctx->temp_reg;
1836 alu.src[0].chan = 2;
1837 alu.src[0].abs = 1;
1838 alu.dst.sel = ctx->temp_reg;
1839 alu.dst.chan = 2;
1840 alu.dst.write = 1;
1841 alu.last = 1;
1842 r = r600_bc_add_alu(ctx->bc, &alu);
1843 if (r)
1844 return r;
1845
1846 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1847 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1848 * muladd has no writemask, have to use another temp
1849 */
1850 memset(&alu, 0, sizeof(struct r600_bc_alu));
1851 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1852 alu.is_op3 = 1;
1853
1854 alu.src[0].sel = ctx->temp_reg;
1855 alu.src[0].chan = 0;
1856 alu.src[1].sel = ctx->temp_reg;
1857 alu.src[1].chan = 2;
1858
1859 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1860 alu.src[2].chan = 0;
1861
1862 alu.dst.sel = ctx->temp_reg;
1863 alu.dst.chan = 0;
1864 alu.dst.write = 1;
1865
1866 r = r600_bc_add_alu(ctx->bc, &alu);
1867 if (r)
1868 return r;
1869
1870 memset(&alu, 0, sizeof(struct r600_bc_alu));
1871 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1872 alu.is_op3 = 1;
1873
1874 alu.src[0].sel = ctx->temp_reg;
1875 alu.src[0].chan = 1;
1876 alu.src[1].sel = ctx->temp_reg;
1877 alu.src[1].chan = 2;
1878
1879 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1880 alu.src[2].chan = 0;
1881
1882 alu.dst.sel = ctx->temp_reg;
1883 alu.dst.chan = 1;
1884 alu.dst.write = 1;
1885
1886 alu.last = 1;
1887 r = r600_bc_add_alu(ctx->bc, &alu);
1888 if (r)
1889 return r;
1890
1891 lit_vals[0] = fui(1.5f);
1892
1893 r = r600_bc_add_literal(ctx->bc, lit_vals);
1894 if (r)
1895 return r;
1896 src_not_temp = FALSE;
1897 src_gpr = ctx->temp_reg;
1898 }
1899
1900 if (src_not_temp) {
1901 for (i = 0; i < 4; i++) {
1902 memset(&alu, 0, sizeof(struct r600_bc_alu));
1903 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1904 alu.src[0].sel = src_gpr;
1905 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1906 alu.dst.sel = ctx->temp_reg;
1907 alu.dst.chan = i;
1908 if (i == 3)
1909 alu.last = 1;
1910 alu.dst.write = 1;
1911 r = r600_bc_add_alu(ctx->bc, &alu);
1912 if (r)
1913 return r;
1914 }
1915 src_gpr = ctx->temp_reg;
1916 }
1917
1918 opcode = ctx->inst_info->r600_opcode;
1919 if (opcode == SQ_TEX_INST_SAMPLE &&
1920 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1921 opcode = SQ_TEX_INST_SAMPLE_C;
1922
1923 memset(&tex, 0, sizeof(struct r600_bc_tex));
1924 tex.inst = opcode;
1925 tex.sampler_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1926 tex.resource_id = tex.sampler_id;
1927 tex.src_gpr = src_gpr;
1928 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1929 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
1930 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
1931 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
1932 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
1933 tex.src_sel_x = 0;
1934 tex.src_sel_y = 1;
1935 tex.src_sel_z = 2;
1936 tex.src_sel_w = 3;
1937
1938 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1939 tex.src_sel_x = 1;
1940 tex.src_sel_y = 0;
1941 tex.src_sel_z = 3;
1942 tex.src_sel_w = 1;
1943 }
1944
1945 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1946 tex.coord_type_x = 1;
1947 tex.coord_type_y = 1;
1948 tex.coord_type_z = 1;
1949 tex.coord_type_w = 1;
1950 }
1951
1952 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1953 tex.src_sel_w = 2;
1954
1955 r = r600_bc_add_tex(ctx->bc, &tex);
1956 if (r)
1957 return r;
1958
1959 /* add shadow ambient support - gallium doesn't do it yet */
1960 return 0;
1961 }
1962
1963 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1964 {
1965 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1966 struct r600_bc_alu_src r600_src[3];
1967 struct r600_bc_alu alu;
1968 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1969 unsigned i;
1970 int r;
1971
1972 r = tgsi_split_constant(ctx, r600_src);
1973 if (r)
1974 return r;
1975 r = tgsi_split_literal_constant(ctx, r600_src);
1976 if (r)
1977 return r;
1978 /* 1 - src0 */
1979 for (i = 0; i < lasti + 1; i++) {
1980 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1981 continue;
1982
1983 memset(&alu, 0, sizeof(struct r600_bc_alu));
1984 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1985 alu.src[0].sel = V_SQ_ALU_SRC_1;
1986 alu.src[0].chan = 0;
1987 alu.src[1] = r600_src[0];
1988 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1989 alu.src[1].neg = 1;
1990 alu.dst.sel = ctx->temp_reg;
1991 alu.dst.chan = i;
1992 if (i == lasti) {
1993 alu.last = 1;
1994 }
1995 alu.dst.write = 1;
1996 r = r600_bc_add_alu(ctx->bc, &alu);
1997 if (r)
1998 return r;
1999 }
2000 r = r600_bc_add_literal(ctx->bc, ctx->value);
2001 if (r)
2002 return r;
2003
2004 /* (1 - src0) * src2 */
2005 for (i = 0; i < lasti + 1; i++) {
2006 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2007 continue;
2008
2009 memset(&alu, 0, sizeof(struct r600_bc_alu));
2010 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2011 alu.src[0].sel = ctx->temp_reg;
2012 alu.src[0].chan = i;
2013 alu.src[1] = r600_src[2];
2014 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
2015 alu.dst.sel = ctx->temp_reg;
2016 alu.dst.chan = i;
2017 if (i == lasti) {
2018 alu.last = 1;
2019 }
2020 alu.dst.write = 1;
2021 r = r600_bc_add_alu(ctx->bc, &alu);
2022 if (r)
2023 return r;
2024 }
2025 r = r600_bc_add_literal(ctx->bc, ctx->value);
2026 if (r)
2027 return r;
2028
2029 /* src0 * src1 + (1 - src0) * src2 */
2030 for (i = 0; i < lasti + 1; i++) {
2031 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2032 continue;
2033
2034 memset(&alu, 0, sizeof(struct r600_bc_alu));
2035 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2036 alu.is_op3 = 1;
2037 alu.src[0] = r600_src[0];
2038 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2039 alu.src[1] = r600_src[1];
2040 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2041 alu.src[2].sel = ctx->temp_reg;
2042 alu.src[2].chan = i;
2043
2044 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2045 if (r)
2046 return r;
2047
2048 alu.dst.chan = i;
2049 if (i == lasti) {
2050 alu.last = 1;
2051 }
2052 r = r600_bc_add_alu(ctx->bc, &alu);
2053 if (r)
2054 return r;
2055 }
2056 return 0;
2057 }
2058
2059 static int tgsi_cmp(struct r600_shader_ctx *ctx)
2060 {
2061 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2062 struct r600_bc_alu_src r600_src[3];
2063 struct r600_bc_alu alu;
2064 int i, r;
2065 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2066
2067 r = tgsi_split_constant(ctx, r600_src);
2068 if (r)
2069 return r;
2070 r = tgsi_split_literal_constant(ctx, r600_src);
2071 if (r)
2072 return r;
2073
2074 for (i = 0; i < lasti + 1; i++) {
2075 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2076 continue;
2077
2078 memset(&alu, 0, sizeof(struct r600_bc_alu));
2079 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
2080 alu.src[0] = r600_src[0];
2081 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2082
2083 alu.src[1] = r600_src[2];
2084 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
2085
2086 alu.src[2] = r600_src[1];
2087 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
2088
2089 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2090 if (r)
2091 return r;
2092
2093 alu.dst.chan = i;
2094 alu.dst.write = 1;
2095 alu.is_op3 = 1;
2096 if (i == lasti)
2097 alu.last = 1;
2098 r = r600_bc_add_alu(ctx->bc, &alu);
2099 if (r)
2100 return r;
2101 }
2102 return 0;
2103 }
2104
2105 static int tgsi_xpd(struct r600_shader_ctx *ctx)
2106 {
2107 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2108 struct r600_bc_alu_src r600_src[3];
2109 struct r600_bc_alu alu;
2110 uint32_t use_temp = 0;
2111 int i, r;
2112
2113 if (inst->Dst[0].Register.WriteMask != 0xf)
2114 use_temp = 1;
2115
2116 r = tgsi_split_constant(ctx, r600_src);
2117 if (r)
2118 return r;
2119 r = tgsi_split_literal_constant(ctx, r600_src);
2120 if (r)
2121 return r;
2122
2123 for (i = 0; i < 4; i++) {
2124 memset(&alu, 0, sizeof(struct r600_bc_alu));
2125 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2126
2127 alu.src[0] = r600_src[0];
2128 switch (i) {
2129 case 0:
2130 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2131 break;
2132 case 1:
2133 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2134 break;
2135 case 2:
2136 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2137 break;
2138 case 3:
2139 alu.src[0].sel = V_SQ_ALU_SRC_0;
2140 alu.src[0].chan = i;
2141 }
2142
2143 alu.src[1] = r600_src[1];
2144 switch (i) {
2145 case 0:
2146 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2147 break;
2148 case 1:
2149 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2150 break;
2151 case 2:
2152 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2153 break;
2154 case 3:
2155 alu.src[1].sel = V_SQ_ALU_SRC_0;
2156 alu.src[1].chan = i;
2157 }
2158
2159 alu.dst.sel = ctx->temp_reg;
2160 alu.dst.chan = i;
2161 alu.dst.write = 1;
2162
2163 if (i == 3)
2164 alu.last = 1;
2165 r = r600_bc_add_alu(ctx->bc, &alu);
2166 if (r)
2167 return r;
2168
2169 r = r600_bc_add_literal(ctx->bc, ctx->value);
2170 if (r)
2171 return r;
2172 }
2173
2174 for (i = 0; i < 4; i++) {
2175 memset(&alu, 0, sizeof(struct r600_bc_alu));
2176 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2177
2178 alu.src[0] = r600_src[0];
2179 switch (i) {
2180 case 0:
2181 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2182 break;
2183 case 1:
2184 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2185 break;
2186 case 2:
2187 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2188 break;
2189 case 3:
2190 alu.src[0].sel = V_SQ_ALU_SRC_0;
2191 alu.src[0].chan = i;
2192 }
2193
2194 alu.src[1] = r600_src[1];
2195 switch (i) {
2196 case 0:
2197 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2198 break;
2199 case 1:
2200 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2201 break;
2202 case 2:
2203 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2204 break;
2205 case 3:
2206 alu.src[1].sel = V_SQ_ALU_SRC_0;
2207 alu.src[1].chan = i;
2208 }
2209
2210 alu.src[2].sel = ctx->temp_reg;
2211 alu.src[2].neg = 1;
2212 alu.src[2].chan = i;
2213
2214 if (use_temp)
2215 alu.dst.sel = ctx->temp_reg;
2216 else {
2217 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2218 if (r)
2219 return r;
2220 }
2221 alu.dst.chan = i;
2222 alu.dst.write = 1;
2223 alu.is_op3 = 1;
2224 if (i == 3)
2225 alu.last = 1;
2226 r = r600_bc_add_alu(ctx->bc, &alu);
2227 if (r)
2228 return r;
2229
2230 r = r600_bc_add_literal(ctx->bc, ctx->value);
2231 if (r)
2232 return r;
2233 }
2234 if (use_temp)
2235 return tgsi_helper_copy(ctx, inst);
2236 return 0;
2237 }
2238
2239 static int tgsi_exp(struct r600_shader_ctx *ctx)
2240 {
2241 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2242 struct r600_bc_alu_src r600_src[3] = { { 0 } };
2243 struct r600_bc_alu alu;
2244 int r;
2245
2246 /* result.x = 2^floor(src); */
2247 if (inst->Dst[0].Register.WriteMask & 1) {
2248 memset(&alu, 0, sizeof(struct r600_bc_alu));
2249
2250 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2251 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2252 if (r)
2253 return r;
2254
2255 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2256
2257 alu.dst.sel = ctx->temp_reg;
2258 alu.dst.chan = 0;
2259 alu.dst.write = 1;
2260 alu.last = 1;
2261 r = r600_bc_add_alu(ctx->bc, &alu);
2262 if (r)
2263 return r;
2264
2265 r = r600_bc_add_literal(ctx->bc, ctx->value);
2266 if (r)
2267 return r;
2268
2269 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2270 alu.src[0].sel = ctx->temp_reg;
2271 alu.src[0].chan = 0;
2272
2273 alu.dst.sel = ctx->temp_reg;
2274 alu.dst.chan = 0;
2275 alu.dst.write = 1;
2276 alu.last = 1;
2277 r = r600_bc_add_alu(ctx->bc, &alu);
2278 if (r)
2279 return r;
2280
2281 r = r600_bc_add_literal(ctx->bc, ctx->value);
2282 if (r)
2283 return r;
2284 }
2285
2286 /* result.y = tmp - floor(tmp); */
2287 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2288 memset(&alu, 0, sizeof(struct r600_bc_alu));
2289
2290 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2291 alu.src[0] = r600_src[0];
2292 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2293 if (r)
2294 return r;
2295 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2296
2297 alu.dst.sel = ctx->temp_reg;
2298 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2299 // if (r)
2300 // return r;
2301 alu.dst.write = 1;
2302 alu.dst.chan = 1;
2303
2304 alu.last = 1;
2305
2306 r = r600_bc_add_alu(ctx->bc, &alu);
2307 if (r)
2308 return r;
2309 r = r600_bc_add_literal(ctx->bc, ctx->value);
2310 if (r)
2311 return r;
2312 }
2313
2314 /* result.z = RoughApprox2ToX(tmp);*/
2315 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2316 memset(&alu, 0, sizeof(struct r600_bc_alu));
2317 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2318 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2319 if (r)
2320 return r;
2321 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2322
2323 alu.dst.sel = ctx->temp_reg;
2324 alu.dst.write = 1;
2325 alu.dst.chan = 2;
2326
2327 alu.last = 1;
2328
2329 r = r600_bc_add_alu(ctx->bc, &alu);
2330 if (r)
2331 return r;
2332 r = r600_bc_add_literal(ctx->bc, ctx->value);
2333 if (r)
2334 return r;
2335 }
2336
2337 /* result.w = 1.0;*/
2338 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2339 memset(&alu, 0, sizeof(struct r600_bc_alu));
2340
2341 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2342 alu.src[0].sel = V_SQ_ALU_SRC_1;
2343 alu.src[0].chan = 0;
2344
2345 alu.dst.sel = ctx->temp_reg;
2346 alu.dst.chan = 3;
2347 alu.dst.write = 1;
2348 alu.last = 1;
2349 r = r600_bc_add_alu(ctx->bc, &alu);
2350 if (r)
2351 return r;
2352 r = r600_bc_add_literal(ctx->bc, ctx->value);
2353 if (r)
2354 return r;
2355 }
2356 return tgsi_helper_copy(ctx, inst);
2357 }
2358
2359 static int tgsi_log(struct r600_shader_ctx *ctx)
2360 {
2361 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2362 struct r600_bc_alu alu;
2363 int r;
2364
2365 /* result.x = floor(log2(src)); */
2366 if (inst->Dst[0].Register.WriteMask & 1) {
2367 memset(&alu, 0, sizeof(struct r600_bc_alu));
2368
2369 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2370 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2371 if (r)
2372 return r;
2373
2374 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2375
2376 alu.dst.sel = ctx->temp_reg;
2377 alu.dst.chan = 0;
2378 alu.dst.write = 1;
2379 alu.last = 1;
2380 r = r600_bc_add_alu(ctx->bc, &alu);
2381 if (r)
2382 return r;
2383
2384 r = r600_bc_add_literal(ctx->bc, ctx->value);
2385 if (r)
2386 return r;
2387
2388 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2389 alu.src[0].sel = ctx->temp_reg;
2390 alu.src[0].chan = 0;
2391
2392 alu.dst.sel = ctx->temp_reg;
2393 alu.dst.chan = 0;
2394 alu.dst.write = 1;
2395 alu.last = 1;
2396
2397 r = r600_bc_add_alu(ctx->bc, &alu);
2398 if (r)
2399 return r;
2400
2401 r = r600_bc_add_literal(ctx->bc, ctx->value);
2402 if (r)
2403 return r;
2404 }
2405
2406 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2407 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2408 memset(&alu, 0, sizeof(struct r600_bc_alu));
2409
2410 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2411 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2412 if (r)
2413 return r;
2414
2415 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2416
2417 alu.dst.sel = ctx->temp_reg;
2418 alu.dst.chan = 1;
2419 alu.dst.write = 1;
2420 alu.last = 1;
2421
2422 r = r600_bc_add_alu(ctx->bc, &alu);
2423 if (r)
2424 return r;
2425
2426 r = r600_bc_add_literal(ctx->bc, ctx->value);
2427 if (r)
2428 return r;
2429
2430 memset(&alu, 0, sizeof(struct r600_bc_alu));
2431
2432 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2433 alu.src[0].sel = ctx->temp_reg;
2434 alu.src[0].chan = 1;
2435
2436 alu.dst.sel = ctx->temp_reg;
2437 alu.dst.chan = 1;
2438 alu.dst.write = 1;
2439 alu.last = 1;
2440
2441 r = r600_bc_add_alu(ctx->bc, &alu);
2442 if (r)
2443 return r;
2444
2445 r = r600_bc_add_literal(ctx->bc, ctx->value);
2446 if (r)
2447 return r;
2448
2449 memset(&alu, 0, sizeof(struct r600_bc_alu));
2450
2451 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2452 alu.src[0].sel = ctx->temp_reg;
2453 alu.src[0].chan = 1;
2454
2455 alu.dst.sel = ctx->temp_reg;
2456 alu.dst.chan = 1;
2457 alu.dst.write = 1;
2458 alu.last = 1;
2459
2460 r = r600_bc_add_alu(ctx->bc, &alu);
2461 if (r)
2462 return r;
2463
2464 r = r600_bc_add_literal(ctx->bc, ctx->value);
2465 if (r)
2466 return r;
2467
2468 memset(&alu, 0, sizeof(struct r600_bc_alu));
2469
2470 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2471 alu.src[0].sel = ctx->temp_reg;
2472 alu.src[0].chan = 1;
2473
2474 alu.dst.sel = ctx->temp_reg;
2475 alu.dst.chan = 1;
2476 alu.dst.write = 1;
2477 alu.last = 1;
2478
2479 r = r600_bc_add_alu(ctx->bc, &alu);
2480 if (r)
2481 return r;
2482
2483 r = r600_bc_add_literal(ctx->bc, ctx->value);
2484 if (r)
2485 return r;
2486
2487 memset(&alu, 0, sizeof(struct r600_bc_alu));
2488
2489 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2490
2491 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2492 if (r)
2493 return r;
2494
2495 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2496
2497 alu.src[1].sel = ctx->temp_reg;
2498 alu.src[1].chan = 1;
2499
2500 alu.dst.sel = ctx->temp_reg;
2501 alu.dst.chan = 1;
2502 alu.dst.write = 1;
2503 alu.last = 1;
2504
2505 r = r600_bc_add_alu(ctx->bc, &alu);
2506 if (r)
2507 return r;
2508
2509 r = r600_bc_add_literal(ctx->bc, ctx->value);
2510 if (r)
2511 return r;
2512 }
2513
2514 /* result.z = log2(src);*/
2515 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2516 memset(&alu, 0, sizeof(struct r600_bc_alu));
2517
2518 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2519 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2520 if (r)
2521 return r;
2522
2523 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2524
2525 alu.dst.sel = ctx->temp_reg;
2526 alu.dst.write = 1;
2527 alu.dst.chan = 2;
2528 alu.last = 1;
2529
2530 r = r600_bc_add_alu(ctx->bc, &alu);
2531 if (r)
2532 return r;
2533
2534 r = r600_bc_add_literal(ctx->bc, ctx->value);
2535 if (r)
2536 return r;
2537 }
2538
2539 /* result.w = 1.0; */
2540 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2541 memset(&alu, 0, sizeof(struct r600_bc_alu));
2542
2543 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2544 alu.src[0].sel = V_SQ_ALU_SRC_1;
2545 alu.src[0].chan = 0;
2546
2547 alu.dst.sel = ctx->temp_reg;
2548 alu.dst.chan = 3;
2549 alu.dst.write = 1;
2550 alu.last = 1;
2551
2552 r = r600_bc_add_alu(ctx->bc, &alu);
2553 if (r)
2554 return r;
2555
2556 r = r600_bc_add_literal(ctx->bc, ctx->value);
2557 if (r)
2558 return r;
2559 }
2560
2561 return tgsi_helper_copy(ctx, inst);
2562 }
2563
2564 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
2565 {
2566 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2567 struct r600_bc_alu alu;
2568 int r;
2569 memset(&alu, 0, sizeof(struct r600_bc_alu));
2570
2571 switch (inst->Instruction.Opcode) {
2572 case TGSI_OPCODE_ARL:
2573 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
2574 break;
2575 case TGSI_OPCODE_ARR:
2576 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
2577 break;
2578 default:
2579 assert(0);
2580 return -1;
2581 }
2582
2583 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2584 if (r)
2585 return r;
2586 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2587 alu.last = 1;
2588 alu.dst.chan = 0;
2589 alu.dst.sel = ctx->temp_reg;
2590 alu.dst.write = 1;
2591 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2592 if (r)
2593 return r;
2594 memset(&alu, 0, sizeof(struct r600_bc_alu));
2595 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT;
2596 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2597 if (r)
2598 return r;
2599 alu.src[0].sel = ctx->temp_reg;
2600 alu.src[0].chan = 0;
2601 alu.last = 1;
2602 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2603 if (r)
2604 return r;
2605 return 0;
2606 }
2607 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
2608 {
2609 /* TODO from r600c, ar values don't persist between clauses */
2610 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2611 struct r600_bc_alu alu;
2612 int r;
2613 memset(&alu, 0, sizeof(struct r600_bc_alu));
2614
2615 switch (inst->Instruction.Opcode) {
2616 case TGSI_OPCODE_ARL:
2617 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2618 break;
2619 case TGSI_OPCODE_ARR:
2620 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA;
2621 break;
2622 default:
2623 assert(0);
2624 return -1;
2625 }
2626
2627
2628 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2629 if (r)
2630 return r;
2631 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2632
2633 alu.last = 1;
2634
2635 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2636 if (r)
2637 return r;
2638 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2639 return 0;
2640 }
2641
2642 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2643 {
2644 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2645 struct r600_bc_alu alu;
2646 int i, r = 0;
2647
2648 for (i = 0; i < 4; i++) {
2649 memset(&alu, 0, sizeof(struct r600_bc_alu));
2650
2651 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2652 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2653 if (r)
2654 return r;
2655
2656 if (i == 0 || i == 3) {
2657 alu.src[0].sel = V_SQ_ALU_SRC_1;
2658 } else {
2659 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2660 if (r)
2661 return r;
2662 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2663 }
2664
2665 if (i == 0 || i == 2) {
2666 alu.src[1].sel = V_SQ_ALU_SRC_1;
2667 } else {
2668 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2669 if (r)
2670 return r;
2671 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2672 }
2673 if (i == 3)
2674 alu.last = 1;
2675 r = r600_bc_add_alu(ctx->bc, &alu);
2676 if (r)
2677 return r;
2678 }
2679 return 0;
2680 }
2681
2682 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2683 {
2684 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2685 struct r600_bc_alu alu;
2686 int r;
2687
2688 memset(&alu, 0, sizeof(struct r600_bc_alu));
2689 alu.inst = opcode;
2690 alu.predicate = 1;
2691
2692 alu.dst.sel = ctx->temp_reg;
2693 alu.dst.write = 1;
2694 alu.dst.chan = 0;
2695
2696 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2697 if (r)
2698 return r;
2699 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2700 alu.src[1].sel = V_SQ_ALU_SRC_0;
2701 alu.src[1].chan = 0;
2702
2703 alu.last = 1;
2704
2705 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2706 if (r)
2707 return r;
2708 return 0;
2709 }
2710
2711 static int pops(struct r600_shader_ctx *ctx, int pops)
2712 {
2713 int alu_pop = 3;
2714 if (ctx->bc->cf_last) {
2715 if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) << 3)
2716 alu_pop = 0;
2717 else if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER) << 3)
2718 alu_pop = 1;
2719 }
2720 alu_pop += pops;
2721 if (alu_pop == 1) {
2722 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER) << 3;
2723 ctx->bc->force_add_cf = 1;
2724 } else if (alu_pop == 2) {
2725 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER) << 3;
2726 ctx->bc->force_add_cf = 1;
2727 } else {
2728 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2729 ctx->bc->cf_last->pop_count = pops;
2730 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
2731 }
2732 return 0;
2733 }
2734
2735 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2736 {
2737 switch(reason) {
2738 case FC_PUSH_VPM:
2739 ctx->bc->callstack[ctx->bc->call_sp].current--;
2740 break;
2741 case FC_PUSH_WQM:
2742 case FC_LOOP:
2743 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2744 break;
2745 case FC_REP:
2746 /* TOODO : for 16 vp asic should -= 2; */
2747 ctx->bc->callstack[ctx->bc->call_sp].current --;
2748 break;
2749 }
2750 }
2751
2752 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2753 {
2754 if (check_max_only) {
2755 int diff;
2756 switch (reason) {
2757 case FC_PUSH_VPM:
2758 diff = 1;
2759 break;
2760 case FC_PUSH_WQM:
2761 diff = 4;
2762 break;
2763 default:
2764 assert(0);
2765 diff = 0;
2766 }
2767 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2768 ctx->bc->callstack[ctx->bc->call_sp].max) {
2769 ctx->bc->callstack[ctx->bc->call_sp].max =
2770 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2771 }
2772 return;
2773 }
2774 switch (reason) {
2775 case FC_PUSH_VPM:
2776 ctx->bc->callstack[ctx->bc->call_sp].current++;
2777 break;
2778 case FC_PUSH_WQM:
2779 case FC_LOOP:
2780 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2781 break;
2782 case FC_REP:
2783 ctx->bc->callstack[ctx->bc->call_sp].current++;
2784 break;
2785 }
2786
2787 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2788 ctx->bc->callstack[ctx->bc->call_sp].max) {
2789 ctx->bc->callstack[ctx->bc->call_sp].max =
2790 ctx->bc->callstack[ctx->bc->call_sp].current;
2791 }
2792 }
2793
2794 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2795 {
2796 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2797
2798 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2799 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2800 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2801 sp->num_mid++;
2802 }
2803
2804 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2805 {
2806 ctx->bc->fc_sp++;
2807 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2808 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2809 }
2810
2811 static void fc_poplevel(struct r600_shader_ctx *ctx)
2812 {
2813 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2814 if (sp->mid) {
2815 free(sp->mid);
2816 sp->mid = NULL;
2817 }
2818 sp->num_mid = 0;
2819 sp->start = NULL;
2820 sp->type = 0;
2821 ctx->bc->fc_sp--;
2822 }
2823
2824 #if 0
2825 static int emit_return(struct r600_shader_ctx *ctx)
2826 {
2827 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2828 return 0;
2829 }
2830
2831 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2832 {
2833
2834 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2835 ctx->bc->cf_last->pop_count = pops;
2836 /* TODO work out offset */
2837 return 0;
2838 }
2839
2840 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2841 {
2842 return 0;
2843 }
2844
2845 static void emit_testflag(struct r600_shader_ctx *ctx)
2846 {
2847
2848 }
2849
2850 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2851 {
2852 emit_testflag(ctx);
2853 emit_jump_to_offset(ctx, 1, 4);
2854 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2855 pops(ctx, ifidx + 1);
2856 emit_return(ctx);
2857 }
2858
2859 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2860 {
2861 emit_testflag(ctx);
2862
2863 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2864 ctx->bc->cf_last->pop_count = 1;
2865
2866 fc_set_mid(ctx, fc_sp);
2867
2868 pops(ctx, 1);
2869 }
2870 #endif
2871
2872 static int tgsi_if(struct r600_shader_ctx *ctx)
2873 {
2874 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2875
2876 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2877
2878 fc_pushlevel(ctx, FC_IF);
2879
2880 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2881 return 0;
2882 }
2883
2884 static int tgsi_else(struct r600_shader_ctx *ctx)
2885 {
2886 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2887 ctx->bc->cf_last->pop_count = 1;
2888
2889 fc_set_mid(ctx, ctx->bc->fc_sp);
2890 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2891 return 0;
2892 }
2893
2894 static int tgsi_endif(struct r600_shader_ctx *ctx)
2895 {
2896 pops(ctx, 1);
2897 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2898 R600_ERR("if/endif unbalanced in shader\n");
2899 return -1;
2900 }
2901
2902 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2903 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2904 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2905 } else {
2906 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2907 }
2908 fc_poplevel(ctx);
2909
2910 callstack_decrease_current(ctx, FC_PUSH_VPM);
2911 return 0;
2912 }
2913
2914 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2915 {
2916 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2917
2918 fc_pushlevel(ctx, FC_LOOP);
2919
2920 /* check stack depth */
2921 callstack_check_depth(ctx, FC_LOOP, 0);
2922 return 0;
2923 }
2924
2925 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2926 {
2927 int i;
2928
2929 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2930
2931 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2932 R600_ERR("loop/endloop in shader code are not paired.\n");
2933 return -EINVAL;
2934 }
2935
2936 /* fixup loop pointers - from r600isa
2937 LOOP END points to CF after LOOP START,
2938 LOOP START point to CF after LOOP END
2939 BRK/CONT point to LOOP END CF
2940 */
2941 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2942
2943 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2944
2945 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2946 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2947 }
2948 /* TODO add LOOPRET support */
2949 fc_poplevel(ctx);
2950 callstack_decrease_current(ctx, FC_LOOP);
2951 return 0;
2952 }
2953
2954 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2955 {
2956 unsigned int fscp;
2957
2958 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2959 {
2960 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2961 break;
2962 }
2963
2964 if (fscp == 0) {
2965 R600_ERR("Break not inside loop/endloop pair\n");
2966 return -EINVAL;
2967 }
2968
2969 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2970 ctx->bc->cf_last->pop_count = 1;
2971
2972 fc_set_mid(ctx, fscp);
2973
2974 pops(ctx, 1);
2975 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2976 return 0;
2977 }
2978
2979 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2980 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2981 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2982 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2983
2984 /* FIXME:
2985 * For state trackers other than OpenGL, we'll want to use
2986 * _RECIP_IEEE instead.
2987 */
2988 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2989
2990 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2991 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2992 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2993 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2994 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2995 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2996 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2997 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2998 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2999 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
3000 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
3001 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
3002 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
3003 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3004 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
3005 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3006 /* gap */
3007 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3008 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3009 /* gap */
3010 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3011 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3012 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3013 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3014 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3015 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3016 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3017 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3018 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3019 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3020 /* gap */
3021 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3022 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3023 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3024 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3025 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3026 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3027 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3028 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3029 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3030 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3031 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3032 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3033 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3034 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3035 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3036 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3037 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3038 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3039 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3040 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3041 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3042 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3043 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3044 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3045 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3046 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3047 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3048 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3049 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3050 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
3051 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3052 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3053 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3054 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3055 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3056 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3057 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3058 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3059 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3060 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3061 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3062 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3063 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3064 /* gap */
3065 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3066 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3067 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3068 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3069 /* gap */
3070 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3071 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3072 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3073 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3074 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3075 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3076 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3077 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3078 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3079 /* gap */
3080 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3081 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3082 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3083 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3084 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3085 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3086 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3087 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3088 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3089 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3090 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3091 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3092 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3093 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3094 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3095 /* gap */
3096 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3097 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3098 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3099 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3100 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3101 /* gap */
3102 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3103 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3104 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3105 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3106 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3107 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3108 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3109 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3110 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3111 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3112 /* gap */
3113 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3114 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3115 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3116 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3117 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3118 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3119 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3120 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3121 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3122 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3123 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3124 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3125 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3126 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3127 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3128 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3129 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3130 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3131 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3132 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3133 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3134 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3135 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3136 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3137 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3138 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3139 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3140 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3141 };
3142
3143 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
3144 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3145 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3146 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
3147 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
3148 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
3149 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
3150 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3151 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
3152 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3153 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3154 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3155 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
3156 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
3157 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
3158 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
3159 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
3160 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
3161 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3162 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
3163 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3164 /* gap */
3165 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3166 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3167 /* gap */
3168 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3169 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3170 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3171 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3172 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3173 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3174 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3175 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3176 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3177 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3178 /* gap */
3179 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3180 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3181 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3182 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3183 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3184 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3185 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3186 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3187 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3188 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3189 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3190 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3191 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3192 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3193 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3194 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3195 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3196 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3197 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3198 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3199 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3200 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3201 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3202 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3203 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3204 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3205 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3206 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3207 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3208 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3209 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3210 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3211 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3212 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3213 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3214 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3215 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3216 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3217 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3218 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3219 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3220 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3221 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3222 /* gap */
3223 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3224 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3225 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3226 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3227 /* gap */
3228 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3229 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3230 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3231 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3232 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3233 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3234 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3235 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3236 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3237 /* gap */
3238 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3239 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3240 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3241 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3242 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3243 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3244 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3245 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3246 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3247 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3248 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3249 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3250 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3251 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3252 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3253 /* gap */
3254 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3255 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3256 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3257 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3258 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3259 /* gap */
3260 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3261 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3262 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3263 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3264 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3265 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3266 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3267 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3268 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3269 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3270 /* gap */
3271 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3272 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3273 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3274 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3275 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3276 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3277 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3278 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3279 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3280 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3281 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3282 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3283 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3284 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3285 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3286 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3287 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3288 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3289 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3290 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3291 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3292 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3293 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3294 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3295 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3296 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3297 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3298 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3299 };