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r600/sb: disable SB for images.
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
193
194 /* disable SB for shaders using doubles */
195 use_sb &= !shader->shader.uses_doubles;
196
197 use_sb &= !shader->shader.uses_atomics;
198 use_sb &= !shader->shader.uses_images;
199
200 /* Check if the bytecode has already been built. */
201 if (!shader->shader.bc.bytecode) {
202 r = r600_bytecode_build(&shader->shader.bc);
203 if (r) {
204 R600_ERR("building bytecode failed !\n");
205 goto error;
206 }
207 }
208
209 if (dump && !sb_disasm) {
210 fprintf(stderr, "--------------------------------------------------------------\n");
211 r600_bytecode_disasm(&shader->shader.bc);
212 fprintf(stderr, "______________________________________________________________\n");
213 } else if ((dump && sb_disasm) || use_sb) {
214 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
215 dump, use_sb);
216 if (r) {
217 R600_ERR("r600_sb_bytecode_process failed !\n");
218 goto error;
219 }
220 }
221
222 if (shader->gs_copy_shader) {
223 if (dump) {
224 // dump copy shader
225 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
226 &shader->gs_copy_shader->shader, dump, 0);
227 if (r)
228 goto error;
229 }
230
231 if ((r = store_shader(ctx, shader->gs_copy_shader)))
232 goto error;
233 }
234
235 /* Store the shader in a buffer. */
236 if ((r = store_shader(ctx, shader)))
237 goto error;
238
239 /* Build state. */
240 switch (shader->shader.processor_type) {
241 case PIPE_SHADER_TESS_CTRL:
242 evergreen_update_hs_state(ctx, shader);
243 break;
244 case PIPE_SHADER_TESS_EVAL:
245 if (key.tes.as_es)
246 evergreen_update_es_state(ctx, shader);
247 else
248 evergreen_update_vs_state(ctx, shader);
249 break;
250 case PIPE_SHADER_GEOMETRY:
251 if (rctx->b.chip_class >= EVERGREEN) {
252 evergreen_update_gs_state(ctx, shader);
253 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
254 } else {
255 r600_update_gs_state(ctx, shader);
256 r600_update_vs_state(ctx, shader->gs_copy_shader);
257 }
258 break;
259 case PIPE_SHADER_VERTEX:
260 export_shader = key.vs.as_es;
261 if (rctx->b.chip_class >= EVERGREEN) {
262 if (key.vs.as_ls)
263 evergreen_update_ls_state(ctx, shader);
264 else if (key.vs.as_es)
265 evergreen_update_es_state(ctx, shader);
266 else
267 evergreen_update_vs_state(ctx, shader);
268 } else {
269 if (export_shader)
270 r600_update_es_state(ctx, shader);
271 else
272 r600_update_vs_state(ctx, shader);
273 }
274 break;
275 case PIPE_SHADER_FRAGMENT:
276 if (rctx->b.chip_class >= EVERGREEN) {
277 evergreen_update_ps_state(ctx, shader);
278 } else {
279 r600_update_ps_state(ctx, shader);
280 }
281 break;
282 default:
283 r = -EINVAL;
284 goto error;
285 }
286 return 0;
287
288 error:
289 r600_pipe_shader_destroy(ctx, shader);
290 return r;
291 }
292
293 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
294 {
295 r600_resource_reference(&shader->bo, NULL);
296 r600_bytecode_clear(&shader->shader.bc);
297 r600_release_command_buffer(&shader->command_buffer);
298 }
299
300 /*
301 * tgsi -> r600 shader
302 */
303 struct r600_shader_tgsi_instruction;
304
305 struct r600_shader_src {
306 unsigned sel;
307 unsigned swizzle[4];
308 unsigned neg;
309 unsigned abs;
310 unsigned rel;
311 unsigned kc_bank;
312 boolean kc_rel; /* true if cache bank is indexed */
313 uint32_t value[4];
314 };
315
316 struct eg_interp {
317 boolean enabled;
318 unsigned ij_index;
319 };
320
321 struct r600_shader_ctx {
322 struct tgsi_shader_info info;
323 struct tgsi_parse_context parse;
324 const struct tgsi_token *tokens;
325 unsigned type;
326 unsigned file_offset[TGSI_FILE_COUNT];
327 unsigned temp_reg;
328 const struct r600_shader_tgsi_instruction *inst_info;
329 struct r600_bytecode *bc;
330 struct r600_shader *shader;
331 struct r600_shader_src src[4];
332 uint32_t *literals;
333 uint32_t nliterals;
334 uint32_t max_driver_temp_used;
335 /* needed for evergreen interpolation */
336 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
337 /* evergreen/cayman also store sample mask in face register */
338 int face_gpr;
339 /* sample id is .w component stored in fixed point position register */
340 int fixed_pt_position_gpr;
341 int colors_used;
342 boolean clip_vertex_write;
343 unsigned cv_output;
344 unsigned edgeflag_output;
345 int fragcoord_input;
346 int native_integers;
347 int next_ring_offset;
348 int gs_out_ring_offset;
349 int gs_next_vertex;
350 struct r600_shader *gs_for_vs;
351 int gs_export_gpr_tregs[4];
352 int gs_rotated_input[2];
353 const struct pipe_stream_output_info *gs_stream_output_info;
354 unsigned enabled_stream_buffers_mask;
355 unsigned tess_input_info; /* temp with tess input offsets */
356 unsigned tess_output_info; /* temp with tess input offsets */
357 unsigned thread_id_gpr; /* temp with thread id calculated for images */
358 };
359
360 struct r600_shader_tgsi_instruction {
361 unsigned op;
362 int (*process)(struct r600_shader_ctx *ctx);
363 };
364
365 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
366 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
367 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
368 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
369 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
370 static int tgsi_else(struct r600_shader_ctx *ctx);
371 static int tgsi_endif(struct r600_shader_ctx *ctx);
372 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
373 static int tgsi_endloop(struct r600_shader_ctx *ctx);
374 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
375 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
376 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
377 unsigned int dst_reg);
378 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
379 const struct r600_shader_src *shader_src,
380 unsigned chan);
381 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
382 unsigned dst_reg);
383
384 static int tgsi_last_instruction(unsigned writemask)
385 {
386 int i, lasti = 0;
387
388 for (i = 0; i < 4; i++) {
389 if (writemask & (1 << i)) {
390 lasti = i;
391 }
392 }
393 return lasti;
394 }
395
396 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
397 {
398 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
399 unsigned j;
400
401 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
402 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
403 return -EINVAL;
404 }
405 #if 0
406 if (i->Instruction.Label) {
407 R600_ERR("label unsupported\n");
408 return -EINVAL;
409 }
410 #endif
411 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
412 if (i->Src[j].Register.Dimension) {
413 switch (i->Src[j].Register.File) {
414 case TGSI_FILE_CONSTANT:
415 case TGSI_FILE_HW_ATOMIC:
416 break;
417 case TGSI_FILE_INPUT:
418 if (ctx->type == PIPE_SHADER_GEOMETRY ||
419 ctx->type == PIPE_SHADER_TESS_CTRL ||
420 ctx->type == PIPE_SHADER_TESS_EVAL)
421 break;
422 case TGSI_FILE_OUTPUT:
423 if (ctx->type == PIPE_SHADER_TESS_CTRL)
424 break;
425 default:
426 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
427 i->Src[j].Register.File,
428 i->Src[j].Register.Dimension);
429 return -EINVAL;
430 }
431 }
432 }
433 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
434 if (i->Dst[j].Register.Dimension) {
435 if (ctx->type == PIPE_SHADER_TESS_CTRL)
436 continue;
437 R600_ERR("unsupported dst (dimension)\n");
438 return -EINVAL;
439 }
440 }
441 return 0;
442 }
443
444 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
445 {
446 if (interpolate == TGSI_INTERPOLATE_COLOR ||
447 interpolate == TGSI_INTERPOLATE_LINEAR ||
448 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
449 {
450 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
451 int loc;
452
453 switch(location) {
454 case TGSI_INTERPOLATE_LOC_CENTER:
455 loc = 1;
456 break;
457 case TGSI_INTERPOLATE_LOC_CENTROID:
458 loc = 2;
459 break;
460 case TGSI_INTERPOLATE_LOC_SAMPLE:
461 default:
462 loc = 0; break;
463 }
464
465 return is_linear * 3 + loc;
466 }
467
468 return -1;
469 }
470
471 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
472 int input)
473 {
474 int i = eg_get_interpolator_index(
475 ctx->shader->input[input].interpolate,
476 ctx->shader->input[input].interpolate_location);
477 assert(i >= 0);
478 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
479 }
480
481 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
482 {
483 int i, r;
484 struct r600_bytecode_alu alu;
485 int gpr = 0, base_chan = 0;
486 int ij_index = ctx->shader->input[input].ij_index;
487
488 /* work out gpr and base_chan from index */
489 gpr = ij_index / 2;
490 base_chan = (2 * (ij_index % 2)) + 1;
491
492 for (i = 0; i < 8; i++) {
493 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
494
495 if (i < 4)
496 alu.op = ALU_OP2_INTERP_ZW;
497 else
498 alu.op = ALU_OP2_INTERP_XY;
499
500 if ((i > 1) && (i < 6)) {
501 alu.dst.sel = ctx->shader->input[input].gpr;
502 alu.dst.write = 1;
503 }
504
505 alu.dst.chan = i % 4;
506
507 alu.src[0].sel = gpr;
508 alu.src[0].chan = (base_chan - (i % 2));
509
510 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
511
512 alu.bank_swizzle_force = SQ_ALU_VEC_210;
513 if ((i % 4) == 3)
514 alu.last = 1;
515 r = r600_bytecode_add_alu(ctx->bc, &alu);
516 if (r)
517 return r;
518 }
519 return 0;
520 }
521
522 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
523 {
524 int i, r;
525 struct r600_bytecode_alu alu;
526
527 for (i = 0; i < 4; i++) {
528 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
529
530 alu.op = ALU_OP1_INTERP_LOAD_P0;
531
532 alu.dst.sel = ctx->shader->input[input].gpr;
533 alu.dst.write = 1;
534
535 alu.dst.chan = i;
536
537 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
538 alu.src[0].chan = i;
539
540 if (i == 3)
541 alu.last = 1;
542 r = r600_bytecode_add_alu(ctx->bc, &alu);
543 if (r)
544 return r;
545 }
546 return 0;
547 }
548
549 /*
550 * Special export handling in shaders
551 *
552 * shader export ARRAY_BASE for EXPORT_POS:
553 * 60 is position
554 * 61 is misc vector
555 * 62, 63 are clip distance vectors
556 *
557 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
558 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
559 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
560 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
561 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
562 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
563 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
564 * exclusive from render target index)
565 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
566 *
567 *
568 * shader export ARRAY_BASE for EXPORT_PIXEL:
569 * 0-7 CB targets
570 * 61 computed Z vector
571 *
572 * The use of the values exported in the computed Z vector are controlled
573 * by DB_SHADER_CONTROL:
574 * Z_EXPORT_ENABLE - Z as a float in RED
575 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
576 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
577 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
578 * DB_SOURCE_FORMAT - export control restrictions
579 *
580 */
581
582
583 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
584 static int r600_spi_sid(struct r600_shader_io * io)
585 {
586 int index, name = io->name;
587
588 /* These params are handled differently, they don't need
589 * semantic indices, so we'll use 0 for them.
590 */
591 if (name == TGSI_SEMANTIC_POSITION ||
592 name == TGSI_SEMANTIC_PSIZE ||
593 name == TGSI_SEMANTIC_EDGEFLAG ||
594 name == TGSI_SEMANTIC_FACE ||
595 name == TGSI_SEMANTIC_SAMPLEMASK)
596 index = 0;
597 else {
598 if (name == TGSI_SEMANTIC_GENERIC) {
599 /* For generic params simply use sid from tgsi */
600 index = io->sid;
601 } else {
602 /* For non-generic params - pack name and sid into 8 bits */
603 index = 0x80 | (name<<3) | (io->sid);
604 }
605
606 /* Make sure that all really used indices have nonzero value, so
607 * we can just compare it to 0 later instead of comparing the name
608 * with different values to detect special cases. */
609 index++;
610 }
611
612 return index;
613 };
614
615 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
616 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
617 {
618 switch (semantic_name) {
619 case TGSI_SEMANTIC_POSITION:
620 return 0;
621 case TGSI_SEMANTIC_PSIZE:
622 return 1;
623 case TGSI_SEMANTIC_CLIPDIST:
624 assert(index <= 1);
625 return 2 + index;
626 case TGSI_SEMANTIC_GENERIC:
627 if (index <= 63-4)
628 return 4 + index - 9;
629 else
630 /* same explanation as in the default statement,
631 * the only user hitting this is st/nine.
632 */
633 return 0;
634
635 /* patch indices are completely separate and thus start from 0 */
636 case TGSI_SEMANTIC_TESSOUTER:
637 return 0;
638 case TGSI_SEMANTIC_TESSINNER:
639 return 1;
640 case TGSI_SEMANTIC_PATCH:
641 return 2 + index;
642
643 default:
644 /* Don't fail here. The result of this function is only used
645 * for LS, TCS, TES, and GS, where legacy GL semantics can't
646 * occur, but this function is called for all vertex shaders
647 * before it's known whether LS will be compiled or not.
648 */
649 return 0;
650 }
651 }
652
653 /* turn input into interpolate on EG */
654 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
655 {
656 int r = 0;
657
658 if (ctx->shader->input[index].spi_sid) {
659 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
660 if (ctx->shader->input[index].interpolate > 0) {
661 evergreen_interp_assign_ij_index(ctx, index);
662 r = evergreen_interp_alu(ctx, index);
663 } else {
664 r = evergreen_interp_flat(ctx, index);
665 }
666 }
667 return r;
668 }
669
670 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
671 {
672 struct r600_bytecode_alu alu;
673 int i, r;
674 int gpr_front = ctx->shader->input[front].gpr;
675 int gpr_back = ctx->shader->input[back].gpr;
676
677 for (i = 0; i < 4; i++) {
678 memset(&alu, 0, sizeof(alu));
679 alu.op = ALU_OP3_CNDGT;
680 alu.is_op3 = 1;
681 alu.dst.write = 1;
682 alu.dst.sel = gpr_front;
683 alu.src[0].sel = ctx->face_gpr;
684 alu.src[1].sel = gpr_front;
685 alu.src[2].sel = gpr_back;
686
687 alu.dst.chan = i;
688 alu.src[1].chan = i;
689 alu.src[2].chan = i;
690 alu.last = (i==3);
691
692 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
693 return r;
694 }
695
696 return 0;
697 }
698
699 /* execute a single slot ALU calculation */
700 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
701 int dst_sel, int dst_chan,
702 int src0_sel, unsigned src0_chan_val,
703 int src1_sel, unsigned src1_chan_val)
704 {
705 struct r600_bytecode_alu alu;
706 int r, i;
707
708 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
709 for (i = 0; i < 4; i++) {
710 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
711 alu.op = op;
712 alu.src[0].sel = src0_sel;
713 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
714 alu.src[0].value = src0_chan_val;
715 else
716 alu.src[0].chan = src0_chan_val;
717 alu.src[1].sel = src1_sel;
718 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
719 alu.src[1].value = src1_chan_val;
720 else
721 alu.src[1].chan = src1_chan_val;
722 alu.dst.sel = dst_sel;
723 alu.dst.chan = i;
724 alu.dst.write = i == dst_chan;
725 alu.last = (i == 3);
726 r = r600_bytecode_add_alu(ctx->bc, &alu);
727 if (r)
728 return r;
729 }
730 return 0;
731 }
732
733 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
734 alu.op = op;
735 alu.src[0].sel = src0_sel;
736 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
737 alu.src[0].value = src0_chan_val;
738 else
739 alu.src[0].chan = src0_chan_val;
740 alu.src[1].sel = src1_sel;
741 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
742 alu.src[1].value = src1_chan_val;
743 else
744 alu.src[1].chan = src1_chan_val;
745 alu.dst.sel = dst_sel;
746 alu.dst.chan = dst_chan;
747 alu.dst.write = 1;
748 alu.last = 1;
749 r = r600_bytecode_add_alu(ctx->bc, &alu);
750 if (r)
751 return r;
752 return 0;
753 }
754
755 /* execute a single slot ALU calculation */
756 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
757 int dst_sel, int dst_chan,
758 int src0_sel, unsigned src0_chan_val,
759 int src1_sel, unsigned src1_chan_val,
760 int src2_sel, unsigned src2_chan_val)
761 {
762 struct r600_bytecode_alu alu;
763 int r;
764
765 /* validate this for other ops */
766 assert(op == ALU_OP3_MULADD_UINT24 || op == ALU_OP3_CNDE_INT);
767 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
768 alu.op = op;
769 alu.src[0].sel = src0_sel;
770 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
771 alu.src[0].value = src0_chan_val;
772 else
773 alu.src[0].chan = src0_chan_val;
774 alu.src[1].sel = src1_sel;
775 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
776 alu.src[1].value = src1_chan_val;
777 else
778 alu.src[1].chan = src1_chan_val;
779 alu.src[2].sel = src2_sel;
780 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
781 alu.src[2].value = src2_chan_val;
782 else
783 alu.src[2].chan = src2_chan_val;
784 alu.dst.sel = dst_sel;
785 alu.dst.chan = dst_chan;
786 alu.is_op3 = 1;
787 alu.last = 1;
788 r = r600_bytecode_add_alu(ctx->bc, &alu);
789 if (r)
790 return r;
791 return 0;
792 }
793
794 /* put it in temp_reg.x */
795 static int get_lds_offset0(struct r600_shader_ctx *ctx,
796 int rel_patch_chan,
797 int temp_reg, bool is_patch_var)
798 {
799 int r;
800
801 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
802 /* ADD
803 Dimension - patch0_offset (input_vals.z),
804 Non-dim - patch0_data_offset (input_vals.w)
805 */
806 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
807 temp_reg, 0,
808 ctx->tess_output_info, 0,
809 0, rel_patch_chan,
810 ctx->tess_output_info, is_patch_var ? 3 : 2);
811 if (r)
812 return r;
813 return 0;
814 }
815
816 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
817 {
818 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
819 }
820
821 static int r600_get_temp(struct r600_shader_ctx *ctx)
822 {
823 return ctx->temp_reg + ctx->max_driver_temp_used++;
824 }
825
826 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
827 {
828 int i;
829 i = ctx->shader->noutput++;
830 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
831 ctx->shader->output[i].sid = 0;
832 ctx->shader->output[i].gpr = 0;
833 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
834 ctx->shader->output[i].write_mask = 0x4;
835 ctx->shader->output[i].spi_sid = prim_id_sid;
836
837 return 0;
838 }
839
840 static int tgsi_barrier(struct r600_shader_ctx *ctx)
841 {
842 struct r600_bytecode_alu alu;
843 int r;
844
845 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
846 alu.op = ctx->inst_info->op;
847 alu.last = 1;
848
849 r = r600_bytecode_add_alu(ctx->bc, &alu);
850 if (r)
851 return r;
852 return 0;
853 }
854
855 static int tgsi_declaration(struct r600_shader_ctx *ctx)
856 {
857 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
858 int r, i, j, count = d->Range.Last - d->Range.First + 1;
859
860 switch (d->Declaration.File) {
861 case TGSI_FILE_INPUT:
862 for (j = 0; j < count; j++) {
863 i = ctx->shader->ninput + j;
864 assert(i < ARRAY_SIZE(ctx->shader->input));
865 ctx->shader->input[i].name = d->Semantic.Name;
866 ctx->shader->input[i].sid = d->Semantic.Index + j;
867 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
868 ctx->shader->input[i].interpolate_location = d->Interp.Location;
869 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
870 if (ctx->type == PIPE_SHADER_FRAGMENT) {
871 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
872 switch (ctx->shader->input[i].name) {
873 case TGSI_SEMANTIC_FACE:
874 if (ctx->face_gpr != -1)
875 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
876 else
877 ctx->face_gpr = ctx->shader->input[i].gpr;
878 break;
879 case TGSI_SEMANTIC_COLOR:
880 ctx->colors_used++;
881 break;
882 case TGSI_SEMANTIC_POSITION:
883 ctx->fragcoord_input = i;
884 break;
885 case TGSI_SEMANTIC_PRIMID:
886 /* set this for now */
887 ctx->shader->gs_prim_id_input = true;
888 ctx->shader->ps_prim_id_input = i;
889 break;
890 }
891 if (ctx->bc->chip_class >= EVERGREEN) {
892 if ((r = evergreen_interp_input(ctx, i)))
893 return r;
894 }
895 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
896 /* FIXME probably skip inputs if they aren't passed in the ring */
897 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
898 ctx->next_ring_offset += 16;
899 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
900 ctx->shader->gs_prim_id_input = true;
901 }
902 }
903 ctx->shader->ninput += count;
904 break;
905 case TGSI_FILE_OUTPUT:
906 for (j = 0; j < count; j++) {
907 i = ctx->shader->noutput + j;
908 assert(i < ARRAY_SIZE(ctx->shader->output));
909 ctx->shader->output[i].name = d->Semantic.Name;
910 ctx->shader->output[i].sid = d->Semantic.Index + j;
911 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
912 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
913 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
914 if (ctx->type == PIPE_SHADER_VERTEX ||
915 ctx->type == PIPE_SHADER_GEOMETRY ||
916 ctx->type == PIPE_SHADER_TESS_EVAL) {
917 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
918 switch (d->Semantic.Name) {
919 case TGSI_SEMANTIC_CLIPDIST:
920 ctx->shader->clip_dist_write |= d->Declaration.UsageMask <<
921 ((d->Semantic.Index + j) << 2);
922 break;
923 case TGSI_SEMANTIC_PSIZE:
924 ctx->shader->vs_out_misc_write = 1;
925 ctx->shader->vs_out_point_size = 1;
926 break;
927 case TGSI_SEMANTIC_EDGEFLAG:
928 ctx->shader->vs_out_misc_write = 1;
929 ctx->shader->vs_out_edgeflag = 1;
930 ctx->edgeflag_output = i;
931 break;
932 case TGSI_SEMANTIC_VIEWPORT_INDEX:
933 ctx->shader->vs_out_misc_write = 1;
934 ctx->shader->vs_out_viewport = 1;
935 break;
936 case TGSI_SEMANTIC_LAYER:
937 ctx->shader->vs_out_misc_write = 1;
938 ctx->shader->vs_out_layer = 1;
939 break;
940 case TGSI_SEMANTIC_CLIPVERTEX:
941 ctx->clip_vertex_write = TRUE;
942 ctx->cv_output = i;
943 break;
944 }
945 if (ctx->type == PIPE_SHADER_GEOMETRY) {
946 ctx->gs_out_ring_offset += 16;
947 }
948 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
949 switch (d->Semantic.Name) {
950 case TGSI_SEMANTIC_COLOR:
951 ctx->shader->nr_ps_max_color_exports++;
952 break;
953 }
954 }
955 }
956 ctx->shader->noutput += count;
957 break;
958 case TGSI_FILE_TEMPORARY:
959 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
960 if (d->Array.ArrayID) {
961 r600_add_gpr_array(ctx->shader,
962 ctx->file_offset[TGSI_FILE_TEMPORARY] +
963 d->Range.First,
964 d->Range.Last - d->Range.First + 1, 0x0F);
965 }
966 }
967 break;
968
969 case TGSI_FILE_CONSTANT:
970 case TGSI_FILE_SAMPLER:
971 case TGSI_FILE_SAMPLER_VIEW:
972 case TGSI_FILE_ADDRESS:
973 case TGSI_FILE_IMAGE:
974 break;
975
976 case TGSI_FILE_HW_ATOMIC:
977 i = ctx->shader->nhwatomic_ranges;
978 ctx->shader->atomics[i].start = d->Range.First;
979 ctx->shader->atomics[i].end = d->Range.Last;
980 ctx->shader->atomics[i].hw_idx = ctx->shader->atomic_base + ctx->shader->nhwatomic;
981 ctx->shader->atomics[i].array_id = d->Array.ArrayID;
982 ctx->shader->atomics[i].buffer_id = d->Dim.Index2D;
983 ctx->shader->nhwatomic_ranges++;
984 ctx->shader->nhwatomic += count;
985 break;
986
987 case TGSI_FILE_SYSTEM_VALUE:
988 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
989 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
990 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
991 break; /* Already handled from allocate_system_value_inputs */
992 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
993 if (!ctx->native_integers) {
994 struct r600_bytecode_alu alu;
995 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
996
997 alu.op = ALU_OP1_INT_TO_FLT;
998 alu.src[0].sel = 0;
999 alu.src[0].chan = 3;
1000
1001 alu.dst.sel = 0;
1002 alu.dst.chan = 3;
1003 alu.dst.write = 1;
1004 alu.last = 1;
1005
1006 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1007 return r;
1008 }
1009 break;
1010 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
1011 break;
1012 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
1013 break;
1014 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1015 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1016 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1017 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1018 unsigned temp_reg = r600_get_temp(ctx);
1019
1020 r = get_lds_offset0(ctx, 2, temp_reg, true);
1021 if (r)
1022 return r;
1023
1024 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1025 temp_reg, 0,
1026 temp_reg, 0,
1027 V_SQ_ALU_SRC_LITERAL, param * 16);
1028 if (r)
1029 return r;
1030
1031 do_lds_fetch_values(ctx, temp_reg, dreg);
1032 }
1033 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1034 /* MOV r1.x, r0.x;
1035 MOV r1.y, r0.y;
1036 */
1037 for (i = 0; i < 2; i++) {
1038 struct r600_bytecode_alu alu;
1039 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1040 alu.op = ALU_OP1_MOV;
1041 alu.src[0].sel = 0;
1042 alu.src[0].chan = 0 + i;
1043 alu.dst.sel = 1;
1044 alu.dst.chan = 0 + i;
1045 alu.dst.write = 1;
1046 alu.last = (i == 1) ? 1 : 0;
1047 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1048 return r;
1049 }
1050 /* ADD r1.z, 1.0f, -r0.x */
1051 struct r600_bytecode_alu alu;
1052 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1053 alu.op = ALU_OP2_ADD;
1054 alu.src[0].sel = V_SQ_ALU_SRC_1;
1055 alu.src[1].sel = 1;
1056 alu.src[1].chan = 0;
1057 alu.src[1].neg = 1;
1058 alu.dst.sel = 1;
1059 alu.dst.chan = 2;
1060 alu.dst.write = 1;
1061 alu.last = 1;
1062 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1063 return r;
1064
1065 /* ADD r1.z, r1.z, -r1.y */
1066 alu.op = ALU_OP2_ADD;
1067 alu.src[0].sel = 1;
1068 alu.src[0].chan = 2;
1069 alu.src[1].sel = 1;
1070 alu.src[1].chan = 1;
1071 alu.src[1].neg = 1;
1072 alu.dst.sel = 1;
1073 alu.dst.chan = 2;
1074 alu.dst.write = 1;
1075 alu.last = 1;
1076 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1077 return r;
1078 break;
1079 }
1080 break;
1081 default:
1082 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1083 return -EINVAL;
1084 }
1085 return 0;
1086 }
1087
1088 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1089 {
1090 struct tgsi_parse_context parse;
1091 struct {
1092 boolean enabled;
1093 int *reg;
1094 unsigned name, alternate_name;
1095 } inputs[2] = {
1096 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1097
1098 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1099 };
1100 int i, k, num_regs = 0;
1101
1102 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1103 return 0;
1104 }
1105
1106 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1107 while (!tgsi_parse_end_of_tokens(&parse)) {
1108 tgsi_parse_token(&parse);
1109
1110 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1111 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1112 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1113 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1114 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1115 {
1116 int interpolate, location, k;
1117
1118 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1119 location = TGSI_INTERPOLATE_LOC_CENTER;
1120 inputs[1].enabled = true; /* needs SAMPLEID */
1121 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1122 location = TGSI_INTERPOLATE_LOC_CENTER;
1123 /* Needs sample positions, currently those are always available */
1124 } else {
1125 location = TGSI_INTERPOLATE_LOC_CENTROID;
1126 }
1127
1128 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1129 k = eg_get_interpolator_index(interpolate, location);
1130 if (k >= 0)
1131 ctx->eg_interpolators[k].enabled = true;
1132 }
1133 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1134 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1135 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1136 for (k = 0; k < ARRAY_SIZE(inputs); k++) {
1137 if (d->Semantic.Name == inputs[k].name ||
1138 d->Semantic.Name == inputs[k].alternate_name) {
1139 inputs[k].enabled = true;
1140 }
1141 }
1142 }
1143 }
1144 }
1145
1146 tgsi_parse_free(&parse);
1147
1148 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
1149 boolean enabled = inputs[i].enabled;
1150 int *reg = inputs[i].reg;
1151 unsigned name = inputs[i].name;
1152
1153 if (enabled) {
1154 int gpr = gpr_offset + num_regs++;
1155 ctx->shader->nsys_inputs++;
1156
1157 // add to inputs, allocate a gpr
1158 k = ctx->shader->ninput++;
1159 ctx->shader->input[k].name = name;
1160 ctx->shader->input[k].sid = 0;
1161 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1162 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1163 *reg = ctx->shader->input[k].gpr = gpr;
1164 }
1165 }
1166
1167 return gpr_offset + num_regs;
1168 }
1169
1170 /*
1171 * for evergreen we need to scan the shader to find the number of GPRs we need to
1172 * reserve for interpolation and system values
1173 *
1174 * we need to know if we are going to emit
1175 * any sample or centroid inputs
1176 * if perspective and linear are required
1177 */
1178 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1179 {
1180 unsigned i;
1181 int num_baryc;
1182 struct tgsi_parse_context parse;
1183
1184 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1185
1186 for (i = 0; i < ctx->info.num_inputs; i++) {
1187 int k;
1188 /* skip position/face/mask/sampleid */
1189 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1190 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1191 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1192 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1193 continue;
1194
1195 k = eg_get_interpolator_index(
1196 ctx->info.input_interpolate[i],
1197 ctx->info.input_interpolate_loc[i]);
1198 if (k >= 0)
1199 ctx->eg_interpolators[k].enabled = TRUE;
1200 }
1201
1202 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1203 return 0;
1204 }
1205
1206 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1207 while (!tgsi_parse_end_of_tokens(&parse)) {
1208 tgsi_parse_token(&parse);
1209
1210 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1211 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1212 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1213 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1214 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1215 {
1216 int interpolate, location, k;
1217
1218 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1219 location = TGSI_INTERPOLATE_LOC_CENTER;
1220 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1221 location = TGSI_INTERPOLATE_LOC_CENTER;
1222 } else {
1223 location = TGSI_INTERPOLATE_LOC_CENTROID;
1224 }
1225
1226 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1227 k = eg_get_interpolator_index(interpolate, location);
1228 if (k >= 0)
1229 ctx->eg_interpolators[k].enabled = true;
1230 }
1231 }
1232 }
1233
1234 tgsi_parse_free(&parse);
1235
1236 /* assign gpr to each interpolator according to priority */
1237 num_baryc = 0;
1238 for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
1239 if (ctx->eg_interpolators[i].enabled) {
1240 ctx->eg_interpolators[i].ij_index = num_baryc;
1241 num_baryc ++;
1242 }
1243 }
1244
1245 /* XXX PULL MODEL and LINE STIPPLE */
1246
1247 num_baryc = (num_baryc + 1) >> 1;
1248 return allocate_system_value_inputs(ctx, num_baryc);
1249 }
1250
1251 /* sample_id_sel == NULL means fetch for current sample */
1252 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1253 {
1254 struct r600_bytecode_vtx vtx;
1255 int r, t1;
1256
1257 assert(ctx->fixed_pt_position_gpr != -1);
1258
1259 t1 = r600_get_temp(ctx);
1260
1261 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1262 vtx.op = FETCH_OP_VFETCH;
1263 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1264 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1265 if (sample_id == NULL) {
1266 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1267 vtx.src_sel_x = 3;
1268 }
1269 else {
1270 struct r600_bytecode_alu alu;
1271
1272 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1273 alu.op = ALU_OP1_MOV;
1274 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1275 alu.dst.sel = t1;
1276 alu.dst.write = 1;
1277 alu.last = 1;
1278 r = r600_bytecode_add_alu(ctx->bc, &alu);
1279 if (r)
1280 return r;
1281
1282 vtx.src_gpr = t1;
1283 vtx.src_sel_x = 0;
1284 }
1285 vtx.mega_fetch_count = 16;
1286 vtx.dst_gpr = t1;
1287 vtx.dst_sel_x = 0;
1288 vtx.dst_sel_y = 1;
1289 vtx.dst_sel_z = 2;
1290 vtx.dst_sel_w = 3;
1291 vtx.data_format = FMT_32_32_32_32_FLOAT;
1292 vtx.num_format_all = 2;
1293 vtx.format_comp_all = 1;
1294 vtx.use_const_fields = 0;
1295 vtx.offset = 1; // first element is size of buffer
1296 vtx.endian = r600_endian_swap(32);
1297 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1298
1299 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1300 if (r)
1301 return r;
1302
1303 return t1;
1304 }
1305
1306 static void tgsi_src(struct r600_shader_ctx *ctx,
1307 const struct tgsi_full_src_register *tgsi_src,
1308 struct r600_shader_src *r600_src)
1309 {
1310 memset(r600_src, 0, sizeof(*r600_src));
1311 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1312 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1313 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1314 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1315 r600_src->neg = tgsi_src->Register.Negate;
1316 r600_src->abs = tgsi_src->Register.Absolute;
1317
1318 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1319 int index;
1320 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1321 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1322 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1323
1324 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1325 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1326 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1327 return;
1328 }
1329 index = tgsi_src->Register.Index;
1330 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1331 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1332 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1333 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1334 r600_src->swizzle[0] = 2; // Z value
1335 r600_src->swizzle[1] = 2;
1336 r600_src->swizzle[2] = 2;
1337 r600_src->swizzle[3] = 2;
1338 r600_src->sel = ctx->face_gpr;
1339 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1340 r600_src->swizzle[0] = 3; // W value
1341 r600_src->swizzle[1] = 3;
1342 r600_src->swizzle[2] = 3;
1343 r600_src->swizzle[3] = 3;
1344 r600_src->sel = ctx->fixed_pt_position_gpr;
1345 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1346 r600_src->swizzle[0] = 0;
1347 r600_src->swizzle[1] = 1;
1348 r600_src->swizzle[2] = 4;
1349 r600_src->swizzle[3] = 4;
1350 r600_src->sel = load_sample_position(ctx, NULL, -1);
1351 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1352 r600_src->swizzle[0] = 3;
1353 r600_src->swizzle[1] = 3;
1354 r600_src->swizzle[2] = 3;
1355 r600_src->swizzle[3] = 3;
1356 r600_src->sel = 0;
1357 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1358 r600_src->swizzle[0] = 0;
1359 r600_src->swizzle[1] = 0;
1360 r600_src->swizzle[2] = 0;
1361 r600_src->swizzle[3] = 0;
1362 r600_src->sel = 0;
1363 } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1364 r600_src->swizzle[0] = 3;
1365 r600_src->swizzle[1] = 3;
1366 r600_src->swizzle[2] = 3;
1367 r600_src->swizzle[3] = 3;
1368 r600_src->sel = 1;
1369 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1370 r600_src->swizzle[0] = 2;
1371 r600_src->swizzle[1] = 2;
1372 r600_src->swizzle[2] = 2;
1373 r600_src->swizzle[3] = 2;
1374 r600_src->sel = 0;
1375 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1376 r600_src->sel = 1;
1377 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1378 r600_src->sel = 3;
1379 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1380 r600_src->sel = 2;
1381 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1382 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
1383 r600_src->sel = ctx->tess_input_info;
1384 r600_src->swizzle[0] = 2;
1385 r600_src->swizzle[1] = 2;
1386 r600_src->swizzle[2] = 2;
1387 r600_src->swizzle[3] = 2;
1388 } else {
1389 r600_src->sel = ctx->tess_input_info;
1390 r600_src->swizzle[0] = 3;
1391 r600_src->swizzle[1] = 3;
1392 r600_src->swizzle[2] = 3;
1393 r600_src->swizzle[3] = 3;
1394 }
1395 } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1396 r600_src->sel = 0;
1397 r600_src->swizzle[0] = 0;
1398 r600_src->swizzle[1] = 0;
1399 r600_src->swizzle[2] = 0;
1400 r600_src->swizzle[3] = 0;
1401 } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1402 r600_src->sel = 0;
1403 r600_src->swizzle[0] = 3;
1404 r600_src->swizzle[1] = 3;
1405 r600_src->swizzle[2] = 3;
1406 r600_src->swizzle[3] = 3;
1407 }
1408 } else {
1409 if (tgsi_src->Register.Indirect)
1410 r600_src->rel = V_SQ_REL_RELATIVE;
1411 r600_src->sel = tgsi_src->Register.Index;
1412 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1413 }
1414 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1415 if (tgsi_src->Register.Dimension) {
1416 r600_src->kc_bank = tgsi_src->Dimension.Index;
1417 if (tgsi_src->Dimension.Indirect) {
1418 r600_src->kc_rel = 1;
1419 }
1420 }
1421 }
1422 }
1423
1424 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1425 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1426 unsigned int dst_reg)
1427 {
1428 struct r600_bytecode_vtx vtx;
1429 unsigned int ar_reg;
1430 int r;
1431
1432 if (offset) {
1433 struct r600_bytecode_alu alu;
1434
1435 memset(&alu, 0, sizeof(alu));
1436
1437 alu.op = ALU_OP2_ADD_INT;
1438 alu.src[0].sel = ctx->bc->ar_reg;
1439 alu.src[0].chan = ar_chan;
1440
1441 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1442 alu.src[1].value = offset;
1443
1444 alu.dst.sel = dst_reg;
1445 alu.dst.chan = ar_chan;
1446 alu.dst.write = 1;
1447 alu.last = 1;
1448
1449 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1450 return r;
1451
1452 ar_reg = dst_reg;
1453 } else {
1454 ar_reg = ctx->bc->ar_reg;
1455 }
1456
1457 memset(&vtx, 0, sizeof(vtx));
1458 vtx.buffer_id = cb_idx;
1459 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1460 vtx.src_gpr = ar_reg;
1461 vtx.src_sel_x = ar_chan;
1462 vtx.mega_fetch_count = 16;
1463 vtx.dst_gpr = dst_reg;
1464 vtx.dst_sel_x = 0; /* SEL_X */
1465 vtx.dst_sel_y = 1; /* SEL_Y */
1466 vtx.dst_sel_z = 2; /* SEL_Z */
1467 vtx.dst_sel_w = 3; /* SEL_W */
1468 vtx.data_format = FMT_32_32_32_32_FLOAT;
1469 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1470 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1471 vtx.endian = r600_endian_swap(32);
1472 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1473
1474 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1475 return r;
1476
1477 return 0;
1478 }
1479
1480 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1481 {
1482 struct r600_bytecode_vtx vtx;
1483 int r;
1484 unsigned index = src->Register.Index;
1485 unsigned vtx_id = src->Dimension.Index;
1486 int offset_reg = ctx->gs_rotated_input[vtx_id / 3];
1487 int offset_chan = vtx_id % 3;
1488 int t2 = 0;
1489
1490 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1491 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1492
1493 if (offset_reg == ctx->gs_rotated_input[0] && offset_chan == 2)
1494 offset_chan = 3;
1495
1496 if (src->Dimension.Indirect || src->Register.Indirect)
1497 t2 = r600_get_temp(ctx);
1498
1499 if (src->Dimension.Indirect) {
1500 int treg[3];
1501 struct r600_bytecode_alu alu;
1502 int r, i;
1503 unsigned addr_reg;
1504 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1505 if (src->DimIndirect.Index > 0) {
1506 r = single_alu_op2(ctx, ALU_OP1_MOV,
1507 ctx->bc->ar_reg, 0,
1508 addr_reg, 0,
1509 0, 0);
1510 if (r)
1511 return r;
1512 }
1513 /*
1514 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1515 at least this is what fglrx seems to do. */
1516 for (i = 0; i < 3; i++) {
1517 treg[i] = r600_get_temp(ctx);
1518 }
1519 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1520
1521 for (i = 0; i < 3; i++) {
1522 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1523 alu.op = ALU_OP1_MOV;
1524 alu.src[0].sel = ctx->gs_rotated_input[0];
1525 alu.src[0].chan = i == 2 ? 3 : i;
1526 alu.dst.sel = treg[i];
1527 alu.dst.chan = 0;
1528 alu.dst.write = 1;
1529 alu.last = 1;
1530 r = r600_bytecode_add_alu(ctx->bc, &alu);
1531 if (r)
1532 return r;
1533 }
1534 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1535 alu.op = ALU_OP1_MOV;
1536 alu.src[0].sel = treg[0];
1537 alu.src[0].rel = 1;
1538 alu.dst.sel = t2;
1539 alu.dst.write = 1;
1540 alu.last = 1;
1541 r = r600_bytecode_add_alu(ctx->bc, &alu);
1542 if (r)
1543 return r;
1544 offset_reg = t2;
1545 offset_chan = 0;
1546 }
1547
1548 if (src->Register.Indirect) {
1549 int addr_reg;
1550 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1551
1552 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1553
1554 /* pull the value from index_reg */
1555 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1556 t2, 1,
1557 addr_reg, 0,
1558 V_SQ_ALU_SRC_LITERAL, first);
1559 if (r)
1560 return r;
1561 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1562 t2, 0,
1563 t2, 1,
1564 V_SQ_ALU_SRC_LITERAL, 4,
1565 offset_reg, offset_chan);
1566 if (r)
1567 return r;
1568 offset_reg = t2;
1569 offset_chan = 0;
1570 index = src->Register.Index - first;
1571 }
1572
1573 memset(&vtx, 0, sizeof(vtx));
1574 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1575 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1576 vtx.src_gpr = offset_reg;
1577 vtx.src_sel_x = offset_chan;
1578 vtx.offset = index * 16; /*bytes*/
1579 vtx.mega_fetch_count = 16;
1580 vtx.dst_gpr = dst_reg;
1581 vtx.dst_sel_x = 0; /* SEL_X */
1582 vtx.dst_sel_y = 1; /* SEL_Y */
1583 vtx.dst_sel_z = 2; /* SEL_Z */
1584 vtx.dst_sel_w = 3; /* SEL_W */
1585 if (ctx->bc->chip_class >= EVERGREEN) {
1586 vtx.use_const_fields = 1;
1587 } else {
1588 vtx.data_format = FMT_32_32_32_32_FLOAT;
1589 }
1590
1591 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1592 return r;
1593
1594 return 0;
1595 }
1596
1597 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1598 {
1599 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1600 unsigned i;
1601
1602 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1603 struct tgsi_full_src_register *src = &inst->Src[i];
1604
1605 if (src->Register.File == TGSI_FILE_INPUT) {
1606 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1607 /* primitive id is in R0.z */
1608 ctx->src[i].sel = 0;
1609 ctx->src[i].swizzle[0] = 2;
1610 }
1611 }
1612 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1613 int treg = r600_get_temp(ctx);
1614
1615 fetch_gs_input(ctx, src, treg);
1616 ctx->src[i].sel = treg;
1617 ctx->src[i].rel = 0;
1618 }
1619 }
1620 return 0;
1621 }
1622
1623
1624 /* Tessellation shaders pass outputs to the next shader using LDS.
1625 *
1626 * LS outputs = TCS(HS) inputs
1627 * TCS(HS) outputs = TES(DS) inputs
1628 *
1629 * The LDS layout is:
1630 * - TCS inputs for patch 0
1631 * - TCS inputs for patch 1
1632 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1633 * - ...
1634 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1635 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1636 * - TCS outputs for patch 1
1637 * - Per-patch TCS outputs for patch 1
1638 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1639 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1640 * - ...
1641 *
1642 * All three shaders VS(LS), TCS, TES share the same LDS space.
1643 */
1644 /* this will return with the dw address in temp_reg.x */
1645 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1646 const struct tgsi_full_dst_register *dst,
1647 const struct tgsi_full_src_register *src,
1648 int stride_bytes_reg, int stride_bytes_chan)
1649 {
1650 struct tgsi_full_dst_register reg;
1651 ubyte *name, *index, *array_first;
1652 int r;
1653 int param;
1654 struct tgsi_shader_info *info = &ctx->info;
1655 /* Set the register description. The address computation is the same
1656 * for sources and destinations. */
1657 if (src) {
1658 reg.Register.File = src->Register.File;
1659 reg.Register.Index = src->Register.Index;
1660 reg.Register.Indirect = src->Register.Indirect;
1661 reg.Register.Dimension = src->Register.Dimension;
1662 reg.Indirect = src->Indirect;
1663 reg.Dimension = src->Dimension;
1664 reg.DimIndirect = src->DimIndirect;
1665 } else
1666 reg = *dst;
1667
1668 /* If the register is 2-dimensional (e.g. an array of vertices
1669 * in a primitive), calculate the base address of the vertex. */
1670 if (reg.Register.Dimension) {
1671 int sel, chan;
1672 if (reg.Dimension.Indirect) {
1673 unsigned addr_reg;
1674 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1675
1676 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1677 /* pull the value from index_reg */
1678 sel = addr_reg;
1679 chan = 0;
1680 } else {
1681 sel = V_SQ_ALU_SRC_LITERAL;
1682 chan = reg.Dimension.Index;
1683 }
1684
1685 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1686 temp_reg, 0,
1687 stride_bytes_reg, stride_bytes_chan,
1688 sel, chan,
1689 temp_reg, 0);
1690 if (r)
1691 return r;
1692 }
1693
1694 if (reg.Register.File == TGSI_FILE_INPUT) {
1695 name = info->input_semantic_name;
1696 index = info->input_semantic_index;
1697 array_first = info->input_array_first;
1698 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1699 name = info->output_semantic_name;
1700 index = info->output_semantic_index;
1701 array_first = info->output_array_first;
1702 } else {
1703 assert(0);
1704 return -1;
1705 }
1706 if (reg.Register.Indirect) {
1707 int addr_reg;
1708 int first;
1709 /* Add the relative address of the element. */
1710 if (reg.Indirect.ArrayID)
1711 first = array_first[reg.Indirect.ArrayID];
1712 else
1713 first = reg.Register.Index;
1714
1715 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
1716
1717 /* pull the value from index_reg */
1718 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1719 temp_reg, 0,
1720 V_SQ_ALU_SRC_LITERAL, 16,
1721 addr_reg, 0,
1722 temp_reg, 0);
1723 if (r)
1724 return r;
1725
1726 param = r600_get_lds_unique_index(name[first],
1727 index[first]);
1728
1729 } else {
1730 param = r600_get_lds_unique_index(name[reg.Register.Index],
1731 index[reg.Register.Index]);
1732 }
1733
1734 /* add to base_addr - passed in temp_reg.x */
1735 if (param) {
1736 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1737 temp_reg, 0,
1738 temp_reg, 0,
1739 V_SQ_ALU_SRC_LITERAL, param * 16);
1740 if (r)
1741 return r;
1742
1743 }
1744 return 0;
1745 }
1746
1747 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
1748 unsigned dst_reg)
1749 {
1750 struct r600_bytecode_alu alu;
1751 int r, i;
1752
1753 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
1754 ctx->bc->force_add_cf = 1;
1755 for (i = 1; i < 4; i++) {
1756 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1757 temp_reg, i,
1758 temp_reg, 0,
1759 V_SQ_ALU_SRC_LITERAL, 4 * i);
1760 if (r)
1761 return r;
1762 }
1763 for (i = 0; i < 4; i++) {
1764 /* emit an LDS_READ_RET */
1765 memset(&alu, 0, sizeof(alu));
1766 alu.op = LDS_OP1_LDS_READ_RET;
1767 alu.src[0].sel = temp_reg;
1768 alu.src[0].chan = i;
1769 alu.src[1].sel = V_SQ_ALU_SRC_0;
1770 alu.src[2].sel = V_SQ_ALU_SRC_0;
1771 alu.dst.chan = 0;
1772 alu.is_lds_idx_op = true;
1773 alu.last = 1;
1774 r = r600_bytecode_add_alu(ctx->bc, &alu);
1775 if (r)
1776 return r;
1777 }
1778 for (i = 0; i < 4; i++) {
1779 /* then read from LDS_OQ_A_POP */
1780 memset(&alu, 0, sizeof(alu));
1781
1782 alu.op = ALU_OP1_MOV;
1783 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
1784 alu.src[0].chan = 0;
1785 alu.dst.sel = dst_reg;
1786 alu.dst.chan = i;
1787 alu.dst.write = 1;
1788 alu.last = 1;
1789 r = r600_bytecode_add_alu(ctx->bc, &alu);
1790 if (r)
1791 return r;
1792 }
1793 return 0;
1794 }
1795
1796 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1797 {
1798 int r;
1799 unsigned temp_reg = r600_get_temp(ctx);
1800
1801 r = get_lds_offset0(ctx, 2, temp_reg,
1802 src->Register.Dimension ? false : true);
1803 if (r)
1804 return r;
1805
1806 /* the base address is now in temp.x */
1807 r = r600_get_byte_address(ctx, temp_reg,
1808 NULL, src, ctx->tess_output_info, 1);
1809 if (r)
1810 return r;
1811
1812 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1813 if (r)
1814 return r;
1815 return 0;
1816 }
1817
1818 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1819 {
1820 int r;
1821 unsigned temp_reg = r600_get_temp(ctx);
1822
1823 /* t.x = ips * r0.y */
1824 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
1825 temp_reg, 0,
1826 ctx->tess_input_info, 0,
1827 0, 1);
1828
1829 if (r)
1830 return r;
1831
1832 /* the base address is now in temp.x */
1833 r = r600_get_byte_address(ctx, temp_reg,
1834 NULL, src, ctx->tess_input_info, 1);
1835 if (r)
1836 return r;
1837
1838 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1839 if (r)
1840 return r;
1841 return 0;
1842 }
1843
1844 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1845 {
1846 int r;
1847 unsigned temp_reg = r600_get_temp(ctx);
1848
1849 r = get_lds_offset0(ctx, 1, temp_reg,
1850 src->Register.Dimension ? false : true);
1851 if (r)
1852 return r;
1853 /* the base address is now in temp.x */
1854 r = r600_get_byte_address(ctx, temp_reg,
1855 NULL, src,
1856 ctx->tess_output_info, 1);
1857 if (r)
1858 return r;
1859
1860 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1861 if (r)
1862 return r;
1863 return 0;
1864 }
1865
1866 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
1867 {
1868 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1869 unsigned i;
1870
1871 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1872 struct tgsi_full_src_register *src = &inst->Src[i];
1873
1874 if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
1875 int treg = r600_get_temp(ctx);
1876 fetch_tes_input(ctx, src, treg);
1877 ctx->src[i].sel = treg;
1878 ctx->src[i].rel = 0;
1879 }
1880 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
1881 int treg = r600_get_temp(ctx);
1882 fetch_tcs_input(ctx, src, treg);
1883 ctx->src[i].sel = treg;
1884 ctx->src[i].rel = 0;
1885 }
1886 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
1887 int treg = r600_get_temp(ctx);
1888 fetch_tcs_output(ctx, src, treg);
1889 ctx->src[i].sel = treg;
1890 ctx->src[i].rel = 0;
1891 }
1892 }
1893 return 0;
1894 }
1895
1896 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1897 {
1898 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1899 struct r600_bytecode_alu alu;
1900 int i, j, k, nconst, r;
1901
1902 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1903 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1904 nconst++;
1905 }
1906 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1907 }
1908 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1909 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1910 continue;
1911 }
1912
1913 if (ctx->src[i].rel) {
1914 int chan = inst->Src[i].Indirect.Swizzle;
1915 int treg = r600_get_temp(ctx);
1916 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1917 return r;
1918
1919 ctx->src[i].kc_bank = 0;
1920 ctx->src[i].kc_rel = 0;
1921 ctx->src[i].sel = treg;
1922 ctx->src[i].rel = 0;
1923 j--;
1924 } else if (j > 0) {
1925 int treg = r600_get_temp(ctx);
1926 for (k = 0; k < 4; k++) {
1927 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1928 alu.op = ALU_OP1_MOV;
1929 alu.src[0].sel = ctx->src[i].sel;
1930 alu.src[0].chan = k;
1931 alu.src[0].rel = ctx->src[i].rel;
1932 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1933 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1934 alu.dst.sel = treg;
1935 alu.dst.chan = k;
1936 alu.dst.write = 1;
1937 if (k == 3)
1938 alu.last = 1;
1939 r = r600_bytecode_add_alu(ctx->bc, &alu);
1940 if (r)
1941 return r;
1942 }
1943 ctx->src[i].sel = treg;
1944 ctx->src[i].rel =0;
1945 j--;
1946 }
1947 }
1948 return 0;
1949 }
1950
1951 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1952 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1953 {
1954 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1955 struct r600_bytecode_alu alu;
1956 int i, j, k, nliteral, r;
1957
1958 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1959 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1960 nliteral++;
1961 }
1962 }
1963 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1964 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1965 int treg = r600_get_temp(ctx);
1966 for (k = 0; k < 4; k++) {
1967 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1968 alu.op = ALU_OP1_MOV;
1969 alu.src[0].sel = ctx->src[i].sel;
1970 alu.src[0].chan = k;
1971 alu.src[0].value = ctx->src[i].value[k];
1972 alu.dst.sel = treg;
1973 alu.dst.chan = k;
1974 alu.dst.write = 1;
1975 if (k == 3)
1976 alu.last = 1;
1977 r = r600_bytecode_add_alu(ctx->bc, &alu);
1978 if (r)
1979 return r;
1980 }
1981 ctx->src[i].sel = treg;
1982 j--;
1983 }
1984 }
1985 return 0;
1986 }
1987
1988 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1989 {
1990 int i, r, count = ctx->shader->ninput;
1991
1992 for (i = 0; i < count; i++) {
1993 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1994 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1995 if (r)
1996 return r;
1997 }
1998 }
1999 return 0;
2000 }
2001
2002 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
2003 int stream, unsigned *stream_item_size)
2004 {
2005 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
2006 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
2007 int i, j, r;
2008
2009 /* Sanity checking. */
2010 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
2011 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
2012 r = -EINVAL;
2013 goto out_err;
2014 }
2015 for (i = 0; i < so->num_outputs; i++) {
2016 if (so->output[i].output_buffer >= 4) {
2017 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2018 so->output[i].output_buffer);
2019 r = -EINVAL;
2020 goto out_err;
2021 }
2022 }
2023
2024 /* Initialize locations where the outputs are stored. */
2025 for (i = 0; i < so->num_outputs; i++) {
2026
2027 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2028 start_comp[i] = so->output[i].start_component;
2029 /* Lower outputs with dst_offset < start_component.
2030 *
2031 * We can only output 4D vectors with a write mask, e.g. we can
2032 * only output the W component at offset 3, etc. If we want
2033 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2034 * to move it to X and output X. */
2035 if (so->output[i].dst_offset < so->output[i].start_component) {
2036 unsigned tmp = r600_get_temp(ctx);
2037
2038 for (j = 0; j < so->output[i].num_components; j++) {
2039 struct r600_bytecode_alu alu;
2040 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2041 alu.op = ALU_OP1_MOV;
2042 alu.src[0].sel = so_gpr[i];
2043 alu.src[0].chan = so->output[i].start_component + j;
2044
2045 alu.dst.sel = tmp;
2046 alu.dst.chan = j;
2047 alu.dst.write = 1;
2048 if (j == so->output[i].num_components - 1)
2049 alu.last = 1;
2050 r = r600_bytecode_add_alu(ctx->bc, &alu);
2051 if (r)
2052 return r;
2053 }
2054 start_comp[i] = 0;
2055 so_gpr[i] = tmp;
2056 }
2057 }
2058
2059 /* Write outputs to buffers. */
2060 for (i = 0; i < so->num_outputs; i++) {
2061 struct r600_bytecode_output output;
2062
2063 if (stream != -1 && stream != so->output[i].output_buffer)
2064 continue;
2065
2066 memset(&output, 0, sizeof(struct r600_bytecode_output));
2067 output.gpr = so_gpr[i];
2068 output.elem_size = so->output[i].num_components - 1;
2069 if (output.elem_size == 2)
2070 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2071 output.array_base = so->output[i].dst_offset - start_comp[i];
2072 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2073 output.burst_count = 1;
2074 /* array_size is an upper limit for the burst_count
2075 * with MEM_STREAM instructions */
2076 output.array_size = 0xFFF;
2077 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2078
2079 if (ctx->bc->chip_class >= EVERGREEN) {
2080 switch (so->output[i].output_buffer) {
2081 case 0:
2082 output.op = CF_OP_MEM_STREAM0_BUF0;
2083 break;
2084 case 1:
2085 output.op = CF_OP_MEM_STREAM0_BUF1;
2086 break;
2087 case 2:
2088 output.op = CF_OP_MEM_STREAM0_BUF2;
2089 break;
2090 case 3:
2091 output.op = CF_OP_MEM_STREAM0_BUF3;
2092 break;
2093 }
2094 output.op += so->output[i].stream * 4;
2095 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2096 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2097 } else {
2098 switch (so->output[i].output_buffer) {
2099 case 0:
2100 output.op = CF_OP_MEM_STREAM0;
2101 break;
2102 case 1:
2103 output.op = CF_OP_MEM_STREAM1;
2104 break;
2105 case 2:
2106 output.op = CF_OP_MEM_STREAM2;
2107 break;
2108 case 3:
2109 output.op = CF_OP_MEM_STREAM3;
2110 break;
2111 }
2112 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2113 }
2114 r = r600_bytecode_add_output(ctx->bc, &output);
2115 if (r)
2116 goto out_err;
2117 }
2118 return 0;
2119 out_err:
2120 return r;
2121 }
2122
2123 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2124 {
2125 struct r600_bytecode_alu alu;
2126 unsigned reg;
2127
2128 if (!ctx->shader->vs_out_edgeflag)
2129 return;
2130
2131 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2132
2133 /* clamp(x, 0, 1) */
2134 memset(&alu, 0, sizeof(alu));
2135 alu.op = ALU_OP1_MOV;
2136 alu.src[0].sel = reg;
2137 alu.dst.sel = reg;
2138 alu.dst.write = 1;
2139 alu.dst.clamp = 1;
2140 alu.last = 1;
2141 r600_bytecode_add_alu(ctx->bc, &alu);
2142
2143 memset(&alu, 0, sizeof(alu));
2144 alu.op = ALU_OP1_FLT_TO_INT;
2145 alu.src[0].sel = reg;
2146 alu.dst.sel = reg;
2147 alu.dst.write = 1;
2148 alu.last = 1;
2149 r600_bytecode_add_alu(ctx->bc, &alu);
2150 }
2151
2152 static int generate_gs_copy_shader(struct r600_context *rctx,
2153 struct r600_pipe_shader *gs,
2154 struct pipe_stream_output_info *so)
2155 {
2156 struct r600_shader_ctx ctx = {};
2157 struct r600_shader *gs_shader = &gs->shader;
2158 struct r600_pipe_shader *cshader;
2159 int ocnt = gs_shader->noutput;
2160 struct r600_bytecode_alu alu;
2161 struct r600_bytecode_vtx vtx;
2162 struct r600_bytecode_output output;
2163 struct r600_bytecode_cf *cf_jump, *cf_pop,
2164 *last_exp_pos = NULL, *last_exp_param = NULL;
2165 int i, j, next_clip_pos = 61, next_param = 0;
2166 int ring;
2167 bool only_ring_0 = true;
2168 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2169 if (!cshader)
2170 return 0;
2171
2172 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2173 sizeof(struct r600_shader_io));
2174
2175 cshader->shader.noutput = ocnt;
2176
2177 ctx.shader = &cshader->shader;
2178 ctx.bc = &ctx.shader->bc;
2179 ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
2180
2181 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2182 rctx->screen->has_compressed_msaa_texturing);
2183
2184 ctx.bc->isa = rctx->isa;
2185
2186 cf_jump = NULL;
2187 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2188
2189 /* R0.x = R0.x & 0x3fffffff */
2190 memset(&alu, 0, sizeof(alu));
2191 alu.op = ALU_OP2_AND_INT;
2192 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2193 alu.src[1].value = 0x3fffffff;
2194 alu.dst.write = 1;
2195 r600_bytecode_add_alu(ctx.bc, &alu);
2196
2197 /* R0.y = R0.x >> 30 */
2198 memset(&alu, 0, sizeof(alu));
2199 alu.op = ALU_OP2_LSHR_INT;
2200 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2201 alu.src[1].value = 0x1e;
2202 alu.dst.chan = 1;
2203 alu.dst.write = 1;
2204 alu.last = 1;
2205 r600_bytecode_add_alu(ctx.bc, &alu);
2206
2207 /* fetch vertex data from GSVS ring */
2208 for (i = 0; i < ocnt; ++i) {
2209 struct r600_shader_io *out = &ctx.shader->output[i];
2210
2211 out->gpr = i + 1;
2212 out->ring_offset = i * 16;
2213
2214 memset(&vtx, 0, sizeof(vtx));
2215 vtx.op = FETCH_OP_VFETCH;
2216 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2217 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2218 vtx.mega_fetch_count = 16;
2219 vtx.offset = out->ring_offset;
2220 vtx.dst_gpr = out->gpr;
2221 vtx.src_gpr = 0;
2222 vtx.dst_sel_x = 0;
2223 vtx.dst_sel_y = 1;
2224 vtx.dst_sel_z = 2;
2225 vtx.dst_sel_w = 3;
2226 if (rctx->b.chip_class >= EVERGREEN) {
2227 vtx.use_const_fields = 1;
2228 } else {
2229 vtx.data_format = FMT_32_32_32_32_FLOAT;
2230 }
2231
2232 r600_bytecode_add_vtx(ctx.bc, &vtx);
2233 }
2234 ctx.temp_reg = i + 1;
2235 for (ring = 3; ring >= 0; --ring) {
2236 bool enabled = false;
2237 for (i = 0; i < so->num_outputs; i++) {
2238 if (so->output[i].stream == ring) {
2239 enabled = true;
2240 if (ring > 0)
2241 only_ring_0 = false;
2242 break;
2243 }
2244 }
2245 if (ring != 0 && !enabled) {
2246 cshader->shader.ring_item_sizes[ring] = 0;
2247 continue;
2248 }
2249
2250 if (cf_jump) {
2251 // Patch up jump label
2252 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2253 cf_pop = ctx.bc->cf_last;
2254
2255 cf_jump->cf_addr = cf_pop->id + 2;
2256 cf_jump->pop_count = 1;
2257 cf_pop->cf_addr = cf_pop->id + 2;
2258 cf_pop->pop_count = 1;
2259 }
2260
2261 /* PRED_SETE_INT __, R0.y, ring */
2262 memset(&alu, 0, sizeof(alu));
2263 alu.op = ALU_OP2_PRED_SETE_INT;
2264 alu.src[0].chan = 1;
2265 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2266 alu.src[1].value = ring;
2267 alu.execute_mask = 1;
2268 alu.update_pred = 1;
2269 alu.last = 1;
2270 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2271
2272 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2273 cf_jump = ctx.bc->cf_last;
2274
2275 if (enabled)
2276 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2277 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2278 }
2279
2280 /* bc adds nops - copy it */
2281 if (ctx.bc->chip_class == R600) {
2282 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2283 alu.op = ALU_OP0_NOP;
2284 alu.last = 1;
2285 r600_bytecode_add_alu(ctx.bc, &alu);
2286
2287 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2288 }
2289
2290 /* export vertex data */
2291 /* XXX factor out common code with r600_shader_from_tgsi ? */
2292 for (i = 0; i < ocnt; ++i) {
2293 struct r600_shader_io *out = &ctx.shader->output[i];
2294 bool instream0 = true;
2295 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2296 continue;
2297
2298 for (j = 0; j < so->num_outputs; j++) {
2299 if (so->output[j].register_index == i) {
2300 if (so->output[j].stream == 0)
2301 break;
2302 if (so->output[j].stream > 0)
2303 instream0 = false;
2304 }
2305 }
2306 if (!instream0)
2307 continue;
2308 memset(&output, 0, sizeof(output));
2309 output.gpr = out->gpr;
2310 output.elem_size = 3;
2311 output.swizzle_x = 0;
2312 output.swizzle_y = 1;
2313 output.swizzle_z = 2;
2314 output.swizzle_w = 3;
2315 output.burst_count = 1;
2316 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2317 output.op = CF_OP_EXPORT;
2318 switch (out->name) {
2319 case TGSI_SEMANTIC_POSITION:
2320 output.array_base = 60;
2321 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2322 break;
2323
2324 case TGSI_SEMANTIC_PSIZE:
2325 output.array_base = 61;
2326 if (next_clip_pos == 61)
2327 next_clip_pos = 62;
2328 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2329 output.swizzle_y = 7;
2330 output.swizzle_z = 7;
2331 output.swizzle_w = 7;
2332 ctx.shader->vs_out_misc_write = 1;
2333 ctx.shader->vs_out_point_size = 1;
2334 break;
2335 case TGSI_SEMANTIC_LAYER:
2336 if (out->spi_sid) {
2337 /* duplicate it as PARAM to pass to the pixel shader */
2338 output.array_base = next_param++;
2339 r600_bytecode_add_output(ctx.bc, &output);
2340 last_exp_param = ctx.bc->cf_last;
2341 }
2342 output.array_base = 61;
2343 if (next_clip_pos == 61)
2344 next_clip_pos = 62;
2345 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2346 output.swizzle_x = 7;
2347 output.swizzle_y = 7;
2348 output.swizzle_z = 0;
2349 output.swizzle_w = 7;
2350 ctx.shader->vs_out_misc_write = 1;
2351 ctx.shader->vs_out_layer = 1;
2352 break;
2353 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2354 if (out->spi_sid) {
2355 /* duplicate it as PARAM to pass to the pixel shader */
2356 output.array_base = next_param++;
2357 r600_bytecode_add_output(ctx.bc, &output);
2358 last_exp_param = ctx.bc->cf_last;
2359 }
2360 output.array_base = 61;
2361 if (next_clip_pos == 61)
2362 next_clip_pos = 62;
2363 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2364 ctx.shader->vs_out_misc_write = 1;
2365 ctx.shader->vs_out_viewport = 1;
2366 output.swizzle_x = 7;
2367 output.swizzle_y = 7;
2368 output.swizzle_z = 7;
2369 output.swizzle_w = 0;
2370 break;
2371 case TGSI_SEMANTIC_CLIPDIST:
2372 /* spi_sid is 0 for clipdistance outputs that were generated
2373 * for clipvertex - we don't need to pass them to PS */
2374 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2375 if (out->spi_sid) {
2376 /* duplicate it as PARAM to pass to the pixel shader */
2377 output.array_base = next_param++;
2378 r600_bytecode_add_output(ctx.bc, &output);
2379 last_exp_param = ctx.bc->cf_last;
2380 }
2381 output.array_base = next_clip_pos++;
2382 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2383 break;
2384 case TGSI_SEMANTIC_FOG:
2385 output.swizzle_y = 4; /* 0 */
2386 output.swizzle_z = 4; /* 0 */
2387 output.swizzle_w = 5; /* 1 */
2388 break;
2389 default:
2390 output.array_base = next_param++;
2391 break;
2392 }
2393 r600_bytecode_add_output(ctx.bc, &output);
2394 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2395 last_exp_param = ctx.bc->cf_last;
2396 else
2397 last_exp_pos = ctx.bc->cf_last;
2398 }
2399
2400 if (!last_exp_pos) {
2401 memset(&output, 0, sizeof(output));
2402 output.gpr = 0;
2403 output.elem_size = 3;
2404 output.swizzle_x = 7;
2405 output.swizzle_y = 7;
2406 output.swizzle_z = 7;
2407 output.swizzle_w = 7;
2408 output.burst_count = 1;
2409 output.type = 2;
2410 output.op = CF_OP_EXPORT;
2411 output.array_base = 60;
2412 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2413 r600_bytecode_add_output(ctx.bc, &output);
2414 last_exp_pos = ctx.bc->cf_last;
2415 }
2416
2417 if (!last_exp_param) {
2418 memset(&output, 0, sizeof(output));
2419 output.gpr = 0;
2420 output.elem_size = 3;
2421 output.swizzle_x = 7;
2422 output.swizzle_y = 7;
2423 output.swizzle_z = 7;
2424 output.swizzle_w = 7;
2425 output.burst_count = 1;
2426 output.type = 2;
2427 output.op = CF_OP_EXPORT;
2428 output.array_base = next_param++;
2429 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2430 r600_bytecode_add_output(ctx.bc, &output);
2431 last_exp_param = ctx.bc->cf_last;
2432 }
2433
2434 last_exp_pos->op = CF_OP_EXPORT_DONE;
2435 last_exp_param->op = CF_OP_EXPORT_DONE;
2436
2437 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2438 cf_pop = ctx.bc->cf_last;
2439
2440 cf_jump->cf_addr = cf_pop->id + 2;
2441 cf_jump->pop_count = 1;
2442 cf_pop->cf_addr = cf_pop->id + 2;
2443 cf_pop->pop_count = 1;
2444
2445 if (ctx.bc->chip_class == CAYMAN)
2446 cm_bytecode_add_cf_end(ctx.bc);
2447 else {
2448 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2449 ctx.bc->cf_last->end_of_program = 1;
2450 }
2451
2452 gs->gs_copy_shader = cshader;
2453 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2454
2455 ctx.bc->nstack = 1;
2456
2457 return r600_bytecode_build(ctx.bc);
2458 }
2459
2460 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2461 {
2462 if (ind) {
2463 struct r600_bytecode_alu alu;
2464 int r;
2465
2466 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2467 alu.op = ALU_OP2_ADD_INT;
2468 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2469 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2470 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2471 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2472 alu.dst.write = 1;
2473 alu.last = 1;
2474 r = r600_bytecode_add_alu(ctx->bc, &alu);
2475 if (r)
2476 return r;
2477 }
2478 return 0;
2479 }
2480
2481 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind)
2482 {
2483 struct r600_bytecode_output output;
2484 int i, k, ring_offset;
2485 int effective_stream = stream == -1 ? 0 : stream;
2486 int idx = 0;
2487
2488 for (i = 0; i < ctx->shader->noutput; i++) {
2489 if (ctx->gs_for_vs) {
2490 /* for ES we need to lookup corresponding ring offset expected by GS
2491 * (map this output to GS input by name and sid) */
2492 /* FIXME precompute offsets */
2493 ring_offset = -1;
2494 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2495 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2496 struct r600_shader_io *out = &ctx->shader->output[i];
2497 if (in->name == out->name && in->sid == out->sid)
2498 ring_offset = in->ring_offset;
2499 }
2500
2501 if (ring_offset == -1)
2502 continue;
2503 } else {
2504 ring_offset = idx * 16;
2505 idx++;
2506 }
2507
2508 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2509 continue;
2510 /* next_ring_offset after parsing input decls contains total size of
2511 * single vertex data, gs_next_vertex - current vertex index */
2512 if (!ind)
2513 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2514
2515 memset(&output, 0, sizeof(struct r600_bytecode_output));
2516 output.gpr = ctx->shader->output[i].gpr;
2517 output.elem_size = 3;
2518 output.comp_mask = 0xF;
2519 output.burst_count = 1;
2520
2521 if (ind)
2522 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2523 else
2524 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2525
2526 switch (stream) {
2527 default:
2528 case 0:
2529 output.op = CF_OP_MEM_RING; break;
2530 case 1:
2531 output.op = CF_OP_MEM_RING1; break;
2532 case 2:
2533 output.op = CF_OP_MEM_RING2; break;
2534 case 3:
2535 output.op = CF_OP_MEM_RING3; break;
2536 }
2537
2538 if (ind) {
2539 output.array_base = ring_offset >> 2; /* in dwords */
2540 output.array_size = 0xfff;
2541 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2542 } else
2543 output.array_base = ring_offset >> 2; /* in dwords */
2544 r600_bytecode_add_output(ctx->bc, &output);
2545 }
2546
2547 ++ctx->gs_next_vertex;
2548 return 0;
2549 }
2550
2551
2552 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2553 {
2554 int r;
2555 struct r600_bytecode_vtx vtx;
2556 int temp_val = ctx->temp_reg;
2557 /* need to store the TCS output somewhere */
2558 r = single_alu_op2(ctx, ALU_OP1_MOV,
2559 temp_val, 0,
2560 V_SQ_ALU_SRC_LITERAL, 0,
2561 0, 0);
2562 if (r)
2563 return r;
2564
2565 /* used by VS/TCS */
2566 if (ctx->tess_input_info) {
2567 /* fetch tcs input values into resv space */
2568 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2569 vtx.op = FETCH_OP_VFETCH;
2570 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2571 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2572 vtx.mega_fetch_count = 16;
2573 vtx.data_format = FMT_32_32_32_32;
2574 vtx.num_format_all = 2;
2575 vtx.format_comp_all = 1;
2576 vtx.use_const_fields = 0;
2577 vtx.endian = r600_endian_swap(32);
2578 vtx.srf_mode_all = 1;
2579 vtx.offset = 0;
2580 vtx.dst_gpr = ctx->tess_input_info;
2581 vtx.dst_sel_x = 0;
2582 vtx.dst_sel_y = 1;
2583 vtx.dst_sel_z = 2;
2584 vtx.dst_sel_w = 3;
2585 vtx.src_gpr = temp_val;
2586 vtx.src_sel_x = 0;
2587
2588 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2589 if (r)
2590 return r;
2591 }
2592
2593 /* used by TCS/TES */
2594 if (ctx->tess_output_info) {
2595 /* fetch tcs output values into resv space */
2596 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2597 vtx.op = FETCH_OP_VFETCH;
2598 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2599 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2600 vtx.mega_fetch_count = 16;
2601 vtx.data_format = FMT_32_32_32_32;
2602 vtx.num_format_all = 2;
2603 vtx.format_comp_all = 1;
2604 vtx.use_const_fields = 0;
2605 vtx.endian = r600_endian_swap(32);
2606 vtx.srf_mode_all = 1;
2607 vtx.offset = 16;
2608 vtx.dst_gpr = ctx->tess_output_info;
2609 vtx.dst_sel_x = 0;
2610 vtx.dst_sel_y = 1;
2611 vtx.dst_sel_z = 2;
2612 vtx.dst_sel_w = 3;
2613 vtx.src_gpr = temp_val;
2614 vtx.src_sel_x = 0;
2615
2616 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2617 if (r)
2618 return r;
2619 }
2620 return 0;
2621 }
2622
2623 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2624 {
2625 int i, j, r;
2626 int temp_reg;
2627
2628 /* fetch tcs input values into input_vals */
2629 ctx->tess_input_info = r600_get_temp(ctx);
2630 ctx->tess_output_info = 0;
2631 r = r600_fetch_tess_io_info(ctx);
2632 if (r)
2633 return r;
2634
2635 temp_reg = r600_get_temp(ctx);
2636 /* dst reg contains LDS address stride * idx */
2637 /* MUL vertexID, vertex_dw_stride */
2638 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2639 temp_reg, 0,
2640 ctx->tess_input_info, 1,
2641 0, 1); /* rel id in r0.y? */
2642 if (r)
2643 return r;
2644
2645 for (i = 0; i < ctx->shader->noutput; i++) {
2646 struct r600_bytecode_alu alu;
2647 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2648
2649 if (param) {
2650 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2651 temp_reg, 1,
2652 temp_reg, 0,
2653 V_SQ_ALU_SRC_LITERAL, param * 16);
2654 if (r)
2655 return r;
2656 }
2657
2658 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2659 temp_reg, 2,
2660 temp_reg, param ? 1 : 0,
2661 V_SQ_ALU_SRC_LITERAL, 8);
2662 if (r)
2663 return r;
2664
2665
2666 for (j = 0; j < 2; j++) {
2667 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2668 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2669 alu.op = LDS_OP3_LDS_WRITE_REL;
2670 alu.src[0].sel = temp_reg;
2671 alu.src[0].chan = chan;
2672 alu.src[1].sel = ctx->shader->output[i].gpr;
2673 alu.src[1].chan = j * 2;
2674 alu.src[2].sel = ctx->shader->output[i].gpr;
2675 alu.src[2].chan = (j * 2) + 1;
2676 alu.last = 1;
2677 alu.dst.chan = 0;
2678 alu.lds_idx = 1;
2679 alu.is_lds_idx_op = true;
2680 r = r600_bytecode_add_alu(ctx->bc, &alu);
2681 if (r)
2682 return r;
2683 }
2684 }
2685 return 0;
2686 }
2687
2688 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
2689 {
2690 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2691 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
2692 int i, r, lasti;
2693 int temp_reg = r600_get_temp(ctx);
2694 struct r600_bytecode_alu alu;
2695 unsigned write_mask = dst->Register.WriteMask;
2696
2697 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
2698 return 0;
2699
2700 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
2701 if (r)
2702 return r;
2703
2704 /* the base address is now in temp.x */
2705 r = r600_get_byte_address(ctx, temp_reg,
2706 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
2707 if (r)
2708 return r;
2709
2710 /* LDS write */
2711 lasti = tgsi_last_instruction(write_mask);
2712 for (i = 1; i <= lasti; i++) {
2713
2714 if (!(write_mask & (1 << i)))
2715 continue;
2716 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2717 temp_reg, i,
2718 temp_reg, 0,
2719 V_SQ_ALU_SRC_LITERAL, 4 * i);
2720 if (r)
2721 return r;
2722 }
2723
2724 for (i = 0; i <= lasti; i++) {
2725 if (!(write_mask & (1 << i)))
2726 continue;
2727
2728 if ((i == 0 && ((write_mask & 3) == 3)) ||
2729 (i == 2 && ((write_mask & 0xc) == 0xc))) {
2730 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2731 alu.op = LDS_OP3_LDS_WRITE_REL;
2732 alu.src[0].sel = temp_reg;
2733 alu.src[0].chan = i;
2734
2735 alu.src[1].sel = dst->Register.Index;
2736 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2737 alu.src[1].chan = i;
2738
2739 alu.src[2].sel = dst->Register.Index;
2740 alu.src[2].sel += ctx->file_offset[dst->Register.File];
2741 alu.src[2].chan = i + 1;
2742 alu.lds_idx = 1;
2743 alu.dst.chan = 0;
2744 alu.last = 1;
2745 alu.is_lds_idx_op = true;
2746 r = r600_bytecode_add_alu(ctx->bc, &alu);
2747 if (r)
2748 return r;
2749 i += 1;
2750 continue;
2751 }
2752 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2753 alu.op = LDS_OP2_LDS_WRITE;
2754 alu.src[0].sel = temp_reg;
2755 alu.src[0].chan = i;
2756
2757 alu.src[1].sel = dst->Register.Index;
2758 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2759 alu.src[1].chan = i;
2760
2761 alu.src[2].sel = V_SQ_ALU_SRC_0;
2762 alu.dst.chan = 0;
2763 alu.last = 1;
2764 alu.is_lds_idx_op = true;
2765 r = r600_bytecode_add_alu(ctx->bc, &alu);
2766 if (r)
2767 return r;
2768 }
2769 return 0;
2770 }
2771
2772 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
2773 int output_idx)
2774 {
2775 int param;
2776 unsigned temp_reg = r600_get_temp(ctx);
2777 unsigned name = ctx->shader->output[output_idx].name;
2778 int dreg = ctx->shader->output[output_idx].gpr;
2779 int r;
2780
2781 param = r600_get_lds_unique_index(name, 0);
2782 r = get_lds_offset0(ctx, 1, temp_reg, true);
2783 if (r)
2784 return r;
2785
2786 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2787 temp_reg, 0,
2788 temp_reg, 0,
2789 V_SQ_ALU_SRC_LITERAL, param * 16);
2790 if (r)
2791 return r;
2792
2793 do_lds_fetch_values(ctx, temp_reg, dreg);
2794 return 0;
2795 }
2796
2797 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
2798 {
2799 unsigned i;
2800 int stride, outer_comps, inner_comps;
2801 int tessinner_idx = -1, tessouter_idx = -1;
2802 int r;
2803 int temp_reg = r600_get_temp(ctx);
2804 int treg[3] = {-1, -1, -1};
2805 struct r600_bytecode_alu alu;
2806 struct r600_bytecode_cf *cf_jump, *cf_pop;
2807
2808 /* only execute factor emission for invocation 0 */
2809 /* PRED_SETE_INT __, R0.x, 0 */
2810 memset(&alu, 0, sizeof(alu));
2811 alu.op = ALU_OP2_PRED_SETE_INT;
2812 alu.src[0].chan = 2;
2813 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2814 alu.execute_mask = 1;
2815 alu.update_pred = 1;
2816 alu.last = 1;
2817 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2818
2819 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
2820 cf_jump = ctx->bc->cf_last;
2821
2822 treg[0] = r600_get_temp(ctx);
2823 switch (ctx->shader->tcs_prim_mode) {
2824 case PIPE_PRIM_LINES:
2825 stride = 8; /* 2 dwords, 1 vec2 store */
2826 outer_comps = 2;
2827 inner_comps = 0;
2828 break;
2829 case PIPE_PRIM_TRIANGLES:
2830 stride = 16; /* 4 dwords, 1 vec4 store */
2831 outer_comps = 3;
2832 inner_comps = 1;
2833 treg[1] = r600_get_temp(ctx);
2834 break;
2835 case PIPE_PRIM_QUADS:
2836 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2837 outer_comps = 4;
2838 inner_comps = 2;
2839 treg[1] = r600_get_temp(ctx);
2840 treg[2] = r600_get_temp(ctx);
2841 break;
2842 default:
2843 assert(0);
2844 return -1;
2845 }
2846
2847 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2848 /* TF_WRITE takes index in R.x, value in R.y */
2849 for (i = 0; i < ctx->shader->noutput; i++) {
2850 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSINNER)
2851 tessinner_idx = i;
2852 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSOUTER)
2853 tessouter_idx = i;
2854 }
2855
2856 if (tessouter_idx == -1)
2857 return -1;
2858
2859 if (tessinner_idx == -1 && inner_comps)
2860 return -1;
2861
2862 if (tessouter_idx != -1) {
2863 r = r600_tess_factor_read(ctx, tessouter_idx);
2864 if (r)
2865 return r;
2866 }
2867
2868 if (tessinner_idx != -1) {
2869 r = r600_tess_factor_read(ctx, tessinner_idx);
2870 if (r)
2871 return r;
2872 }
2873
2874 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2875 /* r.x = relpatchid(r0.y) * tf_stride */
2876
2877 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2878 /* add incoming r0.w to it: t.x = t.x + r0.w */
2879 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2880 temp_reg, 0,
2881 0, 1,
2882 V_SQ_ALU_SRC_LITERAL, stride,
2883 0, 3);
2884 if (r)
2885 return r;
2886
2887 for (i = 0; i < outer_comps + inner_comps; i++) {
2888 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
2889 int out_comp = i >= outer_comps ? i - outer_comps : i;
2890
2891 if (ctx->shader->tcs_prim_mode == PIPE_PRIM_LINES) {
2892 if (out_comp == 1)
2893 out_comp = 0;
2894 else if (out_comp == 0)
2895 out_comp = 1;
2896 }
2897
2898 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2899 treg[i / 2], (2 * (i % 2)),
2900 temp_reg, 0,
2901 V_SQ_ALU_SRC_LITERAL, 4 * i);
2902 if (r)
2903 return r;
2904 r = single_alu_op2(ctx, ALU_OP1_MOV,
2905 treg[i / 2], 1 + (2 * (i%2)),
2906 ctx->shader->output[out_idx].gpr, out_comp,
2907 0, 0);
2908 if (r)
2909 return r;
2910 }
2911 for (i = 0; i < outer_comps + inner_comps; i++) {
2912 struct r600_bytecode_gds gds;
2913
2914 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
2915 gds.src_gpr = treg[i / 2];
2916 gds.src_sel_x = 2 * (i % 2);
2917 gds.src_sel_y = 1 + (2 * (i % 2));
2918 gds.src_sel_z = 4;
2919 gds.dst_sel_x = 7;
2920 gds.dst_sel_y = 7;
2921 gds.dst_sel_z = 7;
2922 gds.dst_sel_w = 7;
2923 gds.op = FETCH_OP_TF_WRITE;
2924 r = r600_bytecode_add_gds(ctx->bc, &gds);
2925 if (r)
2926 return r;
2927 }
2928
2929 // Patch up jump label
2930 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
2931 cf_pop = ctx->bc->cf_last;
2932
2933 cf_jump->cf_addr = cf_pop->id + 2;
2934 cf_jump->pop_count = 1;
2935 cf_pop->cf_addr = cf_pop->id + 2;
2936 cf_pop->pop_count = 1;
2937
2938 return 0;
2939 }
2940
2941 /*
2942 * We have to work out the thread ID for load and atomic
2943 * operations, which store the returned value to an index
2944 * in an intermediate buffer.
2945 * The index is calculated by taking the thread id,
2946 * calculated from the MBCNT instructions.
2947 * Then the shader engine ID is multiplied by 256,
2948 * and the wave id is added.
2949 * Then the result is multipled by 64 and thread id is
2950 * added.
2951 */
2952 static int load_thread_id_gpr(struct r600_shader_ctx *ctx)
2953 {
2954 struct r600_bytecode_alu alu;
2955 int r;
2956
2957 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2958 alu.op = ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT;
2959 alu.dst.sel = ctx->temp_reg;
2960 alu.dst.chan = 0;
2961 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
2962 alu.src[0].value = 0xffffffff;
2963 alu.dst.write = 1;
2964 r = r600_bytecode_add_alu(ctx->bc, &alu);
2965 if (r)
2966 return r;
2967
2968 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2969 alu.op = ALU_OP1_MBCNT_32HI_INT;
2970 alu.dst.sel = ctx->temp_reg;
2971 alu.dst.chan = 1;
2972 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
2973 alu.src[0].value = 0xffffffff;
2974 alu.dst.write = 1;
2975 r = r600_bytecode_add_alu(ctx->bc, &alu);
2976 if (r)
2977 return r;
2978
2979 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2980 alu.op = ALU_OP3_MULADD_UINT24;
2981 alu.dst.sel = ctx->temp_reg;
2982 alu.dst.chan = 2;
2983 alu.src[0].sel = EG_V_SQ_ALU_SRC_SE_ID;
2984 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2985 alu.src[1].value = 256;
2986 alu.src[2].sel = EG_V_SQ_ALU_SRC_HW_WAVE_ID;
2987 alu.dst.write = 1;
2988 alu.is_op3 = 1;
2989 alu.last = 1;
2990 r = r600_bytecode_add_alu(ctx->bc, &alu);
2991 if (r)
2992 return r;
2993
2994 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2995 ctx->thread_id_gpr, 1,
2996 ctx->temp_reg, 2,
2997 V_SQ_ALU_SRC_LITERAL, 0x40,
2998 ctx->temp_reg, 0);
2999 if (r)
3000 return r;
3001 return 0;
3002 }
3003
3004 static int r600_shader_from_tgsi(struct r600_context *rctx,
3005 struct r600_pipe_shader *pipeshader,
3006 union r600_shader_key key)
3007 {
3008 struct r600_screen *rscreen = rctx->screen;
3009 struct r600_shader *shader = &pipeshader->shader;
3010 struct tgsi_token *tokens = pipeshader->selector->tokens;
3011 struct pipe_stream_output_info so = pipeshader->selector->so;
3012 struct tgsi_full_immediate *immediate;
3013 struct r600_shader_ctx ctx;
3014 struct r600_bytecode_output output[ARRAY_SIZE(shader->output)];
3015 unsigned output_done, noutput;
3016 unsigned opcode;
3017 int i, j, k, r = 0;
3018 int next_param_base = 0, next_clip_base;
3019 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
3020 bool indirect_gprs;
3021 bool ring_outputs = false;
3022 bool lds_outputs = false;
3023 bool lds_inputs = false;
3024 bool pos_emitted = false;
3025
3026 ctx.bc = &shader->bc;
3027 ctx.shader = shader;
3028 ctx.native_integers = true;
3029
3030 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
3031 rscreen->has_compressed_msaa_texturing);
3032 ctx.tokens = tokens;
3033 tgsi_scan_shader(tokens, &ctx.info);
3034 shader->indirect_files = ctx.info.indirect_files;
3035
3036 shader->uses_doubles = ctx.info.uses_doubles;
3037 shader->uses_atomics = ctx.info.file_mask[TGSI_FILE_HW_ATOMIC];
3038 shader->nsys_inputs = 0;
3039
3040 shader->uses_images = ctx.info.file_count[TGSI_FILE_IMAGE] > 0;
3041 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
3042 tgsi_parse_init(&ctx.parse, tokens);
3043 ctx.type = ctx.info.processor;
3044 shader->processor_type = ctx.type;
3045 ctx.bc->type = shader->processor_type;
3046
3047 switch (ctx.type) {
3048 case PIPE_SHADER_VERTEX:
3049 shader->vs_as_gs_a = key.vs.as_gs_a;
3050 shader->vs_as_es = key.vs.as_es;
3051 shader->vs_as_ls = key.vs.as_ls;
3052 shader->atomic_base = key.vs.first_atomic_counter;
3053 if (shader->vs_as_es)
3054 ring_outputs = true;
3055 if (shader->vs_as_ls)
3056 lds_outputs = true;
3057 break;
3058 case PIPE_SHADER_GEOMETRY:
3059 ring_outputs = true;
3060 shader->atomic_base = key.gs.first_atomic_counter;
3061 shader->gs_tri_strip_adj_fix = key.gs.tri_strip_adj_fix;
3062 break;
3063 case PIPE_SHADER_TESS_CTRL:
3064 shader->tcs_prim_mode = key.tcs.prim_mode;
3065 shader->atomic_base = key.tcs.first_atomic_counter;
3066 lds_outputs = true;
3067 lds_inputs = true;
3068 break;
3069 case PIPE_SHADER_TESS_EVAL:
3070 shader->tes_as_es = key.tes.as_es;
3071 shader->atomic_base = key.tes.first_atomic_counter;
3072 lds_inputs = true;
3073 if (shader->tes_as_es)
3074 ring_outputs = true;
3075 break;
3076 case PIPE_SHADER_FRAGMENT:
3077 shader->two_side = key.ps.color_two_side;
3078 shader->atomic_base = key.ps.first_atomic_counter;
3079 shader->rat_base = key.ps.nr_cbufs;
3080 break;
3081 default:
3082 break;
3083 }
3084
3085 if (shader->vs_as_es || shader->tes_as_es) {
3086 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
3087 } else {
3088 ctx.gs_for_vs = NULL;
3089 }
3090
3091 ctx.next_ring_offset = 0;
3092 ctx.gs_out_ring_offset = 0;
3093 ctx.gs_next_vertex = 0;
3094 ctx.gs_stream_output_info = &so;
3095
3096 ctx.face_gpr = -1;
3097 ctx.fixed_pt_position_gpr = -1;
3098 ctx.fragcoord_input = -1;
3099 ctx.colors_used = 0;
3100 ctx.clip_vertex_write = 0;
3101
3102 shader->nr_ps_color_exports = 0;
3103 shader->nr_ps_max_color_exports = 0;
3104
3105
3106 /* register allocations */
3107 /* Values [0,127] correspond to GPR[0..127].
3108 * Values [128,159] correspond to constant buffer bank 0
3109 * Values [160,191] correspond to constant buffer bank 1
3110 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3111 * Values [256,287] correspond to constant buffer bank 2 (EG)
3112 * Values [288,319] correspond to constant buffer bank 3 (EG)
3113 * Other special values are shown in the list below.
3114 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3115 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3116 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3117 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3118 * 248 SQ_ALU_SRC_0: special constant 0.0.
3119 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3120 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3121 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3122 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3123 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3124 * 254 SQ_ALU_SRC_PV: previous vector result.
3125 * 255 SQ_ALU_SRC_PS: previous scalar result.
3126 */
3127 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3128 ctx.file_offset[i] = 0;
3129 }
3130
3131 if (ctx.type == PIPE_SHADER_VERTEX) {
3132
3133 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3134 if (ctx.info.num_inputs)
3135 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3136 }
3137 if (ctx.type == PIPE_SHADER_FRAGMENT) {
3138 if (ctx.bc->chip_class >= EVERGREEN)
3139 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3140 else
3141 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3142 }
3143 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3144 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3145 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3146 }
3147 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3148 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3149 if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3150 bool add_tesscoord = false, add_tess_inout = false;
3151 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3152 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3153 /* if we have tesscoord save one reg */
3154 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3155 add_tesscoord = true;
3156 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3157 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3158 add_tess_inout = true;
3159 }
3160 if (add_tesscoord || add_tess_inout)
3161 ctx.file_offset[TGSI_FILE_INPUT]++;
3162 if (add_tess_inout)
3163 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3164 }
3165
3166 ctx.file_offset[TGSI_FILE_OUTPUT] =
3167 ctx.file_offset[TGSI_FILE_INPUT] +
3168 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3169 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3170 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3171
3172 /* Outside the GPR range. This will be translated to one of the
3173 * kcache banks later. */
3174 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3175
3176 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3177 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3178 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
3179 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
3180 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
3181
3182 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3183 ctx.tess_input_info = ctx.bc->ar_reg + 3;
3184 ctx.tess_output_info = ctx.bc->ar_reg + 4;
3185 ctx.temp_reg = ctx.bc->ar_reg + 5;
3186 } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3187 ctx.tess_input_info = 0;
3188 ctx.tess_output_info = ctx.bc->ar_reg + 3;
3189 ctx.temp_reg = ctx.bc->ar_reg + 4;
3190 } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
3191 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
3192 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
3193 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
3194 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
3195 ctx.temp_reg = ctx.bc->ar_reg + 7;
3196 if (ctx.shader->gs_tri_strip_adj_fix) {
3197 ctx.gs_rotated_input[0] = ctx.bc->ar_reg + 7;
3198 ctx.gs_rotated_input[1] = ctx.bc->ar_reg + 8;
3199 ctx.temp_reg += 2;
3200 } else {
3201 ctx.gs_rotated_input[0] = 0;
3202 ctx.gs_rotated_input[1] = 1;
3203 }
3204 } else {
3205 ctx.temp_reg = ctx.bc->ar_reg + 3;
3206 }
3207
3208 if (shader->uses_images && ctx.type == PIPE_SHADER_FRAGMENT) {
3209 ctx.thread_id_gpr = ctx.temp_reg;
3210 ctx.temp_reg++;
3211 } else
3212 ctx.thread_id_gpr = 0;
3213
3214 shader->max_arrays = 0;
3215 shader->num_arrays = 0;
3216 if (indirect_gprs) {
3217
3218 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3219 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3220 ctx.file_offset[TGSI_FILE_OUTPUT] -
3221 ctx.file_offset[TGSI_FILE_INPUT],
3222 0x0F);
3223 }
3224 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3225 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3226 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3227 ctx.file_offset[TGSI_FILE_OUTPUT],
3228 0x0F);
3229 }
3230 }
3231
3232 ctx.nliterals = 0;
3233 ctx.literals = NULL;
3234
3235 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3236 ctx.info.colors_written == 1;
3237 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3238 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3239
3240 if (shader->vs_as_gs_a)
3241 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3242
3243 if (ctx.type == PIPE_SHADER_TESS_EVAL)
3244 r600_fetch_tess_io_info(&ctx);
3245
3246 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3247 tgsi_parse_token(&ctx.parse);
3248 switch (ctx.parse.FullToken.Token.Type) {
3249 case TGSI_TOKEN_TYPE_IMMEDIATE:
3250 immediate = &ctx.parse.FullToken.FullImmediate;
3251 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3252 if(ctx.literals == NULL) {
3253 r = -ENOMEM;
3254 goto out_err;
3255 }
3256 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3257 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3258 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3259 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3260 ctx.nliterals++;
3261 break;
3262 case TGSI_TOKEN_TYPE_DECLARATION:
3263 r = tgsi_declaration(&ctx);
3264 if (r)
3265 goto out_err;
3266 break;
3267 case TGSI_TOKEN_TYPE_INSTRUCTION:
3268 case TGSI_TOKEN_TYPE_PROPERTY:
3269 break;
3270 default:
3271 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3272 r = -EINVAL;
3273 goto out_err;
3274 }
3275 }
3276
3277 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3278 shader->ring_item_sizes[1] = 0;
3279 shader->ring_item_sizes[2] = 0;
3280 shader->ring_item_sizes[3] = 0;
3281
3282 /* Process two side if needed */
3283 if (shader->two_side && ctx.colors_used) {
3284 int i, count = ctx.shader->ninput;
3285 unsigned next_lds_loc = ctx.shader->nlds;
3286
3287 /* additional inputs will be allocated right after the existing inputs,
3288 * we won't need them after the color selection, so we don't need to
3289 * reserve these gprs for the rest of the shader code and to adjust
3290 * output offsets etc. */
3291 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3292 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3293
3294 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3295 if (ctx.face_gpr == -1) {
3296 i = ctx.shader->ninput++;
3297 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3298 ctx.shader->input[i].spi_sid = 0;
3299 ctx.shader->input[i].gpr = gpr++;
3300 ctx.face_gpr = ctx.shader->input[i].gpr;
3301 }
3302
3303 for (i = 0; i < count; i++) {
3304 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3305 int ni = ctx.shader->ninput++;
3306 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3307 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3308 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3309 ctx.shader->input[ni].gpr = gpr++;
3310 // TGSI to LLVM needs to know the lds position of inputs.
3311 // Non LLVM path computes it later (in process_twoside_color)
3312 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3313 ctx.shader->input[i].back_color_input = ni;
3314 if (ctx.bc->chip_class >= EVERGREEN) {
3315 if ((r = evergreen_interp_input(&ctx, ni)))
3316 return r;
3317 }
3318 }
3319 }
3320 }
3321
3322 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3323 shader->nr_ps_max_color_exports = 8;
3324
3325 if (ctx.fragcoord_input >= 0) {
3326 if (ctx.bc->chip_class == CAYMAN) {
3327 for (j = 0 ; j < 4; j++) {
3328 struct r600_bytecode_alu alu;
3329 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3330 alu.op = ALU_OP1_RECIP_IEEE;
3331 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3332 alu.src[0].chan = 3;
3333
3334 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3335 alu.dst.chan = j;
3336 alu.dst.write = (j == 3);
3337 alu.last = 1;
3338 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3339 return r;
3340 }
3341 } else {
3342 struct r600_bytecode_alu alu;
3343 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3344 alu.op = ALU_OP1_RECIP_IEEE;
3345 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3346 alu.src[0].chan = 3;
3347
3348 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3349 alu.dst.chan = 3;
3350 alu.dst.write = 1;
3351 alu.last = 1;
3352 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3353 return r;
3354 }
3355 }
3356
3357 if (ctx.thread_id_gpr) {
3358 load_thread_id_gpr(&ctx);
3359 }
3360
3361 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3362 struct r600_bytecode_alu alu;
3363 int r;
3364
3365 /* GS thread with no output workaround - emit a cut at start of GS */
3366 if (ctx.bc->chip_class == R600)
3367 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3368
3369 for (j = 0; j < 4; j++) {
3370 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3371 alu.op = ALU_OP1_MOV;
3372 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3373 alu.src[0].value = 0;
3374 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3375 alu.dst.write = 1;
3376 alu.last = 1;
3377 r = r600_bytecode_add_alu(ctx.bc, &alu);
3378 if (r)
3379 return r;
3380 }
3381
3382 if (ctx.shader->gs_tri_strip_adj_fix) {
3383 r = single_alu_op2(&ctx, ALU_OP2_AND_INT,
3384 ctx.gs_rotated_input[0], 2,
3385 0, 2,
3386 V_SQ_ALU_SRC_LITERAL, 1);
3387 if (r)
3388 return r;
3389
3390 for (i = 0; i < 6; i++) {
3391 int rotated = (i + 4) % 6;
3392 int offset_reg = i / 3;
3393 int offset_chan = i % 3;
3394 int rotated_offset_reg = rotated / 3;
3395 int rotated_offset_chan = rotated % 3;
3396
3397 if (offset_reg == 0 && offset_chan == 2)
3398 offset_chan = 3;
3399 if (rotated_offset_reg == 0 && rotated_offset_chan == 2)
3400 rotated_offset_chan = 3;
3401
3402 r = single_alu_op3(&ctx, ALU_OP3_CNDE_INT,
3403 ctx.gs_rotated_input[offset_reg], offset_chan,
3404 ctx.gs_rotated_input[0], 2,
3405 offset_reg, offset_chan,
3406 rotated_offset_reg, rotated_offset_chan);
3407 if (r)
3408 return r;
3409 }
3410 }
3411 }
3412
3413 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3414 r600_fetch_tess_io_info(&ctx);
3415
3416 if (shader->two_side && ctx.colors_used) {
3417 if ((r = process_twoside_color_inputs(&ctx)))
3418 return r;
3419 }
3420
3421 tgsi_parse_init(&ctx.parse, tokens);
3422 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3423 tgsi_parse_token(&ctx.parse);
3424 switch (ctx.parse.FullToken.Token.Type) {
3425 case TGSI_TOKEN_TYPE_INSTRUCTION:
3426 r = tgsi_is_supported(&ctx);
3427 if (r)
3428 goto out_err;
3429 ctx.max_driver_temp_used = 0;
3430 /* reserve first tmp for everyone */
3431 r600_get_temp(&ctx);
3432
3433 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3434 if ((r = tgsi_split_constant(&ctx)))
3435 goto out_err;
3436 if ((r = tgsi_split_literal_constant(&ctx)))
3437 goto out_err;
3438 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3439 if ((r = tgsi_split_gs_inputs(&ctx)))
3440 goto out_err;
3441 } else if (lds_inputs) {
3442 if ((r = tgsi_split_lds_inputs(&ctx)))
3443 goto out_err;
3444 }
3445 if (ctx.bc->chip_class == CAYMAN)
3446 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3447 else if (ctx.bc->chip_class >= EVERGREEN)
3448 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3449 else
3450 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3451 r = ctx.inst_info->process(&ctx);
3452 if (r)
3453 goto out_err;
3454
3455 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3456 r = r600_store_tcs_output(&ctx);
3457 if (r)
3458 goto out_err;
3459 }
3460 break;
3461 default:
3462 break;
3463 }
3464 }
3465
3466 /* Reset the temporary register counter. */
3467 ctx.max_driver_temp_used = 0;
3468
3469 noutput = shader->noutput;
3470
3471 if (!ring_outputs && ctx.clip_vertex_write) {
3472 unsigned clipdist_temp[2];
3473
3474 clipdist_temp[0] = r600_get_temp(&ctx);
3475 clipdist_temp[1] = r600_get_temp(&ctx);
3476
3477 /* need to convert a clipvertex write into clipdistance writes and not export
3478 the clip vertex anymore */
3479
3480 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3481 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3482 shader->output[noutput].gpr = clipdist_temp[0];
3483 noutput++;
3484 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3485 shader->output[noutput].gpr = clipdist_temp[1];
3486 noutput++;
3487
3488 /* reset spi_sid for clipvertex output to avoid confusing spi */
3489 shader->output[ctx.cv_output].spi_sid = 0;
3490
3491 shader->clip_dist_write = 0xFF;
3492
3493 for (i = 0; i < 8; i++) {
3494 int oreg = i >> 2;
3495 int ochan = i & 3;
3496
3497 for (j = 0; j < 4; j++) {
3498 struct r600_bytecode_alu alu;
3499 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3500 alu.op = ALU_OP2_DOT4;
3501 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3502 alu.src[0].chan = j;
3503
3504 alu.src[1].sel = 512 + i;
3505 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3506 alu.src[1].chan = j;
3507
3508 alu.dst.sel = clipdist_temp[oreg];
3509 alu.dst.chan = j;
3510 alu.dst.write = (j == ochan);
3511 if (j == 3)
3512 alu.last = 1;
3513 r = r600_bytecode_add_alu(ctx.bc, &alu);
3514 if (r)
3515 return r;
3516 }
3517 }
3518 }
3519
3520 /* Add stream outputs. */
3521 if (so.num_outputs) {
3522 bool emit = false;
3523 if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
3524 emit = true;
3525 if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
3526 emit = true;
3527 if (emit)
3528 emit_streamout(&ctx, &so, -1, NULL);
3529 }
3530 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3531 convert_edgeflag_to_int(&ctx);
3532
3533 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3534 r600_emit_tess_factor(&ctx);
3535
3536 if (lds_outputs) {
3537 if (ctx.type == PIPE_SHADER_VERTEX) {
3538 if (ctx.shader->noutput)
3539 emit_lds_vs_writes(&ctx);
3540 }
3541 } else if (ring_outputs) {
3542 if (shader->vs_as_es || shader->tes_as_es) {
3543 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3544 ctx.gs_export_gpr_tregs[1] = -1;
3545 ctx.gs_export_gpr_tregs[2] = -1;
3546 ctx.gs_export_gpr_tregs[3] = -1;
3547
3548 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3549 }
3550 } else {
3551 /* Export output */
3552 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3553
3554 for (i = 0, j = 0; i < noutput; i++, j++) {
3555 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3556 output[j].gpr = shader->output[i].gpr;
3557 output[j].elem_size = 3;
3558 output[j].swizzle_x = 0;
3559 output[j].swizzle_y = 1;
3560 output[j].swizzle_z = 2;
3561 output[j].swizzle_w = 3;
3562 output[j].burst_count = 1;
3563 output[j].type = -1;
3564 output[j].op = CF_OP_EXPORT;
3565 switch (ctx.type) {
3566 case PIPE_SHADER_VERTEX:
3567 case PIPE_SHADER_TESS_EVAL:
3568 switch (shader->output[i].name) {
3569 case TGSI_SEMANTIC_POSITION:
3570 output[j].array_base = 60;
3571 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3572 pos_emitted = true;
3573 break;
3574
3575 case TGSI_SEMANTIC_PSIZE:
3576 output[j].array_base = 61;
3577 output[j].swizzle_y = 7;
3578 output[j].swizzle_z = 7;
3579 output[j].swizzle_w = 7;
3580 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3581 pos_emitted = true;
3582 break;
3583 case TGSI_SEMANTIC_EDGEFLAG:
3584 output[j].array_base = 61;
3585 output[j].swizzle_x = 7;
3586 output[j].swizzle_y = 0;
3587 output[j].swizzle_z = 7;
3588 output[j].swizzle_w = 7;
3589 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3590 pos_emitted = true;
3591 break;
3592 case TGSI_SEMANTIC_LAYER:
3593 /* spi_sid is 0 for outputs that are
3594 * not consumed by PS */
3595 if (shader->output[i].spi_sid) {
3596 output[j].array_base = next_param_base++;
3597 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3598 j++;
3599 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3600 }
3601 output[j].array_base = 61;
3602 output[j].swizzle_x = 7;
3603 output[j].swizzle_y = 7;
3604 output[j].swizzle_z = 0;
3605 output[j].swizzle_w = 7;
3606 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3607 pos_emitted = true;
3608 break;
3609 case TGSI_SEMANTIC_VIEWPORT_INDEX:
3610 /* spi_sid is 0 for outputs that are
3611 * not consumed by PS */
3612 if (shader->output[i].spi_sid) {
3613 output[j].array_base = next_param_base++;
3614 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3615 j++;
3616 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3617 }
3618 output[j].array_base = 61;
3619 output[j].swizzle_x = 7;
3620 output[j].swizzle_y = 7;
3621 output[j].swizzle_z = 7;
3622 output[j].swizzle_w = 0;
3623 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3624 pos_emitted = true;
3625 break;
3626 case TGSI_SEMANTIC_CLIPVERTEX:
3627 j--;
3628 break;
3629 case TGSI_SEMANTIC_CLIPDIST:
3630 output[j].array_base = next_clip_base++;
3631 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3632 pos_emitted = true;
3633 /* spi_sid is 0 for clipdistance outputs that were generated
3634 * for clipvertex - we don't need to pass them to PS */
3635 if (shader->output[i].spi_sid) {
3636 j++;
3637 /* duplicate it as PARAM to pass to the pixel shader */
3638 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3639 output[j].array_base = next_param_base++;
3640 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3641 }
3642 break;
3643 case TGSI_SEMANTIC_FOG:
3644 output[j].swizzle_y = 4; /* 0 */
3645 output[j].swizzle_z = 4; /* 0 */
3646 output[j].swizzle_w = 5; /* 1 */
3647 break;
3648 case TGSI_SEMANTIC_PRIMID:
3649 output[j].swizzle_x = 2;
3650 output[j].swizzle_y = 4; /* 0 */
3651 output[j].swizzle_z = 4; /* 0 */
3652 output[j].swizzle_w = 4; /* 0 */
3653 break;
3654 }
3655
3656 break;
3657 case PIPE_SHADER_FRAGMENT:
3658 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
3659 /* never export more colors than the number of CBs */
3660 if (shader->output[i].sid >= max_color_exports) {
3661 /* skip export */
3662 j--;
3663 continue;
3664 }
3665 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3666 output[j].array_base = shader->output[i].sid;
3667 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3668 shader->nr_ps_color_exports++;
3669 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
3670 for (k = 1; k < max_color_exports; k++) {
3671 j++;
3672 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3673 output[j].gpr = shader->output[i].gpr;
3674 output[j].elem_size = 3;
3675 output[j].swizzle_x = 0;
3676 output[j].swizzle_y = 1;
3677 output[j].swizzle_z = 2;
3678 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3679 output[j].burst_count = 1;
3680 output[j].array_base = k;
3681 output[j].op = CF_OP_EXPORT;
3682 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3683 shader->nr_ps_color_exports++;
3684 }
3685 }
3686 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
3687 output[j].array_base = 61;
3688 output[j].swizzle_x = 2;
3689 output[j].swizzle_y = 7;
3690 output[j].swizzle_z = output[j].swizzle_w = 7;
3691 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3692 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
3693 output[j].array_base = 61;
3694 output[j].swizzle_x = 7;
3695 output[j].swizzle_y = 1;
3696 output[j].swizzle_z = output[j].swizzle_w = 7;
3697 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3698 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3699 output[j].array_base = 61;
3700 output[j].swizzle_x = 7;
3701 output[j].swizzle_y = 7;
3702 output[j].swizzle_z = 0;
3703 output[j].swizzle_w = 7;
3704 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3705 } else {
3706 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
3707 r = -EINVAL;
3708 goto out_err;
3709 }
3710 break;
3711 case PIPE_SHADER_TESS_CTRL:
3712 break;
3713 default:
3714 R600_ERR("unsupported processor type %d\n", ctx.type);
3715 r = -EINVAL;
3716 goto out_err;
3717 }
3718
3719 if (output[j].type==-1) {
3720 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3721 output[j].array_base = next_param_base++;
3722 }
3723 }
3724
3725 /* add fake position export */
3726 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
3727 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3728 output[j].gpr = 0;
3729 output[j].elem_size = 3;
3730 output[j].swizzle_x = 7;
3731 output[j].swizzle_y = 7;
3732 output[j].swizzle_z = 7;
3733 output[j].swizzle_w = 7;
3734 output[j].burst_count = 1;
3735 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3736 output[j].array_base = 60;
3737 output[j].op = CF_OP_EXPORT;
3738 j++;
3739 }
3740
3741 /* add fake param output for vertex shader if no param is exported */
3742 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
3743 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3744 output[j].gpr = 0;
3745 output[j].elem_size = 3;
3746 output[j].swizzle_x = 7;
3747 output[j].swizzle_y = 7;
3748 output[j].swizzle_z = 7;
3749 output[j].swizzle_w = 7;
3750 output[j].burst_count = 1;
3751 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3752 output[j].array_base = 0;
3753 output[j].op = CF_OP_EXPORT;
3754 j++;
3755 }
3756
3757 /* add fake pixel export */
3758 if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
3759 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3760 output[j].gpr = 0;
3761 output[j].elem_size = 3;
3762 output[j].swizzle_x = 7;
3763 output[j].swizzle_y = 7;
3764 output[j].swizzle_z = 7;
3765 output[j].swizzle_w = 7;
3766 output[j].burst_count = 1;
3767 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3768 output[j].array_base = 0;
3769 output[j].op = CF_OP_EXPORT;
3770 j++;
3771 shader->nr_ps_color_exports++;
3772 }
3773
3774 noutput = j;
3775
3776 /* set export done on last export of each type */
3777 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
3778 if (!(output_done & (1 << output[i].type))) {
3779 output_done |= (1 << output[i].type);
3780 output[i].op = CF_OP_EXPORT_DONE;
3781 }
3782 }
3783 /* add output to bytecode */
3784 for (i = 0; i < noutput; i++) {
3785 r = r600_bytecode_add_output(ctx.bc, &output[i]);
3786 if (r)
3787 goto out_err;
3788 }
3789 }
3790
3791 /* add program end */
3792 if (ctx.bc->chip_class == CAYMAN)
3793 cm_bytecode_add_cf_end(ctx.bc);
3794 else {
3795 const struct cf_op_info *last = NULL;
3796
3797 if (ctx.bc->cf_last)
3798 last = r600_isa_cf(ctx.bc->cf_last->op);
3799
3800 /* alu clause instructions don't have EOP bit, so add NOP */
3801 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS || ctx.bc->cf_last->op == CF_OP_POP || ctx.bc->cf_last->op == CF_OP_GDS)
3802 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
3803
3804 ctx.bc->cf_last->end_of_program = 1;
3805 }
3806
3807 /* check GPR limit - we have 124 = 128 - 4
3808 * (4 are reserved as alu clause temporary registers) */
3809 if (ctx.bc->ngpr > 124) {
3810 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
3811 r = -ENOMEM;
3812 goto out_err;
3813 }
3814
3815 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3816 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
3817 return r;
3818 }
3819
3820 free(ctx.literals);
3821 tgsi_parse_free(&ctx.parse);
3822 return 0;
3823 out_err:
3824 free(ctx.literals);
3825 tgsi_parse_free(&ctx.parse);
3826 return r;
3827 }
3828
3829 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
3830 {
3831 const unsigned tgsi_opcode =
3832 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
3833 R600_ERR("%s tgsi opcode unsupported\n",
3834 tgsi_get_opcode_name(tgsi_opcode));
3835 return -EINVAL;
3836 }
3837
3838 static int tgsi_end(struct r600_shader_ctx *ctx)
3839 {
3840 return 0;
3841 }
3842
3843 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
3844 const struct r600_shader_src *shader_src,
3845 unsigned chan)
3846 {
3847 bc_src->sel = shader_src->sel;
3848 bc_src->chan = shader_src->swizzle[chan];
3849 bc_src->neg = shader_src->neg;
3850 bc_src->abs = shader_src->abs;
3851 bc_src->rel = shader_src->rel;
3852 bc_src->value = shader_src->value[bc_src->chan];
3853 bc_src->kc_bank = shader_src->kc_bank;
3854 bc_src->kc_rel = shader_src->kc_rel;
3855 }
3856
3857 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
3858 {
3859 bc_src->abs = 1;
3860 bc_src->neg = 0;
3861 }
3862
3863 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
3864 {
3865 bc_src->neg = !bc_src->neg;
3866 }
3867
3868 static void tgsi_dst(struct r600_shader_ctx *ctx,
3869 const struct tgsi_full_dst_register *tgsi_dst,
3870 unsigned swizzle,
3871 struct r600_bytecode_alu_dst *r600_dst)
3872 {
3873 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3874
3875 r600_dst->sel = tgsi_dst->Register.Index;
3876 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
3877 r600_dst->chan = swizzle;
3878 r600_dst->write = 1;
3879 if (inst->Instruction.Saturate) {
3880 r600_dst->clamp = 1;
3881 }
3882 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
3883 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
3884 return;
3885 }
3886 }
3887 if (tgsi_dst->Register.Indirect)
3888 r600_dst->rel = V_SQ_REL_RELATIVE;
3889
3890 }
3891
3892 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
3893 {
3894 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3895 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3896 struct r600_bytecode_alu alu;
3897 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3898 int use_tmp = 0;
3899
3900 if (singledest) {
3901 switch (write_mask) {
3902 case 0x1:
3903 write_mask = 0x3;
3904 break;
3905 case 0x2:
3906 use_tmp = 1;
3907 write_mask = 0x3;
3908 break;
3909 case 0x4:
3910 write_mask = 0xc;
3911 break;
3912 case 0x8:
3913 write_mask = 0xc;
3914 use_tmp = 3;
3915 break;
3916 }
3917 }
3918
3919 lasti = tgsi_last_instruction(write_mask);
3920 for (i = 0; i <= lasti; i++) {
3921
3922 if (!(write_mask & (1 << i)))
3923 continue;
3924
3925 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3926
3927 if (singledest) {
3928 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3929 if (use_tmp) {
3930 alu.dst.sel = ctx->temp_reg;
3931 alu.dst.chan = i;
3932 alu.dst.write = 1;
3933 }
3934 if (i == 1 || i == 3)
3935 alu.dst.write = 0;
3936 } else
3937 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3938
3939 alu.op = ctx->inst_info->op;
3940 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
3941 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3942 } else if (!swap) {
3943 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3944 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
3945 }
3946 } else {
3947 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
3948 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
3949 }
3950
3951 /* handle some special cases */
3952 if (i == 1 || i == 3) {
3953 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
3954 case TGSI_OPCODE_DABS:
3955 r600_bytecode_src_set_abs(&alu.src[0]);
3956 break;
3957 default:
3958 break;
3959 }
3960 }
3961 if (i == lasti) {
3962 alu.last = 1;
3963 }
3964 r = r600_bytecode_add_alu(ctx->bc, &alu);
3965 if (r)
3966 return r;
3967 }
3968
3969 if (use_tmp) {
3970 write_mask = inst->Dst[0].Register.WriteMask;
3971
3972 /* move result from temp to dst */
3973 for (i = 0; i <= lasti; i++) {
3974 if (!(write_mask & (1 << i)))
3975 continue;
3976
3977 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3978 alu.op = ALU_OP1_MOV;
3979 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3980 alu.src[0].sel = ctx->temp_reg;
3981 alu.src[0].chan = use_tmp - 1;
3982 alu.last = (i == lasti);
3983
3984 r = r600_bytecode_add_alu(ctx->bc, &alu);
3985 if (r)
3986 return r;
3987 }
3988 }
3989 return 0;
3990 }
3991
3992 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
3993 {
3994 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3995 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3996 /* confirm writemasking */
3997 if ((write_mask & 0x3) != 0x3 &&
3998 (write_mask & 0xc) != 0xc) {
3999 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
4000 return -1;
4001 }
4002 return tgsi_op2_64_params(ctx, false, false);
4003 }
4004
4005 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
4006 {
4007 return tgsi_op2_64_params(ctx, true, false);
4008 }
4009
4010 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
4011 {
4012 return tgsi_op2_64_params(ctx, true, true);
4013 }
4014
4015 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
4016 {
4017 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4018 struct r600_bytecode_alu alu;
4019 int i, j, r;
4020 int lasti = 3;
4021 int tmp = r600_get_temp(ctx);
4022
4023 for (i = 0; i < lasti + 1; i++) {
4024
4025 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4026 alu.op = ctx->inst_info->op;
4027 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4028 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
4029 }
4030
4031 if (inst->Dst[0].Register.WriteMask & (1 << i))
4032 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4033 else
4034 alu.dst.sel = tmp;
4035
4036 alu.dst.chan = i;
4037 alu.is_op3 = 1;
4038 if (i == lasti) {
4039 alu.last = 1;
4040 }
4041 r = r600_bytecode_add_alu(ctx->bc, &alu);
4042 if (r)
4043 return r;
4044 }
4045 return 0;
4046 }
4047
4048 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
4049 {
4050 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4051 struct r600_bytecode_alu alu;
4052 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4053 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4054 /* use temp register if trans_only and more than one dst component */
4055 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
4056 unsigned op = ctx->inst_info->op;
4057
4058 if (op == ALU_OP2_MUL_IEEE &&
4059 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
4060 op = ALU_OP2_MUL;
4061
4062 for (i = 0; i <= lasti; i++) {
4063 if (!(write_mask & (1 << i)))
4064 continue;
4065
4066 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4067 if (use_tmp) {
4068 alu.dst.sel = ctx->temp_reg;
4069 alu.dst.chan = i;
4070 alu.dst.write = 1;
4071 } else
4072 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4073
4074 alu.op = op;
4075 if (!swap) {
4076 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4077 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4078 }
4079 } else {
4080 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4081 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4082 }
4083 if (i == lasti || trans_only) {
4084 alu.last = 1;
4085 }
4086 r = r600_bytecode_add_alu(ctx->bc, &alu);
4087 if (r)
4088 return r;
4089 }
4090
4091 if (use_tmp) {
4092 /* move result from temp to dst */
4093 for (i = 0; i <= lasti; i++) {
4094 if (!(write_mask & (1 << i)))
4095 continue;
4096
4097 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4098 alu.op = ALU_OP1_MOV;
4099 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4100 alu.src[0].sel = ctx->temp_reg;
4101 alu.src[0].chan = i;
4102 alu.last = (i == lasti);
4103
4104 r = r600_bytecode_add_alu(ctx->bc, &alu);
4105 if (r)
4106 return r;
4107 }
4108 }
4109 return 0;
4110 }
4111
4112 static int tgsi_op2(struct r600_shader_ctx *ctx)
4113 {
4114 return tgsi_op2_s(ctx, 0, 0);
4115 }
4116
4117 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
4118 {
4119 return tgsi_op2_s(ctx, 1, 0);
4120 }
4121
4122 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
4123 {
4124 return tgsi_op2_s(ctx, 0, 1);
4125 }
4126
4127 static int tgsi_ineg(struct r600_shader_ctx *ctx)
4128 {
4129 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4130 struct r600_bytecode_alu alu;
4131 int i, r;
4132 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4133
4134 for (i = 0; i < lasti + 1; i++) {
4135
4136 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4137 continue;
4138 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4139 alu.op = ctx->inst_info->op;
4140
4141 alu.src[0].sel = V_SQ_ALU_SRC_0;
4142
4143 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4144
4145 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4146
4147 if (i == lasti) {
4148 alu.last = 1;
4149 }
4150 r = r600_bytecode_add_alu(ctx->bc, &alu);
4151 if (r)
4152 return r;
4153 }
4154 return 0;
4155
4156 }
4157
4158 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4159 {
4160 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4161 struct r600_bytecode_alu alu;
4162 int i, r;
4163 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4164
4165 for (i = 0; i < lasti + 1; i++) {
4166
4167 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4168 continue;
4169 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4170 alu.op = ALU_OP1_MOV;
4171
4172 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4173
4174 if (i == 1 || i == 3)
4175 r600_bytecode_src_toggle_neg(&alu.src[0]);
4176 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4177
4178 if (i == lasti) {
4179 alu.last = 1;
4180 }
4181 r = r600_bytecode_add_alu(ctx->bc, &alu);
4182 if (r)
4183 return r;
4184 }
4185 return 0;
4186
4187 }
4188
4189 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4190 {
4191 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4192 struct r600_bytecode_alu alu;
4193 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4194 int i, j, r;
4195
4196 for (i = 0; i <= 3; i++) {
4197 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4198 alu.op = ctx->inst_info->op;
4199
4200 alu.dst.sel = ctx->temp_reg;
4201 alu.dst.chan = i;
4202 alu.dst.write = 1;
4203 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4204 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4205 }
4206
4207 if (i == 3)
4208 alu.last = 1;
4209
4210 r = r600_bytecode_add_alu(ctx->bc, &alu);
4211 if (r)
4212 return r;
4213 }
4214
4215 /* Replicate significand result across channels. */
4216 for (i = 0; i <= 3; i++) {
4217 if (!(write_mask & (1 << i)))
4218 continue;
4219
4220 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4221 alu.op = ALU_OP1_MOV;
4222 alu.src[0].chan = (i & 1) + 2;
4223 alu.src[0].sel = ctx->temp_reg;
4224
4225 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4226 alu.dst.write = 1;
4227 alu.last = 1;
4228 r = r600_bytecode_add_alu(ctx->bc, &alu);
4229 if (r)
4230 return r;
4231 }
4232
4233 for (i = 0; i <= 3; i++) {
4234 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4235 /* MOV third channels to writemask dst1 */
4236 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4237 alu.op = ALU_OP1_MOV;
4238 alu.src[0].chan = 1;
4239 alu.src[0].sel = ctx->temp_reg;
4240
4241 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4242 alu.last = 1;
4243 r = r600_bytecode_add_alu(ctx->bc, &alu);
4244 if (r)
4245 return r;
4246 break;
4247 }
4248 }
4249 return 0;
4250 }
4251
4252
4253 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4254 {
4255 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4256 struct r600_bytecode_alu alu;
4257 int i, r;
4258 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4259
4260 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4261 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4262
4263 for (i = 0; i <= (lasti+1)/2; i++) {
4264 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4265 alu.op = ctx->inst_info->op;
4266
4267 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4268 alu.dst.sel = ctx->temp_reg;
4269 alu.dst.chan = i;
4270 alu.dst.write = 1;
4271 alu.last = 1;
4272
4273 r = r600_bytecode_add_alu(ctx->bc, &alu);
4274 if (r)
4275 return r;
4276 }
4277
4278 for (i = 0; i <= lasti; i++) {
4279 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4280 alu.op = ALU_OP1_FLT32_TO_FLT64;
4281
4282 alu.src[0].chan = i/2;
4283 if (i%2 == 0)
4284 alu.src[0].sel = ctx->temp_reg;
4285 else {
4286 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4287 alu.src[0].value = 0x0;
4288 }
4289 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4290 alu.last = i == lasti;
4291
4292 r = r600_bytecode_add_alu(ctx->bc, &alu);
4293 if (r)
4294 return r;
4295 }
4296
4297 return 0;
4298 }
4299
4300 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4301 {
4302 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4303 struct r600_bytecode_alu alu;
4304 int i, r;
4305 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4306
4307 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4308 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4309
4310 for (i = 0; i <= lasti; i++) {
4311 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4312 alu.op = ALU_OP1_FLT64_TO_FLT32;
4313
4314 r600_bytecode_src(&alu.src[0], &ctx->src[0], fp64_switch(i));
4315 alu.dst.chan = i;
4316 alu.dst.sel = ctx->temp_reg;
4317 alu.dst.write = i%2 == 0;
4318 alu.last = i == lasti;
4319
4320 r = r600_bytecode_add_alu(ctx->bc, &alu);
4321 if (r)
4322 return r;
4323 }
4324
4325 for (i = 0; i <= (lasti+1)/2; i++) {
4326 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4327 alu.op = ctx->inst_info->op;
4328
4329 alu.src[0].chan = i*2;
4330 alu.src[0].sel = ctx->temp_reg;
4331 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4332 alu.last = 1;
4333
4334 r = r600_bytecode_add_alu(ctx->bc, &alu);
4335 if (r)
4336 return r;
4337 }
4338
4339 return 0;
4340 }
4341
4342 static int cayman_emit_unary_double_raw(struct r600_bytecode *bc,
4343 unsigned op,
4344 int dst_reg,
4345 struct r600_shader_src *src,
4346 bool abs)
4347 {
4348 struct r600_bytecode_alu alu;
4349 const int last_slot = 3;
4350 int r;
4351
4352 /* these have to write the result to X/Y by the looks of it */
4353 for (int i = 0 ; i < last_slot; i++) {
4354 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4355 alu.op = op;
4356
4357 r600_bytecode_src(&alu.src[0], src, 1);
4358 r600_bytecode_src(&alu.src[1], src, 0);
4359
4360 if (abs)
4361 r600_bytecode_src_set_abs(&alu.src[1]);
4362
4363 alu.dst.sel = dst_reg;
4364 alu.dst.chan = i;
4365 alu.dst.write = (i == 0 || i == 1);
4366
4367 if (bc->chip_class != CAYMAN || i == last_slot - 1)
4368 alu.last = 1;
4369 r = r600_bytecode_add_alu(bc, &alu);
4370 if (r)
4371 return r;
4372 }
4373
4374 return 0;
4375 }
4376
4377 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4378 {
4379 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4380 int i, r;
4381 struct r600_bytecode_alu alu;
4382 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4383 int t1 = ctx->temp_reg;
4384
4385 /* should only be one src regs */
4386 assert(inst->Instruction.NumSrcRegs == 1);
4387
4388 /* only support one double at a time */
4389 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4390 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4391
4392 r = cayman_emit_unary_double_raw(
4393 ctx->bc, ctx->inst_info->op, t1,
4394 &ctx->src[0],
4395 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4396 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT);
4397 if (r)
4398 return r;
4399
4400 for (i = 0 ; i <= lasti; i++) {
4401 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4402 continue;
4403 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4404 alu.op = ALU_OP1_MOV;
4405 alu.src[0].sel = t1;
4406 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
4407 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4408 alu.dst.write = 1;
4409 if (i == lasti)
4410 alu.last = 1;
4411 r = r600_bytecode_add_alu(ctx->bc, &alu);
4412 if (r)
4413 return r;
4414 }
4415 return 0;
4416 }
4417
4418 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
4419 {
4420 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4421 int i, j, r;
4422 struct r600_bytecode_alu alu;
4423 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4424
4425 for (i = 0 ; i < last_slot; i++) {
4426 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4427 alu.op = ctx->inst_info->op;
4428 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4429 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
4430
4431 /* RSQ should take the absolute value of src */
4432 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
4433 r600_bytecode_src_set_abs(&alu.src[j]);
4434 }
4435 }
4436 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4437 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4438
4439 if (i == last_slot - 1)
4440 alu.last = 1;
4441 r = r600_bytecode_add_alu(ctx->bc, &alu);
4442 if (r)
4443 return r;
4444 }
4445 return 0;
4446 }
4447
4448 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
4449 {
4450 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4451 int i, j, k, r;
4452 struct r600_bytecode_alu alu;
4453 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4454 int t1 = ctx->temp_reg;
4455
4456 for (k = 0; k <= lasti; k++) {
4457 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
4458 continue;
4459
4460 for (i = 0 ; i < 4; i++) {
4461 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4462 alu.op = ctx->inst_info->op;
4463 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4464 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
4465 }
4466 alu.dst.sel = t1;
4467 alu.dst.chan = i;
4468 alu.dst.write = (i == k);
4469 if (i == 3)
4470 alu.last = 1;
4471 r = r600_bytecode_add_alu(ctx->bc, &alu);
4472 if (r)
4473 return r;
4474 }
4475 }
4476
4477 for (i = 0 ; i <= lasti; i++) {
4478 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4479 continue;
4480 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4481 alu.op = ALU_OP1_MOV;
4482 alu.src[0].sel = t1;
4483 alu.src[0].chan = i;
4484 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4485 alu.dst.write = 1;
4486 if (i == lasti)
4487 alu.last = 1;
4488 r = r600_bytecode_add_alu(ctx->bc, &alu);
4489 if (r)
4490 return r;
4491 }
4492
4493 return 0;
4494 }
4495
4496
4497 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
4498 {
4499 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4500 int i, j, k, r;
4501 struct r600_bytecode_alu alu;
4502 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4503 int t1 = ctx->temp_reg;
4504
4505 /* t1 would get overwritten below if we actually tried to
4506 * multiply two pairs of doubles at a time. */
4507 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4508 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4509
4510 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4511
4512 for (i = 0; i < 4; i++) {
4513 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4514 alu.op = ctx->inst_info->op;
4515 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4516 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));
4517 }
4518 alu.dst.sel = t1;
4519 alu.dst.chan = i;
4520 alu.dst.write = 1;
4521 if (i == 3)
4522 alu.last = 1;
4523 r = r600_bytecode_add_alu(ctx->bc, &alu);
4524 if (r)
4525 return r;
4526 }
4527
4528 for (i = 0; i <= lasti; i++) {
4529 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4530 continue;
4531 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4532 alu.op = ALU_OP1_MOV;
4533 alu.src[0].sel = t1;
4534 alu.src[0].chan = i;
4535 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4536 alu.dst.write = 1;
4537 if (i == lasti)
4538 alu.last = 1;
4539 r = r600_bytecode_add_alu(ctx->bc, &alu);
4540 if (r)
4541 return r;
4542 }
4543
4544 return 0;
4545 }
4546
4547 /*
4548 * Emit RECIP_64 + MUL_64 to implement division.
4549 */
4550 static int cayman_ddiv_instr(struct r600_shader_ctx *ctx)
4551 {
4552 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4553 int r;
4554 struct r600_bytecode_alu alu;
4555 int t1 = ctx->temp_reg;
4556 int k;
4557
4558 /* Only support one double at a time. This is the same constraint as
4559 * in DMUL lowering. */
4560 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4561 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4562
4563 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4564
4565 r = cayman_emit_unary_double_raw(ctx->bc, ALU_OP2_RECIP_64, t1, &ctx->src[1], false);
4566 if (r)
4567 return r;
4568
4569 for (int i = 0; i < 4; i++) {
4570 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4571 alu.op = ALU_OP2_MUL_64;
4572
4573 r600_bytecode_src(&alu.src[0], &ctx->src[0], k * 2 + ((i == 3) ? 0 : 1));
4574
4575 alu.src[1].sel = t1;
4576 alu.src[1].chan = (i == 3) ? 0 : 1;
4577
4578 alu.dst.sel = t1;
4579 alu.dst.chan = i;
4580 alu.dst.write = 1;
4581 if (i == 3)
4582 alu.last = 1;
4583 r = r600_bytecode_add_alu(ctx->bc, &alu);
4584 if (r)
4585 return r;
4586 }
4587
4588 for (int i = 0; i < 2; i++) {
4589 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4590 alu.op = ALU_OP1_MOV;
4591 alu.src[0].sel = t1;
4592 alu.src[0].chan = i;
4593 tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
4594 alu.dst.write = 1;
4595 if (i == 1)
4596 alu.last = 1;
4597 r = r600_bytecode_add_alu(ctx->bc, &alu);
4598 if (r)
4599 return r;
4600 }
4601 return 0;
4602 }
4603
4604 /*
4605 * r600 - trunc to -PI..PI range
4606 * r700 - normalize by dividing by 2PI
4607 * see fdo bug 27901
4608 */
4609 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
4610 {
4611 int r;
4612 struct r600_bytecode_alu alu;
4613
4614 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4615 alu.op = ALU_OP3_MULADD;
4616 alu.is_op3 = 1;
4617
4618 alu.dst.chan = 0;
4619 alu.dst.sel = ctx->temp_reg;
4620 alu.dst.write = 1;
4621
4622 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4623
4624 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4625 alu.src[1].chan = 0;
4626 alu.src[1].value = u_bitcast_f2u(0.5f * M_1_PI);
4627 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4628 alu.src[2].chan = 0;
4629 alu.last = 1;
4630 r = r600_bytecode_add_alu(ctx->bc, &alu);
4631 if (r)
4632 return r;
4633
4634 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4635 alu.op = ALU_OP1_FRACT;
4636
4637 alu.dst.chan = 0;
4638 alu.dst.sel = ctx->temp_reg;
4639 alu.dst.write = 1;
4640
4641 alu.src[0].sel = ctx->temp_reg;
4642 alu.src[0].chan = 0;
4643 alu.last = 1;
4644 r = r600_bytecode_add_alu(ctx->bc, &alu);
4645 if (r)
4646 return r;
4647
4648 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4649 alu.op = ALU_OP3_MULADD;
4650 alu.is_op3 = 1;
4651
4652 alu.dst.chan = 0;
4653 alu.dst.sel = ctx->temp_reg;
4654 alu.dst.write = 1;
4655
4656 alu.src[0].sel = ctx->temp_reg;
4657 alu.src[0].chan = 0;
4658
4659 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4660 alu.src[1].chan = 0;
4661 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4662 alu.src[2].chan = 0;
4663
4664 if (ctx->bc->chip_class == R600) {
4665 alu.src[1].value = u_bitcast_f2u(2.0f * M_PI);
4666 alu.src[2].value = u_bitcast_f2u(-M_PI);
4667 } else {
4668 alu.src[1].sel = V_SQ_ALU_SRC_1;
4669 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4670 alu.src[2].neg = 1;
4671 }
4672
4673 alu.last = 1;
4674 r = r600_bytecode_add_alu(ctx->bc, &alu);
4675 if (r)
4676 return r;
4677 return 0;
4678 }
4679
4680 static int cayman_trig(struct r600_shader_ctx *ctx)
4681 {
4682 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4683 struct r600_bytecode_alu alu;
4684 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4685 int i, r;
4686
4687 r = tgsi_setup_trig(ctx);
4688 if (r)
4689 return r;
4690
4691
4692 for (i = 0; i < last_slot; i++) {
4693 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4694 alu.op = ctx->inst_info->op;
4695 alu.dst.chan = i;
4696
4697 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4698 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4699
4700 alu.src[0].sel = ctx->temp_reg;
4701 alu.src[0].chan = 0;
4702 if (i == last_slot - 1)
4703 alu.last = 1;
4704 r = r600_bytecode_add_alu(ctx->bc, &alu);
4705 if (r)
4706 return r;
4707 }
4708 return 0;
4709 }
4710
4711 static int tgsi_trig(struct r600_shader_ctx *ctx)
4712 {
4713 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4714 struct r600_bytecode_alu alu;
4715 int i, r;
4716 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4717
4718 r = tgsi_setup_trig(ctx);
4719 if (r)
4720 return r;
4721
4722 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4723 alu.op = ctx->inst_info->op;
4724 alu.dst.chan = 0;
4725 alu.dst.sel = ctx->temp_reg;
4726 alu.dst.write = 1;
4727
4728 alu.src[0].sel = ctx->temp_reg;
4729 alu.src[0].chan = 0;
4730 alu.last = 1;
4731 r = r600_bytecode_add_alu(ctx->bc, &alu);
4732 if (r)
4733 return r;
4734
4735 /* replicate result */
4736 for (i = 0; i < lasti + 1; i++) {
4737 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4738 continue;
4739
4740 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4741 alu.op = ALU_OP1_MOV;
4742
4743 alu.src[0].sel = ctx->temp_reg;
4744 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4745 if (i == lasti)
4746 alu.last = 1;
4747 r = r600_bytecode_add_alu(ctx->bc, &alu);
4748 if (r)
4749 return r;
4750 }
4751 return 0;
4752 }
4753
4754 static int tgsi_kill(struct r600_shader_ctx *ctx)
4755 {
4756 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4757 struct r600_bytecode_alu alu;
4758 int i, r;
4759
4760 for (i = 0; i < 4; i++) {
4761 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4762 alu.op = ctx->inst_info->op;
4763
4764 alu.dst.chan = i;
4765
4766 alu.src[0].sel = V_SQ_ALU_SRC_0;
4767
4768 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
4769 alu.src[1].sel = V_SQ_ALU_SRC_1;
4770 alu.src[1].neg = 1;
4771 } else {
4772 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4773 }
4774 if (i == 3) {
4775 alu.last = 1;
4776 }
4777 r = r600_bytecode_add_alu(ctx->bc, &alu);
4778 if (r)
4779 return r;
4780 }
4781
4782 /* kill must be last in ALU */
4783 ctx->bc->force_add_cf = 1;
4784 ctx->shader->uses_kill = TRUE;
4785 return 0;
4786 }
4787
4788 static int tgsi_lit(struct r600_shader_ctx *ctx)
4789 {
4790 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4791 struct r600_bytecode_alu alu;
4792 int r;
4793
4794 /* tmp.x = max(src.y, 0.0) */
4795 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4796 alu.op = ALU_OP2_MAX;
4797 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4798 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4799 alu.src[1].chan = 1;
4800
4801 alu.dst.sel = ctx->temp_reg;
4802 alu.dst.chan = 0;
4803 alu.dst.write = 1;
4804
4805 alu.last = 1;
4806 r = r600_bytecode_add_alu(ctx->bc, &alu);
4807 if (r)
4808 return r;
4809
4810 if (inst->Dst[0].Register.WriteMask & (1 << 2))
4811 {
4812 int chan;
4813 int sel;
4814 unsigned i;
4815
4816 if (ctx->bc->chip_class == CAYMAN) {
4817 for (i = 0; i < 3; i++) {
4818 /* tmp.z = log(tmp.x) */
4819 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4820 alu.op = ALU_OP1_LOG_CLAMPED;
4821 alu.src[0].sel = ctx->temp_reg;
4822 alu.src[0].chan = 0;
4823 alu.dst.sel = ctx->temp_reg;
4824 alu.dst.chan = i;
4825 if (i == 2) {
4826 alu.dst.write = 1;
4827 alu.last = 1;
4828 } else
4829 alu.dst.write = 0;
4830
4831 r = r600_bytecode_add_alu(ctx->bc, &alu);
4832 if (r)
4833 return r;
4834 }
4835 } else {
4836 /* tmp.z = log(tmp.x) */
4837 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4838 alu.op = ALU_OP1_LOG_CLAMPED;
4839 alu.src[0].sel = ctx->temp_reg;
4840 alu.src[0].chan = 0;
4841 alu.dst.sel = ctx->temp_reg;
4842 alu.dst.chan = 2;
4843 alu.dst.write = 1;
4844 alu.last = 1;
4845 r = r600_bytecode_add_alu(ctx->bc, &alu);
4846 if (r)
4847 return r;
4848 }
4849
4850 chan = alu.dst.chan;
4851 sel = alu.dst.sel;
4852
4853 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4854 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4855 alu.op = ALU_OP3_MUL_LIT;
4856 alu.src[0].sel = sel;
4857 alu.src[0].chan = chan;
4858 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
4859 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
4860 alu.dst.sel = ctx->temp_reg;
4861 alu.dst.chan = 0;
4862 alu.dst.write = 1;
4863 alu.is_op3 = 1;
4864 alu.last = 1;
4865 r = r600_bytecode_add_alu(ctx->bc, &alu);
4866 if (r)
4867 return r;
4868
4869 if (ctx->bc->chip_class == CAYMAN) {
4870 for (i = 0; i < 3; i++) {
4871 /* dst.z = exp(tmp.x) */
4872 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4873 alu.op = ALU_OP1_EXP_IEEE;
4874 alu.src[0].sel = ctx->temp_reg;
4875 alu.src[0].chan = 0;
4876 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4877 if (i == 2) {
4878 alu.dst.write = 1;
4879 alu.last = 1;
4880 } else
4881 alu.dst.write = 0;
4882 r = r600_bytecode_add_alu(ctx->bc, &alu);
4883 if (r)
4884 return r;
4885 }
4886 } else {
4887 /* dst.z = exp(tmp.x) */
4888 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4889 alu.op = ALU_OP1_EXP_IEEE;
4890 alu.src[0].sel = ctx->temp_reg;
4891 alu.src[0].chan = 0;
4892 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4893 alu.last = 1;
4894 r = r600_bytecode_add_alu(ctx->bc, &alu);
4895 if (r)
4896 return r;
4897 }
4898 }
4899
4900 /* dst.x, <- 1.0 */
4901 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4902 alu.op = ALU_OP1_MOV;
4903 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
4904 alu.src[0].chan = 0;
4905 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4906 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
4907 r = r600_bytecode_add_alu(ctx->bc, &alu);
4908 if (r)
4909 return r;
4910
4911 /* dst.y = max(src.x, 0.0) */
4912 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4913 alu.op = ALU_OP2_MAX;
4914 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4915 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4916 alu.src[1].chan = 0;
4917 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4918 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
4919 r = r600_bytecode_add_alu(ctx->bc, &alu);
4920 if (r)
4921 return r;
4922
4923 /* dst.w, <- 1.0 */
4924 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4925 alu.op = ALU_OP1_MOV;
4926 alu.src[0].sel = V_SQ_ALU_SRC_1;
4927 alu.src[0].chan = 0;
4928 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4929 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
4930 alu.last = 1;
4931 r = r600_bytecode_add_alu(ctx->bc, &alu);
4932 if (r)
4933 return r;
4934
4935 return 0;
4936 }
4937
4938 static int tgsi_rsq(struct r600_shader_ctx *ctx)
4939 {
4940 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4941 struct r600_bytecode_alu alu;
4942 int i, r;
4943
4944 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4945
4946 alu.op = ALU_OP1_RECIPSQRT_IEEE;
4947
4948 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4949 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4950 r600_bytecode_src_set_abs(&alu.src[i]);
4951 }
4952 alu.dst.sel = ctx->temp_reg;
4953 alu.dst.write = 1;
4954 alu.last = 1;
4955 r = r600_bytecode_add_alu(ctx->bc, &alu);
4956 if (r)
4957 return r;
4958 /* replicate result */
4959 return tgsi_helper_tempx_replicate(ctx);
4960 }
4961
4962 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
4963 {
4964 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4965 struct r600_bytecode_alu alu;
4966 int i, r;
4967
4968 for (i = 0; i < 4; i++) {
4969 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4970 alu.src[0].sel = ctx->temp_reg;
4971 alu.op = ALU_OP1_MOV;
4972 alu.dst.chan = i;
4973 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4974 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4975 if (i == 3)
4976 alu.last = 1;
4977 r = r600_bytecode_add_alu(ctx->bc, &alu);
4978 if (r)
4979 return r;
4980 }
4981 return 0;
4982 }
4983
4984 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
4985 {
4986 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4987 struct r600_bytecode_alu alu;
4988 int i, r;
4989
4990 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4991 alu.op = ctx->inst_info->op;
4992 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4993 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4994 }
4995 alu.dst.sel = ctx->temp_reg;
4996 alu.dst.write = 1;
4997 alu.last = 1;
4998 r = r600_bytecode_add_alu(ctx->bc, &alu);
4999 if (r)
5000 return r;
5001 /* replicate result */
5002 return tgsi_helper_tempx_replicate(ctx);
5003 }
5004
5005 static int cayman_pow(struct r600_shader_ctx *ctx)
5006 {
5007 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5008 int i, r;
5009 struct r600_bytecode_alu alu;
5010 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5011
5012 for (i = 0; i < 3; i++) {
5013 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5014 alu.op = ALU_OP1_LOG_IEEE;
5015 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5016 alu.dst.sel = ctx->temp_reg;
5017 alu.dst.chan = i;
5018 alu.dst.write = 1;
5019 if (i == 2)
5020 alu.last = 1;
5021 r = r600_bytecode_add_alu(ctx->bc, &alu);
5022 if (r)
5023 return r;
5024 }
5025
5026 /* b * LOG2(a) */
5027 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5028 alu.op = ALU_OP2_MUL;
5029 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5030 alu.src[1].sel = ctx->temp_reg;
5031 alu.dst.sel = ctx->temp_reg;
5032 alu.dst.write = 1;
5033 alu.last = 1;
5034 r = r600_bytecode_add_alu(ctx->bc, &alu);
5035 if (r)
5036 return r;
5037
5038 for (i = 0; i < last_slot; i++) {
5039 /* POW(a,b) = EXP2(b * LOG2(a))*/
5040 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5041 alu.op = ALU_OP1_EXP_IEEE;
5042 alu.src[0].sel = ctx->temp_reg;
5043
5044 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5045 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5046 if (i == last_slot - 1)
5047 alu.last = 1;
5048 r = r600_bytecode_add_alu(ctx->bc, &alu);
5049 if (r)
5050 return r;
5051 }
5052 return 0;
5053 }
5054
5055 static int tgsi_pow(struct r600_shader_ctx *ctx)
5056 {
5057 struct r600_bytecode_alu alu;
5058 int r;
5059
5060 /* LOG2(a) */
5061 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5062 alu.op = ALU_OP1_LOG_IEEE;
5063 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5064 alu.dst.sel = ctx->temp_reg;
5065 alu.dst.write = 1;
5066 alu.last = 1;
5067 r = r600_bytecode_add_alu(ctx->bc, &alu);
5068 if (r)
5069 return r;
5070 /* b * LOG2(a) */
5071 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5072 alu.op = ALU_OP2_MUL;
5073 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5074 alu.src[1].sel = ctx->temp_reg;
5075 alu.dst.sel = ctx->temp_reg;
5076 alu.dst.write = 1;
5077 alu.last = 1;
5078 r = r600_bytecode_add_alu(ctx->bc, &alu);
5079 if (r)
5080 return r;
5081 /* POW(a,b) = EXP2(b * LOG2(a))*/
5082 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5083 alu.op = ALU_OP1_EXP_IEEE;
5084 alu.src[0].sel = ctx->temp_reg;
5085 alu.dst.sel = ctx->temp_reg;
5086 alu.dst.write = 1;
5087 alu.last = 1;
5088 r = r600_bytecode_add_alu(ctx->bc, &alu);
5089 if (r)
5090 return r;
5091 return tgsi_helper_tempx_replicate(ctx);
5092 }
5093
5094 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5095 {
5096 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5097 struct r600_bytecode_alu alu;
5098 int i, r, j;
5099 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5100 int tmp0 = ctx->temp_reg;
5101 int tmp1 = r600_get_temp(ctx);
5102 int tmp2 = r600_get_temp(ctx);
5103 int tmp3 = r600_get_temp(ctx);
5104 /* Unsigned path:
5105 *
5106 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5107 *
5108 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5109 * 2. tmp0.z = lo (tmp0.x * src2)
5110 * 3. tmp0.w = -tmp0.z
5111 * 4. tmp0.y = hi (tmp0.x * src2)
5112 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5113 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5114 * 7. tmp1.x = tmp0.x - tmp0.w
5115 * 8. tmp1.y = tmp0.x + tmp0.w
5116 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5117 * 10. tmp0.z = hi(tmp0.x * src1) = q
5118 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5119 *
5120 * 12. tmp0.w = src1 - tmp0.y = r
5121 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5122 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5123 *
5124 * if DIV
5125 *
5126 * 15. tmp1.z = tmp0.z + 1 = q + 1
5127 * 16. tmp1.w = tmp0.z - 1 = q - 1
5128 *
5129 * else MOD
5130 *
5131 * 15. tmp1.z = tmp0.w - src2 = r - src2
5132 * 16. tmp1.w = tmp0.w + src2 = r + src2
5133 *
5134 * endif
5135 *
5136 * 17. tmp1.x = tmp1.x & tmp1.y
5137 *
5138 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5139 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5140 *
5141 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5142 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5143 *
5144 * Signed path:
5145 *
5146 * Same as unsigned, using abs values of the operands,
5147 * and fixing the sign of the result in the end.
5148 */
5149
5150 for (i = 0; i < 4; i++) {
5151 if (!(write_mask & (1<<i)))
5152 continue;
5153
5154 if (signed_op) {
5155
5156 /* tmp2.x = -src0 */
5157 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5158 alu.op = ALU_OP2_SUB_INT;
5159
5160 alu.dst.sel = tmp2;
5161 alu.dst.chan = 0;
5162 alu.dst.write = 1;
5163
5164 alu.src[0].sel = V_SQ_ALU_SRC_0;
5165
5166 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5167
5168 alu.last = 1;
5169 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5170 return r;
5171
5172 /* tmp2.y = -src1 */
5173 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5174 alu.op = ALU_OP2_SUB_INT;
5175
5176 alu.dst.sel = tmp2;
5177 alu.dst.chan = 1;
5178 alu.dst.write = 1;
5179
5180 alu.src[0].sel = V_SQ_ALU_SRC_0;
5181
5182 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5183
5184 alu.last = 1;
5185 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5186 return r;
5187
5188 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5189 /* it will be a sign of the quotient */
5190 if (!mod) {
5191
5192 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5193 alu.op = ALU_OP2_XOR_INT;
5194
5195 alu.dst.sel = tmp2;
5196 alu.dst.chan = 2;
5197 alu.dst.write = 1;
5198
5199 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5200 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5201
5202 alu.last = 1;
5203 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5204 return r;
5205 }
5206
5207 /* tmp2.x = |src0| */
5208 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5209 alu.op = ALU_OP3_CNDGE_INT;
5210 alu.is_op3 = 1;
5211
5212 alu.dst.sel = tmp2;
5213 alu.dst.chan = 0;
5214 alu.dst.write = 1;
5215
5216 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5217 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5218 alu.src[2].sel = tmp2;
5219 alu.src[2].chan = 0;
5220
5221 alu.last = 1;
5222 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5223 return r;
5224
5225 /* tmp2.y = |src1| */
5226 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5227 alu.op = ALU_OP3_CNDGE_INT;
5228 alu.is_op3 = 1;
5229
5230 alu.dst.sel = tmp2;
5231 alu.dst.chan = 1;
5232 alu.dst.write = 1;
5233
5234 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5235 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5236 alu.src[2].sel = tmp2;
5237 alu.src[2].chan = 1;
5238
5239 alu.last = 1;
5240 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5241 return r;
5242
5243 }
5244
5245 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5246 if (ctx->bc->chip_class == CAYMAN) {
5247 /* tmp3.x = u2f(src2) */
5248 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5249 alu.op = ALU_OP1_UINT_TO_FLT;
5250
5251 alu.dst.sel = tmp3;
5252 alu.dst.chan = 0;
5253 alu.dst.write = 1;
5254
5255 if (signed_op) {
5256 alu.src[0].sel = tmp2;
5257 alu.src[0].chan = 1;
5258 } else {
5259 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5260 }
5261
5262 alu.last = 1;
5263 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5264 return r;
5265
5266 /* tmp0.x = recip(tmp3.x) */
5267 for (j = 0 ; j < 3; j++) {
5268 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5269 alu.op = ALU_OP1_RECIP_IEEE;
5270
5271 alu.dst.sel = tmp0;
5272 alu.dst.chan = j;
5273 alu.dst.write = (j == 0);
5274
5275 alu.src[0].sel = tmp3;
5276 alu.src[0].chan = 0;
5277
5278 if (j == 2)
5279 alu.last = 1;
5280 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5281 return r;
5282 }
5283
5284 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5285 alu.op = ALU_OP2_MUL;
5286
5287 alu.src[0].sel = tmp0;
5288 alu.src[0].chan = 0;
5289
5290 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5291 alu.src[1].value = 0x4f800000;
5292
5293 alu.dst.sel = tmp3;
5294 alu.dst.write = 1;
5295 alu.last = 1;
5296 r = r600_bytecode_add_alu(ctx->bc, &alu);
5297 if (r)
5298 return r;
5299
5300 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5301 alu.op = ALU_OP1_FLT_TO_UINT;
5302
5303 alu.dst.sel = tmp0;
5304 alu.dst.chan = 0;
5305 alu.dst.write = 1;
5306
5307 alu.src[0].sel = tmp3;
5308 alu.src[0].chan = 0;
5309
5310 alu.last = 1;
5311 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5312 return r;
5313
5314 } else {
5315 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5316 alu.op = ALU_OP1_RECIP_UINT;
5317
5318 alu.dst.sel = tmp0;
5319 alu.dst.chan = 0;
5320 alu.dst.write = 1;
5321
5322 if (signed_op) {
5323 alu.src[0].sel = tmp2;
5324 alu.src[0].chan = 1;
5325 } else {
5326 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5327 }
5328
5329 alu.last = 1;
5330 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5331 return r;
5332 }
5333
5334 /* 2. tmp0.z = lo (tmp0.x * src2) */
5335 if (ctx->bc->chip_class == CAYMAN) {
5336 for (j = 0 ; j < 4; j++) {
5337 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5338 alu.op = ALU_OP2_MULLO_UINT;
5339
5340 alu.dst.sel = tmp0;
5341 alu.dst.chan = j;
5342 alu.dst.write = (j == 2);
5343
5344 alu.src[0].sel = tmp0;
5345 alu.src[0].chan = 0;
5346 if (signed_op) {
5347 alu.src[1].sel = tmp2;
5348 alu.src[1].chan = 1;
5349 } else {
5350 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5351 }
5352
5353 alu.last = (j == 3);
5354 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5355 return r;
5356 }
5357 } else {
5358 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5359 alu.op = ALU_OP2_MULLO_UINT;
5360
5361 alu.dst.sel = tmp0;
5362 alu.dst.chan = 2;
5363 alu.dst.write = 1;
5364
5365 alu.src[0].sel = tmp0;
5366 alu.src[0].chan = 0;
5367 if (signed_op) {
5368 alu.src[1].sel = tmp2;
5369 alu.src[1].chan = 1;
5370 } else {
5371 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5372 }
5373
5374 alu.last = 1;
5375 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5376 return r;
5377 }
5378
5379 /* 3. tmp0.w = -tmp0.z */
5380 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5381 alu.op = ALU_OP2_SUB_INT;
5382
5383 alu.dst.sel = tmp0;
5384 alu.dst.chan = 3;
5385 alu.dst.write = 1;
5386
5387 alu.src[0].sel = V_SQ_ALU_SRC_0;
5388 alu.src[1].sel = tmp0;
5389 alu.src[1].chan = 2;
5390
5391 alu.last = 1;
5392 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5393 return r;
5394
5395 /* 4. tmp0.y = hi (tmp0.x * src2) */
5396 if (ctx->bc->chip_class == CAYMAN) {
5397 for (j = 0 ; j < 4; j++) {
5398 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5399 alu.op = ALU_OP2_MULHI_UINT;
5400
5401 alu.dst.sel = tmp0;
5402 alu.dst.chan = j;
5403 alu.dst.write = (j == 1);
5404
5405 alu.src[0].sel = tmp0;
5406 alu.src[0].chan = 0;
5407
5408 if (signed_op) {
5409 alu.src[1].sel = tmp2;
5410 alu.src[1].chan = 1;
5411 } else {
5412 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5413 }
5414 alu.last = (j == 3);
5415 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5416 return r;
5417 }
5418 } else {
5419 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5420 alu.op = ALU_OP2_MULHI_UINT;
5421
5422 alu.dst.sel = tmp0;
5423 alu.dst.chan = 1;
5424 alu.dst.write = 1;
5425
5426 alu.src[0].sel = tmp0;
5427 alu.src[0].chan = 0;
5428
5429 if (signed_op) {
5430 alu.src[1].sel = tmp2;
5431 alu.src[1].chan = 1;
5432 } else {
5433 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5434 }
5435
5436 alu.last = 1;
5437 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5438 return r;
5439 }
5440
5441 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5442 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5443 alu.op = ALU_OP3_CNDE_INT;
5444 alu.is_op3 = 1;
5445
5446 alu.dst.sel = tmp0;
5447 alu.dst.chan = 2;
5448 alu.dst.write = 1;
5449
5450 alu.src[0].sel = tmp0;
5451 alu.src[0].chan = 1;
5452 alu.src[1].sel = tmp0;
5453 alu.src[1].chan = 3;
5454 alu.src[2].sel = tmp0;
5455 alu.src[2].chan = 2;
5456
5457 alu.last = 1;
5458 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5459 return r;
5460
5461 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5462 if (ctx->bc->chip_class == CAYMAN) {
5463 for (j = 0 ; j < 4; j++) {
5464 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5465 alu.op = ALU_OP2_MULHI_UINT;
5466
5467 alu.dst.sel = tmp0;
5468 alu.dst.chan = j;
5469 alu.dst.write = (j == 3);
5470
5471 alu.src[0].sel = tmp0;
5472 alu.src[0].chan = 2;
5473
5474 alu.src[1].sel = tmp0;
5475 alu.src[1].chan = 0;
5476
5477 alu.last = (j == 3);
5478 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5479 return r;
5480 }
5481 } else {
5482 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5483 alu.op = ALU_OP2_MULHI_UINT;
5484
5485 alu.dst.sel = tmp0;
5486 alu.dst.chan = 3;
5487 alu.dst.write = 1;
5488
5489 alu.src[0].sel = tmp0;
5490 alu.src[0].chan = 2;
5491
5492 alu.src[1].sel = tmp0;
5493 alu.src[1].chan = 0;
5494
5495 alu.last = 1;
5496 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5497 return r;
5498 }
5499
5500 /* 7. tmp1.x = tmp0.x - tmp0.w */
5501 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5502 alu.op = ALU_OP2_SUB_INT;
5503
5504 alu.dst.sel = tmp1;
5505 alu.dst.chan = 0;
5506 alu.dst.write = 1;
5507
5508 alu.src[0].sel = tmp0;
5509 alu.src[0].chan = 0;
5510 alu.src[1].sel = tmp0;
5511 alu.src[1].chan = 3;
5512
5513 alu.last = 1;
5514 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5515 return r;
5516
5517 /* 8. tmp1.y = tmp0.x + tmp0.w */
5518 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5519 alu.op = ALU_OP2_ADD_INT;
5520
5521 alu.dst.sel = tmp1;
5522 alu.dst.chan = 1;
5523 alu.dst.write = 1;
5524
5525 alu.src[0].sel = tmp0;
5526 alu.src[0].chan = 0;
5527 alu.src[1].sel = tmp0;
5528 alu.src[1].chan = 3;
5529
5530 alu.last = 1;
5531 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5532 return r;
5533
5534 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5535 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5536 alu.op = ALU_OP3_CNDE_INT;
5537 alu.is_op3 = 1;
5538
5539 alu.dst.sel = tmp0;
5540 alu.dst.chan = 0;
5541 alu.dst.write = 1;
5542
5543 alu.src[0].sel = tmp0;
5544 alu.src[0].chan = 1;
5545 alu.src[1].sel = tmp1;
5546 alu.src[1].chan = 1;
5547 alu.src[2].sel = tmp1;
5548 alu.src[2].chan = 0;
5549
5550 alu.last = 1;
5551 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5552 return r;
5553
5554 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5555 if (ctx->bc->chip_class == CAYMAN) {
5556 for (j = 0 ; j < 4; j++) {
5557 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5558 alu.op = ALU_OP2_MULHI_UINT;
5559
5560 alu.dst.sel = tmp0;
5561 alu.dst.chan = j;
5562 alu.dst.write = (j == 2);
5563
5564 alu.src[0].sel = tmp0;
5565 alu.src[0].chan = 0;
5566
5567 if (signed_op) {
5568 alu.src[1].sel = tmp2;
5569 alu.src[1].chan = 0;
5570 } else {
5571 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5572 }
5573
5574 alu.last = (j == 3);
5575 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5576 return r;
5577 }
5578 } else {
5579 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5580 alu.op = ALU_OP2_MULHI_UINT;
5581
5582 alu.dst.sel = tmp0;
5583 alu.dst.chan = 2;
5584 alu.dst.write = 1;
5585
5586 alu.src[0].sel = tmp0;
5587 alu.src[0].chan = 0;
5588
5589 if (signed_op) {
5590 alu.src[1].sel = tmp2;
5591 alu.src[1].chan = 0;
5592 } else {
5593 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5594 }
5595
5596 alu.last = 1;
5597 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5598 return r;
5599 }
5600
5601 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5602 if (ctx->bc->chip_class == CAYMAN) {
5603 for (j = 0 ; j < 4; j++) {
5604 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5605 alu.op = ALU_OP2_MULLO_UINT;
5606
5607 alu.dst.sel = tmp0;
5608 alu.dst.chan = j;
5609 alu.dst.write = (j == 1);
5610
5611 if (signed_op) {
5612 alu.src[0].sel = tmp2;
5613 alu.src[0].chan = 1;
5614 } else {
5615 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5616 }
5617
5618 alu.src[1].sel = tmp0;
5619 alu.src[1].chan = 2;
5620
5621 alu.last = (j == 3);
5622 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5623 return r;
5624 }
5625 } else {
5626 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5627 alu.op = ALU_OP2_MULLO_UINT;
5628
5629 alu.dst.sel = tmp0;
5630 alu.dst.chan = 1;
5631 alu.dst.write = 1;
5632
5633 if (signed_op) {
5634 alu.src[0].sel = tmp2;
5635 alu.src[0].chan = 1;
5636 } else {
5637 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5638 }
5639
5640 alu.src[1].sel = tmp0;
5641 alu.src[1].chan = 2;
5642
5643 alu.last = 1;
5644 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5645 return r;
5646 }
5647
5648 /* 12. tmp0.w = src1 - tmp0.y = r */
5649 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5650 alu.op = ALU_OP2_SUB_INT;
5651
5652 alu.dst.sel = tmp0;
5653 alu.dst.chan = 3;
5654 alu.dst.write = 1;
5655
5656 if (signed_op) {
5657 alu.src[0].sel = tmp2;
5658 alu.src[0].chan = 0;
5659 } else {
5660 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5661 }
5662
5663 alu.src[1].sel = tmp0;
5664 alu.src[1].chan = 1;
5665
5666 alu.last = 1;
5667 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5668 return r;
5669
5670 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5671 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5672 alu.op = ALU_OP2_SETGE_UINT;
5673
5674 alu.dst.sel = tmp1;
5675 alu.dst.chan = 0;
5676 alu.dst.write = 1;
5677
5678 alu.src[0].sel = tmp0;
5679 alu.src[0].chan = 3;
5680 if (signed_op) {
5681 alu.src[1].sel = tmp2;
5682 alu.src[1].chan = 1;
5683 } else {
5684 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5685 }
5686
5687 alu.last = 1;
5688 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5689 return r;
5690
5691 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5692 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5693 alu.op = ALU_OP2_SETGE_UINT;
5694
5695 alu.dst.sel = tmp1;
5696 alu.dst.chan = 1;
5697 alu.dst.write = 1;
5698
5699 if (signed_op) {
5700 alu.src[0].sel = tmp2;
5701 alu.src[0].chan = 0;
5702 } else {
5703 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5704 }
5705
5706 alu.src[1].sel = tmp0;
5707 alu.src[1].chan = 1;
5708
5709 alu.last = 1;
5710 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5711 return r;
5712
5713 if (mod) { /* UMOD */
5714
5715 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5716 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5717 alu.op = ALU_OP2_SUB_INT;
5718
5719 alu.dst.sel = tmp1;
5720 alu.dst.chan = 2;
5721 alu.dst.write = 1;
5722
5723 alu.src[0].sel = tmp0;
5724 alu.src[0].chan = 3;
5725
5726 if (signed_op) {
5727 alu.src[1].sel = tmp2;
5728 alu.src[1].chan = 1;
5729 } else {
5730 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5731 }
5732
5733 alu.last = 1;
5734 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5735 return r;
5736
5737 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5738 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5739 alu.op = ALU_OP2_ADD_INT;
5740
5741 alu.dst.sel = tmp1;
5742 alu.dst.chan = 3;
5743 alu.dst.write = 1;
5744
5745 alu.src[0].sel = tmp0;
5746 alu.src[0].chan = 3;
5747 if (signed_op) {
5748 alu.src[1].sel = tmp2;
5749 alu.src[1].chan = 1;
5750 } else {
5751 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5752 }
5753
5754 alu.last = 1;
5755 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5756 return r;
5757
5758 } else { /* UDIV */
5759
5760 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5761 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5762 alu.op = ALU_OP2_ADD_INT;
5763
5764 alu.dst.sel = tmp1;
5765 alu.dst.chan = 2;
5766 alu.dst.write = 1;
5767
5768 alu.src[0].sel = tmp0;
5769 alu.src[0].chan = 2;
5770 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5771
5772 alu.last = 1;
5773 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5774 return r;
5775
5776 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5777 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5778 alu.op = ALU_OP2_ADD_INT;
5779
5780 alu.dst.sel = tmp1;
5781 alu.dst.chan = 3;
5782 alu.dst.write = 1;
5783
5784 alu.src[0].sel = tmp0;
5785 alu.src[0].chan = 2;
5786 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
5787
5788 alu.last = 1;
5789 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5790 return r;
5791
5792 }
5793
5794 /* 17. tmp1.x = tmp1.x & tmp1.y */
5795 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5796 alu.op = ALU_OP2_AND_INT;
5797
5798 alu.dst.sel = tmp1;
5799 alu.dst.chan = 0;
5800 alu.dst.write = 1;
5801
5802 alu.src[0].sel = tmp1;
5803 alu.src[0].chan = 0;
5804 alu.src[1].sel = tmp1;
5805 alu.src[1].chan = 1;
5806
5807 alu.last = 1;
5808 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5809 return r;
5810
5811 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5812 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5813 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5814 alu.op = ALU_OP3_CNDE_INT;
5815 alu.is_op3 = 1;
5816
5817 alu.dst.sel = tmp0;
5818 alu.dst.chan = 2;
5819 alu.dst.write = 1;
5820
5821 alu.src[0].sel = tmp1;
5822 alu.src[0].chan = 0;
5823 alu.src[1].sel = tmp0;
5824 alu.src[1].chan = mod ? 3 : 2;
5825 alu.src[2].sel = tmp1;
5826 alu.src[2].chan = 2;
5827
5828 alu.last = 1;
5829 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5830 return r;
5831
5832 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5833 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5834 alu.op = ALU_OP3_CNDE_INT;
5835 alu.is_op3 = 1;
5836
5837 if (signed_op) {
5838 alu.dst.sel = tmp0;
5839 alu.dst.chan = 2;
5840 alu.dst.write = 1;
5841 } else {
5842 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5843 }
5844
5845 alu.src[0].sel = tmp1;
5846 alu.src[0].chan = 1;
5847 alu.src[1].sel = tmp1;
5848 alu.src[1].chan = 3;
5849 alu.src[2].sel = tmp0;
5850 alu.src[2].chan = 2;
5851
5852 alu.last = 1;
5853 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5854 return r;
5855
5856 if (signed_op) {
5857
5858 /* fix the sign of the result */
5859
5860 if (mod) {
5861
5862 /* tmp0.x = -tmp0.z */
5863 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5864 alu.op = ALU_OP2_SUB_INT;
5865
5866 alu.dst.sel = tmp0;
5867 alu.dst.chan = 0;
5868 alu.dst.write = 1;
5869
5870 alu.src[0].sel = V_SQ_ALU_SRC_0;
5871 alu.src[1].sel = tmp0;
5872 alu.src[1].chan = 2;
5873
5874 alu.last = 1;
5875 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5876 return r;
5877
5878 /* sign of the remainder is the same as the sign of src0 */
5879 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5880 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5881 alu.op = ALU_OP3_CNDGE_INT;
5882 alu.is_op3 = 1;
5883
5884 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5885
5886 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5887 alu.src[1].sel = tmp0;
5888 alu.src[1].chan = 2;
5889 alu.src[2].sel = tmp0;
5890 alu.src[2].chan = 0;
5891
5892 alu.last = 1;
5893 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5894 return r;
5895
5896 } else {
5897
5898 /* tmp0.x = -tmp0.z */
5899 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5900 alu.op = ALU_OP2_SUB_INT;
5901
5902 alu.dst.sel = tmp0;
5903 alu.dst.chan = 0;
5904 alu.dst.write = 1;
5905
5906 alu.src[0].sel = V_SQ_ALU_SRC_0;
5907 alu.src[1].sel = tmp0;
5908 alu.src[1].chan = 2;
5909
5910 alu.last = 1;
5911 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5912 return r;
5913
5914 /* fix the quotient sign (same as the sign of src0*src1) */
5915 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5916 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5917 alu.op = ALU_OP3_CNDGE_INT;
5918 alu.is_op3 = 1;
5919
5920 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5921
5922 alu.src[0].sel = tmp2;
5923 alu.src[0].chan = 2;
5924 alu.src[1].sel = tmp0;
5925 alu.src[1].chan = 2;
5926 alu.src[2].sel = tmp0;
5927 alu.src[2].chan = 0;
5928
5929 alu.last = 1;
5930 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5931 return r;
5932 }
5933 }
5934 }
5935 return 0;
5936 }
5937
5938 static int tgsi_udiv(struct r600_shader_ctx *ctx)
5939 {
5940 return tgsi_divmod(ctx, 0, 0);
5941 }
5942
5943 static int tgsi_umod(struct r600_shader_ctx *ctx)
5944 {
5945 return tgsi_divmod(ctx, 1, 0);
5946 }
5947
5948 static int tgsi_idiv(struct r600_shader_ctx *ctx)
5949 {
5950 return tgsi_divmod(ctx, 0, 1);
5951 }
5952
5953 static int tgsi_imod(struct r600_shader_ctx *ctx)
5954 {
5955 return tgsi_divmod(ctx, 1, 1);
5956 }
5957
5958
5959 static int tgsi_f2i(struct r600_shader_ctx *ctx)
5960 {
5961 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5962 struct r600_bytecode_alu alu;
5963 int i, r;
5964 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5965 int last_inst = tgsi_last_instruction(write_mask);
5966
5967 for (i = 0; i < 4; i++) {
5968 if (!(write_mask & (1<<i)))
5969 continue;
5970
5971 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5972 alu.op = ALU_OP1_TRUNC;
5973
5974 alu.dst.sel = ctx->temp_reg;
5975 alu.dst.chan = i;
5976 alu.dst.write = 1;
5977
5978 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5979 if (i == last_inst)
5980 alu.last = 1;
5981 r = r600_bytecode_add_alu(ctx->bc, &alu);
5982 if (r)
5983 return r;
5984 }
5985
5986 for (i = 0; i < 4; i++) {
5987 if (!(write_mask & (1<<i)))
5988 continue;
5989
5990 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5991 alu.op = ctx->inst_info->op;
5992
5993 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5994
5995 alu.src[0].sel = ctx->temp_reg;
5996 alu.src[0].chan = i;
5997
5998 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
5999 alu.last = 1;
6000 r = r600_bytecode_add_alu(ctx->bc, &alu);
6001 if (r)
6002 return r;
6003 }
6004
6005 return 0;
6006 }
6007
6008 static int tgsi_iabs(struct r600_shader_ctx *ctx)
6009 {
6010 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6011 struct r600_bytecode_alu alu;
6012 int i, r;
6013 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6014 int last_inst = tgsi_last_instruction(write_mask);
6015
6016 /* tmp = -src */
6017 for (i = 0; i < 4; i++) {
6018 if (!(write_mask & (1<<i)))
6019 continue;
6020
6021 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6022 alu.op = ALU_OP2_SUB_INT;
6023
6024 alu.dst.sel = ctx->temp_reg;
6025 alu.dst.chan = i;
6026 alu.dst.write = 1;
6027
6028 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6029 alu.src[0].sel = V_SQ_ALU_SRC_0;
6030
6031 if (i == last_inst)
6032 alu.last = 1;
6033 r = r600_bytecode_add_alu(ctx->bc, &alu);
6034 if (r)
6035 return r;
6036 }
6037
6038 /* dst = (src >= 0 ? src : tmp) */
6039 for (i = 0; i < 4; i++) {
6040 if (!(write_mask & (1<<i)))
6041 continue;
6042
6043 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6044 alu.op = ALU_OP3_CNDGE_INT;
6045 alu.is_op3 = 1;
6046 alu.dst.write = 1;
6047
6048 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6049
6050 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6051 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6052 alu.src[2].sel = ctx->temp_reg;
6053 alu.src[2].chan = i;
6054
6055 if (i == last_inst)
6056 alu.last = 1;
6057 r = r600_bytecode_add_alu(ctx->bc, &alu);
6058 if (r)
6059 return r;
6060 }
6061 return 0;
6062 }
6063
6064 static int tgsi_issg(struct r600_shader_ctx *ctx)
6065 {
6066 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6067 struct r600_bytecode_alu alu;
6068 int i, r;
6069 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6070 int last_inst = tgsi_last_instruction(write_mask);
6071
6072 /* tmp = (src >= 0 ? src : -1) */
6073 for (i = 0; i < 4; i++) {
6074 if (!(write_mask & (1<<i)))
6075 continue;
6076
6077 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6078 alu.op = ALU_OP3_CNDGE_INT;
6079 alu.is_op3 = 1;
6080
6081 alu.dst.sel = ctx->temp_reg;
6082 alu.dst.chan = i;
6083 alu.dst.write = 1;
6084
6085 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6086 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6087 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6088
6089 if (i == last_inst)
6090 alu.last = 1;
6091 r = r600_bytecode_add_alu(ctx->bc, &alu);
6092 if (r)
6093 return r;
6094 }
6095
6096 /* dst = (tmp > 0 ? 1 : tmp) */
6097 for (i = 0; i < 4; i++) {
6098 if (!(write_mask & (1<<i)))
6099 continue;
6100
6101 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6102 alu.op = ALU_OP3_CNDGT_INT;
6103 alu.is_op3 = 1;
6104 alu.dst.write = 1;
6105
6106 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6107
6108 alu.src[0].sel = ctx->temp_reg;
6109 alu.src[0].chan = i;
6110
6111 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6112
6113 alu.src[2].sel = ctx->temp_reg;
6114 alu.src[2].chan = i;
6115
6116 if (i == last_inst)
6117 alu.last = 1;
6118 r = r600_bytecode_add_alu(ctx->bc, &alu);
6119 if (r)
6120 return r;
6121 }
6122 return 0;
6123 }
6124
6125
6126
6127 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6128 {
6129 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6130 struct r600_bytecode_alu alu;
6131 int i, r;
6132
6133 /* tmp = (src > 0 ? 1 : src) */
6134 for (i = 0; i < 4; i++) {
6135 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6136 alu.op = ALU_OP3_CNDGT;
6137 alu.is_op3 = 1;
6138
6139 alu.dst.sel = ctx->temp_reg;
6140 alu.dst.chan = i;
6141
6142 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6143 alu.src[1].sel = V_SQ_ALU_SRC_1;
6144 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6145
6146 if (i == 3)
6147 alu.last = 1;
6148 r = r600_bytecode_add_alu(ctx->bc, &alu);
6149 if (r)
6150 return r;
6151 }
6152
6153 /* dst = (-tmp > 0 ? -1 : tmp) */
6154 for (i = 0; i < 4; i++) {
6155 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6156 alu.op = ALU_OP3_CNDGT;
6157 alu.is_op3 = 1;
6158 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6159
6160 alu.src[0].sel = ctx->temp_reg;
6161 alu.src[0].chan = i;
6162 alu.src[0].neg = 1;
6163
6164 alu.src[1].sel = V_SQ_ALU_SRC_1;
6165 alu.src[1].neg = 1;
6166
6167 alu.src[2].sel = ctx->temp_reg;
6168 alu.src[2].chan = i;
6169
6170 if (i == 3)
6171 alu.last = 1;
6172 r = r600_bytecode_add_alu(ctx->bc, &alu);
6173 if (r)
6174 return r;
6175 }
6176 return 0;
6177 }
6178
6179 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6180 {
6181 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6182 struct r600_bytecode_alu alu;
6183 int i, r, t1, t2;
6184
6185 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6186 int last_inst = tgsi_last_instruction(write_mask);
6187
6188 t1 = r600_get_temp(ctx);
6189
6190 for (i = 0; i < 4; i++) {
6191 if (!(write_mask & (1<<i)))
6192 continue;
6193
6194 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6195 alu.op = ALU_OP2_SETGE_INT;
6196 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6197 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6198 alu.src[1].value = 32;
6199 alu.dst.sel = ctx->temp_reg;
6200 alu.dst.chan = i;
6201 alu.dst.write = 1;
6202 alu.last = i == last_inst;
6203 r = r600_bytecode_add_alu(ctx->bc, &alu);
6204 if (r)
6205 return r;
6206 }
6207
6208 for (i = 0; i < 4; i++) {
6209 if (!(write_mask & (1<<i)))
6210 continue;
6211
6212 /* create mask tmp */
6213 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6214 alu.op = ALU_OP2_BFM_INT;
6215 alu.dst.sel = t1;
6216 alu.dst.chan = i;
6217 alu.dst.write = 1;
6218 alu.last = i == last_inst;
6219
6220 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6221 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6222
6223 r = r600_bytecode_add_alu(ctx->bc, &alu);
6224 if (r)
6225 return r;
6226 }
6227
6228 t2 = r600_get_temp(ctx);
6229
6230 for (i = 0; i < 4; i++) {
6231 if (!(write_mask & (1<<i)))
6232 continue;
6233
6234 /* shift insert left */
6235 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6236 alu.op = ALU_OP2_LSHL_INT;
6237 alu.dst.sel = t2;
6238 alu.dst.chan = i;
6239 alu.dst.write = 1;
6240 alu.last = i == last_inst;
6241
6242 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6243 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6244
6245 r = r600_bytecode_add_alu(ctx->bc, &alu);
6246 if (r)
6247 return r;
6248 }
6249
6250 for (i = 0; i < 4; i++) {
6251 if (!(write_mask & (1<<i)))
6252 continue;
6253
6254 /* actual bitfield insert */
6255 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6256 alu.op = ALU_OP3_BFI_INT;
6257 alu.is_op3 = 1;
6258 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6259 alu.dst.chan = i;
6260 alu.dst.write = 1;
6261 alu.last = i == last_inst;
6262
6263 alu.src[0].sel = t1;
6264 alu.src[0].chan = i;
6265 alu.src[1].sel = t2;
6266 alu.src[1].chan = i;
6267 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6268
6269 r = r600_bytecode_add_alu(ctx->bc, &alu);
6270 if (r)
6271 return r;
6272 }
6273
6274 for (i = 0; i < 4; i++) {
6275 if (!(write_mask & (1<<i)))
6276 continue;
6277 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6278 alu.op = ALU_OP3_CNDE_INT;
6279 alu.is_op3 = 1;
6280 alu.src[0].sel = ctx->temp_reg;
6281 alu.src[0].chan = i;
6282 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6283
6284 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6285
6286 alu.src[1].sel = alu.dst.sel;
6287 alu.src[1].chan = i;
6288
6289 alu.last = i == last_inst;
6290 r = r600_bytecode_add_alu(ctx->bc, &alu);
6291 if (r)
6292 return r;
6293 }
6294 return 0;
6295 }
6296
6297 static int tgsi_msb(struct r600_shader_ctx *ctx)
6298 {
6299 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6300 struct r600_bytecode_alu alu;
6301 int i, r, t1, t2;
6302
6303 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6304 int last_inst = tgsi_last_instruction(write_mask);
6305
6306 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6307 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6308
6309 t1 = ctx->temp_reg;
6310
6311 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6312 for (i = 0; i < 4; i++) {
6313 if (!(write_mask & (1<<i)))
6314 continue;
6315
6316 /* t1 = FFBH_INT / FFBH_UINT */
6317 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6318 alu.op = ctx->inst_info->op;
6319 alu.dst.sel = t1;
6320 alu.dst.chan = i;
6321 alu.dst.write = 1;
6322 alu.last = i == last_inst;
6323
6324 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6325
6326 r = r600_bytecode_add_alu(ctx->bc, &alu);
6327 if (r)
6328 return r;
6329 }
6330
6331 t2 = r600_get_temp(ctx);
6332
6333 for (i = 0; i < 4; i++) {
6334 if (!(write_mask & (1<<i)))
6335 continue;
6336
6337 /* t2 = 31 - t1 */
6338 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6339 alu.op = ALU_OP2_SUB_INT;
6340 alu.dst.sel = t2;
6341 alu.dst.chan = i;
6342 alu.dst.write = 1;
6343 alu.last = i == last_inst;
6344
6345 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6346 alu.src[0].value = 31;
6347 alu.src[1].sel = t1;
6348 alu.src[1].chan = i;
6349
6350 r = r600_bytecode_add_alu(ctx->bc, &alu);
6351 if (r)
6352 return r;
6353 }
6354
6355 for (i = 0; i < 4; i++) {
6356 if (!(write_mask & (1<<i)))
6357 continue;
6358
6359 /* result = t1 >= 0 ? t2 : t1 */
6360 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6361 alu.op = ALU_OP3_CNDGE_INT;
6362 alu.is_op3 = 1;
6363 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6364 alu.dst.chan = i;
6365 alu.dst.write = 1;
6366 alu.last = i == last_inst;
6367
6368 alu.src[0].sel = t1;
6369 alu.src[0].chan = i;
6370 alu.src[1].sel = t2;
6371 alu.src[1].chan = i;
6372 alu.src[2].sel = t1;
6373 alu.src[2].chan = i;
6374
6375 r = r600_bytecode_add_alu(ctx->bc, &alu);
6376 if (r)
6377 return r;
6378 }
6379
6380 return 0;
6381 }
6382
6383 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6384 {
6385 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6386 struct r600_bytecode_alu alu;
6387 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6388 unsigned location;
6389 const int input = inst->Src[0].Register.Index + ctx->shader->nsys_inputs;
6390
6391 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6392
6393 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6394 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6395 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6396 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6397 }
6398 else {
6399 location = TGSI_INTERPOLATE_LOC_CENTROID;
6400 }
6401
6402 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6403 if (k < 0)
6404 k = 0;
6405 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6406 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6407
6408 /* NOTE: currently offset is not perspective correct */
6409 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6410 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6411 int sample_gpr = -1;
6412 int gradientsH, gradientsV;
6413 struct r600_bytecode_tex tex;
6414
6415 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6416 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6417 }
6418
6419 gradientsH = r600_get_temp(ctx);
6420 gradientsV = r600_get_temp(ctx);
6421 for (i = 0; i < 2; i++) {
6422 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6423 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6424 tex.src_gpr = interp_gpr;
6425 tex.src_sel_x = interp_base_chan + 0;
6426 tex.src_sel_y = interp_base_chan + 1;
6427 tex.src_sel_z = 0;
6428 tex.src_sel_w = 0;
6429 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6430 tex.dst_sel_x = 0;
6431 tex.dst_sel_y = 1;
6432 tex.dst_sel_z = 7;
6433 tex.dst_sel_w = 7;
6434 tex.inst_mod = 1; // Use per pixel gradient calculation
6435 tex.sampler_id = 0;
6436 tex.resource_id = tex.sampler_id;
6437 r = r600_bytecode_add_tex(ctx->bc, &tex);
6438 if (r)
6439 return r;
6440 }
6441
6442 for (i = 0; i < 2; i++) {
6443 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6444 alu.op = ALU_OP3_MULADD;
6445 alu.is_op3 = 1;
6446 alu.src[0].sel = gradientsH;
6447 alu.src[0].chan = i;
6448 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6449 alu.src[1].sel = sample_gpr;
6450 alu.src[1].chan = 2;
6451 }
6452 else {
6453 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6454 }
6455 alu.src[2].sel = interp_gpr;
6456 alu.src[2].chan = interp_base_chan + i;
6457 alu.dst.sel = ctx->temp_reg;
6458 alu.dst.chan = i;
6459 alu.last = i == 1;
6460
6461 r = r600_bytecode_add_alu(ctx->bc, &alu);
6462 if (r)
6463 return r;
6464 }
6465
6466 for (i = 0; i < 2; i++) {
6467 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6468 alu.op = ALU_OP3_MULADD;
6469 alu.is_op3 = 1;
6470 alu.src[0].sel = gradientsV;
6471 alu.src[0].chan = i;
6472 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6473 alu.src[1].sel = sample_gpr;
6474 alu.src[1].chan = 3;
6475 }
6476 else {
6477 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6478 }
6479 alu.src[2].sel = ctx->temp_reg;
6480 alu.src[2].chan = i;
6481 alu.dst.sel = ctx->temp_reg;
6482 alu.dst.chan = i;
6483 alu.last = i == 1;
6484
6485 r = r600_bytecode_add_alu(ctx->bc, &alu);
6486 if (r)
6487 return r;
6488 }
6489 }
6490
6491 tmp = r600_get_temp(ctx);
6492 for (i = 0; i < 8; i++) {
6493 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6494 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6495
6496 alu.dst.sel = tmp;
6497 if ((i > 1 && i < 6)) {
6498 alu.dst.write = 1;
6499 }
6500 else {
6501 alu.dst.write = 0;
6502 }
6503 alu.dst.chan = i % 4;
6504
6505 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6506 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6507 alu.src[0].sel = ctx->temp_reg;
6508 alu.src[0].chan = 1 - (i % 2);
6509 } else {
6510 alu.src[0].sel = interp_gpr;
6511 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
6512 }
6513 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
6514 alu.src[1].chan = 0;
6515
6516 alu.last = i % 4 == 3;
6517 alu.bank_swizzle_force = SQ_ALU_VEC_210;
6518
6519 r = r600_bytecode_add_alu(ctx->bc, &alu);
6520 if (r)
6521 return r;
6522 }
6523
6524 // INTERP can't swizzle dst
6525 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6526 for (i = 0; i <= lasti; i++) {
6527 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6528 continue;
6529
6530 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6531 alu.op = ALU_OP1_MOV;
6532 alu.src[0].sel = tmp;
6533 alu.src[0].chan = ctx->src[0].swizzle[i];
6534 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6535 alu.dst.write = 1;
6536 alu.last = i == lasti;
6537 r = r600_bytecode_add_alu(ctx->bc, &alu);
6538 if (r)
6539 return r;
6540 }
6541
6542 return 0;
6543 }
6544
6545
6546 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
6547 {
6548 struct r600_bytecode_alu alu;
6549 int i, r;
6550
6551 for (i = 0; i < 4; i++) {
6552 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6553 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
6554 alu.op = ALU_OP0_NOP;
6555 alu.dst.chan = i;
6556 } else {
6557 alu.op = ALU_OP1_MOV;
6558 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6559 alu.src[0].sel = ctx->temp_reg;
6560 alu.src[0].chan = i;
6561 }
6562 if (i == 3) {
6563 alu.last = 1;
6564 }
6565 r = r600_bytecode_add_alu(ctx->bc, &alu);
6566 if (r)
6567 return r;
6568 }
6569 return 0;
6570 }
6571
6572 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
6573 unsigned temp, int chan,
6574 struct r600_bytecode_alu_src *bc_src,
6575 const struct r600_shader_src *shader_src)
6576 {
6577 struct r600_bytecode_alu alu;
6578 int r;
6579
6580 r600_bytecode_src(bc_src, shader_src, chan);
6581
6582 /* op3 operands don't support abs modifier */
6583 if (bc_src->abs) {
6584 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
6585 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6586 alu.op = ALU_OP1_MOV;
6587 alu.dst.sel = temp;
6588 alu.dst.chan = chan;
6589 alu.dst.write = 1;
6590
6591 alu.src[0] = *bc_src;
6592 alu.last = true; // sufficient?
6593 r = r600_bytecode_add_alu(ctx->bc, &alu);
6594 if (r)
6595 return r;
6596
6597 memset(bc_src, 0, sizeof(*bc_src));
6598 bc_src->sel = temp;
6599 bc_src->chan = chan;
6600 }
6601 return 0;
6602 }
6603
6604 static int tgsi_op3(struct r600_shader_ctx *ctx)
6605 {
6606 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6607 struct r600_bytecode_alu alu;
6608 int i, j, r;
6609 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6610 int temp_regs[4];
6611 unsigned op = ctx->inst_info->op;
6612
6613 if (op == ALU_OP3_MULADD_IEEE &&
6614 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6615 op = ALU_OP3_MULADD;
6616
6617 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6618 temp_regs[j] = 0;
6619 if (ctx->src[j].abs)
6620 temp_regs[j] = r600_get_temp(ctx);
6621 }
6622 for (i = 0; i < lasti + 1; i++) {
6623 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6624 continue;
6625
6626 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6627 alu.op = op;
6628 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6629 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
6630 if (r)
6631 return r;
6632 }
6633
6634 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6635 alu.dst.chan = i;
6636 alu.dst.write = 1;
6637 alu.is_op3 = 1;
6638 if (i == lasti) {
6639 alu.last = 1;
6640 }
6641 r = r600_bytecode_add_alu(ctx->bc, &alu);
6642 if (r)
6643 return r;
6644 }
6645 return 0;
6646 }
6647
6648 static int tgsi_dp(struct r600_shader_ctx *ctx)
6649 {
6650 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6651 struct r600_bytecode_alu alu;
6652 int i, j, r;
6653 unsigned op = ctx->inst_info->op;
6654 if (op == ALU_OP2_DOT4_IEEE &&
6655 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6656 op = ALU_OP2_DOT4;
6657
6658 for (i = 0; i < 4; i++) {
6659 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6660 alu.op = op;
6661 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6662 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6663 }
6664
6665 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6666 alu.dst.chan = i;
6667 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
6668 /* handle some special cases */
6669 switch (inst->Instruction.Opcode) {
6670 case TGSI_OPCODE_DP2:
6671 if (i > 1) {
6672 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6673 alu.src[0].chan = alu.src[1].chan = 0;
6674 }
6675 break;
6676 case TGSI_OPCODE_DP3:
6677 if (i > 2) {
6678 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6679 alu.src[0].chan = alu.src[1].chan = 0;
6680 }
6681 break;
6682 default:
6683 break;
6684 }
6685 if (i == 3) {
6686 alu.last = 1;
6687 }
6688 r = r600_bytecode_add_alu(ctx->bc, &alu);
6689 if (r)
6690 return r;
6691 }
6692 return 0;
6693 }
6694
6695 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
6696 unsigned index)
6697 {
6698 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6699 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
6700 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
6701 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
6702 ctx->src[index].neg || ctx->src[index].abs ||
6703 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
6704 }
6705
6706 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
6707 unsigned index)
6708 {
6709 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6710 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
6711 }
6712
6713 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
6714 {
6715 struct r600_bytecode_vtx vtx;
6716 struct r600_bytecode_alu alu;
6717 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6718 int src_gpr, r, i;
6719 int id = tgsi_tex_get_src_gpr(ctx, 1);
6720
6721 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6722 if (src_requires_loading) {
6723 for (i = 0; i < 4; i++) {
6724 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6725 alu.op = ALU_OP1_MOV;
6726 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6727 alu.dst.sel = ctx->temp_reg;
6728 alu.dst.chan = i;
6729 if (i == 3)
6730 alu.last = 1;
6731 alu.dst.write = 1;
6732 r = r600_bytecode_add_alu(ctx->bc, &alu);
6733 if (r)
6734 return r;
6735 }
6736 src_gpr = ctx->temp_reg;
6737 }
6738
6739 memset(&vtx, 0, sizeof(vtx));
6740 vtx.op = FETCH_OP_VFETCH;
6741 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6742 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6743 vtx.src_gpr = src_gpr;
6744 vtx.mega_fetch_count = 16;
6745 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6746 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6747 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
6748 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
6749 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
6750 vtx.use_const_fields = 1;
6751
6752 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
6753 return r;
6754
6755 if (ctx->bc->chip_class >= EVERGREEN)
6756 return 0;
6757
6758 for (i = 0; i < 4; i++) {
6759 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6760 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6761 continue;
6762
6763 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6764 alu.op = ALU_OP2_AND_INT;
6765
6766 alu.dst.chan = i;
6767 alu.dst.sel = vtx.dst_gpr;
6768 alu.dst.write = 1;
6769
6770 alu.src[0].sel = vtx.dst_gpr;
6771 alu.src[0].chan = i;
6772
6773 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
6774 alu.src[1].sel += (id * 2);
6775 alu.src[1].chan = i % 4;
6776 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6777
6778 if (i == lasti)
6779 alu.last = 1;
6780 r = r600_bytecode_add_alu(ctx->bc, &alu);
6781 if (r)
6782 return r;
6783 }
6784
6785 if (inst->Dst[0].Register.WriteMask & 3) {
6786 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6787 alu.op = ALU_OP2_OR_INT;
6788
6789 alu.dst.chan = 3;
6790 alu.dst.sel = vtx.dst_gpr;
6791 alu.dst.write = 1;
6792
6793 alu.src[0].sel = vtx.dst_gpr;
6794 alu.src[0].chan = 3;
6795
6796 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
6797 alu.src[1].chan = 0;
6798 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6799
6800 alu.last = 1;
6801 r = r600_bytecode_add_alu(ctx->bc, &alu);
6802 if (r)
6803 return r;
6804 }
6805 return 0;
6806 }
6807
6808 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
6809 {
6810 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6811 struct r600_bytecode_alu alu;
6812 int r;
6813 int id = tgsi_tex_get_src_gpr(ctx, 1);
6814
6815 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6816 alu.op = ALU_OP1_MOV;
6817 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6818 if (ctx->bc->chip_class >= EVERGREEN) {
6819 /* channel 0 or 2 of each word */
6820 alu.src[0].sel += (id / 2);
6821 alu.src[0].chan = (id % 2) * 2;
6822 } else {
6823 /* r600 we have them at channel 2 of the second dword */
6824 alu.src[0].sel += (id * 2) + 1;
6825 alu.src[0].chan = 1;
6826 }
6827 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6828 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
6829 alu.last = 1;
6830 r = r600_bytecode_add_alu(ctx->bc, &alu);
6831 if (r)
6832 return r;
6833 return 0;
6834 }
6835
6836 static int tgsi_tex(struct r600_shader_ctx *ctx)
6837 {
6838 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6839 struct r600_bytecode_tex tex;
6840 struct r600_bytecode_alu alu;
6841 unsigned src_gpr;
6842 int r, i, j;
6843 int opcode;
6844 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
6845 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6846 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
6847 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
6848
6849 bool txf_add_offsets = inst->Texture.NumOffsets &&
6850 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6851 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
6852
6853 /* Texture fetch instructions can only use gprs as source.
6854 * Also they cannot negate the source or take the absolute value */
6855 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
6856 tgsi_tex_src_requires_loading(ctx, 0)) ||
6857 read_compressed_msaa || txf_add_offsets;
6858
6859 boolean src_loaded = FALSE;
6860 unsigned sampler_src_reg = 1;
6861 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
6862 boolean has_txq_cube_array_z = false;
6863 unsigned sampler_index_mode;
6864
6865 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
6866 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6867 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
6868 if (inst->Dst[0].Register.WriteMask & 4) {
6869 ctx->shader->has_txq_cube_array_z_comp = true;
6870 has_txq_cube_array_z = true;
6871 }
6872
6873 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
6874 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
6875 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
6876 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
6877 sampler_src_reg = 2;
6878
6879 /* TGSI moves the sampler to src reg 3 for TXD */
6880 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
6881 sampler_src_reg = 3;
6882
6883 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6884
6885 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6886
6887 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
6888 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
6889 ctx->shader->uses_tex_buffers = true;
6890 return r600_do_buffer_txq(ctx);
6891 }
6892 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
6893 if (ctx->bc->chip_class < EVERGREEN)
6894 ctx->shader->uses_tex_buffers = true;
6895 return do_vtx_fetch_inst(ctx, src_requires_loading);
6896 }
6897 }
6898
6899 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
6900 int out_chan;
6901 /* Add perspective divide */
6902 if (ctx->bc->chip_class == CAYMAN) {
6903 out_chan = 2;
6904 for (i = 0; i < 3; i++) {
6905 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6906 alu.op = ALU_OP1_RECIP_IEEE;
6907 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6908
6909 alu.dst.sel = ctx->temp_reg;
6910 alu.dst.chan = i;
6911 if (i == 2)
6912 alu.last = 1;
6913 if (out_chan == i)
6914 alu.dst.write = 1;
6915 r = r600_bytecode_add_alu(ctx->bc, &alu);
6916 if (r)
6917 return r;
6918 }
6919
6920 } else {
6921 out_chan = 3;
6922 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6923 alu.op = ALU_OP1_RECIP_IEEE;
6924 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6925
6926 alu.dst.sel = ctx->temp_reg;
6927 alu.dst.chan = out_chan;
6928 alu.last = 1;
6929 alu.dst.write = 1;
6930 r = r600_bytecode_add_alu(ctx->bc, &alu);
6931 if (r)
6932 return r;
6933 }
6934
6935 for (i = 0; i < 3; i++) {
6936 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6937 alu.op = ALU_OP2_MUL;
6938 alu.src[0].sel = ctx->temp_reg;
6939 alu.src[0].chan = out_chan;
6940 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6941 alu.dst.sel = ctx->temp_reg;
6942 alu.dst.chan = i;
6943 alu.dst.write = 1;
6944 r = r600_bytecode_add_alu(ctx->bc, &alu);
6945 if (r)
6946 return r;
6947 }
6948 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6949 alu.op = ALU_OP1_MOV;
6950 alu.src[0].sel = V_SQ_ALU_SRC_1;
6951 alu.src[0].chan = 0;
6952 alu.dst.sel = ctx->temp_reg;
6953 alu.dst.chan = 3;
6954 alu.last = 1;
6955 alu.dst.write = 1;
6956 r = r600_bytecode_add_alu(ctx->bc, &alu);
6957 if (r)
6958 return r;
6959 src_loaded = TRUE;
6960 src_gpr = ctx->temp_reg;
6961 }
6962
6963
6964 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
6965 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6966 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6967 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
6968 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
6969
6970 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
6971 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
6972
6973 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
6974 for (i = 0; i < 4; i++) {
6975 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6976 alu.op = ALU_OP2_CUBE;
6977 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6978 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
6979 alu.dst.sel = ctx->temp_reg;
6980 alu.dst.chan = i;
6981 if (i == 3)
6982 alu.last = 1;
6983 alu.dst.write = 1;
6984 r = r600_bytecode_add_alu(ctx->bc, &alu);
6985 if (r)
6986 return r;
6987 }
6988
6989 /* tmp1.z = RCP_e(|tmp1.z|) */
6990 if (ctx->bc->chip_class == CAYMAN) {
6991 for (i = 0; i < 3; i++) {
6992 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6993 alu.op = ALU_OP1_RECIP_IEEE;
6994 alu.src[0].sel = ctx->temp_reg;
6995 alu.src[0].chan = 2;
6996 alu.src[0].abs = 1;
6997 alu.dst.sel = ctx->temp_reg;
6998 alu.dst.chan = i;
6999 if (i == 2)
7000 alu.dst.write = 1;
7001 if (i == 2)
7002 alu.last = 1;
7003 r = r600_bytecode_add_alu(ctx->bc, &alu);
7004 if (r)
7005 return r;
7006 }
7007 } else {
7008 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7009 alu.op = ALU_OP1_RECIP_IEEE;
7010 alu.src[0].sel = ctx->temp_reg;
7011 alu.src[0].chan = 2;
7012 alu.src[0].abs = 1;
7013 alu.dst.sel = ctx->temp_reg;
7014 alu.dst.chan = 2;
7015 alu.dst.write = 1;
7016 alu.last = 1;
7017 r = r600_bytecode_add_alu(ctx->bc, &alu);
7018 if (r)
7019 return r;
7020 }
7021
7022 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
7023 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
7024 * muladd has no writemask, have to use another temp
7025 */
7026 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7027 alu.op = ALU_OP3_MULADD;
7028 alu.is_op3 = 1;
7029
7030 alu.src[0].sel = ctx->temp_reg;
7031 alu.src[0].chan = 0;
7032 alu.src[1].sel = ctx->temp_reg;
7033 alu.src[1].chan = 2;
7034
7035 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7036 alu.src[2].chan = 0;
7037 alu.src[2].value = u_bitcast_f2u(1.5f);
7038
7039 alu.dst.sel = ctx->temp_reg;
7040 alu.dst.chan = 0;
7041 alu.dst.write = 1;
7042
7043 r = r600_bytecode_add_alu(ctx->bc, &alu);
7044 if (r)
7045 return r;
7046
7047 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7048 alu.op = ALU_OP3_MULADD;
7049 alu.is_op3 = 1;
7050
7051 alu.src[0].sel = ctx->temp_reg;
7052 alu.src[0].chan = 1;
7053 alu.src[1].sel = ctx->temp_reg;
7054 alu.src[1].chan = 2;
7055
7056 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7057 alu.src[2].chan = 0;
7058 alu.src[2].value = u_bitcast_f2u(1.5f);
7059
7060 alu.dst.sel = ctx->temp_reg;
7061 alu.dst.chan = 1;
7062 alu.dst.write = 1;
7063
7064 alu.last = 1;
7065 r = r600_bytecode_add_alu(ctx->bc, &alu);
7066 if (r)
7067 return r;
7068 /* write initial compare value into Z component
7069 - W src 0 for shadow cube
7070 - X src 1 for shadow cube array */
7071 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7072 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7073 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7074 alu.op = ALU_OP1_MOV;
7075 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
7076 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7077 else
7078 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7079 alu.dst.sel = ctx->temp_reg;
7080 alu.dst.chan = 2;
7081 alu.dst.write = 1;
7082 alu.last = 1;
7083 r = r600_bytecode_add_alu(ctx->bc, &alu);
7084 if (r)
7085 return r;
7086 }
7087
7088 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7089 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7090 if (ctx->bc->chip_class >= EVERGREEN) {
7091 int mytmp = r600_get_temp(ctx);
7092 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7093 alu.op = ALU_OP1_MOV;
7094 alu.src[0].sel = ctx->temp_reg;
7095 alu.src[0].chan = 3;
7096 alu.dst.sel = mytmp;
7097 alu.dst.chan = 0;
7098 alu.dst.write = 1;
7099 alu.last = 1;
7100 r = r600_bytecode_add_alu(ctx->bc, &alu);
7101 if (r)
7102 return r;
7103
7104 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7105 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7106 alu.op = ALU_OP3_MULADD;
7107 alu.is_op3 = 1;
7108 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7109 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7110 alu.src[1].chan = 0;
7111 alu.src[1].value = u_bitcast_f2u(8.0f);
7112 alu.src[2].sel = mytmp;
7113 alu.src[2].chan = 0;
7114 alu.dst.sel = ctx->temp_reg;
7115 alu.dst.chan = 3;
7116 alu.dst.write = 1;
7117 alu.last = 1;
7118 r = r600_bytecode_add_alu(ctx->bc, &alu);
7119 if (r)
7120 return r;
7121 } else if (ctx->bc->chip_class < EVERGREEN) {
7122 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7123 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7124 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7125 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7126 tex.src_gpr = r600_get_temp(ctx);
7127 tex.src_sel_x = 0;
7128 tex.src_sel_y = 0;
7129 tex.src_sel_z = 0;
7130 tex.src_sel_w = 0;
7131 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7132 tex.coord_type_x = 1;
7133 tex.coord_type_y = 1;
7134 tex.coord_type_z = 1;
7135 tex.coord_type_w = 1;
7136 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7137 alu.op = ALU_OP1_MOV;
7138 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7139 alu.dst.sel = tex.src_gpr;
7140 alu.dst.chan = 0;
7141 alu.last = 1;
7142 alu.dst.write = 1;
7143 r = r600_bytecode_add_alu(ctx->bc, &alu);
7144 if (r)
7145 return r;
7146
7147 r = r600_bytecode_add_tex(ctx->bc, &tex);
7148 if (r)
7149 return r;
7150 }
7151
7152 }
7153
7154 /* for cube forms of lod and bias we need to route things */
7155 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7156 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7157 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7158 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7159 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7160 alu.op = ALU_OP1_MOV;
7161 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7162 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7163 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7164 else
7165 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7166 alu.dst.sel = ctx->temp_reg;
7167 alu.dst.chan = 2;
7168 alu.last = 1;
7169 alu.dst.write = 1;
7170 r = r600_bytecode_add_alu(ctx->bc, &alu);
7171 if (r)
7172 return r;
7173 }
7174
7175 src_loaded = TRUE;
7176 src_gpr = ctx->temp_reg;
7177 }
7178
7179 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7180 int temp_h = 0, temp_v = 0;
7181 int start_val = 0;
7182
7183 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7184 if (src_loaded == TRUE)
7185 start_val = 1;
7186 else
7187 src_loaded = TRUE;
7188 for (i = start_val; i < 3; i++) {
7189 int treg = r600_get_temp(ctx);
7190
7191 if (i == 0)
7192 src_gpr = treg;
7193 else if (i == 1)
7194 temp_h = treg;
7195 else
7196 temp_v = treg;
7197
7198 for (j = 0; j < 4; j++) {
7199 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7200 alu.op = ALU_OP1_MOV;
7201 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7202 alu.dst.sel = treg;
7203 alu.dst.chan = j;
7204 if (j == 3)
7205 alu.last = 1;
7206 alu.dst.write = 1;
7207 r = r600_bytecode_add_alu(ctx->bc, &alu);
7208 if (r)
7209 return r;
7210 }
7211 }
7212 for (i = 1; i < 3; i++) {
7213 /* set gradients h/v */
7214 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7215 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7216 FETCH_OP_SET_GRADIENTS_V;
7217 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7218 tex.sampler_index_mode = sampler_index_mode;
7219 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7220 tex.resource_index_mode = sampler_index_mode;
7221
7222 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7223 tex.src_sel_x = 0;
7224 tex.src_sel_y = 1;
7225 tex.src_sel_z = 2;
7226 tex.src_sel_w = 3;
7227
7228 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7229 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7230 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7231 tex.coord_type_x = 1;
7232 tex.coord_type_y = 1;
7233 tex.coord_type_z = 1;
7234 tex.coord_type_w = 1;
7235 }
7236 r = r600_bytecode_add_tex(ctx->bc, &tex);
7237 if (r)
7238 return r;
7239 }
7240 }
7241
7242 if (src_requires_loading && !src_loaded) {
7243 for (i = 0; i < 4; i++) {
7244 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7245 alu.op = ALU_OP1_MOV;
7246 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7247 alu.dst.sel = ctx->temp_reg;
7248 alu.dst.chan = i;
7249 if (i == 3)
7250 alu.last = 1;
7251 alu.dst.write = 1;
7252 r = r600_bytecode_add_alu(ctx->bc, &alu);
7253 if (r)
7254 return r;
7255 }
7256 src_loaded = TRUE;
7257 src_gpr = ctx->temp_reg;
7258 }
7259
7260 /* get offset values */
7261 if (inst->Texture.NumOffsets) {
7262 assert(inst->Texture.NumOffsets == 1);
7263
7264 /* The texture offset feature doesn't work with the TXF instruction
7265 * and must be emulated by adding the offset to the texture coordinates. */
7266 if (txf_add_offsets) {
7267 const struct tgsi_texture_offset *off = inst->TexOffsets;
7268
7269 switch (inst->Texture.Texture) {
7270 case TGSI_TEXTURE_3D:
7271 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7272 alu.op = ALU_OP2_ADD_INT;
7273 alu.src[0].sel = src_gpr;
7274 alu.src[0].chan = 2;
7275 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7276 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7277 alu.dst.sel = src_gpr;
7278 alu.dst.chan = 2;
7279 alu.dst.write = 1;
7280 alu.last = 1;
7281 r = r600_bytecode_add_alu(ctx->bc, &alu);
7282 if (r)
7283 return r;
7284 /* fall through */
7285
7286 case TGSI_TEXTURE_2D:
7287 case TGSI_TEXTURE_SHADOW2D:
7288 case TGSI_TEXTURE_RECT:
7289 case TGSI_TEXTURE_SHADOWRECT:
7290 case TGSI_TEXTURE_2D_ARRAY:
7291 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7292 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7293 alu.op = ALU_OP2_ADD_INT;
7294 alu.src[0].sel = src_gpr;
7295 alu.src[0].chan = 1;
7296 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7297 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7298 alu.dst.sel = src_gpr;
7299 alu.dst.chan = 1;
7300 alu.dst.write = 1;
7301 alu.last = 1;
7302 r = r600_bytecode_add_alu(ctx->bc, &alu);
7303 if (r)
7304 return r;
7305 /* fall through */
7306
7307 case TGSI_TEXTURE_1D:
7308 case TGSI_TEXTURE_SHADOW1D:
7309 case TGSI_TEXTURE_1D_ARRAY:
7310 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7311 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7312 alu.op = ALU_OP2_ADD_INT;
7313 alu.src[0].sel = src_gpr;
7314 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7315 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
7316 alu.dst.sel = src_gpr;
7317 alu.dst.write = 1;
7318 alu.last = 1;
7319 r = r600_bytecode_add_alu(ctx->bc, &alu);
7320 if (r)
7321 return r;
7322 break;
7323 /* texture offsets do not apply to other texture targets */
7324 }
7325 } else {
7326 switch (inst->Texture.Texture) {
7327 case TGSI_TEXTURE_3D:
7328 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
7329 /* fallthrough */
7330 case TGSI_TEXTURE_2D:
7331 case TGSI_TEXTURE_SHADOW2D:
7332 case TGSI_TEXTURE_RECT:
7333 case TGSI_TEXTURE_SHADOWRECT:
7334 case TGSI_TEXTURE_2D_ARRAY:
7335 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7336 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
7337 /* fallthrough */
7338 case TGSI_TEXTURE_1D:
7339 case TGSI_TEXTURE_SHADOW1D:
7340 case TGSI_TEXTURE_1D_ARRAY:
7341 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7342 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
7343 }
7344 }
7345 }
7346
7347 /* Obtain the sample index for reading a compressed MSAA color texture.
7348 * To read the FMASK, we use the ldfptr instruction, which tells us
7349 * where the samples are stored.
7350 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7351 * which is the identity mapping. Each nibble says which physical sample
7352 * should be fetched to get that sample.
7353 *
7354 * Assume src.z contains the sample index. It should be modified like this:
7355 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7356 * Then fetch the texel with src.
7357 */
7358 if (read_compressed_msaa) {
7359 unsigned sample_chan = 3;
7360 unsigned temp = r600_get_temp(ctx);
7361 assert(src_loaded);
7362
7363 /* temp.w = ldfptr() */
7364 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7365 tex.op = FETCH_OP_LD;
7366 tex.inst_mod = 1; /* to indicate this is ldfptr */
7367 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7368 tex.sampler_index_mode = sampler_index_mode;
7369 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7370 tex.resource_index_mode = sampler_index_mode;
7371 tex.src_gpr = src_gpr;
7372 tex.dst_gpr = temp;
7373 tex.dst_sel_x = 7; /* mask out these components */
7374 tex.dst_sel_y = 7;
7375 tex.dst_sel_z = 7;
7376 tex.dst_sel_w = 0; /* store X */
7377 tex.src_sel_x = 0;
7378 tex.src_sel_y = 1;
7379 tex.src_sel_z = 2;
7380 tex.src_sel_w = 3;
7381 tex.offset_x = offset_x;
7382 tex.offset_y = offset_y;
7383 tex.offset_z = offset_z;
7384 r = r600_bytecode_add_tex(ctx->bc, &tex);
7385 if (r)
7386 return r;
7387
7388 /* temp.x = sample_index*4 */
7389 if (ctx->bc->chip_class == CAYMAN) {
7390 for (i = 0 ; i < 4; i++) {
7391 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7392 alu.op = ALU_OP2_MULLO_INT;
7393 alu.src[0].sel = src_gpr;
7394 alu.src[0].chan = sample_chan;
7395 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7396 alu.src[1].value = 4;
7397 alu.dst.sel = temp;
7398 alu.dst.chan = i;
7399 alu.dst.write = i == 0;
7400 if (i == 3)
7401 alu.last = 1;
7402 r = r600_bytecode_add_alu(ctx->bc, &alu);
7403 if (r)
7404 return r;
7405 }
7406 } else {
7407 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7408 alu.op = ALU_OP2_MULLO_INT;
7409 alu.src[0].sel = src_gpr;
7410 alu.src[0].chan = sample_chan;
7411 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7412 alu.src[1].value = 4;
7413 alu.dst.sel = temp;
7414 alu.dst.chan = 0;
7415 alu.dst.write = 1;
7416 alu.last = 1;
7417 r = r600_bytecode_add_alu(ctx->bc, &alu);
7418 if (r)
7419 return r;
7420 }
7421
7422 /* sample_index = temp.w >> temp.x */
7423 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7424 alu.op = ALU_OP2_LSHR_INT;
7425 alu.src[0].sel = temp;
7426 alu.src[0].chan = 3;
7427 alu.src[1].sel = temp;
7428 alu.src[1].chan = 0;
7429 alu.dst.sel = src_gpr;
7430 alu.dst.chan = sample_chan;
7431 alu.dst.write = 1;
7432 alu.last = 1;
7433 r = r600_bytecode_add_alu(ctx->bc, &alu);
7434 if (r)
7435 return r;
7436
7437 /* sample_index & 0xF */
7438 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7439 alu.op = ALU_OP2_AND_INT;
7440 alu.src[0].sel = src_gpr;
7441 alu.src[0].chan = sample_chan;
7442 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7443 alu.src[1].value = 0xF;
7444 alu.dst.sel = src_gpr;
7445 alu.dst.chan = sample_chan;
7446 alu.dst.write = 1;
7447 alu.last = 1;
7448 r = r600_bytecode_add_alu(ctx->bc, &alu);
7449 if (r)
7450 return r;
7451 #if 0
7452 /* visualize the FMASK */
7453 for (i = 0; i < 4; i++) {
7454 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7455 alu.op = ALU_OP1_INT_TO_FLT;
7456 alu.src[0].sel = src_gpr;
7457 alu.src[0].chan = sample_chan;
7458 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7459 alu.dst.chan = i;
7460 alu.dst.write = 1;
7461 alu.last = 1;
7462 r = r600_bytecode_add_alu(ctx->bc, &alu);
7463 if (r)
7464 return r;
7465 }
7466 return 0;
7467 #endif
7468 }
7469
7470 /* does this shader want a num layers from TXQ for a cube array? */
7471 if (has_txq_cube_array_z) {
7472 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7473
7474 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7475 alu.op = ALU_OP1_MOV;
7476
7477 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7478 if (ctx->bc->chip_class >= EVERGREEN) {
7479 /* channel 1 or 3 of each word */
7480 alu.src[0].sel += (id / 2);
7481 alu.src[0].chan = ((id % 2) * 2) + 1;
7482 } else {
7483 /* r600 we have them at channel 2 of the second dword */
7484 alu.src[0].sel += (id * 2) + 1;
7485 alu.src[0].chan = 2;
7486 }
7487 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7488 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
7489 alu.last = 1;
7490 r = r600_bytecode_add_alu(ctx->bc, &alu);
7491 if (r)
7492 return r;
7493 /* disable writemask from texture instruction */
7494 inst->Dst[0].Register.WriteMask &= ~4;
7495 }
7496
7497 opcode = ctx->inst_info->op;
7498 if (opcode == FETCH_OP_GATHER4 &&
7499 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
7500 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
7501 opcode = FETCH_OP_GATHER4_O;
7502
7503 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7504 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7505 encoded in the instruction are ignored. */
7506 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7507 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
7508 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7509 tex.sampler_index_mode = sampler_index_mode;
7510 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7511 tex.resource_index_mode = sampler_index_mode;
7512
7513 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
7514 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
7515 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
7516 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
7517 tex.src_sel_w = 4;
7518
7519 tex.dst_sel_x = 7;
7520 tex.dst_sel_y = 7;
7521 tex.dst_sel_z = 7;
7522 tex.dst_sel_w = 7;
7523
7524 r = r600_bytecode_add_tex(ctx->bc, &tex);
7525 if (r)
7526 return r;
7527 }
7528
7529 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7530 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7531 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7532 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7533 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
7534 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7535 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7536 switch (opcode) {
7537 case FETCH_OP_SAMPLE:
7538 opcode = FETCH_OP_SAMPLE_C;
7539 break;
7540 case FETCH_OP_SAMPLE_L:
7541 opcode = FETCH_OP_SAMPLE_C_L;
7542 break;
7543 case FETCH_OP_SAMPLE_LB:
7544 opcode = FETCH_OP_SAMPLE_C_LB;
7545 break;
7546 case FETCH_OP_SAMPLE_G:
7547 opcode = FETCH_OP_SAMPLE_C_G;
7548 break;
7549 /* Texture gather variants */
7550 case FETCH_OP_GATHER4:
7551 opcode = FETCH_OP_GATHER4_C;
7552 break;
7553 case FETCH_OP_GATHER4_O:
7554 opcode = FETCH_OP_GATHER4_C_O;
7555 break;
7556 }
7557 }
7558
7559 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7560 tex.op = opcode;
7561
7562 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7563 tex.sampler_index_mode = sampler_index_mode;
7564 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7565 tex.resource_index_mode = sampler_index_mode;
7566 tex.src_gpr = src_gpr;
7567 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7568
7569 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
7570 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
7571 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
7572 }
7573
7574 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7575 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
7576 tex.inst_mod = texture_component_select;
7577
7578 if (ctx->bc->chip_class == CAYMAN) {
7579 /* GATHER4 result order is different from TGSI TG4 */
7580 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
7581 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
7582 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
7583 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7584 } else {
7585 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7586 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7587 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7588 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7589 }
7590 }
7591 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
7592 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7593 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7594 tex.dst_sel_z = 7;
7595 tex.dst_sel_w = 7;
7596 }
7597 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7598 tex.dst_sel_x = 3;
7599 tex.dst_sel_y = 7;
7600 tex.dst_sel_z = 7;
7601 tex.dst_sel_w = 7;
7602 }
7603 else {
7604 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7605 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7606 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7607 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7608 }
7609
7610
7611 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7612 tex.src_sel_x = 4;
7613 tex.src_sel_y = 4;
7614 tex.src_sel_z = 4;
7615 tex.src_sel_w = 4;
7616 } else if (src_loaded) {
7617 tex.src_sel_x = 0;
7618 tex.src_sel_y = 1;
7619 tex.src_sel_z = 2;
7620 tex.src_sel_w = 3;
7621 } else {
7622 tex.src_sel_x = ctx->src[0].swizzle[0];
7623 tex.src_sel_y = ctx->src[0].swizzle[1];
7624 tex.src_sel_z = ctx->src[0].swizzle[2];
7625 tex.src_sel_w = ctx->src[0].swizzle[3];
7626 tex.src_rel = ctx->src[0].rel;
7627 }
7628
7629 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7630 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7631 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7632 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7633 tex.src_sel_x = 1;
7634 tex.src_sel_y = 0;
7635 tex.src_sel_z = 3;
7636 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
7637 }
7638
7639 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
7640 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
7641 tex.coord_type_x = 1;
7642 tex.coord_type_y = 1;
7643 }
7644 tex.coord_type_z = 1;
7645 tex.coord_type_w = 1;
7646
7647 tex.offset_x = offset_x;
7648 tex.offset_y = offset_y;
7649 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
7650 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7651 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
7652 tex.offset_z = 0;
7653 }
7654 else {
7655 tex.offset_z = offset_z;
7656 }
7657
7658 /* Put the depth for comparison in W.
7659 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7660 * Some instructions expect the depth in Z. */
7661 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7662 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7663 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7664 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
7665 opcode != FETCH_OP_SAMPLE_C_L &&
7666 opcode != FETCH_OP_SAMPLE_C_LB) {
7667 tex.src_sel_w = tex.src_sel_z;
7668 }
7669
7670 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
7671 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
7672 if (opcode == FETCH_OP_SAMPLE_C_L ||
7673 opcode == FETCH_OP_SAMPLE_C_LB) {
7674 /* the array index is read from Y */
7675 tex.coord_type_y = 0;
7676 } else {
7677 /* the array index is read from Z */
7678 tex.coord_type_z = 0;
7679 tex.src_sel_z = tex.src_sel_y;
7680 }
7681 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7682 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7683 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7684 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7685 (ctx->bc->chip_class >= EVERGREEN)))
7686 /* the array index is read from Z */
7687 tex.coord_type_z = 0;
7688
7689 /* mask unused source components */
7690 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
7691 switch (inst->Texture.Texture) {
7692 case TGSI_TEXTURE_2D:
7693 case TGSI_TEXTURE_RECT:
7694 tex.src_sel_z = 7;
7695 tex.src_sel_w = 7;
7696 break;
7697 case TGSI_TEXTURE_1D_ARRAY:
7698 tex.src_sel_y = 7;
7699 tex.src_sel_w = 7;
7700 break;
7701 case TGSI_TEXTURE_1D:
7702 tex.src_sel_y = 7;
7703 tex.src_sel_z = 7;
7704 tex.src_sel_w = 7;
7705 break;
7706 }
7707 }
7708
7709 r = r600_bytecode_add_tex(ctx->bc, &tex);
7710 if (r)
7711 return r;
7712
7713 /* add shadow ambient support - gallium doesn't do it yet */
7714 return 0;
7715 }
7716
7717 static int find_hw_atomic_counter(struct r600_shader_ctx *ctx,
7718 struct tgsi_full_src_register *src)
7719 {
7720 int i;
7721
7722 if (src->Register.Indirect) {
7723 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7724 if (src->Indirect.ArrayID == ctx->shader->atomics[i].array_id)
7725 return ctx->shader->atomics[i].hw_idx;
7726 }
7727 } else {
7728 uint32_t index = src->Register.Index;
7729 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7730 if (ctx->shader->atomics[i].buffer_id != src->Dimension.Index)
7731 continue;
7732 if (index > ctx->shader->atomics[i].end)
7733 continue;
7734 if (index < ctx->shader->atomics[i].start)
7735 continue;
7736 uint32_t offset = (index - ctx->shader->atomics[i].start);
7737 return ctx->shader->atomics[i].hw_idx + offset;
7738 }
7739 }
7740 assert(0);
7741 return -1;
7742 }
7743
7744
7745 static int tgsi_load_gds(struct r600_shader_ctx *ctx)
7746 {
7747 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7748 int r;
7749 struct r600_bytecode_gds gds;
7750 int uav_id = 0;
7751 int uav_index_mode = 0;
7752
7753 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
7754
7755 if (inst->Src[0].Register.Indirect)
7756 uav_index_mode = 2;
7757
7758 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
7759 gds.op = FETCH_OP_GDS_READ_RET;
7760 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7761 gds.uav_id = uav_id;
7762 gds.uav_index_mode = uav_index_mode;
7763 gds.src_gpr = ctx->temp_reg;
7764 gds.src_sel_x = 4;
7765 gds.src_sel_y = 4;
7766 gds.src_sel_z = 4;
7767 gds.dst_sel_x = 0;
7768 gds.dst_sel_y = 7;
7769 gds.dst_sel_z = 7;
7770 gds.dst_sel_w = 7;
7771 gds.src_gpr2 = ctx->temp_reg;
7772 gds.alloc_consume = 1;
7773 r = r600_bytecode_add_gds(ctx->bc, &gds);
7774 if (r)
7775 return r;
7776
7777 ctx->bc->cf_last->vpm = 1;
7778 return 0;
7779 }
7780
7781 /* this fixes up 1D arrays properly */
7782 static int load_index_src(struct r600_shader_ctx *ctx, int src_index, int *idx_gpr)
7783 {
7784 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7785 int r, i;
7786 struct r600_bytecode_alu alu;
7787 int temp_reg = r600_get_temp(ctx);
7788
7789 for (i = 0; i < 4; i++) {
7790 bool def_val = true, write_zero = false;
7791 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7792 alu.op = ALU_OP1_MOV;
7793 alu.dst.sel = temp_reg;
7794 alu.dst.chan = i;
7795
7796 switch (inst->Memory.Texture) {
7797 case TGSI_TEXTURE_BUFFER:
7798 case TGSI_TEXTURE_1D:
7799 if (i == 1 || i == 2 || i == 3) {
7800 write_zero = true;
7801 }
7802 break;
7803 case TGSI_TEXTURE_1D_ARRAY:
7804 if (i == 1 || i == 3)
7805 write_zero = true;
7806 else if (i == 2) {
7807 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], 1);
7808 def_val = false;
7809 }
7810 break;
7811 case TGSI_TEXTURE_2D:
7812 if (i == 2 || i == 3)
7813 write_zero = true;
7814 break;
7815 default:
7816 if (i == 3)
7817 write_zero = true;
7818 break;
7819 }
7820
7821 if (write_zero) {
7822 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
7823 alu.src[0].value = 0;
7824 } else if (def_val) {
7825 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], i);
7826 }
7827
7828 if (i == 3)
7829 alu.last = 1;
7830 alu.dst.write = 1;
7831 r = r600_bytecode_add_alu(ctx->bc, &alu);
7832 if (r)
7833 return r;
7834 }
7835 *idx_gpr = temp_reg;
7836 return 0;
7837 }
7838
7839 static int tgsi_load_rat(struct r600_shader_ctx *ctx)
7840 {
7841 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7842 /* have to work out the offset into the RAT immediate return buffer */
7843 struct r600_bytecode_vtx vtx;
7844 struct r600_bytecode_cf *cf;
7845 int r;
7846 int idx_gpr;
7847 unsigned format, num_format, format_comp, endian;
7848 const struct util_format_description *desc;
7849 unsigned rat_index_mode;
7850 unsigned immed_base;
7851
7852 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7853
7854 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
7855 r = load_index_src(ctx, 1, &idx_gpr);
7856 if (r)
7857 return r;
7858
7859 if (rat_index_mode)
7860 egcm_load_index_reg(ctx->bc, 1, false);
7861
7862 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
7863 cf = ctx->bc->cf_last;
7864
7865 cf->rat.id = ctx->shader->rat_base + inst->Src[0].Register.Index;
7866 cf->rat.inst = V_RAT_INST_NOP_RTN;
7867 cf->rat.index_mode = rat_index_mode;
7868 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
7869 cf->output.gpr = ctx->thread_id_gpr;
7870 cf->output.index_gpr = idx_gpr;
7871 cf->output.comp_mask = 0xf;
7872 cf->output.burst_count = 1;
7873 cf->vpm = 1;
7874 cf->barrier = 1;
7875 cf->mark = 1;
7876 cf->output.elem_size = 0;
7877
7878 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
7879 cf = ctx->bc->cf_last;
7880 cf->barrier = 1;
7881
7882 desc = util_format_description(inst->Memory.Format);
7883 r600_vertex_data_type(inst->Memory.Format,
7884 &format, &num_format, &format_comp, &endian);
7885 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
7886 vtx.op = FETCH_OP_VFETCH;
7887 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
7888 vtx.buffer_index_mode = rat_index_mode;
7889 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
7890 vtx.src_gpr = ctx->thread_id_gpr;
7891 vtx.src_sel_x = 1;
7892 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7893 vtx.dst_sel_x = desc->swizzle[0];
7894 vtx.dst_sel_y = desc->swizzle[1];
7895 vtx.dst_sel_z = desc->swizzle[2];
7896 vtx.dst_sel_w = desc->swizzle[3];
7897 vtx.srf_mode_all = 1;
7898 vtx.data_format = format;
7899 vtx.num_format_all = num_format;
7900 vtx.format_comp_all = format_comp;
7901 vtx.endian = endian;
7902 vtx.offset = 0;
7903 vtx.mega_fetch_count = 3;
7904 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
7905 if (r)
7906 return r;
7907 cf = ctx->bc->cf_last;
7908 cf->barrier = 1;
7909 return 0;
7910 }
7911
7912 static int tgsi_load(struct r600_shader_ctx *ctx)
7913 {
7914 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7915 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
7916 return tgsi_load_rat(ctx);
7917 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
7918 return tgsi_load_gds(ctx);
7919 return 0;
7920 }
7921
7922 static int tgsi_store_rat(struct r600_shader_ctx *ctx)
7923 {
7924 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7925 struct r600_bytecode_cf *cf;
7926 bool src_requires_loading = false;
7927 int val_gpr, idx_gpr;
7928 int r, i;
7929 unsigned rat_index_mode;
7930
7931 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7932
7933 r = load_index_src(ctx, 0, &idx_gpr);
7934 if (r)
7935 return r;
7936
7937 if (inst->Src[1].Register.File != TGSI_FILE_TEMPORARY)
7938 src_requires_loading = true;
7939
7940 if (src_requires_loading) {
7941 struct r600_bytecode_alu alu;
7942 for (i = 0; i < 4; i++) {
7943 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7944 alu.op = ALU_OP1_MOV;
7945 alu.dst.sel = ctx->temp_reg;
7946 alu.dst.chan = i;
7947
7948 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
7949 if (i == 3)
7950 alu.last = 1;
7951 alu.dst.write = 1;
7952 r = r600_bytecode_add_alu(ctx->bc, &alu);
7953 if (r)
7954 return r;
7955 }
7956 val_gpr = ctx->temp_reg;
7957 } else
7958 val_gpr = tgsi_tex_get_src_gpr(ctx, 1);
7959 if (rat_index_mode)
7960 egcm_load_index_reg(ctx->bc, 1, false);
7961
7962 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
7963 cf = ctx->bc->cf_last;
7964
7965 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index;
7966 cf->rat.inst = V_RAT_INST_STORE_TYPED;
7967 cf->rat.index_mode = rat_index_mode;
7968 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
7969 cf->output.gpr = val_gpr;
7970 cf->output.index_gpr = idx_gpr;
7971 cf->output.comp_mask = 0xf;
7972 cf->output.burst_count = 1;
7973 cf->vpm = 1;
7974 cf->barrier = 1;
7975 cf->output.elem_size = 0;
7976 return 0;
7977 }
7978
7979 static int tgsi_store(struct r600_shader_ctx *ctx)
7980 {
7981 return tgsi_store_rat(ctx);
7982 }
7983
7984 static int tgsi_atomic_op_rat(struct r600_shader_ctx *ctx)
7985 {
7986 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7987 /* have to work out the offset into the RAT immediate return buffer */
7988 struct r600_bytecode_alu alu;
7989 struct r600_bytecode_vtx vtx;
7990 struct r600_bytecode_cf *cf;
7991 int r;
7992 int idx_gpr;
7993 unsigned format, num_format, format_comp, endian;
7994 const struct util_format_description *desc;
7995 unsigned rat_index_mode;
7996 unsigned immed_base;
7997
7998 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
7999
8000 assert (inst->Src[0].Register.File == TGSI_FILE_IMAGE);
8001 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8002
8003 r = load_index_src(ctx, 1, &idx_gpr);
8004 if (r)
8005 return r;
8006
8007 if (ctx->inst_info->op == V_RAT_INST_CMPXCHG_INT_RTN) {
8008 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8009 alu.op = ALU_OP1_MOV;
8010 alu.dst.sel = ctx->thread_id_gpr;
8011 alu.dst.chan = 0;
8012 alu.dst.write = 1;
8013 r600_bytecode_src(&alu.src[0], &ctx->src[3], 0);
8014 alu.last = 1;
8015 r = r600_bytecode_add_alu(ctx->bc, &alu);
8016 if (r)
8017 return r;
8018
8019 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8020 alu.op = ALU_OP1_MOV;
8021 alu.dst.sel = ctx->thread_id_gpr;
8022 alu.dst.chan = 3;
8023 alu.dst.write = 1;
8024 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8025 alu.last = 1;
8026 r = r600_bytecode_add_alu(ctx->bc, &alu);
8027 if (r)
8028 return r;
8029 } else {
8030 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8031 alu.op = ALU_OP1_MOV;
8032 alu.dst.sel = ctx->thread_id_gpr;
8033 alu.dst.chan = 0;
8034 alu.dst.write = 1;
8035 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8036 alu.last = 1;
8037 r = r600_bytecode_add_alu(ctx->bc, &alu);
8038 if (r)
8039 return r;
8040 }
8041
8042 if (rat_index_mode)
8043 egcm_load_index_reg(ctx->bc, 1, false);
8044 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8045 cf = ctx->bc->cf_last;
8046
8047 cf->rat.id = ctx->shader->rat_base + inst->Src[0].Register.Index;
8048 cf->rat.inst = ctx->inst_info->op;
8049 cf->rat.index_mode = rat_index_mode;
8050 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
8051 cf->output.gpr = ctx->thread_id_gpr;
8052 cf->output.index_gpr = idx_gpr;
8053 cf->output.comp_mask = 0xf;
8054 cf->output.burst_count = 1;
8055 cf->vpm = 1;
8056 cf->barrier = 1;
8057 cf->mark = 1;
8058 cf->output.elem_size = 0;
8059 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
8060 cf = ctx->bc->cf_last;
8061 cf->barrier = 1;
8062 cf->cf_addr = 1;
8063
8064 desc = util_format_description(inst->Memory.Format);
8065 r600_vertex_data_type(inst->Memory.Format,
8066 &format, &num_format, &format_comp, &endian);
8067 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8068 vtx.op = FETCH_OP_VFETCH;
8069 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
8070 vtx.buffer_index_mode = rat_index_mode;
8071 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8072 vtx.src_gpr = ctx->thread_id_gpr;
8073 vtx.src_sel_x = 1;
8074 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8075 vtx.dst_sel_x = desc->swizzle[0];
8076 vtx.dst_sel_y = 7;
8077 vtx.dst_sel_z = 7;
8078 vtx.dst_sel_w = 7;
8079 vtx.use_const_fields = 0;
8080 vtx.srf_mode_all = 1;
8081 vtx.data_format = format;
8082 vtx.num_format_all = num_format;
8083 vtx.format_comp_all = format_comp;
8084 vtx.endian = endian;
8085 vtx.offset = 0;
8086 vtx.mega_fetch_count = 0xf;
8087 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8088 if (r)
8089 return r;
8090 cf = ctx->bc->cf_last;
8091 cf->vpm = 1;
8092 cf->barrier = 1;
8093 return 0;
8094 }
8095
8096 static int get_gds_op(int opcode)
8097 {
8098 switch (opcode) {
8099 case TGSI_OPCODE_ATOMUADD:
8100 return FETCH_OP_GDS_ADD_RET;
8101 case TGSI_OPCODE_ATOMAND:
8102 return FETCH_OP_GDS_AND_RET;
8103 case TGSI_OPCODE_ATOMOR:
8104 return FETCH_OP_GDS_OR_RET;
8105 case TGSI_OPCODE_ATOMXOR:
8106 return FETCH_OP_GDS_XOR_RET;
8107 case TGSI_OPCODE_ATOMUMIN:
8108 return FETCH_OP_GDS_MIN_UINT_RET;
8109 case TGSI_OPCODE_ATOMUMAX:
8110 return FETCH_OP_GDS_MAX_UINT_RET;
8111 case TGSI_OPCODE_ATOMXCHG:
8112 return FETCH_OP_GDS_XCHG_RET;
8113 case TGSI_OPCODE_ATOMCAS:
8114 return FETCH_OP_GDS_CMP_XCHG_RET;
8115 default:
8116 return -1;
8117 }
8118 }
8119
8120 static int tgsi_atomic_op_gds(struct r600_shader_ctx *ctx)
8121 {
8122 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8123 struct r600_bytecode_gds gds;
8124 struct r600_bytecode_alu alu;
8125 int gds_op = get_gds_op(inst->Instruction.Opcode);
8126 int r;
8127 int uav_id = 0;
8128 int uav_index_mode = 0;
8129
8130 if (gds_op == -1) {
8131 fprintf(stderr, "unknown GDS op for opcode %d\n", inst->Instruction.Opcode);
8132 return -1;
8133 }
8134
8135 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
8136
8137 if (inst->Src[0].Register.Indirect)
8138 uav_index_mode = 2;
8139
8140 if (inst->Src[2].Register.File == TGSI_FILE_IMMEDIATE) {
8141 int value = (ctx->literals[4 * inst->Src[2].Register.Index + inst->Src[2].Register.SwizzleX]);
8142 int abs_value = abs(value);
8143 if (abs_value != value && gds_op == FETCH_OP_GDS_ADD_RET)
8144 gds_op = FETCH_OP_GDS_SUB_RET;
8145 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8146 alu.op = ALU_OP1_MOV;
8147 alu.dst.sel = ctx->temp_reg;
8148 alu.dst.chan = 0;
8149 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
8150 alu.src[0].value = abs_value;
8151 alu.last = 1;
8152 alu.dst.write = 1;
8153 r = r600_bytecode_add_alu(ctx->bc, &alu);
8154 if (r)
8155 return r;
8156 } else {
8157 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8158 alu.op = ALU_OP1_MOV;
8159 alu.dst.sel = ctx->temp_reg;
8160 alu.dst.chan = 0;
8161 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8162 alu.last = 1;
8163 alu.dst.write = 1;
8164 r = r600_bytecode_add_alu(ctx->bc, &alu);
8165 if (r)
8166 return r;
8167 }
8168
8169 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
8170 gds.op = gds_op;
8171 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8172 gds.uav_id = uav_id;
8173 gds.uav_index_mode = uav_index_mode;
8174 gds.src_gpr = ctx->temp_reg;
8175 gds.src_gpr2 = ctx->temp_reg;
8176 gds.src_sel_x = 4;
8177 gds.src_sel_y = 0;
8178 gds.src_sel_z = 4;
8179 gds.dst_sel_x = 0;
8180 gds.dst_sel_y = 7;
8181 gds.dst_sel_z = 7;
8182 gds.dst_sel_w = 7;
8183 gds.alloc_consume = 1;
8184 r = r600_bytecode_add_gds(ctx->bc, &gds);
8185 if (r)
8186 return r;
8187 ctx->bc->cf_last->vpm = 1;
8188 return 0;
8189 }
8190
8191 static int tgsi_atomic_op(struct r600_shader_ctx *ctx)
8192 {
8193 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8194 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
8195 return tgsi_atomic_op_rat(ctx);
8196 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
8197 return tgsi_atomic_op_gds(ctx);
8198 return 0;
8199 }
8200
8201 static int tgsi_lrp(struct r600_shader_ctx *ctx)
8202 {
8203 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8204 struct r600_bytecode_alu alu;
8205 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8206 unsigned i, temp_regs[2];
8207 int r;
8208
8209 /* optimize if it's just an equal balance */
8210 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
8211 for (i = 0; i < lasti + 1; i++) {
8212 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8213 continue;
8214
8215 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8216 alu.op = ALU_OP2_ADD;
8217 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8218 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8219 alu.omod = 3;
8220 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8221 alu.dst.chan = i;
8222 if (i == lasti) {
8223 alu.last = 1;
8224 }
8225 r = r600_bytecode_add_alu(ctx->bc, &alu);
8226 if (r)
8227 return r;
8228 }
8229 return 0;
8230 }
8231
8232 /* 1 - src0 */
8233 for (i = 0; i < lasti + 1; i++) {
8234 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8235 continue;
8236
8237 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8238 alu.op = ALU_OP2_ADD;
8239 alu.src[0].sel = V_SQ_ALU_SRC_1;
8240 alu.src[0].chan = 0;
8241 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
8242 r600_bytecode_src_toggle_neg(&alu.src[1]);
8243 alu.dst.sel = ctx->temp_reg;
8244 alu.dst.chan = i;
8245 if (i == lasti) {
8246 alu.last = 1;
8247 }
8248 alu.dst.write = 1;
8249 r = r600_bytecode_add_alu(ctx->bc, &alu);
8250 if (r)
8251 return r;
8252 }
8253
8254 /* (1 - src0) * src2 */
8255 for (i = 0; i < lasti + 1; i++) {
8256 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8257 continue;
8258
8259 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8260 alu.op = ALU_OP2_MUL;
8261 alu.src[0].sel = ctx->temp_reg;
8262 alu.src[0].chan = i;
8263 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8264 alu.dst.sel = ctx->temp_reg;
8265 alu.dst.chan = i;
8266 if (i == lasti) {
8267 alu.last = 1;
8268 }
8269 alu.dst.write = 1;
8270 r = r600_bytecode_add_alu(ctx->bc, &alu);
8271 if (r)
8272 return r;
8273 }
8274
8275 /* src0 * src1 + (1 - src0) * src2 */
8276 if (ctx->src[0].abs)
8277 temp_regs[0] = r600_get_temp(ctx);
8278 else
8279 temp_regs[0] = 0;
8280 if (ctx->src[1].abs)
8281 temp_regs[1] = r600_get_temp(ctx);
8282 else
8283 temp_regs[1] = 0;
8284
8285 for (i = 0; i < lasti + 1; i++) {
8286 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8287 continue;
8288
8289 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8290 alu.op = ALU_OP3_MULADD;
8291 alu.is_op3 = 1;
8292 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
8293 if (r)
8294 return r;
8295 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
8296 if (r)
8297 return r;
8298 alu.src[2].sel = ctx->temp_reg;
8299 alu.src[2].chan = i;
8300
8301 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8302 alu.dst.chan = i;
8303 if (i == lasti) {
8304 alu.last = 1;
8305 }
8306 r = r600_bytecode_add_alu(ctx->bc, &alu);
8307 if (r)
8308 return r;
8309 }
8310 return 0;
8311 }
8312
8313 static int tgsi_cmp(struct r600_shader_ctx *ctx)
8314 {
8315 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8316 struct r600_bytecode_alu alu;
8317 int i, r, j;
8318 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8319 int temp_regs[3];
8320 unsigned op;
8321
8322 if (ctx->src[0].abs && ctx->src[0].neg) {
8323 op = ALU_OP3_CNDE;
8324 ctx->src[0].abs = 0;
8325 ctx->src[0].neg = 0;
8326 } else {
8327 op = ALU_OP3_CNDGE;
8328 }
8329
8330 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
8331 temp_regs[j] = 0;
8332 if (ctx->src[j].abs)
8333 temp_regs[j] = r600_get_temp(ctx);
8334 }
8335
8336 for (i = 0; i < lasti + 1; i++) {
8337 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8338 continue;
8339
8340 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8341 alu.op = op;
8342 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
8343 if (r)
8344 return r;
8345 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
8346 if (r)
8347 return r;
8348 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
8349 if (r)
8350 return r;
8351 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8352 alu.dst.chan = i;
8353 alu.dst.write = 1;
8354 alu.is_op3 = 1;
8355 if (i == lasti)
8356 alu.last = 1;
8357 r = r600_bytecode_add_alu(ctx->bc, &alu);
8358 if (r)
8359 return r;
8360 }
8361 return 0;
8362 }
8363
8364 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
8365 {
8366 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8367 struct r600_bytecode_alu alu;
8368 int i, r;
8369 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8370
8371 for (i = 0; i < lasti + 1; i++) {
8372 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8373 continue;
8374
8375 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8376 alu.op = ALU_OP3_CNDE_INT;
8377 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8378 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8379 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
8380 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8381 alu.dst.chan = i;
8382 alu.dst.write = 1;
8383 alu.is_op3 = 1;
8384 if (i == lasti)
8385 alu.last = 1;
8386 r = r600_bytecode_add_alu(ctx->bc, &alu);
8387 if (r)
8388 return r;
8389 }
8390 return 0;
8391 }
8392
8393 static int tgsi_exp(struct r600_shader_ctx *ctx)
8394 {
8395 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8396 struct r600_bytecode_alu alu;
8397 int r;
8398 unsigned i;
8399
8400 /* result.x = 2^floor(src); */
8401 if (inst->Dst[0].Register.WriteMask & 1) {
8402 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8403
8404 alu.op = ALU_OP1_FLOOR;
8405 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8406
8407 alu.dst.sel = ctx->temp_reg;
8408 alu.dst.chan = 0;
8409 alu.dst.write = 1;
8410 alu.last = 1;
8411 r = r600_bytecode_add_alu(ctx->bc, &alu);
8412 if (r)
8413 return r;
8414
8415 if (ctx->bc->chip_class == CAYMAN) {
8416 for (i = 0; i < 3; i++) {
8417 alu.op = ALU_OP1_EXP_IEEE;
8418 alu.src[0].sel = ctx->temp_reg;
8419 alu.src[0].chan = 0;
8420
8421 alu.dst.sel = ctx->temp_reg;
8422 alu.dst.chan = i;
8423 alu.dst.write = i == 0;
8424 alu.last = i == 2;
8425 r = r600_bytecode_add_alu(ctx->bc, &alu);
8426 if (r)
8427 return r;
8428 }
8429 } else {
8430 alu.op = ALU_OP1_EXP_IEEE;
8431 alu.src[0].sel = ctx->temp_reg;
8432 alu.src[0].chan = 0;
8433
8434 alu.dst.sel = ctx->temp_reg;
8435 alu.dst.chan = 0;
8436 alu.dst.write = 1;
8437 alu.last = 1;
8438 r = r600_bytecode_add_alu(ctx->bc, &alu);
8439 if (r)
8440 return r;
8441 }
8442 }
8443
8444 /* result.y = tmp - floor(tmp); */
8445 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8446 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8447
8448 alu.op = ALU_OP1_FRACT;
8449 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8450
8451 alu.dst.sel = ctx->temp_reg;
8452 #if 0
8453 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8454 if (r)
8455 return r;
8456 #endif
8457 alu.dst.write = 1;
8458 alu.dst.chan = 1;
8459
8460 alu.last = 1;
8461
8462 r = r600_bytecode_add_alu(ctx->bc, &alu);
8463 if (r)
8464 return r;
8465 }
8466
8467 /* result.z = RoughApprox2ToX(tmp);*/
8468 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
8469 if (ctx->bc->chip_class == CAYMAN) {
8470 for (i = 0; i < 3; i++) {
8471 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8472 alu.op = ALU_OP1_EXP_IEEE;
8473 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8474
8475 alu.dst.sel = ctx->temp_reg;
8476 alu.dst.chan = i;
8477 if (i == 2) {
8478 alu.dst.write = 1;
8479 alu.last = 1;
8480 }
8481
8482 r = r600_bytecode_add_alu(ctx->bc, &alu);
8483 if (r)
8484 return r;
8485 }
8486 } else {
8487 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8488 alu.op = ALU_OP1_EXP_IEEE;
8489 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8490
8491 alu.dst.sel = ctx->temp_reg;
8492 alu.dst.write = 1;
8493 alu.dst.chan = 2;
8494
8495 alu.last = 1;
8496
8497 r = r600_bytecode_add_alu(ctx->bc, &alu);
8498 if (r)
8499 return r;
8500 }
8501 }
8502
8503 /* result.w = 1.0;*/
8504 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
8505 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8506
8507 alu.op = ALU_OP1_MOV;
8508 alu.src[0].sel = V_SQ_ALU_SRC_1;
8509 alu.src[0].chan = 0;
8510
8511 alu.dst.sel = ctx->temp_reg;
8512 alu.dst.chan = 3;
8513 alu.dst.write = 1;
8514 alu.last = 1;
8515 r = r600_bytecode_add_alu(ctx->bc, &alu);
8516 if (r)
8517 return r;
8518 }
8519 return tgsi_helper_copy(ctx, inst);
8520 }
8521
8522 static int tgsi_log(struct r600_shader_ctx *ctx)
8523 {
8524 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8525 struct r600_bytecode_alu alu;
8526 int r;
8527 unsigned i;
8528
8529 /* result.x = floor(log2(|src|)); */
8530 if (inst->Dst[0].Register.WriteMask & 1) {
8531 if (ctx->bc->chip_class == CAYMAN) {
8532 for (i = 0; i < 3; i++) {
8533 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8534
8535 alu.op = ALU_OP1_LOG_IEEE;
8536 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8537 r600_bytecode_src_set_abs(&alu.src[0]);
8538
8539 alu.dst.sel = ctx->temp_reg;
8540 alu.dst.chan = i;
8541 if (i == 0)
8542 alu.dst.write = 1;
8543 if (i == 2)
8544 alu.last = 1;
8545 r = r600_bytecode_add_alu(ctx->bc, &alu);
8546 if (r)
8547 return r;
8548 }
8549
8550 } else {
8551 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8552
8553 alu.op = ALU_OP1_LOG_IEEE;
8554 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8555 r600_bytecode_src_set_abs(&alu.src[0]);
8556
8557 alu.dst.sel = ctx->temp_reg;
8558 alu.dst.chan = 0;
8559 alu.dst.write = 1;
8560 alu.last = 1;
8561 r = r600_bytecode_add_alu(ctx->bc, &alu);
8562 if (r)
8563 return r;
8564 }
8565
8566 alu.op = ALU_OP1_FLOOR;
8567 alu.src[0].sel = ctx->temp_reg;
8568 alu.src[0].chan = 0;
8569
8570 alu.dst.sel = ctx->temp_reg;
8571 alu.dst.chan = 0;
8572 alu.dst.write = 1;
8573 alu.last = 1;
8574
8575 r = r600_bytecode_add_alu(ctx->bc, &alu);
8576 if (r)
8577 return r;
8578 }
8579
8580 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
8581 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8582
8583 if (ctx->bc->chip_class == CAYMAN) {
8584 for (i = 0; i < 3; i++) {
8585 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8586
8587 alu.op = ALU_OP1_LOG_IEEE;
8588 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8589 r600_bytecode_src_set_abs(&alu.src[0]);
8590
8591 alu.dst.sel = ctx->temp_reg;
8592 alu.dst.chan = i;
8593 if (i == 1)
8594 alu.dst.write = 1;
8595 if (i == 2)
8596 alu.last = 1;
8597
8598 r = r600_bytecode_add_alu(ctx->bc, &alu);
8599 if (r)
8600 return r;
8601 }
8602 } else {
8603 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8604
8605 alu.op = ALU_OP1_LOG_IEEE;
8606 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8607 r600_bytecode_src_set_abs(&alu.src[0]);
8608
8609 alu.dst.sel = ctx->temp_reg;
8610 alu.dst.chan = 1;
8611 alu.dst.write = 1;
8612 alu.last = 1;
8613
8614 r = r600_bytecode_add_alu(ctx->bc, &alu);
8615 if (r)
8616 return r;
8617 }
8618
8619 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8620
8621 alu.op = ALU_OP1_FLOOR;
8622 alu.src[0].sel = ctx->temp_reg;
8623 alu.src[0].chan = 1;
8624
8625 alu.dst.sel = ctx->temp_reg;
8626 alu.dst.chan = 1;
8627 alu.dst.write = 1;
8628 alu.last = 1;
8629
8630 r = r600_bytecode_add_alu(ctx->bc, &alu);
8631 if (r)
8632 return r;
8633
8634 if (ctx->bc->chip_class == CAYMAN) {
8635 for (i = 0; i < 3; i++) {
8636 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8637 alu.op = ALU_OP1_EXP_IEEE;
8638 alu.src[0].sel = ctx->temp_reg;
8639 alu.src[0].chan = 1;
8640
8641 alu.dst.sel = ctx->temp_reg;
8642 alu.dst.chan = i;
8643 if (i == 1)
8644 alu.dst.write = 1;
8645 if (i == 2)
8646 alu.last = 1;
8647
8648 r = r600_bytecode_add_alu(ctx->bc, &alu);
8649 if (r)
8650 return r;
8651 }
8652 } else {
8653 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8654 alu.op = ALU_OP1_EXP_IEEE;
8655 alu.src[0].sel = ctx->temp_reg;
8656 alu.src[0].chan = 1;
8657
8658 alu.dst.sel = ctx->temp_reg;
8659 alu.dst.chan = 1;
8660 alu.dst.write = 1;
8661 alu.last = 1;
8662
8663 r = r600_bytecode_add_alu(ctx->bc, &alu);
8664 if (r)
8665 return r;
8666 }
8667
8668 if (ctx->bc->chip_class == CAYMAN) {
8669 for (i = 0; i < 3; i++) {
8670 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8671 alu.op = ALU_OP1_RECIP_IEEE;
8672 alu.src[0].sel = ctx->temp_reg;
8673 alu.src[0].chan = 1;
8674
8675 alu.dst.sel = ctx->temp_reg;
8676 alu.dst.chan = i;
8677 if (i == 1)
8678 alu.dst.write = 1;
8679 if (i == 2)
8680 alu.last = 1;
8681
8682 r = r600_bytecode_add_alu(ctx->bc, &alu);
8683 if (r)
8684 return r;
8685 }
8686 } else {
8687 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8688 alu.op = ALU_OP1_RECIP_IEEE;
8689 alu.src[0].sel = ctx->temp_reg;
8690 alu.src[0].chan = 1;
8691
8692 alu.dst.sel = ctx->temp_reg;
8693 alu.dst.chan = 1;
8694 alu.dst.write = 1;
8695 alu.last = 1;
8696
8697 r = r600_bytecode_add_alu(ctx->bc, &alu);
8698 if (r)
8699 return r;
8700 }
8701
8702 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8703
8704 alu.op = ALU_OP2_MUL;
8705
8706 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8707 r600_bytecode_src_set_abs(&alu.src[0]);
8708
8709 alu.src[1].sel = ctx->temp_reg;
8710 alu.src[1].chan = 1;
8711
8712 alu.dst.sel = ctx->temp_reg;
8713 alu.dst.chan = 1;
8714 alu.dst.write = 1;
8715 alu.last = 1;
8716
8717 r = r600_bytecode_add_alu(ctx->bc, &alu);
8718 if (r)
8719 return r;
8720 }
8721
8722 /* result.z = log2(|src|);*/
8723 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
8724 if (ctx->bc->chip_class == CAYMAN) {
8725 for (i = 0; i < 3; i++) {
8726 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8727
8728 alu.op = ALU_OP1_LOG_IEEE;
8729 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8730 r600_bytecode_src_set_abs(&alu.src[0]);
8731
8732 alu.dst.sel = ctx->temp_reg;
8733 if (i == 2)
8734 alu.dst.write = 1;
8735 alu.dst.chan = i;
8736 if (i == 2)
8737 alu.last = 1;
8738
8739 r = r600_bytecode_add_alu(ctx->bc, &alu);
8740 if (r)
8741 return r;
8742 }
8743 } else {
8744 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8745
8746 alu.op = ALU_OP1_LOG_IEEE;
8747 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8748 r600_bytecode_src_set_abs(&alu.src[0]);
8749
8750 alu.dst.sel = ctx->temp_reg;
8751 alu.dst.write = 1;
8752 alu.dst.chan = 2;
8753 alu.last = 1;
8754
8755 r = r600_bytecode_add_alu(ctx->bc, &alu);
8756 if (r)
8757 return r;
8758 }
8759 }
8760
8761 /* result.w = 1.0; */
8762 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
8763 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8764
8765 alu.op = ALU_OP1_MOV;
8766 alu.src[0].sel = V_SQ_ALU_SRC_1;
8767 alu.src[0].chan = 0;
8768
8769 alu.dst.sel = ctx->temp_reg;
8770 alu.dst.chan = 3;
8771 alu.dst.write = 1;
8772 alu.last = 1;
8773
8774 r = r600_bytecode_add_alu(ctx->bc, &alu);
8775 if (r)
8776 return r;
8777 }
8778
8779 return tgsi_helper_copy(ctx, inst);
8780 }
8781
8782 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
8783 {
8784 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8785 struct r600_bytecode_alu alu;
8786 int r;
8787 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8788 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
8789
8790 assert(inst->Dst[0].Register.Index < 3);
8791 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8792
8793 switch (inst->Instruction.Opcode) {
8794 case TGSI_OPCODE_ARL:
8795 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
8796 break;
8797 case TGSI_OPCODE_ARR:
8798 alu.op = ALU_OP1_FLT_TO_INT;
8799 break;
8800 case TGSI_OPCODE_UARL:
8801 alu.op = ALU_OP1_MOV;
8802 break;
8803 default:
8804 assert(0);
8805 return -1;
8806 }
8807
8808 for (i = 0; i <= lasti; ++i) {
8809 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8810 continue;
8811 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8812 alu.last = i == lasti;
8813 alu.dst.sel = reg;
8814 alu.dst.chan = i;
8815 alu.dst.write = 1;
8816 r = r600_bytecode_add_alu(ctx->bc, &alu);
8817 if (r)
8818 return r;
8819 }
8820
8821 if (inst->Dst[0].Register.Index > 0)
8822 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
8823 else
8824 ctx->bc->ar_loaded = 0;
8825
8826 return 0;
8827 }
8828 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
8829 {
8830 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8831 struct r600_bytecode_alu alu;
8832 int r;
8833 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8834
8835 switch (inst->Instruction.Opcode) {
8836 case TGSI_OPCODE_ARL:
8837 memset(&alu, 0, sizeof(alu));
8838 alu.op = ALU_OP1_FLOOR;
8839 alu.dst.sel = ctx->bc->ar_reg;
8840 alu.dst.write = 1;
8841 for (i = 0; i <= lasti; ++i) {
8842 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8843 alu.dst.chan = i;
8844 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8845 alu.last = i == lasti;
8846 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8847 return r;
8848 }
8849 }
8850
8851 memset(&alu, 0, sizeof(alu));
8852 alu.op = ALU_OP1_FLT_TO_INT;
8853 alu.src[0].sel = ctx->bc->ar_reg;
8854 alu.dst.sel = ctx->bc->ar_reg;
8855 alu.dst.write = 1;
8856 /* FLT_TO_INT is trans-only on r600/r700 */
8857 alu.last = TRUE;
8858 for (i = 0; i <= lasti; ++i) {
8859 alu.dst.chan = i;
8860 alu.src[0].chan = i;
8861 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8862 return r;
8863 }
8864 break;
8865 case TGSI_OPCODE_ARR:
8866 memset(&alu, 0, sizeof(alu));
8867 alu.op = ALU_OP1_FLT_TO_INT;
8868 alu.dst.sel = ctx->bc->ar_reg;
8869 alu.dst.write = 1;
8870 /* FLT_TO_INT is trans-only on r600/r700 */
8871 alu.last = TRUE;
8872 for (i = 0; i <= lasti; ++i) {
8873 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8874 alu.dst.chan = i;
8875 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8876 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8877 return r;
8878 }
8879 }
8880 break;
8881 case TGSI_OPCODE_UARL:
8882 memset(&alu, 0, sizeof(alu));
8883 alu.op = ALU_OP1_MOV;
8884 alu.dst.sel = ctx->bc->ar_reg;
8885 alu.dst.write = 1;
8886 for (i = 0; i <= lasti; ++i) {
8887 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8888 alu.dst.chan = i;
8889 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8890 alu.last = i == lasti;
8891 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8892 return r;
8893 }
8894 }
8895 break;
8896 default:
8897 assert(0);
8898 return -1;
8899 }
8900
8901 ctx->bc->ar_loaded = 0;
8902 return 0;
8903 }
8904
8905 static int tgsi_opdst(struct r600_shader_ctx *ctx)
8906 {
8907 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8908 struct r600_bytecode_alu alu;
8909 int i, r = 0;
8910
8911 for (i = 0; i < 4; i++) {
8912 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8913
8914 alu.op = ALU_OP2_MUL;
8915 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8916
8917 if (i == 0 || i == 3) {
8918 alu.src[0].sel = V_SQ_ALU_SRC_1;
8919 } else {
8920 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8921 }
8922
8923 if (i == 0 || i == 2) {
8924 alu.src[1].sel = V_SQ_ALU_SRC_1;
8925 } else {
8926 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8927 }
8928 if (i == 3)
8929 alu.last = 1;
8930 r = r600_bytecode_add_alu(ctx->bc, &alu);
8931 if (r)
8932 return r;
8933 }
8934 return 0;
8935 }
8936
8937 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
8938 {
8939 struct r600_bytecode_alu alu;
8940 int r;
8941
8942 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8943 alu.op = opcode;
8944 alu.execute_mask = 1;
8945 alu.update_pred = 1;
8946
8947 alu.dst.sel = ctx->temp_reg;
8948 alu.dst.write = 1;
8949 alu.dst.chan = 0;
8950
8951 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8952 alu.src[1].sel = V_SQ_ALU_SRC_0;
8953 alu.src[1].chan = 0;
8954
8955 alu.last = 1;
8956
8957 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
8958 if (r)
8959 return r;
8960 return 0;
8961 }
8962
8963 static int pops(struct r600_shader_ctx *ctx, int pops)
8964 {
8965 unsigned force_pop = ctx->bc->force_add_cf;
8966
8967 if (!force_pop) {
8968 int alu_pop = 3;
8969 if (ctx->bc->cf_last) {
8970 if (ctx->bc->cf_last->op == CF_OP_ALU)
8971 alu_pop = 0;
8972 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
8973 alu_pop = 1;
8974 }
8975 alu_pop += pops;
8976 if (alu_pop == 1) {
8977 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
8978 ctx->bc->force_add_cf = 1;
8979 } else if (alu_pop == 2) {
8980 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
8981 ctx->bc->force_add_cf = 1;
8982 } else {
8983 force_pop = 1;
8984 }
8985 }
8986
8987 if (force_pop) {
8988 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
8989 ctx->bc->cf_last->pop_count = pops;
8990 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8991 }
8992
8993 return 0;
8994 }
8995
8996 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
8997 unsigned reason)
8998 {
8999 struct r600_stack_info *stack = &ctx->bc->stack;
9000 unsigned elements, entries;
9001
9002 unsigned entry_size = stack->entry_size;
9003
9004 elements = (stack->loop + stack->push_wqm ) * entry_size;
9005 elements += stack->push;
9006
9007 switch (ctx->bc->chip_class) {
9008 case R600:
9009 case R700:
9010 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
9011 * the stack must be reserved to hold the current active/continue
9012 * masks */
9013 if (reason == FC_PUSH_VPM) {
9014 elements += 2;
9015 }
9016 break;
9017
9018 case CAYMAN:
9019 /* r9xx: any stack operation on empty stack consumes 2 additional
9020 * elements */
9021 elements += 2;
9022
9023 /* fallthrough */
9024 /* FIXME: do the two elements added above cover the cases for the
9025 * r8xx+ below? */
9026
9027 case EVERGREEN:
9028 /* r8xx+: 2 extra elements are not always required, but one extra
9029 * element must be added for each of the following cases:
9030 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
9031 * stack usage.
9032 * (Currently we don't use ALU_ELSE_AFTER.)
9033 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
9034 * PUSH instruction executed.
9035 *
9036 * NOTE: it seems we also need to reserve additional element in some
9037 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
9038 * then STACK_SIZE should be 2 instead of 1 */
9039 if (reason == FC_PUSH_VPM) {
9040 elements += 1;
9041 }
9042 break;
9043
9044 default:
9045 assert(0);
9046 break;
9047 }
9048
9049 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
9050 * for all chips, so we use 4 in the final formula, not the real entry_size
9051 * for the chip */
9052 entry_size = 4;
9053
9054 entries = (elements + (entry_size - 1)) / entry_size;
9055
9056 if (entries > stack->max_entries)
9057 stack->max_entries = entries;
9058 }
9059
9060 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
9061 {
9062 switch(reason) {
9063 case FC_PUSH_VPM:
9064 --ctx->bc->stack.push;
9065 assert(ctx->bc->stack.push >= 0);
9066 break;
9067 case FC_PUSH_WQM:
9068 --ctx->bc->stack.push_wqm;
9069 assert(ctx->bc->stack.push_wqm >= 0);
9070 break;
9071 case FC_LOOP:
9072 --ctx->bc->stack.loop;
9073 assert(ctx->bc->stack.loop >= 0);
9074 break;
9075 default:
9076 assert(0);
9077 break;
9078 }
9079 }
9080
9081 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
9082 {
9083 switch (reason) {
9084 case FC_PUSH_VPM:
9085 ++ctx->bc->stack.push;
9086 break;
9087 case FC_PUSH_WQM:
9088 ++ctx->bc->stack.push_wqm;
9089 case FC_LOOP:
9090 ++ctx->bc->stack.loop;
9091 break;
9092 default:
9093 assert(0);
9094 }
9095
9096 callstack_update_max_depth(ctx, reason);
9097 }
9098
9099 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
9100 {
9101 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
9102
9103 sp->mid = realloc((void *)sp->mid,
9104 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
9105 sp->mid[sp->num_mid] = ctx->bc->cf_last;
9106 sp->num_mid++;
9107 }
9108
9109 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
9110 {
9111 assert(ctx->bc->fc_sp < ARRAY_SIZE(ctx->bc->fc_stack));
9112 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
9113 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
9114 ctx->bc->fc_sp++;
9115 }
9116
9117 static void fc_poplevel(struct r600_shader_ctx *ctx)
9118 {
9119 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp - 1];
9120 free(sp->mid);
9121 sp->mid = NULL;
9122 sp->num_mid = 0;
9123 sp->start = NULL;
9124 sp->type = 0;
9125 ctx->bc->fc_sp--;
9126 }
9127
9128 #if 0
9129 static int emit_return(struct r600_shader_ctx *ctx)
9130 {
9131 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
9132 return 0;
9133 }
9134
9135 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
9136 {
9137
9138 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
9139 ctx->bc->cf_last->pop_count = pops;
9140 /* XXX work out offset */
9141 return 0;
9142 }
9143
9144 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
9145 {
9146 return 0;
9147 }
9148
9149 static void emit_testflag(struct r600_shader_ctx *ctx)
9150 {
9151
9152 }
9153
9154 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
9155 {
9156 emit_testflag(ctx);
9157 emit_jump_to_offset(ctx, 1, 4);
9158 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
9159 pops(ctx, ifidx + 1);
9160 emit_return(ctx);
9161 }
9162
9163 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
9164 {
9165 emit_testflag(ctx);
9166
9167 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9168 ctx->bc->cf_last->pop_count = 1;
9169
9170 fc_set_mid(ctx, fc_sp);
9171
9172 pops(ctx, 1);
9173 }
9174 #endif
9175
9176 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
9177 {
9178 int alu_type = CF_OP_ALU_PUSH_BEFORE;
9179
9180 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
9181 * LOOP_STARTxxx for nested loops may put the branch stack into a state
9182 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
9183 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
9184 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
9185 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
9186 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
9187 alu_type = CF_OP_ALU;
9188 }
9189
9190 emit_logic_pred(ctx, opcode, alu_type);
9191
9192 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
9193
9194 fc_pushlevel(ctx, FC_IF);
9195
9196 callstack_push(ctx, FC_PUSH_VPM);
9197 return 0;
9198 }
9199
9200 static int tgsi_if(struct r600_shader_ctx *ctx)
9201 {
9202 return emit_if(ctx, ALU_OP2_PRED_SETNE);
9203 }
9204
9205 static int tgsi_uif(struct r600_shader_ctx *ctx)
9206 {
9207 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
9208 }
9209
9210 static int tgsi_else(struct r600_shader_ctx *ctx)
9211 {
9212 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
9213 ctx->bc->cf_last->pop_count = 1;
9214
9215 fc_set_mid(ctx, ctx->bc->fc_sp - 1);
9216 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id;
9217 return 0;
9218 }
9219
9220 static int tgsi_endif(struct r600_shader_ctx *ctx)
9221 {
9222 pops(ctx, 1);
9223 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_IF) {
9224 R600_ERR("if/endif unbalanced in shader\n");
9225 return -1;
9226 }
9227
9228 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid == NULL) {
9229 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
9230 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->pop_count = 1;
9231 } else {
9232 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
9233 }
9234 fc_poplevel(ctx);
9235
9236 callstack_pop(ctx, FC_PUSH_VPM);
9237 return 0;
9238 }
9239
9240 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
9241 {
9242 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
9243 * limited to 4096 iterations, like the other LOOP_* instructions. */
9244 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
9245
9246 fc_pushlevel(ctx, FC_LOOP);
9247
9248 /* check stack depth */
9249 callstack_push(ctx, FC_LOOP);
9250 return 0;
9251 }
9252
9253 static int tgsi_endloop(struct r600_shader_ctx *ctx)
9254 {
9255 unsigned i;
9256
9257 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
9258
9259 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_LOOP) {
9260 R600_ERR("loop/endloop in shader code are not paired.\n");
9261 return -EINVAL;
9262 }
9263
9264 /* fixup loop pointers - from r600isa
9265 LOOP END points to CF after LOOP START,
9266 LOOP START point to CF after LOOP END
9267 BRK/CONT point to LOOP END CF
9268 */
9269 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->id + 2;
9270
9271 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
9272
9273 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp - 1].num_mid; i++) {
9274 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[i]->cf_addr = ctx->bc->cf_last->id;
9275 }
9276 /* XXX add LOOPRET support */
9277 fc_poplevel(ctx);
9278 callstack_pop(ctx, FC_LOOP);
9279 return 0;
9280 }
9281
9282 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
9283 {
9284 unsigned int fscp;
9285
9286 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
9287 {
9288 if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
9289 break;
9290 }
9291
9292 if (fscp == 0) {
9293 R600_ERR("Break not inside loop/endloop pair\n");
9294 return -EINVAL;
9295 }
9296
9297 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9298
9299 fc_set_mid(ctx, fscp - 1);
9300
9301 return 0;
9302 }
9303
9304 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
9305 {
9306 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9307 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
9308 int r;
9309
9310 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
9311 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
9312
9313 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9314 if (!r) {
9315 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
9316 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
9317 return emit_inc_ring_offset(ctx, stream, TRUE);
9318 }
9319 return r;
9320 }
9321
9322 static int tgsi_umad(struct r600_shader_ctx *ctx)
9323 {
9324 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9325 struct r600_bytecode_alu alu;
9326 int i, j, k, r;
9327 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9328
9329 /* src0 * src1 */
9330 for (i = 0; i < lasti + 1; i++) {
9331 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9332 continue;
9333
9334 if (ctx->bc->chip_class == CAYMAN) {
9335 for (j = 0 ; j < 4; j++) {
9336 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9337
9338 alu.op = ALU_OP2_MULLO_UINT;
9339 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
9340 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
9341 }
9342 alu.dst.chan = j;
9343 alu.dst.sel = ctx->temp_reg;
9344 alu.dst.write = (j == i);
9345 if (j == 3)
9346 alu.last = 1;
9347 r = r600_bytecode_add_alu(ctx->bc, &alu);
9348 if (r)
9349 return r;
9350 }
9351 } else {
9352 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9353
9354 alu.dst.chan = i;
9355 alu.dst.sel = ctx->temp_reg;
9356 alu.dst.write = 1;
9357
9358 alu.op = ALU_OP2_MULLO_UINT;
9359 for (j = 0; j < 2; j++) {
9360 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
9361 }
9362
9363 alu.last = 1;
9364 r = r600_bytecode_add_alu(ctx->bc, &alu);
9365 if (r)
9366 return r;
9367 }
9368 }
9369
9370
9371 for (i = 0; i < lasti + 1; i++) {
9372 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9373 continue;
9374
9375 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9376 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9377
9378 alu.op = ALU_OP2_ADD_INT;
9379
9380 alu.src[0].sel = ctx->temp_reg;
9381 alu.src[0].chan = i;
9382
9383 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9384 if (i == lasti) {
9385 alu.last = 1;
9386 }
9387 r = r600_bytecode_add_alu(ctx->bc, &alu);
9388 if (r)
9389 return r;
9390 }
9391 return 0;
9392 }
9393
9394 static int tgsi_pk2h(struct r600_shader_ctx *ctx)
9395 {
9396 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9397 struct r600_bytecode_alu alu;
9398 int r, i;
9399 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9400
9401 /* temp.xy = f32_to_f16(src) */
9402 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9403 alu.op = ALU_OP1_FLT32_TO_FLT16;
9404 alu.dst.chan = 0;
9405 alu.dst.sel = ctx->temp_reg;
9406 alu.dst.write = 1;
9407 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9408 r = r600_bytecode_add_alu(ctx->bc, &alu);
9409 if (r)
9410 return r;
9411 alu.dst.chan = 1;
9412 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
9413 alu.last = 1;
9414 r = r600_bytecode_add_alu(ctx->bc, &alu);
9415 if (r)
9416 return r;
9417
9418 /* dst.x = temp.y * 0x10000 + temp.x */
9419 for (i = 0; i < lasti + 1; i++) {
9420 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9421 continue;
9422
9423 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9424 alu.op = ALU_OP3_MULADD_UINT24;
9425 alu.is_op3 = 1;
9426 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9427 alu.last = i == lasti;
9428 alu.src[0].sel = ctx->temp_reg;
9429 alu.src[0].chan = 1;
9430 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9431 alu.src[1].value = 0x10000;
9432 alu.src[2].sel = ctx->temp_reg;
9433 alu.src[2].chan = 0;
9434 r = r600_bytecode_add_alu(ctx->bc, &alu);
9435 if (r)
9436 return r;
9437 }
9438
9439 return 0;
9440 }
9441
9442 static int tgsi_up2h(struct r600_shader_ctx *ctx)
9443 {
9444 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9445 struct r600_bytecode_alu alu;
9446 int r, i;
9447 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9448
9449 /* temp.x = src.x */
9450 /* note: no need to mask out the high bits */
9451 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9452 alu.op = ALU_OP1_MOV;
9453 alu.dst.chan = 0;
9454 alu.dst.sel = ctx->temp_reg;
9455 alu.dst.write = 1;
9456 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9457 r = r600_bytecode_add_alu(ctx->bc, &alu);
9458 if (r)
9459 return r;
9460
9461 /* temp.y = src.x >> 16 */
9462 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9463 alu.op = ALU_OP2_LSHR_INT;
9464 alu.dst.chan = 1;
9465 alu.dst.sel = ctx->temp_reg;
9466 alu.dst.write = 1;
9467 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9468 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9469 alu.src[1].value = 16;
9470 alu.last = 1;
9471 r = r600_bytecode_add_alu(ctx->bc, &alu);
9472 if (r)
9473 return r;
9474
9475 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
9476 for (i = 0; i < lasti + 1; i++) {
9477 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9478 continue;
9479 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9480 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9481 alu.op = ALU_OP1_FLT16_TO_FLT32;
9482 alu.src[0].sel = ctx->temp_reg;
9483 alu.src[0].chan = i % 2;
9484 alu.last = i == lasti;
9485 r = r600_bytecode_add_alu(ctx->bc, &alu);
9486 if (r)
9487 return r;
9488 }
9489
9490 return 0;
9491 }
9492
9493 static int tgsi_bfe(struct r600_shader_ctx *ctx)
9494 {
9495 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9496 struct r600_bytecode_alu alu;
9497 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9498 int r, i;
9499
9500 r = tgsi_op3(ctx);
9501 if (r)
9502 return r;
9503
9504 for (i = 0; i < lasti + 1; i++) {
9505 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9506 alu.op = ALU_OP2_SETGE_INT;
9507 r600_bytecode_src(&alu.src[0], &ctx->src[2], i);
9508 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9509 alu.src[1].value = 32;
9510 alu.dst.sel = ctx->temp_reg;
9511 alu.dst.chan = i;
9512 alu.dst.write = 1;
9513 if (i == lasti)
9514 alu.last = 1;
9515 r = r600_bytecode_add_alu(ctx->bc, &alu);
9516 if (r)
9517 return r;
9518 }
9519
9520 for (i = 0; i < lasti + 1; i++) {
9521 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9522 alu.op = ALU_OP3_CNDE_INT;
9523 alu.is_op3 = 1;
9524 alu.src[0].sel = ctx->temp_reg;
9525 alu.src[1].chan = i;
9526
9527 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9528 alu.src[1].sel = alu.dst.sel;
9529 alu.src[1].chan = i;
9530 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
9531 alu.dst.write = 1;
9532 if (i == lasti)
9533 alu.last = 1;
9534 r = r600_bytecode_add_alu(ctx->bc, &alu);
9535 if (r)
9536 return r;
9537 }
9538
9539 return 0;
9540 }
9541
9542 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
9543 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
9544 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9545 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9546
9547 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
9548
9549 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
9550 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9551 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9552 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9553 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9554 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9555 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9556 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9557 /* MIN_DX10 returns non-nan result if one src is NaN, MIN returns NaN */
9558 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
9559 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
9560 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9561 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9562 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9563 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9564 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
9565 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9566 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9567 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9568 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9569 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9570 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9571 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9572 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9573 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9574 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9575 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9576 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9577 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9578 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9579 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9580 [35] = { ALU_OP0_NOP, tgsi_unsupported},
9581 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9582 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9583 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9584 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9585 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
9586 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9587 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9588 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9589 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9590 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9591 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9592 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9593 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9594 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9595 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9596 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9597 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9598 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9599 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9600 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9601 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9602 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9603 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9604 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9605 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9606 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
9607 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9608 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9609 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9610 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9611 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9612 [67] = { ALU_OP0_NOP, tgsi_unsupported},
9613 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9614 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9615 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9616 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9617 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9618 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9619 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9620 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9621 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9622 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9623 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9624 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9625 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9626 [81] = { ALU_OP0_NOP, tgsi_unsupported},
9627 [82] = { ALU_OP0_NOP, tgsi_unsupported},
9628 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9629 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9630 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9631 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9632 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
9633 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9634 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9635 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9636 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9637 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9638 [93] = { ALU_OP0_NOP, tgsi_unsupported},
9639 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9640 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9641 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9642 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9643 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9644 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9645 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9646 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9647 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9648 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9649 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9650 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9651 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9652 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9653 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9654 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9655 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9656 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9657 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9658 [113] = { ALU_OP0_NOP, tgsi_unsupported},
9659 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9660 [115] = { ALU_OP0_NOP, tgsi_unsupported},
9661 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9662 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9663 [TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
9664 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
9665 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9666 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9667 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9668 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9669 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9670 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
9671 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9672 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
9673 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9674 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9675 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9676 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9677 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9678 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9679 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9680 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9681 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9682 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9683 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
9684 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9685 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
9686 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9687 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9688 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9689 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9690 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9691 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9692 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9693 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9694 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9695 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9696 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9697 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9698 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9699 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9700 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9701 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9702 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
9703 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9704 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9705 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9706 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9707 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9708 [163] = { ALU_OP0_NOP, tgsi_unsupported},
9709 [164] = { ALU_OP0_NOP, tgsi_unsupported},
9710 [165] = { ALU_OP0_NOP, tgsi_unsupported},
9711 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
9712 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9713 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9714 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9715 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9716 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9717 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9718 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9719 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9720 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9721 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9722 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9723 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9724 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9725 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9726 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9727 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
9728 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
9729 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
9730 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
9731 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
9732 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
9733 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
9734 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
9735 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
9736 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
9737 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
9738 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
9739 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
9740 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9741 };
9742
9743 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
9744 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9745 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9746 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9747 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
9748 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
9749 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9750 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9751 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9752 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9753 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9754 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9755 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9756 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
9757 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
9758 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9759 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9760 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9761 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9762 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
9763 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9764 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9765 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9766 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9767 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9768 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9769 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9770 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9771 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9772 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9773 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9774 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9775 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9776 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9777 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9778 [35] = { ALU_OP0_NOP, tgsi_unsupported},
9779 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9780 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9781 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9782 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9783 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
9784 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9785 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9786 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9787 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9788 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9789 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9790 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9791 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9792 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9793 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9794 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9795 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9796 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9797 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9798 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
9799 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9800 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9801 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9802 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9803 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9804 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9805 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9806 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9807 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9808 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9809 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9810 [67] = { ALU_OP0_NOP, tgsi_unsupported},
9811 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9812 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9813 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9814 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9815 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9816 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9817 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9818 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9819 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9820 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9821 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9822 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9823 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9824 [82] = { ALU_OP0_NOP, tgsi_unsupported},
9825 [83] = { ALU_OP0_NOP, tgsi_unsupported},
9826 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9827 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9828 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9829 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9830 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9831 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9832 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9833 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9834 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9835 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9836 [93] = { ALU_OP0_NOP, tgsi_unsupported},
9837 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9838 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9839 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9840 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9841 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9842 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9843 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9844 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9845 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9846 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9847 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9848 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9849 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9850 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9851 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9852 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9853 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9854 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9855 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9856 [113] = { ALU_OP0_NOP, tgsi_unsupported},
9857 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9858 [115] = { ALU_OP0_NOP, tgsi_unsupported},
9859 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9860 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9861 /* Refer below for TGSI_OPCODE_DFMA */
9862 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
9863 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9864 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9865 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9866 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9867 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9868 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9869 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9870 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
9871 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9872 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9873 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9874 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9875 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9876 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9877 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9878 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9879 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9880 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9881 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9882 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9883 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9884 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9885 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9886 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9887 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9888 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9889 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9890 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9891 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9892 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9893 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9894 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9895 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9896 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9897 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9898 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9899 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9900 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9901 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9902 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9903 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9904 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
9905 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
9906 [163] = { ALU_OP0_NOP, tgsi_unsupported},
9907 [164] = { ALU_OP0_NOP, tgsi_unsupported},
9908 [165] = { ALU_OP0_NOP, tgsi_unsupported},
9909 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9910 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
9911 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
9912 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
9913 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
9914 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
9915 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
9916 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
9917 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
9918 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
9919 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
9920 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9921 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9922 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9923 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9924 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9925 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9926 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9927 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
9928 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
9929 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9930 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9931 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9932 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9933 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9934 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9935 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9936 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9937 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9938 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9939 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9940 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9941 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9942 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9943 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9944 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
9945 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9946 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9947 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9948 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9949 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9950 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9951 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9952 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9953 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9954 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
9955 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9956 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9957 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9958 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9959 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9960 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9961 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9962 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9963 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9964 };
9965
9966 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
9967 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9968 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9969 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9970 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
9971 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
9972 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9973 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9974 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9975 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9976 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9977 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9978 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9979 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
9980 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
9981 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9982 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9983 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9984 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9985 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
9986 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
9987 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9988 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9989 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9990 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9991 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9992 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9993 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9994 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
9995 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
9996 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
9997 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9998 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9999 [33] = { ALU_OP0_NOP, tgsi_unsupported},
10000 [34] = { ALU_OP0_NOP, tgsi_unsupported},
10001 [35] = { ALU_OP0_NOP, tgsi_unsupported},
10002 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
10003 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10004 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10005 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
10006 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
10007 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
10008 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
10009 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10010 [44] = { ALU_OP0_NOP, tgsi_unsupported},
10011 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
10012 [46] = { ALU_OP0_NOP, tgsi_unsupported},
10013 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
10014 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
10015 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
10016 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
10017 [51] = { ALU_OP0_NOP, tgsi_unsupported},
10018 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
10019 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
10020 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
10021 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
10022 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
10023 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
10024 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10025 [59] = { ALU_OP0_NOP, tgsi_unsupported},
10026 [60] = { ALU_OP0_NOP, tgsi_unsupported},
10027 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
10028 [62] = { ALU_OP0_NOP, tgsi_unsupported},
10029 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
10030 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
10031 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
10032 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
10033 [67] = { ALU_OP0_NOP, tgsi_unsupported},
10034 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10035 [69] = { ALU_OP0_NOP, tgsi_unsupported},
10036 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
10037 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10038 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10039 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
10040 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
10041 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
10042 [76] = { ALU_OP0_NOP, tgsi_unsupported},
10043 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
10044 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
10045 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10046 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10047 [82] = { ALU_OP0_NOP, tgsi_unsupported},
10048 [83] = { ALU_OP0_NOP, tgsi_unsupported},
10049 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
10050 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
10051 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
10052 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
10053 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
10054 [88] = { ALU_OP0_NOP, tgsi_unsupported},
10055 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
10056 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
10057 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
10058 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
10059 [93] = { ALU_OP0_NOP, tgsi_unsupported},
10060 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
10061 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10062 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
10063 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
10064 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
10065 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
10066 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10067 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
10068 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10069 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10070 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
10071 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
10072 [106] = { ALU_OP0_NOP, tgsi_unsupported},
10073 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
10074 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
10075 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
10076 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
10077 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
10078 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
10079 [113] = { ALU_OP0_NOP, tgsi_unsupported},
10080 [114] = { ALU_OP0_NOP, tgsi_unsupported},
10081 [115] = { ALU_OP0_NOP, tgsi_unsupported},
10082 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
10083 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
10084 /* Refer below for TGSI_OPCODE_DFMA */
10085 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
10086 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
10087 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
10088 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
10089 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
10090 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
10091 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
10092 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
10093 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
10094 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
10095 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
10096 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
10097 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
10098 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
10099 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
10100 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
10101 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
10102 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
10103 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
10104 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
10105 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
10106 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
10107 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10108 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
10109 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
10110 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10111 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
10112 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
10113 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
10114 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
10115 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
10116 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
10117 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
10118 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
10119 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
10120 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
10121 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
10122 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
10123 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
10124 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
10125 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
10126 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
10127 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
10128 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
10129 [163] = { ALU_OP0_NOP, tgsi_unsupported},
10130 [164] = { ALU_OP0_NOP, tgsi_unsupported},
10131 [165] = { ALU_OP0_NOP, tgsi_unsupported},
10132 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
10133 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
10134 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
10135 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
10136 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
10137 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
10138 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
10139 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
10140 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
10141 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
10142 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
10143 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
10144 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10145 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10146 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
10147 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
10148 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
10149 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
10150 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
10151 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
10152 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
10153 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
10154 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
10155 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
10156 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
10157 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
10158 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
10159 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
10160 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
10161 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
10162 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
10163 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
10164 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
10165 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
10166 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
10167 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
10168 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
10169 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
10170 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
10171 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
10172 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
10173 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
10174 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
10175 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
10176 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
10177 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
10178 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
10179 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
10180 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
10181 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
10182 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
10183 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
10184 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
10185 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
10186 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
10187 };