src/gallium/drivers/r600/r600_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #include <stdio.h>
  27 #include <errno.h>
  28 #include "util/u_inlines.h"
  29 #include "util/u_format.h"
  30 #include "util/u_memory.h"
  31 #include "r600_screen.h"
  32 #include "r600_context.h"
  33 #include "r600_resource.h"
  34 #include "r600d.h"
  35
  36 static void *r600_create_blend_state(struct pipe_context *ctx,
  37                                         const struct pipe_blend_state *state)
  38 {
  39         struct r600_context *rctx = r600_context(ctx);
  40
  41         return r600_context_state(rctx, pipe_blend_type, state);
  42 }
  43
  44 static void *r600_create_dsa_state(struct pipe_context *ctx,
  45                                         const struct pipe_depth_stencil_alpha_state *state)
  46 {
  47         struct r600_context *rctx = r600_context(ctx);
  48
  49         return r600_context_state(rctx, pipe_dsa_type, state);
  50 }
  51
  52 static void *r600_create_rs_state(struct pipe_context *ctx,
  53                                         const struct pipe_rasterizer_state *state)
  54 {
  55         struct r600_context *rctx = r600_context(ctx);
  56
  57         return r600_context_state(rctx, pipe_rasterizer_type, state);
  58 }
  59
  60 static void *r600_create_sampler_state(struct pipe_context *ctx,
  61                                         const struct pipe_sampler_state *state)
  62 {
  63         struct r600_context *rctx = r600_context(ctx);
  64
  65         return r600_context_state(rctx, pipe_sampler_type, state);
  66 }
  67
  68 static void r600_sampler_view_destroy(struct pipe_context *ctx,
  69                                       struct pipe_sampler_view *state)
  70 {
  71         struct r600_context_state *rstate = (struct r600_context_state *)state;
  72
  73         r600_context_state_decref(rstate);
  74 }
  75
  76 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
  77                                                         struct pipe_resource *texture,
  78                                                         const struct pipe_sampler_view *state)
  79 {
  80         struct r600_context *rctx = r600_context(ctx);
  81         struct r600_context_state *rstate;
  82
  83         rstate = r600_context_state(rctx, pipe_sampler_type, state);
  84         pipe_reference(NULL, &texture->reference);
  85         rstate->state.sampler_view.texture = texture;
  86         rstate->state.sampler_view.reference.count = 1;
  87         rstate->state.sampler_view.context = ctx;
  88         return &rstate->state.sampler_view;
  89 }
  90
  91 static void *r600_create_shader_state(struct pipe_context *ctx,
  92                                         const struct pipe_shader_state *state)
  93 {
  94         struct r600_context *rctx = r600_context(ctx);
  95
  96         return r600_context_state(rctx, pipe_shader_type, state);
  97 }
  98
  99 static void *r600_create_vertex_elements(struct pipe_context *ctx,
 100                                 unsigned count,
 101                                 const struct pipe_vertex_element *elements)
 102 {
 103         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 104
 105         assert(count < 32);
 106         v->count = count;
 107         memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
 108         v->refcount = 1;
 109         return v;
 110 }
 111
 112 static void r600_bind_state(struct pipe_context *ctx, void *state)
 113 {
 114         struct r600_context *rctx = r600_context(ctx);
 115         struct r600_context_state *rstate = (struct r600_context_state *)state;
 116
 117         if (state == NULL)
 118                 return;
 119         switch (rstate->type) {
 120         case pipe_rasterizer_type:
 121                 rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
 122                 rctx->rasterizer = r600_context_state_incref(rstate);
 123                 break;
 124         case pipe_poly_stipple_type:
 125                 rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
 126                 rctx->poly_stipple = r600_context_state_incref(rstate);
 127                 break;
 128         case pipe_scissor_type:
 129                 rctx->scissor = r600_context_state_decref(rctx->scissor);
 130                 rctx->scissor = r600_context_state_incref(rstate);
 131                 break;
 132         case pipe_clip_type:
 133                 rctx->clip = r600_context_state_decref(rctx->clip);
 134                 rctx->clip = r600_context_state_incref(rstate);
 135                 break;
 136         case pipe_depth_type:
 137                 rctx->depth = r600_context_state_decref(rctx->depth);
 138                 rctx->depth = r600_context_state_incref(rstate);
 139                 break;
 140         case pipe_stencil_type:
 141                 rctx->stencil = r600_context_state_decref(rctx->stencil);
 142                 rctx->stencil = r600_context_state_incref(rstate);
 143                 break;
 144         case pipe_alpha_type:
 145                 rctx->alpha = r600_context_state_decref(rctx->alpha);
 146                 rctx->alpha = r600_context_state_incref(rstate);
 147                 break;
 148         case pipe_dsa_type:
 149                 rctx->dsa = r600_context_state_decref(rctx->dsa);
 150                 rctx->dsa = r600_context_state_incref(rstate);
 151                 break;
 152         case pipe_blend_type:
 153                 rctx->blend = r600_context_state_decref(rctx->blend);
 154                 rctx->blend = r600_context_state_incref(rstate);
 155                 break;
 156         case pipe_framebuffer_type:
 157                 rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
 158                 rctx->framebuffer = r600_context_state_incref(rstate);
 159                 break;
 160         case pipe_stencil_ref_type:
 161                 rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
 162                 rctx->stencil_ref = r600_context_state_incref(rstate);
 163                 break;
 164         case pipe_viewport_type:
 165                 rctx->viewport = r600_context_state_decref(rctx->viewport);
 166                 rctx->viewport = r600_context_state_incref(rstate);
 167                 break;
 168         case pipe_shader_type:
 169         case pipe_sampler_type:
 170         case pipe_sampler_view_type:
 171         default:
 172                 R600_ERR("invalid type %d\n", rstate->type);
 173                 return;
 174         }
 175 }
 176
 177 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 178 {
 179         struct r600_context *rctx = r600_context(ctx);
 180         struct r600_context_state *rstate = (struct r600_context_state *)state;
 181
 182         rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
 183         rctx->ps_shader = r600_context_state_incref(rstate);
 184 }
 185
 186 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
 187 {
 188         struct r600_context *rctx = r600_context(ctx);
 189         struct r600_context_state *rstate = (struct r600_context_state *)state;
 190
 191         rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
 192         rctx->vs_shader = r600_context_state_incref(rstate);
 193 }
 194
 195 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 196 {
 197         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 198
 199         if (v == NULL)
 200                 return;
 201         if (--v->refcount)
 202                 return;
 203         free(v);
 204 }
 205
 206 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 207 {
 208         struct r600_context *rctx = r600_context(ctx);
 209         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 210
 211         r600_delete_vertex_element(ctx, rctx->vertex_elements);
 212         rctx->vertex_elements = v;
 213         if (v) {
 214                 v->refcount++;
 215         }
 216 }
 217
 218 static void r600_bind_ps_sampler(struct pipe_context *ctx,
 219                                         unsigned count, void **states)
 220 {
 221         struct r600_context *rctx = r600_context(ctx);
 222         struct r600_context_state *rstate;
 223         unsigned i;
 224
 225         for (i = 0; i < rctx->ps_nsampler; i++) {
 226                 rctx->ps_sampler[i] = r600_context_state_decref(rctx->ps_sampler[i]);
 227         }
 228         for (i = 0; i < count; i++) {
 229                 rstate = (struct r600_context_state *)states[i];
 230                 rctx->ps_sampler[i] = r600_context_state_incref(rstate);
 231         }
 232         rctx->ps_nsampler = count;
 233 }
 234
 235 static void r600_bind_vs_sampler(struct pipe_context *ctx,
 236                                         unsigned count, void **states)
 237 {
 238         struct r600_context *rctx = r600_context(ctx);
 239         struct r600_context_state *rstate;
 240         unsigned i;
 241
 242         for (i = 0; i < rctx->vs_nsampler; i++) {
 243                 rctx->vs_sampler[i] = r600_context_state_decref(rctx->vs_sampler[i]);
 244         }
 245         for (i = 0; i < count; i++) {
 246                 rstate = (struct r600_context_state *)states[i];
 247                 rctx->vs_sampler[i] = r600_context_state_incref(rstate);
 248         }
 249         rctx->vs_nsampler = count;
 250 }
 251
 252 static void r600_delete_state(struct pipe_context *ctx, void *state)
 253 {
 254         struct r600_context_state *rstate = (struct r600_context_state *)state;
 255
 256         r600_context_state_decref(rstate);
 257 }
 258
 259 static void r600_set_blend_color(struct pipe_context *ctx,
 260                                         const struct pipe_blend_color *color)
 261 {
 262 }
 263
 264 static void r600_set_clip_state(struct pipe_context *ctx,
 265                                 const struct pipe_clip_state *state)
 266 {
 267 }
 268
 269 static void r600_set_constant_buffer(struct pipe_context *ctx,
 270                                         uint shader, uint index,
 271                                         struct pipe_resource *buffer)
 272 {
 273         struct r600_screen *rscreen = r600_screen(ctx->screen);
 274         struct r600_context *rctx = r600_context(ctx);
 275         unsigned nconstant = 0, i, type, id;
 276         struct radeon_state *rstate;
 277         struct pipe_transfer *transfer;
 278         u32 *ptr;
 279
 280         switch (shader) {
 281         case PIPE_SHADER_VERTEX:
 282                 id = R600_VS_CONSTANT;
 283                 type = R600_VS_CONSTANT_TYPE;
 284                 break;
 285         case PIPE_SHADER_FRAGMENT:
 286                 id = R600_PS_CONSTANT;
 287                 type = R600_PS_CONSTANT_TYPE;
 288                 break;
 289         default:
 290                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, shader);
 291                 return;
 292         }
 293         if (buffer && buffer->width0 > 0) {
 294                 nconstant = buffer->width0 / 16;
 295                 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
 296                 if (ptr == NULL)
 297                         return;
 298                 for (i = 0; i < nconstant; i++) {
 299                         rstate = radeon_state(rscreen->rw, type, id + i);
 300                         if (rstate == NULL)
 301                                 return;
 302                         rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
 303                         rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
 304                         rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
 305                         rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
 306                         if (radeon_state_pm4(rstate))
 307                                 return;
 308                         if (radeon_draw_set_new(rctx->draw, rstate))
 309                                 return;
 310                 }
 311                 pipe_buffer_unmap(ctx, buffer, transfer);
 312         }
 313 }
 314
 315 static void r600_set_ps_sampler_view(struct pipe_context *ctx,
 316                                         unsigned count,
 317                                         struct pipe_sampler_view **views)
 318 {
 319         struct r600_context *rctx = r600_context(ctx);
 320         struct r600_context_state *rstate;
 321         unsigned i;
 322
 323         for (i = 0; i < rctx->ps_nsampler_view; i++) {
 324                 rctx->ps_sampler_view[i] = r600_context_state_decref(rctx->ps_sampler_view[i]);
 325         }
 326         for (i = 0; i < count; i++) {
 327                 rstate = (struct r600_context_state *)views[i];
 328                 rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
 329         }
 330         rctx->ps_nsampler_view = count;
 331 }
 332
 333 static void r600_set_vs_sampler_view(struct pipe_context *ctx,
 334                                         unsigned count,
 335                                         struct pipe_sampler_view **views)
 336 {
 337         struct r600_context *rctx = r600_context(ctx);
 338         struct r600_context_state *rstate;
 339         unsigned i;
 340
 341         for (i = 0; i < rctx->vs_nsampler_view; i++) {
 342                 rctx->vs_sampler_view[i] = r600_context_state_decref(rctx->vs_sampler_view[i]);
 343         }
 344         for (i = 0; i < count; i++) {
 345                 rstate = (struct r600_context_state *)views[i];
 346                 rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
 347         }
 348         rctx->vs_nsampler_view = count;
 349 }
 350
 351 static void r600_set_framebuffer_state(struct pipe_context *ctx,
 352                                         const struct pipe_framebuffer_state *state)
 353 {
 354         struct r600_context *rctx = r600_context(ctx);
 355         struct r600_context_state *rstate;
 356
 357         rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
 358         r600_bind_state(ctx, rstate);
 359 }
 360
 361 static void r600_set_polygon_stipple(struct pipe_context *ctx,
 362                                          const struct pipe_poly_stipple *state)
 363 {
 364 }
 365
 366 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
 367 {
 368 }
 369
 370 static void r600_set_scissor_state(struct pipe_context *ctx,
 371                                         const struct pipe_scissor_state *state)
 372 {
 373         struct r600_context *rctx = r600_context(ctx);
 374         struct r600_context_state *rstate;
 375
 376         rstate = r600_context_state(rctx, pipe_scissor_type, state);
 377         r600_bind_state(ctx, rstate);
 378 }
 379
 380 static void r600_set_stencil_ref(struct pipe_context *ctx,
 381                                 const struct pipe_stencil_ref *state)
 382 {
 383         struct r600_context *rctx = r600_context(ctx);
 384         struct r600_context_state *rstate;
 385
 386         rstate = r600_context_state(rctx, pipe_stencil_ref_type, state);
 387         r600_bind_state(ctx, rstate);
 388 }
 389
 390 static void r600_set_vertex_buffers(struct pipe_context *ctx,
 391                                         unsigned count,
 392                                         const struct pipe_vertex_buffer *buffers)
 393 {
 394         struct r600_context *rctx = r600_context(ctx);
 395         unsigned i;
 396
 397         for (i = 0; i < rctx->nvertex_buffer; i++) {
 398                 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
 399         }
 400         memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
 401         for (i = 0; i < count; i++) {
 402                 rctx->vertex_buffer[i].buffer = NULL;
 403                 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
 404         }
 405         rctx->nvertex_buffer = count;
 406 }
 407
 408 static void r600_set_index_buffer(struct pipe_context *ctx,
 409                                   const struct pipe_index_buffer *ib)
 410 {
 411         struct r600_context *rctx = r600_context(ctx);
 412
 413         if (ib) {
 414                 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
 415                 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
 416         }
 417         else {
 418                 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
 419                 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
 420         }
 421
 422         /* TODO make this more like a state */
 423 }
 424
 425 static void r600_set_viewport_state(struct pipe_context *ctx,
 426                                         const struct pipe_viewport_state *state)
 427 {
 428         struct r600_context *rctx = r600_context(ctx);
 429         struct r600_context_state *rstate;
 430
 431         rstate = r600_context_state(rctx, pipe_viewport_type, state);
 432         r600_bind_state(ctx, rstate);
 433 }
 434
 435 void r600_init_state_functions(struct r600_context *rctx)
 436 {
 437         rctx->context.create_blend_state = r600_create_blend_state;
 438         rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
 439         rctx->context.create_fs_state = r600_create_shader_state;
 440         rctx->context.create_rasterizer_state = r600_create_rs_state;
 441         rctx->context.create_sampler_state = r600_create_sampler_state;
 442         rctx->context.create_sampler_view = r600_create_sampler_view;
 443         rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
 444         rctx->context.create_vs_state = r600_create_shader_state;
 445         rctx->context.bind_blend_state = r600_bind_state;
 446         rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
 447         rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
 448         rctx->context.bind_fs_state = r600_bind_ps_shader;
 449         rctx->context.bind_rasterizer_state = r600_bind_state;
 450         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
 451         rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
 452         rctx->context.bind_vs_state = r600_bind_vs_shader;
 453         rctx->context.delete_blend_state = r600_delete_state;
 454         rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
 455         rctx->context.delete_fs_state = r600_delete_state;
 456         rctx->context.delete_rasterizer_state = r600_delete_state;
 457         rctx->context.delete_sampler_state = r600_delete_state;
 458         rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
 459         rctx->context.delete_vs_state = r600_delete_state;
 460         rctx->context.set_blend_color = r600_set_blend_color;
 461         rctx->context.set_clip_state = r600_set_clip_state;
 462         rctx->context.set_constant_buffer = r600_set_constant_buffer;
 463         rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
 464         rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
 465         rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
 466         rctx->context.set_sample_mask = r600_set_sample_mask;
 467         rctx->context.set_scissor_state = r600_set_scissor_state;
 468         rctx->context.set_stencil_ref = r600_set_stencil_ref;
 469         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
 470         rctx->context.set_index_buffer = r600_set_index_buffer;
 471         rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
 472         rctx->context.set_viewport_state = r600_set_viewport_state;
 473         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
 474 }
 475
 476 struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate)
 477 {
 478         if (rstate == NULL)
 479                 return NULL;
 480         rstate->refcount++;
 481         return rstate;
 482 }
 483
 484 struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate)
 485 {
 486         unsigned i;
 487
 488         if (rstate == NULL)
 489                 return NULL;
 490         if (--rstate->refcount)
 491                 return NULL;
 492         switch (rstate->type) {
 493         case pipe_sampler_view_type:
 494                 pipe_resource_reference(&rstate->state.sampler_view.texture, NULL);
 495                 break;
 496         case pipe_framebuffer_type:
 497                 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
 498                         pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
 499                 }
 500                 pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
 501                 break;
 502         case pipe_viewport_type:
 503         case pipe_depth_type:
 504         case pipe_rasterizer_type:
 505         case pipe_poly_stipple_type:
 506         case pipe_scissor_type:
 507         case pipe_clip_type:
 508         case pipe_stencil_type:
 509         case pipe_alpha_type:
 510         case pipe_dsa_type:
 511         case pipe_blend_type:
 512         case pipe_stencil_ref_type:
 513         case pipe_shader_type:
 514         case pipe_sampler_type:
 515                 break;
 516         default:
 517                 R600_ERR("invalid type %d\n", rstate->type);
 518                 return NULL;
 519         }
 520         radeon_state_decref(rstate->rstate);
 521         FREE(rstate);
 522         return NULL;
 523 }
 524
 525 struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state)
 526 {
 527         struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
 528         const union pipe_states *states = state;
 529         unsigned i;
 530         int r;
 531
 532         if (rstate == NULL)
 533                 return NULL;
 534         rstate->type = type;
 535         rstate->refcount = 1;
 536
 537         switch (rstate->type) {
 538         case pipe_sampler_view_type:
 539                 rstate->state.sampler_view = (*states).sampler_view;
 540                 rstate->state.sampler_view.texture = NULL;
 541                 break;
 542         case pipe_framebuffer_type:
 543                 rstate->state.framebuffer = (*states).framebuffer;
 544                 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
 545                         pipe_surface_reference(&rstate->state.framebuffer.cbufs[i],
 546                                                 (*states).framebuffer.cbufs[i]);
 547                 }
 548                 pipe_surface_reference(&rstate->state.framebuffer.zsbuf,
 549                                         (*states).framebuffer.zsbuf);
 550                 break;
 551         case pipe_viewport_type:
 552                 rstate->state.viewport = (*states).viewport;
 553                 break;
 554         case pipe_depth_type:
 555                 rstate->state.depth = (*states).depth;
 556                 break;
 557         case pipe_rasterizer_type:
 558                 rstate->state.rasterizer = (*states).rasterizer;
 559                 break;
 560         case pipe_poly_stipple_type:
 561                 rstate->state.poly_stipple = (*states).poly_stipple;
 562                 break;
 563         case pipe_scissor_type:
 564                 rstate->state.scissor = (*states).scissor;
 565                 break;
 566         case pipe_clip_type:
 567                 rstate->state.clip = (*states).clip;
 568                 break;
 569         case pipe_stencil_type:
 570                 rstate->state.stencil = (*states).stencil;
 571                 break;
 572         case pipe_alpha_type:
 573                 rstate->state.alpha = (*states).alpha;
 574                 break;
 575         case pipe_dsa_type:
 576                 rstate->state.dsa = (*states).dsa;
 577                 break;
 578         case pipe_blend_type:
 579                 rstate->state.blend = (*states).blend;
 580                 break;
 581         case pipe_stencil_ref_type:
 582                 rstate->state.stencil_ref = (*states).stencil_ref;
 583                 break;
 584         case pipe_shader_type:
 585                 rstate->state.shader = (*states).shader;
 586                 r =  r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
 587                 if (r) {
 588                         r600_context_state_decref(rstate);
 589                         return NULL;
 590                 }
 591                 break;
 592         case pipe_sampler_type:
 593                 rstate->state.sampler = (*states).sampler;
 594                 break;
 595         default:
 596                 R600_ERR("invalid type %d\n", rstate->type);
 597                 FREE(rstate);
 598                 return NULL;
 599         }
 600         return rstate;
 601 }
 602
 603 static struct radeon_state *r600_blend(struct r600_context *rctx)
 604 {
 605         struct r600_screen *rscreen = rctx->screen;
 606         struct radeon_state *rstate;
 607
 608         rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
 609         if (rstate == NULL)
 610                 return NULL;
 611         rstate->states[R600_BLEND__CB_BLEND_RED] = 0x00000000;
 612         rstate->states[R600_BLEND__CB_BLEND_GREEN] = 0x00000000;
 613         rstate->states[R600_BLEND__CB_BLEND_BLUE] = 0x00000000;
 614         rstate->states[R600_BLEND__CB_BLEND_ALPHA] = 0x00000000;
 615         rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00010001;
 616         rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
 617         rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
 618         rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
 619         rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
 620         rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
 621         rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
 622         rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
 623         rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
 624         if (radeon_state_pm4(rstate)) {
 625                 radeon_state_decref(rstate);
 626                 return NULL;
 627         }
 628         return rstate;
 629 }
 630
 631 static struct radeon_state *r600_cb0(struct r600_context *rctx)
 632 {
 633         struct r600_screen *rscreen = rctx->screen;
 634         struct r600_resource_texture *rtex;
 635         struct r600_resource *rbuffer;
 636         struct radeon_state *rstate;
 637         const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
 638         unsigned level = state->cbufs[0]->level;
 639         unsigned pitch, slice;
 640
 641         rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0);
 642         if (rstate == NULL)
 643                 return NULL;
 644         rtex = (struct r600_resource_texture*)state->cbufs[0]->texture;
 645         rbuffer = &rtex->resource;
 646         rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 647         rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 648         rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 649         rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 650         rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
 651         rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
 652         rstate->nbo = 3;
 653         pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
 654         slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[0]->height / 64 - 1;
 655         rstate->states[R600_CB0__CB_COLOR0_BASE] = 0x00000000;
 656         rstate->states[R600_CB0__CB_COLOR0_INFO] = 0x08110068;
 657         rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
 658                                                 S_028060_SLICE_TILE_MAX(slice);
 659         rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
 660         rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
 661         rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
 662         rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
 663         if (radeon_state_pm4(rstate)) {
 664                 radeon_state_decref(rstate);
 665                 return NULL;
 666         }
 667         return rstate;
 668 }
 669
 670 int r600_db_format(unsigned pformat, unsigned *format)
 671 {
 672         switch (pformat) {
 673         case PIPE_FORMAT_Z24X8_UNORM:
 674                 *format = V_028010_DEPTH_X8_24;
 675                 return 0;
 676         case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 677                 *format = V_028010_DEPTH_8_24;
 678                 return 0;
 679         default:
 680                 *format = V_028010_DEPTH_INVALID;
 681                 R600_ERR("unsupported %d\n", pformat);
 682                 return -EINVAL;
 683         }
 684 }
 685
 686 static struct radeon_state *r600_db(struct r600_context *rctx)
 687 {
 688         struct r600_screen *rscreen = rctx->screen;
 689         struct r600_resource_texture *rtex;
 690         struct r600_resource *rbuffer;
 691         struct radeon_state *rstate;
 692         const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
 693         unsigned level = state->cbufs[0]->level;
 694         unsigned pitch, slice, format;
 695
 696         if (state->zsbuf == NULL)
 697                 return NULL;
 698
 699         rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
 700         if (rstate == NULL)
 701                 return NULL;
 702
 703         rtex = (struct r600_resource_texture*)state->zsbuf->texture;
 704         rbuffer = &rtex->resource;
 705         rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 706         rstate->nbo = 1;
 707         rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
 708         level = state->zsbuf->level;
 709         pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
 710         slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
 711         if (r600_db_format(state->zsbuf->texture->format, &format)) {
 712                 radeon_state_decref(rstate);
 713                 return NULL;
 714         }
 715         rstate->states[R600_DB__DB_DEPTH_BASE] = 0x00000000;
 716         rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010000 |
 717                                         S_028010_FORMAT(format);
 718         rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
 719         rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
 720         rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
 721                                                 S_028000_SLICE_TILE_MAX(slice);
 722         if (radeon_state_pm4(rstate)) {
 723                 radeon_state_decref(rstate);
 724                 return NULL;
 725         }
 726         return rstate;
 727 }
 728
 729 static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 730 {
 731         const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
 732         struct r600_screen *rscreen = rctx->screen;
 733         struct radeon_state *rstate;
 734
 735         rctx->flat_shade = state->flatshade;
 736         rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
 737         if (rstate == NULL)
 738                 return NULL;
 739         rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
 740         rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0x00000000;
 741         rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000 |
 742                         S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 743                         S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
 744                         S_028814_FACE(!state->front_ccw);
 745         rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] = 0x00000000;
 746         rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
 747         rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = 0x00080008;
 748         rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x00000000;
 749         rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
 750         rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
 751         rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
 752         rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
 753         rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
 754         rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
 755         rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
 756         rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
 757         rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = 0x00000000;
 758         rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
 759         rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = 0x00000000;
 760         rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = 0x00000000;
 761         rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = 0x00000000;
 762         rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = 0x00000000;
 763         if (radeon_state_pm4(rstate)) {
 764                 radeon_state_decref(rstate);
 765                 return NULL;
 766         }
 767         return rstate;
 768 }
 769
 770 static struct radeon_state *r600_scissor(struct r600_context *rctx)
 771 {
 772         const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
 773         struct r600_screen *rscreen = rctx->screen;
 774         struct radeon_state *rstate;
 775         u32 tl, br;
 776
 777         tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
 778         br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
 779         rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
 780         if (rstate == NULL)
 781                 return NULL;
 782         rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
 783         rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
 784         rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
 785         rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
 786         rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
 787         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
 788         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
 789         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
 790         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
 791         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
 792         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
 793         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
 794         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
 795         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
 796         rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
 797         rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
 798         rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
 799         rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
 800         rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
 801         if (radeon_state_pm4(rstate)) {
 802                 radeon_state_decref(rstate);
 803                 return NULL;
 804         }
 805         return rstate;
 806 }
 807
 808 static struct radeon_state *r600_viewport(struct r600_context *rctx)
 809 {
 810         const struct pipe_viewport_state *state = &rctx->viewport->state.viewport;
 811         struct r600_screen *rscreen = rctx->screen;
 812         struct radeon_state *rstate;
 813
 814         rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
 815         if (rstate == NULL)
 816                 return NULL;
 817         rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
 818         rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
 819         rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
 820         rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
 821         rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
 822         rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
 823         rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
 824         rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
 825         rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
 826         if (radeon_state_pm4(rstate)) {
 827                 radeon_state_decref(rstate);
 828                 return NULL;
 829         }
 830         return rstate;
 831 }
 832
 833 static struct radeon_state *r600_dsa(struct r600_context *rctx)
 834 {
 835         const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
 836         struct r600_screen *rscreen = rctx->screen;
 837         struct radeon_state *rstate;
 838         unsigned db_depth_control;
 839
 840         rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
 841         if (rstate == NULL)
 842                 return NULL;
 843         db_depth_control = 0x00700700 | S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | S_028800_ZFUNC(state->depth.func);
 844
 845         rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
 846         rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
 847         rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = 0x00000000;
 848         rstate->states[R600_DSA__DB_STENCILREFMASK] = 0xFFFFFF00;
 849         rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = 0xFFFFFF00;
 850         rstate->states[R600_DSA__SX_ALPHA_REF] = 0x00000000;
 851         rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
 852         rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
 853         rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
 854         rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
 855         rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210;
 856         rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
 857         rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
 858         rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
 859         rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
 860         rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
 861         if (radeon_state_pm4(rstate)) {
 862                 radeon_state_decref(rstate);
 863                 return NULL;
 864         }
 865         return rstate;
 866 }
 867
 868 static inline unsigned r600_tex_wrap(unsigned wrap)
 869 {
 870         switch (wrap) {
 871         default:
 872         case PIPE_TEX_WRAP_REPEAT:
 873                 return V_03C000_SQ_TEX_WRAP;
 874         case PIPE_TEX_WRAP_CLAMP:
 875                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
 876         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
 877                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
 878         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
 879                 return V_03C000_SQ_TEX_CLAMP_BORDER;
 880         case PIPE_TEX_WRAP_MIRROR_REPEAT:
 881                 return V_03C000_SQ_TEX_MIRROR;
 882         case PIPE_TEX_WRAP_MIRROR_CLAMP:
 883                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
 884         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
 885                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
 886         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
 887                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
 888         }
 889 }
 890
 891 static inline unsigned r600_tex_filter(unsigned filter)
 892 {
 893         switch (filter) {
 894         default:
 895         case PIPE_TEX_FILTER_NEAREST:
 896                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
 897         case PIPE_TEX_FILTER_LINEAR:
 898                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
 899         }
 900 }
 901
 902 static inline unsigned r600_tex_mipfilter(unsigned filter)
 903 {
 904         switch (filter) {
 905         case PIPE_TEX_MIPFILTER_NEAREST:
 906                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
 907         case PIPE_TEX_MIPFILTER_LINEAR:
 908                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
 909         default:
 910         case PIPE_TEX_MIPFILTER_NONE:
 911                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
 912         }
 913 }
 914
 915 static inline unsigned r600_tex_compare(unsigned compare)
 916 {
 917         switch (compare) {
 918         default:
 919         case PIPE_FUNC_NEVER:
 920                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
 921         case PIPE_FUNC_LESS:
 922                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
 923         case PIPE_FUNC_EQUAL:
 924                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
 925         case PIPE_FUNC_LEQUAL:
 926                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
 927         case PIPE_FUNC_GREATER:
 928                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
 929         case PIPE_FUNC_NOTEQUAL:
 930                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
 931         case PIPE_FUNC_GEQUAL:
 932                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
 933         case PIPE_FUNC_ALWAYS:
 934                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
 935         }
 936 }
 937
 938 static INLINE u32 S_FIXED(float value, u32 frac_bits)
 939 {
 940         return value * (1 << frac_bits);
 941 }
 942
 943 static struct radeon_state *r600_sampler(struct r600_context *rctx,
 944                                 const struct pipe_sampler_state *state,
 945                                 unsigned id)
 946 {
 947         struct r600_screen *rscreen = rctx->screen;
 948         struct radeon_state *rstate;
 949
 950         rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
 951         if (rstate == NULL)
 952                 return NULL;
 953         rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
 954                         S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 955                         S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
 956                         S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
 957                         S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
 958                         S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
 959                         S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
 960                         S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func));
 961         /* FIXME LOD it depends on texture base level ... */
 962         rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
 963                         S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
 964                         S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
 965                         S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
 966         rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
 967         if (radeon_state_pm4(rstate)) {
 968                 radeon_state_decref(rstate);
 969                 return NULL;
 970         }
 971         return rstate;
 972 }
 973
 974 static inline unsigned r600_tex_swizzle(unsigned swizzle)
 975 {
 976         switch (swizzle) {
 977         case PIPE_SWIZZLE_RED:
 978                 return V_038010_SQ_SEL_X;
 979         case PIPE_SWIZZLE_GREEN:
 980                 return V_038010_SQ_SEL_Y;
 981         case PIPE_SWIZZLE_BLUE:
 982                 return V_038010_SQ_SEL_Z;
 983         case PIPE_SWIZZLE_ALPHA:
 984                 return V_038010_SQ_SEL_W;
 985         case PIPE_SWIZZLE_ZERO:
 986                 return V_038010_SQ_SEL_0;
 987         default:
 988         case PIPE_SWIZZLE_ONE:
 989                 return V_038010_SQ_SEL_1;
 990         }
 991 }
 992
 993 static inline unsigned r600_format_type(unsigned format_type)
 994 {
 995         switch (format_type) {
 996         default:
 997         case UTIL_FORMAT_TYPE_UNSIGNED:
 998                 return V_038010_SQ_FORMAT_COMP_UNSIGNED;
 999         case UTIL_FORMAT_TYPE_SIGNED:
1000                 return V_038010_SQ_FORMAT_COMP_SIGNED;
1001         case UTIL_FORMAT_TYPE_FIXED:
1002                 return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
1003         }
1004 }
1005
1006 static inline unsigned r600_tex_dim(unsigned dim)
1007 {
1008         switch (dim) {
1009         default:
1010         case PIPE_TEXTURE_1D:
1011                 return V_038000_SQ_TEX_DIM_1D;
1012         case PIPE_TEXTURE_2D:
1013                 return V_038000_SQ_TEX_DIM_2D;
1014         case PIPE_TEXTURE_3D:
1015                 return V_038000_SQ_TEX_DIM_3D;
1016         case PIPE_TEXTURE_CUBE:
1017                 return V_038000_SQ_TEX_DIM_CUBEMAP;
1018         }
1019 }
1020
1021 static struct radeon_state *r600_resource(struct r600_context *rctx,
1022                                         const struct pipe_sampler_view *view,
1023                                         unsigned id)
1024 {
1025         struct r600_screen *rscreen = rctx->screen;
1026         const struct util_format_description *desc;
1027         struct r600_resource_texture *tmp;
1028         struct r600_resource *rbuffer;
1029         struct radeon_state *rstate;
1030         unsigned format;
1031
1032         if (r600_conv_pipe_format(view->texture->format, &format))
1033                 return NULL;
1034         desc = util_format_description(view->texture->format);
1035         assert(desc == NULL);
1036         rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
1037         if (rstate == NULL) {
1038                 return NULL;
1039         }
1040         tmp = (struct r600_resource_texture*)view->texture;
1041         rbuffer = &tmp->resource;
1042         rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1043         rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1044         rstate->nbo = 2;
1045         rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
1046         rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
1047         rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
1048         rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
1049
1050         /* FIXME properly handle first level != 0 */
1051         rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
1052                         S_038000_DIM(r600_tex_dim(view->texture->target)) |
1053                         S_038000_PITCH(((tmp->pitch[0] / tmp->bpt) / 8) - 1) |
1054                         S_038000_TEX_WIDTH(view->texture->width0 - 1);
1055         rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
1056                         S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
1057                         S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
1058                         S_038004_DATA_FORMAT(format);
1059         rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = 0;
1060         rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
1061         rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
1062                         S_038010_FORMAT_COMP_X(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1063                         S_038010_FORMAT_COMP_Y(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1064                         S_038010_FORMAT_COMP_Z(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1065                         S_038010_FORMAT_COMP_W(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1066                         S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
1067                         S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
1068                         S_038010_REQUEST_SIZE(1) |
1069                         S_038010_DST_SEL_X(r600_tex_swizzle(view->swizzle_b)) |
1070                         S_038010_DST_SEL_Y(r600_tex_swizzle(view->swizzle_g)) |
1071                         S_038010_DST_SEL_Z(r600_tex_swizzle(view->swizzle_r)) |
1072                         S_038010_DST_SEL_W(r600_tex_swizzle(view->swizzle_a)) |
1073                         S_038010_BASE_LEVEL(view->first_level);
1074         rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
1075                         S_038014_LAST_LEVEL(view->last_level) |
1076                         S_038014_BASE_ARRAY(0) |
1077                         S_038014_LAST_ARRAY(0);
1078         rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
1079                         S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
1080         if (radeon_state_pm4(rstate)) {
1081                 radeon_state_decref(rstate);
1082                 return NULL;
1083         }
1084         return rstate;
1085 }
1086
1087 int r600_context_hw_states(struct r600_context *rctx)
1088 {
1089         unsigned i;
1090         int r;
1091
1092         /* free previous TODO determine what need to be updated, what
1093          * doesn't
1094          */
1095         //radeon_state_decref(rctx->hw_states.config);
1096         //radeon_state_decref(rctx->hw_states.cb_cntl);
1097         radeon_state_decref(rctx->hw_states.db);
1098         radeon_state_decref(rctx->hw_states.rasterizer);
1099         radeon_state_decref(rctx->hw_states.scissor);
1100         radeon_state_decref(rctx->hw_states.dsa);
1101         radeon_state_decref(rctx->hw_states.blend);
1102         radeon_state_decref(rctx->hw_states.viewport);
1103         radeon_state_decref(rctx->hw_states.cb0);
1104         for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
1105                 radeon_state_decref(rctx->hw_states.ps_resource[i]);
1106                 rctx->hw_states.ps_resource[i] = NULL;
1107         }
1108         rctx->hw_states.ps_nresource = 0;
1109         for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
1110                 radeon_state_decref(rctx->hw_states.ps_sampler[i]);
1111                 rctx->hw_states.ps_sampler[i] = NULL;
1112         }
1113         rctx->hw_states.ps_nsampler = 0;
1114
1115         /* build new states */
1116         rctx->hw_states.rasterizer = r600_rasterizer(rctx);
1117         rctx->hw_states.scissor = r600_scissor(rctx);
1118         rctx->hw_states.dsa = r600_dsa(rctx);
1119         rctx->hw_states.blend = r600_blend(rctx);
1120         rctx->hw_states.viewport = r600_viewport(rctx);
1121         rctx->hw_states.cb0 = r600_cb0(rctx);
1122         rctx->hw_states.db = r600_db(rctx);
1123         for (i = 0; i < rctx->ps_nsampler; i++) {
1124                 if (rctx->ps_sampler[i]) {
1125                         rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
1126                                                         &rctx->ps_sampler[i]->state.sampler,
1127                                                         R600_PS_SAMPLER + i);
1128                 }
1129         }
1130         rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
1131         for (i = 0; i < rctx->ps_nsampler_view; i++) {
1132                 if (rctx->ps_sampler_view[i]) {
1133                         rctx->hw_states.ps_resource[i] = r600_resource(rctx,
1134                                                         &rctx->ps_sampler_view[i]->state.sampler_view,
1135                                                         R600_PS_RESOURCE + i);
1136                 }
1137         }
1138         rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
1139
1140         /* bind states */
1141         r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
1142         if (r)
1143                 return r;
1144         r = radeon_draw_set(rctx->draw, rctx->hw_states.rasterizer);
1145         if (r)
1146                 return r;
1147         r = radeon_draw_set(rctx->draw, rctx->hw_states.scissor);
1148         if (r)
1149                 return r;
1150         r = radeon_draw_set(rctx->draw, rctx->hw_states.dsa);
1151         if (r)
1152                 return r;
1153         r = radeon_draw_set(rctx->draw, rctx->hw_states.blend);
1154         if (r)
1155                 return r;
1156         r = radeon_draw_set(rctx->draw, rctx->hw_states.viewport);
1157         if (r)
1158                 return r;
1159         r = radeon_draw_set(rctx->draw, rctx->hw_states.cb0);
1160         if (r)
1161                 return r;
1162         r = radeon_draw_set(rctx->draw, rctx->hw_states.config);
1163         if (r)
1164                 return r;
1165         r = radeon_draw_set(rctx->draw, rctx->hw_states.cb_cntl);
1166         if (r)
1167                 return r;
1168         for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
1169                 if (rctx->hw_states.ps_resource[i]) {
1170                         r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_resource[i]);
1171                         if (r)
1172                                 return r;
1173                 }
1174         }
1175         for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
1176                 if (rctx->hw_states.ps_sampler[i]) {
1177                         r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_sampler[i]);
1178                         if (r)
1179                                 return r;
1180                 }
1181         }
1182         return 0;
1183 }