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r600g: add draw_vbo check for a NULL pixel shader
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
145 {
146 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
147 FALSE) != ~0U;
148 }
149
150 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
151 {
152 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
153 r600_translate_colorswap(format, FALSE) != ~0U;
154 }
155
156 static bool r600_is_zs_format_supported(enum pipe_format format)
157 {
158 return r600_translate_dbformat(format) != ~0U;
159 }
160
161 boolean r600_is_format_supported(struct pipe_screen *screen,
162 enum pipe_format format,
163 enum pipe_texture_target target,
164 unsigned sample_count,
165 unsigned usage)
166 {
167 struct r600_screen *rscreen = (struct r600_screen*)screen;
168 unsigned retval = 0;
169
170 if (target >= PIPE_MAX_TEXTURE_TYPES) {
171 R600_ERR("r600: unsupported texture type %d\n", target);
172 return FALSE;
173 }
174
175 if (!util_format_is_supported(format, usage))
176 return FALSE;
177
178 if (sample_count > 1) {
179 if (!rscreen->has_msaa)
180 return FALSE;
181
182 /* R11G11B10 is broken on R6xx. */
183 if (rscreen->b.chip_class == R600 &&
184 format == PIPE_FORMAT_R11G11B10_FLOAT)
185 return FALSE;
186
187 /* MSAA integer colorbuffers hang. */
188 if (util_format_is_pure_integer(format) &&
189 !util_format_is_depth_or_stencil(format))
190 return FALSE;
191
192 switch (sample_count) {
193 case 2:
194 case 4:
195 case 8:
196 break;
197 default:
198 return FALSE;
199 }
200 }
201
202 if (usage & PIPE_BIND_SAMPLER_VIEW) {
203 if (target == PIPE_BUFFER) {
204 if (r600_is_vertex_format_supported(format))
205 retval |= PIPE_BIND_SAMPLER_VIEW;
206 } else {
207 if (r600_is_sampler_format_supported(screen, format))
208 retval |= PIPE_BIND_SAMPLER_VIEW;
209 }
210 }
211
212 if ((usage & (PIPE_BIND_RENDER_TARGET |
213 PIPE_BIND_DISPLAY_TARGET |
214 PIPE_BIND_SCANOUT |
215 PIPE_BIND_SHARED |
216 PIPE_BIND_BLENDABLE)) &&
217 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
218 retval |= usage &
219 (PIPE_BIND_RENDER_TARGET |
220 PIPE_BIND_DISPLAY_TARGET |
221 PIPE_BIND_SCANOUT |
222 PIPE_BIND_SHARED);
223 if (!util_format_is_pure_integer(format) &&
224 !util_format_is_depth_or_stencil(format))
225 retval |= usage & PIPE_BIND_BLENDABLE;
226 }
227
228 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
229 r600_is_zs_format_supported(format)) {
230 retval |= PIPE_BIND_DEPTH_STENCIL;
231 }
232
233 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
234 r600_is_vertex_format_supported(format)) {
235 retval |= PIPE_BIND_VERTEX_BUFFER;
236 }
237
238 if ((usage & PIPE_BIND_LINEAR) &&
239 !util_format_is_compressed(format) &&
240 !(usage & PIPE_BIND_DEPTH_STENCIL))
241 retval |= PIPE_BIND_LINEAR;
242
243 return retval == usage;
244 }
245
246 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
247 {
248 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
249 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
250 float offset_units = state->offset_units;
251 float offset_scale = state->offset_scale;
252 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
253
254 if (!state->offset_units_unscaled) {
255 switch (state->zs_format) {
256 case PIPE_FORMAT_Z24X8_UNORM:
257 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
258 offset_units *= 2.0f;
259 pa_su_poly_offset_db_fmt_cntl =
260 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
261 break;
262 case PIPE_FORMAT_Z16_UNORM:
263 offset_units *= 4.0f;
264 pa_su_poly_offset_db_fmt_cntl =
265 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
266 break;
267 default:
268 pa_su_poly_offset_db_fmt_cntl =
269 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
270 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
271 }
272 }
273
274 radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
275 radeon_emit(cs, fui(offset_scale));
276 radeon_emit(cs, fui(offset_units));
277 radeon_emit(cs, fui(offset_scale));
278 radeon_emit(cs, fui(offset_units));
279
280 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
281 pa_su_poly_offset_db_fmt_cntl);
282 }
283
284 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
285 {
286 int j = state->independent_blend_enable ? i : 0;
287
288 unsigned eqRGB = state->rt[j].rgb_func;
289 unsigned srcRGB = state->rt[j].rgb_src_factor;
290 unsigned dstRGB = state->rt[j].rgb_dst_factor;
291
292 unsigned eqA = state->rt[j].alpha_func;
293 unsigned srcA = state->rt[j].alpha_src_factor;
294 unsigned dstA = state->rt[j].alpha_dst_factor;
295 uint32_t bc = 0;
296
297 if (!state->rt[j].blend_enable)
298 return 0;
299
300 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
301 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
302 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
303
304 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
305 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
306 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
307 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
308 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
309 }
310 return bc;
311 }
312
313 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
314 const struct pipe_blend_state *state,
315 int mode)
316 {
317 struct r600_context *rctx = (struct r600_context *)ctx;
318 uint32_t color_control = 0, target_mask = 0;
319 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
320
321 if (!blend) {
322 return NULL;
323 }
324
325 r600_init_command_buffer(&blend->buffer, 20);
326 r600_init_command_buffer(&blend->buffer_no_blend, 20);
327
328 /* R600 does not support per-MRT blends */
329 if (rctx->b.family > CHIP_R600)
330 color_control |= S_028808_PER_MRT_BLEND(1);
331
332 if (state->logicop_enable) {
333 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
334 } else {
335 color_control |= (0xcc << 16);
336 }
337 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
338 if (state->independent_blend_enable) {
339 for (int i = 0; i < 8; i++) {
340 if (state->rt[i].blend_enable) {
341 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
342 }
343 target_mask |= (state->rt[i].colormask << (4 * i));
344 }
345 } else {
346 for (int i = 0; i < 8; i++) {
347 if (state->rt[0].blend_enable) {
348 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
349 }
350 target_mask |= (state->rt[0].colormask << (4 * i));
351 }
352 }
353
354 if (target_mask)
355 color_control |= S_028808_SPECIAL_OP(mode);
356 else
357 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
358
359 /* only MRT0 has dual src blend */
360 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
361 blend->cb_target_mask = target_mask;
362 blend->cb_color_control = color_control;
363 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
364 blend->alpha_to_one = state->alpha_to_one;
365
366 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
367 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
368 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
369 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
370 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
371 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
372
373 /* Copy over the registers set so far into buffer_no_blend. */
374 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
375 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
376
377 /* Only add blend registers if blending is enabled. */
378 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
379 return blend;
380 }
381
382 /* The first R600 does not support per-MRT blends */
383 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
384 r600_get_blend_control(state, 0));
385
386 if (rctx->b.family > CHIP_R600) {
387 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
388 for (int i = 0; i < 8; i++) {
389 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
390 }
391 }
392 return blend;
393 }
394
395 static void *r600_create_blend_state(struct pipe_context *ctx,
396 const struct pipe_blend_state *state)
397 {
398 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
399 }
400
401 static void *r600_create_dsa_state(struct pipe_context *ctx,
402 const struct pipe_depth_stencil_alpha_state *state)
403 {
404 unsigned db_depth_control, alpha_test_control, alpha_ref;
405 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
406
407 if (!dsa) {
408 return NULL;
409 }
410
411 r600_init_command_buffer(&dsa->buffer, 3);
412
413 dsa->valuemask[0] = state->stencil[0].valuemask;
414 dsa->valuemask[1] = state->stencil[1].valuemask;
415 dsa->writemask[0] = state->stencil[0].writemask;
416 dsa->writemask[1] = state->stencil[1].writemask;
417 dsa->zwritemask = state->depth.writemask;
418
419 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
420 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
421 S_028800_ZFUNC(state->depth.func);
422
423 /* stencil */
424 if (state->stencil[0].enabled) {
425 db_depth_control |= S_028800_STENCIL_ENABLE(1);
426 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
427 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
428 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
429 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
430
431 if (state->stencil[1].enabled) {
432 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
433 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
434 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
435 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
436 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
437 }
438 }
439
440 /* alpha */
441 alpha_test_control = 0;
442 alpha_ref = 0;
443 if (state->alpha.enabled) {
444 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
445 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
446 alpha_ref = fui(state->alpha.ref_value);
447 }
448 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
449 dsa->alpha_ref = alpha_ref;
450
451 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
452 return dsa;
453 }
454
455 static void *r600_create_rs_state(struct pipe_context *ctx,
456 const struct pipe_rasterizer_state *state)
457 {
458 struct r600_context *rctx = (struct r600_context *)ctx;
459 unsigned tmp, sc_mode_cntl, spi_interp;
460 float psize_min, psize_max;
461 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
462
463 if (!rs) {
464 return NULL;
465 }
466
467 r600_init_command_buffer(&rs->buffer, 30);
468
469 rs->scissor_enable = state->scissor;
470 rs->clip_halfz = state->clip_halfz;
471 rs->flatshade = state->flatshade;
472 rs->sprite_coord_enable = state->sprite_coord_enable;
473 rs->rasterizer_discard = state->rasterizer_discard;
474 rs->two_side = state->light_twoside;
475 rs->clip_plane_enable = state->clip_plane_enable;
476 rs->pa_sc_line_stipple = state->line_stipple_enable ?
477 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
478 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
479 rs->pa_cl_clip_cntl =
480 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
481 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
482 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
483 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
484 if (rctx->b.chip_class == R700) {
485 rs->pa_cl_clip_cntl |=
486 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
487 }
488 rs->multisample_enable = state->multisample;
489
490 /* offset */
491 rs->offset_units = state->offset_units;
492 rs->offset_scale = state->offset_scale * 16.0f;
493 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
494 rs->offset_units_unscaled = state->offset_units_unscaled;
495
496 if (state->point_size_per_vertex) {
497 psize_min = util_get_min_point_size(state);
498 psize_max = 8192;
499 } else {
500 /* Force the point size to be as if the vertex output was disabled. */
501 psize_min = state->point_size;
502 psize_max = state->point_size;
503 }
504
505 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
506 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
507 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
508 S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1);
509 if (rctx->b.family == CHIP_RV770) {
510 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */
511 sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1);
512 }
513 if (rctx->b.chip_class >= R700) {
514 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
515 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
516 S_028A4C_R700_VPORT_SCISSOR_ENABLE(1);
517 } else {
518 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
519 }
520
521 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
522 if (state->sprite_coord_enable) {
523 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
524 S_0286D4_PNT_SPRITE_OVRD_X(2) |
525 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
526 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
527 S_0286D4_PNT_SPRITE_OVRD_W(1);
528 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
529 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
530 }
531 }
532
533 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
534 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
535 tmp = r600_pack_float_12p4(state->point_size/2);
536 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
537 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
538 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
539 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
540 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
541 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
542 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
543
544 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
545 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
546 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
547 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
548 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
549 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
550
551 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
552 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
553 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
554 S_028814_FACE(!state->front_ccw) |
555 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
556 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
557 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
558 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
559 state->fill_back != PIPE_POLYGON_MODE_FILL) |
560 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
561 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
562 if (rctx->b.chip_class == R700) {
563 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
564 }
565 if (rctx->b.chip_class == R600) {
566 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
567 S_028350_MULTIPASS(state->rasterizer_discard));
568 }
569 return rs;
570 }
571
572 static unsigned r600_tex_filter(unsigned filter, unsigned max_aniso)
573 {
574 if (filter == PIPE_TEX_FILTER_LINEAR)
575 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_BILINEAR
576 : V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
577 else
578 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_POINT
579 : V_03C000_SQ_TEX_XY_FILTER_POINT;
580 }
581
582 static void *r600_create_sampler_state(struct pipe_context *ctx,
583 const struct pipe_sampler_state *state)
584 {
585 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
586 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
587 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
588 : state->max_anisotropy;
589 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
590
591 if (!ss) {
592 return NULL;
593 }
594
595 ss->seamless_cube_map = state->seamless_cube_map;
596 ss->border_color_use = sampler_state_needs_border_color(state);
597
598 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
599 ss->tex_sampler_words[0] =
600 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
601 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
602 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
603 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter, max_aniso)) |
604 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter, max_aniso)) |
605 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
606 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
607 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
608 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
609 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
610 ss->tex_sampler_words[1] =
611 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
612 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
613 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
614 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
615 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
616
617 if (ss->border_color_use) {
618 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
619 }
620 return ss;
621 }
622
623 static struct pipe_sampler_view *
624 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
625 unsigned width0, unsigned height0)
626
627 {
628 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
629 int stride = util_format_get_blocksize(view->base.format);
630 unsigned format, num_format, format_comp, endian;
631 uint64_t offset = view->base.u.buf.offset;
632 unsigned size = view->base.u.buf.size;
633
634 r600_vertex_data_type(view->base.format,
635 &format, &num_format, &format_comp,
636 &endian);
637
638 view->tex_resource = &tmp->resource;
639 view->skip_mip_address_reloc = true;
640
641 view->tex_resource_words[0] = offset;
642 view->tex_resource_words[1] = size - 1;
643 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) |
644 S_038008_STRIDE(stride) |
645 S_038008_DATA_FORMAT(format) |
646 S_038008_NUM_FORMAT_ALL(num_format) |
647 S_038008_FORMAT_COMP_ALL(format_comp) |
648 S_038008_ENDIAN_SWAP(endian);
649 view->tex_resource_words[3] = 0;
650 /*
651 * in theory dword 4 is for number of elements, for use with resinfo,
652 * but it seems to utterly fail to work, the amd gpu shader analyser
653 * uses a const buffer to store the element sizes for buffer txq
654 */
655 view->tex_resource_words[4] = 0;
656 view->tex_resource_words[5] = 0;
657 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
658 return &view->base;
659 }
660
661 struct pipe_sampler_view *
662 r600_create_sampler_view_custom(struct pipe_context *ctx,
663 struct pipe_resource *texture,
664 const struct pipe_sampler_view *state,
665 unsigned width_first_level, unsigned height_first_level)
666 {
667 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
668 struct r600_texture *tmp = (struct r600_texture*)texture;
669 unsigned format, endian;
670 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
671 unsigned char swizzle[4], array_mode = 0;
672 unsigned width, height, depth, offset_level, last_level;
673 bool do_endian_swap = FALSE;
674
675 if (!view)
676 return NULL;
677
678 /* initialize base object */
679 view->base = *state;
680 view->base.texture = NULL;
681 pipe_reference(NULL, &texture->reference);
682 view->base.texture = texture;
683 view->base.reference.count = 1;
684 view->base.context = ctx;
685
686 if (texture->target == PIPE_BUFFER)
687 return texture_buffer_sampler_view(view, texture->width0, 1);
688
689 swizzle[0] = state->swizzle_r;
690 swizzle[1] = state->swizzle_g;
691 swizzle[2] = state->swizzle_b;
692 swizzle[3] = state->swizzle_a;
693
694 if (R600_BIG_ENDIAN)
695 do_endian_swap = !tmp->db_compatible;
696
697 format = r600_translate_texformat(ctx->screen, state->format,
698 swizzle,
699 &word4, &yuv_format, do_endian_swap);
700 assert(format != ~0);
701 if (format == ~0) {
702 FREE(view);
703 return NULL;
704 }
705
706 if (state->format == PIPE_FORMAT_X24S8_UINT ||
707 state->format == PIPE_FORMAT_S8X24_UINT ||
708 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
709 state->format == PIPE_FORMAT_S8_UINT)
710 view->is_stencil_sampler = true;
711
712 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
713 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
714 FREE(view);
715 return NULL;
716 }
717 tmp = tmp->flushed_depth_texture;
718 }
719
720 endian = r600_colorformat_endian_swap(format, do_endian_swap);
721
722 offset_level = state->u.tex.first_level;
723 last_level = state->u.tex.last_level - offset_level;
724 width = width_first_level;
725 height = height_first_level;
726 depth = u_minify(texture->depth0, offset_level);
727 pitch = tmp->surface.u.legacy.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
728
729 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
730 height = 1;
731 depth = texture->array_size;
732 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
733 depth = texture->array_size;
734 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
735 depth = texture->array_size / 6;
736
737 switch (tmp->surface.u.legacy.level[offset_level].mode) {
738 default:
739 case RADEON_SURF_MODE_LINEAR_ALIGNED:
740 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
741 break;
742 case RADEON_SURF_MODE_1D:
743 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
744 break;
745 case RADEON_SURF_MODE_2D:
746 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
747 break;
748 }
749
750 view->tex_resource = &tmp->resource;
751 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
752 S_038000_TILE_MODE(array_mode) |
753 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
754 S_038000_PITCH((pitch / 8) - 1) |
755 S_038000_TEX_WIDTH(width - 1));
756 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
757 S_038004_TEX_DEPTH(depth - 1) |
758 S_038004_DATA_FORMAT(format));
759 view->tex_resource_words[2] = tmp->surface.u.legacy.level[offset_level].offset >> 8;
760 if (offset_level >= tmp->resource.b.b.last_level) {
761 view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level].offset >> 8;
762 } else {
763 view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level + 1].offset >> 8;
764 }
765 view->tex_resource_words[4] = (word4 |
766 S_038010_REQUEST_SIZE(1) |
767 S_038010_ENDIAN_SWAP(endian) |
768 S_038010_BASE_LEVEL(0));
769 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
770 S_038014_LAST_ARRAY(state->u.tex.last_layer));
771 if (texture->nr_samples > 1) {
772 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
773 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
774 } else {
775 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
776 }
777 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
778 S_038018_MAX_ANISO(4 /* max 16 samples */));
779 return &view->base;
780 }
781
782 static struct pipe_sampler_view *
783 r600_create_sampler_view(struct pipe_context *ctx,
784 struct pipe_resource *tex,
785 const struct pipe_sampler_view *state)
786 {
787 return r600_create_sampler_view_custom(ctx, tex, state,
788 u_minify(tex->width0, state->u.tex.first_level),
789 u_minify(tex->height0, state->u.tex.first_level));
790 }
791
792 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
793 {
794 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
795 struct pipe_clip_state *state = &rctx->clip_state.state;
796
797 radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
798 radeon_emit_array(cs, (unsigned*)state, 6*4);
799 }
800
801 static void r600_set_polygon_stipple(struct pipe_context *ctx,
802 const struct pipe_poly_stipple *state)
803 {
804 }
805
806 static void r600_init_color_surface(struct r600_context *rctx,
807 struct r600_surface *surf,
808 bool force_cmask_fmask)
809 {
810 struct r600_screen *rscreen = rctx->screen;
811 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
812 unsigned level = surf->base.u.tex.level;
813 unsigned pitch, slice;
814 unsigned color_info;
815 unsigned color_view;
816 unsigned format, swap, ntype, endian;
817 unsigned offset;
818 const struct util_format_description *desc;
819 int i;
820 bool blend_bypass = 0, blend_clamp = 1, do_endian_swap = FALSE;
821
822 if (rtex->db_compatible && !r600_can_sample_zs(rtex, false)) {
823 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
824 rtex = rtex->flushed_depth_texture;
825 assert(rtex);
826 }
827
828 offset = rtex->surface.u.legacy.level[level].offset;
829 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
830 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
831
832 pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1;
833 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
834 if (slice) {
835 slice = slice - 1;
836 }
837 color_info = 0;
838 switch (rtex->surface.u.legacy.level[level].mode) {
839 default:
840 case RADEON_SURF_MODE_LINEAR_ALIGNED:
841 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
842 break;
843 case RADEON_SURF_MODE_1D:
844 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
845 break;
846 case RADEON_SURF_MODE_2D:
847 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
848 break;
849 }
850
851 desc = util_format_description(surf->base.format);
852
853 for (i = 0; i < 4; i++) {
854 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
855 break;
856 }
857 }
858
859 ntype = V_0280A0_NUMBER_UNORM;
860 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
861 ntype = V_0280A0_NUMBER_SRGB;
862 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
863 if (desc->channel[i].normalized)
864 ntype = V_0280A0_NUMBER_SNORM;
865 else if (desc->channel[i].pure_integer)
866 ntype = V_0280A0_NUMBER_SINT;
867 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
868 if (desc->channel[i].normalized)
869 ntype = V_0280A0_NUMBER_UNORM;
870 else if (desc->channel[i].pure_integer)
871 ntype = V_0280A0_NUMBER_UINT;
872 }
873
874 if (R600_BIG_ENDIAN)
875 do_endian_swap = !rtex->db_compatible;
876
877 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format,
878 do_endian_swap);
879 assert(format != ~0);
880
881 swap = r600_translate_colorswap(surf->base.format, do_endian_swap);
882 assert(swap != ~0);
883
884 endian = r600_colorformat_endian_swap(format, do_endian_swap);
885
886 /* set blend bypass according to docs if SINT/UINT or
887 8/24 COLOR variants */
888 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
889 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
890 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
891 blend_clamp = 0;
892 blend_bypass = 1;
893 }
894
895 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
896
897 color_info |= S_0280A0_FORMAT(format) |
898 S_0280A0_COMP_SWAP(swap) |
899 S_0280A0_BLEND_BYPASS(blend_bypass) |
900 S_0280A0_BLEND_CLAMP(blend_clamp) |
901 S_0280A0_NUMBER_TYPE(ntype) |
902 S_0280A0_ENDIAN(endian);
903
904 /* EXPORT_NORM is an optimzation that can be enabled for better
905 * performance in certain cases
906 */
907 if (rctx->b.chip_class == R600) {
908 /* EXPORT_NORM can be enabled if:
909 * - 11-bit or smaller UNORM/SNORM/SRGB
910 * - BLEND_CLAMP is enabled
911 * - BLEND_FLOAT32 is disabled
912 */
913 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
914 (desc->channel[i].size < 12 &&
915 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
916 ntype != V_0280A0_NUMBER_UINT &&
917 ntype != V_0280A0_NUMBER_SINT) &&
918 G_0280A0_BLEND_CLAMP(color_info) &&
919 !G_0280A0_BLEND_FLOAT32(color_info)) {
920 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
921 surf->export_16bpc = true;
922 }
923 } else {
924 /* EXPORT_NORM can be enabled if:
925 * - 11-bit or smaller UNORM/SNORM/SRGB
926 * - 16-bit or smaller FLOAT
927 */
928 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
929 ((desc->channel[i].size < 12 &&
930 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
931 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
932 (desc->channel[i].size < 17 &&
933 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
934 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
935 surf->export_16bpc = true;
936 }
937 }
938
939 /* These might not always be initialized to zero. */
940 surf->cb_color_base = offset >> 8;
941 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
942 S_028060_SLICE_TILE_MAX(slice);
943 surf->cb_color_fmask = surf->cb_color_base;
944 surf->cb_color_cmask = surf->cb_color_base;
945 surf->cb_color_mask = 0;
946
947 r600_resource_reference(&surf->cb_buffer_cmask, &rtex->resource);
948 r600_resource_reference(&surf->cb_buffer_fmask, &rtex->resource);
949
950 if (rtex->cmask.size) {
951 surf->cb_color_cmask = rtex->cmask.offset >> 8;
952 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
953
954 if (rtex->fmask.size) {
955 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
956 surf->cb_color_fmask = rtex->fmask.offset >> 8;
957 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
958 } else { /* cmask only */
959 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
960 }
961 } else if (force_cmask_fmask) {
962 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
963 *
964 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
965 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
966 * because it's not an MSAA buffer.
967 */
968 struct r600_cmask_info cmask;
969 struct r600_fmask_info fmask;
970
971 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
972 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
973
974 /* CMASK. */
975 if (!rctx->dummy_cmask ||
976 rctx->dummy_cmask->b.b.width0 < cmask.size ||
977 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
978 struct pipe_transfer *transfer;
979 void *ptr;
980
981 r600_resource_reference(&rctx->dummy_cmask, NULL);
982 rctx->dummy_cmask = (struct r600_resource*)
983 r600_aligned_buffer_create(&rscreen->b.b, 0,
984 PIPE_USAGE_DEFAULT,
985 cmask.size, cmask.alignment);
986
987 if (unlikely(!rctx->dummy_cmask)) {
988 surf->color_initialized = false;
989 return;
990 }
991
992 /* Set the contents to 0xCC. */
993 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
994 memset(ptr, 0xCC, cmask.size);
995 pipe_buffer_unmap(&rctx->b.b, transfer);
996 }
997 r600_resource_reference(&surf->cb_buffer_cmask, rctx->dummy_cmask);
998
999 /* FMASK. */
1000 if (!rctx->dummy_fmask ||
1001 rctx->dummy_fmask->b.b.width0 < fmask.size ||
1002 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1003 r600_resource_reference(&rctx->dummy_fmask, NULL);
1004 rctx->dummy_fmask = (struct r600_resource*)
1005 r600_aligned_buffer_create(&rscreen->b.b, 0,
1006 PIPE_USAGE_DEFAULT,
1007 fmask.size, fmask.alignment);
1008
1009 if (unlikely(!rctx->dummy_fmask)) {
1010 surf->color_initialized = false;
1011 return;
1012 }
1013 }
1014 r600_resource_reference(&surf->cb_buffer_fmask, rctx->dummy_fmask);
1015
1016 /* Init the registers. */
1017 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1018 surf->cb_color_cmask = 0;
1019 surf->cb_color_fmask = 0;
1020 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1021 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1022 }
1023
1024 surf->cb_color_info = color_info;
1025 surf->cb_color_view = color_view;
1026 surf->color_initialized = true;
1027 }
1028
1029 static void r600_init_depth_surface(struct r600_context *rctx,
1030 struct r600_surface *surf)
1031 {
1032 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1033 unsigned level, pitch, slice, format, offset, array_mode;
1034
1035 level = surf->base.u.tex.level;
1036 offset = rtex->surface.u.legacy.level[level].offset;
1037 pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1;
1038 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
1039 if (slice) {
1040 slice = slice - 1;
1041 }
1042 switch (rtex->surface.u.legacy.level[level].mode) {
1043 case RADEON_SURF_MODE_2D:
1044 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1045 break;
1046 case RADEON_SURF_MODE_1D:
1047 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1048 default:
1049 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1050 break;
1051 }
1052
1053 format = r600_translate_dbformat(surf->base.format);
1054 assert(format != ~0);
1055
1056 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1057 surf->db_depth_base = offset >> 8;
1058 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1059 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1060 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1061 surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1;
1062
1063 /* use htile only for first level */
1064 if (rtex->htile_buffer && !level) {
1065 surf->db_htile_data_base = 0;
1066 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1067 S_028D24_HTILE_HEIGHT(1) |
1068 S_028D24_FULL_CACHE(1);
1069 /* preload is not working properly on r6xx/r7xx */
1070 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1071 }
1072
1073 surf->depth_initialized = true;
1074 }
1075
1076 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1077 const struct pipe_framebuffer_state *state)
1078 {
1079 struct r600_context *rctx = (struct r600_context *)ctx;
1080 struct r600_surface *surf;
1081 struct r600_texture *rtex;
1082 unsigned i;
1083
1084 /* Flush TC when changing the framebuffer state, because the only
1085 * client not using TC that can change textures is the framebuffer.
1086 * Other places don't typically have to flush TC.
1087 */
1088 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1089 R600_CONTEXT_FLUSH_AND_INV |
1090 R600_CONTEXT_FLUSH_AND_INV_CB |
1091 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1092 R600_CONTEXT_FLUSH_AND_INV_DB |
1093 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1094 R600_CONTEXT_INV_TEX_CACHE;
1095
1096 /* Set the new state. */
1097 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1098
1099 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1100 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1101 util_format_is_pure_integer(state->cbufs[0]->format);
1102 rctx->framebuffer.compressed_cb_mask = 0;
1103 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1104 state->cbufs[0] && state->cbufs[1] &&
1105 state->cbufs[0]->texture->nr_samples > 1 &&
1106 state->cbufs[1]->texture->nr_samples <= 1;
1107 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1108
1109 /* Colorbuffers. */
1110 for (i = 0; i < state->nr_cbufs; i++) {
1111 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1112 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1113 rctx->framebuffer.is_msaa_resolve &&
1114 i == 1;
1115
1116 surf = (struct r600_surface*)state->cbufs[i];
1117 if (!surf)
1118 continue;
1119
1120 rtex = (struct r600_texture*)surf->base.texture;
1121 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1122
1123 if (!surf->color_initialized || force_cmask_fmask) {
1124 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1125 if (force_cmask_fmask) {
1126 /* re-initialize later without compression */
1127 surf->color_initialized = false;
1128 }
1129 }
1130
1131 if (!surf->export_16bpc) {
1132 rctx->framebuffer.export_16bpc = false;
1133 }
1134
1135 if (rtex->fmask.size) {
1136 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1137 }
1138 }
1139
1140 /* Update alpha-test state dependencies.
1141 * Alpha-test is done on the first colorbuffer only. */
1142 if (state->nr_cbufs) {
1143 bool alphatest_bypass = false;
1144
1145 surf = (struct r600_surface*)state->cbufs[0];
1146 if (surf) {
1147 alphatest_bypass = surf->alphatest_bypass;
1148 }
1149
1150 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1151 rctx->alphatest_state.bypass = alphatest_bypass;
1152 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1153 }
1154 }
1155
1156 /* ZS buffer. */
1157 if (state->zsbuf) {
1158 surf = (struct r600_surface*)state->zsbuf;
1159
1160 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1161
1162 if (!surf->depth_initialized) {
1163 r600_init_depth_surface(rctx, surf);
1164 }
1165
1166 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1167 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1168 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1169 }
1170
1171 if (rctx->db_state.rsurf != surf) {
1172 rctx->db_state.rsurf = surf;
1173 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1174 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1175 }
1176 } else if (rctx->db_state.rsurf) {
1177 rctx->db_state.rsurf = NULL;
1178 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1179 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1180 }
1181
1182 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1183 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1184 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1185 }
1186
1187 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1188 rctx->alphatest_state.bypass = false;
1189 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1190 }
1191
1192 /* Calculate the CS size. */
1193 rctx->framebuffer.atom.num_dw =
1194 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1195
1196 if (rctx->framebuffer.state.nr_cbufs) {
1197 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1198 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1199 }
1200 if (rctx->framebuffer.state.zsbuf) {
1201 rctx->framebuffer.atom.num_dw += 16;
1202 } else if (rctx->screen->b.info.drm_minor >= 18) {
1203 rctx->framebuffer.atom.num_dw += 3;
1204 }
1205 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1206 rctx->framebuffer.atom.num_dw += 2;
1207 }
1208
1209 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1210
1211 r600_set_sample_locations_constant_buffer(rctx);
1212 }
1213
1214 static uint32_t sample_locs_2x[] = {
1215 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1216 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1217 };
1218 static unsigned max_dist_2x = 4;
1219
1220 static uint32_t sample_locs_4x[] = {
1221 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1222 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1223 };
1224 static unsigned max_dist_4x = 6;
1225 static uint32_t sample_locs_8x[] = {
1226 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1227 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1228 };
1229 static unsigned max_dist_8x = 7;
1230
1231 static void r600_get_sample_position(struct pipe_context *ctx,
1232 unsigned sample_count,
1233 unsigned sample_index,
1234 float *out_value)
1235 {
1236 int offset, index;
1237 struct {
1238 int idx:4;
1239 } val;
1240 switch (sample_count) {
1241 case 1:
1242 default:
1243 out_value[0] = out_value[1] = 0.5;
1244 break;
1245 case 2:
1246 offset = 4 * (sample_index * 2);
1247 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1248 out_value[0] = (float)(val.idx + 8) / 16.0f;
1249 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1250 out_value[1] = (float)(val.idx + 8) / 16.0f;
1251 break;
1252 case 4:
1253 offset = 4 * (sample_index * 2);
1254 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1255 out_value[0] = (float)(val.idx + 8) / 16.0f;
1256 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1257 out_value[1] = (float)(val.idx + 8) / 16.0f;
1258 break;
1259 case 8:
1260 offset = 4 * (sample_index % 4 * 2);
1261 index = (sample_index / 4);
1262 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1263 out_value[0] = (float)(val.idx + 8) / 16.0f;
1264 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1265 out_value[1] = (float)(val.idx + 8) / 16.0f;
1266 break;
1267 }
1268 }
1269
1270 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1271 {
1272 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1273 unsigned max_dist = 0;
1274
1275 if (rctx->b.family == CHIP_R600) {
1276 switch (nr_samples) {
1277 default:
1278 nr_samples = 0;
1279 break;
1280 case 2:
1281 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1282 max_dist = max_dist_2x;
1283 break;
1284 case 4:
1285 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1286 max_dist = max_dist_4x;
1287 break;
1288 case 8:
1289 radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1290 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1291 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1292 max_dist = max_dist_8x;
1293 break;
1294 }
1295 } else {
1296 switch (nr_samples) {
1297 default:
1298 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1299 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1300 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1301 nr_samples = 0;
1302 break;
1303 case 2:
1304 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1305 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1306 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1307 max_dist = max_dist_2x;
1308 break;
1309 case 4:
1310 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1311 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1312 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1313 max_dist = max_dist_4x;
1314 break;
1315 case 8:
1316 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1317 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1318 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1319 max_dist = max_dist_8x;
1320 break;
1321 }
1322 }
1323
1324 if (nr_samples > 1) {
1325 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1326 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1327 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1328 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1329 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1330 } else {
1331 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1332 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1333 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1334 }
1335 }
1336
1337 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1338 {
1339 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1340 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1341 unsigned nr_cbufs = state->nr_cbufs;
1342 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1343 unsigned i, sbu = 0;
1344
1345 /* Colorbuffers. */
1346 radeon_set_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1347 for (i = 0; i < nr_cbufs; i++) {
1348 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1349 }
1350 /* set CB_COLOR1_INFO for possible dual-src blending */
1351 if (rctx->framebuffer.dual_src_blend && i == 1 && cb[0]) {
1352 radeon_emit(cs, cb[0]->cb_color_info);
1353 i++;
1354 }
1355 for (; i < 8; i++) {
1356 radeon_emit(cs, 0);
1357 }
1358
1359 if (nr_cbufs) {
1360 for (i = 0; i < nr_cbufs; i++) {
1361 unsigned reloc;
1362
1363 if (!cb[i])
1364 continue;
1365
1366 /* COLOR_BASE */
1367 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1368
1369 reloc = radeon_add_to_buffer_list(&rctx->b,
1370 &rctx->b.gfx,
1371 (struct r600_resource*)cb[i]->base.texture,
1372 RADEON_USAGE_READWRITE,
1373 cb[i]->base.texture->nr_samples > 1 ?
1374 RADEON_PRIO_COLOR_BUFFER_MSAA :
1375 RADEON_PRIO_COLOR_BUFFER);
1376 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1377 radeon_emit(cs, reloc);
1378
1379 /* FMASK */
1380 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1381
1382 reloc = radeon_add_to_buffer_list(&rctx->b,
1383 &rctx->b.gfx,
1384 cb[i]->cb_buffer_fmask,
1385 RADEON_USAGE_READWRITE,
1386 cb[i]->base.texture->nr_samples > 1 ?
1387 RADEON_PRIO_COLOR_BUFFER_MSAA :
1388 RADEON_PRIO_COLOR_BUFFER);
1389 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1390 radeon_emit(cs, reloc);
1391
1392 /* CMASK */
1393 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1394
1395 reloc = radeon_add_to_buffer_list(&rctx->b,
1396 &rctx->b.gfx,
1397 cb[i]->cb_buffer_cmask,
1398 RADEON_USAGE_READWRITE,
1399 cb[i]->base.texture->nr_samples > 1 ?
1400 RADEON_PRIO_COLOR_BUFFER_MSAA :
1401 RADEON_PRIO_COLOR_BUFFER);
1402 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1403 radeon_emit(cs, reloc);
1404 }
1405
1406 radeon_set_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1407 for (i = 0; i < nr_cbufs; i++) {
1408 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1409 }
1410
1411 radeon_set_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1412 for (i = 0; i < nr_cbufs; i++) {
1413 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1414 }
1415
1416 radeon_set_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1417 for (i = 0; i < nr_cbufs; i++) {
1418 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1419 }
1420
1421 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1422 }
1423
1424 /* SURFACE_BASE_UPDATE */
1425 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1426 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1427 radeon_emit(cs, sbu);
1428 sbu = 0;
1429 }
1430
1431 /* Zbuffer. */
1432 if (state->zsbuf) {
1433 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1434 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1435 &rctx->b.gfx,
1436 (struct r600_resource*)state->zsbuf->texture,
1437 RADEON_USAGE_READWRITE,
1438 surf->base.texture->nr_samples > 1 ?
1439 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1440 RADEON_PRIO_DEPTH_BUFFER);
1441
1442 radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1443 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1444 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1445 radeon_set_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1446 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1447 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1448
1449 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1450 radeon_emit(cs, reloc);
1451
1452 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1453
1454 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1455 } else if (rctx->screen->b.info.drm_minor >= 18) {
1456 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1457 * Older kernels are out of luck. */
1458 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1459 }
1460
1461 /* SURFACE_BASE_UPDATE */
1462 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1463 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1464 radeon_emit(cs, sbu);
1465 sbu = 0;
1466 }
1467
1468 /* Framebuffer dimensions. */
1469 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1470 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1471 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1472 radeon_emit(cs, S_028244_BR_X(state->width) |
1473 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1474
1475 if (rctx->framebuffer.is_msaa_resolve) {
1476 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1477 } else {
1478 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1479 * will assure that the alpha-test will work even if there is
1480 * no colorbuffer bound. */
1481 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1482 (1ull << MAX2(nr_cbufs, 1)) - 1);
1483 }
1484
1485 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1486 }
1487
1488 static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1489 {
1490 struct r600_context *rctx = (struct r600_context *)ctx;
1491
1492 if (rctx->ps_iter_samples == min_samples)
1493 return;
1494
1495 rctx->ps_iter_samples = min_samples;
1496 if (rctx->framebuffer.nr_samples > 1) {
1497 r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom);
1498 if (rctx->b.chip_class == R600)
1499 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1500 }
1501 }
1502
1503 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1504 {
1505 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1506 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1507
1508 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1509 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1510 if (rctx->b.chip_class == R600) {
1511 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1512 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1513 } else {
1514 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1515 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1516 }
1517 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1518 } else {
1519 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1520 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1521 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1522
1523 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1524 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1525 /* Always enable the first color output to make sure alpha-test works even without one. */
1526 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1527 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1528 a->cb_color_control |
1529 S_028808_MULTIWRITE_ENABLE(multiwrite));
1530 }
1531 }
1532
1533 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1534 {
1535 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1536 struct r600_db_state *a = (struct r600_db_state*)atom;
1537
1538 if (a->rsurf && a->rsurf->db_htile_surface) {
1539 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1540 unsigned reloc_idx;
1541
1542 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1543 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1544 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1545 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1546 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1547 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1548 radeon_emit(cs, reloc_idx);
1549 } else {
1550 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1551 }
1552 }
1553
1554 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1555 {
1556 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1557 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1558 unsigned db_render_control = 0;
1559 unsigned db_render_override =
1560 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1561 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1562
1563 if (rctx->b.chip_class >= R700) {
1564 switch (a->ps_conservative_z) {
1565 default: /* fall through */
1566 case TGSI_FS_DEPTH_LAYOUT_ANY:
1567 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_ANY_Z);
1568 break;
1569 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1570 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_GREATER_THAN_Z);
1571 break;
1572 case TGSI_FS_DEPTH_LAYOUT_LESS:
1573 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_LESS_THAN_Z);
1574 break;
1575 }
1576 }
1577
1578 if (rctx->b.num_occlusion_queries > 0 &&
1579 !a->occlusion_queries_disabled) {
1580 if (rctx->b.chip_class >= R700) {
1581 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1582 }
1583 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1584 } else {
1585 db_render_control |= S_028D0C_ZPASS_INCREMENT_DISABLE(1);
1586 }
1587
1588 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1589 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1590 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1591 /* This is to fix a lockup when hyperz and alpha test are enabled at
1592 * the same time somehow GPU get confuse on which order to pick for
1593 * z test
1594 */
1595 if (rctx->alphatest_state.sx_alpha_test_control) {
1596 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1597 }
1598 } else {
1599 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1600 }
1601 if (rctx->b.chip_class == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) {
1602 /* sample shading and hyperz causes lockups on R6xx chips */
1603 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1604 }
1605 if (a->flush_depthstencil_through_cb) {
1606 assert(a->copy_depth || a->copy_stencil);
1607
1608 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1609 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1610 S_028D0C_COPY_CENTROID(1) |
1611 S_028D0C_COPY_SAMPLE(a->copy_sample);
1612
1613 if (rctx->b.chip_class == R600)
1614 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1615
1616 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
1617 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
1618 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1619 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1620 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1621 S_028D0C_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1622 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1623 }
1624 if (a->htile_clear) {
1625 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1626 }
1627
1628 /* RV770 workaround for a hang with 8x MSAA. */
1629 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1630 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
1631 }
1632
1633 radeon_set_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1634 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1635 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1636 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1637 }
1638
1639 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1640 {
1641 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1642 struct r600_config_state *a = (struct r600_config_state*)atom;
1643
1644 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1645 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1646 }
1647
1648 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1649 {
1650 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1651 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1652
1653 while (dirty_mask) {
1654 struct pipe_vertex_buffer *vb;
1655 struct r600_resource *rbuffer;
1656 unsigned offset;
1657 unsigned buffer_index = u_bit_scan(&dirty_mask);
1658
1659 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1660 rbuffer = (struct r600_resource*)vb->buffer;
1661 assert(rbuffer);
1662
1663 offset = vb->buffer_offset;
1664
1665 /* fetch resources start at index 320 (OFFSET_FS) */
1666 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1667 radeon_emit(cs, (R600_FETCH_CONSTANTS_OFFSET_FS + buffer_index) * 7);
1668 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1669 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1670 radeon_emit(cs, /* RESOURCEi_WORD2 */
1671 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1672 S_038008_STRIDE(vb->stride));
1673 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1674 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1675 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1676 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1677
1678 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1679 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1680 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1681 }
1682 }
1683
1684 static void r600_emit_constant_buffers(struct r600_context *rctx,
1685 struct r600_constbuf_state *state,
1686 unsigned buffer_id_base,
1687 unsigned reg_alu_constbuf_size,
1688 unsigned reg_alu_const_cache)
1689 {
1690 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1691 uint32_t dirty_mask = state->dirty_mask;
1692
1693 while (dirty_mask) {
1694 struct pipe_constant_buffer *cb;
1695 struct r600_resource *rbuffer;
1696 unsigned offset;
1697 unsigned buffer_index = ffs(dirty_mask) - 1;
1698 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1699 cb = &state->cb[buffer_index];
1700 rbuffer = (struct r600_resource*)cb->buffer;
1701 assert(rbuffer);
1702
1703 offset = cb->buffer_offset;
1704
1705 if (!gs_ring_buffer) {
1706 radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1707 DIV_ROUND_UP(cb->buffer_size, 256));
1708 radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1709 }
1710
1711 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1712 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1713 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1714
1715 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1716 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1717 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1718 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1719 radeon_emit(cs, /* RESOURCEi_WORD2 */
1720 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1721 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1722 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1723 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1724 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1725 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1726
1727 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1728 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1729 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1730
1731 dirty_mask &= ~(1 << buffer_index);
1732 }
1733 state->dirty_mask = 0;
1734 }
1735
1736 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1737 {
1738 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1739 R600_FETCH_CONSTANTS_OFFSET_VS,
1740 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1741 R_028980_ALU_CONST_CACHE_VS_0);
1742 }
1743
1744 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1745 {
1746 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1747 R600_FETCH_CONSTANTS_OFFSET_GS,
1748 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1749 R_0289C0_ALU_CONST_CACHE_GS_0);
1750 }
1751
1752 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1753 {
1754 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1755 R600_FETCH_CONSTANTS_OFFSET_PS,
1756 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1757 R_028940_ALU_CONST_CACHE_PS_0);
1758 }
1759
1760 static void r600_emit_sampler_views(struct r600_context *rctx,
1761 struct r600_samplerview_state *state,
1762 unsigned resource_id_base)
1763 {
1764 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1765 uint32_t dirty_mask = state->dirty_mask;
1766
1767 while (dirty_mask) {
1768 struct r600_pipe_sampler_view *rview;
1769 unsigned resource_index = u_bit_scan(&dirty_mask);
1770 unsigned reloc;
1771
1772 rview = state->views[resource_index];
1773 assert(rview);
1774
1775 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1776 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1777 radeon_emit_array(cs, rview->tex_resource_words, 7);
1778
1779 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
1780 RADEON_USAGE_READ,
1781 r600_get_sampler_view_priority(rview->tex_resource));
1782 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1783 radeon_emit(cs, reloc);
1784 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1785 radeon_emit(cs, reloc);
1786 }
1787 state->dirty_mask = 0;
1788 }
1789
1790
1791 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1792 {
1793 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, R600_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS);
1794 }
1795
1796 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1797 {
1798 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, R600_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS);
1799 }
1800
1801 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1802 {
1803 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS);
1804 }
1805
1806 static void r600_emit_sampler_states(struct r600_context *rctx,
1807 struct r600_textures_info *texinfo,
1808 unsigned resource_id_base,
1809 unsigned border_color_reg)
1810 {
1811 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1812 uint32_t dirty_mask = texinfo->states.dirty_mask;
1813
1814 while (dirty_mask) {
1815 struct r600_pipe_sampler_state *rstate;
1816 struct r600_pipe_sampler_view *rview;
1817 unsigned i = u_bit_scan(&dirty_mask);
1818
1819 rstate = texinfo->states.states[i];
1820 assert(rstate);
1821 rview = texinfo->views.views[i];
1822
1823 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1824 * filtering between layers.
1825 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1826 */
1827 if (rview) {
1828 enum pipe_texture_target target = rview->base.texture->target;
1829 if (target == PIPE_TEXTURE_1D_ARRAY ||
1830 target == PIPE_TEXTURE_2D_ARRAY) {
1831 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1832 texinfo->is_array_sampler[i] = true;
1833 } else {
1834 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1835 texinfo->is_array_sampler[i] = false;
1836 }
1837 }
1838
1839 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1840 radeon_emit(cs, (resource_id_base + i) * 3);
1841 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1842
1843 if (rstate->border_color_use) {
1844 unsigned offset;
1845
1846 offset = border_color_reg;
1847 offset += i * 16;
1848 radeon_set_config_reg_seq(cs, offset, 4);
1849 radeon_emit_array(cs, rstate->border_color.ui, 4);
1850 }
1851 }
1852 texinfo->states.dirty_mask = 0;
1853 }
1854
1855 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1856 {
1857 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1858 }
1859
1860 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1861 {
1862 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1863 }
1864
1865 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1866 {
1867 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1868 }
1869
1870 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1871 {
1872 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1873 unsigned tmp;
1874
1875 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1876 S_009508_SYNC_GRADIENT(1) |
1877 S_009508_SYNC_WALKER(1) |
1878 S_009508_SYNC_ALIGNER(1);
1879 if (!rctx->seamless_cube_map.enabled) {
1880 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1881 }
1882 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1883 }
1884
1885 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1886 {
1887 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1888 uint8_t mask = s->sample_mask;
1889
1890 radeon_set_context_reg(rctx->b.gfx.cs, R_028C48_PA_SC_AA_MASK,
1891 mask | (mask << 8) | (mask << 16) | (mask << 24));
1892 }
1893
1894 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1895 {
1896 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1897 struct r600_cso_state *state = (struct r600_cso_state*)a;
1898 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1899
1900 radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1901 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1902 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
1903 RADEON_USAGE_READ,
1904 RADEON_PRIO_SHADER_BINARY));
1905 }
1906
1907 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1908 {
1909 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1910 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1911
1912 uint32_t v2 = 0, primid = 0;
1913
1914 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
1915 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1916 primid = 1;
1917 }
1918
1919 if (state->geom_enable) {
1920 uint32_t cut_val;
1921
1922 if (rctx->gs_shader->gs_max_out_vertices <= 128)
1923 cut_val = V_028A40_GS_CUT_128;
1924 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
1925 cut_val = V_028A40_GS_CUT_256;
1926 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
1927 cut_val = V_028A40_GS_CUT_512;
1928 else
1929 cut_val = V_028A40_GS_CUT_1024;
1930
1931 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1932 S_028A40_CUT_MODE(cut_val);
1933
1934 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1935 primid = 1;
1936 }
1937
1938 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1939 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
1940 }
1941
1942 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1943 {
1944 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1945 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
1946 struct r600_resource *rbuffer;
1947
1948 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1949 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1950 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1951
1952 if (state->enable) {
1953 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
1954 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
1955 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1956 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1957 RADEON_USAGE_READWRITE,
1958 RADEON_PRIO_SHADER_RINGS));
1959 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1960 state->esgs_ring.buffer_size >> 8);
1961
1962 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
1963 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
1964 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1965 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1966 RADEON_USAGE_READWRITE,
1967 RADEON_PRIO_SHADER_RINGS));
1968 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
1969 state->gsvs_ring.buffer_size >> 8);
1970 } else {
1971 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
1972 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
1973 }
1974
1975 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1976 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1977 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1978 }
1979
1980 /* Adjust GPR allocation on R6xx/R7xx */
1981 bool r600_adjust_gprs(struct r600_context *rctx)
1982 {
1983 unsigned num_gprs[R600_NUM_HW_STAGES];
1984 unsigned new_gprs[R600_NUM_HW_STAGES];
1985 unsigned cur_gprs[R600_NUM_HW_STAGES];
1986 unsigned def_gprs[R600_NUM_HW_STAGES];
1987 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
1988 unsigned max_gprs;
1989 unsigned tmp, tmp2;
1990 unsigned i;
1991 bool need_recalc = false, use_default = true;
1992
1993 /* hardware will reserve twice num_clause_temp_gprs */
1994 max_gprs = def_num_clause_temp_gprs * 2;
1995 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
1996 def_gprs[i] = rctx->default_gprs[i];
1997 max_gprs += def_gprs[i];
1998 }
1999
2000 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2001 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2002 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2003 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2004
2005 num_gprs[R600_HW_STAGE_PS] = rctx->ps_shader->current->shader.bc.ngpr;
2006 if (rctx->gs_shader) {
2007 num_gprs[R600_HW_STAGE_ES] = rctx->vs_shader->current->shader.bc.ngpr;
2008 num_gprs[R600_HW_STAGE_GS] = rctx->gs_shader->current->shader.bc.ngpr;
2009 num_gprs[R600_HW_STAGE_VS] = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2010 } else {
2011 num_gprs[R600_HW_STAGE_ES] = 0;
2012 num_gprs[R600_HW_STAGE_GS] = 0;
2013 num_gprs[R600_HW_STAGE_VS] = rctx->vs_shader->current->shader.bc.ngpr;
2014 }
2015
2016 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2017 new_gprs[i] = num_gprs[i];
2018 if (new_gprs[i] > cur_gprs[i])
2019 need_recalc = true;
2020 if (new_gprs[i] > def_gprs[i])
2021 use_default = false;
2022 }
2023
2024 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2025 if (!need_recalc)
2026 return true;
2027
2028 /* try to use switch back to default */
2029 if (!use_default) {
2030 /* always privilege vs stage so that at worst we have the
2031 * pixel stage producing wrong output (not the vertex
2032 * stage) */
2033 new_gprs[R600_HW_STAGE_PS] = max_gprs - def_num_clause_temp_gprs * 2;
2034 for (i = R600_HW_STAGE_VS; i < R600_NUM_HW_STAGES; i++)
2035 new_gprs[R600_HW_STAGE_PS] -= new_gprs[i];
2036 } else {
2037 for (i = 0; i < R600_NUM_HW_STAGES; i++)
2038 new_gprs[i] = def_gprs[i];
2039 }
2040
2041 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2042 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2043 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2044 * it will lockup. So in this case just discard the draw command
2045 * and don't change the current gprs repartitions.
2046 */
2047 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2048 if (num_gprs[i] > new_gprs[i]) {
2049 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2050 "for a combined maximum of %d\n",
2051 num_gprs[R600_HW_STAGE_PS], num_gprs[R600_HW_STAGE_VS], num_gprs[R600_HW_STAGE_ES], num_gprs[R600_HW_STAGE_GS], max_gprs);
2052 return false;
2053 }
2054 }
2055
2056 /* in some case we endup recomputing the current value */
2057 tmp = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
2058 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
2059 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2060
2061 tmp2 = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
2062 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
2063 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2064 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2065 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2066 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
2067 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2068 }
2069 return true;
2070 }
2071
2072 void r600_init_atom_start_cs(struct r600_context *rctx)
2073 {
2074 int ps_prio;
2075 int vs_prio;
2076 int gs_prio;
2077 int es_prio;
2078 int num_ps_gprs;
2079 int num_vs_gprs;
2080 int num_gs_gprs;
2081 int num_es_gprs;
2082 int num_temp_gprs;
2083 int num_ps_threads;
2084 int num_vs_threads;
2085 int num_gs_threads;
2086 int num_es_threads;
2087 int num_ps_stack_entries;
2088 int num_vs_stack_entries;
2089 int num_gs_stack_entries;
2090 int num_es_stack_entries;
2091 enum radeon_family family;
2092 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2093 uint32_t tmp, i;
2094
2095 r600_init_command_buffer(cb, 256);
2096
2097 /* R6xx requires this packet at the start of each command buffer */
2098 if (rctx->b.chip_class == R600) {
2099 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2100 r600_store_value(cb, 0);
2101 }
2102 /* All asics require this one */
2103 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2104 r600_store_value(cb, 0x80000000);
2105 r600_store_value(cb, 0x80000000);
2106
2107 /* We're setting config registers here. */
2108 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2109 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2110
2111 /* This enables pipeline stat & streamout queries.
2112 * They are only disabled by blits.
2113 */
2114 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2115 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2116
2117 family = rctx->b.family;
2118 ps_prio = 0;
2119 vs_prio = 1;
2120 gs_prio = 2;
2121 es_prio = 3;
2122 switch (family) {
2123 case CHIP_R600:
2124 num_ps_gprs = 192;
2125 num_vs_gprs = 56;
2126 num_temp_gprs = 4;
2127 num_gs_gprs = 0;
2128 num_es_gprs = 0;
2129 num_ps_threads = 136;
2130 num_vs_threads = 48;
2131 num_gs_threads = 4;
2132 num_es_threads = 4;
2133 num_ps_stack_entries = 128;
2134 num_vs_stack_entries = 128;
2135 num_gs_stack_entries = 0;
2136 num_es_stack_entries = 0;
2137 break;
2138 case CHIP_RV630:
2139 case CHIP_RV635:
2140 num_ps_gprs = 84;
2141 num_vs_gprs = 36;
2142 num_temp_gprs = 4;
2143 num_gs_gprs = 0;
2144 num_es_gprs = 0;
2145 num_ps_threads = 144;
2146 num_vs_threads = 40;
2147 num_gs_threads = 4;
2148 num_es_threads = 4;
2149 num_ps_stack_entries = 40;
2150 num_vs_stack_entries = 40;
2151 num_gs_stack_entries = 32;
2152 num_es_stack_entries = 16;
2153 break;
2154 case CHIP_RV610:
2155 case CHIP_RV620:
2156 case CHIP_RS780:
2157 case CHIP_RS880:
2158 default:
2159 num_ps_gprs = 84;
2160 num_vs_gprs = 36;
2161 num_temp_gprs = 4;
2162 num_gs_gprs = 0;
2163 num_es_gprs = 0;
2164 /* use limits 40 VS and at least 16 ES/GS */
2165 num_ps_threads = 120;
2166 num_vs_threads = 40;
2167 num_gs_threads = 16;
2168 num_es_threads = 16;
2169 num_ps_stack_entries = 40;
2170 num_vs_stack_entries = 40;
2171 num_gs_stack_entries = 32;
2172 num_es_stack_entries = 16;
2173 break;
2174 case CHIP_RV670:
2175 num_ps_gprs = 144;
2176 num_vs_gprs = 40;
2177 num_temp_gprs = 4;
2178 num_gs_gprs = 0;
2179 num_es_gprs = 0;
2180 num_ps_threads = 136;
2181 num_vs_threads = 48;
2182 num_gs_threads = 4;
2183 num_es_threads = 4;
2184 num_ps_stack_entries = 40;
2185 num_vs_stack_entries = 40;
2186 num_gs_stack_entries = 32;
2187 num_es_stack_entries = 16;
2188 break;
2189 case CHIP_RV770:
2190 num_ps_gprs = 130;
2191 num_vs_gprs = 56;
2192 num_temp_gprs = 4;
2193 num_gs_gprs = 31;
2194 num_es_gprs = 31;
2195 num_ps_threads = 180;
2196 num_vs_threads = 60;
2197 num_gs_threads = 4;
2198 num_es_threads = 4;
2199 num_ps_stack_entries = 128;
2200 num_vs_stack_entries = 128;
2201 num_gs_stack_entries = 128;
2202 num_es_stack_entries = 128;
2203 break;
2204 case CHIP_RV730:
2205 case CHIP_RV740:
2206 num_ps_gprs = 84;
2207 num_vs_gprs = 36;
2208 num_temp_gprs = 4;
2209 num_gs_gprs = 0;
2210 num_es_gprs = 0;
2211 num_ps_threads = 180;
2212 num_vs_threads = 60;
2213 num_gs_threads = 4;
2214 num_es_threads = 4;
2215 num_ps_stack_entries = 128;
2216 num_vs_stack_entries = 128;
2217 num_gs_stack_entries = 0;
2218 num_es_stack_entries = 0;
2219 break;
2220 case CHIP_RV710:
2221 num_ps_gprs = 192;
2222 num_vs_gprs = 56;
2223 num_temp_gprs = 4;
2224 num_gs_gprs = 0;
2225 num_es_gprs = 0;
2226 num_ps_threads = 136;
2227 num_vs_threads = 48;
2228 num_gs_threads = 4;
2229 num_es_threads = 4;
2230 num_ps_stack_entries = 128;
2231 num_vs_stack_entries = 128;
2232 num_gs_stack_entries = 0;
2233 num_es_stack_entries = 0;
2234 break;
2235 }
2236
2237 rctx->default_gprs[R600_HW_STAGE_PS] = num_ps_gprs;
2238 rctx->default_gprs[R600_HW_STAGE_VS] = num_vs_gprs;
2239 rctx->default_gprs[R600_HW_STAGE_GS] = 0;
2240 rctx->default_gprs[R600_HW_STAGE_ES] = 0;
2241
2242 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2243
2244 /* SQ_CONFIG */
2245 tmp = 0;
2246 switch (family) {
2247 case CHIP_RV610:
2248 case CHIP_RV620:
2249 case CHIP_RS780:
2250 case CHIP_RS880:
2251 case CHIP_RV710:
2252 break;
2253 default:
2254 tmp |= S_008C00_VC_ENABLE(1);
2255 break;
2256 }
2257 tmp |= S_008C00_DX9_CONSTS(0);
2258 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2259 tmp |= S_008C00_PS_PRIO(ps_prio);
2260 tmp |= S_008C00_VS_PRIO(vs_prio);
2261 tmp |= S_008C00_GS_PRIO(gs_prio);
2262 tmp |= S_008C00_ES_PRIO(es_prio);
2263 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2264
2265 /* SQ_GPR_RESOURCE_MGMT_2 */
2266 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2267 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2268 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2269 r600_store_value(cb, tmp);
2270
2271 /* SQ_THREAD_RESOURCE_MGMT */
2272 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2273 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2274 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2275 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2276 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2277
2278 /* SQ_STACK_RESOURCE_MGMT_1 */
2279 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2280 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2281 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2282
2283 /* SQ_STACK_RESOURCE_MGMT_2 */
2284 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2285 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2286 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2287
2288 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2289
2290 if (rctx->b.chip_class >= R700) {
2291 r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4);
2292 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2293 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2294 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2295 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2296 } else {
2297 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2298 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2299 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2300 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2301 }
2302 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2303 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2304 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2305 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2306 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2307 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2308 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2309 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2310 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2311 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2312
2313 /* to avoid GPU doing any preloading of constant from random address */
2314 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2315 for (i = 0; i < 16; i++)
2316 r600_store_value(cb, 0);
2317
2318 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2319 for (i = 0; i < 16; i++)
2320 r600_store_value(cb, 0);
2321
2322 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2323 for (i = 0; i < 16; i++)
2324 r600_store_value(cb, 0);
2325
2326 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2327 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2328 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2329 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2330 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2331 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2332 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2333 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2334 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2335 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2336 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2337 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2338 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2339 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2340
2341 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2342 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2343 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2344
2345 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2346 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2347 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2348
2349 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2350
2351 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2352
2353 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2354
2355 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2356 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2357 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2358 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2359
2360 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2361 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2362 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2363 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2364
2365 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2366 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2367
2368 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2369 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2370
2371 if (rctx->b.chip_class >= R700) {
2372 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2373 }
2374
2375 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2376 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2377 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2378 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2379 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2380
2381 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2382 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2383 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2384
2385 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2386 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2387 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2388
2389 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2390 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2391 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2392 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2393 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2394 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2395
2396 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2397
2398 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2399 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2400 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2401
2402 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2403
2404 if (rctx->b.chip_class == R700)
2405 r600_store_context_reg(cb, R_028350_SX_MISC, 0);
2406 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2407 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2408
2409 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2410 if (rctx->screen->b.has_streamout) {
2411 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2412 }
2413
2414 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2415 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2416 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2417 }
2418
2419 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2420 {
2421 struct r600_context *rctx = (struct r600_context *)ctx;
2422 struct r600_command_buffer *cb = &shader->command_buffer;
2423 struct r600_shader *rshader = &shader->shader;
2424 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2425 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2426 unsigned tmp, sid, ufi = 0;
2427 int need_linear = 0;
2428 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2429 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2430
2431 if (!cb->buf) {
2432 r600_init_command_buffer(cb, 64);
2433 } else {
2434 cb->num_dw = 0;
2435 }
2436
2437 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2438 for (i = 0; i < rshader->ninput; i++) {
2439 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2440 pos_index = i;
2441 if (rshader->input[i].name == TGSI_SEMANTIC_FACE && face_index == -1)
2442 face_index = i;
2443 if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID)
2444 fixed_pt_position_index = i;
2445
2446 sid = rshader->input[i].spi_sid;
2447
2448 tmp = S_028644_SEMANTIC(sid);
2449
2450 /* D3D 9 behaviour. GL is undefined */
2451 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
2452 tmp |= S_028644_DEFAULT_VAL(3);
2453
2454 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2455 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2456 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2457 rctx->rasterizer && rctx->rasterizer->flatshade))
2458 tmp |= S_028644_FLAT_SHADE(1);
2459
2460 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2461 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2462 tmp |= S_028644_PT_SPRITE_TEX(1);
2463 }
2464
2465 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID)
2466 tmp |= S_028644_SEL_CENTROID(1);
2467
2468 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE)
2469 tmp |= S_028644_SEL_SAMPLE(1);
2470
2471 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2472 need_linear = 1;
2473 tmp |= S_028644_SEL_LINEAR(1);
2474 }
2475
2476 r600_store_value(cb, tmp);
2477 }
2478
2479 db_shader_control = 0;
2480 for (i = 0; i < rshader->noutput; i++) {
2481 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2482 z_export = 1;
2483 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2484 stencil_export = 1;
2485 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
2486 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
2487 mask_export = 1;
2488 }
2489 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2490 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2491 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
2492 if (rshader->uses_kill)
2493 db_shader_control |= S_02880C_KILL_ENABLE(1);
2494
2495 exports_ps = 0;
2496 for (i = 0; i < rshader->noutput; i++) {
2497 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2498 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
2499 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2500 exports_ps |= 1;
2501 }
2502 }
2503 num_cout = rshader->nr_ps_color_exports;
2504 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2505 if (!exports_ps) {
2506 /* always at least export 1 component per pixel */
2507 exports_ps = 2;
2508 }
2509
2510 shader->nr_ps_color_outputs = num_cout;
2511
2512 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2513 S_0286CC_PERSP_GRADIENT_ENA(1)|
2514 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2515 spi_input_z = 0;
2516 if (pos_index != -1) {
2517 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2518 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
2519 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2520 S_0286CC_BARYC_SAMPLE_CNTL(1)) |
2521 S_0286CC_POSITION_SAMPLE(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE);
2522 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2523 }
2524
2525 spi_ps_in_control_1 = 0;
2526 if (face_index != -1) {
2527 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2528 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2529 }
2530 if (fixed_pt_position_index != -1) {
2531 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2532 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
2533 }
2534
2535 /* HW bug in original R600 */
2536 if (rctx->b.family == CHIP_R600)
2537 ufi = 1;
2538
2539 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2540 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2541 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2542
2543 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2544
2545 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2546 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2547 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2548 S_028850_STACK_SIZE(rshader->bc.nstack) |
2549 S_028850_UNCACHED_FIRST_INST(ufi));
2550 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2551
2552 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2553 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2554
2555 /* only set some bits here, the other bits are set in the dsa state */
2556 shader->db_shader_control = db_shader_control;
2557 shader->ps_depth_export = z_export | stencil_export | mask_export;
2558
2559 shader->sprite_coord_enable = sprite_coord_enable;
2560 if (rctx->rasterizer)
2561 shader->flatshade = rctx->rasterizer->flatshade;
2562 }
2563
2564 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2565 {
2566 struct r600_command_buffer *cb = &shader->command_buffer;
2567 struct r600_shader *rshader = &shader->shader;
2568 unsigned spi_vs_out_id[10] = {};
2569 unsigned i, tmp, nparams = 0;
2570
2571 for (i = 0; i < rshader->noutput; i++) {
2572 if (rshader->output[i].spi_sid) {
2573 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2574 spi_vs_out_id[nparams / 4] |= tmp;
2575 nparams++;
2576 }
2577 }
2578
2579 r600_init_command_buffer(cb, 32);
2580
2581 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2582 for (i = 0; i < 10; i++) {
2583 r600_store_value(cb, spi_vs_out_id[i]);
2584 }
2585
2586 /* Certain attributes (position, psize, etc.) don't count as params.
2587 * VS is required to export at least one param and r600_shader_from_tgsi()
2588 * takes care of adding a dummy export.
2589 */
2590 if (nparams < 1)
2591 nparams = 1;
2592
2593 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2594 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2595 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2596 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2597 S_028868_STACK_SIZE(rshader->bc.nstack));
2598 if (rshader->vs_position_window_space) {
2599 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2600 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2601 } else {
2602 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2603 S_028818_VTX_W0_FMT(1) |
2604 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2605 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2606 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2607
2608 }
2609 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2610 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2611
2612 shader->pa_cl_vs_out_cntl =
2613 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2614 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2615 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2616 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2617 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2618 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2619 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2620 }
2621
2622 #define RV610_GSVS_ALIGN 32
2623 #define R600_GSVS_ALIGN 16
2624
2625 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2626 {
2627 struct r600_context *rctx = (struct r600_context *)ctx;
2628 struct r600_command_buffer *cb = &shader->command_buffer;
2629 struct r600_shader *rshader = &shader->shader;
2630 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2631 unsigned gsvs_itemsize =
2632 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2;
2633
2634 /* some r600s needs gsvs itemsize aligned to cacheline size
2635 this was fixed in rs780 and above. */
2636 switch (rctx->b.family) {
2637 case CHIP_RV610:
2638 gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN);
2639 break;
2640 case CHIP_R600:
2641 case CHIP_RV630:
2642 case CHIP_RV670:
2643 case CHIP_RV620:
2644 case CHIP_RV635:
2645 gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN);
2646 break;
2647 default:
2648 break;
2649 }
2650
2651 r600_init_command_buffer(cb, 64);
2652
2653 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2654 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2655
2656 if (rctx->b.chip_class >= R700) {
2657 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2658 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
2659 }
2660 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2661 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
2662
2663 r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE,
2664 cp_shader->ring_item_sizes[0] >> 2);
2665
2666 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2667 (rshader->ring_item_sizes[0]) >> 2);
2668
2669 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2670 gsvs_itemsize);
2671
2672 /* FIXME calculate these values somehow ??? */
2673 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2674 r600_store_value(cb, 0x80); /* GS_PER_ES */
2675 r600_store_value(cb, 0x100); /* ES_PER_GS */
2676 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2677 r600_store_value(cb, 0x2); /* GS_PER_VS */
2678
2679 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2680 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2681 S_02887C_STACK_SIZE(rshader->bc.nstack));
2682 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0);
2683 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2684 }
2685
2686 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2687 {
2688 struct r600_command_buffer *cb = &shader->command_buffer;
2689 struct r600_shader *rshader = &shader->shader;
2690
2691 r600_init_command_buffer(cb, 32);
2692
2693 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2694 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2695 S_028890_STACK_SIZE(rshader->bc.nstack));
2696 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0);
2697 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2698 }
2699
2700
2701 void *r600_create_resolve_blend(struct r600_context *rctx)
2702 {
2703 struct pipe_blend_state blend;
2704 unsigned i;
2705
2706 memset(&blend, 0, sizeof(blend));
2707 blend.independent_blend_enable = true;
2708 for (i = 0; i < 2; i++) {
2709 blend.rt[i].colormask = 0xf;
2710 blend.rt[i].blend_enable = 1;
2711 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2712 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2713 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2714 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2715 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2716 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2717 }
2718 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2719 }
2720
2721 void *r700_create_resolve_blend(struct r600_context *rctx)
2722 {
2723 struct pipe_blend_state blend;
2724
2725 memset(&blend, 0, sizeof(blend));
2726 blend.independent_blend_enable = true;
2727 blend.rt[0].colormask = 0xf;
2728 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2729 }
2730
2731 void *r600_create_decompress_blend(struct r600_context *rctx)
2732 {
2733 struct pipe_blend_state blend;
2734
2735 memset(&blend, 0, sizeof(blend));
2736 blend.independent_blend_enable = true;
2737 blend.rt[0].colormask = 0xf;
2738 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2739 }
2740
2741 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2742 {
2743 struct pipe_depth_stencil_alpha_state dsa;
2744 boolean quirk = false;
2745
2746 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2747 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2748 quirk = true;
2749
2750 memset(&dsa, 0, sizeof(dsa));
2751
2752 if (quirk) {
2753 dsa.depth.enabled = 1;
2754 dsa.depth.func = PIPE_FUNC_LEQUAL;
2755 dsa.stencil[0].enabled = 1;
2756 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2757 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2758 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2759 dsa.stencil[0].writemask = 0xff;
2760 }
2761
2762 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2763 }
2764
2765 void r600_update_db_shader_control(struct r600_context * rctx)
2766 {
2767 bool dual_export;
2768 unsigned db_shader_control;
2769 uint8_t ps_conservative_z;
2770
2771 if (!rctx->ps_shader) {
2772 return;
2773 }
2774
2775 dual_export = rctx->framebuffer.export_16bpc &&
2776 !rctx->ps_shader->current->ps_depth_export;
2777
2778 db_shader_control = rctx->ps_shader->current->db_shader_control |
2779 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2780
2781 ps_conservative_z = rctx->ps_shader->current->shader.ps_conservative_z;
2782
2783 /* When alpha test is enabled we can't trust the hw to make the proper
2784 * decision on the order in which ztest should be run related to fragment
2785 * shader execution.
2786 *
2787 * If alpha test is enabled perform z test after fragment. RE_Z (early
2788 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2789 */
2790 if (rctx->alphatest_state.sx_alpha_test_control) {
2791 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2792 } else {
2793 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2794 }
2795
2796 if (db_shader_control != rctx->db_misc_state.db_shader_control ||
2797 ps_conservative_z != rctx->db_misc_state.ps_conservative_z) {
2798 rctx->db_misc_state.db_shader_control = db_shader_control;
2799 rctx->db_misc_state.ps_conservative_z = ps_conservative_z;
2800 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2801 }
2802 }
2803
2804 static inline unsigned r600_array_mode(unsigned mode)
2805 {
2806 switch (mode) {
2807 default:
2808 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2809 break;
2810 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2811 break;
2812 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2813 }
2814 }
2815
2816 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2817 struct pipe_resource *dst,
2818 unsigned dst_level,
2819 unsigned dst_x,
2820 unsigned dst_y,
2821 unsigned dst_z,
2822 struct pipe_resource *src,
2823 unsigned src_level,
2824 unsigned src_x,
2825 unsigned src_y,
2826 unsigned src_z,
2827 unsigned copy_height,
2828 unsigned pitch,
2829 unsigned bpp)
2830 {
2831 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
2832 struct r600_texture *rsrc = (struct r600_texture*)src;
2833 struct r600_texture *rdst = (struct r600_texture*)dst;
2834 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2835 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2836 uint64_t base, addr;
2837
2838 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
2839 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
2840 assert(dst_mode != src_mode);
2841
2842 y = 0;
2843 lbpp = util_logbase2(bpp);
2844 pitch_tile_max = ((pitch / bpp) / 8) - 1;
2845
2846 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
2847 /* T2L */
2848 array_mode = r600_array_mode(src_mode);
2849 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
2850 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2851 /* linear height must be the same as the slice tile max height, it's ok even
2852 * if the linear destination/source have smaller heigh as the size of the
2853 * dma packet will be using the copy_height which is always smaller or equal
2854 * to the linear height
2855 */
2856 height = u_minify(rsrc->resource.b.b.height0, src_level);
2857 detile = 1;
2858 x = src_x;
2859 y = src_y;
2860 z = src_z;
2861 base = rsrc->surface.u.legacy.level[src_level].offset;
2862 addr = rdst->surface.u.legacy.level[dst_level].offset;
2863 addr += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
2864 addr += dst_y * pitch + dst_x * bpp;
2865 } else {
2866 /* L2T */
2867 array_mode = r600_array_mode(dst_mode);
2868 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
2869 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2870 /* linear height must be the same as the slice tile max height, it's ok even
2871 * if the linear destination/source have smaller heigh as the size of the
2872 * dma packet will be using the copy_height which is always smaller or equal
2873 * to the linear height
2874 */
2875 height = u_minify(rdst->resource.b.b.height0, dst_level);
2876 detile = 0;
2877 x = dst_x;
2878 y = dst_y;
2879 z = dst_z;
2880 base = rdst->surface.u.legacy.level[dst_level].offset;
2881 addr = rsrc->surface.u.legacy.level[src_level].offset;
2882 addr += rsrc->surface.u.legacy.level[src_level].slice_size * src_z;
2883 addr += src_y * pitch + src_x * bpp;
2884 }
2885 /* check that we are in dw/base alignment constraint */
2886 if (addr % 4 || base % 256) {
2887 return FALSE;
2888 }
2889
2890 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2891 * line in the blit. Compute max 8 line we can copy in the size limit
2892 */
2893 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2894 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2895 r600_need_dma_space(&rctx->b, ncopy * 7, &rdst->resource, &rsrc->resource);
2896
2897 for (i = 0; i < ncopy; i++) {
2898 cheight = cheight > copy_height ? copy_height : cheight;
2899 size = (cheight * pitch) / 4;
2900 /* emit reloc before writing cs so that cs is always in consistent state */
2901 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ,
2902 RADEON_PRIO_SDMA_TEXTURE);
2903 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE,
2904 RADEON_PRIO_SDMA_TEXTURE);
2905 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, 1, 0, size));
2906 radeon_emit(cs, base >> 8);
2907 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
2908 (lbpp << 24) | ((height - 1) << 10) |
2909 pitch_tile_max);
2910 radeon_emit(cs, (slice_tile_max << 12) | (z << 0));
2911 radeon_emit(cs, (x << 3) | (y << 17));
2912 radeon_emit(cs, addr & 0xfffffffc);
2913 radeon_emit(cs, (addr >> 32UL) & 0xff);
2914 copy_height -= cheight;
2915 addr += cheight * pitch;
2916 y += cheight;
2917 }
2918 return TRUE;
2919 }
2920
2921 static void r600_dma_copy(struct pipe_context *ctx,
2922 struct pipe_resource *dst,
2923 unsigned dst_level,
2924 unsigned dstx, unsigned dsty, unsigned dstz,
2925 struct pipe_resource *src,
2926 unsigned src_level,
2927 const struct pipe_box *src_box)
2928 {
2929 struct r600_context *rctx = (struct r600_context *)ctx;
2930 struct r600_texture *rsrc = (struct r600_texture*)src;
2931 struct r600_texture *rdst = (struct r600_texture*)dst;
2932 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2933 unsigned src_w, dst_w;
2934 unsigned src_x, src_y;
2935 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
2936
2937 if (rctx->b.dma.cs == NULL) {
2938 goto fallback;
2939 }
2940
2941 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
2942 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
2943 goto fallback;
2944
2945 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
2946 return;
2947 }
2948
2949 if (src_box->depth > 1 ||
2950 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
2951 dstz, rsrc, src_level, src_box))
2952 goto fallback;
2953
2954 src_x = util_format_get_nblocksx(src->format, src_box->x);
2955 dst_x = util_format_get_nblocksx(src->format, dst_x);
2956 src_y = util_format_get_nblocksy(src->format, src_box->y);
2957 dst_y = util_format_get_nblocksy(src->format, dst_y);
2958
2959 bpp = rdst->surface.bpe;
2960 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
2961 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
2962 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
2963 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
2964 copy_height = src_box->height / rsrc->surface.blk_h;
2965
2966 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
2967 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
2968
2969 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
2970 /* strict requirement on r6xx/r7xx */
2971 goto fallback;
2972 }
2973 /* lot of constraint on alignment this should capture them all */
2974 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
2975 goto fallback;
2976 }
2977
2978 if (src_mode == dst_mode) {
2979 uint64_t dst_offset, src_offset, size;
2980
2981 /* simple dma blit would do NOTE code here assume :
2982 * src_box.x/y == 0
2983 * dst_x/y == 0
2984 * dst_pitch == src_pitch
2985 */
2986 src_offset= rsrc->surface.u.legacy.level[src_level].offset;
2987 src_offset += rsrc->surface.u.legacy.level[src_level].slice_size * src_box->z;
2988 src_offset += src_y * src_pitch + src_x * bpp;
2989 dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
2990 dst_offset += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
2991 dst_offset += dst_y * dst_pitch + dst_x * bpp;
2992 size = src_box->height * src_pitch;
2993 /* must be dw aligned */
2994 if (dst_offset % 4 || src_offset % 4 || size % 4) {
2995 goto fallback;
2996 }
2997 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
2998 } else {
2999 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3000 src, src_level, src_x, src_y, src_box->z,
3001 copy_height, dst_pitch, bpp)) {
3002 goto fallback;
3003 }
3004 }
3005 return;
3006
3007 fallback:
3008 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3009 src, src_level, src_box);
3010 }
3011
3012 void r600_init_state_functions(struct r600_context *rctx)
3013 {
3014 unsigned id = 1;
3015 unsigned i;
3016 /* !!!
3017 * To avoid GPU lockup registers must be emited in a specific order
3018 * (no kidding ...). The order below is important and have been
3019 * partialy infered from analyzing fglrx command stream.
3020 *
3021 * Don't reorder atom without carefully checking the effect (GPU lockup
3022 * or piglit regression).
3023 * !!!
3024 */
3025
3026 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3027
3028 /* shader const */
3029 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3030 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3031 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3032
3033 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3034 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3035 */
3036 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3037 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3038 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3039 /* resource */
3040 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3041 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3042 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3043 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3044
3045 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3046
3047 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3048 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3049 rctx->sample_mask.sample_mask = ~0;
3050
3051 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3052 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3053 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3054 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3055 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3056 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3057 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3058 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3059 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3060 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 9);
3061 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3062 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3063 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3064 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3065 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3066 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3067 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3068 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3069 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3070 for (i = 0; i < R600_NUM_HW_STAGES; i++)
3071 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3072 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3073 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3074
3075 rctx->b.b.create_blend_state = r600_create_blend_state;
3076 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3077 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3078 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3079 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3080 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3081 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3082 rctx->b.b.set_min_samples = r600_set_min_samples;
3083 rctx->b.b.get_sample_position = r600_get_sample_position;
3084 rctx->b.dma_copy = r600_dma_copy;
3085 }
3086 /* this function must be last */