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r600g: handle 16/32 u/s norm formats properly
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_framebuffer.h>
40 #include <pipebuffer/pb_buffer.h>
41 #include "r600.h"
42 #include "r600d.h"
43 #include "r600_resource.h"
44 #include "r600_shader.h"
45 #include "r600_pipe.h"
46 #include "r600_state_inlines.h"
47
48 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
49 {
50 struct r600_pipe_state state;
51
52 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
53 state.nregs = 0;
54 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
55 float offset_units = rctx->rasterizer->offset_units;
56 unsigned offset_db_fmt_cntl = 0, depth;
57
58 switch (rctx->framebuffer.zsbuf->texture->format) {
59 case PIPE_FORMAT_Z24X8_UNORM:
60 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
61 depth = -24;
62 offset_units *= 2.0f;
63 break;
64 case PIPE_FORMAT_Z32_FLOAT:
65 depth = -23;
66 offset_units *= 1.0f;
67 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
68 break;
69 case PIPE_FORMAT_Z16_UNORM:
70 depth = -16;
71 offset_units *= 4.0f;
72 break;
73 default:
74 return;
75 }
76 /* FIXME some of those reg can be computed with cso */
77 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
78 r600_pipe_state_add_reg(&state,
79 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
80 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
81 r600_pipe_state_add_reg(&state,
82 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
83 fui(offset_units), 0xFFFFFFFF, NULL);
84 r600_pipe_state_add_reg(&state,
85 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
86 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
87 r600_pipe_state_add_reg(&state,
88 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
89 fui(offset_units), 0xFFFFFFFF, NULL);
90 r600_pipe_state_add_reg(&state,
91 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
92 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
93 r600_context_pipe_state_set(&rctx->ctx, &state);
94 }
95 }
96
97 static void r600_set_blend_color(struct pipe_context *ctx,
98 const struct pipe_blend_color *state)
99 {
100 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
101 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
102
103 if (rstate == NULL)
104 return;
105
106 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
107 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
108 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
109 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
110 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
111 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
112 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
113 r600_context_pipe_state_set(&rctx->ctx, rstate);
114 }
115
116 static void *r600_create_blend_state(struct pipe_context *ctx,
117 const struct pipe_blend_state *state)
118 {
119 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
120 struct r600_pipe_state *rstate;
121 u32 color_control, target_mask;
122
123 if (blend == NULL) {
124 return NULL;
125 }
126 rstate = &blend->rstate;
127
128 rstate->id = R600_PIPE_STATE_BLEND;
129
130 target_mask = 0;
131 color_control = S_028808_PER_MRT_BLEND(1);
132 if (state->logicop_enable) {
133 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
134 } else {
135 color_control |= (0xcc << 16);
136 }
137 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
138 if (state->independent_blend_enable) {
139 for (int i = 0; i < 8; i++) {
140 if (state->rt[i].blend_enable) {
141 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
142 }
143 target_mask |= (state->rt[i].colormask << (4 * i));
144 }
145 } else {
146 for (int i = 0; i < 8; i++) {
147 if (state->rt[0].blend_enable) {
148 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
149 }
150 target_mask |= (state->rt[0].colormask << (4 * i));
151 }
152 }
153 blend->cb_target_mask = target_mask;
154 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
155 color_control, 0xFFFFFFFF, NULL);
156
157 for (int i = 0; i < 8; i++) {
158 unsigned eqRGB = state->rt[i].rgb_func;
159 unsigned srcRGB = state->rt[i].rgb_src_factor;
160 unsigned dstRGB = state->rt[i].rgb_dst_factor;
161
162 unsigned eqA = state->rt[i].alpha_func;
163 unsigned srcA = state->rt[i].alpha_src_factor;
164 unsigned dstA = state->rt[i].alpha_dst_factor;
165 uint32_t bc = 0;
166
167 if (!state->rt[i].blend_enable)
168 continue;
169
170 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
171 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
172 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
173
174 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
175 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
176 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
177 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
178 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
179 }
180
181 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
182 if (i == 0) {
183 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
184 }
185 }
186 return rstate;
187 }
188
189 static void *r600_create_dsa_state(struct pipe_context *ctx,
190 const struct pipe_depth_stencil_alpha_state *state)
191 {
192 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
193 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
194 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
195
196 if (rstate == NULL) {
197 return NULL;
198 }
199
200 rstate->id = R600_PIPE_STATE_DSA;
201 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
202 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
203 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
204 * be set if shader use texkill instruction
205 */
206 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
207 stencil_ref_mask = 0;
208 stencil_ref_mask_bf = 0;
209 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
210 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
211 S_028800_ZFUNC(state->depth.func);
212
213 /* stencil */
214 if (state->stencil[0].enabled) {
215 db_depth_control |= S_028800_STENCIL_ENABLE(1);
216 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
217 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
218 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
219 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
220
221
222 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
223 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
224 if (state->stencil[1].enabled) {
225 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
226 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
227 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
228 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
229 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
230 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
231 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
232 }
233 }
234
235 /* alpha */
236 alpha_test_control = 0;
237 alpha_ref = 0;
238 if (state->alpha.enabled) {
239 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
240 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
241 alpha_ref = fui(state->alpha.ref_value);
242 }
243
244 /* misc */
245 db_render_control = 0;
246 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
247 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
248 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
249 /* TODO db_render_override depends on query */
250 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
251 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
252 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
253 r600_pipe_state_add_reg(rstate,
254 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
255 0xFFFFFFFF & C_028430_STENCILREF, NULL);
256 r600_pipe_state_add_reg(rstate,
257 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
258 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
259 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
260 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
261 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
262 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
263 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
264 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
265 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
266 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
267 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
268 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
269 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
270
271 return rstate;
272 }
273
274 static void *r600_create_rs_state(struct pipe_context *ctx,
275 const struct pipe_rasterizer_state *state)
276 {
277 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
278 struct r600_pipe_state *rstate;
279 unsigned tmp;
280 unsigned prov_vtx = 1, polygon_dual_mode;
281 unsigned clip_rule;
282
283 if (rs == NULL) {
284 return NULL;
285 }
286
287 rstate = &rs->rstate;
288 rs->flatshade = state->flatshade;
289 rs->sprite_coord_enable = state->sprite_coord_enable;
290
291 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
292 /* offset */
293 rs->offset_units = state->offset_units;
294 rs->offset_scale = state->offset_scale * 12.0f;
295
296 rstate->id = R600_PIPE_STATE_RASTERIZER;
297 if (state->flatshade_first)
298 prov_vtx = 0;
299 tmp = S_0286D4_FLAT_SHADE_ENA(1);
300 if (state->sprite_coord_enable) {
301 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
302 S_0286D4_PNT_SPRITE_OVRD_X(2) |
303 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
304 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
305 S_0286D4_PNT_SPRITE_OVRD_W(1);
306 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
307 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
308 }
309 }
310 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
311
312 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
313 state->fill_back != PIPE_POLYGON_MODE_FILL);
314 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
315 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
316 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
317 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
318 S_028814_FACE(!state->front_ccw) |
319 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
320 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
321 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
322 S_028814_POLY_MODE(polygon_dual_mode) |
323 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
324 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
325 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
326 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
327 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
328 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
329 /* point size 12.4 fixed point */
330 tmp = (unsigned)(state->point_size * 8.0);
331 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
332 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
333
334 tmp = (unsigned)state->line_width * 8;
335 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
336
337 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
338 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
339 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
340
341 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
342 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
343 0xFFFFFFFF, NULL);
344
345 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
346 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
347 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
348 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
349 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
350 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
351
352 return rstate;
353 }
354
355 static void *r600_create_sampler_state(struct pipe_context *ctx,
356 const struct pipe_sampler_state *state)
357 {
358 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
359 union util_color uc;
360
361 if (rstate == NULL) {
362 return NULL;
363 }
364
365 rstate->id = R600_PIPE_STATE_SAMPLER;
366 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
367 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
368 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
369 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
370 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
371 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
372 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
373 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
374 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
375 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
376 /* FIXME LOD it depends on texture base level ... */
377 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
378 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
379 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
380 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
381 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
382 if (uc.ui) {
383 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
384 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
385 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
386 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
387 }
388 return rstate;
389 }
390
391 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
392 struct pipe_resource *texture,
393 const struct pipe_sampler_view *state)
394 {
395 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
396 struct r600_pipe_state *rstate;
397 const struct util_format_description *desc;
398 struct r600_resource_texture *tmp;
399 struct r600_resource *rbuffer;
400 unsigned format;
401 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
402 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
403 struct r600_bo *bo[2];
404
405 if (resource == NULL)
406 return NULL;
407 rstate = &resource->state;
408
409 /* initialize base object */
410 resource->base = *state;
411 resource->base.texture = NULL;
412 pipe_reference(NULL, &texture->reference);
413 resource->base.texture = texture;
414 resource->base.reference.count = 1;
415 resource->base.context = ctx;
416
417 swizzle[0] = state->swizzle_r;
418 swizzle[1] = state->swizzle_g;
419 swizzle[2] = state->swizzle_b;
420 swizzle[3] = state->swizzle_a;
421 format = r600_translate_texformat(state->format,
422 swizzle,
423 &word4, &yuv_format);
424 if (format == ~0) {
425 format = 0;
426 }
427 desc = util_format_description(state->format);
428 if (desc == NULL) {
429 R600_ERR("unknow format %d\n", state->format);
430 }
431 tmp = (struct r600_resource_texture *)texture;
432 if (tmp->depth && !tmp->is_flushing_texture) {
433 r600_texture_depth_flush(ctx, texture, TRUE);
434 tmp = tmp->flushed_depth_texture;
435 }
436 rbuffer = &tmp->resource;
437 bo[0] = rbuffer->bo;
438 bo[1] = rbuffer->bo;
439 pitch = align(tmp->pitch_in_pixels[0], 8);
440 if (tmp->tiled) {
441 array_mode = tmp->array_mode[0];
442 tile_type = tmp->tile_type;
443 }
444
445 /* FIXME properly handle first level != 0 */
446 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
447 S_038000_DIM(r600_tex_dim(texture->target)) |
448 S_038000_TILE_MODE(array_mode) |
449 S_038000_TILE_TYPE(tile_type) |
450 S_038000_PITCH((pitch / 8) - 1) |
451 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
452 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
453 S_038004_TEX_HEIGHT(texture->height0 - 1) |
454 S_038004_TEX_DEPTH(texture->depth0 - 1) |
455 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
456 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
457 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
458 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
459 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
460 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
461 word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
462 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_NO_ZERO) |
463 S_038010_REQUEST_SIZE(1) |
464 S_038010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
465 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
466 S_038014_LAST_LEVEL(state->u.tex.last_level) |
467 S_038014_BASE_ARRAY(0) |
468 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
469 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
470 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
471
472 return &resource->base;
473 }
474
475 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
476 struct pipe_sampler_view **views)
477 {
478 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
479 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
480
481 for (int i = 0; i < count; i++) {
482 if (resource[i]) {
483 r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i);
484 }
485 }
486 }
487
488 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
489 struct pipe_sampler_view **views)
490 {
491 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
492 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
493 int i;
494
495 for (i = 0; i < count; i++) {
496 if (&rctx->ps_samplers.views[i]->base != views[i]) {
497 if (resource[i])
498 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
499 i + R600_MAX_CONST_BUFFERS);
500 else
501 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
502 i + R600_MAX_CONST_BUFFERS);
503
504 pipe_sampler_view_reference(
505 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
506 views[i]);
507
508 }
509 }
510 for (i = count; i < NUM_TEX_UNITS; i++) {
511 if (rctx->ps_samplers.views[i]) {
512 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
513 i + R600_MAX_CONST_BUFFERS);
514 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
515 }
516 }
517 rctx->ps_samplers.n_views = count;
518 }
519
520 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
521 {
522 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
523 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
524
525 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
526 rctx->ps_samplers.n_samplers = count;
527
528 for (int i = 0; i < count; i++) {
529 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
530 }
531 }
532
533 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
534 {
535 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
536 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
537
538 for (int i = 0; i < count; i++) {
539 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
540 }
541 }
542
543 static void r600_set_clip_state(struct pipe_context *ctx,
544 const struct pipe_clip_state *state)
545 {
546 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
547 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
548
549 if (rstate == NULL)
550 return;
551
552 rctx->clip = *state;
553 rstate->id = R600_PIPE_STATE_CLIP;
554 for (int i = 0; i < state->nr; i++) {
555 r600_pipe_state_add_reg(rstate,
556 R_028E20_PA_CL_UCP0_X + i * 16,
557 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
558 r600_pipe_state_add_reg(rstate,
559 R_028E24_PA_CL_UCP0_Y + i * 16,
560 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
561 r600_pipe_state_add_reg(rstate,
562 R_028E28_PA_CL_UCP0_Z + i * 16,
563 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
564 r600_pipe_state_add_reg(rstate,
565 R_028E2C_PA_CL_UCP0_W + i * 16,
566 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
567 }
568 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
569 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
570 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
571 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
572
573 free(rctx->states[R600_PIPE_STATE_CLIP]);
574 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
575 r600_context_pipe_state_set(&rctx->ctx, rstate);
576 }
577
578 static void r600_set_polygon_stipple(struct pipe_context *ctx,
579 const struct pipe_poly_stipple *state)
580 {
581 }
582
583 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
584 {
585 }
586
587 static void r600_set_scissor_state(struct pipe_context *ctx,
588 const struct pipe_scissor_state *state)
589 {
590 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
591 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
592 u32 tl, br;
593
594 if (rstate == NULL)
595 return;
596
597 rstate->id = R600_PIPE_STATE_SCISSOR;
598 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
599 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
600 r600_pipe_state_add_reg(rstate,
601 R_028210_PA_SC_CLIPRECT_0_TL, tl,
602 0xFFFFFFFF, NULL);
603 r600_pipe_state_add_reg(rstate,
604 R_028214_PA_SC_CLIPRECT_0_BR, br,
605 0xFFFFFFFF, NULL);
606 r600_pipe_state_add_reg(rstate,
607 R_028218_PA_SC_CLIPRECT_1_TL, tl,
608 0xFFFFFFFF, NULL);
609 r600_pipe_state_add_reg(rstate,
610 R_02821C_PA_SC_CLIPRECT_1_BR, br,
611 0xFFFFFFFF, NULL);
612 r600_pipe_state_add_reg(rstate,
613 R_028220_PA_SC_CLIPRECT_2_TL, tl,
614 0xFFFFFFFF, NULL);
615 r600_pipe_state_add_reg(rstate,
616 R_028224_PA_SC_CLIPRECT_2_BR, br,
617 0xFFFFFFFF, NULL);
618 r600_pipe_state_add_reg(rstate,
619 R_028228_PA_SC_CLIPRECT_3_TL, tl,
620 0xFFFFFFFF, NULL);
621 r600_pipe_state_add_reg(rstate,
622 R_02822C_PA_SC_CLIPRECT_3_BR, br,
623 0xFFFFFFFF, NULL);
624
625 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
626 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
627 r600_context_pipe_state_set(&rctx->ctx, rstate);
628 }
629
630 static void r600_set_stencil_ref(struct pipe_context *ctx,
631 const struct pipe_stencil_ref *state)
632 {
633 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
634 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
635 u32 tmp;
636
637 if (rstate == NULL)
638 return;
639
640 rctx->stencil_ref = *state;
641 rstate->id = R600_PIPE_STATE_STENCIL_REF;
642 tmp = S_028430_STENCILREF(state->ref_value[0]);
643 r600_pipe_state_add_reg(rstate,
644 R_028430_DB_STENCILREFMASK, tmp,
645 ~C_028430_STENCILREF, NULL);
646 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
647 r600_pipe_state_add_reg(rstate,
648 R_028434_DB_STENCILREFMASK_BF, tmp,
649 ~C_028434_STENCILREF_BF, NULL);
650
651 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
652 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
653 r600_context_pipe_state_set(&rctx->ctx, rstate);
654 }
655
656 static void r600_set_viewport_state(struct pipe_context *ctx,
657 const struct pipe_viewport_state *state)
658 {
659 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
660 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
661
662 if (rstate == NULL)
663 return;
664
665 rctx->viewport = *state;
666 rstate->id = R600_PIPE_STATE_VIEWPORT;
667 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
668 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
669 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
670 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
671 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
672 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
673 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
674 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
675 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
676
677 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
678 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
679 r600_context_pipe_state_set(&rctx->ctx, rstate);
680 }
681
682 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
683 const struct pipe_framebuffer_state *state, int cb)
684 {
685 struct r600_resource_texture *rtex;
686 struct r600_resource *rbuffer;
687 struct r600_surface *surf;
688 unsigned level = state->cbufs[cb]->u.tex.level;
689 unsigned pitch, slice;
690 unsigned color_info;
691 unsigned format, swap, ntype;
692 unsigned offset;
693 const struct util_format_description *desc;
694 struct r600_bo *bo[3];
695 int i;
696
697 surf = (struct r600_surface *)state->cbufs[cb];
698 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
699
700 if (rtex->depth && !rtex->is_flushing_texture) {
701 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
702 rtex = rtex->flushed_depth_texture;
703 }
704
705 rbuffer = &rtex->resource;
706 bo[0] = rbuffer->bo;
707 bo[1] = rbuffer->bo;
708 bo[2] = rbuffer->bo;
709
710 /* XXX quite sure for dx10+ hw don't need any offset hacks */
711 offset = r600_texture_get_offset(rtex,
712 level, state->cbufs[cb]->u.tex.first_layer);
713 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
714 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
715 ntype = 0;
716 desc = util_format_description(surf->base.format);
717 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
718 ntype = V_0280A0_NUMBER_SRGB;
719
720 for (i = 0; i < 4; i++) {
721 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
722 break;
723 }
724 }
725
726 format = r600_translate_colorformat(surf->base.format);
727 swap = r600_translate_colorswap(surf->base.format);
728 color_info = S_0280A0_FORMAT(format) |
729 S_0280A0_COMP_SWAP(swap) |
730 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
731 S_0280A0_BLEND_CLAMP(1) |
732 S_0280A0_NUMBER_TYPE(ntype);
733
734 /* on R600 this can't be set if BLEND_CLAMP isn't set,
735 if BLEND_FLOAT32 is set of > 11 bits in a UNORM or SNORM */
736 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
737 desc->channel[i].size < 12)
738 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
739
740 r600_pipe_state_add_reg(rstate,
741 R_028040_CB_COLOR0_BASE + cb * 4,
742 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
743 r600_pipe_state_add_reg(rstate,
744 R_0280A0_CB_COLOR0_INFO + cb * 4,
745 color_info, 0xFFFFFFFF, bo[0]);
746 r600_pipe_state_add_reg(rstate,
747 R_028060_CB_COLOR0_SIZE + cb * 4,
748 S_028060_PITCH_TILE_MAX(pitch) |
749 S_028060_SLICE_TILE_MAX(slice),
750 0xFFFFFFFF, NULL);
751 r600_pipe_state_add_reg(rstate,
752 R_028080_CB_COLOR0_VIEW + cb * 4,
753 0x00000000, 0xFFFFFFFF, NULL);
754 r600_pipe_state_add_reg(rstate,
755 R_0280E0_CB_COLOR0_FRAG + cb * 4,
756 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
757 r600_pipe_state_add_reg(rstate,
758 R_0280C0_CB_COLOR0_TILE + cb * 4,
759 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
760 r600_pipe_state_add_reg(rstate,
761 R_028100_CB_COLOR0_MASK + cb * 4,
762 0x00000000, 0xFFFFFFFF, NULL);
763 }
764
765 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
766 const struct pipe_framebuffer_state *state)
767 {
768 struct r600_resource_texture *rtex;
769 struct r600_resource *rbuffer;
770 struct r600_surface *surf;
771 unsigned level;
772 unsigned pitch, slice, format;
773 unsigned offset;
774
775 if (state->zsbuf == NULL)
776 return;
777
778 level = state->zsbuf->u.tex.level;
779
780 surf = (struct r600_surface *)state->zsbuf;
781 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
782
783 rbuffer = &rtex->resource;
784
785 /* XXX quite sure for dx10+ hw don't need any offset hacks */
786 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
787 level, state->zsbuf->u.tex.first_layer);
788 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
789 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
790 format = r600_translate_dbformat(state->zsbuf->texture->format);
791
792 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
793 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
794 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
795 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
796 0xFFFFFFFF, NULL);
797 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
798 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
799 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
800 0xFFFFFFFF, rbuffer->bo);
801 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
802 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL);
803 }
804
805 static void r600_set_framebuffer_state(struct pipe_context *ctx,
806 const struct pipe_framebuffer_state *state)
807 {
808 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
809 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
810 u32 shader_mask, tl, br, shader_control, target_mask;
811
812 if (rstate == NULL)
813 return;
814
815 /* unreference old buffer and reference new one */
816 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
817
818 util_copy_framebuffer_state(&rctx->framebuffer, state);
819
820 /* build states */
821 for (int i = 0; i < state->nr_cbufs; i++) {
822 r600_cb(rctx, rstate, state, i);
823 }
824 if (state->zsbuf) {
825 r600_db(rctx, rstate, state);
826 }
827
828 target_mask = 0x00000000;
829 target_mask = 0xFFFFFFFF;
830 shader_mask = 0;
831 shader_control = 0;
832 for (int i = 0; i < state->nr_cbufs; i++) {
833 target_mask ^= 0xf << (i * 4);
834 shader_mask |= 0xf << (i * 4);
835 shader_control |= 1 << i;
836 }
837 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
838 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
839
840 r600_pipe_state_add_reg(rstate,
841 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
842 0xFFFFFFFF, NULL);
843 r600_pipe_state_add_reg(rstate,
844 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
845 0xFFFFFFFF, NULL);
846 r600_pipe_state_add_reg(rstate,
847 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
848 0xFFFFFFFF, NULL);
849 r600_pipe_state_add_reg(rstate,
850 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
851 0xFFFFFFFF, NULL);
852 r600_pipe_state_add_reg(rstate,
853 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
854 0xFFFFFFFF, NULL);
855 r600_pipe_state_add_reg(rstate,
856 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
857 0xFFFFFFFF, NULL);
858 r600_pipe_state_add_reg(rstate,
859 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
860 0xFFFFFFFF, NULL);
861 r600_pipe_state_add_reg(rstate,
862 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
863 0xFFFFFFFF, NULL);
864 r600_pipe_state_add_reg(rstate,
865 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
866 0xFFFFFFFF, NULL);
867 if (rctx->family >= CHIP_RV770) {
868 r600_pipe_state_add_reg(rstate,
869 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
870 0xFFFFFFFF, NULL);
871 }
872
873 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
874 shader_control, 0xFFFFFFFF, NULL);
875 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
876 0x00000000, target_mask, NULL);
877 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
878 shader_mask, 0xFFFFFFFF, NULL);
879 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
880 0x00000000, 0xFFFFFFFF, NULL);
881 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
882 0x00000000, 0xFFFFFFFF, NULL);
883 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
884 0x00000000, 0xFFFFFFFF, NULL);
885 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
886 0x01000000, 0xFFFFFFFF, NULL);
887 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
888 0x00000000, 0xFFFFFFFF, NULL);
889 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
890 0x000000FF, 0xFFFFFFFF, NULL);
891 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
892 0xFFFFFFFF, 0xFFFFFFFF, NULL);
893 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
894 0xFFFFFFFF, 0xFFFFFFFF, NULL);
895
896 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
897 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
898 r600_context_pipe_state_set(&rctx->ctx, rstate);
899
900 if (state->zsbuf) {
901 r600_polygon_offset_update(rctx);
902 }
903 }
904
905 void r600_init_state_functions(struct r600_pipe_context *rctx)
906 {
907 rctx->context.create_blend_state = r600_create_blend_state;
908 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
909 rctx->context.create_fs_state = r600_create_shader_state;
910 rctx->context.create_rasterizer_state = r600_create_rs_state;
911 rctx->context.create_sampler_state = r600_create_sampler_state;
912 rctx->context.create_sampler_view = r600_create_sampler_view;
913 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
914 rctx->context.create_vs_state = r600_create_shader_state;
915 rctx->context.bind_blend_state = r600_bind_blend_state;
916 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
917 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
918 rctx->context.bind_fs_state = r600_bind_ps_shader;
919 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
920 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
921 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
922 rctx->context.bind_vs_state = r600_bind_vs_shader;
923 rctx->context.delete_blend_state = r600_delete_state;
924 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
925 rctx->context.delete_fs_state = r600_delete_ps_shader;
926 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
927 rctx->context.delete_sampler_state = r600_delete_state;
928 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
929 rctx->context.delete_vs_state = r600_delete_vs_shader;
930 rctx->context.set_blend_color = r600_set_blend_color;
931 rctx->context.set_clip_state = r600_set_clip_state;
932 rctx->context.set_constant_buffer = r600_set_constant_buffer;
933 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
934 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
935 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
936 rctx->context.set_sample_mask = r600_set_sample_mask;
937 rctx->context.set_scissor_state = r600_set_scissor_state;
938 rctx->context.set_stencil_ref = r600_set_stencil_ref;
939 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
940 rctx->context.set_index_buffer = r600_set_index_buffer;
941 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
942 rctx->context.set_viewport_state = r600_set_viewport_state;
943 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
944 }
945
946 void r600_init_config(struct r600_pipe_context *rctx)
947 {
948 int ps_prio;
949 int vs_prio;
950 int gs_prio;
951 int es_prio;
952 int num_ps_gprs;
953 int num_vs_gprs;
954 int num_gs_gprs;
955 int num_es_gprs;
956 int num_temp_gprs;
957 int num_ps_threads;
958 int num_vs_threads;
959 int num_gs_threads;
960 int num_es_threads;
961 int num_ps_stack_entries;
962 int num_vs_stack_entries;
963 int num_gs_stack_entries;
964 int num_es_stack_entries;
965 enum radeon_family family;
966 struct r600_pipe_state *rstate = &rctx->config;
967 u32 tmp;
968
969 family = r600_get_family(rctx->radeon);
970 ps_prio = 0;
971 vs_prio = 1;
972 gs_prio = 2;
973 es_prio = 3;
974 switch (family) {
975 case CHIP_R600:
976 num_ps_gprs = 192;
977 num_vs_gprs = 56;
978 num_temp_gprs = 4;
979 num_gs_gprs = 0;
980 num_es_gprs = 0;
981 num_ps_threads = 136;
982 num_vs_threads = 48;
983 num_gs_threads = 4;
984 num_es_threads = 4;
985 num_ps_stack_entries = 128;
986 num_vs_stack_entries = 128;
987 num_gs_stack_entries = 0;
988 num_es_stack_entries = 0;
989 break;
990 case CHIP_RV630:
991 case CHIP_RV635:
992 num_ps_gprs = 84;
993 num_vs_gprs = 36;
994 num_temp_gprs = 4;
995 num_gs_gprs = 0;
996 num_es_gprs = 0;
997 num_ps_threads = 144;
998 num_vs_threads = 40;
999 num_gs_threads = 4;
1000 num_es_threads = 4;
1001 num_ps_stack_entries = 40;
1002 num_vs_stack_entries = 40;
1003 num_gs_stack_entries = 32;
1004 num_es_stack_entries = 16;
1005 break;
1006 case CHIP_RV610:
1007 case CHIP_RV620:
1008 case CHIP_RS780:
1009 case CHIP_RS880:
1010 default:
1011 num_ps_gprs = 84;
1012 num_vs_gprs = 36;
1013 num_temp_gprs = 4;
1014 num_gs_gprs = 0;
1015 num_es_gprs = 0;
1016 num_ps_threads = 136;
1017 num_vs_threads = 48;
1018 num_gs_threads = 4;
1019 num_es_threads = 4;
1020 num_ps_stack_entries = 40;
1021 num_vs_stack_entries = 40;
1022 num_gs_stack_entries = 32;
1023 num_es_stack_entries = 16;
1024 break;
1025 case CHIP_RV670:
1026 num_ps_gprs = 144;
1027 num_vs_gprs = 40;
1028 num_temp_gprs = 4;
1029 num_gs_gprs = 0;
1030 num_es_gprs = 0;
1031 num_ps_threads = 136;
1032 num_vs_threads = 48;
1033 num_gs_threads = 4;
1034 num_es_threads = 4;
1035 num_ps_stack_entries = 40;
1036 num_vs_stack_entries = 40;
1037 num_gs_stack_entries = 32;
1038 num_es_stack_entries = 16;
1039 break;
1040 case CHIP_RV770:
1041 num_ps_gprs = 192;
1042 num_vs_gprs = 56;
1043 num_temp_gprs = 4;
1044 num_gs_gprs = 0;
1045 num_es_gprs = 0;
1046 num_ps_threads = 188;
1047 num_vs_threads = 60;
1048 num_gs_threads = 0;
1049 num_es_threads = 0;
1050 num_ps_stack_entries = 256;
1051 num_vs_stack_entries = 256;
1052 num_gs_stack_entries = 0;
1053 num_es_stack_entries = 0;
1054 break;
1055 case CHIP_RV730:
1056 case CHIP_RV740:
1057 num_ps_gprs = 84;
1058 num_vs_gprs = 36;
1059 num_temp_gprs = 4;
1060 num_gs_gprs = 0;
1061 num_es_gprs = 0;
1062 num_ps_threads = 188;
1063 num_vs_threads = 60;
1064 num_gs_threads = 0;
1065 num_es_threads = 0;
1066 num_ps_stack_entries = 128;
1067 num_vs_stack_entries = 128;
1068 num_gs_stack_entries = 0;
1069 num_es_stack_entries = 0;
1070 break;
1071 case CHIP_RV710:
1072 num_ps_gprs = 192;
1073 num_vs_gprs = 56;
1074 num_temp_gprs = 4;
1075 num_gs_gprs = 0;
1076 num_es_gprs = 0;
1077 num_ps_threads = 144;
1078 num_vs_threads = 48;
1079 num_gs_threads = 0;
1080 num_es_threads = 0;
1081 num_ps_stack_entries = 128;
1082 num_vs_stack_entries = 128;
1083 num_gs_stack_entries = 0;
1084 num_es_stack_entries = 0;
1085 break;
1086 }
1087
1088 rstate->id = R600_PIPE_STATE_CONFIG;
1089
1090 /* SQ_CONFIG */
1091 tmp = 0;
1092 switch (family) {
1093 case CHIP_RV610:
1094 case CHIP_RV620:
1095 case CHIP_RS780:
1096 case CHIP_RS880:
1097 case CHIP_RV710:
1098 break;
1099 default:
1100 tmp |= S_008C00_VC_ENABLE(1);
1101 break;
1102 }
1103 tmp |= S_008C00_DX9_CONSTS(0);
1104 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1105 tmp |= S_008C00_PS_PRIO(ps_prio);
1106 tmp |= S_008C00_VS_PRIO(vs_prio);
1107 tmp |= S_008C00_GS_PRIO(gs_prio);
1108 tmp |= S_008C00_ES_PRIO(es_prio);
1109 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1110
1111 /* SQ_GPR_RESOURCE_MGMT_1 */
1112 tmp = 0;
1113 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1114 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1115 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1116 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1117
1118 /* SQ_GPR_RESOURCE_MGMT_2 */
1119 tmp = 0;
1120 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1121 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1122 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1123
1124 /* SQ_THREAD_RESOURCE_MGMT */
1125 tmp = 0;
1126 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1127 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1128 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1129 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1130 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1131
1132 /* SQ_STACK_RESOURCE_MGMT_1 */
1133 tmp = 0;
1134 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1135 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1136 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1137
1138 /* SQ_STACK_RESOURCE_MGMT_2 */
1139 tmp = 0;
1140 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1141 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1142 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1143
1144 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1145 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1146
1147 if (family >= CHIP_RV770) {
1148 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1149 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1150 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1151 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1152 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1153 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
1154 } else {
1155 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1156 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1157 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1158 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1159 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1160 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
1161 }
1162 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1163 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1164 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1165 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1166 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1167 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1168 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1169 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1170 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1171 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1172 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1173 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1174 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1175 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1176 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1177 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1178 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1179 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1180 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1181 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1182 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1183 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1184 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1185 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1186 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1187 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1188
1189 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1190 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1191 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1192 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1193 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1194 r600_context_pipe_state_set(&rctx->ctx, rstate);
1195 }
1196
1197 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1198 {
1199 struct pipe_depth_stencil_alpha_state dsa;
1200 struct r600_pipe_state *rstate;
1201 boolean quirk = false;
1202
1203 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1204 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1205 quirk = true;
1206
1207 memset(&dsa, 0, sizeof(dsa));
1208
1209 if (quirk) {
1210 dsa.depth.enabled = 1;
1211 dsa.depth.func = PIPE_FUNC_LEQUAL;
1212 dsa.stencil[0].enabled = 1;
1213 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1214 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1215 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1216 dsa.stencil[0].writemask = 0xff;
1217 }
1218
1219 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1220 r600_pipe_state_add_reg(rstate,
1221 R_02880C_DB_SHADER_CONTROL,
1222 0x0,
1223 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1224 r600_pipe_state_add_reg(rstate,
1225 R_028D0C_DB_RENDER_CONTROL,
1226 S_028D0C_DEPTH_COPY_ENABLE(1) |
1227 S_028D0C_STENCIL_COPY_ENABLE(1) |
1228 S_028D0C_COPY_CENTROID(1),
1229 S_028D0C_DEPTH_COPY_ENABLE(1) |
1230 S_028D0C_STENCIL_COPY_ENABLE(1) |
1231 S_028D0C_COPY_CENTROID(1), NULL);
1232 return rstate;
1233 }
1234
1235 void r600_pipe_set_buffer_resource(struct r600_pipe_context *rctx,
1236 struct r600_pipe_state *rstate,
1237 struct r600_resource *rbuffer,
1238 unsigned offset, unsigned stride)
1239 {
1240 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
1241 offset, 0xFFFFFFFF, rbuffer->bo);
1242 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
1243 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
1244 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
1245 S_038008_STRIDE(stride),
1246 0xFFFFFFFF, NULL);
1247 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
1248 0x00000000, 0xFFFFFFFF, NULL);
1249 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
1250 0x00000000, 0xFFFFFFFF, NULL);
1251 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
1252 0x00000000, 0xFFFFFFFF, NULL);
1253 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
1254 0xC0000000, 0xFFFFFFFF, NULL);
1255 }