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gallium: remove PIPE_USAGE_STATIC
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static uint32_t r600_translate_colorswap(enum pipe_format format)
145 {
146 switch (format) {
147 /* 8-bit buffers. */
148 case PIPE_FORMAT_A8_UNORM:
149 case PIPE_FORMAT_A8_SNORM:
150 case PIPE_FORMAT_A8_UINT:
151 case PIPE_FORMAT_A8_SINT:
152 case PIPE_FORMAT_A16_UNORM:
153 case PIPE_FORMAT_A16_SNORM:
154 case PIPE_FORMAT_A16_UINT:
155 case PIPE_FORMAT_A16_SINT:
156 case PIPE_FORMAT_A16_FLOAT:
157 case PIPE_FORMAT_A32_UINT:
158 case PIPE_FORMAT_A32_SINT:
159 case PIPE_FORMAT_A32_FLOAT:
160 case PIPE_FORMAT_R4A4_UNORM:
161 return V_0280A0_SWAP_ALT_REV;
162 case PIPE_FORMAT_I8_UNORM:
163 case PIPE_FORMAT_I8_SNORM:
164 case PIPE_FORMAT_I8_UINT:
165 case PIPE_FORMAT_I8_SINT:
166 case PIPE_FORMAT_L8_UNORM:
167 case PIPE_FORMAT_L8_SNORM:
168 case PIPE_FORMAT_L8_UINT:
169 case PIPE_FORMAT_L8_SINT:
170 case PIPE_FORMAT_L8_SRGB:
171 case PIPE_FORMAT_L16_UNORM:
172 case PIPE_FORMAT_L16_SNORM:
173 case PIPE_FORMAT_L16_UINT:
174 case PIPE_FORMAT_L16_SINT:
175 case PIPE_FORMAT_L16_FLOAT:
176 case PIPE_FORMAT_L32_UINT:
177 case PIPE_FORMAT_L32_SINT:
178 case PIPE_FORMAT_L32_FLOAT:
179 case PIPE_FORMAT_I16_UNORM:
180 case PIPE_FORMAT_I16_SNORM:
181 case PIPE_FORMAT_I16_UINT:
182 case PIPE_FORMAT_I16_SINT:
183 case PIPE_FORMAT_I16_FLOAT:
184 case PIPE_FORMAT_I32_UINT:
185 case PIPE_FORMAT_I32_SINT:
186 case PIPE_FORMAT_I32_FLOAT:
187 case PIPE_FORMAT_R8_UNORM:
188 case PIPE_FORMAT_R8_SNORM:
189 case PIPE_FORMAT_R8_UINT:
190 case PIPE_FORMAT_R8_SINT:
191 return V_0280A0_SWAP_STD;
192
193 case PIPE_FORMAT_L4A4_UNORM:
194 case PIPE_FORMAT_A4R4_UNORM:
195 return V_0280A0_SWAP_ALT;
196
197 /* 16-bit buffers. */
198 case PIPE_FORMAT_B5G6R5_UNORM:
199 return V_0280A0_SWAP_STD_REV;
200
201 case PIPE_FORMAT_B5G5R5A1_UNORM:
202 case PIPE_FORMAT_B5G5R5X1_UNORM:
203 return V_0280A0_SWAP_ALT;
204
205 case PIPE_FORMAT_B4G4R4A4_UNORM:
206 case PIPE_FORMAT_B4G4R4X4_UNORM:
207 return V_0280A0_SWAP_ALT;
208
209 case PIPE_FORMAT_Z16_UNORM:
210 return V_0280A0_SWAP_STD;
211
212 case PIPE_FORMAT_L8A8_UNORM:
213 case PIPE_FORMAT_L8A8_SNORM:
214 case PIPE_FORMAT_L8A8_UINT:
215 case PIPE_FORMAT_L8A8_SINT:
216 case PIPE_FORMAT_L8A8_SRGB:
217 case PIPE_FORMAT_L16A16_UNORM:
218 case PIPE_FORMAT_L16A16_SNORM:
219 case PIPE_FORMAT_L16A16_UINT:
220 case PIPE_FORMAT_L16A16_SINT:
221 case PIPE_FORMAT_L16A16_FLOAT:
222 case PIPE_FORMAT_L32A32_UINT:
223 case PIPE_FORMAT_L32A32_SINT:
224 case PIPE_FORMAT_L32A32_FLOAT:
225 case PIPE_FORMAT_R8A8_UNORM:
226 case PIPE_FORMAT_R8A8_SNORM:
227 case PIPE_FORMAT_R8A8_UINT:
228 case PIPE_FORMAT_R8A8_SINT:
229 case PIPE_FORMAT_R16A16_UNORM:
230 case PIPE_FORMAT_R16A16_SNORM:
231 case PIPE_FORMAT_R16A16_UINT:
232 case PIPE_FORMAT_R16A16_SINT:
233 case PIPE_FORMAT_R16A16_FLOAT:
234 case PIPE_FORMAT_R32A32_UINT:
235 case PIPE_FORMAT_R32A32_SINT:
236 case PIPE_FORMAT_R32A32_FLOAT:
237 return V_0280A0_SWAP_ALT;
238 case PIPE_FORMAT_R8G8_UNORM:
239 case PIPE_FORMAT_R8G8_SNORM:
240 case PIPE_FORMAT_R8G8_UINT:
241 case PIPE_FORMAT_R8G8_SINT:
242 return V_0280A0_SWAP_STD;
243
244 case PIPE_FORMAT_R16_UNORM:
245 case PIPE_FORMAT_R16_SNORM:
246 case PIPE_FORMAT_R16_UINT:
247 case PIPE_FORMAT_R16_SINT:
248 case PIPE_FORMAT_R16_FLOAT:
249 return V_0280A0_SWAP_STD;
250
251 /* 32-bit buffers. */
252
253 case PIPE_FORMAT_A8B8G8R8_SRGB:
254 return V_0280A0_SWAP_STD_REV;
255 case PIPE_FORMAT_B8G8R8A8_SRGB:
256 return V_0280A0_SWAP_ALT;
257
258 case PIPE_FORMAT_B8G8R8A8_UNORM:
259 case PIPE_FORMAT_B8G8R8X8_UNORM:
260 return V_0280A0_SWAP_ALT;
261
262 case PIPE_FORMAT_A8R8G8B8_UNORM:
263 case PIPE_FORMAT_X8R8G8B8_UNORM:
264 return V_0280A0_SWAP_ALT_REV;
265 case PIPE_FORMAT_R8G8B8A8_SNORM:
266 case PIPE_FORMAT_R8G8B8A8_UNORM:
267 case PIPE_FORMAT_R8G8B8X8_UNORM:
268 case PIPE_FORMAT_R8G8B8X8_SNORM:
269 case PIPE_FORMAT_R8G8B8X8_SRGB:
270 case PIPE_FORMAT_R8G8B8X8_UINT:
271 case PIPE_FORMAT_R8G8B8X8_SINT:
272 case PIPE_FORMAT_R8G8B8A8_SINT:
273 case PIPE_FORMAT_R8G8B8A8_UINT:
274 return V_0280A0_SWAP_STD;
275
276 case PIPE_FORMAT_A8B8G8R8_UNORM:
277 case PIPE_FORMAT_X8B8G8R8_UNORM:
278 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
279 return V_0280A0_SWAP_STD_REV;
280
281 case PIPE_FORMAT_Z24X8_UNORM:
282 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
283 return V_0280A0_SWAP_STD;
284
285 case PIPE_FORMAT_R10G10B10A2_UNORM:
286 case PIPE_FORMAT_R10G10B10X2_SNORM:
287 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
288 return V_0280A0_SWAP_STD;
289
290 case PIPE_FORMAT_B10G10R10A2_UNORM:
291 case PIPE_FORMAT_B10G10R10A2_UINT:
292 case PIPE_FORMAT_B10G10R10X2_UNORM:
293 return V_0280A0_SWAP_ALT;
294
295 case PIPE_FORMAT_R11G11B10_FLOAT:
296 case PIPE_FORMAT_R16G16_UNORM:
297 case PIPE_FORMAT_R16G16_SNORM:
298 case PIPE_FORMAT_R16G16_FLOAT:
299 case PIPE_FORMAT_R16G16_UINT:
300 case PIPE_FORMAT_R16G16_SINT:
301 case PIPE_FORMAT_R32_UINT:
302 case PIPE_FORMAT_R32_SINT:
303 case PIPE_FORMAT_R32_FLOAT:
304 case PIPE_FORMAT_Z32_FLOAT:
305 return V_0280A0_SWAP_STD;
306
307 /* 64-bit buffers. */
308 case PIPE_FORMAT_R32G32_FLOAT:
309 case PIPE_FORMAT_R32G32_UINT:
310 case PIPE_FORMAT_R32G32_SINT:
311 case PIPE_FORMAT_R16G16B16A16_UNORM:
312 case PIPE_FORMAT_R16G16B16A16_SNORM:
313 case PIPE_FORMAT_R16G16B16A16_UINT:
314 case PIPE_FORMAT_R16G16B16A16_SINT:
315 case PIPE_FORMAT_R16G16B16A16_FLOAT:
316 case PIPE_FORMAT_R16G16B16X16_UNORM:
317 case PIPE_FORMAT_R16G16B16X16_SNORM:
318 case PIPE_FORMAT_R16G16B16X16_FLOAT:
319 case PIPE_FORMAT_R16G16B16X16_UINT:
320 case PIPE_FORMAT_R16G16B16X16_SINT:
321 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
322
323 /* 128-bit buffers. */
324 case PIPE_FORMAT_R32G32B32A32_FLOAT:
325 case PIPE_FORMAT_R32G32B32A32_SNORM:
326 case PIPE_FORMAT_R32G32B32A32_UNORM:
327 case PIPE_FORMAT_R32G32B32A32_SINT:
328 case PIPE_FORMAT_R32G32B32A32_UINT:
329 case PIPE_FORMAT_R32G32B32X32_FLOAT:
330 case PIPE_FORMAT_R32G32B32X32_UINT:
331 case PIPE_FORMAT_R32G32B32X32_SINT:
332 return V_0280A0_SWAP_STD;
333 default:
334 R600_ERR("unsupported colorswap format %d\n", format);
335 return ~0U;
336 }
337 return ~0U;
338 }
339
340 static uint32_t r600_translate_colorformat(enum pipe_format format)
341 {
342 switch (format) {
343 case PIPE_FORMAT_L4A4_UNORM:
344 case PIPE_FORMAT_R4A4_UNORM:
345 case PIPE_FORMAT_A4R4_UNORM:
346 return V_0280A0_COLOR_4_4;
347
348 /* 8-bit buffers. */
349 case PIPE_FORMAT_A8_UNORM:
350 case PIPE_FORMAT_A8_SNORM:
351 case PIPE_FORMAT_A8_UINT:
352 case PIPE_FORMAT_A8_SINT:
353 case PIPE_FORMAT_I8_UNORM:
354 case PIPE_FORMAT_I8_SNORM:
355 case PIPE_FORMAT_I8_UINT:
356 case PIPE_FORMAT_I8_SINT:
357 case PIPE_FORMAT_L8_UNORM:
358 case PIPE_FORMAT_L8_SNORM:
359 case PIPE_FORMAT_L8_UINT:
360 case PIPE_FORMAT_L8_SINT:
361 case PIPE_FORMAT_L8_SRGB:
362 case PIPE_FORMAT_R8_UNORM:
363 case PIPE_FORMAT_R8_SNORM:
364 case PIPE_FORMAT_R8_UINT:
365 case PIPE_FORMAT_R8_SINT:
366 return V_0280A0_COLOR_8;
367
368 /* 16-bit buffers. */
369 case PIPE_FORMAT_B5G6R5_UNORM:
370 return V_0280A0_COLOR_5_6_5;
371
372 case PIPE_FORMAT_B5G5R5A1_UNORM:
373 case PIPE_FORMAT_B5G5R5X1_UNORM:
374 return V_0280A0_COLOR_1_5_5_5;
375
376 case PIPE_FORMAT_B4G4R4A4_UNORM:
377 case PIPE_FORMAT_B4G4R4X4_UNORM:
378 return V_0280A0_COLOR_4_4_4_4;
379
380 case PIPE_FORMAT_Z16_UNORM:
381 return V_0280A0_COLOR_16;
382
383 case PIPE_FORMAT_L8A8_UNORM:
384 case PIPE_FORMAT_L8A8_SNORM:
385 case PIPE_FORMAT_L8A8_UINT:
386 case PIPE_FORMAT_L8A8_SINT:
387 case PIPE_FORMAT_L8A8_SRGB:
388 case PIPE_FORMAT_R8G8_UNORM:
389 case PIPE_FORMAT_R8G8_SNORM:
390 case PIPE_FORMAT_R8G8_UINT:
391 case PIPE_FORMAT_R8G8_SINT:
392 case PIPE_FORMAT_R8A8_UNORM:
393 case PIPE_FORMAT_R8A8_SNORM:
394 case PIPE_FORMAT_R8A8_UINT:
395 case PIPE_FORMAT_R8A8_SINT:
396 return V_0280A0_COLOR_8_8;
397
398 case PIPE_FORMAT_R16_UNORM:
399 case PIPE_FORMAT_R16_SNORM:
400 case PIPE_FORMAT_R16_UINT:
401 case PIPE_FORMAT_R16_SINT:
402 case PIPE_FORMAT_A16_UNORM:
403 case PIPE_FORMAT_A16_SNORM:
404 case PIPE_FORMAT_A16_UINT:
405 case PIPE_FORMAT_A16_SINT:
406 case PIPE_FORMAT_L16_UNORM:
407 case PIPE_FORMAT_L16_SNORM:
408 case PIPE_FORMAT_L16_UINT:
409 case PIPE_FORMAT_L16_SINT:
410 case PIPE_FORMAT_I16_UNORM:
411 case PIPE_FORMAT_I16_SNORM:
412 case PIPE_FORMAT_I16_UINT:
413 case PIPE_FORMAT_I16_SINT:
414 return V_0280A0_COLOR_16;
415
416 case PIPE_FORMAT_R16_FLOAT:
417 case PIPE_FORMAT_A16_FLOAT:
418 case PIPE_FORMAT_L16_FLOAT:
419 case PIPE_FORMAT_I16_FLOAT:
420 return V_0280A0_COLOR_16_FLOAT;
421
422 /* 32-bit buffers. */
423 case PIPE_FORMAT_A8B8G8R8_SRGB:
424 case PIPE_FORMAT_A8B8G8R8_UNORM:
425 case PIPE_FORMAT_A8R8G8B8_UNORM:
426 case PIPE_FORMAT_B8G8R8A8_SRGB:
427 case PIPE_FORMAT_B8G8R8A8_UNORM:
428 case PIPE_FORMAT_B8G8R8X8_UNORM:
429 case PIPE_FORMAT_R8G8B8A8_SNORM:
430 case PIPE_FORMAT_R8G8B8A8_UNORM:
431 case PIPE_FORMAT_R8G8B8X8_UNORM:
432 case PIPE_FORMAT_R8G8B8X8_SNORM:
433 case PIPE_FORMAT_R8G8B8X8_SRGB:
434 case PIPE_FORMAT_R8G8B8X8_UINT:
435 case PIPE_FORMAT_R8G8B8X8_SINT:
436 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
437 case PIPE_FORMAT_X8B8G8R8_UNORM:
438 case PIPE_FORMAT_X8R8G8B8_UNORM:
439 case PIPE_FORMAT_R8G8B8A8_SINT:
440 case PIPE_FORMAT_R8G8B8A8_UINT:
441 return V_0280A0_COLOR_8_8_8_8;
442
443 case PIPE_FORMAT_R10G10B10A2_UNORM:
444 case PIPE_FORMAT_R10G10B10X2_SNORM:
445 case PIPE_FORMAT_B10G10R10A2_UNORM:
446 case PIPE_FORMAT_B10G10R10A2_UINT:
447 case PIPE_FORMAT_B10G10R10X2_UNORM:
448 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
449 return V_0280A0_COLOR_2_10_10_10;
450
451 case PIPE_FORMAT_Z24X8_UNORM:
452 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
453 return V_0280A0_COLOR_8_24;
454
455 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
456 return V_0280A0_COLOR_X24_8_32_FLOAT;
457
458 case PIPE_FORMAT_R32_UINT:
459 case PIPE_FORMAT_R32_SINT:
460 case PIPE_FORMAT_A32_UINT:
461 case PIPE_FORMAT_A32_SINT:
462 case PIPE_FORMAT_L32_UINT:
463 case PIPE_FORMAT_L32_SINT:
464 case PIPE_FORMAT_I32_UINT:
465 case PIPE_FORMAT_I32_SINT:
466 return V_0280A0_COLOR_32;
467
468 case PIPE_FORMAT_R32_FLOAT:
469 case PIPE_FORMAT_A32_FLOAT:
470 case PIPE_FORMAT_L32_FLOAT:
471 case PIPE_FORMAT_I32_FLOAT:
472 case PIPE_FORMAT_Z32_FLOAT:
473 return V_0280A0_COLOR_32_FLOAT;
474
475 case PIPE_FORMAT_R16G16_FLOAT:
476 case PIPE_FORMAT_L16A16_FLOAT:
477 case PIPE_FORMAT_R16A16_FLOAT:
478 return V_0280A0_COLOR_16_16_FLOAT;
479
480 case PIPE_FORMAT_R16G16_UNORM:
481 case PIPE_FORMAT_R16G16_SNORM:
482 case PIPE_FORMAT_R16G16_UINT:
483 case PIPE_FORMAT_R16G16_SINT:
484 case PIPE_FORMAT_L16A16_UNORM:
485 case PIPE_FORMAT_L16A16_SNORM:
486 case PIPE_FORMAT_L16A16_UINT:
487 case PIPE_FORMAT_L16A16_SINT:
488 case PIPE_FORMAT_R16A16_UNORM:
489 case PIPE_FORMAT_R16A16_SNORM:
490 case PIPE_FORMAT_R16A16_UINT:
491 case PIPE_FORMAT_R16A16_SINT:
492 return V_0280A0_COLOR_16_16;
493
494 case PIPE_FORMAT_R11G11B10_FLOAT:
495 return V_0280A0_COLOR_10_11_11_FLOAT;
496
497 /* 64-bit buffers. */
498 case PIPE_FORMAT_R16G16B16A16_UINT:
499 case PIPE_FORMAT_R16G16B16A16_SINT:
500 case PIPE_FORMAT_R16G16B16A16_UNORM:
501 case PIPE_FORMAT_R16G16B16A16_SNORM:
502 case PIPE_FORMAT_R16G16B16X16_UNORM:
503 case PIPE_FORMAT_R16G16B16X16_SNORM:
504 case PIPE_FORMAT_R16G16B16X16_UINT:
505 case PIPE_FORMAT_R16G16B16X16_SINT:
506 return V_0280A0_COLOR_16_16_16_16;
507
508 case PIPE_FORMAT_R16G16B16A16_FLOAT:
509 case PIPE_FORMAT_R16G16B16X16_FLOAT:
510 return V_0280A0_COLOR_16_16_16_16_FLOAT;
511
512 case PIPE_FORMAT_R32G32_FLOAT:
513 case PIPE_FORMAT_L32A32_FLOAT:
514 case PIPE_FORMAT_R32A32_FLOAT:
515 return V_0280A0_COLOR_32_32_FLOAT;
516
517 case PIPE_FORMAT_R32G32_SINT:
518 case PIPE_FORMAT_R32G32_UINT:
519 case PIPE_FORMAT_L32A32_UINT:
520 case PIPE_FORMAT_L32A32_SINT:
521 return V_0280A0_COLOR_32_32;
522
523 /* 128-bit buffers. */
524 case PIPE_FORMAT_R32G32B32A32_FLOAT:
525 case PIPE_FORMAT_R32G32B32X32_FLOAT:
526 return V_0280A0_COLOR_32_32_32_32_FLOAT;
527 case PIPE_FORMAT_R32G32B32A32_SNORM:
528 case PIPE_FORMAT_R32G32B32A32_UNORM:
529 case PIPE_FORMAT_R32G32B32A32_SINT:
530 case PIPE_FORMAT_R32G32B32A32_UINT:
531 case PIPE_FORMAT_R32G32B32X32_UINT:
532 case PIPE_FORMAT_R32G32B32X32_SINT:
533 return V_0280A0_COLOR_32_32_32_32;
534
535 /* YUV buffers. */
536 case PIPE_FORMAT_UYVY:
537 case PIPE_FORMAT_YUYV:
538 default:
539 return ~0U; /* Unsupported. */
540 }
541 }
542
543 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
544 {
545 if (R600_BIG_ENDIAN) {
546 switch(colorformat) {
547 case V_0280A0_COLOR_4_4:
548 return ENDIAN_NONE;
549
550 /* 8-bit buffers. */
551 case V_0280A0_COLOR_8:
552 return ENDIAN_NONE;
553
554 /* 16-bit buffers. */
555 case V_0280A0_COLOR_5_6_5:
556 case V_0280A0_COLOR_1_5_5_5:
557 case V_0280A0_COLOR_4_4_4_4:
558 case V_0280A0_COLOR_16:
559 case V_0280A0_COLOR_8_8:
560 return ENDIAN_8IN16;
561
562 /* 32-bit buffers. */
563 case V_0280A0_COLOR_8_8_8_8:
564 case V_0280A0_COLOR_2_10_10_10:
565 case V_0280A0_COLOR_8_24:
566 case V_0280A0_COLOR_24_8:
567 case V_0280A0_COLOR_32_FLOAT:
568 case V_0280A0_COLOR_16_16_FLOAT:
569 case V_0280A0_COLOR_16_16:
570 return ENDIAN_8IN32;
571
572 /* 64-bit buffers. */
573 case V_0280A0_COLOR_16_16_16_16:
574 case V_0280A0_COLOR_16_16_16_16_FLOAT:
575 return ENDIAN_8IN16;
576
577 case V_0280A0_COLOR_32_32_FLOAT:
578 case V_0280A0_COLOR_32_32:
579 case V_0280A0_COLOR_X24_8_32_FLOAT:
580 return ENDIAN_8IN32;
581
582 /* 128-bit buffers. */
583 case V_0280A0_COLOR_32_32_32_FLOAT:
584 case V_0280A0_COLOR_32_32_32_32_FLOAT:
585 case V_0280A0_COLOR_32_32_32_32:
586 return ENDIAN_8IN32;
587 default:
588 return ENDIAN_NONE; /* Unsupported. */
589 }
590 } else {
591 return ENDIAN_NONE;
592 }
593 }
594
595 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
596 {
597 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
598 }
599
600 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
601 {
602 return r600_translate_colorformat(format) != ~0U &&
603 r600_translate_colorswap(format) != ~0U;
604 }
605
606 static bool r600_is_zs_format_supported(enum pipe_format format)
607 {
608 return r600_translate_dbformat(format) != ~0U;
609 }
610
611 boolean r600_is_format_supported(struct pipe_screen *screen,
612 enum pipe_format format,
613 enum pipe_texture_target target,
614 unsigned sample_count,
615 unsigned usage)
616 {
617 struct r600_screen *rscreen = (struct r600_screen*)screen;
618 unsigned retval = 0;
619
620 if (target >= PIPE_MAX_TEXTURE_TYPES) {
621 R600_ERR("r600: unsupported texture type %d\n", target);
622 return FALSE;
623 }
624
625 if (!util_format_is_supported(format, usage))
626 return FALSE;
627
628 if (sample_count > 1) {
629 if (!rscreen->has_msaa)
630 return FALSE;
631
632 /* R11G11B10 is broken on R6xx. */
633 if (rscreen->b.chip_class == R600 &&
634 format == PIPE_FORMAT_R11G11B10_FLOAT)
635 return FALSE;
636
637 /* MSAA integer colorbuffers hang. */
638 if (util_format_is_pure_integer(format) &&
639 !util_format_is_depth_or_stencil(format))
640 return FALSE;
641
642 switch (sample_count) {
643 case 2:
644 case 4:
645 case 8:
646 break;
647 default:
648 return FALSE;
649 }
650 }
651
652 if (usage & PIPE_BIND_SAMPLER_VIEW) {
653 if (target == PIPE_BUFFER) {
654 if (r600_is_vertex_format_supported(format))
655 retval |= PIPE_BIND_SAMPLER_VIEW;
656 } else {
657 if (r600_is_sampler_format_supported(screen, format))
658 retval |= PIPE_BIND_SAMPLER_VIEW;
659 }
660 }
661
662 if ((usage & (PIPE_BIND_RENDER_TARGET |
663 PIPE_BIND_DISPLAY_TARGET |
664 PIPE_BIND_SCANOUT |
665 PIPE_BIND_SHARED)) &&
666 r600_is_colorbuffer_format_supported(format)) {
667 retval |= usage &
668 (PIPE_BIND_RENDER_TARGET |
669 PIPE_BIND_DISPLAY_TARGET |
670 PIPE_BIND_SCANOUT |
671 PIPE_BIND_SHARED);
672 }
673
674 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
675 r600_is_zs_format_supported(format)) {
676 retval |= PIPE_BIND_DEPTH_STENCIL;
677 }
678
679 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
680 r600_is_vertex_format_supported(format)) {
681 retval |= PIPE_BIND_VERTEX_BUFFER;
682 }
683
684 if (usage & PIPE_BIND_TRANSFER_READ)
685 retval |= PIPE_BIND_TRANSFER_READ;
686 if (usage & PIPE_BIND_TRANSFER_WRITE)
687 retval |= PIPE_BIND_TRANSFER_WRITE;
688
689 return retval == usage;
690 }
691
692 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
693 {
694 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
695 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
696 float offset_units = state->offset_units;
697 float offset_scale = state->offset_scale;
698
699 switch (state->zs_format) {
700 case PIPE_FORMAT_Z24X8_UNORM:
701 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
702 offset_units *= 2.0f;
703 break;
704 case PIPE_FORMAT_Z16_UNORM:
705 offset_units *= 4.0f;
706 break;
707 default:;
708 }
709
710 r600_write_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
711 radeon_emit(cs, fui(offset_scale));
712 radeon_emit(cs, fui(offset_units));
713 radeon_emit(cs, fui(offset_scale));
714 radeon_emit(cs, fui(offset_units));
715 }
716
717 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
718 {
719 int j = state->independent_blend_enable ? i : 0;
720
721 unsigned eqRGB = state->rt[j].rgb_func;
722 unsigned srcRGB = state->rt[j].rgb_src_factor;
723 unsigned dstRGB = state->rt[j].rgb_dst_factor;
724
725 unsigned eqA = state->rt[j].alpha_func;
726 unsigned srcA = state->rt[j].alpha_src_factor;
727 unsigned dstA = state->rt[j].alpha_dst_factor;
728 uint32_t bc = 0;
729
730 if (!state->rt[j].blend_enable)
731 return 0;
732
733 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
734 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
735 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
736
737 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
738 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
739 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
740 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
741 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
742 }
743 return bc;
744 }
745
746 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
747 const struct pipe_blend_state *state,
748 int mode)
749 {
750 struct r600_context *rctx = (struct r600_context *)ctx;
751 uint32_t color_control = 0, target_mask = 0;
752 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
753
754 if (!blend) {
755 return NULL;
756 }
757
758 r600_init_command_buffer(&blend->buffer, 20);
759 r600_init_command_buffer(&blend->buffer_no_blend, 20);
760
761 /* R600 does not support per-MRT blends */
762 if (rctx->b.family > CHIP_R600)
763 color_control |= S_028808_PER_MRT_BLEND(1);
764
765 if (state->logicop_enable) {
766 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
767 } else {
768 color_control |= (0xcc << 16);
769 }
770 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
771 if (state->independent_blend_enable) {
772 for (int i = 0; i < 8; i++) {
773 if (state->rt[i].blend_enable) {
774 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
775 }
776 target_mask |= (state->rt[i].colormask << (4 * i));
777 }
778 } else {
779 for (int i = 0; i < 8; i++) {
780 if (state->rt[0].blend_enable) {
781 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
782 }
783 target_mask |= (state->rt[0].colormask << (4 * i));
784 }
785 }
786
787 if (target_mask)
788 color_control |= S_028808_SPECIAL_OP(mode);
789 else
790 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
791
792 /* only MRT0 has dual src blend */
793 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
794 blend->cb_target_mask = target_mask;
795 blend->cb_color_control = color_control;
796 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
797 blend->alpha_to_one = state->alpha_to_one;
798
799 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
800 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
801 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
802 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
803 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
804 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
805
806 /* Copy over the registers set so far into buffer_no_blend. */
807 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
808 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
809
810 /* Only add blend registers if blending is enabled. */
811 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
812 return blend;
813 }
814
815 /* The first R600 does not support per-MRT blends */
816 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
817 r600_get_blend_control(state, 0));
818
819 if (rctx->b.family > CHIP_R600) {
820 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
821 for (int i = 0; i < 8; i++) {
822 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
823 }
824 }
825 return blend;
826 }
827
828 static void *r600_create_blend_state(struct pipe_context *ctx,
829 const struct pipe_blend_state *state)
830 {
831 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
832 }
833
834 static void *r600_create_dsa_state(struct pipe_context *ctx,
835 const struct pipe_depth_stencil_alpha_state *state)
836 {
837 unsigned db_depth_control, alpha_test_control, alpha_ref;
838 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
839
840 if (dsa == NULL) {
841 return NULL;
842 }
843
844 r600_init_command_buffer(&dsa->buffer, 3);
845
846 dsa->valuemask[0] = state->stencil[0].valuemask;
847 dsa->valuemask[1] = state->stencil[1].valuemask;
848 dsa->writemask[0] = state->stencil[0].writemask;
849 dsa->writemask[1] = state->stencil[1].writemask;
850 dsa->zwritemask = state->depth.writemask;
851
852 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
853 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
854 S_028800_ZFUNC(state->depth.func);
855
856 /* stencil */
857 if (state->stencil[0].enabled) {
858 db_depth_control |= S_028800_STENCIL_ENABLE(1);
859 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
860 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
861 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
862 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
863
864 if (state->stencil[1].enabled) {
865 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
866 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
867 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
868 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
869 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
870 }
871 }
872
873 /* alpha */
874 alpha_test_control = 0;
875 alpha_ref = 0;
876 if (state->alpha.enabled) {
877 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
878 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
879 alpha_ref = fui(state->alpha.ref_value);
880 }
881 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
882 dsa->alpha_ref = alpha_ref;
883
884 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
885 return dsa;
886 }
887
888 static void *r600_create_rs_state(struct pipe_context *ctx,
889 const struct pipe_rasterizer_state *state)
890 {
891 struct r600_context *rctx = (struct r600_context *)ctx;
892 unsigned tmp, sc_mode_cntl, spi_interp;
893 float psize_min, psize_max;
894 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
895
896 if (rs == NULL) {
897 return NULL;
898 }
899
900 r600_init_command_buffer(&rs->buffer, 30);
901
902 rs->flatshade = state->flatshade;
903 rs->sprite_coord_enable = state->sprite_coord_enable;
904 rs->two_side = state->light_twoside;
905 rs->clip_plane_enable = state->clip_plane_enable;
906 rs->pa_sc_line_stipple = state->line_stipple_enable ?
907 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
908 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
909 rs->pa_cl_clip_cntl =
910 S_028810_PS_UCP_MODE(3) |
911 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
912 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
913 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
914 rs->multisample_enable = state->multisample;
915
916 /* offset */
917 rs->offset_units = state->offset_units;
918 rs->offset_scale = state->offset_scale * 12.0f;
919 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
920
921 if (state->point_size_per_vertex) {
922 psize_min = util_get_min_point_size(state);
923 psize_max = 8192;
924 } else {
925 /* Force the point size to be as if the vertex output was disabled. */
926 psize_min = state->point_size;
927 psize_max = state->point_size;
928 }
929
930 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
931 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
932 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
933 if (rctx->b.chip_class >= R700) {
934 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
935 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
936 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
937 } else {
938 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
939 rs->scissor_enable = state->scissor;
940 }
941
942 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
943 if (state->sprite_coord_enable) {
944 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
945 S_0286D4_PNT_SPRITE_OVRD_X(2) |
946 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
947 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
948 S_0286D4_PNT_SPRITE_OVRD_W(1);
949 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
950 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
951 }
952 }
953
954 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
955 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
956 tmp = r600_pack_float_12p4(state->point_size/2);
957 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
958 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
959 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
960 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
961 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
962 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
963 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
964
965 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
966 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
967 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
968 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
969 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
970 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
971 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
972 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
973 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
974 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
975 S_028814_FACE(!state->front_ccw) |
976 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
977 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
978 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
979 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
980 state->fill_back != PIPE_POLYGON_MODE_FILL) |
981 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
982 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
983 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
984 return rs;
985 }
986
987 static void *r600_create_sampler_state(struct pipe_context *ctx,
988 const struct pipe_sampler_state *state)
989 {
990 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
991 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
992
993 if (ss == NULL) {
994 return NULL;
995 }
996
997 ss->seamless_cube_map = state->seamless_cube_map;
998 ss->border_color_use = sampler_state_needs_border_color(state);
999
1000 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
1001 ss->tex_sampler_words[0] =
1002 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1003 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1004 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1005 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1006 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1007 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1008 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1009 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1010 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
1011 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
1012 ss->tex_sampler_words[1] =
1013 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1014 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1015 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
1016 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
1017 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
1018
1019 if (ss->border_color_use) {
1020 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
1021 }
1022 return ss;
1023 }
1024
1025 static struct pipe_sampler_view *
1026 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
1027 unsigned width0, unsigned height0)
1028
1029 {
1030 struct pipe_context *ctx = view->base.context;
1031 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
1032 uint64_t va;
1033 int stride = util_format_get_blocksize(view->base.format);
1034 unsigned format, num_format, format_comp, endian;
1035 unsigned offset = view->base.u.buf.first_element * stride;
1036 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
1037
1038 r600_vertex_data_type(view->base.format,
1039 &format, &num_format, &format_comp,
1040 &endian);
1041
1042 va = r600_resource_va(ctx->screen, view->base.texture) + offset;
1043 view->tex_resource = &tmp->resource;
1044
1045 view->skip_mip_address_reloc = true;
1046 view->tex_resource_words[0] = va;
1047 view->tex_resource_words[1] = size - 1;
1048 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(va >> 32UL) |
1049 S_038008_STRIDE(stride) |
1050 S_038008_DATA_FORMAT(format) |
1051 S_038008_NUM_FORMAT_ALL(num_format) |
1052 S_038008_FORMAT_COMP_ALL(format_comp) |
1053 S_038008_SRF_MODE_ALL(1) |
1054 S_038008_ENDIAN_SWAP(endian);
1055 view->tex_resource_words[3] = 0;
1056 /*
1057 * in theory dword 4 is for number of elements, for use with resinfo,
1058 * but it seems to utterly fail to work, the amd gpu shader analyser
1059 * uses a const buffer to store the element sizes for buffer txq
1060 */
1061 view->tex_resource_words[4] = 0;
1062 view->tex_resource_words[5] = 0;
1063 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
1064 return &view->base;
1065 }
1066
1067 struct pipe_sampler_view *
1068 r600_create_sampler_view_custom(struct pipe_context *ctx,
1069 struct pipe_resource *texture,
1070 const struct pipe_sampler_view *state,
1071 unsigned width_first_level, unsigned height_first_level)
1072 {
1073 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1074 struct r600_texture *tmp = (struct r600_texture*)texture;
1075 unsigned format, endian;
1076 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1077 unsigned char swizzle[4], array_mode = 0;
1078 unsigned width, height, depth, offset_level, last_level;
1079
1080 if (view == NULL)
1081 return NULL;
1082
1083 /* initialize base object */
1084 view->base = *state;
1085 view->base.texture = NULL;
1086 pipe_reference(NULL, &texture->reference);
1087 view->base.texture = texture;
1088 view->base.reference.count = 1;
1089 view->base.context = ctx;
1090
1091 if (texture->target == PIPE_BUFFER)
1092 return texture_buffer_sampler_view(view, texture->width0, 1);
1093
1094 swizzle[0] = state->swizzle_r;
1095 swizzle[1] = state->swizzle_g;
1096 swizzle[2] = state->swizzle_b;
1097 swizzle[3] = state->swizzle_a;
1098
1099 format = r600_translate_texformat(ctx->screen, state->format,
1100 swizzle,
1101 &word4, &yuv_format);
1102 assert(format != ~0);
1103 if (format == ~0) {
1104 FREE(view);
1105 return NULL;
1106 }
1107
1108 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
1109 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1110 FREE(view);
1111 return NULL;
1112 }
1113 tmp = tmp->flushed_depth_texture;
1114 }
1115
1116 endian = r600_colorformat_endian_swap(format);
1117
1118 offset_level = state->u.tex.first_level;
1119 last_level = state->u.tex.last_level - offset_level;
1120 width = width_first_level;
1121 height = height_first_level;
1122 depth = u_minify(texture->depth0, offset_level);
1123 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1124
1125 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1126 height = 1;
1127 depth = texture->array_size;
1128 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1129 depth = texture->array_size;
1130 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
1131 depth = texture->array_size / 6;
1132 switch (tmp->surface.level[offset_level].mode) {
1133 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1134 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1135 break;
1136 case RADEON_SURF_MODE_1D:
1137 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1138 break;
1139 case RADEON_SURF_MODE_2D:
1140 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1141 break;
1142 case RADEON_SURF_MODE_LINEAR:
1143 default:
1144 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1145 break;
1146 }
1147
1148 view->tex_resource = &tmp->resource;
1149 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1150 S_038000_TILE_MODE(array_mode) |
1151 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
1152 S_038000_PITCH((pitch / 8) - 1) |
1153 S_038000_TEX_WIDTH(width - 1));
1154 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1155 S_038004_TEX_DEPTH(depth - 1) |
1156 S_038004_DATA_FORMAT(format));
1157 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1158 if (offset_level >= tmp->surface.last_level) {
1159 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1160 } else {
1161 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1162 }
1163 view->tex_resource_words[4] = (word4 |
1164 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1165 S_038010_REQUEST_SIZE(1) |
1166 S_038010_ENDIAN_SWAP(endian) |
1167 S_038010_BASE_LEVEL(0));
1168 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1169 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1170 if (texture->nr_samples > 1) {
1171 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1172 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1173 } else {
1174 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
1175 }
1176 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1177 S_038018_MAX_ANISO(4 /* max 16 samples */));
1178 return &view->base;
1179 }
1180
1181 static struct pipe_sampler_view *
1182 r600_create_sampler_view(struct pipe_context *ctx,
1183 struct pipe_resource *tex,
1184 const struct pipe_sampler_view *state)
1185 {
1186 return r600_create_sampler_view_custom(ctx, tex, state,
1187 u_minify(tex->width0, state->u.tex.first_level),
1188 u_minify(tex->height0, state->u.tex.first_level));
1189 }
1190
1191 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1192 {
1193 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1194 struct pipe_clip_state *state = &rctx->clip_state.state;
1195
1196 r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
1197 radeon_emit_array(cs, (unsigned*)state, 6*4);
1198 }
1199
1200 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1201 const struct pipe_poly_stipple *state)
1202 {
1203 }
1204
1205 static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
1206 {
1207 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1208 struct pipe_scissor_state *state = &rctx->scissor.scissor;
1209
1210 if (rctx->b.chip_class != R600 || rctx->scissor.enable) {
1211 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1212 radeon_emit(cs, S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
1213 S_028240_WINDOW_OFFSET_DISABLE(1));
1214 radeon_emit(cs, S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy));
1215 } else {
1216 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1217 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1218 S_028240_WINDOW_OFFSET_DISABLE(1));
1219 radeon_emit(cs, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
1220 }
1221 }
1222
1223 static void r600_set_scissor_states(struct pipe_context *ctx,
1224 unsigned start_slot,
1225 unsigned num_scissors,
1226 const struct pipe_scissor_state *state)
1227 {
1228 struct r600_context *rctx = (struct r600_context *)ctx;
1229
1230 rctx->scissor.scissor = *state;
1231
1232 if (rctx->b.chip_class == R600 && !rctx->scissor.enable)
1233 return;
1234
1235 rctx->scissor.atom.dirty = true;
1236 }
1237
1238 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
1239 unsigned size, unsigned alignment)
1240 {
1241 struct pipe_resource buffer;
1242
1243 memset(&buffer, 0, sizeof buffer);
1244 buffer.target = PIPE_BUFFER;
1245 buffer.format = PIPE_FORMAT_R8_UNORM;
1246 buffer.bind = PIPE_BIND_CUSTOM;
1247 buffer.usage = PIPE_USAGE_DEFAULT;
1248 buffer.flags = 0;
1249 buffer.width0 = size;
1250 buffer.height0 = 1;
1251 buffer.depth0 = 1;
1252 buffer.array_size = 1;
1253
1254 return (struct r600_resource*)
1255 r600_buffer_create(&rscreen->b.b, &buffer, alignment);
1256 }
1257
1258 static void r600_init_color_surface(struct r600_context *rctx,
1259 struct r600_surface *surf,
1260 bool force_cmask_fmask)
1261 {
1262 struct r600_screen *rscreen = rctx->screen;
1263 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1264 unsigned level = surf->base.u.tex.level;
1265 unsigned pitch, slice;
1266 unsigned color_info;
1267 unsigned color_view;
1268 unsigned format, swap, ntype, endian;
1269 unsigned offset;
1270 const struct util_format_description *desc;
1271 int i;
1272 bool blend_bypass = 0, blend_clamp = 1;
1273
1274 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
1275 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
1276 rtex = rtex->flushed_depth_texture;
1277 assert(rtex);
1278 }
1279
1280 offset = rtex->surface.level[level].offset;
1281 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1282 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1283 offset += rtex->surface.level[level].slice_size *
1284 surf->base.u.tex.first_layer;
1285 color_view = 0;
1286 } else
1287 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1288 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1289
1290 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1291 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1292 if (slice) {
1293 slice = slice - 1;
1294 }
1295 color_info = 0;
1296 switch (rtex->surface.level[level].mode) {
1297 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1298 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1299 break;
1300 case RADEON_SURF_MODE_1D:
1301 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1302 break;
1303 case RADEON_SURF_MODE_2D:
1304 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1305 break;
1306 case RADEON_SURF_MODE_LINEAR:
1307 default:
1308 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1309 break;
1310 }
1311
1312 desc = util_format_description(surf->base.format);
1313
1314 for (i = 0; i < 4; i++) {
1315 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1316 break;
1317 }
1318 }
1319
1320 ntype = V_0280A0_NUMBER_UNORM;
1321 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1322 ntype = V_0280A0_NUMBER_SRGB;
1323 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1324 if (desc->channel[i].normalized)
1325 ntype = V_0280A0_NUMBER_SNORM;
1326 else if (desc->channel[i].pure_integer)
1327 ntype = V_0280A0_NUMBER_SINT;
1328 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1329 if (desc->channel[i].normalized)
1330 ntype = V_0280A0_NUMBER_UNORM;
1331 else if (desc->channel[i].pure_integer)
1332 ntype = V_0280A0_NUMBER_UINT;
1333 }
1334
1335 format = r600_translate_colorformat(surf->base.format);
1336 assert(format != ~0);
1337
1338 swap = r600_translate_colorswap(surf->base.format);
1339 assert(swap != ~0);
1340
1341 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1342 endian = ENDIAN_NONE;
1343 } else {
1344 endian = r600_colorformat_endian_swap(format);
1345 }
1346
1347 /* set blend bypass according to docs if SINT/UINT or
1348 8/24 COLOR variants */
1349 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1350 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1351 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1352 blend_clamp = 0;
1353 blend_bypass = 1;
1354 }
1355
1356 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1357
1358 color_info |= S_0280A0_FORMAT(format) |
1359 S_0280A0_COMP_SWAP(swap) |
1360 S_0280A0_BLEND_BYPASS(blend_bypass) |
1361 S_0280A0_BLEND_CLAMP(blend_clamp) |
1362 S_0280A0_NUMBER_TYPE(ntype) |
1363 S_0280A0_ENDIAN(endian);
1364
1365 /* EXPORT_NORM is an optimzation that can be enabled for better
1366 * performance in certain cases
1367 */
1368 if (rctx->b.chip_class == R600) {
1369 /* EXPORT_NORM can be enabled if:
1370 * - 11-bit or smaller UNORM/SNORM/SRGB
1371 * - BLEND_CLAMP is enabled
1372 * - BLEND_FLOAT32 is disabled
1373 */
1374 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1375 (desc->channel[i].size < 12 &&
1376 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1377 ntype != V_0280A0_NUMBER_UINT &&
1378 ntype != V_0280A0_NUMBER_SINT) &&
1379 G_0280A0_BLEND_CLAMP(color_info) &&
1380 !G_0280A0_BLEND_FLOAT32(color_info)) {
1381 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1382 surf->export_16bpc = true;
1383 }
1384 } else {
1385 /* EXPORT_NORM can be enabled if:
1386 * - 11-bit or smaller UNORM/SNORM/SRGB
1387 * - 16-bit or smaller FLOAT
1388 */
1389 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1390 ((desc->channel[i].size < 12 &&
1391 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1392 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1393 (desc->channel[i].size < 17 &&
1394 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1395 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1396 surf->export_16bpc = true;
1397 }
1398 }
1399
1400 /* These might not always be initialized to zero. */
1401 surf->cb_color_base = offset >> 8;
1402 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1403 S_028060_SLICE_TILE_MAX(slice);
1404 surf->cb_color_fmask = surf->cb_color_base;
1405 surf->cb_color_cmask = surf->cb_color_base;
1406 surf->cb_color_mask = 0;
1407
1408 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1409 &rtex->resource.b.b);
1410 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1411 &rtex->resource.b.b);
1412
1413 if (rtex->cmask.size) {
1414 surf->cb_color_cmask = rtex->cmask.offset >> 8;
1415 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
1416
1417 if (rtex->fmask.size) {
1418 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1419 surf->cb_color_fmask = rtex->fmask.offset >> 8;
1420 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
1421 } else { /* cmask only */
1422 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1423 }
1424 } else if (force_cmask_fmask) {
1425 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1426 *
1427 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1428 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1429 * because it's not an MSAA buffer.
1430 */
1431 struct r600_cmask_info cmask;
1432 struct r600_fmask_info fmask;
1433
1434 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
1435 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
1436
1437 /* CMASK. */
1438 if (!rctx->dummy_cmask ||
1439 rctx->dummy_cmask->buf->size < cmask.size ||
1440 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1441 struct pipe_transfer *transfer;
1442 void *ptr;
1443
1444 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1445 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1446
1447 /* Set the contents to 0xCC. */
1448 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1449 memset(ptr, 0xCC, cmask.size);
1450 pipe_buffer_unmap(&rctx->b.b, transfer);
1451 }
1452 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1453 &rctx->dummy_cmask->b.b);
1454
1455 /* FMASK. */
1456 if (!rctx->dummy_fmask ||
1457 rctx->dummy_fmask->buf->size < fmask.size ||
1458 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1459 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1460 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1461
1462 }
1463 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1464 &rctx->dummy_fmask->b.b);
1465
1466 /* Init the registers. */
1467 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1468 surf->cb_color_cmask = 0;
1469 surf->cb_color_fmask = 0;
1470 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1471 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1472 }
1473
1474 surf->cb_color_info = color_info;
1475 surf->cb_color_view = color_view;
1476 surf->color_initialized = true;
1477 }
1478
1479 static void r600_init_depth_surface(struct r600_context *rctx,
1480 struct r600_surface *surf)
1481 {
1482 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1483 unsigned level, pitch, slice, format, offset, array_mode;
1484
1485 level = surf->base.u.tex.level;
1486 offset = rtex->surface.level[level].offset;
1487 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1488 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1489 if (slice) {
1490 slice = slice - 1;
1491 }
1492 switch (rtex->surface.level[level].mode) {
1493 case RADEON_SURF_MODE_2D:
1494 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1495 break;
1496 case RADEON_SURF_MODE_1D:
1497 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1498 case RADEON_SURF_MODE_LINEAR:
1499 default:
1500 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1501 break;
1502 }
1503
1504 format = r600_translate_dbformat(surf->base.format);
1505 assert(format != ~0);
1506
1507 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1508 surf->db_depth_base = offset >> 8;
1509 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1510 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1511 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1512 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1513
1514 switch (surf->base.format) {
1515 case PIPE_FORMAT_Z24X8_UNORM:
1516 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1517 surf->pa_su_poly_offset_db_fmt_cntl =
1518 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1519 break;
1520 case PIPE_FORMAT_Z32_FLOAT:
1521 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1522 surf->pa_su_poly_offset_db_fmt_cntl =
1523 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1524 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1525 break;
1526 case PIPE_FORMAT_Z16_UNORM:
1527 surf->pa_su_poly_offset_db_fmt_cntl =
1528 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1529 break;
1530 default:;
1531 }
1532
1533 surf->htile_enabled = 0;
1534 /* use htile only for first level */
1535 if (rtex->htile_buffer && !level) {
1536 uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b);
1537 surf->htile_enabled = 1;
1538 surf->db_htile_data_base = va >> 8;
1539 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1540 S_028D24_HTILE_HEIGHT(1) |
1541 S_028D24_FULL_CACHE(1) |
1542 S_028D24_LINEAR(1);
1543 /* preload is not working properly on r6xx/r7xx */
1544 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1545 }
1546
1547 surf->depth_initialized = true;
1548 }
1549
1550 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1551 const struct pipe_framebuffer_state *state)
1552 {
1553 struct r600_context *rctx = (struct r600_context *)ctx;
1554 struct r600_surface *surf;
1555 struct r600_texture *rtex;
1556 unsigned i;
1557
1558 if (rctx->framebuffer.state.nr_cbufs) {
1559 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1560 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1561 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1562 }
1563 if (rctx->framebuffer.state.zsbuf) {
1564 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1565 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1566
1567 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1568 if (rctx->b.chip_class >= R700 && rtex->htile_buffer) {
1569 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1570 }
1571 }
1572
1573 /* Set the new state. */
1574 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1575
1576 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1577 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1578 util_format_is_pure_integer(state->cbufs[0]->format);
1579 rctx->framebuffer.compressed_cb_mask = 0;
1580 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1581 state->cbufs[0] && state->cbufs[1] &&
1582 state->cbufs[0]->texture->nr_samples > 1 &&
1583 state->cbufs[1]->texture->nr_samples <= 1;
1584 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1585
1586 /* Colorbuffers. */
1587 for (i = 0; i < state->nr_cbufs; i++) {
1588 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1589 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1590 rctx->framebuffer.is_msaa_resolve &&
1591 i == 1;
1592
1593 surf = (struct r600_surface*)state->cbufs[i];
1594 if (!surf)
1595 continue;
1596
1597 rtex = (struct r600_texture*)surf->base.texture;
1598 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1599
1600 if (!surf->color_initialized || force_cmask_fmask) {
1601 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1602 if (force_cmask_fmask) {
1603 /* re-initialize later without compression */
1604 surf->color_initialized = false;
1605 }
1606 }
1607
1608 if (!surf->export_16bpc) {
1609 rctx->framebuffer.export_16bpc = false;
1610 }
1611
1612 if (rtex->fmask.size && rtex->cmask.size) {
1613 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1614 }
1615 }
1616
1617 /* Update alpha-test state dependencies.
1618 * Alpha-test is done on the first colorbuffer only. */
1619 if (state->nr_cbufs) {
1620 bool alphatest_bypass = false;
1621
1622 surf = (struct r600_surface*)state->cbufs[0];
1623 if (surf) {
1624 alphatest_bypass = surf->alphatest_bypass;
1625 }
1626
1627 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1628 rctx->alphatest_state.bypass = alphatest_bypass;
1629 rctx->alphatest_state.atom.dirty = true;
1630 }
1631 }
1632
1633 /* ZS buffer. */
1634 if (state->zsbuf) {
1635 surf = (struct r600_surface*)state->zsbuf;
1636
1637 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1638
1639 if (!surf->depth_initialized) {
1640 r600_init_depth_surface(rctx, surf);
1641 }
1642
1643 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1644 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1645 rctx->poly_offset_state.atom.dirty = true;
1646 }
1647
1648 if (rctx->db_state.rsurf != surf) {
1649 rctx->db_state.rsurf = surf;
1650 rctx->db_state.atom.dirty = true;
1651 rctx->db_misc_state.atom.dirty = true;
1652 }
1653 } else if (rctx->db_state.rsurf) {
1654 rctx->db_state.rsurf = NULL;
1655 rctx->db_state.atom.dirty = true;
1656 rctx->db_misc_state.atom.dirty = true;
1657 }
1658
1659 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1660 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1661 rctx->cb_misc_state.atom.dirty = true;
1662 }
1663
1664 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1665 rctx->alphatest_state.bypass = false;
1666 rctx->alphatest_state.atom.dirty = true;
1667 }
1668
1669 /* Calculate the CS size. */
1670 rctx->framebuffer.atom.num_dw =
1671 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1672
1673 if (rctx->framebuffer.state.nr_cbufs) {
1674 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1675 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1676 }
1677 if (rctx->framebuffer.state.zsbuf) {
1678 rctx->framebuffer.atom.num_dw += 16;
1679 } else if (rctx->screen->b.info.drm_minor >= 18) {
1680 rctx->framebuffer.atom.num_dw += 3;
1681 }
1682 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1683 rctx->framebuffer.atom.num_dw += 2;
1684 }
1685
1686 rctx->framebuffer.atom.dirty = true;
1687 }
1688
1689 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1690 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1691 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1692 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1693 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1694
1695
1696 static uint32_t sample_locs_2x[] = {
1697 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1698 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1699 };
1700 static unsigned max_dist_2x = 4;
1701
1702 static uint32_t sample_locs_4x[] = {
1703 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1704 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1705 };
1706 static unsigned max_dist_4x = 6;
1707 static uint32_t sample_locs_8x[] = {
1708 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1709 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1710 };
1711 static unsigned max_dist_8x = 7;
1712
1713 static void r600_get_sample_position(struct pipe_context *ctx,
1714 unsigned sample_count,
1715 unsigned sample_index,
1716 float *out_value)
1717 {
1718 int offset, index;
1719 struct {
1720 int idx:4;
1721 } val;
1722 switch (sample_count) {
1723 case 1:
1724 default:
1725 out_value[0] = out_value[1] = 0.5;
1726 break;
1727 case 2:
1728 offset = 4 * (sample_index * 2);
1729 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1730 out_value[0] = (float)(val.idx + 8) / 16.0f;
1731 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1732 out_value[1] = (float)(val.idx + 8) / 16.0f;
1733 break;
1734 case 4:
1735 offset = 4 * (sample_index * 2);
1736 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1737 out_value[0] = (float)(val.idx + 8) / 16.0f;
1738 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1739 out_value[1] = (float)(val.idx + 8) / 16.0f;
1740 break;
1741 case 8:
1742 offset = 4 * (sample_index % 4 * 2);
1743 index = (sample_index / 4);
1744 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1745 out_value[0] = (float)(val.idx + 8) / 16.0f;
1746 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1747 out_value[1] = (float)(val.idx + 8) / 16.0f;
1748 break;
1749 }
1750 }
1751
1752 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1753 {
1754 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1755 unsigned max_dist = 0;
1756
1757 if (rctx->b.family == CHIP_R600) {
1758 switch (nr_samples) {
1759 default:
1760 nr_samples = 0;
1761 break;
1762 case 2:
1763 r600_write_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1764 max_dist = max_dist_2x;
1765 break;
1766 case 4:
1767 r600_write_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1768 max_dist = max_dist_4x;
1769 break;
1770 case 8:
1771 r600_write_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1772 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1773 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1774 max_dist = max_dist_8x;
1775 break;
1776 }
1777 } else {
1778 switch (nr_samples) {
1779 default:
1780 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1781 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1782 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1783 nr_samples = 0;
1784 break;
1785 case 2:
1786 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1787 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1788 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1789 max_dist = max_dist_2x;
1790 break;
1791 case 4:
1792 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1793 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1794 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1795 max_dist = max_dist_4x;
1796 break;
1797 case 8:
1798 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1799 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1800 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1801 max_dist = max_dist_8x;
1802 break;
1803 }
1804 }
1805
1806 if (nr_samples > 1) {
1807 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1808 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1809 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1810 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1811 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1812 } else {
1813 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1814 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1815 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1816 }
1817 }
1818
1819 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1820 {
1821 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1822 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1823 unsigned nr_cbufs = state->nr_cbufs;
1824 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1825 unsigned i, sbu = 0;
1826
1827 /* Colorbuffers. */
1828 r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1829 for (i = 0; i < nr_cbufs; i++) {
1830 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1831 }
1832 /* set CB_COLOR1_INFO for possible dual-src blending */
1833 if (i == 1 && cb[0]) {
1834 radeon_emit(cs, cb[0]->cb_color_info);
1835 i++;
1836 }
1837 for (; i < 8; i++) {
1838 radeon_emit(cs, 0);
1839 }
1840
1841 if (nr_cbufs) {
1842 for (i = 0; i < nr_cbufs; i++) {
1843 unsigned reloc;
1844
1845 if (!cb[i])
1846 continue;
1847
1848 /* COLOR_BASE */
1849 r600_write_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1850
1851 reloc = r600_context_bo_reloc(&rctx->b,
1852 &rctx->b.rings.gfx,
1853 (struct r600_resource*)cb[i]->base.texture,
1854 RADEON_USAGE_READWRITE);
1855 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1856 radeon_emit(cs, reloc);
1857
1858 /* FMASK */
1859 r600_write_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1860
1861 reloc = r600_context_bo_reloc(&rctx->b,
1862 &rctx->b.rings.gfx,
1863 cb[i]->cb_buffer_fmask,
1864 RADEON_USAGE_READWRITE);
1865 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1866 radeon_emit(cs, reloc);
1867
1868 /* CMASK */
1869 r600_write_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1870
1871 reloc = r600_context_bo_reloc(&rctx->b,
1872 &rctx->b.rings.gfx,
1873 cb[i]->cb_buffer_cmask,
1874 RADEON_USAGE_READWRITE);
1875 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1876 radeon_emit(cs, reloc);
1877 }
1878
1879 r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1880 for (i = 0; i < nr_cbufs; i++) {
1881 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1882 }
1883
1884 r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1885 for (i = 0; i < nr_cbufs; i++) {
1886 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1887 }
1888
1889 r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1890 for (i = 0; i < nr_cbufs; i++) {
1891 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1892 }
1893
1894 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1895 }
1896
1897 /* SURFACE_BASE_UPDATE */
1898 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1899 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1900 radeon_emit(cs, sbu);
1901 sbu = 0;
1902 }
1903
1904 /* Zbuffer. */
1905 if (state->zsbuf) {
1906 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1907 unsigned reloc = r600_context_bo_reloc(&rctx->b,
1908 &rctx->b.rings.gfx,
1909 (struct r600_resource*)state->zsbuf->texture,
1910 RADEON_USAGE_READWRITE);
1911
1912 r600_write_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1913 surf->pa_su_poly_offset_db_fmt_cntl);
1914
1915 r600_write_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1916 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1917 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1918 r600_write_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1919 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1920 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1921
1922 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1923 radeon_emit(cs, reloc);
1924
1925 r600_write_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1926
1927 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1928 } else if (rctx->screen->b.info.drm_minor >= 18) {
1929 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1930 * Older kernels are out of luck. */
1931 r600_write_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1932 }
1933
1934 /* SURFACE_BASE_UPDATE */
1935 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1936 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1937 radeon_emit(cs, sbu);
1938 sbu = 0;
1939 }
1940
1941 /* Framebuffer dimensions. */
1942 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1943 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1944 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1945 radeon_emit(cs, S_028244_BR_X(state->width) |
1946 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1947
1948 if (rctx->framebuffer.is_msaa_resolve) {
1949 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1950 } else {
1951 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1952 * will assure that the alpha-test will work even if there is
1953 * no colorbuffer bound. */
1954 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1955 (1ull << MAX2(nr_cbufs, 1)) - 1);
1956 }
1957
1958 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1959 }
1960
1961 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1962 {
1963 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1964 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1965
1966 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1967 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1968 if (rctx->b.chip_class == R600) {
1969 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1970 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1971 } else {
1972 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1973 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1974 }
1975 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1976 } else {
1977 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1978 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1979 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1980
1981 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1982 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1983 /* Always enable the first color output to make sure alpha-test works even without one. */
1984 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1985 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1986 a->cb_color_control |
1987 S_028808_MULTIWRITE_ENABLE(multiwrite));
1988 }
1989 }
1990
1991 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1992 {
1993 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1994 struct r600_db_state *a = (struct r600_db_state*)atom;
1995
1996 if (a->rsurf && a->rsurf->htile_enabled) {
1997 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1998 unsigned reloc_idx;
1999
2000 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2001 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
2002 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
2003 reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer, RADEON_USAGE_READWRITE);
2004 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
2005 cs->buf[cs->cdw++] = reloc_idx;
2006 } else {
2007 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
2008 }
2009 }
2010
2011 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2012 {
2013 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2014 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
2015 unsigned db_render_control = 0;
2016 unsigned db_render_override =
2017 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
2018 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
2019
2020 if (a->occlusion_query_enabled) {
2021 if (rctx->b.chip_class >= R700) {
2022 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
2023 }
2024 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
2025 }
2026 if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled) {
2027 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
2028 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
2029 /* This is to fix a lockup when hyperz and alpha test are enabled at
2030 * the same time somehow GPU get confuse on which order to pick for
2031 * z test
2032 */
2033 if (rctx->alphatest_state.sx_alpha_test_control) {
2034 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
2035 }
2036 } else {
2037 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
2038 }
2039 if (a->flush_depthstencil_through_cb) {
2040 assert(a->copy_depth || a->copy_stencil);
2041
2042 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
2043 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
2044 S_028D0C_COPY_CENTROID(1) |
2045 S_028D0C_COPY_SAMPLE(a->copy_sample);
2046 } else if (a->flush_depthstencil_in_place) {
2047 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(1) |
2048 S_028D0C_STENCIL_COMPRESS_DISABLE(1);
2049 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
2050 }
2051 if (a->htile_clear) {
2052 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
2053 }
2054
2055 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
2056 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
2057 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
2058 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
2059 }
2060
2061 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
2062 {
2063 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2064 struct r600_config_state *a = (struct r600_config_state*)atom;
2065
2066 r600_write_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
2067 r600_write_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
2068 }
2069
2070 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
2071 {
2072 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2073 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
2074
2075 while (dirty_mask) {
2076 struct pipe_vertex_buffer *vb;
2077 struct r600_resource *rbuffer;
2078 unsigned offset;
2079 unsigned buffer_index = u_bit_scan(&dirty_mask);
2080
2081 vb = &rctx->vertex_buffer_state.vb[buffer_index];
2082 rbuffer = (struct r600_resource*)vb->buffer;
2083 assert(rbuffer);
2084
2085 offset = vb->buffer_offset;
2086
2087 /* fetch resources start at index 320 */
2088 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
2089 radeon_emit(cs, (320 + buffer_index) * 7);
2090 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
2091 radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
2092 radeon_emit(cs, /* RESOURCEi_WORD2 */
2093 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2094 S_038008_STRIDE(vb->stride));
2095 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
2096 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2097 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2098 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
2099
2100 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2101 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
2102 }
2103 }
2104
2105 static void r600_emit_constant_buffers(struct r600_context *rctx,
2106 struct r600_constbuf_state *state,
2107 unsigned buffer_id_base,
2108 unsigned reg_alu_constbuf_size,
2109 unsigned reg_alu_const_cache)
2110 {
2111 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2112 uint32_t dirty_mask = state->dirty_mask;
2113
2114 while (dirty_mask) {
2115 struct pipe_constant_buffer *cb;
2116 struct r600_resource *rbuffer;
2117 unsigned offset;
2118 unsigned buffer_index = ffs(dirty_mask) - 1;
2119 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
2120 cb = &state->cb[buffer_index];
2121 rbuffer = (struct r600_resource*)cb->buffer;
2122 assert(rbuffer);
2123
2124 offset = cb->buffer_offset;
2125
2126 if (!gs_ring_buffer) {
2127 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
2128 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
2129 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
2130 }
2131
2132 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2133 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
2134
2135 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
2136 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
2137 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
2138 radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
2139 radeon_emit(cs, /* RESOURCEi_WORD2 */
2140 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
2141 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
2142 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
2143 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2144 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2145 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
2146
2147 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2148 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
2149
2150 dirty_mask &= ~(1 << buffer_index);
2151 }
2152 state->dirty_mask = 0;
2153 }
2154
2155 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2156 {
2157 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
2158 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2159 R_028980_ALU_CONST_CACHE_VS_0);
2160 }
2161
2162 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2163 {
2164 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
2165 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2166 R_0289C0_ALU_CONST_CACHE_GS_0);
2167 }
2168
2169 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2170 {
2171 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
2172 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2173 R_028940_ALU_CONST_CACHE_PS_0);
2174 }
2175
2176 static void r600_emit_sampler_views(struct r600_context *rctx,
2177 struct r600_samplerview_state *state,
2178 unsigned resource_id_base)
2179 {
2180 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2181 uint32_t dirty_mask = state->dirty_mask;
2182
2183 while (dirty_mask) {
2184 struct r600_pipe_sampler_view *rview;
2185 unsigned resource_index = u_bit_scan(&dirty_mask);
2186 unsigned reloc;
2187
2188 rview = state->views[resource_index];
2189 assert(rview);
2190
2191 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
2192 radeon_emit(cs, (resource_id_base + resource_index) * 7);
2193 radeon_emit_array(cs, rview->tex_resource_words, 7);
2194
2195 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
2196 RADEON_USAGE_READ);
2197 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2198 radeon_emit(cs, reloc);
2199 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2200 radeon_emit(cs, reloc);
2201 }
2202 state->dirty_mask = 0;
2203 }
2204
2205 /* Resource IDs:
2206 * PS: 0 .. +160
2207 * VS: 160 .. +160
2208 * FS: 320 .. +16
2209 * GS: 336 .. +160
2210 */
2211
2212 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2213 {
2214 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
2215 }
2216
2217 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2218 {
2219 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2220 }
2221
2222 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2223 {
2224 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2225 }
2226
2227 static void r600_emit_sampler_states(struct r600_context *rctx,
2228 struct r600_textures_info *texinfo,
2229 unsigned resource_id_base,
2230 unsigned border_color_reg)
2231 {
2232 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2233 uint32_t dirty_mask = texinfo->states.dirty_mask;
2234
2235 while (dirty_mask) {
2236 struct r600_pipe_sampler_state *rstate;
2237 struct r600_pipe_sampler_view *rview;
2238 unsigned i = u_bit_scan(&dirty_mask);
2239
2240 rstate = texinfo->states.states[i];
2241 assert(rstate);
2242 rview = texinfo->views.views[i];
2243
2244 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
2245 * filtering between layers.
2246 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
2247 */
2248 if (rview) {
2249 enum pipe_texture_target target = rview->base.texture->target;
2250 if (target == PIPE_TEXTURE_1D_ARRAY ||
2251 target == PIPE_TEXTURE_2D_ARRAY) {
2252 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
2253 texinfo->is_array_sampler[i] = true;
2254 } else {
2255 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
2256 texinfo->is_array_sampler[i] = false;
2257 }
2258 }
2259
2260 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2261 radeon_emit(cs, (resource_id_base + i) * 3);
2262 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2263
2264 if (rstate->border_color_use) {
2265 unsigned offset;
2266
2267 offset = border_color_reg;
2268 offset += i * 16;
2269 r600_write_config_reg_seq(cs, offset, 4);
2270 radeon_emit_array(cs, rstate->border_color.ui, 4);
2271 }
2272 }
2273 texinfo->states.dirty_mask = 0;
2274 }
2275
2276 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2277 {
2278 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
2279 }
2280
2281 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2282 {
2283 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
2284 }
2285
2286 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2287 {
2288 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
2289 }
2290
2291 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
2292 {
2293 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2294 unsigned tmp;
2295
2296 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
2297 S_009508_SYNC_GRADIENT(1) |
2298 S_009508_SYNC_WALKER(1) |
2299 S_009508_SYNC_ALIGNER(1);
2300 if (!rctx->seamless_cube_map.enabled) {
2301 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
2302 }
2303 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
2304 }
2305
2306 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2307 {
2308 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2309 uint8_t mask = s->sample_mask;
2310
2311 r600_write_context_reg(rctx->b.rings.gfx.cs, R_028C48_PA_SC_AA_MASK,
2312 mask | (mask << 8) | (mask << 16) | (mask << 24));
2313 }
2314
2315 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2316 {
2317 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2318 struct r600_cso_state *state = (struct r600_cso_state*)a;
2319 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2320
2321 r600_write_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
2322 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2323 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer, RADEON_USAGE_READ));
2324 }
2325
2326 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2327 {
2328 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2329 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2330
2331 uint32_t v2 = 0, primid = 0;
2332
2333 if (state->geom_enable) {
2334 uint32_t cut_val;
2335
2336 if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 128)
2337 cut_val = V_028A40_GS_CUT_128;
2338 else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 256)
2339 cut_val = V_028A40_GS_CUT_256;
2340 else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 512)
2341 cut_val = V_028A40_GS_CUT_512;
2342 else
2343 cut_val = V_028A40_GS_CUT_1024;
2344
2345 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2346 S_028A40_CUT_MODE(cut_val);
2347
2348 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2349 primid = 1;
2350 }
2351
2352 r600_write_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2353 r600_write_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2354 }
2355
2356 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2357 {
2358 struct pipe_screen *screen = rctx->b.b.screen;
2359 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2360 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2361 struct r600_resource *rbuffer;
2362
2363 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2364 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2365 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2366
2367 if (state->enable) {
2368 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2369 r600_write_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2370 (r600_resource_va(screen, &rbuffer->b.b)) >> 8);
2371 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2372 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READWRITE));
2373 r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2374 state->esgs_ring.buffer_size >> 8);
2375
2376 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2377 r600_write_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2378 (r600_resource_va(screen, &rbuffer->b.b)) >> 8);
2379 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2380 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READWRITE));
2381 r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2382 state->gsvs_ring.buffer_size >> 8);
2383 } else {
2384 r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2385 r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2386 }
2387
2388 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2389 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2390 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2391 }
2392
2393 /* Adjust GPR allocation on R6xx/R7xx */
2394 bool r600_adjust_gprs(struct r600_context *rctx)
2395 {
2396 unsigned num_ps_gprs = rctx->ps_shader->current->shader.bc.ngpr;
2397 unsigned num_vs_gprs, num_es_gprs, num_gs_gprs;
2398 unsigned new_num_ps_gprs = num_ps_gprs;
2399 unsigned new_num_vs_gprs, new_num_es_gprs, new_num_gs_gprs;
2400 unsigned cur_num_ps_gprs = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2401 unsigned cur_num_vs_gprs = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2402 unsigned cur_num_gs_gprs = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2403 unsigned cur_num_es_gprs = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2404 unsigned def_num_ps_gprs = rctx->default_ps_gprs;
2405 unsigned def_num_vs_gprs = rctx->default_vs_gprs;
2406 unsigned def_num_gs_gprs = 0;
2407 unsigned def_num_es_gprs = 0;
2408 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2409 /* hardware will reserve twice num_clause_temp_gprs */
2410 unsigned max_gprs = def_num_gs_gprs + def_num_es_gprs + def_num_ps_gprs + def_num_vs_gprs + def_num_clause_temp_gprs * 2;
2411 unsigned tmp, tmp2;
2412
2413 if (rctx->gs_shader) {
2414 num_es_gprs = rctx->vs_shader->current->shader.bc.ngpr;
2415 num_gs_gprs = rctx->gs_shader->current->shader.bc.ngpr;
2416 num_vs_gprs = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2417 } else {
2418 num_es_gprs = 0;
2419 num_gs_gprs = 0;
2420 num_vs_gprs = rctx->vs_shader->current->shader.bc.ngpr;
2421 }
2422 new_num_vs_gprs = num_vs_gprs;
2423 new_num_es_gprs = num_es_gprs;
2424 new_num_gs_gprs = num_gs_gprs;
2425
2426 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2427 if (new_num_ps_gprs > cur_num_ps_gprs || new_num_vs_gprs > cur_num_vs_gprs ||
2428 new_num_es_gprs > cur_num_es_gprs || new_num_gs_gprs > cur_num_gs_gprs) {
2429 /* try to use switch back to default */
2430 if (new_num_ps_gprs > def_num_ps_gprs || new_num_vs_gprs > def_num_vs_gprs ||
2431 new_num_gs_gprs > def_num_gs_gprs || new_num_es_gprs > def_num_es_gprs) {
2432 /* always privilege vs stage so that at worst we have the
2433 * pixel stage producing wrong output (not the vertex
2434 * stage) */
2435 new_num_ps_gprs = max_gprs - ((new_num_vs_gprs - new_num_es_gprs - new_num_gs_gprs) + def_num_clause_temp_gprs * 2);
2436 new_num_vs_gprs = num_vs_gprs;
2437 new_num_gs_gprs = num_gs_gprs;
2438 new_num_es_gprs = num_es_gprs;
2439 } else {
2440 new_num_ps_gprs = def_num_ps_gprs;
2441 new_num_vs_gprs = def_num_vs_gprs;
2442 new_num_es_gprs = def_num_es_gprs;
2443 new_num_gs_gprs = def_num_gs_gprs;
2444 }
2445 } else {
2446 return true;
2447 }
2448
2449 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2450 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2451 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2452 * it will lockup. So in this case just discard the draw command
2453 * and don't change the current gprs repartitions.
2454 */
2455 if (num_ps_gprs > new_num_ps_gprs || num_vs_gprs > new_num_vs_gprs ||
2456 num_gs_gprs > new_num_gs_gprs || num_es_gprs > new_num_es_gprs) {
2457 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2458 "for a combined maximum of %d\n",
2459 num_ps_gprs, num_vs_gprs, num_es_gprs, num_gs_gprs, max_gprs);
2460 return false;
2461 }
2462
2463 /* in some case we endup recomputing the current value */
2464 tmp = S_008C04_NUM_PS_GPRS(new_num_ps_gprs) |
2465 S_008C04_NUM_VS_GPRS(new_num_vs_gprs) |
2466 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2467
2468 tmp2 = S_008C08_NUM_ES_GPRS(new_num_es_gprs) |
2469 S_008C08_NUM_GS_GPRS(new_num_gs_gprs);
2470 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2471 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2472 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2473 rctx->config_state.atom.dirty = true;
2474 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2475 }
2476 return true;
2477 }
2478
2479 void r600_init_atom_start_cs(struct r600_context *rctx)
2480 {
2481 int ps_prio;
2482 int vs_prio;
2483 int gs_prio;
2484 int es_prio;
2485 int num_ps_gprs;
2486 int num_vs_gprs;
2487 int num_gs_gprs;
2488 int num_es_gprs;
2489 int num_temp_gprs;
2490 int num_ps_threads;
2491 int num_vs_threads;
2492 int num_gs_threads;
2493 int num_es_threads;
2494 int num_ps_stack_entries;
2495 int num_vs_stack_entries;
2496 int num_gs_stack_entries;
2497 int num_es_stack_entries;
2498 enum radeon_family family;
2499 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2500 uint32_t tmp;
2501
2502 r600_init_command_buffer(cb, 256);
2503
2504 /* R6xx requires this packet at the start of each command buffer */
2505 if (rctx->b.chip_class == R600) {
2506 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2507 r600_store_value(cb, 0);
2508 }
2509 /* All asics require this one */
2510 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2511 r600_store_value(cb, 0x80000000);
2512 r600_store_value(cb, 0x80000000);
2513
2514 /* We're setting config registers here. */
2515 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2516 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2517
2518 family = rctx->b.family;
2519 ps_prio = 0;
2520 vs_prio = 1;
2521 gs_prio = 2;
2522 es_prio = 3;
2523 switch (family) {
2524 case CHIP_R600:
2525 num_ps_gprs = 192;
2526 num_vs_gprs = 56;
2527 num_temp_gprs = 4;
2528 num_gs_gprs = 0;
2529 num_es_gprs = 0;
2530 num_ps_threads = 136;
2531 num_vs_threads = 48;
2532 num_gs_threads = 4;
2533 num_es_threads = 4;
2534 num_ps_stack_entries = 128;
2535 num_vs_stack_entries = 128;
2536 num_gs_stack_entries = 0;
2537 num_es_stack_entries = 0;
2538 break;
2539 case CHIP_RV630:
2540 case CHIP_RV635:
2541 num_ps_gprs = 84;
2542 num_vs_gprs = 36;
2543 num_temp_gprs = 4;
2544 num_gs_gprs = 0;
2545 num_es_gprs = 0;
2546 num_ps_threads = 144;
2547 num_vs_threads = 40;
2548 num_gs_threads = 4;
2549 num_es_threads = 4;
2550 num_ps_stack_entries = 40;
2551 num_vs_stack_entries = 40;
2552 num_gs_stack_entries = 32;
2553 num_es_stack_entries = 16;
2554 break;
2555 case CHIP_RV610:
2556 case CHIP_RV620:
2557 case CHIP_RS780:
2558 case CHIP_RS880:
2559 default:
2560 num_ps_gprs = 84;
2561 num_vs_gprs = 36;
2562 num_temp_gprs = 4;
2563 num_gs_gprs = 0;
2564 num_es_gprs = 0;
2565 num_ps_threads = 136;
2566 num_vs_threads = 48;
2567 num_gs_threads = 4;
2568 num_es_threads = 4;
2569 num_ps_stack_entries = 40;
2570 num_vs_stack_entries = 40;
2571 num_gs_stack_entries = 32;
2572 num_es_stack_entries = 16;
2573 break;
2574 case CHIP_RV670:
2575 num_ps_gprs = 144;
2576 num_vs_gprs = 40;
2577 num_temp_gprs = 4;
2578 num_gs_gprs = 0;
2579 num_es_gprs = 0;
2580 num_ps_threads = 136;
2581 num_vs_threads = 48;
2582 num_gs_threads = 4;
2583 num_es_threads = 4;
2584 num_ps_stack_entries = 40;
2585 num_vs_stack_entries = 40;
2586 num_gs_stack_entries = 32;
2587 num_es_stack_entries = 16;
2588 break;
2589 case CHIP_RV770:
2590 num_ps_gprs = 130;
2591 num_vs_gprs = 56;
2592 num_temp_gprs = 4;
2593 num_gs_gprs = 31;
2594 num_es_gprs = 31;
2595 num_ps_threads = 180;
2596 num_vs_threads = 60;
2597 num_gs_threads = 4;
2598 num_es_threads = 4;
2599 num_ps_stack_entries = 128;
2600 num_vs_stack_entries = 128;
2601 num_gs_stack_entries = 128;
2602 num_es_stack_entries = 128;
2603 break;
2604 case CHIP_RV730:
2605 case CHIP_RV740:
2606 num_ps_gprs = 84;
2607 num_vs_gprs = 36;
2608 num_temp_gprs = 4;
2609 num_gs_gprs = 0;
2610 num_es_gprs = 0;
2611 num_ps_threads = 180;
2612 num_vs_threads = 60;
2613 num_gs_threads = 4;
2614 num_es_threads = 4;
2615 num_ps_stack_entries = 128;
2616 num_vs_stack_entries = 128;
2617 num_gs_stack_entries = 0;
2618 num_es_stack_entries = 0;
2619 break;
2620 case CHIP_RV710:
2621 num_ps_gprs = 192;
2622 num_vs_gprs = 56;
2623 num_temp_gprs = 4;
2624 num_gs_gprs = 0;
2625 num_es_gprs = 0;
2626 num_ps_threads = 136;
2627 num_vs_threads = 48;
2628 num_gs_threads = 4;
2629 num_es_threads = 4;
2630 num_ps_stack_entries = 128;
2631 num_vs_stack_entries = 128;
2632 num_gs_stack_entries = 0;
2633 num_es_stack_entries = 0;
2634 break;
2635 }
2636
2637 rctx->default_ps_gprs = num_ps_gprs;
2638 rctx->default_vs_gprs = num_vs_gprs;
2639 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2640
2641 /* SQ_CONFIG */
2642 tmp = 0;
2643 switch (family) {
2644 case CHIP_RV610:
2645 case CHIP_RV620:
2646 case CHIP_RS780:
2647 case CHIP_RS880:
2648 case CHIP_RV710:
2649 break;
2650 default:
2651 tmp |= S_008C00_VC_ENABLE(1);
2652 break;
2653 }
2654 tmp |= S_008C00_DX9_CONSTS(0);
2655 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2656 tmp |= S_008C00_PS_PRIO(ps_prio);
2657 tmp |= S_008C00_VS_PRIO(vs_prio);
2658 tmp |= S_008C00_GS_PRIO(gs_prio);
2659 tmp |= S_008C00_ES_PRIO(es_prio);
2660 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2661
2662 /* SQ_GPR_RESOURCE_MGMT_2 */
2663 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2664 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2665 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2666 r600_store_value(cb, tmp);
2667
2668 /* SQ_THREAD_RESOURCE_MGMT */
2669 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2670 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2671 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2672 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2673 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2674
2675 /* SQ_STACK_RESOURCE_MGMT_1 */
2676 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2677 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2678 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2679
2680 /* SQ_STACK_RESOURCE_MGMT_2 */
2681 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2682 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2683 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2684
2685 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2686
2687 if (rctx->b.chip_class >= R700) {
2688 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2689 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2690 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2691 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2692 } else {
2693 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2694 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2695 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2696 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2697 }
2698 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2699 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2700 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2701 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2702 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2703 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2704 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2705 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2706 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2707 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2708
2709 /* to avoid GPU doing any preloading of constant from random address */
2710 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2711 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2712 r600_store_value(cb, 0);
2713 r600_store_value(cb, 0);
2714 r600_store_value(cb, 0);
2715 r600_store_value(cb, 0);
2716 r600_store_value(cb, 0);
2717 r600_store_value(cb, 0);
2718 r600_store_value(cb, 0);
2719 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2720 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2721 r600_store_value(cb, 0);
2722 r600_store_value(cb, 0);
2723 r600_store_value(cb, 0);
2724 r600_store_value(cb, 0);
2725 r600_store_value(cb, 0);
2726 r600_store_value(cb, 0);
2727 r600_store_value(cb, 0);
2728
2729 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2730 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2731 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2732 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2733 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2734 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2735 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2736 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2737 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2738 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2739 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2740 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2741 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2742 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2743
2744 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2745 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2746 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2747
2748 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2749 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2750 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2751 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2752
2753 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2754
2755 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2756
2757 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2758
2759 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2760 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2761 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2762 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2763
2764 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2765 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2766 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2767 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2768
2769 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2770 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2771
2772 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2773 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2774 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2775 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2776 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2777
2778 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2779 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2780 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2781
2782 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2783
2784 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2785 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2786
2787 if (rctx->b.chip_class >= R700) {
2788 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2789 }
2790
2791 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2792 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2793 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2794 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2795 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2796
2797 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2798 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2799 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2800
2801 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2802 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2803 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2804
2805 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2806 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2807 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2808 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2809 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2810 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2811
2812 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2813
2814 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2815 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2816 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2817
2818 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2819
2820 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2821 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2822 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2823 if (rctx->screen->b.has_streamout) {
2824 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2825 }
2826
2827 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2828 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2829 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2830 }
2831
2832 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2833 {
2834 struct r600_context *rctx = (struct r600_context *)ctx;
2835 struct r600_command_buffer *cb = &shader->command_buffer;
2836 struct r600_shader *rshader = &shader->shader;
2837 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2838 int pos_index = -1, face_index = -1;
2839 unsigned tmp, sid, ufi = 0;
2840 int need_linear = 0;
2841 unsigned z_export = 0, stencil_export = 0;
2842 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2843
2844 if (!cb->buf) {
2845 r600_init_command_buffer(cb, 64);
2846 } else {
2847 cb->num_dw = 0;
2848 }
2849
2850 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2851 for (i = 0; i < rshader->ninput; i++) {
2852 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2853 pos_index = i;
2854 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2855 face_index = i;
2856
2857 sid = rshader->input[i].spi_sid;
2858
2859 tmp = S_028644_SEMANTIC(sid);
2860
2861 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2862 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2863 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2864 rctx->rasterizer && rctx->rasterizer->flatshade))
2865 tmp |= S_028644_FLAT_SHADE(1);
2866
2867 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2868 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2869 tmp |= S_028644_PT_SPRITE_TEX(1);
2870 }
2871
2872 if (rshader->input[i].centroid)
2873 tmp |= S_028644_SEL_CENTROID(1);
2874
2875 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2876 need_linear = 1;
2877 tmp |= S_028644_SEL_LINEAR(1);
2878 }
2879
2880 r600_store_value(cb, tmp);
2881 }
2882
2883 db_shader_control = 0;
2884 for (i = 0; i < rshader->noutput; i++) {
2885 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2886 z_export = 1;
2887 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2888 stencil_export = 1;
2889 }
2890 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2891 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2892 if (rshader->uses_kill)
2893 db_shader_control |= S_02880C_KILL_ENABLE(1);
2894
2895 exports_ps = 0;
2896 for (i = 0; i < rshader->noutput; i++) {
2897 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2898 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2899 exports_ps |= 1;
2900 }
2901 }
2902 num_cout = rshader->nr_ps_color_exports;
2903 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2904 if (!exports_ps) {
2905 /* always at least export 1 component per pixel */
2906 exports_ps = 2;
2907 }
2908
2909 shader->nr_ps_color_outputs = num_cout;
2910
2911 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2912 S_0286CC_PERSP_GRADIENT_ENA(1)|
2913 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2914 spi_input_z = 0;
2915 if (pos_index != -1) {
2916 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2917 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2918 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2919 S_0286CC_BARYC_SAMPLE_CNTL(1));
2920 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2921 }
2922
2923 spi_ps_in_control_1 = 0;
2924 if (face_index != -1) {
2925 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2926 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2927 }
2928
2929 /* HW bug in original R600 */
2930 if (rctx->b.family == CHIP_R600)
2931 ufi = 1;
2932
2933 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2934 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2935 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2936
2937 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2938
2939 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2940 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2941 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2942 S_028850_STACK_SIZE(rshader->bc.nstack) |
2943 S_028850_UNCACHED_FIRST_INST(ufi));
2944 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2945
2946 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2947 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2948
2949 /* only set some bits here, the other bits are set in the dsa state */
2950 shader->db_shader_control = db_shader_control;
2951 shader->ps_depth_export = z_export | stencil_export;
2952
2953 shader->sprite_coord_enable = sprite_coord_enable;
2954 if (rctx->rasterizer)
2955 shader->flatshade = rctx->rasterizer->flatshade;
2956 }
2957
2958 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2959 {
2960 struct r600_command_buffer *cb = &shader->command_buffer;
2961 struct r600_shader *rshader = &shader->shader;
2962 unsigned spi_vs_out_id[10] = {};
2963 unsigned i, tmp, nparams = 0;
2964
2965 for (i = 0; i < rshader->noutput; i++) {
2966 if (rshader->output[i].spi_sid) {
2967 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2968 spi_vs_out_id[nparams / 4] |= tmp;
2969 nparams++;
2970 }
2971 }
2972
2973 r600_init_command_buffer(cb, 32);
2974
2975 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2976 for (i = 0; i < 10; i++) {
2977 r600_store_value(cb, spi_vs_out_id[i]);
2978 }
2979
2980 /* Certain attributes (position, psize, etc.) don't count as params.
2981 * VS is required to export at least one param and r600_shader_from_tgsi()
2982 * takes care of adding a dummy export.
2983 */
2984 if (nparams < 1)
2985 nparams = 1;
2986
2987 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2988 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2989 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2990 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2991 S_028868_STACK_SIZE(rshader->bc.nstack));
2992 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2993 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2994
2995 shader->pa_cl_vs_out_cntl =
2996 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2997 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2998 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2999 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
3000 }
3001
3002 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
3003 {
3004 static const int prim_conv[] = {
3005 V_028A6C_OUTPRIM_TYPE_POINTLIST,
3006 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
3007 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
3008 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
3009 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
3010 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
3011 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
3012 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
3013 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
3014 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
3015 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
3016 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
3017 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
3018 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
3019 V_028A6C_OUTPRIM_TYPE_TRISTRIP
3020 };
3021 assert(mode < Elements(prim_conv));
3022
3023 return prim_conv[mode];
3024 }
3025
3026 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3027 {
3028 struct r600_context *rctx = (struct r600_context *)ctx;
3029 struct r600_command_buffer *cb = &shader->command_buffer;
3030 struct r600_shader *rshader = &shader->shader;
3031 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3032 unsigned gsvs_itemsize =
3033 (cp_shader->ring_item_size * rshader->gs_max_out_vertices) >> 2;
3034
3035 r600_init_command_buffer(cb, 64);
3036
3037 /* VGT_GS_MODE is written by r600_emit_shader_stages */
3038 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
3039
3040 if (rctx->b.chip_class >= R700) {
3041 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3042 S_028B38_MAX_VERT_OUT(rshader->gs_max_out_vertices));
3043 }
3044 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3045 r600_conv_prim_to_gs_out(rshader->gs_output_prim));
3046
3047 r600_store_context_reg_seq(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE, 4);
3048 r600_store_value(cb, cp_shader->ring_item_size >> 2);
3049 r600_store_value(cb, 0);
3050 r600_store_value(cb, 0);
3051 r600_store_value(cb, 0);
3052
3053 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
3054 (rshader->ring_item_size) >> 2);
3055
3056 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
3057 gsvs_itemsize);
3058
3059 /* FIXME calculate these values somehow ??? */
3060 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
3061 r600_store_value(cb, 0x80); /* GS_PER_ES */
3062 r600_store_value(cb, 0x100); /* ES_PER_GS */
3063 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
3064 r600_store_value(cb, 0x2); /* GS_PER_VS */
3065
3066 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
3067 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
3068 S_02887C_STACK_SIZE(rshader->bc.nstack));
3069 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS,
3070 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
3071 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3072 }
3073
3074 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3075 {
3076 struct r600_command_buffer *cb = &shader->command_buffer;
3077 struct r600_shader *rshader = &shader->shader;
3078
3079 r600_init_command_buffer(cb, 32);
3080
3081 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3082 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3083 S_028890_STACK_SIZE(rshader->bc.nstack));
3084 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES,
3085 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
3086 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3087 }
3088
3089
3090 void *r600_create_resolve_blend(struct r600_context *rctx)
3091 {
3092 struct pipe_blend_state blend;
3093 unsigned i;
3094
3095 memset(&blend, 0, sizeof(blend));
3096 blend.independent_blend_enable = true;
3097 for (i = 0; i < 2; i++) {
3098 blend.rt[i].colormask = 0xf;
3099 blend.rt[i].blend_enable = 1;
3100 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
3101 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
3102 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
3103 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
3104 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
3105 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
3106 }
3107 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
3108 }
3109
3110 void *r700_create_resolve_blend(struct r600_context *rctx)
3111 {
3112 struct pipe_blend_state blend;
3113
3114 memset(&blend, 0, sizeof(blend));
3115 blend.independent_blend_enable = true;
3116 blend.rt[0].colormask = 0xf;
3117 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
3118 }
3119
3120 void *r600_create_decompress_blend(struct r600_context *rctx)
3121 {
3122 struct pipe_blend_state blend;
3123
3124 memset(&blend, 0, sizeof(blend));
3125 blend.independent_blend_enable = true;
3126 blend.rt[0].colormask = 0xf;
3127 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
3128 }
3129
3130 void *r600_create_db_flush_dsa(struct r600_context *rctx)
3131 {
3132 struct pipe_depth_stencil_alpha_state dsa;
3133 boolean quirk = false;
3134
3135 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
3136 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
3137 quirk = true;
3138
3139 memset(&dsa, 0, sizeof(dsa));
3140
3141 if (quirk) {
3142 dsa.depth.enabled = 1;
3143 dsa.depth.func = PIPE_FUNC_LEQUAL;
3144 dsa.stencil[0].enabled = 1;
3145 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
3146 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
3147 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
3148 dsa.stencil[0].writemask = 0xff;
3149 }
3150
3151 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3152 }
3153
3154 void r600_update_db_shader_control(struct r600_context * rctx)
3155 {
3156 bool dual_export;
3157 unsigned db_shader_control;
3158
3159 if (!rctx->ps_shader) {
3160 return;
3161 }
3162
3163 dual_export = rctx->framebuffer.export_16bpc &&
3164 !rctx->ps_shader->current->ps_depth_export;
3165
3166 db_shader_control = rctx->ps_shader->current->db_shader_control |
3167 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
3168
3169 /* When alpha test is enabled we can't trust the hw to make the proper
3170 * decision on the order in which ztest should be run related to fragment
3171 * shader execution.
3172 *
3173 * If alpha test is enabled perform z test after fragment. RE_Z (early
3174 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
3175 */
3176 if (rctx->alphatest_state.sx_alpha_test_control) {
3177 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3178 } else {
3179 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3180 }
3181
3182 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3183 rctx->db_misc_state.db_shader_control = db_shader_control;
3184 rctx->db_misc_state.atom.dirty = true;
3185 }
3186 }
3187
3188 static INLINE unsigned r600_array_mode(unsigned mode)
3189 {
3190 switch (mode) {
3191 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
3192 break;
3193 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
3194 break;
3195 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
3196 default:
3197 case RADEON_SURF_MODE_LINEAR: return V_0280A0_ARRAY_LINEAR_GENERAL;
3198 }
3199 }
3200
3201 static boolean r600_dma_copy_tile(struct r600_context *rctx,
3202 struct pipe_resource *dst,
3203 unsigned dst_level,
3204 unsigned dst_x,
3205 unsigned dst_y,
3206 unsigned dst_z,
3207 struct pipe_resource *src,
3208 unsigned src_level,
3209 unsigned src_x,
3210 unsigned src_y,
3211 unsigned src_z,
3212 unsigned copy_height,
3213 unsigned pitch,
3214 unsigned bpp)
3215 {
3216 struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
3217 struct r600_texture *rsrc = (struct r600_texture*)src;
3218 struct r600_texture *rdst = (struct r600_texture*)dst;
3219 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3220 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3221 uint64_t base, addr;
3222
3223 /* make sure that the dma ring is only one active */
3224 rctx->b.rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
3225
3226 dst_mode = rdst->surface.level[dst_level].mode;
3227 src_mode = rsrc->surface.level[src_level].mode;
3228 /* downcast linear aligned to linear to simplify test */
3229 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3230 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3231 assert(dst_mode != src_mode);
3232
3233 y = 0;
3234 lbpp = util_logbase2(bpp);
3235 pitch_tile_max = ((pitch / bpp) >> 3) - 1;
3236
3237 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
3238 /* T2L */
3239 array_mode = r600_array_mode(src_mode);
3240 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) >> 6;
3241 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3242 /* linear height must be the same as the slice tile max height, it's ok even
3243 * if the linear destination/source have smaller heigh as the size of the
3244 * dma packet will be using the copy_height which is always smaller or equal
3245 * to the linear height
3246 */
3247 height = rsrc->surface.level[src_level].npix_y;
3248 detile = 1;
3249 x = src_x;
3250 y = src_y;
3251 z = src_z;
3252 base = rsrc->surface.level[src_level].offset;
3253 addr = rdst->surface.level[dst_level].offset;
3254 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3255 addr += dst_y * pitch + dst_x * bpp;
3256 } else {
3257 /* L2T */
3258 array_mode = r600_array_mode(dst_mode);
3259 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) >> 6;
3260 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3261 /* linear height must be the same as the slice tile max height, it's ok even
3262 * if the linear destination/source have smaller heigh as the size of the
3263 * dma packet will be using the copy_height which is always smaller or equal
3264 * to the linear height
3265 */
3266 height = rdst->surface.level[dst_level].npix_y;
3267 detile = 0;
3268 x = dst_x;
3269 y = dst_y;
3270 z = dst_z;
3271 base = rdst->surface.level[dst_level].offset;
3272 addr = rsrc->surface.level[src_level].offset;
3273 addr += rsrc->surface.level[src_level].slice_size * src_z;
3274 addr += src_y * pitch + src_x * bpp;
3275 }
3276 /* check that we are in dw/base alignment constraint */
3277 if ((addr & 0x3) || (base & 0xff)) {
3278 return FALSE;
3279 }
3280
3281 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
3282 * line in the blit. Compute max 8 line we can copy in the size limit
3283 */
3284 cheight = ((0x0000ffff << 2) / pitch) & 0xfffffff8;
3285 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
3286 r600_need_dma_space(rctx, ncopy * 7);
3287
3288 for (i = 0; i < ncopy; i++) {
3289 cheight = cheight > copy_height ? copy_height : cheight;
3290 size = (cheight * pitch) >> 2;
3291 /* emit reloc before writting cs so that cs is always in consistent state */
3292 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ);
3293 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE);
3294 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
3295 cs->buf[cs->cdw++] = base >> 8;
3296 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
3297 (lbpp << 24) | ((height - 1) << 10) |
3298 pitch_tile_max;
3299 cs->buf[cs->cdw++] = (slice_tile_max << 12) | (z << 0);
3300 cs->buf[cs->cdw++] = (x << 3) | (y << 17);
3301 cs->buf[cs->cdw++] = addr & 0xfffffffc;
3302 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
3303 copy_height -= cheight;
3304 addr += cheight * pitch;
3305 y += cheight;
3306 }
3307 return TRUE;
3308 }
3309
3310 static boolean r600_dma_blit(struct pipe_context *ctx,
3311 struct pipe_resource *dst,
3312 unsigned dst_level,
3313 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3314 struct pipe_resource *src,
3315 unsigned src_level,
3316 const struct pipe_box *src_box)
3317 {
3318 struct r600_context *rctx = (struct r600_context *)ctx;
3319 struct r600_texture *rsrc = (struct r600_texture*)src;
3320 struct r600_texture *rdst = (struct r600_texture*)dst;
3321 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3322 unsigned src_w, dst_w;
3323 unsigned src_x, src_y;
3324
3325 if (rctx->b.rings.dma.cs == NULL) {
3326 return FALSE;
3327 }
3328
3329 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3330 r600_dma_copy(rctx, dst, src, dst_x, src_box->x, src_box->width);
3331 return TRUE;
3332 }
3333
3334 if (src->format != dst->format) {
3335 return FALSE;
3336 }
3337
3338 src_x = util_format_get_nblocksx(src->format, src_box->x);
3339 dst_x = util_format_get_nblocksx(src->format, dst_x);
3340 src_y = util_format_get_nblocksy(src->format, src_box->y);
3341 dst_y = util_format_get_nblocksy(src->format, dst_y);
3342
3343 bpp = rdst->surface.bpe;
3344 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3345 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3346 src_w = rsrc->surface.level[src_level].npix_x;
3347 dst_w = rdst->surface.level[dst_level].npix_x;
3348 copy_height = src_box->height / rsrc->surface.blk_h;
3349
3350 dst_mode = rdst->surface.level[dst_level].mode;
3351 src_mode = rsrc->surface.level[src_level].mode;
3352 /* downcast linear aligned to linear to simplify test */
3353 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3354 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3355
3356 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3357 /* strick requirement on r6xx/r7xx */
3358 return FALSE;
3359 }
3360 /* lot of constraint on alignment this should capture them all */
3361 if ((src_pitch & 0x7) || (src_box->y & 0x7) || (dst_y & 0x7)) {
3362 return FALSE;
3363 }
3364
3365 if (src_mode == dst_mode) {
3366 uint64_t dst_offset, src_offset, size;
3367
3368 /* simple dma blit would do NOTE code here assume :
3369 * src_box.x/y == 0
3370 * dst_x/y == 0
3371 * dst_pitch == src_pitch
3372 */
3373 src_offset= rsrc->surface.level[src_level].offset;
3374 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3375 src_offset += src_y * src_pitch + src_x * bpp;
3376 dst_offset = rdst->surface.level[dst_level].offset;
3377 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3378 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3379 size = src_box->height * src_pitch;
3380 /* must be dw aligned */
3381 if ((dst_offset & 0x3) || (src_offset & 0x3) || (size & 0x3)) {
3382 return FALSE;
3383 }
3384 r600_dma_copy(rctx, dst, src, dst_offset, src_offset, size);
3385 } else {
3386 return r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3387 src, src_level, src_x, src_y, src_box->z,
3388 copy_height, dst_pitch, bpp);
3389 }
3390 return TRUE;
3391 }
3392
3393 void r600_init_state_functions(struct r600_context *rctx)
3394 {
3395 unsigned id = 4;
3396
3397 /* !!!
3398 * To avoid GPU lockup registers must be emited in a specific order
3399 * (no kidding ...). The order below is important and have been
3400 * partialy infered from analyzing fglrx command stream.
3401 *
3402 * Don't reorder atom without carefully checking the effect (GPU lockup
3403 * or piglit regression).
3404 * !!!
3405 */
3406
3407 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3408
3409 /* shader const */
3410 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3411 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3412 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3413
3414 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3415 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3416 */
3417 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3418 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3419 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3420 /* resource */
3421 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3422 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3423 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3424 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3425
3426 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 7);
3427
3428 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3429 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3430 rctx->sample_mask.sample_mask = ~0;
3431
3432 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3433 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3434 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3435 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3436 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3437 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3438 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3439 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3440 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3441 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
3442 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3443 r600_init_atom(rctx, &rctx->scissor.atom, id++, r600_emit_scissor_state, 4);
3444 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3445 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3446 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
3447 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3448 rctx->atoms[id++] = &rctx->b.streamout.begin_atom;
3449 r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader, 23);
3450 r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader, 0);
3451 r600_init_atom(rctx, &rctx->geometry_shader.atom, id++, r600_emit_shader, 0);
3452 r600_init_atom(rctx, &rctx->export_shader.atom, id++, r600_emit_shader, 0);
3453 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3454 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3455
3456 rctx->b.b.create_blend_state = r600_create_blend_state;
3457 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3458 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3459 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3460 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3461 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3462 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3463 rctx->b.b.set_scissor_states = r600_set_scissor_states;
3464 rctx->b.b.get_sample_position = r600_get_sample_position;
3465 rctx->b.dma_copy = r600_dma_blit;
3466 }
3467 /* this function must be last */