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116ec5fca0e5fa1f77e027e3652dc3845d7327d9
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600d.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31
32 static uint32_t r600_translate_blend_function(int blend_func)
33 {
34 switch (blend_func) {
35 case PIPE_BLEND_ADD:
36 return V_028804_COMB_DST_PLUS_SRC;
37 case PIPE_BLEND_SUBTRACT:
38 return V_028804_COMB_SRC_MINUS_DST;
39 case PIPE_BLEND_REVERSE_SUBTRACT:
40 return V_028804_COMB_DST_MINUS_SRC;
41 case PIPE_BLEND_MIN:
42 return V_028804_COMB_MIN_DST_SRC;
43 case PIPE_BLEND_MAX:
44 return V_028804_COMB_MAX_DST_SRC;
45 default:
46 R600_ERR("Unknown blend function %d\n", blend_func);
47 assert(0);
48 break;
49 }
50 return 0;
51 }
52
53 static uint32_t r600_translate_blend_factor(int blend_fact)
54 {
55 switch (blend_fact) {
56 case PIPE_BLENDFACTOR_ONE:
57 return V_028804_BLEND_ONE;
58 case PIPE_BLENDFACTOR_SRC_COLOR:
59 return V_028804_BLEND_SRC_COLOR;
60 case PIPE_BLENDFACTOR_SRC_ALPHA:
61 return V_028804_BLEND_SRC_ALPHA;
62 case PIPE_BLENDFACTOR_DST_ALPHA:
63 return V_028804_BLEND_DST_ALPHA;
64 case PIPE_BLENDFACTOR_DST_COLOR:
65 return V_028804_BLEND_DST_COLOR;
66 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
67 return V_028804_BLEND_SRC_ALPHA_SATURATE;
68 case PIPE_BLENDFACTOR_CONST_COLOR:
69 return V_028804_BLEND_CONST_COLOR;
70 case PIPE_BLENDFACTOR_CONST_ALPHA:
71 return V_028804_BLEND_CONST_ALPHA;
72 case PIPE_BLENDFACTOR_ZERO:
73 return V_028804_BLEND_ZERO;
74 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
75 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
76 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
77 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
78 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
79 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
80 case PIPE_BLENDFACTOR_INV_DST_COLOR:
81 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
82 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
83 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
84 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
85 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
86 case PIPE_BLENDFACTOR_SRC1_COLOR:
87 return V_028804_BLEND_SRC1_COLOR;
88 case PIPE_BLENDFACTOR_SRC1_ALPHA:
89 return V_028804_BLEND_SRC1_ALPHA;
90 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
91 return V_028804_BLEND_INV_SRC1_COLOR;
92 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
93 return V_028804_BLEND_INV_SRC1_ALPHA;
94 default:
95 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
96 assert(0);
97 break;
98 }
99 return 0;
100 }
101
102 static unsigned r600_tex_dim(unsigned dim)
103 {
104 switch (dim) {
105 default:
106 case PIPE_TEXTURE_1D:
107 return V_038000_SQ_TEX_DIM_1D;
108 case PIPE_TEXTURE_1D_ARRAY:
109 return V_038000_SQ_TEX_DIM_1D_ARRAY;
110 case PIPE_TEXTURE_2D:
111 case PIPE_TEXTURE_RECT:
112 return V_038000_SQ_TEX_DIM_2D;
113 case PIPE_TEXTURE_2D_ARRAY:
114 return V_038000_SQ_TEX_DIM_2D_ARRAY;
115 case PIPE_TEXTURE_3D:
116 return V_038000_SQ_TEX_DIM_3D;
117 case PIPE_TEXTURE_CUBE:
118 return V_038000_SQ_TEX_DIM_CUBEMAP;
119 }
120 }
121
122 static uint32_t r600_translate_dbformat(enum pipe_format format)
123 {
124 switch (format) {
125 case PIPE_FORMAT_Z16_UNORM:
126 return V_028010_DEPTH_16;
127 case PIPE_FORMAT_Z24X8_UNORM:
128 return V_028010_DEPTH_X8_24;
129 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
130 return V_028010_DEPTH_8_24;
131 case PIPE_FORMAT_Z32_FLOAT:
132 return V_028010_DEPTH_32_FLOAT;
133 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
134 return V_028010_DEPTH_X24_8_32_FLOAT;
135 default:
136 return ~0U;
137 }
138 }
139
140 static uint32_t r600_translate_colorswap(enum pipe_format format)
141 {
142 switch (format) {
143 /* 8-bit buffers. */
144 case PIPE_FORMAT_A8_UNORM:
145 case PIPE_FORMAT_A8_SNORM:
146 case PIPE_FORMAT_A8_UINT:
147 case PIPE_FORMAT_A8_SINT:
148 case PIPE_FORMAT_A16_UNORM:
149 case PIPE_FORMAT_A16_SNORM:
150 case PIPE_FORMAT_A16_UINT:
151 case PIPE_FORMAT_A16_SINT:
152 case PIPE_FORMAT_A16_FLOAT:
153 case PIPE_FORMAT_A32_UINT:
154 case PIPE_FORMAT_A32_SINT:
155 case PIPE_FORMAT_A32_FLOAT:
156 case PIPE_FORMAT_R4A4_UNORM:
157 return V_0280A0_SWAP_ALT_REV;
158 case PIPE_FORMAT_I8_UNORM:
159 case PIPE_FORMAT_I8_SNORM:
160 case PIPE_FORMAT_I8_UINT:
161 case PIPE_FORMAT_I8_SINT:
162 case PIPE_FORMAT_L8_UNORM:
163 case PIPE_FORMAT_L8_SNORM:
164 case PIPE_FORMAT_L8_UINT:
165 case PIPE_FORMAT_L8_SINT:
166 case PIPE_FORMAT_L8_SRGB:
167 case PIPE_FORMAT_L16_UNORM:
168 case PIPE_FORMAT_L16_SNORM:
169 case PIPE_FORMAT_L16_UINT:
170 case PIPE_FORMAT_L16_SINT:
171 case PIPE_FORMAT_L16_FLOAT:
172 case PIPE_FORMAT_L32_UINT:
173 case PIPE_FORMAT_L32_SINT:
174 case PIPE_FORMAT_L32_FLOAT:
175 case PIPE_FORMAT_I16_UNORM:
176 case PIPE_FORMAT_I16_SNORM:
177 case PIPE_FORMAT_I16_UINT:
178 case PIPE_FORMAT_I16_SINT:
179 case PIPE_FORMAT_I16_FLOAT:
180 case PIPE_FORMAT_I32_UINT:
181 case PIPE_FORMAT_I32_SINT:
182 case PIPE_FORMAT_I32_FLOAT:
183 case PIPE_FORMAT_R8_UNORM:
184 case PIPE_FORMAT_R8_SNORM:
185 case PIPE_FORMAT_R8_UINT:
186 case PIPE_FORMAT_R8_SINT:
187 return V_0280A0_SWAP_STD;
188
189 case PIPE_FORMAT_L4A4_UNORM:
190 case PIPE_FORMAT_A4R4_UNORM:
191 return V_0280A0_SWAP_ALT;
192
193 /* 16-bit buffers. */
194 case PIPE_FORMAT_B5G6R5_UNORM:
195 return V_0280A0_SWAP_STD_REV;
196
197 case PIPE_FORMAT_B5G5R5A1_UNORM:
198 case PIPE_FORMAT_B5G5R5X1_UNORM:
199 return V_0280A0_SWAP_ALT;
200
201 case PIPE_FORMAT_B4G4R4A4_UNORM:
202 case PIPE_FORMAT_B4G4R4X4_UNORM:
203 return V_0280A0_SWAP_ALT;
204
205 case PIPE_FORMAT_Z16_UNORM:
206 return V_0280A0_SWAP_STD;
207
208 case PIPE_FORMAT_L8A8_UNORM:
209 case PIPE_FORMAT_L8A8_SNORM:
210 case PIPE_FORMAT_L8A8_UINT:
211 case PIPE_FORMAT_L8A8_SINT:
212 case PIPE_FORMAT_L8A8_SRGB:
213 case PIPE_FORMAT_L16A16_UNORM:
214 case PIPE_FORMAT_L16A16_SNORM:
215 case PIPE_FORMAT_L16A16_UINT:
216 case PIPE_FORMAT_L16A16_SINT:
217 case PIPE_FORMAT_L16A16_FLOAT:
218 case PIPE_FORMAT_L32A32_UINT:
219 case PIPE_FORMAT_L32A32_SINT:
220 case PIPE_FORMAT_L32A32_FLOAT:
221 return V_0280A0_SWAP_ALT;
222 case PIPE_FORMAT_R8G8_UNORM:
223 case PIPE_FORMAT_R8G8_SNORM:
224 case PIPE_FORMAT_R8G8_UINT:
225 case PIPE_FORMAT_R8G8_SINT:
226 return V_0280A0_SWAP_STD;
227
228 case PIPE_FORMAT_R16_UNORM:
229 case PIPE_FORMAT_R16_SNORM:
230 case PIPE_FORMAT_R16_UINT:
231 case PIPE_FORMAT_R16_SINT:
232 case PIPE_FORMAT_R16_FLOAT:
233 return V_0280A0_SWAP_STD;
234
235 /* 32-bit buffers. */
236
237 case PIPE_FORMAT_A8B8G8R8_SRGB:
238 return V_0280A0_SWAP_STD_REV;
239 case PIPE_FORMAT_B8G8R8A8_SRGB:
240 return V_0280A0_SWAP_ALT;
241
242 case PIPE_FORMAT_B8G8R8A8_UNORM:
243 case PIPE_FORMAT_B8G8R8X8_UNORM:
244 return V_0280A0_SWAP_ALT;
245
246 case PIPE_FORMAT_A8R8G8B8_UNORM:
247 case PIPE_FORMAT_X8R8G8B8_UNORM:
248 return V_0280A0_SWAP_ALT_REV;
249 case PIPE_FORMAT_R8G8B8A8_SNORM:
250 case PIPE_FORMAT_R8G8B8A8_UNORM:
251 case PIPE_FORMAT_R8G8B8X8_UNORM:
252 case PIPE_FORMAT_R8G8B8A8_SINT:
253 case PIPE_FORMAT_R8G8B8A8_UINT:
254 return V_0280A0_SWAP_STD;
255
256 case PIPE_FORMAT_A8B8G8R8_UNORM:
257 case PIPE_FORMAT_X8B8G8R8_UNORM:
258 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
259 return V_0280A0_SWAP_STD_REV;
260
261 case PIPE_FORMAT_Z24X8_UNORM:
262 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
263 return V_0280A0_SWAP_STD;
264
265 case PIPE_FORMAT_X8Z24_UNORM:
266 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
267 return V_0280A0_SWAP_STD;
268
269 case PIPE_FORMAT_R10G10B10A2_UNORM:
270 case PIPE_FORMAT_R10G10B10X2_SNORM:
271 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
272 return V_0280A0_SWAP_STD;
273
274 case PIPE_FORMAT_B10G10R10A2_UNORM:
275 case PIPE_FORMAT_B10G10R10A2_UINT:
276 return V_0280A0_SWAP_ALT;
277
278 case PIPE_FORMAT_R11G11B10_FLOAT:
279 case PIPE_FORMAT_R16G16_UNORM:
280 case PIPE_FORMAT_R16G16_SNORM:
281 case PIPE_FORMAT_R16G16_FLOAT:
282 case PIPE_FORMAT_R16G16_UINT:
283 case PIPE_FORMAT_R16G16_SINT:
284 case PIPE_FORMAT_R32_UINT:
285 case PIPE_FORMAT_R32_SINT:
286 case PIPE_FORMAT_R32_FLOAT:
287 case PIPE_FORMAT_Z32_FLOAT:
288 return V_0280A0_SWAP_STD;
289
290 /* 64-bit buffers. */
291 case PIPE_FORMAT_R32G32_FLOAT:
292 case PIPE_FORMAT_R32G32_UINT:
293 case PIPE_FORMAT_R32G32_SINT:
294 case PIPE_FORMAT_R16G16B16A16_UNORM:
295 case PIPE_FORMAT_R16G16B16A16_SNORM:
296 case PIPE_FORMAT_R16G16B16A16_UINT:
297 case PIPE_FORMAT_R16G16B16A16_SINT:
298 case PIPE_FORMAT_R16G16B16A16_FLOAT:
299 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
300
301 /* 128-bit buffers. */
302 case PIPE_FORMAT_R32G32B32A32_FLOAT:
303 case PIPE_FORMAT_R32G32B32A32_SNORM:
304 case PIPE_FORMAT_R32G32B32A32_UNORM:
305 case PIPE_FORMAT_R32G32B32A32_SINT:
306 case PIPE_FORMAT_R32G32B32A32_UINT:
307 return V_0280A0_SWAP_STD;
308 default:
309 R600_ERR("unsupported colorswap format %d\n", format);
310 return ~0U;
311 }
312 return ~0U;
313 }
314
315 static uint32_t r600_translate_colorformat(enum pipe_format format)
316 {
317 switch (format) {
318 case PIPE_FORMAT_L4A4_UNORM:
319 case PIPE_FORMAT_R4A4_UNORM:
320 case PIPE_FORMAT_A4R4_UNORM:
321 return V_0280A0_COLOR_4_4;
322
323 /* 8-bit buffers. */
324 case PIPE_FORMAT_A8_UNORM:
325 case PIPE_FORMAT_A8_SNORM:
326 case PIPE_FORMAT_A8_UINT:
327 case PIPE_FORMAT_A8_SINT:
328 case PIPE_FORMAT_I8_UNORM:
329 case PIPE_FORMAT_I8_SNORM:
330 case PIPE_FORMAT_I8_UINT:
331 case PIPE_FORMAT_I8_SINT:
332 case PIPE_FORMAT_L8_UNORM:
333 case PIPE_FORMAT_L8_SNORM:
334 case PIPE_FORMAT_L8_UINT:
335 case PIPE_FORMAT_L8_SINT:
336 case PIPE_FORMAT_L8_SRGB:
337 case PIPE_FORMAT_R8_UNORM:
338 case PIPE_FORMAT_R8_SNORM:
339 case PIPE_FORMAT_R8_UINT:
340 case PIPE_FORMAT_R8_SINT:
341 return V_0280A0_COLOR_8;
342
343 /* 16-bit buffers. */
344 case PIPE_FORMAT_B5G6R5_UNORM:
345 return V_0280A0_COLOR_5_6_5;
346
347 case PIPE_FORMAT_B5G5R5A1_UNORM:
348 case PIPE_FORMAT_B5G5R5X1_UNORM:
349 return V_0280A0_COLOR_1_5_5_5;
350
351 case PIPE_FORMAT_B4G4R4A4_UNORM:
352 case PIPE_FORMAT_B4G4R4X4_UNORM:
353 return V_0280A0_COLOR_4_4_4_4;
354
355 case PIPE_FORMAT_Z16_UNORM:
356 return V_0280A0_COLOR_16;
357
358 case PIPE_FORMAT_L8A8_UNORM:
359 case PIPE_FORMAT_L8A8_SNORM:
360 case PIPE_FORMAT_L8A8_UINT:
361 case PIPE_FORMAT_L8A8_SINT:
362 case PIPE_FORMAT_L8A8_SRGB:
363 case PIPE_FORMAT_R8G8_UNORM:
364 case PIPE_FORMAT_R8G8_SNORM:
365 case PIPE_FORMAT_R8G8_UINT:
366 case PIPE_FORMAT_R8G8_SINT:
367 return V_0280A0_COLOR_8_8;
368
369 case PIPE_FORMAT_R16_UNORM:
370 case PIPE_FORMAT_R16_SNORM:
371 case PIPE_FORMAT_R16_UINT:
372 case PIPE_FORMAT_R16_SINT:
373 case PIPE_FORMAT_A16_UNORM:
374 case PIPE_FORMAT_A16_SNORM:
375 case PIPE_FORMAT_A16_UINT:
376 case PIPE_FORMAT_A16_SINT:
377 case PIPE_FORMAT_L16_UNORM:
378 case PIPE_FORMAT_L16_SNORM:
379 case PIPE_FORMAT_L16_UINT:
380 case PIPE_FORMAT_L16_SINT:
381 case PIPE_FORMAT_I16_UNORM:
382 case PIPE_FORMAT_I16_SNORM:
383 case PIPE_FORMAT_I16_UINT:
384 case PIPE_FORMAT_I16_SINT:
385 return V_0280A0_COLOR_16;
386
387 case PIPE_FORMAT_R16_FLOAT:
388 case PIPE_FORMAT_A16_FLOAT:
389 case PIPE_FORMAT_L16_FLOAT:
390 case PIPE_FORMAT_I16_FLOAT:
391 return V_0280A0_COLOR_16_FLOAT;
392
393 /* 32-bit buffers. */
394 case PIPE_FORMAT_A8B8G8R8_SRGB:
395 case PIPE_FORMAT_A8B8G8R8_UNORM:
396 case PIPE_FORMAT_A8R8G8B8_UNORM:
397 case PIPE_FORMAT_B8G8R8A8_SRGB:
398 case PIPE_FORMAT_B8G8R8A8_UNORM:
399 case PIPE_FORMAT_B8G8R8X8_UNORM:
400 case PIPE_FORMAT_R8G8B8A8_SNORM:
401 case PIPE_FORMAT_R8G8B8A8_UNORM:
402 case PIPE_FORMAT_R8G8B8X8_UNORM:
403 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
404 case PIPE_FORMAT_X8B8G8R8_UNORM:
405 case PIPE_FORMAT_X8R8G8B8_UNORM:
406 case PIPE_FORMAT_R8G8B8_UNORM:
407 case PIPE_FORMAT_R8G8B8A8_SINT:
408 case PIPE_FORMAT_R8G8B8A8_UINT:
409 return V_0280A0_COLOR_8_8_8_8;
410
411 case PIPE_FORMAT_R10G10B10A2_UNORM:
412 case PIPE_FORMAT_R10G10B10X2_SNORM:
413 case PIPE_FORMAT_B10G10R10A2_UNORM:
414 case PIPE_FORMAT_B10G10R10A2_UINT:
415 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
416 return V_0280A0_COLOR_2_10_10_10;
417
418 case PIPE_FORMAT_Z24X8_UNORM:
419 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
420 return V_0280A0_COLOR_8_24;
421
422 case PIPE_FORMAT_X8Z24_UNORM:
423 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
424 return V_0280A0_COLOR_24_8;
425
426 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
427 return V_0280A0_COLOR_X24_8_32_FLOAT;
428
429 case PIPE_FORMAT_R32_UINT:
430 case PIPE_FORMAT_R32_SINT:
431 case PIPE_FORMAT_A32_UINT:
432 case PIPE_FORMAT_A32_SINT:
433 case PIPE_FORMAT_L32_UINT:
434 case PIPE_FORMAT_L32_SINT:
435 case PIPE_FORMAT_I32_UINT:
436 case PIPE_FORMAT_I32_SINT:
437 return V_0280A0_COLOR_32;
438
439 case PIPE_FORMAT_R32_FLOAT:
440 case PIPE_FORMAT_A32_FLOAT:
441 case PIPE_FORMAT_L32_FLOAT:
442 case PIPE_FORMAT_I32_FLOAT:
443 case PIPE_FORMAT_Z32_FLOAT:
444 return V_0280A0_COLOR_32_FLOAT;
445
446 case PIPE_FORMAT_R16G16_FLOAT:
447 case PIPE_FORMAT_L16A16_FLOAT:
448 return V_0280A0_COLOR_16_16_FLOAT;
449
450 case PIPE_FORMAT_R16G16_UNORM:
451 case PIPE_FORMAT_R16G16_SNORM:
452 case PIPE_FORMAT_R16G16_UINT:
453 case PIPE_FORMAT_R16G16_SINT:
454 case PIPE_FORMAT_L16A16_UNORM:
455 case PIPE_FORMAT_L16A16_SNORM:
456 case PIPE_FORMAT_L16A16_UINT:
457 case PIPE_FORMAT_L16A16_SINT:
458 return V_0280A0_COLOR_16_16;
459
460 case PIPE_FORMAT_R11G11B10_FLOAT:
461 return V_0280A0_COLOR_10_11_11_FLOAT;
462
463 /* 64-bit buffers. */
464 case PIPE_FORMAT_R16G16B16A16_UINT:
465 case PIPE_FORMAT_R16G16B16A16_SINT:
466 case PIPE_FORMAT_R16G16B16A16_UNORM:
467 case PIPE_FORMAT_R16G16B16A16_SNORM:
468 return V_0280A0_COLOR_16_16_16_16;
469
470 case PIPE_FORMAT_R16G16B16_FLOAT:
471 case PIPE_FORMAT_R16G16B16A16_FLOAT:
472 return V_0280A0_COLOR_16_16_16_16_FLOAT;
473
474 case PIPE_FORMAT_R32G32_FLOAT:
475 case PIPE_FORMAT_L32A32_FLOAT:
476 return V_0280A0_COLOR_32_32_FLOAT;
477
478 case PIPE_FORMAT_R32G32_SINT:
479 case PIPE_FORMAT_R32G32_UINT:
480 case PIPE_FORMAT_L32A32_UINT:
481 case PIPE_FORMAT_L32A32_SINT:
482 return V_0280A0_COLOR_32_32;
483
484 /* 96-bit buffers. */
485 case PIPE_FORMAT_R32G32B32_FLOAT:
486 return V_0280A0_COLOR_32_32_32_FLOAT;
487
488 /* 128-bit buffers. */
489 case PIPE_FORMAT_R32G32B32A32_FLOAT:
490 return V_0280A0_COLOR_32_32_32_32_FLOAT;
491 case PIPE_FORMAT_R32G32B32A32_SNORM:
492 case PIPE_FORMAT_R32G32B32A32_UNORM:
493 case PIPE_FORMAT_R32G32B32A32_SINT:
494 case PIPE_FORMAT_R32G32B32A32_UINT:
495 return V_0280A0_COLOR_32_32_32_32;
496
497 /* YUV buffers. */
498 case PIPE_FORMAT_UYVY:
499 case PIPE_FORMAT_YUYV:
500 default:
501 return ~0U; /* Unsupported. */
502 }
503 }
504
505 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
506 {
507 if (R600_BIG_ENDIAN) {
508 switch(colorformat) {
509 case V_0280A0_COLOR_4_4:
510 return ENDIAN_NONE;
511
512 /* 8-bit buffers. */
513 case V_0280A0_COLOR_8:
514 return ENDIAN_NONE;
515
516 /* 16-bit buffers. */
517 case V_0280A0_COLOR_5_6_5:
518 case V_0280A0_COLOR_1_5_5_5:
519 case V_0280A0_COLOR_4_4_4_4:
520 case V_0280A0_COLOR_16:
521 case V_0280A0_COLOR_8_8:
522 return ENDIAN_8IN16;
523
524 /* 32-bit buffers. */
525 case V_0280A0_COLOR_8_8_8_8:
526 case V_0280A0_COLOR_2_10_10_10:
527 case V_0280A0_COLOR_8_24:
528 case V_0280A0_COLOR_24_8:
529 case V_0280A0_COLOR_32_FLOAT:
530 case V_0280A0_COLOR_16_16_FLOAT:
531 case V_0280A0_COLOR_16_16:
532 return ENDIAN_8IN32;
533
534 /* 64-bit buffers. */
535 case V_0280A0_COLOR_16_16_16_16:
536 case V_0280A0_COLOR_16_16_16_16_FLOAT:
537 return ENDIAN_8IN16;
538
539 case V_0280A0_COLOR_32_32_FLOAT:
540 case V_0280A0_COLOR_32_32:
541 case V_0280A0_COLOR_X24_8_32_FLOAT:
542 return ENDIAN_8IN32;
543
544 /* 128-bit buffers. */
545 case V_0280A0_COLOR_32_32_32_FLOAT:
546 case V_0280A0_COLOR_32_32_32_32_FLOAT:
547 case V_0280A0_COLOR_32_32_32_32:
548 return ENDIAN_8IN32;
549 default:
550 return ENDIAN_NONE; /* Unsupported. */
551 }
552 } else {
553 return ENDIAN_NONE;
554 }
555 }
556
557 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
558 {
559 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
560 }
561
562 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
563 {
564 return r600_translate_colorformat(format) != ~0U &&
565 r600_translate_colorswap(format) != ~0U;
566 }
567
568 static bool r600_is_zs_format_supported(enum pipe_format format)
569 {
570 return r600_translate_dbformat(format) != ~0U;
571 }
572
573 boolean r600_is_format_supported(struct pipe_screen *screen,
574 enum pipe_format format,
575 enum pipe_texture_target target,
576 unsigned sample_count,
577 unsigned usage)
578 {
579 unsigned retval = 0;
580
581 if (target >= PIPE_MAX_TEXTURE_TYPES) {
582 R600_ERR("r600: unsupported texture type %d\n", target);
583 return FALSE;
584 }
585
586 if (!util_format_is_supported(format, usage))
587 return FALSE;
588
589 /* Multisample */
590 if (sample_count > 1)
591 return FALSE;
592
593 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
594 r600_is_sampler_format_supported(screen, format)) {
595 retval |= PIPE_BIND_SAMPLER_VIEW;
596 }
597
598 if ((usage & (PIPE_BIND_RENDER_TARGET |
599 PIPE_BIND_DISPLAY_TARGET |
600 PIPE_BIND_SCANOUT |
601 PIPE_BIND_SHARED)) &&
602 r600_is_colorbuffer_format_supported(format)) {
603 retval |= usage &
604 (PIPE_BIND_RENDER_TARGET |
605 PIPE_BIND_DISPLAY_TARGET |
606 PIPE_BIND_SCANOUT |
607 PIPE_BIND_SHARED);
608 }
609
610 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
611 r600_is_zs_format_supported(format)) {
612 retval |= PIPE_BIND_DEPTH_STENCIL;
613 }
614
615 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
616 r600_is_vertex_format_supported(format)) {
617 retval |= PIPE_BIND_VERTEX_BUFFER;
618 }
619
620 if (usage & PIPE_BIND_TRANSFER_READ)
621 retval |= PIPE_BIND_TRANSFER_READ;
622 if (usage & PIPE_BIND_TRANSFER_WRITE)
623 retval |= PIPE_BIND_TRANSFER_WRITE;
624
625 return retval == usage;
626 }
627
628 void r600_polygon_offset_update(struct r600_context *rctx)
629 {
630 struct r600_pipe_state state;
631
632 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
633 state.nregs = 0;
634 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
635 float offset_units = rctx->rasterizer->offset_units;
636 unsigned offset_db_fmt_cntl = 0, depth;
637
638 switch (rctx->framebuffer.zsbuf->texture->format) {
639 case PIPE_FORMAT_Z24X8_UNORM:
640 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
641 depth = -24;
642 offset_units *= 2.0f;
643 break;
644 case PIPE_FORMAT_Z32_FLOAT:
645 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
646 depth = -23;
647 offset_units *= 1.0f;
648 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
649 break;
650 case PIPE_FORMAT_Z16_UNORM:
651 depth = -16;
652 offset_units *= 4.0f;
653 break;
654 default:
655 return;
656 }
657 /* XXX some of those reg can be computed with cso */
658 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
659 r600_pipe_state_add_reg(&state,
660 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
661 fui(rctx->rasterizer->offset_scale));
662 r600_pipe_state_add_reg(&state,
663 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
664 fui(offset_units));
665 r600_pipe_state_add_reg(&state,
666 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
667 fui(rctx->rasterizer->offset_scale));
668 r600_pipe_state_add_reg(&state,
669 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
670 fui(offset_units));
671 r600_pipe_state_add_reg(&state,
672 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
673 offset_db_fmt_cntl);
674 r600_context_pipe_state_set(rctx, &state);
675 }
676 }
677
678 static void *r600_create_blend_state(struct pipe_context *ctx,
679 const struct pipe_blend_state *state)
680 {
681 struct r600_context *rctx = (struct r600_context *)ctx;
682 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
683 struct r600_pipe_state *rstate;
684 uint32_t color_control = 0, target_mask;
685
686 if (blend == NULL) {
687 return NULL;
688 }
689 rstate = &blend->rstate;
690
691 rstate->id = R600_PIPE_STATE_BLEND;
692
693 target_mask = 0;
694
695 /* R600 does not support per-MRT blends */
696 if (rctx->family > CHIP_R600)
697 color_control |= S_028808_PER_MRT_BLEND(1);
698 if (state->logicop_enable) {
699 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
700 } else {
701 color_control |= (0xcc << 16);
702 }
703 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
704 if (state->independent_blend_enable) {
705 for (int i = 0; i < 8; i++) {
706 if (state->rt[i].blend_enable) {
707 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
708 }
709 target_mask |= (state->rt[i].colormask << (4 * i));
710 }
711 } else {
712 for (int i = 0; i < 8; i++) {
713 if (state->rt[0].blend_enable) {
714 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
715 }
716 target_mask |= (state->rt[0].colormask << (4 * i));
717 }
718 }
719 blend->cb_target_mask = target_mask;
720 blend->cb_color_control = color_control;
721 /* only MRT0 has dual src blend */
722 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
723 for (int i = 0; i < 8; i++) {
724 /* state->rt entries > 0 only written if independent blending */
725 const int j = state->independent_blend_enable ? i : 0;
726
727 unsigned eqRGB = state->rt[j].rgb_func;
728 unsigned srcRGB = state->rt[j].rgb_src_factor;
729 unsigned dstRGB = state->rt[j].rgb_dst_factor;
730
731 unsigned eqA = state->rt[j].alpha_func;
732 unsigned srcA = state->rt[j].alpha_src_factor;
733 unsigned dstA = state->rt[j].alpha_dst_factor;
734 uint32_t bc = 0;
735
736 if (!state->rt[j].blend_enable)
737 continue;
738
739 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
740 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
741 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
742
743 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
744 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
745 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
746 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
747 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
748 }
749
750 /* R600 does not support per-MRT blends */
751 if (rctx->family > CHIP_R600)
752 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc);
753 if (i == 0)
754 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
755 }
756 return rstate;
757 }
758
759 static void *r600_create_dsa_state(struct pipe_context *ctx,
760 const struct pipe_depth_stencil_alpha_state *state)
761 {
762 struct r600_context *rctx = (struct r600_context *)ctx;
763 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
764 unsigned db_depth_control, alpha_test_control, alpha_ref;
765 struct r600_pipe_state *rstate;
766
767 if (dsa == NULL) {
768 return NULL;
769 }
770
771 dsa->valuemask[0] = state->stencil[0].valuemask;
772 dsa->valuemask[1] = state->stencil[1].valuemask;
773 dsa->writemask[0] = state->stencil[0].writemask;
774 dsa->writemask[1] = state->stencil[1].writemask;
775
776 rstate = &dsa->rstate;
777
778 rstate->id = R600_PIPE_STATE_DSA;
779 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
780 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
781 S_028800_ZFUNC(state->depth.func);
782
783 /* stencil */
784 if (state->stencil[0].enabled) {
785 db_depth_control |= S_028800_STENCIL_ENABLE(1);
786 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
787 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
788 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
789 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
790
791 if (state->stencil[1].enabled) {
792 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
793 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
794 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
795 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
796 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
797 }
798 }
799
800 /* alpha */
801 alpha_test_control = 0;
802 alpha_ref = 0;
803 if (state->alpha.enabled) {
804 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
805 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
806 alpha_ref = fui(state->alpha.ref_value);
807 }
808 dsa->alpha_ref = alpha_ref;
809
810 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
811 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
812 return rstate;
813 }
814
815 static void *r600_create_rs_state(struct pipe_context *ctx,
816 const struct pipe_rasterizer_state *state)
817 {
818 struct r600_context *rctx = (struct r600_context *)ctx;
819 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
820 struct r600_pipe_state *rstate;
821 unsigned tmp;
822 unsigned prov_vtx = 1, polygon_dual_mode;
823 unsigned sc_mode_cntl;
824 float psize_min, psize_max;
825
826 if (rs == NULL) {
827 return NULL;
828 }
829
830 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
831 state->fill_back != PIPE_POLYGON_MODE_FILL);
832
833 if (state->flatshade_first)
834 prov_vtx = 0;
835
836 rstate = &rs->rstate;
837 rs->flatshade = state->flatshade;
838 rs->sprite_coord_enable = state->sprite_coord_enable;
839 rs->two_side = state->light_twoside;
840 rs->clip_plane_enable = state->clip_plane_enable;
841 rs->pa_sc_line_stipple = state->line_stipple_enable ?
842 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
843 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
844 rs->pa_cl_clip_cntl =
845 S_028810_PS_UCP_MODE(3) |
846 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
847 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
848 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
849
850 /* offset */
851 rs->offset_units = state->offset_units;
852 rs->offset_scale = state->offset_scale * 12.0f;
853
854 rstate->id = R600_PIPE_STATE_RASTERIZER;
855 tmp = S_0286D4_FLAT_SHADE_ENA(1);
856 if (state->sprite_coord_enable) {
857 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
858 S_0286D4_PNT_SPRITE_OVRD_X(2) |
859 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
860 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
861 S_0286D4_PNT_SPRITE_OVRD_W(1);
862 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
863 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
864 }
865 }
866 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
867
868 /* point size 12.4 fixed point */
869 tmp = r600_pack_float_12p4(state->point_size/2);
870 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
871
872 if (state->point_size_per_vertex) {
873 psize_min = util_get_min_point_size(state);
874 psize_max = 8192;
875 } else {
876 /* Force the point size to be as if the vertex output was disabled. */
877 psize_min = state->point_size;
878 psize_max = state->point_size;
879 }
880 /* Divide by two, because 0.5 = 1 pixel. */
881 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
882 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
883 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
884
885 tmp = r600_pack_float_12p4(state->line_width/2);
886 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
887
888 if (rctx->chip_class >= R700) {
889 sc_mode_cntl =
890 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
891 S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
892 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
893 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
894 } else {
895 sc_mode_cntl =
896 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
897 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
898 rs->scissor_enable = state->scissor;
899 }
900 sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
901
902 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
903
904 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
905 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
906
907 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
908 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
909 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
910 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
911 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
912 S_028814_FACE(!state->front_ccw) |
913 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
914 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
915 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
916 S_028814_POLY_MODE(polygon_dual_mode) |
917 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
918 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
919 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
920 return rstate;
921 }
922
923 static void *r600_create_sampler_state(struct pipe_context *ctx,
924 const struct pipe_sampler_state *state)
925 {
926 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
927 struct r600_pipe_state *rstate;
928 union util_color uc;
929 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
930
931 if (ss == NULL) {
932 return NULL;
933 }
934
935 ss->seamless_cube_map = state->seamless_cube_map;
936 rstate = &ss->rstate;
937 rstate->id = R600_PIPE_STATE_SAMPLER;
938 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
939 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
940 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
941 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
942 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
943 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
944 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
945 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
946 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
947 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
948 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
949 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
950 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
951 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
952 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), NULL, 0);
953 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), NULL, 0);
954 if (uc.ui) {
955 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
956 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
957 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
958 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
959 }
960 return rstate;
961 }
962
963 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
964 struct pipe_resource *texture,
965 const struct pipe_sampler_view *state)
966 {
967 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
968 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
969 struct r600_pipe_resource_state *rstate;
970 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
971 unsigned format, endian;
972 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
973 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
974 unsigned width, height, depth, offset_level, last_level;
975
976 if (view == NULL)
977 return NULL;
978 rstate = &view->state;
979
980 /* initialize base object */
981 view->base = *state;
982 view->base.texture = NULL;
983 pipe_reference(NULL, &texture->reference);
984 view->base.texture = texture;
985 view->base.reference.count = 1;
986 view->base.context = ctx;
987
988 swizzle[0] = state->swizzle_r;
989 swizzle[1] = state->swizzle_g;
990 swizzle[2] = state->swizzle_b;
991 swizzle[3] = state->swizzle_a;
992
993 format = r600_translate_texformat(ctx->screen, state->format,
994 swizzle,
995 &word4, &yuv_format);
996 if (format == ~0) {
997 format = 0;
998 }
999
1000 if (tmp->is_depth && !tmp->is_flushing_texture) {
1001 r600_texture_depth_flush(ctx, texture, TRUE);
1002 tmp = tmp->flushed_depth_texture;
1003 }
1004
1005 endian = r600_colorformat_endian_swap(format);
1006
1007 offset_level = state->u.tex.first_level;
1008 last_level = state->u.tex.last_level - offset_level;
1009 if (!rscreen->use_surface_alloc) {
1010 width = u_minify(texture->width0, offset_level);
1011 height = u_minify(texture->height0, offset_level);
1012 depth = u_minify(texture->depth0, offset_level);
1013
1014 pitch = align(tmp->pitch_in_blocks[offset_level] *
1015 util_format_get_blockwidth(state->format), 8);
1016 array_mode = tmp->array_mode[offset_level];
1017 tile_type = tmp->tile_type;
1018
1019 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1020 height = 1;
1021 depth = texture->array_size;
1022 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1023 depth = texture->array_size;
1024 }
1025
1026 rstate->bo[0] = &tmp->resource;
1027 rstate->bo[1] = &tmp->resource;
1028 rstate->bo_usage[0] = RADEON_USAGE_READ;
1029 rstate->bo_usage[1] = RADEON_USAGE_READ;
1030
1031 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1032 S_038000_TILE_MODE(array_mode) |
1033 S_038000_TILE_TYPE(tile_type) |
1034 S_038000_PITCH((pitch / 8) - 1) |
1035 S_038000_TEX_WIDTH(width - 1));
1036 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1037 S_038004_TEX_DEPTH(depth - 1) |
1038 S_038004_DATA_FORMAT(format));
1039 rstate->val[2] = tmp->offset[offset_level] >> 8;
1040 rstate->val[3] = tmp->offset[offset_level+1] >> 8;
1041 rstate->val[4] = (word4 |
1042 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1043 S_038010_REQUEST_SIZE(1) |
1044 S_038010_ENDIAN_SWAP(endian) |
1045 S_038010_BASE_LEVEL(0));
1046 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1047 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1048 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1049 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1050 S_038018_MAX_ANISO(4 /* max 16 samples */));
1051 } else {
1052 width = tmp->surface.level[offset_level].npix_x;
1053 height = tmp->surface.level[offset_level].npix_y;
1054 depth = tmp->surface.level[offset_level].npix_z;
1055 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1056 tile_type = tmp->tile_type;
1057
1058 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1059 height = 1;
1060 depth = texture->array_size;
1061 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1062 depth = texture->array_size;
1063 }
1064 switch (tmp->surface.level[offset_level].mode) {
1065 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1066 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1067 break;
1068 case RADEON_SURF_MODE_1D:
1069 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1070 break;
1071 case RADEON_SURF_MODE_2D:
1072 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1073 break;
1074 case RADEON_SURF_MODE_LINEAR:
1075 default:
1076 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1077 break;
1078 }
1079
1080 rstate->bo[0] = &tmp->resource;
1081 rstate->bo[1] = &tmp->resource;
1082 rstate->bo_usage[0] = RADEON_USAGE_READ;
1083 rstate->bo_usage[1] = RADEON_USAGE_READ;
1084
1085 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1086 S_038000_TILE_MODE(array_mode) |
1087 S_038000_TILE_TYPE(tile_type) |
1088 S_038000_PITCH((pitch / 8) - 1) |
1089 S_038000_TEX_WIDTH(width - 1));
1090 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1091 S_038004_TEX_DEPTH(depth - 1) |
1092 S_038004_DATA_FORMAT(format));
1093 rstate->val[2] = tmp->surface.level[offset_level].offset >> 8;
1094 if (offset_level >= tmp->surface.last_level) {
1095 rstate->val[3] = tmp->surface.level[offset_level].offset >> 8;
1096 } else {
1097 rstate->val[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1098 }
1099 rstate->val[4] = (word4 |
1100 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1101 S_038010_REQUEST_SIZE(1) |
1102 S_038010_ENDIAN_SWAP(endian) |
1103 S_038010_BASE_LEVEL(0));
1104 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1105 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1106 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1107 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1108 S_038018_MAX_ANISO(4 /* max 16 samples */));
1109 }
1110 return &view->base;
1111 }
1112
1113 static void r600_set_sampler_views(struct r600_context *rctx,
1114 struct r600_textures_info *dst,
1115 unsigned count,
1116 struct pipe_sampler_view **views,
1117 void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned))
1118 {
1119 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
1120 unsigned i;
1121
1122 if (count)
1123 r600_inval_texture_cache(rctx);
1124
1125 for (i = 0; i < count; i++) {
1126 if (rviews[i]) {
1127 if (((struct r600_resource_texture *)rviews[i]->base.texture)->is_depth)
1128 rctx->have_depth_texture = true;
1129
1130 /* Changing from array to non-arrays textures and vice versa requires updating TEX_ARRAY_OVERRIDE. */
1131 if ((rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1132 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i])
1133 dst->samplers_dirty = true;
1134
1135 set_resource(rctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS);
1136 } else {
1137 set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
1138 }
1139
1140 pipe_sampler_view_reference(
1141 (struct pipe_sampler_view **)&dst->views[i],
1142 views[i]);
1143 }
1144
1145 for (i = count; i < dst->n_views; i++) {
1146 if (dst->views[i]) {
1147 set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
1148 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL);
1149 }
1150 }
1151
1152 dst->n_views = count;
1153 }
1154
1155 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1156 struct pipe_sampler_view **views)
1157 {
1158 struct r600_context *rctx = (struct r600_context *)ctx;
1159 r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views,
1160 r600_context_pipe_state_set_vs_resource);
1161 }
1162
1163 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1164 struct pipe_sampler_view **views)
1165 {
1166 struct r600_context *rctx = (struct r600_context *)ctx;
1167 r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views,
1168 r600_context_pipe_state_set_ps_resource);
1169 }
1170
1171 static void r600_set_seamless_cubemap(struct r600_context *rctx, boolean enable)
1172 {
1173 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1174 if (rstate == NULL)
1175 return;
1176
1177 rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP;
1178 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1179 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)) |
1180 S_009508_DISABLE_CUBE_ANISO(1) |
1181 S_009508_SYNC_GRADIENT(1) |
1182 S_009508_SYNC_WALKER(1) |
1183 S_009508_SYNC_ALIGNER(1));
1184
1185 free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]);
1186 rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate;
1187 r600_context_pipe_state_set(rctx, rstate);
1188 }
1189
1190 static void r600_bind_samplers(struct r600_context *rctx,
1191 struct r600_textures_info *dst,
1192 unsigned count, void **states)
1193 {
1194 memcpy(dst->samplers, states, sizeof(void*) * count);
1195 dst->n_samplers = count;
1196 dst->samplers_dirty = true;
1197 }
1198
1199 static void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
1200 {
1201 struct r600_context *rctx = (struct r600_context *)ctx;
1202 r600_bind_samplers(rctx, &rctx->vs_samplers, count, states);
1203 }
1204
1205 static void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
1206 {
1207 struct r600_context *rctx = (struct r600_context *)ctx;
1208 r600_bind_samplers(rctx, &rctx->ps_samplers, count, states);
1209 }
1210
1211 static void r600_update_samplers(struct r600_context *rctx,
1212 struct r600_textures_info *tex,
1213 void (*set_sampler)(struct r600_context*, struct r600_pipe_state*, unsigned))
1214 {
1215 unsigned i;
1216
1217 if (tex->samplers_dirty) {
1218 int seamless = -1;
1219 for (i = 0; i < tex->n_samplers; i++) {
1220 if (!tex->samplers[i])
1221 continue;
1222
1223 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1224 * filtering between layers.
1225 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */
1226 if (tex->views[i]) {
1227 if (tex->views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1228 tex->views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1229 tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1230 tex->is_array_sampler[i] = true;
1231 } else {
1232 tex->samplers[i]->rstate.regs[0].value &= C_03C000_TEX_ARRAY_OVERRIDE;
1233 tex->is_array_sampler[i] = false;
1234 }
1235 }
1236
1237 set_sampler(rctx, &tex->samplers[i]->rstate, i);
1238
1239 if (tex->samplers[i])
1240 seamless = tex->samplers[i]->seamless_cube_map;
1241 }
1242
1243 if (seamless != -1)
1244 r600_set_seamless_cubemap(rctx, seamless);
1245
1246 tex->samplers_dirty = false;
1247 }
1248 }
1249
1250 void r600_update_sampler_states(struct r600_context *rctx)
1251 {
1252 r600_update_samplers(rctx, &rctx->vs_samplers,
1253 r600_context_pipe_state_set_vs_sampler);
1254 r600_update_samplers(rctx, &rctx->ps_samplers,
1255 r600_context_pipe_state_set_ps_sampler);
1256 }
1257
1258 static void r600_set_clip_state(struct pipe_context *ctx,
1259 const struct pipe_clip_state *state)
1260 {
1261 struct r600_context *rctx = (struct r600_context *)ctx;
1262 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1263 struct pipe_resource * cbuf;
1264
1265 if (rstate == NULL)
1266 return;
1267
1268 rctx->clip = *state;
1269 rstate->id = R600_PIPE_STATE_CLIP;
1270 for (int i = 0; i < 6; i++) {
1271 r600_pipe_state_add_reg(rstate,
1272 R_028E20_PA_CL_UCP0_X + i * 16,
1273 fui(state->ucp[i][0]));
1274 r600_pipe_state_add_reg(rstate,
1275 R_028E24_PA_CL_UCP0_Y + i * 16,
1276 fui(state->ucp[i][1]) );
1277 r600_pipe_state_add_reg(rstate,
1278 R_028E28_PA_CL_UCP0_Z + i * 16,
1279 fui(state->ucp[i][2]));
1280 r600_pipe_state_add_reg(rstate,
1281 R_028E2C_PA_CL_UCP0_W + i * 16,
1282 fui(state->ucp[i][3]));
1283 }
1284
1285 free(rctx->states[R600_PIPE_STATE_CLIP]);
1286 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1287 r600_context_pipe_state_set(rctx, rstate);
1288
1289 cbuf = pipe_user_buffer_create(ctx->screen,
1290 state->ucp,
1291 4*4*8, /* 8*4 floats */
1292 PIPE_BIND_CONSTANT_BUFFER);
1293 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
1294 pipe_resource_reference(&cbuf, NULL);
1295 }
1296
1297 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1298 const struct pipe_poly_stipple *state)
1299 {
1300 }
1301
1302 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1303 {
1304 }
1305
1306 void r600_set_scissor_state(struct r600_context *rctx,
1307 const struct pipe_scissor_state *state)
1308 {
1309 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1310 uint32_t tl, br;
1311
1312 if (rstate == NULL)
1313 return;
1314
1315 rstate->id = R600_PIPE_STATE_SCISSOR;
1316 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1317 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1318 r600_pipe_state_add_reg(rstate,
1319 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1320 r600_pipe_state_add_reg(rstate,
1321 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1322
1323 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1324 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1325 r600_context_pipe_state_set(rctx, rstate);
1326 }
1327
1328 static void r600_pipe_set_scissor_state(struct pipe_context *ctx,
1329 const struct pipe_scissor_state *state)
1330 {
1331 struct r600_context *rctx = (struct r600_context *)ctx;
1332
1333 if (rctx->chip_class == R600) {
1334 rctx->scissor_state = *state;
1335
1336 if (!rctx->scissor_enable)
1337 return;
1338 }
1339
1340 r600_set_scissor_state(rctx, state);
1341 }
1342
1343 static void r600_set_viewport_state(struct pipe_context *ctx,
1344 const struct pipe_viewport_state *state)
1345 {
1346 struct r600_context *rctx = (struct r600_context *)ctx;
1347 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1348
1349 if (rstate == NULL)
1350 return;
1351
1352 rctx->viewport = *state;
1353 rstate->id = R600_PIPE_STATE_VIEWPORT;
1354 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1355 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1356 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1357 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1358 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1359 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1360
1361 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1362 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1363 r600_context_pipe_state_set(rctx, rstate);
1364 }
1365
1366 static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1367 const struct pipe_framebuffer_state *state, int cb)
1368 {
1369 struct r600_screen *rscreen = rctx->screen;
1370 struct r600_resource_texture *rtex;
1371 struct r600_surface *surf;
1372 unsigned level = state->cbufs[cb]->u.tex.level;
1373 unsigned pitch, slice;
1374 unsigned color_info;
1375 unsigned format, swap, ntype, endian;
1376 unsigned offset;
1377 const struct util_format_description *desc;
1378 int i;
1379 unsigned blend_bypass = 0, blend_clamp = 1;
1380
1381 surf = (struct r600_surface *)state->cbufs[cb];
1382 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1383
1384 if (rtex->is_depth)
1385 rctx->have_depth_fb = TRUE;
1386
1387 if (rtex->is_depth && !rtex->is_flushing_texture) {
1388 rtex = rtex->flushed_depth_texture;
1389 }
1390
1391 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1392 if (!rscreen->use_surface_alloc) {
1393 offset = r600_texture_get_offset(rtex,
1394 level, state->cbufs[cb]->u.tex.first_layer);
1395 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1396 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1397 if (slice) {
1398 slice = slice - 1;
1399 }
1400 color_info = S_0280A0_ARRAY_MODE(rtex->array_mode[level]);
1401 } else {
1402 offset = rtex->surface.level[level].offset;
1403 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1404 offset += rtex->surface.level[level].slice_size *
1405 state->cbufs[cb]->u.tex.first_layer;
1406 }
1407 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1408 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1409 if (slice) {
1410 slice = slice - 1;
1411 }
1412 color_info = 0;
1413 switch (rtex->surface.level[level].mode) {
1414 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1415 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1416 break;
1417 case RADEON_SURF_MODE_1D:
1418 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1419 break;
1420 case RADEON_SURF_MODE_2D:
1421 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1422 break;
1423 case RADEON_SURF_MODE_LINEAR:
1424 default:
1425 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1426 break;
1427 }
1428 }
1429 desc = util_format_description(surf->base.format);
1430
1431 for (i = 0; i < 4; i++) {
1432 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1433 break;
1434 }
1435 }
1436
1437 ntype = V_0280A0_NUMBER_UNORM;
1438 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1439 ntype = V_0280A0_NUMBER_SRGB;
1440 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1441 if (desc->channel[i].normalized)
1442 ntype = V_0280A0_NUMBER_SNORM;
1443 else if (desc->channel[i].pure_integer)
1444 ntype = V_0280A0_NUMBER_SINT;
1445 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1446 if (desc->channel[i].normalized)
1447 ntype = V_0280A0_NUMBER_UNORM;
1448 else if (desc->channel[i].pure_integer)
1449 ntype = V_0280A0_NUMBER_UINT;
1450 }
1451
1452 format = r600_translate_colorformat(surf->base.format);
1453 swap = r600_translate_colorswap(surf->base.format);
1454 if(rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1455 endian = ENDIAN_NONE;
1456 } else {
1457 endian = r600_colorformat_endian_swap(format);
1458 }
1459
1460 /* set blend bypass according to docs if SINT/UINT or
1461 8/24 COLOR variants */
1462 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1463 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1464 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1465 blend_clamp = 0;
1466 blend_bypass = 1;
1467 }
1468
1469 color_info |= S_0280A0_FORMAT(format) |
1470 S_0280A0_COMP_SWAP(swap) |
1471 S_0280A0_BLEND_BYPASS(blend_bypass) |
1472 S_0280A0_BLEND_CLAMP(blend_clamp) |
1473 S_0280A0_NUMBER_TYPE(ntype) |
1474 S_0280A0_ENDIAN(endian);
1475
1476 /* EXPORT_NORM is an optimzation that can be enabled for better
1477 * performance in certain cases
1478 */
1479 if (rctx->chip_class == R600) {
1480 /* EXPORT_NORM can be enabled if:
1481 * - 11-bit or smaller UNORM/SNORM/SRGB
1482 * - BLEND_CLAMP is enabled
1483 * - BLEND_FLOAT32 is disabled
1484 */
1485 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1486 (desc->channel[i].size < 12 &&
1487 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1488 ntype != V_0280A0_NUMBER_UINT &&
1489 ntype != V_0280A0_NUMBER_SINT) &&
1490 G_0280A0_BLEND_CLAMP(color_info) &&
1491 !G_0280A0_BLEND_FLOAT32(color_info))
1492 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1493 } else {
1494 /* EXPORT_NORM can be enabled if:
1495 * - 11-bit or smaller UNORM/SNORM/SRGB
1496 * - 16-bit or smaller FLOAT
1497 */
1498 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1499 ((desc->channel[i].size < 12 &&
1500 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1501 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1502 (desc->channel[i].size < 17 &&
1503 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)))
1504 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1505 }
1506
1507 if (cb == 0)
1508 rctx->color0_format = color_info;
1509
1510 r600_pipe_state_add_reg_bo(rstate,
1511 R_028040_CB_COLOR0_BASE + cb * 4,
1512 offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
1513 r600_pipe_state_add_reg_bo(rstate,
1514 R_0280A0_CB_COLOR0_INFO + cb * 4,
1515 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1516 r600_pipe_state_add_reg(rstate,
1517 R_028060_CB_COLOR0_SIZE + cb * 4,
1518 S_028060_PITCH_TILE_MAX(pitch) |
1519 S_028060_SLICE_TILE_MAX(slice));
1520 if (!rscreen->use_surface_alloc) {
1521 r600_pipe_state_add_reg(rstate,
1522 R_028080_CB_COLOR0_VIEW + cb * 4,
1523 0x00000000);
1524 } else {
1525 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1526 r600_pipe_state_add_reg(rstate,
1527 R_028080_CB_COLOR0_VIEW + cb * 4,
1528 0x00000000);
1529 } else {
1530 r600_pipe_state_add_reg(rstate,
1531 R_028080_CB_COLOR0_VIEW + cb * 4,
1532 S_028080_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1533 S_028080_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1534 }
1535 }
1536 r600_pipe_state_add_reg_bo(rstate,
1537 R_0280E0_CB_COLOR0_FRAG + cb * 4,
1538 0, &rtex->resource, RADEON_USAGE_READWRITE);
1539 r600_pipe_state_add_reg_bo(rstate,
1540 R_0280C0_CB_COLOR0_TILE + cb * 4,
1541 0, &rtex->resource, RADEON_USAGE_READWRITE);
1542 }
1543
1544 static void r600_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1545 const struct pipe_framebuffer_state *state)
1546 {
1547 struct r600_screen *rscreen = rctx->screen;
1548 struct r600_resource_texture *rtex;
1549 struct r600_surface *surf;
1550 unsigned level, pitch, slice, format, offset, array_mode;
1551
1552 if (state->zsbuf == NULL)
1553 return;
1554
1555 level = state->zsbuf->u.tex.level;
1556
1557 surf = (struct r600_surface *)state->zsbuf;
1558 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1559
1560 if (!rscreen->use_surface_alloc) {
1561 /* XXX remove this once tiling is properly supported */
1562 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1563 V_0280A0_ARRAY_1D_TILED_THIN1;
1564
1565 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1566 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1567 level, state->zsbuf->u.tex.first_layer);
1568 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1569 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1570 if (slice) {
1571 slice = slice - 1;
1572 }
1573 } else {
1574 offset = rtex->surface.level[level].offset;
1575 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1576 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1577 if (slice) {
1578 slice = slice - 1;
1579 }
1580 switch (rtex->surface.level[level].mode) {
1581 case RADEON_SURF_MODE_2D:
1582 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1583 break;
1584 case RADEON_SURF_MODE_1D:
1585 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1586 case RADEON_SURF_MODE_LINEAR:
1587 default:
1588 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1589 break;
1590 }
1591 }
1592
1593 format = r600_translate_dbformat(state->zsbuf->texture->format);
1594
1595 r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE,
1596 offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
1597 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1598 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice));
1599 if (!rscreen->use_surface_alloc) {
1600 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000);
1601 } else {
1602 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW,
1603 S_028004_SLICE_START(state->zsbuf->u.tex.first_layer) |
1604 S_028004_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1605 }
1606 r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO,
1607 S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format),
1608 &rtex->resource, RADEON_USAGE_READWRITE);
1609 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1610 (surf->aligned_height / 8) - 1);
1611 }
1612
1613 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1614 const struct pipe_framebuffer_state *state)
1615 {
1616 struct r600_context *rctx = (struct r600_context *)ctx;
1617 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1618 uint32_t tl, br, shader_control;
1619
1620 if (rstate == NULL)
1621 return;
1622
1623 r600_flush_framebuffer(rctx, false);
1624
1625 /* unreference old buffer and reference new one */
1626 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1627
1628 util_copy_framebuffer_state(&rctx->framebuffer, state);
1629
1630 /* build states */
1631 rctx->have_depth_fb = 0;
1632 for (int i = 0; i < state->nr_cbufs; i++) {
1633 r600_cb(rctx, rstate, state, i);
1634 }
1635 if (state->zsbuf) {
1636 r600_db(rctx, rstate, state);
1637 }
1638
1639 shader_control = 0;
1640 rctx->fb_cb_shader_mask = 0;
1641 for (int i = 0; i < state->nr_cbufs; i++) {
1642 shader_control |= 1 << i;
1643 rctx->fb_cb_shader_mask |= 0xf << (i * 4);
1644 }
1645 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1646 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1647
1648 r600_pipe_state_add_reg(rstate,
1649 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1650 r600_pipe_state_add_reg(rstate,
1651 R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1652
1653 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1654 shader_control);
1655
1656 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1657 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1658 r600_context_pipe_state_set(rctx, rstate);
1659
1660 if (state->zsbuf) {
1661 r600_polygon_offset_update(rctx);
1662 }
1663 }
1664
1665 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1666 {
1667 struct radeon_winsys_cs *cs = rctx->cs;
1668 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1669 unsigned db_render_control = 0;
1670 unsigned db_render_override =
1671 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1672 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1673 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1674
1675 if (a->occlusion_query_enabled) {
1676 if (rctx->chip_class >= R700) {
1677 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1678 }
1679 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1680 }
1681 if (a->flush_depthstencil_enabled) {
1682 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(1) |
1683 S_028D0C_STENCIL_COPY_ENABLE(1) |
1684 S_028D0C_COPY_CENTROID(1);
1685 }
1686
1687 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1688 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1689 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1690 }
1691
1692 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1693 {
1694 struct radeon_winsys_cs *cs = rctx->cs;
1695 struct pipe_vertex_buffer *vb = rctx->vertex_buffer;
1696 unsigned count = rctx->nr_vertex_buffers;
1697 unsigned i, offset;
1698
1699 for (i = 0; i < count; i++) {
1700 struct r600_resource *rbuffer = (struct r600_resource*)vb[i].buffer;
1701
1702 if (!rbuffer) {
1703 continue;
1704 }
1705
1706 offset = vb[i].buffer_offset;
1707
1708 /* fetch resources start at index 320 */
1709 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1710 r600_write_value(cs, (320 + i) * 7);
1711 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1712 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1713 r600_write_value(cs, /* RESOURCEi_WORD2 */
1714 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1715 S_038008_STRIDE(vb[i].stride));
1716 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1717 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1718 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1719 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1720
1721 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1722 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1723 }
1724 }
1725
1726 static void r600_emit_constant_buffers(struct r600_context *rctx,
1727 struct r600_constbuf_state *state,
1728 unsigned buffer_id_base,
1729 unsigned reg_alu_constbuf_size,
1730 unsigned reg_alu_const_cache)
1731 {
1732 struct radeon_winsys_cs *cs = rctx->cs;
1733 uint32_t dirty_mask = state->dirty_mask;
1734
1735 while (dirty_mask) {
1736 struct r600_constant_buffer *cb;
1737 struct r600_resource *rbuffer;
1738 unsigned offset;
1739 unsigned buffer_index = ffs(dirty_mask) - 1;
1740
1741 cb = &state->cb[buffer_index];
1742 rbuffer = (struct r600_resource*)cb->buffer;
1743 assert(rbuffer);
1744
1745 offset = cb->buffer_offset;
1746
1747 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1748 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1749 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1750
1751 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1752 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1753
1754 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1755 r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1756 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1757 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1758 r600_write_value(cs, /* RESOURCEi_WORD2 */
1759 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1760 S_038008_STRIDE(16));
1761 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1762 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1763 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1764 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1765
1766 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1767 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1768
1769 dirty_mask &= ~(1 << buffer_index);
1770 }
1771 state->dirty_mask = 0;
1772 }
1773
1774 static void r600_emit_vs_constant_buffer(struct r600_context *rctx, struct r600_atom *atom)
1775 {
1776 r600_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 160,
1777 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1778 R_028980_ALU_CONST_CACHE_VS_0);
1779 }
1780
1781 static void r600_emit_ps_constant_buffer(struct r600_context *rctx, struct r600_atom *atom)
1782 {
1783 r600_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1784 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1785 R_028940_ALU_CONST_CACHE_PS_0);
1786 }
1787
1788 void r600_init_state_functions(struct r600_context *rctx)
1789 {
1790 r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0);
1791 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1792 r600_init_atom(&rctx->vertex_buffer_state, r600_emit_vertex_buffers, 0, 0);
1793 r600_init_atom(&rctx->vs_constbuf_state.atom, r600_emit_vs_constant_buffer, 0, 0);
1794 r600_init_atom(&rctx->ps_constbuf_state.atom, r600_emit_ps_constant_buffer, 0, 0);
1795
1796 rctx->context.create_blend_state = r600_create_blend_state;
1797 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1798 rctx->context.create_fs_state = r600_create_shader_state;
1799 rctx->context.create_rasterizer_state = r600_create_rs_state;
1800 rctx->context.create_sampler_state = r600_create_sampler_state;
1801 rctx->context.create_sampler_view = r600_create_sampler_view;
1802 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1803 rctx->context.create_vs_state = r600_create_shader_state;
1804 rctx->context.bind_blend_state = r600_bind_blend_state;
1805 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1806 rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1807 rctx->context.bind_fs_state = r600_bind_ps_shader;
1808 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1809 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1810 rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1811 rctx->context.bind_vs_state = r600_bind_vs_shader;
1812 rctx->context.delete_blend_state = r600_delete_state;
1813 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1814 rctx->context.delete_fs_state = r600_delete_ps_shader;
1815 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1816 rctx->context.delete_sampler_state = r600_delete_state;
1817 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1818 rctx->context.delete_vs_state = r600_delete_vs_shader;
1819 rctx->context.set_blend_color = r600_set_blend_color;
1820 rctx->context.set_clip_state = r600_set_clip_state;
1821 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1822 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1823 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1824 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1825 rctx->context.set_sample_mask = r600_set_sample_mask;
1826 rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
1827 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1828 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1829 rctx->context.set_index_buffer = r600_set_index_buffer;
1830 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1831 rctx->context.set_viewport_state = r600_set_viewport_state;
1832 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1833 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1834 rctx->context.texture_barrier = r600_texture_barrier;
1835 rctx->context.create_stream_output_target = r600_create_so_target;
1836 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1837 rctx->context.set_stream_output_targets = r600_set_so_targets;
1838 }
1839
1840 void r600_adjust_gprs(struct r600_context *rctx)
1841 {
1842 struct r600_pipe_state rstate;
1843 unsigned num_ps_gprs = rctx->default_ps_gprs;
1844 unsigned num_vs_gprs = rctx->default_vs_gprs;
1845 unsigned tmp;
1846 int diff;
1847
1848 if (rctx->chip_class >= EVERGREEN)
1849 return;
1850
1851 if (!rctx->ps_shader || !rctx->vs_shader)
1852 return;
1853
1854 if (rctx->ps_shader->shader.bc.ngpr > rctx->default_ps_gprs)
1855 {
1856 diff = rctx->ps_shader->shader.bc.ngpr - rctx->default_ps_gprs;
1857 num_vs_gprs -= diff;
1858 num_ps_gprs += diff;
1859 }
1860
1861 if (rctx->vs_shader->shader.bc.ngpr > rctx->default_vs_gprs)
1862 {
1863 diff = rctx->vs_shader->shader.bc.ngpr - rctx->default_vs_gprs;
1864 num_ps_gprs -= diff;
1865 num_vs_gprs += diff;
1866 }
1867
1868 tmp = 0;
1869 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1870 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1871 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
1872 rstate.nregs = 0;
1873 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
1874
1875 r600_context_pipe_state_set(rctx, &rstate);
1876 }
1877
1878 void r600_init_atom_start_cs(struct r600_context *rctx)
1879 {
1880 int ps_prio;
1881 int vs_prio;
1882 int gs_prio;
1883 int es_prio;
1884 int num_ps_gprs;
1885 int num_vs_gprs;
1886 int num_gs_gprs;
1887 int num_es_gprs;
1888 int num_temp_gprs;
1889 int num_ps_threads;
1890 int num_vs_threads;
1891 int num_gs_threads;
1892 int num_es_threads;
1893 int num_ps_stack_entries;
1894 int num_vs_stack_entries;
1895 int num_gs_stack_entries;
1896 int num_es_stack_entries;
1897 enum radeon_family family;
1898 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1899 uint32_t tmp;
1900 unsigned i;
1901
1902 r600_init_command_buffer(cb, 256, EMIT_EARLY);
1903
1904 /* R6xx requires this packet at the start of each command buffer */
1905 if (rctx->chip_class == R600) {
1906 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
1907 r600_store_value(cb, 0);
1908 }
1909 /* All asics require this one */
1910 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1911 r600_store_value(cb, 0x80000000);
1912 r600_store_value(cb, 0x80000000);
1913
1914 family = rctx->family;
1915 ps_prio = 0;
1916 vs_prio = 1;
1917 gs_prio = 2;
1918 es_prio = 3;
1919 switch (family) {
1920 case CHIP_R600:
1921 num_ps_gprs = 192;
1922 num_vs_gprs = 56;
1923 num_temp_gprs = 4;
1924 num_gs_gprs = 0;
1925 num_es_gprs = 0;
1926 num_ps_threads = 136;
1927 num_vs_threads = 48;
1928 num_gs_threads = 4;
1929 num_es_threads = 4;
1930 num_ps_stack_entries = 128;
1931 num_vs_stack_entries = 128;
1932 num_gs_stack_entries = 0;
1933 num_es_stack_entries = 0;
1934 break;
1935 case CHIP_RV630:
1936 case CHIP_RV635:
1937 num_ps_gprs = 84;
1938 num_vs_gprs = 36;
1939 num_temp_gprs = 4;
1940 num_gs_gprs = 0;
1941 num_es_gprs = 0;
1942 num_ps_threads = 144;
1943 num_vs_threads = 40;
1944 num_gs_threads = 4;
1945 num_es_threads = 4;
1946 num_ps_stack_entries = 40;
1947 num_vs_stack_entries = 40;
1948 num_gs_stack_entries = 32;
1949 num_es_stack_entries = 16;
1950 break;
1951 case CHIP_RV610:
1952 case CHIP_RV620:
1953 case CHIP_RS780:
1954 case CHIP_RS880:
1955 default:
1956 num_ps_gprs = 84;
1957 num_vs_gprs = 36;
1958 num_temp_gprs = 4;
1959 num_gs_gprs = 0;
1960 num_es_gprs = 0;
1961 num_ps_threads = 136;
1962 num_vs_threads = 48;
1963 num_gs_threads = 4;
1964 num_es_threads = 4;
1965 num_ps_stack_entries = 40;
1966 num_vs_stack_entries = 40;
1967 num_gs_stack_entries = 32;
1968 num_es_stack_entries = 16;
1969 break;
1970 case CHIP_RV670:
1971 num_ps_gprs = 144;
1972 num_vs_gprs = 40;
1973 num_temp_gprs = 4;
1974 num_gs_gprs = 0;
1975 num_es_gprs = 0;
1976 num_ps_threads = 136;
1977 num_vs_threads = 48;
1978 num_gs_threads = 4;
1979 num_es_threads = 4;
1980 num_ps_stack_entries = 40;
1981 num_vs_stack_entries = 40;
1982 num_gs_stack_entries = 32;
1983 num_es_stack_entries = 16;
1984 break;
1985 case CHIP_RV770:
1986 num_ps_gprs = 192;
1987 num_vs_gprs = 56;
1988 num_temp_gprs = 4;
1989 num_gs_gprs = 0;
1990 num_es_gprs = 0;
1991 num_ps_threads = 188;
1992 num_vs_threads = 60;
1993 num_gs_threads = 0;
1994 num_es_threads = 0;
1995 num_ps_stack_entries = 256;
1996 num_vs_stack_entries = 256;
1997 num_gs_stack_entries = 0;
1998 num_es_stack_entries = 0;
1999 break;
2000 case CHIP_RV730:
2001 case CHIP_RV740:
2002 num_ps_gprs = 84;
2003 num_vs_gprs = 36;
2004 num_temp_gprs = 4;
2005 num_gs_gprs = 0;
2006 num_es_gprs = 0;
2007 num_ps_threads = 188;
2008 num_vs_threads = 60;
2009 num_gs_threads = 0;
2010 num_es_threads = 0;
2011 num_ps_stack_entries = 128;
2012 num_vs_stack_entries = 128;
2013 num_gs_stack_entries = 0;
2014 num_es_stack_entries = 0;
2015 break;
2016 case CHIP_RV710:
2017 num_ps_gprs = 192;
2018 num_vs_gprs = 56;
2019 num_temp_gprs = 4;
2020 num_gs_gprs = 0;
2021 num_es_gprs = 0;
2022 num_ps_threads = 144;
2023 num_vs_threads = 48;
2024 num_gs_threads = 0;
2025 num_es_threads = 0;
2026 num_ps_stack_entries = 128;
2027 num_vs_stack_entries = 128;
2028 num_gs_stack_entries = 0;
2029 num_es_stack_entries = 0;
2030 break;
2031 }
2032
2033 rctx->default_ps_gprs = num_ps_gprs;
2034 rctx->default_vs_gprs = num_vs_gprs;
2035 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2036
2037 /* SQ_CONFIG */
2038 tmp = 0;
2039 switch (family) {
2040 case CHIP_RV610:
2041 case CHIP_RV620:
2042 case CHIP_RS780:
2043 case CHIP_RS880:
2044 case CHIP_RV710:
2045 break;
2046 default:
2047 tmp |= S_008C00_VC_ENABLE(1);
2048 break;
2049 }
2050 tmp |= S_008C00_DX9_CONSTS(0);
2051 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2052 tmp |= S_008C00_PS_PRIO(ps_prio);
2053 tmp |= S_008C00_VS_PRIO(vs_prio);
2054 tmp |= S_008C00_GS_PRIO(gs_prio);
2055 tmp |= S_008C00_ES_PRIO(es_prio);
2056 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2057
2058 /* SQ_GPR_RESOURCE_MGMT_2 */
2059 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2060 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2061 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2062 r600_store_value(cb, tmp);
2063
2064 /* SQ_THREAD_RESOURCE_MGMT */
2065 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2066 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2067 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2068 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2069 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2070
2071 /* SQ_STACK_RESOURCE_MGMT_1 */
2072 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2073 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2074 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2075
2076 /* SQ_STACK_RESOURCE_MGMT_2 */
2077 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2078 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2079 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2080
2081 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2082
2083 if (rctx->chip_class >= R700) {
2084 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2085 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2086 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2087 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2088 } else {
2089 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2090 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2091 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2092 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2093 }
2094 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2095 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2096 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2097 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2098 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2099 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2100 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2101 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2102 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2103 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2104
2105 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2106 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2107 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2108 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2109 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2110 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2111 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2112 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2113 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2114 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2115 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2116 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2117 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2118 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2119
2120 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2121 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2122 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2123
2124 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2125 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2126 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2127 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2128
2129 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2130
2131 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2132 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2133 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2134
2135 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2136
2137 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2138 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2139 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2140
2141 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2142 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2143 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2144 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2145
2146 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2147 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2148 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2149
2150 r600_store_context_reg(cb, R_028D44_DB_ALPHA_TO_MASK, 0xAA00);
2151
2152 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2153 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2154
2155 r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2156 r600_store_value(cb, 0x400); /* R_028C00_PA_SC_LINE_CNTL */
2157 r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2158
2159 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 6);
2160 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2161 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2162 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2163 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2164 r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
2165 r600_store_value(cb, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX */
2166
2167 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2168 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2169 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2170
2171 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2172
2173 r600_store_context_reg_seq(cb, R_028100_CB_COLOR0_MASK, 8);
2174 for (i = 0; i < 8; i++) {
2175 r600_store_value(cb, 0);
2176 }
2177
2178 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2179 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2180
2181 if (rctx->chip_class >= R700) {
2182 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2183 }
2184
2185 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2186 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2187 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2188 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2189 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2190
2191 r600_store_context_reg(cb, R_028C48_PA_SC_AA_MASK, 0xFFFFFFFF);
2192
2193 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2194 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2195 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2196
2197 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2198 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2199 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2200
2201 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2202 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2203 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2204
2205 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2206 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2207
2208 if (rctx->chip_class == R700 && rctx->screen->info.r600_has_streamout)
2209 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2210 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2211
2212 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2213 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2214 }
2215
2216 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2217 {
2218 struct r600_context *rctx = (struct r600_context *)ctx;
2219 struct r600_pipe_state *rstate = &shader->rstate;
2220 struct r600_shader *rshader = &shader->shader;
2221 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2222 int pos_index = -1, face_index = -1;
2223 unsigned tmp, sid, ufi = 0;
2224 int need_linear = 0;
2225
2226 rstate->nregs = 0;
2227
2228 for (i = 0; i < rshader->ninput; i++) {
2229 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2230 pos_index = i;
2231 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2232 face_index = i;
2233
2234 sid = rshader->input[i].spi_sid;
2235
2236 tmp = S_028644_SEMANTIC(sid);
2237
2238 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2239 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2240 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2241 rctx->rasterizer && rctx->rasterizer->flatshade))
2242 tmp |= S_028644_FLAT_SHADE(1);
2243
2244 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2245 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2246 tmp |= S_028644_PT_SPRITE_TEX(1);
2247 }
2248
2249 if (rshader->input[i].centroid)
2250 tmp |= S_028644_SEL_CENTROID(1);
2251
2252 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2253 need_linear = 1;
2254 tmp |= S_028644_SEL_LINEAR(1);
2255 }
2256
2257 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2258 tmp);
2259 }
2260
2261 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2262 for (i = 0; i < rshader->noutput; i++) {
2263 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2264 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2265 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2266 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
2267 }
2268 if (rshader->uses_kill)
2269 db_shader_control |= S_02880C_KILL_ENABLE(1);
2270
2271 exports_ps = 0;
2272 num_cout = 0;
2273 for (i = 0; i < rshader->noutput; i++) {
2274 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2275 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2276 exports_ps |= 1;
2277 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2278 num_cout++;
2279 }
2280 }
2281 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2282 if (!exports_ps) {
2283 /* always at least export 1 component per pixel */
2284 exports_ps = 2;
2285 }
2286
2287 shader->ps_cb_shader_mask = (1ULL << ((unsigned)num_cout * 4)) - 1;
2288
2289 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2290 S_0286CC_PERSP_GRADIENT_ENA(1)|
2291 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2292 spi_input_z = 0;
2293 if (pos_index != -1) {
2294 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2295 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2296 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2297 S_0286CC_BARYC_SAMPLE_CNTL(1));
2298 spi_input_z |= 1;
2299 }
2300
2301 spi_ps_in_control_1 = 0;
2302 if (face_index != -1) {
2303 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2304 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2305 }
2306
2307 /* HW bug in original R600 */
2308 if (rctx->family == CHIP_R600)
2309 ufi = 1;
2310
2311 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2312 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2313 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2314 r600_pipe_state_add_reg_bo(rstate,
2315 R_028840_SQ_PGM_START_PS,
2316 0, shader->bo, RADEON_USAGE_READ);
2317 r600_pipe_state_add_reg(rstate,
2318 R_028850_SQ_PGM_RESOURCES_PS,
2319 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2320 S_028850_STACK_SIZE(rshader->bc.nstack) |
2321 S_028850_UNCACHED_FIRST_INST(ufi));
2322 r600_pipe_state_add_reg(rstate,
2323 R_028854_SQ_PGM_EXPORTS_PS,
2324 exports_ps);
2325 /* only set some bits here, the other bits are set in the dsa state */
2326 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2327 db_shader_control);
2328
2329 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2330 if (rctx->rasterizer)
2331 shader->flatshade = rctx->rasterizer->flatshade;
2332 }
2333
2334 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2335 {
2336 struct r600_context *rctx = (struct r600_context *)ctx;
2337 struct r600_pipe_state *rstate = &shader->rstate;
2338 struct r600_shader *rshader = &shader->shader;
2339 unsigned spi_vs_out_id[10] = {};
2340 unsigned i, tmp, nparams = 0;
2341
2342 /* clear previous register */
2343 rstate->nregs = 0;
2344
2345 for (i = 0; i < rshader->noutput; i++) {
2346 if (rshader->output[i].spi_sid) {
2347 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2348 spi_vs_out_id[nparams / 4] |= tmp;
2349 nparams++;
2350 }
2351 }
2352
2353 for (i = 0; i < 10; i++) {
2354 r600_pipe_state_add_reg(rstate,
2355 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2356 spi_vs_out_id[i]);
2357 }
2358
2359 /* Certain attributes (position, psize, etc.) don't count as params.
2360 * VS is required to export at least one param and r600_shader_from_tgsi()
2361 * takes care of adding a dummy export.
2362 */
2363 if (nparams < 1)
2364 nparams = 1;
2365
2366 r600_pipe_state_add_reg(rstate,
2367 R_0286C4_SPI_VS_OUT_CONFIG,
2368 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2369 r600_pipe_state_add_reg(rstate,
2370 R_028868_SQ_PGM_RESOURCES_VS,
2371 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2372 S_028868_STACK_SIZE(rshader->bc.nstack));
2373 r600_pipe_state_add_reg_bo(rstate,
2374 R_028858_SQ_PGM_START_VS,
2375 0, shader->bo, RADEON_USAGE_READ);
2376
2377 shader->pa_cl_vs_out_cntl =
2378 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2379 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2380 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2381 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2382 }
2383
2384 void r600_fetch_shader(struct pipe_context *ctx,
2385 struct r600_vertex_element *ve)
2386 {
2387 struct r600_pipe_state *rstate;
2388 struct r600_context *rctx = (struct r600_context *)ctx;
2389
2390 rstate = &ve->rstate;
2391 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2392 rstate->nregs = 0;
2393 r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS,
2394 0,
2395 ve->fetch_shader, RADEON_USAGE_READ);
2396 }
2397
2398 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2399 {
2400 struct pipe_depth_stencil_alpha_state dsa;
2401 struct r600_pipe_state *rstate;
2402 struct r600_pipe_dsa *dsa_state;
2403 boolean quirk = false;
2404
2405 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2406 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2407 quirk = true;
2408
2409 memset(&dsa, 0, sizeof(dsa));
2410
2411 if (quirk) {
2412 dsa.depth.enabled = 1;
2413 dsa.depth.func = PIPE_FUNC_LEQUAL;
2414 dsa.stencil[0].enabled = 1;
2415 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2416 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2417 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2418 dsa.stencil[0].writemask = 0xff;
2419 }
2420
2421 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2422 dsa_state = (struct r600_pipe_dsa*)rstate;
2423 dsa_state->is_flush = true;
2424 return rstate;
2425 }