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1be641798f7a624f3227cfa46fcbcac66233f314
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_framebuffer.h>
40 #include "util/u_transfer.h"
41 #include <pipebuffer/pb_buffer.h>
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_state_inlines.h"
48
49 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
50 {
51 struct r600_pipe_state state;
52
53 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
54 state.nregs = 0;
55 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
56 float offset_units = rctx->rasterizer->offset_units;
57 unsigned offset_db_fmt_cntl = 0, depth;
58
59 switch (rctx->framebuffer.zsbuf->texture->format) {
60 case PIPE_FORMAT_Z24X8_UNORM:
61 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
62 depth = -24;
63 offset_units *= 2.0f;
64 break;
65 case PIPE_FORMAT_Z32_FLOAT:
66 depth = -23;
67 offset_units *= 1.0f;
68 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
69 break;
70 case PIPE_FORMAT_Z16_UNORM:
71 depth = -16;
72 offset_units *= 4.0f;
73 break;
74 default:
75 return;
76 }
77 /* FIXME some of those reg can be computed with cso */
78 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
79 r600_pipe_state_add_reg(&state,
80 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
81 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
82 r600_pipe_state_add_reg(&state,
83 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
84 fui(offset_units), 0xFFFFFFFF, NULL);
85 r600_pipe_state_add_reg(&state,
86 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
87 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
88 r600_pipe_state_add_reg(&state,
89 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
90 fui(offset_units), 0xFFFFFFFF, NULL);
91 r600_pipe_state_add_reg(&state,
92 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
93 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
94 r600_context_pipe_state_set(&rctx->ctx, &state);
95 }
96 }
97
98 static void r600_set_blend_color(struct pipe_context *ctx,
99 const struct pipe_blend_color *state)
100 {
101 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
102 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
103
104 if (rstate == NULL)
105 return;
106
107 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
108 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
109 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
110 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
111 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
112 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
113 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
114 r600_context_pipe_state_set(&rctx->ctx, rstate);
115 }
116
117 static void *r600_create_blend_state(struct pipe_context *ctx,
118 const struct pipe_blend_state *state)
119 {
120 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
121 struct r600_pipe_state *rstate;
122 u32 color_control, target_mask;
123
124 if (blend == NULL) {
125 return NULL;
126 }
127 rstate = &blend->rstate;
128
129 rstate->id = R600_PIPE_STATE_BLEND;
130
131 target_mask = 0;
132 color_control = S_028808_PER_MRT_BLEND(1);
133 if (state->logicop_enable) {
134 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
135 } else {
136 color_control |= (0xcc << 16);
137 }
138 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
139 if (state->independent_blend_enable) {
140 for (int i = 0; i < 8; i++) {
141 if (state->rt[i].blend_enable) {
142 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
143 }
144 target_mask |= (state->rt[i].colormask << (4 * i));
145 }
146 } else {
147 for (int i = 0; i < 8; i++) {
148 if (state->rt[0].blend_enable) {
149 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
150 }
151 target_mask |= (state->rt[0].colormask << (4 * i));
152 }
153 }
154 blend->cb_target_mask = target_mask;
155 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
156 color_control, 0xFFFFFFFF, NULL);
157
158 for (int i = 0; i < 8; i++) {
159 unsigned eqRGB = state->rt[i].rgb_func;
160 unsigned srcRGB = state->rt[i].rgb_src_factor;
161 unsigned dstRGB = state->rt[i].rgb_dst_factor;
162
163 unsigned eqA = state->rt[i].alpha_func;
164 unsigned srcA = state->rt[i].alpha_src_factor;
165 unsigned dstA = state->rt[i].alpha_dst_factor;
166 uint32_t bc = 0;
167
168 if (!state->rt[i].blend_enable)
169 continue;
170
171 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
172 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
173 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
174
175 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
176 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
177 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
178 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
179 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
180 }
181
182 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
183 if (i == 0) {
184 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
185 }
186 }
187 return rstate;
188 }
189
190 static void *r600_create_dsa_state(struct pipe_context *ctx,
191 const struct pipe_depth_stencil_alpha_state *state)
192 {
193 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
194 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
195 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
196
197 if (rstate == NULL) {
198 return NULL;
199 }
200
201 rstate->id = R600_PIPE_STATE_DSA;
202 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
203 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
204 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
205 * be set if shader use texkill instruction
206 */
207 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
208 stencil_ref_mask = 0;
209 stencil_ref_mask_bf = 0;
210 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
211 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
212 S_028800_ZFUNC(state->depth.func);
213
214 /* stencil */
215 if (state->stencil[0].enabled) {
216 db_depth_control |= S_028800_STENCIL_ENABLE(1);
217 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
218 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
219 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
220 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
221
222
223 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
224 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
225 if (state->stencil[1].enabled) {
226 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
227 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
228 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
229 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
230 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
231 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
232 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
233 }
234 }
235
236 /* alpha */
237 alpha_test_control = 0;
238 alpha_ref = 0;
239 if (state->alpha.enabled) {
240 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
241 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
242 alpha_ref = fui(state->alpha.ref_value);
243 }
244
245 /* misc */
246 db_render_control = 0;
247 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
248 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
249 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
250 /* TODO db_render_override depends on query */
251 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
252 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
253 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
254 r600_pipe_state_add_reg(rstate,
255 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
256 0xFFFFFFFF & C_028430_STENCILREF, NULL);
257 r600_pipe_state_add_reg(rstate,
258 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
259 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
260 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
261 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
262 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
263 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
264 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
265 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
266 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
267 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
268 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
269 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
270 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
271
272 return rstate;
273 }
274
275 static void *r600_create_rs_state(struct pipe_context *ctx,
276 const struct pipe_rasterizer_state *state)
277 {
278 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
279 struct r600_pipe_state *rstate;
280 unsigned tmp;
281 unsigned prov_vtx = 1, polygon_dual_mode;
282 unsigned clip_rule;
283
284 if (rs == NULL) {
285 return NULL;
286 }
287
288 rstate = &rs->rstate;
289 rs->flatshade = state->flatshade;
290 rs->sprite_coord_enable = state->sprite_coord_enable;
291
292 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
293 /* offset */
294 rs->offset_units = state->offset_units;
295 rs->offset_scale = state->offset_scale * 12.0f;
296
297 rstate->id = R600_PIPE_STATE_RASTERIZER;
298 if (state->flatshade_first)
299 prov_vtx = 0;
300 tmp = S_0286D4_FLAT_SHADE_ENA(1);
301 if (state->sprite_coord_enable) {
302 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
303 S_0286D4_PNT_SPRITE_OVRD_X(2) |
304 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
305 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
306 S_0286D4_PNT_SPRITE_OVRD_W(1);
307 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
308 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
309 }
310 }
311 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
312
313 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
314 state->fill_back != PIPE_POLYGON_MODE_FILL);
315 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
316 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
317 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
318 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
319 S_028814_FACE(!state->front_ccw) |
320 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
321 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
322 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
323 S_028814_POLY_MODE(polygon_dual_mode) |
324 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
325 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
326 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
327 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
328 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
329 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
330 /* point size 12.4 fixed point */
331 tmp = (unsigned)(state->point_size * 8.0);
332 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
333 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
334
335 tmp = (unsigned)state->line_width * 8;
336 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
337
338 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
339 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
340 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
341
342 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
343 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
344 0xFFFFFFFF, NULL);
345
346 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
347 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
348 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
349 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
350 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
351 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
352
353 return rstate;
354 }
355
356 static void *r600_create_sampler_state(struct pipe_context *ctx,
357 const struct pipe_sampler_state *state)
358 {
359 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
360 union util_color uc;
361 uint32_t coord_trunc = 0;
362
363 if (rstate == NULL) {
364 return NULL;
365 }
366
367 if ((state->mag_img_filter == PIPE_TEX_FILTER_NEAREST) ||
368 (state->min_img_filter == PIPE_TEX_FILTER_NEAREST))
369 coord_trunc = 1;
370
371 rstate->id = R600_PIPE_STATE_SAMPLER;
372 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
373 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
374 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
375 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
376 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
377 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
378 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
379 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
380 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
381 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
382 /* FIXME LOD it depends on texture base level ... */
383 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
384 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
385 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
386 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
387 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
388 S_03C008_MC_COORD_TRUNCATE(coord_trunc) |
389 S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
390 if (uc.ui) {
391 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
392 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
393 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
394 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
395 }
396 return rstate;
397 }
398
399 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
400 struct pipe_resource *texture,
401 const struct pipe_sampler_view *state)
402 {
403 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
404 struct r600_pipe_state *rstate;
405 const struct util_format_description *desc;
406 struct r600_resource_texture *tmp;
407 struct r600_resource *rbuffer;
408 unsigned format;
409 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
410 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
411 struct r600_bo *bo[2];
412 unsigned height, depth;
413
414 if (resource == NULL)
415 return NULL;
416 rstate = &resource->state;
417
418 /* initialize base object */
419 resource->base = *state;
420 resource->base.texture = NULL;
421 pipe_reference(NULL, &texture->reference);
422 resource->base.texture = texture;
423 resource->base.reference.count = 1;
424 resource->base.context = ctx;
425
426 swizzle[0] = state->swizzle_r;
427 swizzle[1] = state->swizzle_g;
428 swizzle[2] = state->swizzle_b;
429 swizzle[3] = state->swizzle_a;
430 format = r600_translate_texformat(ctx->screen, state->format,
431 swizzle,
432 &word4, &yuv_format);
433 if (format == ~0) {
434 format = 0;
435 }
436 desc = util_format_description(state->format);
437 if (desc == NULL) {
438 R600_ERR("unknow format %d\n", state->format);
439 }
440 tmp = (struct r600_resource_texture *)texture;
441 if (tmp->depth && !tmp->is_flushing_texture) {
442 r600_texture_depth_flush(ctx, texture, TRUE);
443 tmp = tmp->flushed_depth_texture;
444 }
445
446 if (tmp->force_int_type) {
447 word4 &= C_038010_NUM_FORMAT_ALL;
448 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
449 }
450 rbuffer = &tmp->resource;
451 bo[0] = rbuffer->bo;
452 bo[1] = rbuffer->bo;
453 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8);
454 array_mode = tmp->array_mode[0];
455 tile_type = tmp->tile_type;
456
457 height = texture->height0;
458 depth = texture->depth0;
459 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
460 height = 1;
461 depth = texture->array_size;
462 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
463 depth = texture->array_size;
464 }
465
466 /* FIXME properly handle first level != 0 */
467 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
468 S_038000_DIM(r600_tex_dim(texture->target)) |
469 S_038000_TILE_MODE(array_mode) |
470 S_038000_TILE_TYPE(tile_type) |
471 S_038000_PITCH((pitch / 8) - 1) |
472 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
473 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
474 S_038004_TEX_HEIGHT(height - 1) |
475 S_038004_TEX_DEPTH(depth - 1) |
476 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
477 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
478 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
479 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
480 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
481 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
482 word4 |
483 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_NO_ZERO) |
484 S_038010_REQUEST_SIZE(1) |
485 S_038010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
486 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
487 S_038014_LAST_LEVEL(state->u.tex.last_level) |
488 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
489 S_038014_LAST_ARRAY(state->u.tex.last_layer), 0xFFFFFFFF, NULL);
490 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
491 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
492
493 return &resource->base;
494 }
495
496 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
497 struct pipe_sampler_view **views)
498 {
499 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
500 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
501
502 for (int i = 0; i < count; i++) {
503 if (resource[i]) {
504 r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i);
505 }
506 }
507 }
508
509 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
510 struct pipe_sampler_view **views)
511 {
512 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
513 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
514 int i;
515
516 for (i = 0; i < count; i++) {
517 if (&rctx->ps_samplers.views[i]->base != views[i]) {
518 if (resource[i])
519 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
520 i + R600_MAX_CONST_BUFFERS);
521 else
522 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
523 i + R600_MAX_CONST_BUFFERS);
524
525 pipe_sampler_view_reference(
526 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
527 views[i]);
528
529 }
530 }
531 for (i = count; i < NUM_TEX_UNITS; i++) {
532 if (rctx->ps_samplers.views[i]) {
533 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
534 i + R600_MAX_CONST_BUFFERS);
535 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
536 }
537 }
538 rctx->ps_samplers.n_views = count;
539 }
540
541 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
542 {
543 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
544 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
545
546 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
547 rctx->ps_samplers.n_samplers = count;
548
549 for (int i = 0; i < count; i++) {
550 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
551 }
552 }
553
554 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
555 {
556 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
557 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
558
559 for (int i = 0; i < count; i++) {
560 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
561 }
562 }
563
564 static void r600_set_clip_state(struct pipe_context *ctx,
565 const struct pipe_clip_state *state)
566 {
567 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
568 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
569
570 if (rstate == NULL)
571 return;
572
573 rctx->clip = *state;
574 rstate->id = R600_PIPE_STATE_CLIP;
575 for (int i = 0; i < state->nr; i++) {
576 r600_pipe_state_add_reg(rstate,
577 R_028E20_PA_CL_UCP0_X + i * 16,
578 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
579 r600_pipe_state_add_reg(rstate,
580 R_028E24_PA_CL_UCP0_Y + i * 16,
581 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
582 r600_pipe_state_add_reg(rstate,
583 R_028E28_PA_CL_UCP0_Z + i * 16,
584 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
585 r600_pipe_state_add_reg(rstate,
586 R_028E2C_PA_CL_UCP0_W + i * 16,
587 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
588 }
589 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
590 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
591 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
592 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
593
594 free(rctx->states[R600_PIPE_STATE_CLIP]);
595 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
596 r600_context_pipe_state_set(&rctx->ctx, rstate);
597 }
598
599 static void r600_set_polygon_stipple(struct pipe_context *ctx,
600 const struct pipe_poly_stipple *state)
601 {
602 }
603
604 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
605 {
606 }
607
608 static void r600_set_scissor_state(struct pipe_context *ctx,
609 const struct pipe_scissor_state *state)
610 {
611 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
612 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
613 u32 tl, br;
614
615 if (rstate == NULL)
616 return;
617
618 rstate->id = R600_PIPE_STATE_SCISSOR;
619 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
620 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
621 r600_pipe_state_add_reg(rstate,
622 R_028210_PA_SC_CLIPRECT_0_TL, tl,
623 0xFFFFFFFF, NULL);
624 r600_pipe_state_add_reg(rstate,
625 R_028214_PA_SC_CLIPRECT_0_BR, br,
626 0xFFFFFFFF, NULL);
627 r600_pipe_state_add_reg(rstate,
628 R_028218_PA_SC_CLIPRECT_1_TL, tl,
629 0xFFFFFFFF, NULL);
630 r600_pipe_state_add_reg(rstate,
631 R_02821C_PA_SC_CLIPRECT_1_BR, br,
632 0xFFFFFFFF, NULL);
633 r600_pipe_state_add_reg(rstate,
634 R_028220_PA_SC_CLIPRECT_2_TL, tl,
635 0xFFFFFFFF, NULL);
636 r600_pipe_state_add_reg(rstate,
637 R_028224_PA_SC_CLIPRECT_2_BR, br,
638 0xFFFFFFFF, NULL);
639 r600_pipe_state_add_reg(rstate,
640 R_028228_PA_SC_CLIPRECT_3_TL, tl,
641 0xFFFFFFFF, NULL);
642 r600_pipe_state_add_reg(rstate,
643 R_02822C_PA_SC_CLIPRECT_3_BR, br,
644 0xFFFFFFFF, NULL);
645
646 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
647 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
648 r600_context_pipe_state_set(&rctx->ctx, rstate);
649 }
650
651 static void r600_set_stencil_ref(struct pipe_context *ctx,
652 const struct pipe_stencil_ref *state)
653 {
654 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
655 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
656 u32 tmp;
657
658 if (rstate == NULL)
659 return;
660
661 rctx->stencil_ref = *state;
662 rstate->id = R600_PIPE_STATE_STENCIL_REF;
663 tmp = S_028430_STENCILREF(state->ref_value[0]);
664 r600_pipe_state_add_reg(rstate,
665 R_028430_DB_STENCILREFMASK, tmp,
666 ~C_028430_STENCILREF, NULL);
667 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
668 r600_pipe_state_add_reg(rstate,
669 R_028434_DB_STENCILREFMASK_BF, tmp,
670 ~C_028434_STENCILREF_BF, NULL);
671
672 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
673 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
674 r600_context_pipe_state_set(&rctx->ctx, rstate);
675 }
676
677 static void r600_set_viewport_state(struct pipe_context *ctx,
678 const struct pipe_viewport_state *state)
679 {
680 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
681 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
682
683 if (rstate == NULL)
684 return;
685
686 rctx->viewport = *state;
687 rstate->id = R600_PIPE_STATE_VIEWPORT;
688 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
689 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
690 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
691 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
692 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
693 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
694 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
695 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
696 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
697
698 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
699 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
700 r600_context_pipe_state_set(&rctx->ctx, rstate);
701 }
702
703 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
704 const struct pipe_framebuffer_state *state, int cb)
705 {
706 struct r600_resource_texture *rtex;
707 struct r600_resource *rbuffer;
708 struct r600_surface *surf;
709 unsigned level = state->cbufs[cb]->u.tex.level;
710 unsigned pitch, slice;
711 unsigned color_info;
712 unsigned format, swap, ntype;
713 unsigned offset;
714 const struct util_format_description *desc;
715 struct r600_bo *bo[3];
716 int i;
717
718 surf = (struct r600_surface *)state->cbufs[cb];
719 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
720
721 if (rtex->depth && !rtex->is_flushing_texture) {
722 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
723 rtex = rtex->flushed_depth_texture;
724 }
725
726 rbuffer = &rtex->resource;
727 bo[0] = rbuffer->bo;
728 bo[1] = rbuffer->bo;
729 bo[2] = rbuffer->bo;
730
731 /* XXX quite sure for dx10+ hw don't need any offset hacks */
732 offset = r600_texture_get_offset(rtex,
733 level, state->cbufs[cb]->u.tex.first_layer);
734 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
735 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
736 ntype = 0;
737 desc = util_format_description(surf->base.format);
738 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
739 ntype = V_0280A0_NUMBER_SRGB;
740 else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
741 switch(desc->channel[0].type) {
742 case UTIL_FORMAT_TYPE_UNSIGNED:
743 ntype = V_0280A0_NUMBER_UNORM;
744 break;
745
746 case UTIL_FORMAT_TYPE_SIGNED:
747 ntype = V_0280A0_NUMBER_SNORM;
748 break;
749 }
750 }
751
752 for (i = 0; i < 4; i++) {
753 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
754 break;
755 }
756 }
757
758 format = r600_translate_colorformat(surf->base.format);
759 swap = r600_translate_colorswap(surf->base.format);
760
761 /* disable when gallium grows int textures */
762 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
763 ntype = 4;
764
765 color_info = S_0280A0_FORMAT(format) |
766 S_0280A0_COMP_SWAP(swap) |
767 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
768 S_0280A0_BLEND_CLAMP(1) |
769 S_0280A0_NUMBER_TYPE(ntype);
770
771 /* on R600 this can't be set if BLEND_CLAMP isn't set,
772 if BLEND_FLOAT32 is set of > 11 bits in a UNORM or SNORM */
773 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
774 desc->channel[i].size < 12)
775 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
776
777 r600_pipe_state_add_reg(rstate,
778 R_028040_CB_COLOR0_BASE + cb * 4,
779 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
780 r600_pipe_state_add_reg(rstate,
781 R_0280A0_CB_COLOR0_INFO + cb * 4,
782 color_info, 0xFFFFFFFF, bo[0]);
783 r600_pipe_state_add_reg(rstate,
784 R_028060_CB_COLOR0_SIZE + cb * 4,
785 S_028060_PITCH_TILE_MAX(pitch) |
786 S_028060_SLICE_TILE_MAX(slice),
787 0xFFFFFFFF, NULL);
788 r600_pipe_state_add_reg(rstate,
789 R_028080_CB_COLOR0_VIEW + cb * 4,
790 0x00000000, 0xFFFFFFFF, NULL);
791 r600_pipe_state_add_reg(rstate,
792 R_0280E0_CB_COLOR0_FRAG + cb * 4,
793 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
794 r600_pipe_state_add_reg(rstate,
795 R_0280C0_CB_COLOR0_TILE + cb * 4,
796 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
797 r600_pipe_state_add_reg(rstate,
798 R_028100_CB_COLOR0_MASK + cb * 4,
799 0x00000000, 0xFFFFFFFF, NULL);
800 }
801
802 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
803 const struct pipe_framebuffer_state *state)
804 {
805 struct r600_resource_texture *rtex;
806 struct r600_resource *rbuffer;
807 struct r600_surface *surf;
808 unsigned level;
809 unsigned pitch, slice, format;
810 unsigned offset;
811
812 if (state->zsbuf == NULL)
813 return;
814
815 level = state->zsbuf->u.tex.level;
816
817 surf = (struct r600_surface *)state->zsbuf;
818 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
819
820 rbuffer = &rtex->resource;
821
822 /* XXX quite sure for dx10+ hw don't need any offset hacks */
823 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
824 level, state->zsbuf->u.tex.first_layer);
825 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
826 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
827 format = r600_translate_dbformat(state->zsbuf->texture->format);
828
829 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
830 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
831 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
832 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
833 0xFFFFFFFF, NULL);
834 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
835 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
836 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
837 0xFFFFFFFF, rbuffer->bo);
838 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
839 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL);
840 }
841
842 static void r600_set_framebuffer_state(struct pipe_context *ctx,
843 const struct pipe_framebuffer_state *state)
844 {
845 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
846 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
847 u32 shader_mask, tl, br, shader_control, target_mask;
848
849 if (rstate == NULL)
850 return;
851
852 /* unreference old buffer and reference new one */
853 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
854
855 util_copy_framebuffer_state(&rctx->framebuffer, state);
856
857 /* build states */
858 for (int i = 0; i < state->nr_cbufs; i++) {
859 r600_cb(rctx, rstate, state, i);
860 }
861 if (state->zsbuf) {
862 r600_db(rctx, rstate, state);
863 }
864
865 target_mask = 0x00000000;
866 target_mask = 0xFFFFFFFF;
867 shader_mask = 0;
868 shader_control = 0;
869 for (int i = 0; i < state->nr_cbufs; i++) {
870 target_mask ^= 0xf << (i * 4);
871 shader_mask |= 0xf << (i * 4);
872 shader_control |= 1 << i;
873 }
874 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
875 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
876
877 r600_pipe_state_add_reg(rstate,
878 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
879 0xFFFFFFFF, NULL);
880 r600_pipe_state_add_reg(rstate,
881 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
882 0xFFFFFFFF, NULL);
883 r600_pipe_state_add_reg(rstate,
884 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
885 0xFFFFFFFF, NULL);
886 r600_pipe_state_add_reg(rstate,
887 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
888 0xFFFFFFFF, NULL);
889 r600_pipe_state_add_reg(rstate,
890 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
891 0xFFFFFFFF, NULL);
892 r600_pipe_state_add_reg(rstate,
893 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
894 0xFFFFFFFF, NULL);
895 r600_pipe_state_add_reg(rstate,
896 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
897 0xFFFFFFFF, NULL);
898 r600_pipe_state_add_reg(rstate,
899 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
900 0xFFFFFFFF, NULL);
901 r600_pipe_state_add_reg(rstate,
902 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
903 0xFFFFFFFF, NULL);
904 if (rctx->family >= CHIP_RV770) {
905 r600_pipe_state_add_reg(rstate,
906 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
907 0xFFFFFFFF, NULL);
908 }
909
910 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
911 shader_control, 0xFFFFFFFF, NULL);
912 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
913 0x00000000, target_mask, NULL);
914 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
915 shader_mask, 0xFFFFFFFF, NULL);
916 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
917 0x00000000, 0xFFFFFFFF, NULL);
918 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
919 0x00000000, 0xFFFFFFFF, NULL);
920 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
921 0x00000000, 0xFFFFFFFF, NULL);
922 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
923 0x01000000, 0xFFFFFFFF, NULL);
924 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
925 0x00000000, 0xFFFFFFFF, NULL);
926 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
927 0x000000FF, 0xFFFFFFFF, NULL);
928 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
929 0xFFFFFFFF, 0xFFFFFFFF, NULL);
930 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
931 0xFFFFFFFF, 0xFFFFFFFF, NULL);
932
933 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
934 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
935 r600_context_pipe_state_set(&rctx->ctx, rstate);
936
937 if (state->zsbuf) {
938 r600_polygon_offset_update(rctx);
939 }
940 }
941
942 void r600_init_state_functions(struct r600_pipe_context *rctx)
943 {
944 rctx->context.create_blend_state = r600_create_blend_state;
945 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
946 rctx->context.create_fs_state = r600_create_shader_state;
947 rctx->context.create_rasterizer_state = r600_create_rs_state;
948 rctx->context.create_sampler_state = r600_create_sampler_state;
949 rctx->context.create_sampler_view = r600_create_sampler_view;
950 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
951 rctx->context.create_vs_state = r600_create_shader_state;
952 rctx->context.bind_blend_state = r600_bind_blend_state;
953 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
954 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
955 rctx->context.bind_fs_state = r600_bind_ps_shader;
956 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
957 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
958 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
959 rctx->context.bind_vs_state = r600_bind_vs_shader;
960 rctx->context.delete_blend_state = r600_delete_state;
961 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
962 rctx->context.delete_fs_state = r600_delete_ps_shader;
963 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
964 rctx->context.delete_sampler_state = r600_delete_state;
965 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
966 rctx->context.delete_vs_state = r600_delete_vs_shader;
967 rctx->context.set_blend_color = r600_set_blend_color;
968 rctx->context.set_clip_state = r600_set_clip_state;
969 rctx->context.set_constant_buffer = r600_set_constant_buffer;
970 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
971 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
972 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
973 rctx->context.set_sample_mask = r600_set_sample_mask;
974 rctx->context.set_scissor_state = r600_set_scissor_state;
975 rctx->context.set_stencil_ref = r600_set_stencil_ref;
976 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
977 rctx->context.set_index_buffer = r600_set_index_buffer;
978 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
979 rctx->context.set_viewport_state = r600_set_viewport_state;
980 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
981 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
982 }
983
984 void r600_init_config(struct r600_pipe_context *rctx)
985 {
986 int ps_prio;
987 int vs_prio;
988 int gs_prio;
989 int es_prio;
990 int num_ps_gprs;
991 int num_vs_gprs;
992 int num_gs_gprs;
993 int num_es_gprs;
994 int num_temp_gprs;
995 int num_ps_threads;
996 int num_vs_threads;
997 int num_gs_threads;
998 int num_es_threads;
999 int num_ps_stack_entries;
1000 int num_vs_stack_entries;
1001 int num_gs_stack_entries;
1002 int num_es_stack_entries;
1003 enum radeon_family family;
1004 struct r600_pipe_state *rstate = &rctx->config;
1005 u32 tmp;
1006
1007 family = r600_get_family(rctx->radeon);
1008 ps_prio = 0;
1009 vs_prio = 1;
1010 gs_prio = 2;
1011 es_prio = 3;
1012 switch (family) {
1013 case CHIP_R600:
1014 num_ps_gprs = 192;
1015 num_vs_gprs = 56;
1016 num_temp_gprs = 4;
1017 num_gs_gprs = 0;
1018 num_es_gprs = 0;
1019 num_ps_threads = 136;
1020 num_vs_threads = 48;
1021 num_gs_threads = 4;
1022 num_es_threads = 4;
1023 num_ps_stack_entries = 128;
1024 num_vs_stack_entries = 128;
1025 num_gs_stack_entries = 0;
1026 num_es_stack_entries = 0;
1027 break;
1028 case CHIP_RV630:
1029 case CHIP_RV635:
1030 num_ps_gprs = 84;
1031 num_vs_gprs = 36;
1032 num_temp_gprs = 4;
1033 num_gs_gprs = 0;
1034 num_es_gprs = 0;
1035 num_ps_threads = 144;
1036 num_vs_threads = 40;
1037 num_gs_threads = 4;
1038 num_es_threads = 4;
1039 num_ps_stack_entries = 40;
1040 num_vs_stack_entries = 40;
1041 num_gs_stack_entries = 32;
1042 num_es_stack_entries = 16;
1043 break;
1044 case CHIP_RV610:
1045 case CHIP_RV620:
1046 case CHIP_RS780:
1047 case CHIP_RS880:
1048 default:
1049 num_ps_gprs = 84;
1050 num_vs_gprs = 36;
1051 num_temp_gprs = 4;
1052 num_gs_gprs = 0;
1053 num_es_gprs = 0;
1054 num_ps_threads = 136;
1055 num_vs_threads = 48;
1056 num_gs_threads = 4;
1057 num_es_threads = 4;
1058 num_ps_stack_entries = 40;
1059 num_vs_stack_entries = 40;
1060 num_gs_stack_entries = 32;
1061 num_es_stack_entries = 16;
1062 break;
1063 case CHIP_RV670:
1064 num_ps_gprs = 144;
1065 num_vs_gprs = 40;
1066 num_temp_gprs = 4;
1067 num_gs_gprs = 0;
1068 num_es_gprs = 0;
1069 num_ps_threads = 136;
1070 num_vs_threads = 48;
1071 num_gs_threads = 4;
1072 num_es_threads = 4;
1073 num_ps_stack_entries = 40;
1074 num_vs_stack_entries = 40;
1075 num_gs_stack_entries = 32;
1076 num_es_stack_entries = 16;
1077 break;
1078 case CHIP_RV770:
1079 num_ps_gprs = 192;
1080 num_vs_gprs = 56;
1081 num_temp_gprs = 4;
1082 num_gs_gprs = 0;
1083 num_es_gprs = 0;
1084 num_ps_threads = 188;
1085 num_vs_threads = 60;
1086 num_gs_threads = 0;
1087 num_es_threads = 0;
1088 num_ps_stack_entries = 256;
1089 num_vs_stack_entries = 256;
1090 num_gs_stack_entries = 0;
1091 num_es_stack_entries = 0;
1092 break;
1093 case CHIP_RV730:
1094 case CHIP_RV740:
1095 num_ps_gprs = 84;
1096 num_vs_gprs = 36;
1097 num_temp_gprs = 4;
1098 num_gs_gprs = 0;
1099 num_es_gprs = 0;
1100 num_ps_threads = 188;
1101 num_vs_threads = 60;
1102 num_gs_threads = 0;
1103 num_es_threads = 0;
1104 num_ps_stack_entries = 128;
1105 num_vs_stack_entries = 128;
1106 num_gs_stack_entries = 0;
1107 num_es_stack_entries = 0;
1108 break;
1109 case CHIP_RV710:
1110 num_ps_gprs = 192;
1111 num_vs_gprs = 56;
1112 num_temp_gprs = 4;
1113 num_gs_gprs = 0;
1114 num_es_gprs = 0;
1115 num_ps_threads = 144;
1116 num_vs_threads = 48;
1117 num_gs_threads = 0;
1118 num_es_threads = 0;
1119 num_ps_stack_entries = 128;
1120 num_vs_stack_entries = 128;
1121 num_gs_stack_entries = 0;
1122 num_es_stack_entries = 0;
1123 break;
1124 }
1125
1126 rstate->id = R600_PIPE_STATE_CONFIG;
1127
1128 /* SQ_CONFIG */
1129 tmp = 0;
1130 switch (family) {
1131 case CHIP_RV610:
1132 case CHIP_RV620:
1133 case CHIP_RS780:
1134 case CHIP_RS880:
1135 case CHIP_RV710:
1136 break;
1137 default:
1138 tmp |= S_008C00_VC_ENABLE(1);
1139 break;
1140 }
1141 tmp |= S_008C00_DX9_CONSTS(0);
1142 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1143 tmp |= S_008C00_PS_PRIO(ps_prio);
1144 tmp |= S_008C00_VS_PRIO(vs_prio);
1145 tmp |= S_008C00_GS_PRIO(gs_prio);
1146 tmp |= S_008C00_ES_PRIO(es_prio);
1147 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1148
1149 /* SQ_GPR_RESOURCE_MGMT_1 */
1150 tmp = 0;
1151 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1152 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1153 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1154 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1155
1156 /* SQ_GPR_RESOURCE_MGMT_2 */
1157 tmp = 0;
1158 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1159 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1160 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1161
1162 /* SQ_THREAD_RESOURCE_MGMT */
1163 tmp = 0;
1164 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1165 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1166 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1167 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1168 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1169
1170 /* SQ_STACK_RESOURCE_MGMT_1 */
1171 tmp = 0;
1172 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1173 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1174 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1175
1176 /* SQ_STACK_RESOURCE_MGMT_2 */
1177 tmp = 0;
1178 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1179 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1180 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1181
1182 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1183 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1184
1185 if (family >= CHIP_RV770) {
1186 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1187 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1188 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1189 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1190 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1191 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
1192 } else {
1193 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1194 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1195 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1196 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1197 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1198 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
1199 }
1200 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1201 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1202 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1203 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1204 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1205 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1206 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1207 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1208 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1209 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1210 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1211 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1212 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1213 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1214 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1215 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1216 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1217 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1218 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1219 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1220 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1221 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1222 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1223 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1224 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1225 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1226
1227 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1228 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1229 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1230 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1231 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1232 r600_context_pipe_state_set(&rctx->ctx, rstate);
1233 }
1234
1235 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1236 {
1237 struct pipe_depth_stencil_alpha_state dsa;
1238 struct r600_pipe_state *rstate;
1239 boolean quirk = false;
1240
1241 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1242 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1243 quirk = true;
1244
1245 memset(&dsa, 0, sizeof(dsa));
1246
1247 if (quirk) {
1248 dsa.depth.enabled = 1;
1249 dsa.depth.func = PIPE_FUNC_LEQUAL;
1250 dsa.stencil[0].enabled = 1;
1251 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1252 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1253 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1254 dsa.stencil[0].writemask = 0xff;
1255 }
1256
1257 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1258 r600_pipe_state_add_reg(rstate,
1259 R_02880C_DB_SHADER_CONTROL,
1260 0x0,
1261 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1262 r600_pipe_state_add_reg(rstate,
1263 R_028D0C_DB_RENDER_CONTROL,
1264 S_028D0C_DEPTH_COPY_ENABLE(1) |
1265 S_028D0C_STENCIL_COPY_ENABLE(1) |
1266 S_028D0C_COPY_CENTROID(1),
1267 S_028D0C_DEPTH_COPY_ENABLE(1) |
1268 S_028D0C_STENCIL_COPY_ENABLE(1) |
1269 S_028D0C_COPY_CENTROID(1), NULL);
1270 return rstate;
1271 }
1272
1273 void r600_pipe_set_buffer_resource(struct r600_pipe_context *rctx,
1274 struct r600_pipe_state *rstate,
1275 struct r600_resource *rbuffer,
1276 unsigned offset, unsigned stride)
1277 {
1278 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
1279 offset, 0xFFFFFFFF, rbuffer->bo);
1280 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
1281 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
1282 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
1283 S_038008_STRIDE(stride),
1284 0xFFFFFFFF, NULL);
1285 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
1286 0x00000000, 0xFFFFFFFF, NULL);
1287 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
1288 0x00000000, 0xFFFFFFFF, NULL);
1289 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
1290 0x00000000, 0xFFFFFFFF, NULL);
1291 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
1292 0xC0000000, 0xFFFFFFFF, NULL);
1293 }