projects / mesa.git / blob
? search:


2071fef403d2929029b37940d8ae061fdc747269
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <stdio.h>
27 #include <errno.h>
28 #include "util/u_inlines.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "r600_screen.h"
32 #include "r600_context.h"
33 #include "r600_resource.h"
34 #include "r600d.h"
35 #include "r600_state_inlines.h"
36
37 static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state);
38 static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state);
39 static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_clip_state *state);
40 static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_sampler_state *state, unsigned id);
41 static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate, const struct pipe_sampler_view *view, unsigned id);
42 static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
43 const struct pipe_framebuffer_state *state, int cb);
44 static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
45 const struct pipe_framebuffer_state *state);
46
47
48 static void *r600_create_blend_state(struct pipe_context *ctx,
49 const struct pipe_blend_state *state)
50 {
51 struct r600_context *rctx = r600_context(ctx);
52
53 return r600_context_state(rctx, pipe_blend_type, state);
54 }
55
56 static void *r600_create_dsa_state(struct pipe_context *ctx,
57 const struct pipe_depth_stencil_alpha_state *state)
58 {
59 struct r600_context *rctx = r600_context(ctx);
60
61 return r600_context_state(rctx, pipe_dsa_type, state);
62 }
63
64 static void *r600_create_rs_state(struct pipe_context *ctx,
65 const struct pipe_rasterizer_state *state)
66 {
67 struct r600_context *rctx = r600_context(ctx);
68
69 return r600_context_state(rctx, pipe_rasterizer_type, state);
70 }
71
72 static void *r600_create_sampler_state(struct pipe_context *ctx,
73 const struct pipe_sampler_state *state)
74 {
75 struct r600_context *rctx = r600_context(ctx);
76
77 return r600_context_state(rctx, pipe_sampler_type, state);
78 }
79
80 static void r600_sampler_view_destroy(struct pipe_context *ctx,
81 struct pipe_sampler_view *state)
82 {
83 struct r600_context_state *rstate = (struct r600_context_state *)state;
84
85 r600_context_state_decref(rstate);
86 }
87
88 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
89 struct pipe_resource *texture,
90 const struct pipe_sampler_view *state)
91 {
92 struct r600_context *rctx = r600_context(ctx);
93 struct r600_context_state *rstate;
94
95 rstate = r600_context_state(rctx, pipe_sampler_view_type, state);
96 pipe_reference(NULL, &texture->reference);
97 rstate->state.sampler_view.texture = texture;
98 rstate->state.sampler_view.reference.count = 1;
99 rstate->state.sampler_view.context = ctx;
100 r600_resource(ctx, &rstate->rstate[0], &rstate->state.sampler_view, 0);
101 return &rstate->state.sampler_view;
102 }
103
104 static void r600_set_ps_sampler_view(struct pipe_context *ctx,
105 unsigned count,
106 struct pipe_sampler_view **views)
107 {
108 struct r600_context *rctx = r600_context(ctx);
109 struct r600_context_state *rstate;
110 unsigned i;
111
112 for (i = 0; i < rctx->ps_nsampler_view; i++) {
113 radeon_draw_unbind(&rctx->draw, rctx->ps_sampler_view[i]);
114 }
115 for (i = 0; i < count; i++) {
116 rstate = (struct r600_context_state *)views[i];
117 if (rstate) {
118 rstate->nrstate = 0;
119 }
120 }
121 for (i = 0; i < count; i++) {
122 rstate = (struct r600_context_state *)views[i];
123 if (rstate) {
124 if (rstate->nrstate >= R600_MAX_RSTATE)
125 continue;
126 if (rstate->nrstate) {
127 memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
128 }
129 radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_RESOURCE, i, R600_SHADER_PS);
130 rctx->ps_sampler_view[i] = &rstate->rstate[rstate->nrstate];
131 rstate->nrstate++;
132 }
133 }
134 rctx->ps_nsampler_view = count;
135 }
136
137 static void r600_set_vs_sampler_view(struct pipe_context *ctx,
138 unsigned count,
139 struct pipe_sampler_view **views)
140 {
141 struct r600_context *rctx = r600_context(ctx);
142 struct r600_context_state *rstate;
143 unsigned i;
144
145 for (i = 0; i < rctx->vs_nsampler_view; i++) {
146 radeon_draw_unbind(&rctx->draw, rctx->vs_sampler_view[i]);
147 }
148 for (i = 0; i < count; i++) {
149 rstate = (struct r600_context_state *)views[i];
150 if (rstate) {
151 rstate->nrstate = 0;
152 }
153 }
154 for (i = 0; i < count; i++) {
155 rstate = (struct r600_context_state *)views[i];
156 if (rstate) {
157 if (rstate->nrstate >= R600_MAX_RSTATE)
158 continue;
159 if (rstate->nrstate) {
160 memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
161 }
162 radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_RESOURCE, i, R600_SHADER_VS);
163 rctx->vs_sampler_view[i] = &rstate->rstate[rstate->nrstate];
164 rstate->nrstate++;
165 }
166 }
167 rctx->vs_nsampler_view = count;
168 }
169
170 static void *r600_create_shader_state(struct pipe_context *ctx,
171 const struct pipe_shader_state *state)
172 {
173 struct r600_context *rctx = r600_context(ctx);
174
175 return r600_context_state(rctx, pipe_shader_type, state);
176 }
177
178 static void *r600_create_vertex_elements(struct pipe_context *ctx,
179 unsigned count,
180 const struct pipe_vertex_element *elements)
181 {
182 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
183
184 assert(count < 32);
185 v->count = count;
186 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
187 v->refcount = 1;
188 return v;
189 }
190
191 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
192 {
193 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
194
195 if (v == NULL)
196 return;
197 if (--v->refcount)
198 return;
199 free(v);
200 }
201
202 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
203 {
204 struct r600_context *rctx = r600_context(ctx);
205 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
206
207 r600_delete_vertex_element(ctx, rctx->vertex_elements);
208 rctx->vertex_elements = v;
209 if (v) {
210 v->refcount++;
211 }
212 }
213
214 static void r600_bind_state(struct pipe_context *ctx, void *state)
215 {
216 struct r600_context *rctx = r600_context(ctx);
217 struct r600_context_state *rstate = (struct r600_context_state *)state;
218
219 if (state == NULL)
220 return;
221 switch (rstate->type) {
222 case pipe_rasterizer_type:
223 rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
224 rctx->rasterizer = r600_context_state_incref(rstate);
225 break;
226 case pipe_poly_stipple_type:
227 rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
228 rctx->poly_stipple = r600_context_state_incref(rstate);
229 break;
230 case pipe_scissor_type:
231 rctx->scissor = r600_context_state_decref(rctx->scissor);
232 rctx->scissor = r600_context_state_incref(rstate);
233 break;
234 case pipe_clip_type:
235 rctx->clip = r600_context_state_decref(rctx->clip);
236 rctx->clip = r600_context_state_incref(rstate);
237 break;
238 case pipe_depth_type:
239 rctx->depth = r600_context_state_decref(rctx->depth);
240 rctx->depth = r600_context_state_incref(rstate);
241 break;
242 case pipe_stencil_type:
243 rctx->stencil = r600_context_state_decref(rctx->stencil);
244 rctx->stencil = r600_context_state_incref(rstate);
245 break;
246 case pipe_alpha_type:
247 rctx->alpha = r600_context_state_decref(rctx->alpha);
248 rctx->alpha = r600_context_state_incref(rstate);
249 break;
250 case pipe_dsa_type:
251 rctx->dsa = r600_context_state_decref(rctx->dsa);
252 rctx->dsa = r600_context_state_incref(rstate);
253 break;
254 case pipe_blend_type:
255 rctx->blend = r600_context_state_decref(rctx->blend);
256 rctx->blend = r600_context_state_incref(rstate);
257 break;
258 case pipe_framebuffer_type:
259 rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
260 rctx->framebuffer = r600_context_state_incref(rstate);
261 break;
262 case pipe_stencil_ref_type:
263 rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
264 rctx->stencil_ref = r600_context_state_incref(rstate);
265 break;
266 case pipe_viewport_type:
267 rctx->viewport = r600_context_state_decref(rctx->viewport);
268 rctx->viewport = r600_context_state_incref(rstate);
269 break;
270 case pipe_shader_type:
271 case pipe_sampler_type:
272 case pipe_sampler_view_type:
273 default:
274 R600_ERR("invalid type %d\n", rstate->type);
275 return;
276 }
277 }
278
279 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
280 {
281 struct r600_context *rctx = r600_context(ctx);
282 struct r600_context_state *rstate = (struct r600_context_state *)state;
283
284 rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
285 rctx->ps_shader = r600_context_state_incref(rstate);
286 }
287
288 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
289 {
290 struct r600_context *rctx = r600_context(ctx);
291 struct r600_context_state *rstate = (struct r600_context_state *)state;
292
293 rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
294 rctx->vs_shader = r600_context_state_incref(rstate);
295 }
296
297 static void r600_bind_ps_sampler(struct pipe_context *ctx,
298 unsigned count, void **states)
299 {
300 struct r600_context *rctx = r600_context(ctx);
301 struct r600_context_state *rstate;
302 unsigned i;
303
304 for (i = 0; i < rctx->ps_nsampler; i++) {
305 radeon_draw_unbind(&rctx->draw, rctx->ps_sampler[i]);
306 }
307 for (i = 0; i < count; i++) {
308 rstate = (struct r600_context_state *)states[i];
309 if (rstate) {
310 rstate->nrstate = 0;
311 }
312 }
313 for (i = 0; i < count; i++) {
314 rstate = (struct r600_context_state *)states[i];
315 if (rstate) {
316 if (rstate->nrstate >= R600_MAX_RSTATE)
317 continue;
318 if (rstate->nrstate) {
319 memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
320 }
321 radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_SAMPLER, i, R600_SHADER_PS);
322 rctx->ps_sampler[i] = &rstate->rstate[rstate->nrstate];
323 rstate->nrstate++;
324 }
325 }
326 rctx->ps_nsampler = count;
327 }
328
329 static void r600_bind_vs_sampler(struct pipe_context *ctx,
330 unsigned count, void **states)
331 {
332 struct r600_context *rctx = r600_context(ctx);
333 struct r600_context_state *rstate;
334 unsigned i;
335
336 for (i = 0; i < rctx->vs_nsampler; i++) {
337 radeon_draw_unbind(&rctx->draw, rctx->vs_sampler[i]);
338 }
339 for (i = 0; i < count; i++) {
340 rstate = (struct r600_context_state *)states[i];
341 if (rstate) {
342 rstate->nrstate = 0;
343 }
344 }
345 for (i = 0; i < count; i++) {
346 rstate = (struct r600_context_state *)states[i];
347 if (rstate) {
348 if (rstate->nrstate >= R600_MAX_RSTATE)
349 continue;
350 if (rstate->nrstate) {
351 memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
352 }
353 radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_SAMPLER, i, R600_SHADER_VS);
354 rctx->vs_sampler[i] = &rstate->rstate[rstate->nrstate];
355 rstate->nrstate++;
356 }
357 }
358 rctx->vs_nsampler = count;
359 }
360
361 static void r600_delete_state(struct pipe_context *ctx, void *state)
362 {
363 struct r600_context_state *rstate = (struct r600_context_state *)state;
364
365 r600_context_state_decref(rstate);
366 }
367
368 static void r600_set_blend_color(struct pipe_context *ctx,
369 const struct pipe_blend_color *color)
370 {
371 struct r600_context *rctx = r600_context(ctx);
372
373 rctx->blend_color = *color;
374 }
375
376 static void r600_set_clip_state(struct pipe_context *ctx,
377 const struct pipe_clip_state *state)
378 {
379 struct r600_context *rctx = r600_context(ctx);
380 struct r600_context_state *rstate;
381
382 rstate = r600_context_state(rctx, pipe_clip_type, state);
383 r600_bind_state(ctx, rstate);
384 /* refcount is taken care of this */
385 r600_delete_state(ctx, rstate);
386 }
387
388 static void r600_set_constant_buffer(struct pipe_context *ctx,
389 uint shader, uint index,
390 struct pipe_resource *buffer)
391 {
392 struct r600_screen *rscreen = r600_screen(ctx->screen);
393 struct r600_context *rctx = r600_context(ctx);
394 unsigned nconstant = 0, i, type, shader_class;
395 struct radeon_state *rstate, *rstates;
396 struct pipe_transfer *transfer;
397 u32 *ptr;
398
399 type = R600_STATE_CONSTANT;
400
401 switch (shader) {
402 case PIPE_SHADER_VERTEX:
403 shader_class = R600_SHADER_VS;
404 rstates = rctx->vs_constant;
405 break;
406 case PIPE_SHADER_FRAGMENT:
407 shader_class = R600_SHADER_PS;
408 rstates = rctx->ps_constant;
409 break;
410 default:
411 R600_ERR("unsupported %d\n", shader);
412 return;
413 }
414 if (buffer && buffer->width0 > 0) {
415 nconstant = buffer->width0 / 16;
416 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
417 if (ptr == NULL)
418 return;
419 for (i = 0; i < nconstant; i++) {
420 rstate = &rstates[i];
421 radeon_state_init(rstate, rscreen->rw, type, i, shader_class);
422 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
423 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
424 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
425 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
426 if (radeon_state_pm4(rstate))
427 return;
428 radeon_draw_bind(&rctx->draw, rstate);
429 }
430 pipe_buffer_unmap(ctx, buffer, transfer);
431 }
432 }
433
434 static void r600_set_framebuffer_state(struct pipe_context *ctx,
435 const struct pipe_framebuffer_state *state)
436 {
437 struct r600_context *rctx = r600_context(ctx);
438 struct r600_context_state *rstate;
439
440 rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
441 r600_bind_state(ctx, rstate);
442 for (int i = 0; i < state->nr_cbufs; i++) {
443 r600_cb(rctx, &rstate->rstate[i+1], state, i);
444 }
445 if (state->zsbuf) {
446 r600_db(rctx, &rstate->rstate[0], state);
447 }
448 }
449
450 static void r600_set_polygon_stipple(struct pipe_context *ctx,
451 const struct pipe_poly_stipple *state)
452 {
453 }
454
455 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
456 {
457 }
458
459 static void r600_set_scissor_state(struct pipe_context *ctx,
460 const struct pipe_scissor_state *state)
461 {
462 struct r600_context *rctx = r600_context(ctx);
463 struct r600_context_state *rstate;
464
465 rstate = r600_context_state(rctx, pipe_scissor_type, state);
466 r600_bind_state(ctx, rstate);
467 /* refcount is taken care of this */
468 r600_delete_state(ctx, rstate);
469 }
470
471 static void r600_set_stencil_ref(struct pipe_context *ctx,
472 const struct pipe_stencil_ref *state)
473 {
474 struct r600_context *rctx = r600_context(ctx);
475 struct r600_context_state *rstate;
476
477 rstate = r600_context_state(rctx, pipe_stencil_ref_type, state);
478 r600_bind_state(ctx, rstate);
479 /* refcount is taken care of this */
480 r600_delete_state(ctx, rstate);
481 }
482
483 static void r600_set_vertex_buffers(struct pipe_context *ctx,
484 unsigned count,
485 const struct pipe_vertex_buffer *buffers)
486 {
487 struct r600_context *rctx = r600_context(ctx);
488 unsigned i;
489
490 for (i = 0; i < rctx->nvertex_buffer; i++) {
491 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
492 }
493 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
494 for (i = 0; i < count; i++) {
495 rctx->vertex_buffer[i].buffer = NULL;
496 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
497 }
498 rctx->nvertex_buffer = count;
499 }
500
501 static void r600_set_index_buffer(struct pipe_context *ctx,
502 const struct pipe_index_buffer *ib)
503 {
504 struct r600_context *rctx = r600_context(ctx);
505
506 if (ib) {
507 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
508 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
509 } else {
510 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
511 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
512 }
513
514 /* TODO make this more like a state */
515 }
516
517 static void r600_set_viewport_state(struct pipe_context *ctx,
518 const struct pipe_viewport_state *state)
519 {
520 struct r600_context *rctx = r600_context(ctx);
521 struct r600_context_state *rstate;
522
523 rstate = r600_context_state(rctx, pipe_viewport_type, state);
524 r600_bind_state(ctx, rstate);
525 r600_delete_state(ctx, rstate);
526 }
527
528 void r600_init_state_functions(struct r600_context *rctx)
529 {
530 rctx->context.create_blend_state = r600_create_blend_state;
531 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
532 rctx->context.create_fs_state = r600_create_shader_state;
533 rctx->context.create_rasterizer_state = r600_create_rs_state;
534 rctx->context.create_sampler_state = r600_create_sampler_state;
535 rctx->context.create_sampler_view = r600_create_sampler_view;
536 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
537 rctx->context.create_vs_state = r600_create_shader_state;
538 rctx->context.bind_blend_state = r600_bind_state;
539 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
540 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
541 rctx->context.bind_fs_state = r600_bind_ps_shader;
542 rctx->context.bind_rasterizer_state = r600_bind_state;
543 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
544 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
545 rctx->context.bind_vs_state = r600_bind_vs_shader;
546 rctx->context.delete_blend_state = r600_delete_state;
547 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
548 rctx->context.delete_fs_state = r600_delete_state;
549 rctx->context.delete_rasterizer_state = r600_delete_state;
550 rctx->context.delete_sampler_state = r600_delete_state;
551 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
552 rctx->context.delete_vs_state = r600_delete_state;
553 rctx->context.set_blend_color = r600_set_blend_color;
554 rctx->context.set_clip_state = r600_set_clip_state;
555 rctx->context.set_constant_buffer = r600_set_constant_buffer;
556 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
557 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
558 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
559 rctx->context.set_sample_mask = r600_set_sample_mask;
560 rctx->context.set_scissor_state = r600_set_scissor_state;
561 rctx->context.set_stencil_ref = r600_set_stencil_ref;
562 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
563 rctx->context.set_index_buffer = r600_set_index_buffer;
564 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
565 rctx->context.set_viewport_state = r600_set_viewport_state;
566 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
567 }
568
569 struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate)
570 {
571 if (rstate == NULL)
572 return NULL;
573 rstate->refcount++;
574 return rstate;
575 }
576
577 struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate)
578 {
579 unsigned i;
580
581 if (rstate == NULL)
582 return NULL;
583 if (--rstate->refcount)
584 return NULL;
585 switch (rstate->type) {
586 case pipe_sampler_view_type:
587 pipe_resource_reference(&rstate->state.sampler_view.texture, NULL);
588 break;
589 case pipe_framebuffer_type:
590 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
591 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
592 }
593 pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
594 break;
595 case pipe_viewport_type:
596 case pipe_depth_type:
597 case pipe_rasterizer_type:
598 case pipe_poly_stipple_type:
599 case pipe_scissor_type:
600 case pipe_clip_type:
601 case pipe_stencil_type:
602 case pipe_alpha_type:
603 case pipe_dsa_type:
604 case pipe_blend_type:
605 case pipe_stencil_ref_type:
606 case pipe_shader_type:
607 case pipe_sampler_type:
608 break;
609 default:
610 R600_ERR("invalid type %d\n", rstate->type);
611 return NULL;
612 }
613 radeon_state_fini(&rstate->rstate[0]);
614 FREE(rstate);
615 return NULL;
616 }
617
618 struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state)
619 {
620 struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
621 const union pipe_states *states = state;
622 unsigned i;
623 int r;
624
625 if (rstate == NULL)
626 return NULL;
627 rstate->type = type;
628 rstate->refcount = 1;
629
630 switch (rstate->type) {
631 case pipe_sampler_view_type:
632 rstate->state.sampler_view = (*states).sampler_view;
633 rstate->state.sampler_view.texture = NULL;
634 break;
635 case pipe_framebuffer_type:
636 rstate->state.framebuffer = (*states).framebuffer;
637 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
638 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i],
639 (*states).framebuffer.cbufs[i]);
640 }
641 pipe_surface_reference(&rstate->state.framebuffer.zsbuf,
642 (*states).framebuffer.zsbuf);
643 break;
644 case pipe_viewport_type:
645 rstate->state.viewport = (*states).viewport;
646 r600_viewport(rctx, &rstate->rstate[0], &rstate->state.viewport);
647 break;
648 case pipe_depth_type:
649 rstate->state.depth = (*states).depth;
650 break;
651 case pipe_rasterizer_type:
652 rstate->state.rasterizer = (*states).rasterizer;
653 break;
654 case pipe_poly_stipple_type:
655 rstate->state.poly_stipple = (*states).poly_stipple;
656 break;
657 case pipe_scissor_type:
658 rstate->state.scissor = (*states).scissor;
659 break;
660 case pipe_clip_type:
661 rstate->state.clip = (*states).clip;
662 r600_ucp(rctx, &rstate->rstate[0], &rstate->state.clip);
663 break;
664 case pipe_stencil_type:
665 rstate->state.stencil = (*states).stencil;
666 break;
667 case pipe_alpha_type:
668 rstate->state.alpha = (*states).alpha;
669 break;
670 case pipe_dsa_type:
671 rstate->state.dsa = (*states).dsa;
672 break;
673 case pipe_blend_type:
674 rstate->state.blend = (*states).blend;
675 r600_blend(rctx, &rstate->rstate[0], &rstate->state.blend);
676 break;
677 case pipe_stencil_ref_type:
678 rstate->state.stencil_ref = (*states).stencil_ref;
679 break;
680 case pipe_shader_type:
681 rstate->state.shader = (*states).shader;
682 r = r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
683 if (r) {
684 r600_context_state_decref(rstate);
685 return NULL;
686 }
687 break;
688 case pipe_sampler_type:
689 rstate->state.sampler = (*states).sampler;
690 r600_sampler(rctx, &rstate->rstate[0], &rstate->state.sampler, 0);
691 break;
692 default:
693 R600_ERR("invalid type %d\n", rstate->type);
694 FREE(rstate);
695 return NULL;
696 }
697 return rstate;
698 }
699
700 static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
701 {
702 struct r600_screen *rscreen = rctx->screen;
703 int i;
704
705 radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
706 rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
707 rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
708 rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
709 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
710 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
711 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
712 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
713 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
714 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
715 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
716 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
717 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
718 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
719
720 for (i = 0; i < 8; i++) {
721 unsigned eqRGB = state->rt[i].rgb_func;
722 unsigned srcRGB = state->rt[i].rgb_src_factor;
723 unsigned dstRGB = state->rt[i].rgb_dst_factor;
724
725 unsigned eqA = state->rt[i].alpha_func;
726 unsigned srcA = state->rt[i].alpha_src_factor;
727 unsigned dstA = state->rt[i].alpha_dst_factor;
728 uint32_t bc = 0;
729
730 if (!state->rt[i].blend_enable)
731 continue;
732
733 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
734 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
735 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
736
737 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
738 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
739 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
740 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
741 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
742 }
743
744 rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
745 if (i == 0)
746 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
747 }
748
749 radeon_state_pm4(rstate);
750 }
751
752 static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate,
753 const struct pipe_clip_state *state)
754 {
755 struct r600_screen *rscreen = rctx->screen;
756
757 radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
758
759 for (int i = 0; i < state->nr; i++) {
760 rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
761 rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
762 rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
763 rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
764 }
765 radeon_state_pm4(rstate);
766 }
767
768 static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
769 const struct pipe_framebuffer_state *state, int cb)
770 {
771 struct r600_screen *rscreen = rctx->screen;
772 struct r600_resource_texture *rtex;
773 struct r600_resource *rbuffer;
774 unsigned level = state->cbufs[cb]->level;
775 unsigned pitch, slice;
776 unsigned color_info;
777 unsigned format, swap, ntype;
778 const struct util_format_description *desc;
779
780 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
781 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
782 rbuffer = &rtex->resource;
783 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
784 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
785 rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
786 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
787 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
788 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
789 rstate->nbo = 3;
790 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
791 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
792
793 ntype = 0;
794 desc = util_format_description(rtex->resource.base.b.format);
795 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
796 ntype = V_0280A0_NUMBER_SRGB;
797
798 format = r600_translate_colorformat(rtex->resource.base.b.format);
799 swap = r600_translate_colorswap(rtex->resource.base.b.format);
800
801 color_info = S_0280A0_FORMAT(format) |
802 S_0280A0_COMP_SWAP(swap) |
803 S_0280A0_BLEND_CLAMP(1) |
804 S_0280A0_SOURCE_FORMAT(1) |
805 S_0280A0_NUMBER_TYPE(ntype);
806
807 rstate->states[R600_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
808 rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
809 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
810 S_028060_SLICE_TILE_MAX(slice);
811 rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
812 rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
813 rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
814 rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
815 radeon_state_pm4(rstate);
816 }
817
818 static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
819 const struct pipe_framebuffer_state *state)
820 {
821 struct r600_screen *rscreen = rctx->screen;
822 struct r600_resource_texture *rtex;
823 struct r600_resource *rbuffer;
824 unsigned level;
825 unsigned pitch, slice, format;
826
827 radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
828 if (state->zsbuf == NULL)
829 return;
830
831 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
832 rtex->tilled = 1;
833 rtex->array_mode = 2;
834 rtex->tile_type = 1;
835 rtex->depth = 1;
836 rbuffer = &rtex->resource;
837
838 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
839 rstate->nbo = 1;
840 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
841 level = state->zsbuf->level;
842 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
843 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
844 format = r600_translate_dbformat(state->zsbuf->texture->format);
845 rstate->states[R600_DB__DB_DEPTH_BASE] = state->zsbuf->offset >> 8;
846 rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) |
847 S_028010_FORMAT(format);
848 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
849 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
850 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
851 S_028000_SLICE_TILE_MAX(slice);
852 radeon_state_pm4(rstate);
853 }
854
855 static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
856 {
857 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
858 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
859 const struct pipe_clip_state *clip = NULL;
860 struct r600_screen *rscreen = rctx->screen;
861 float offset_units = 0, offset_scale = 0;
862 char depth = 0;
863 unsigned offset_db_fmt_cntl = 0;
864 unsigned tmp;
865 unsigned prov_vtx = 1;
866
867 if (rctx->clip)
868 clip = &rctx->clip->state.clip;
869 if (fb->zsbuf) {
870 offset_units = state->offset_units;
871 offset_scale = state->offset_scale * 12.0f;
872 switch (fb->zsbuf->texture->format) {
873 case PIPE_FORMAT_Z24X8_UNORM:
874 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
875 depth = -24;
876 offset_units *= 2.0f;
877 break;
878 case PIPE_FORMAT_Z32_FLOAT:
879 depth = -23;
880 offset_units *= 1.0f;
881 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
882 break;
883 case PIPE_FORMAT_Z16_UNORM:
884 depth = -16;
885 offset_units *= 4.0f;
886 break;
887 default:
888 R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
889 return;
890 }
891 }
892 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
893
894 if (state->flatshade_first)
895 prov_vtx = 0;
896
897 rctx->flat_shade = state->flatshade;
898 radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
899 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
900 if (state->sprite_coord_enable) {
901 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
902 S_0286D4_PNT_SPRITE_ENA(1) |
903 S_0286D4_PNT_SPRITE_OVRD_X(2) |
904 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
905 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
906 S_0286D4_PNT_SPRITE_OVRD_W(1);
907 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
908 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
909 S_0286D4_PNT_SPRITE_TOP_1(1);
910 }
911 }
912 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
913 if (clip) {
914 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
915 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
916 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
917 }
918 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] =
919 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
920 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
921 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
922 S_028814_FACE(!state->front_ccw) |
923 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
924 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
925 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
926 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] =
927 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
928 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
929 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
930 /* point size 12.4 fixed point */
931 tmp = (unsigned)(state->point_size * 8.0);
932 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
933 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
934 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
935 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
936 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
937 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
938 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
939 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
940 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
941 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
942 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
943 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
944 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
945 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
946 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
947 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
948 radeon_state_pm4(rstate);
949 }
950
951 static void r600_scissor(struct r600_context *rctx, struct radeon_state *rstate)
952 {
953 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
954 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
955 struct r600_screen *rscreen = rctx->screen;
956 unsigned minx, maxx, miny, maxy;
957 u32 tl, br;
958
959 if (state == NULL) {
960 minx = 0;
961 miny = 0;
962 maxx = fb->cbufs[0]->width;
963 maxy = fb->cbufs[0]->height;
964 } else {
965 minx = state->minx;
966 miny = state->miny;
967 maxx = state->maxx;
968 maxy = state->maxy;
969 }
970 tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
971 br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
972 radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
973 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
974 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
975 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
976 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
977 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
978 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
979 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
980 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
981 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
982 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
983 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
984 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
985 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
986 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
987 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
988 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
989 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
990 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
991 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
992 radeon_state_pm4(rstate);
993 }
994
995 static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
996 {
997 struct r600_screen *rscreen = rctx->screen;
998
999 radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
1000 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
1001 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
1002 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
1003 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
1004 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
1005 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
1006 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
1007 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
1008 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
1009 radeon_state_pm4(rstate);
1010 }
1011
1012 static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
1013 {
1014 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
1015 const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
1016 struct r600_screen *rscreen = rctx->screen;
1017 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
1018 unsigned stencil_ref_mask, stencil_ref_mask_bf;
1019 struct r600_shader *rshader;
1020 int i;
1021
1022 if (rctx->ps_shader == NULL) {
1023 return;
1024 }
1025 radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
1026
1027 db_shader_control = 0x210;
1028 rshader = &rctx->ps_shader->shader;
1029 if (rshader->uses_kill)
1030 db_shader_control |= (1 << 6);
1031 for (i = 0; i < rshader->noutput; i++) {
1032 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1033 db_shader_control |= 1;
1034 }
1035 stencil_ref_mask = 0;
1036 stencil_ref_mask_bf = 0;
1037 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1038 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1039 S_028800_ZFUNC(state->depth.func);
1040 /* set stencil enable */
1041
1042 if (state->stencil[0].enabled) {
1043 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1044 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
1045 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
1046 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
1047 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
1048
1049 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
1050 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
1051 stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
1052 if (state->stencil[1].enabled) {
1053 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1054 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
1055 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
1056 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
1057 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
1058 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
1059 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
1060 stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
1061 }
1062 }
1063
1064 alpha_test_control = 0;
1065 alpha_ref = 0;
1066 if (state->alpha.enabled) {
1067 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
1068 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
1069 alpha_ref = fui(state->alpha.ref_value);
1070 }
1071
1072 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
1073 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
1074 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
1075 rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
1076 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
1077 rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
1078 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
1079 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
1080 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
1081 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
1082 rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control;
1083 rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
1084 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
1085 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
1086 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
1087 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
1088 radeon_state_pm4(rstate);
1089 }
1090
1091 static inline unsigned r600_tex_wrap(unsigned wrap)
1092 {
1093 switch (wrap) {
1094 default:
1095 case PIPE_TEX_WRAP_REPEAT:
1096 return V_03C000_SQ_TEX_WRAP;
1097 case PIPE_TEX_WRAP_CLAMP:
1098 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1099 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1100 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1101 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1102 return V_03C000_SQ_TEX_CLAMP_BORDER;
1103 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1104 return V_03C000_SQ_TEX_MIRROR;
1105 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1106 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1107 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1108 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1109 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1110 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1111 }
1112 }
1113
1114 static inline unsigned r600_tex_filter(unsigned filter)
1115 {
1116 switch (filter) {
1117 default:
1118 case PIPE_TEX_FILTER_NEAREST:
1119 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1120 case PIPE_TEX_FILTER_LINEAR:
1121 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1122 }
1123 }
1124
1125 static inline unsigned r600_tex_mipfilter(unsigned filter)
1126 {
1127 switch (filter) {
1128 case PIPE_TEX_MIPFILTER_NEAREST:
1129 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1130 case PIPE_TEX_MIPFILTER_LINEAR:
1131 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1132 default:
1133 case PIPE_TEX_MIPFILTER_NONE:
1134 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1135 }
1136 }
1137
1138 static inline unsigned r600_tex_compare(unsigned compare)
1139 {
1140 switch (compare) {
1141 default:
1142 case PIPE_FUNC_NEVER:
1143 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1144 case PIPE_FUNC_LESS:
1145 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1146 case PIPE_FUNC_EQUAL:
1147 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1148 case PIPE_FUNC_LEQUAL:
1149 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1150 case PIPE_FUNC_GREATER:
1151 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1152 case PIPE_FUNC_NOTEQUAL:
1153 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1154 case PIPE_FUNC_GEQUAL:
1155 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1156 case PIPE_FUNC_ALWAYS:
1157 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1158 }
1159 }
1160
1161 static INLINE u32 S_FIXED(float value, u32 frac_bits)
1162 {
1163 return value * (1 << frac_bits);
1164 }
1165
1166 static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate,
1167 const struct pipe_sampler_state *state, unsigned id)
1168 {
1169 struct r600_screen *rscreen = rctx->screen;
1170
1171 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
1172 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
1173 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1174 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1175 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1176 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
1177 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
1178 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1179 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func));
1180 /* FIXME LOD it depends on texture base level ... */
1181 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
1182 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1183 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1184 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
1185 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
1186 radeon_state_pm4(rstate);
1187 }
1188
1189 static inline unsigned r600_tex_swizzle(unsigned swizzle)
1190 {
1191 switch (swizzle) {
1192 case PIPE_SWIZZLE_RED:
1193 return V_038010_SQ_SEL_X;
1194 case PIPE_SWIZZLE_GREEN:
1195 return V_038010_SQ_SEL_Y;
1196 case PIPE_SWIZZLE_BLUE:
1197 return V_038010_SQ_SEL_Z;
1198 case PIPE_SWIZZLE_ALPHA:
1199 return V_038010_SQ_SEL_W;
1200 case PIPE_SWIZZLE_ZERO:
1201 return V_038010_SQ_SEL_0;
1202 default:
1203 case PIPE_SWIZZLE_ONE:
1204 return V_038010_SQ_SEL_1;
1205 }
1206 }
1207
1208 static inline unsigned r600_format_type(unsigned format_type)
1209 {
1210 switch (format_type) {
1211 default:
1212 case UTIL_FORMAT_TYPE_UNSIGNED:
1213 return V_038010_SQ_FORMAT_COMP_UNSIGNED;
1214 case UTIL_FORMAT_TYPE_SIGNED:
1215 return V_038010_SQ_FORMAT_COMP_SIGNED;
1216 case UTIL_FORMAT_TYPE_FIXED:
1217 return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
1218 }
1219 }
1220
1221 static inline unsigned r600_tex_dim(unsigned dim)
1222 {
1223 switch (dim) {
1224 default:
1225 case PIPE_TEXTURE_1D:
1226 return V_038000_SQ_TEX_DIM_1D;
1227 case PIPE_TEXTURE_2D:
1228 case PIPE_TEXTURE_RECT:
1229 return V_038000_SQ_TEX_DIM_2D;
1230 case PIPE_TEXTURE_3D:
1231 return V_038000_SQ_TEX_DIM_3D;
1232 case PIPE_TEXTURE_CUBE:
1233 return V_038000_SQ_TEX_DIM_CUBEMAP;
1234 }
1235 }
1236
1237 static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate,
1238 const struct pipe_sampler_view *view, unsigned id)
1239 {
1240 struct r600_context *rctx = r600_context(ctx);
1241 struct r600_screen *rscreen = rctx->screen;
1242 const struct util_format_description *desc;
1243 struct r600_resource_texture *tmp;
1244 struct r600_resource *rbuffer;
1245 unsigned format;
1246 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1247 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1248 int r;
1249
1250 rstate->cpm4 = 0;
1251 swizzle[0] = view->swizzle_r;
1252 swizzle[1] = view->swizzle_g;
1253 swizzle[2] = view->swizzle_b;
1254 swizzle[3] = view->swizzle_a;
1255 format = r600_translate_texformat(view->texture->format,
1256 swizzle,
1257 &word4, &yuv_format);
1258 if (format == ~0) {
1259 return;
1260 }
1261 desc = util_format_description(view->texture->format);
1262 if (desc == NULL) {
1263 R600_ERR("unknow format %d\n", view->texture->format);
1264 return;
1265 }
1266 radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
1267 tmp = (struct r600_resource_texture*)view->texture;
1268 rbuffer = &tmp->resource;
1269 if (tmp->depth) {
1270 r = r600_texture_from_depth(ctx, tmp, view->first_level);
1271 if (r) {
1272 return;
1273 }
1274 rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
1275 rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
1276 } else {
1277 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1278 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1279 }
1280 rstate->nbo = 2;
1281 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
1282 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
1283 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
1284 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
1285
1286 pitch = (tmp->pitch[0] / tmp->bpt);
1287 pitch = (pitch + 0x7) & ~0x7;
1288
1289 /* FIXME properly handle first level != 0 */
1290 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
1291 S_038000_DIM(r600_tex_dim(view->texture->target)) |
1292 S_038000_TILE_MODE(array_mode) |
1293 S_038000_TILE_TYPE(tile_type) |
1294 S_038000_PITCH((pitch / 8) - 1) |
1295 S_038000_TEX_WIDTH(view->texture->width0 - 1);
1296 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
1297 S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
1298 S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
1299 S_038004_DATA_FORMAT(format);
1300 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
1301 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
1302 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
1303 word4 |
1304 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
1305 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
1306 S_038010_REQUEST_SIZE(1) |
1307 S_038010_BASE_LEVEL(view->first_level);
1308 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
1309 S_038014_LAST_LEVEL(view->last_level) |
1310 S_038014_BASE_ARRAY(0) |
1311 S_038014_LAST_ARRAY(0);
1312 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
1313 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
1314 radeon_state_pm4(rstate);
1315 }
1316
1317 static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
1318 {
1319 struct r600_screen *rscreen = rctx->screen;
1320 const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
1321 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
1322 uint32_t color_control, target_mask, shader_mask;
1323 int i;
1324
1325 target_mask = 0;
1326 shader_mask = 0;
1327 color_control = S_028808_PER_MRT_BLEND(1);
1328
1329 for (i = 0; i < nr_cbufs; i++) {
1330 shader_mask |= 0xf << (i * 4);
1331 }
1332
1333 if (pbs->logicop_enable) {
1334 color_control |= (pbs->logicop_func << 16) | (pbs->logicop_func << 20);
1335 } else {
1336 color_control |= (0xcc << 16);
1337 }
1338
1339 if (pbs->independent_blend_enable) {
1340 for (i = 0; i < nr_cbufs; i++) {
1341 if (pbs->rt[i].blend_enable) {
1342 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1343 }
1344 target_mask |= (pbs->rt[i].colormask << (4 * i));
1345 }
1346 } else {
1347 for (i = 0; i < nr_cbufs; i++) {
1348 if (pbs->rt[0].blend_enable) {
1349 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1350 }
1351 target_mask |= (pbs->rt[0].colormask << (4 * i));
1352 }
1353 }
1354 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
1355 rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
1356 rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
1357 rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
1358 rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
1359 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
1360 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
1361 rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
1362 rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
1363 rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
1364 rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
1365 rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
1366 radeon_state_pm4(rstate);
1367 }
1368
1369 int r600_context_hw_states(struct pipe_context *ctx)
1370 {
1371 struct r600_context *rctx = r600_context(ctx);
1372 unsigned i;
1373
1374 /* build new states */
1375 r600_rasterizer(rctx, &rctx->hw_states.rasterizer);
1376 r600_scissor(rctx, &rctx->hw_states.scissor);
1377 r600_dsa(rctx, &rctx->hw_states.dsa);
1378 r600_cb_cntl(rctx, &rctx->hw_states.cb_cntl);
1379
1380 /* bind states */
1381 radeon_draw_bind(&rctx->draw, &rctx->hw_states.rasterizer);
1382 radeon_draw_bind(&rctx->draw, &rctx->hw_states.scissor);
1383 radeon_draw_bind(&rctx->draw, &rctx->hw_states.dsa);
1384 radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_cntl);
1385
1386 radeon_draw_bind(&rctx->draw, &rctx->config);
1387
1388 if (rctx->viewport) {
1389 radeon_draw_bind(&rctx->draw, &rctx->viewport->rstate[0]);
1390 }
1391 if (rctx->blend) {
1392 radeon_draw_bind(&rctx->draw, &rctx->blend->rstate[0]);
1393 }
1394 if (rctx->clip) {
1395 radeon_draw_bind(&rctx->draw, &rctx->clip->rstate[0]);
1396 }
1397 for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
1398 radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[i+1]);
1399 }
1400 if (rctx->framebuffer->state.framebuffer.zsbuf) {
1401 radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[0]);
1402 }
1403 for (i = 0; i < rctx->ps_nsampler; i++) {
1404 if (rctx->ps_sampler[i]) {
1405 radeon_draw_bind(&rctx->draw, rctx->ps_sampler[i]);
1406 }
1407 }
1408 for (i = 0; i < rctx->ps_nsampler_view; i++) {
1409 if (rctx->ps_sampler_view[i]) {
1410 radeon_draw_bind(&rctx->draw, rctx->ps_sampler_view[i]);
1411 }
1412 }
1413 return 0;
1414 }