projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g,radeonsi: cleanup of hex literals
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
145 {
146 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
147 }
148
149 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
150 {
151 return r600_translate_colorformat(chip, format) != ~0U &&
152 r600_translate_colorswap(format) != ~0U;
153 }
154
155 static bool r600_is_zs_format_supported(enum pipe_format format)
156 {
157 return r600_translate_dbformat(format) != ~0U;
158 }
159
160 boolean r600_is_format_supported(struct pipe_screen *screen,
161 enum pipe_format format,
162 enum pipe_texture_target target,
163 unsigned sample_count,
164 unsigned usage)
165 {
166 struct r600_screen *rscreen = (struct r600_screen*)screen;
167 unsigned retval = 0;
168
169 if (target >= PIPE_MAX_TEXTURE_TYPES) {
170 R600_ERR("r600: unsupported texture type %d\n", target);
171 return FALSE;
172 }
173
174 if (!util_format_is_supported(format, usage))
175 return FALSE;
176
177 if (sample_count > 1) {
178 if (!rscreen->has_msaa)
179 return FALSE;
180
181 /* R11G11B10 is broken on R6xx. */
182 if (rscreen->b.chip_class == R600 &&
183 format == PIPE_FORMAT_R11G11B10_FLOAT)
184 return FALSE;
185
186 /* MSAA integer colorbuffers hang. */
187 if (util_format_is_pure_integer(format) &&
188 !util_format_is_depth_or_stencil(format))
189 return FALSE;
190
191 switch (sample_count) {
192 case 2:
193 case 4:
194 case 8:
195 break;
196 default:
197 return FALSE;
198 }
199 }
200
201 if (usage & PIPE_BIND_SAMPLER_VIEW) {
202 if (target == PIPE_BUFFER) {
203 if (r600_is_vertex_format_supported(format))
204 retval |= PIPE_BIND_SAMPLER_VIEW;
205 } else {
206 if (r600_is_sampler_format_supported(screen, format))
207 retval |= PIPE_BIND_SAMPLER_VIEW;
208 }
209 }
210
211 if ((usage & (PIPE_BIND_RENDER_TARGET |
212 PIPE_BIND_DISPLAY_TARGET |
213 PIPE_BIND_SCANOUT |
214 PIPE_BIND_SHARED |
215 PIPE_BIND_BLENDABLE)) &&
216 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
217 retval |= usage &
218 (PIPE_BIND_RENDER_TARGET |
219 PIPE_BIND_DISPLAY_TARGET |
220 PIPE_BIND_SCANOUT |
221 PIPE_BIND_SHARED);
222 if (!util_format_is_pure_integer(format) &&
223 !util_format_is_depth_or_stencil(format))
224 retval |= usage & PIPE_BIND_BLENDABLE;
225 }
226
227 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
228 r600_is_zs_format_supported(format)) {
229 retval |= PIPE_BIND_DEPTH_STENCIL;
230 }
231
232 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
233 r600_is_vertex_format_supported(format)) {
234 retval |= PIPE_BIND_VERTEX_BUFFER;
235 }
236
237 if (usage & PIPE_BIND_TRANSFER_READ)
238 retval |= PIPE_BIND_TRANSFER_READ;
239 if (usage & PIPE_BIND_TRANSFER_WRITE)
240 retval |= PIPE_BIND_TRANSFER_WRITE;
241
242 return retval == usage;
243 }
244
245 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
246 {
247 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
248 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
249 float offset_units = state->offset_units;
250 float offset_scale = state->offset_scale;
251
252 switch (state->zs_format) {
253 case PIPE_FORMAT_Z24X8_UNORM:
254 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
255 offset_units *= 2.0f;
256 break;
257 case PIPE_FORMAT_Z16_UNORM:
258 offset_units *= 4.0f;
259 break;
260 default:;
261 }
262
263 r600_write_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
264 radeon_emit(cs, fui(offset_scale));
265 radeon_emit(cs, fui(offset_units));
266 radeon_emit(cs, fui(offset_scale));
267 radeon_emit(cs, fui(offset_units));
268 }
269
270 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
271 {
272 int j = state->independent_blend_enable ? i : 0;
273
274 unsigned eqRGB = state->rt[j].rgb_func;
275 unsigned srcRGB = state->rt[j].rgb_src_factor;
276 unsigned dstRGB = state->rt[j].rgb_dst_factor;
277
278 unsigned eqA = state->rt[j].alpha_func;
279 unsigned srcA = state->rt[j].alpha_src_factor;
280 unsigned dstA = state->rt[j].alpha_dst_factor;
281 uint32_t bc = 0;
282
283 if (!state->rt[j].blend_enable)
284 return 0;
285
286 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
287 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
288 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
289
290 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
291 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
292 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
293 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
294 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
295 }
296 return bc;
297 }
298
299 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
300 const struct pipe_blend_state *state,
301 int mode)
302 {
303 struct r600_context *rctx = (struct r600_context *)ctx;
304 uint32_t color_control = 0, target_mask = 0;
305 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
306
307 if (!blend) {
308 return NULL;
309 }
310
311 r600_init_command_buffer(&blend->buffer, 20);
312 r600_init_command_buffer(&blend->buffer_no_blend, 20);
313
314 /* R600 does not support per-MRT blends */
315 if (rctx->b.family > CHIP_R600)
316 color_control |= S_028808_PER_MRT_BLEND(1);
317
318 if (state->logicop_enable) {
319 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
320 } else {
321 color_control |= (0xcc << 16);
322 }
323 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
324 if (state->independent_blend_enable) {
325 for (int i = 0; i < 8; i++) {
326 if (state->rt[i].blend_enable) {
327 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
328 }
329 target_mask |= (state->rt[i].colormask << (4 * i));
330 }
331 } else {
332 for (int i = 0; i < 8; i++) {
333 if (state->rt[0].blend_enable) {
334 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
335 }
336 target_mask |= (state->rt[0].colormask << (4 * i));
337 }
338 }
339
340 if (target_mask)
341 color_control |= S_028808_SPECIAL_OP(mode);
342 else
343 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
344
345 /* only MRT0 has dual src blend */
346 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
347 blend->cb_target_mask = target_mask;
348 blend->cb_color_control = color_control;
349 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
350 blend->alpha_to_one = state->alpha_to_one;
351
352 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
353 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
354 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
355 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
356 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
357 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
358
359 /* Copy over the registers set so far into buffer_no_blend. */
360 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
361 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
362
363 /* Only add blend registers if blending is enabled. */
364 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
365 return blend;
366 }
367
368 /* The first R600 does not support per-MRT blends */
369 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
370 r600_get_blend_control(state, 0));
371
372 if (rctx->b.family > CHIP_R600) {
373 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
374 for (int i = 0; i < 8; i++) {
375 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
376 }
377 }
378 return blend;
379 }
380
381 static void *r600_create_blend_state(struct pipe_context *ctx,
382 const struct pipe_blend_state *state)
383 {
384 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
385 }
386
387 static void *r600_create_dsa_state(struct pipe_context *ctx,
388 const struct pipe_depth_stencil_alpha_state *state)
389 {
390 unsigned db_depth_control, alpha_test_control, alpha_ref;
391 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
392
393 if (dsa == NULL) {
394 return NULL;
395 }
396
397 r600_init_command_buffer(&dsa->buffer, 3);
398
399 dsa->valuemask[0] = state->stencil[0].valuemask;
400 dsa->valuemask[1] = state->stencil[1].valuemask;
401 dsa->writemask[0] = state->stencil[0].writemask;
402 dsa->writemask[1] = state->stencil[1].writemask;
403 dsa->zwritemask = state->depth.writemask;
404
405 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
406 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
407 S_028800_ZFUNC(state->depth.func);
408
409 /* stencil */
410 if (state->stencil[0].enabled) {
411 db_depth_control |= S_028800_STENCIL_ENABLE(1);
412 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
413 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
414 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
415 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
416
417 if (state->stencil[1].enabled) {
418 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
419 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
420 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
421 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
422 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
423 }
424 }
425
426 /* alpha */
427 alpha_test_control = 0;
428 alpha_ref = 0;
429 if (state->alpha.enabled) {
430 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
431 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
432 alpha_ref = fui(state->alpha.ref_value);
433 }
434 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
435 dsa->alpha_ref = alpha_ref;
436
437 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
438 return dsa;
439 }
440
441 static void *r600_create_rs_state(struct pipe_context *ctx,
442 const struct pipe_rasterizer_state *state)
443 {
444 struct r600_context *rctx = (struct r600_context *)ctx;
445 unsigned tmp, sc_mode_cntl, spi_interp;
446 float psize_min, psize_max;
447 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
448
449 if (rs == NULL) {
450 return NULL;
451 }
452
453 r600_init_command_buffer(&rs->buffer, 30);
454
455 rs->flatshade = state->flatshade;
456 rs->sprite_coord_enable = state->sprite_coord_enable;
457 rs->two_side = state->light_twoside;
458 rs->clip_plane_enable = state->clip_plane_enable;
459 rs->pa_sc_line_stipple = state->line_stipple_enable ?
460 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
461 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
462 rs->pa_cl_clip_cntl =
463 S_028810_PS_UCP_MODE(3) |
464 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
465 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
466 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
467 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
468 if (rctx->b.chip_class == R700) {
469 rs->pa_cl_clip_cntl |=
470 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
471 }
472 rs->multisample_enable = state->multisample;
473
474 /* offset */
475 rs->offset_units = state->offset_units;
476 rs->offset_scale = state->offset_scale * 12.0f;
477 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
478
479 if (state->point_size_per_vertex) {
480 psize_min = util_get_min_point_size(state);
481 psize_max = 8192;
482 } else {
483 /* Force the point size to be as if the vertex output was disabled. */
484 psize_min = state->point_size;
485 psize_max = state->point_size;
486 }
487
488 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
489 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
490 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
491 S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1);
492 if (rctx->b.family == CHIP_RV770) {
493 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */
494 sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1);
495 }
496 if (rctx->b.chip_class >= R700) {
497 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
498 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
499 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
500 } else {
501 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
502 rs->scissor_enable = state->scissor;
503 }
504
505 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
506 if (state->sprite_coord_enable) {
507 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
508 S_0286D4_PNT_SPRITE_OVRD_X(2) |
509 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
510 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
511 S_0286D4_PNT_SPRITE_OVRD_W(1);
512 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
513 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
514 }
515 }
516
517 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
518 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
519 tmp = r600_pack_float_12p4(state->point_size/2);
520 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
521 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
522 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
523 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
524 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
525 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
526 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
527
528 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
529 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
530 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
531 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
532 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
533 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
534
535 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
536 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
537 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
538 S_028814_FACE(!state->front_ccw) |
539 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
540 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
541 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
542 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
543 state->fill_back != PIPE_POLYGON_MODE_FILL) |
544 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
545 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
546 if (rctx->b.chip_class == R700) {
547 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
548 }
549 if (rctx->b.chip_class == R600) {
550 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
551 S_028350_MULTIPASS(state->rasterizer_discard));
552 }
553 return rs;
554 }
555
556 static void *r600_create_sampler_state(struct pipe_context *ctx,
557 const struct pipe_sampler_state *state)
558 {
559 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
560 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
561
562 if (ss == NULL) {
563 return NULL;
564 }
565
566 ss->seamless_cube_map = state->seamless_cube_map;
567 ss->border_color_use = sampler_state_needs_border_color(state);
568
569 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
570 ss->tex_sampler_words[0] =
571 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
572 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
573 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
574 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
575 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
576 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
577 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
578 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
579 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
580 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
581 ss->tex_sampler_words[1] =
582 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
583 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
584 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
585 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
586 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
587
588 if (ss->border_color_use) {
589 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
590 }
591 return ss;
592 }
593
594 static struct pipe_sampler_view *
595 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
596 unsigned width0, unsigned height0)
597
598 {
599 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
600 int stride = util_format_get_blocksize(view->base.format);
601 unsigned format, num_format, format_comp, endian;
602 uint64_t offset = view->base.u.buf.first_element * stride;
603 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
604
605 r600_vertex_data_type(view->base.format,
606 &format, &num_format, &format_comp,
607 &endian);
608
609 view->tex_resource = &tmp->resource;
610 view->skip_mip_address_reloc = true;
611
612 view->tex_resource_words[0] = offset;
613 view->tex_resource_words[1] = size - 1;
614 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) |
615 S_038008_STRIDE(stride) |
616 S_038008_DATA_FORMAT(format) |
617 S_038008_NUM_FORMAT_ALL(num_format) |
618 S_038008_FORMAT_COMP_ALL(format_comp) |
619 S_038008_ENDIAN_SWAP(endian);
620 view->tex_resource_words[3] = 0;
621 /*
622 * in theory dword 4 is for number of elements, for use with resinfo,
623 * but it seems to utterly fail to work, the amd gpu shader analyser
624 * uses a const buffer to store the element sizes for buffer txq
625 */
626 view->tex_resource_words[4] = 0;
627 view->tex_resource_words[5] = 0;
628 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
629 return &view->base;
630 }
631
632 struct pipe_sampler_view *
633 r600_create_sampler_view_custom(struct pipe_context *ctx,
634 struct pipe_resource *texture,
635 const struct pipe_sampler_view *state,
636 unsigned width_first_level, unsigned height_first_level)
637 {
638 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
639 struct r600_texture *tmp = (struct r600_texture*)texture;
640 unsigned format, endian;
641 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
642 unsigned char swizzle[4], array_mode = 0;
643 unsigned width, height, depth, offset_level, last_level;
644
645 if (view == NULL)
646 return NULL;
647
648 /* initialize base object */
649 view->base = *state;
650 view->base.texture = NULL;
651 pipe_reference(NULL, &texture->reference);
652 view->base.texture = texture;
653 view->base.reference.count = 1;
654 view->base.context = ctx;
655
656 if (texture->target == PIPE_BUFFER)
657 return texture_buffer_sampler_view(view, texture->width0, 1);
658
659 swizzle[0] = state->swizzle_r;
660 swizzle[1] = state->swizzle_g;
661 swizzle[2] = state->swizzle_b;
662 swizzle[3] = state->swizzle_a;
663
664 format = r600_translate_texformat(ctx->screen, state->format,
665 swizzle,
666 &word4, &yuv_format);
667 assert(format != ~0);
668 if (format == ~0) {
669 FREE(view);
670 return NULL;
671 }
672
673 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
674 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
675 FREE(view);
676 return NULL;
677 }
678 tmp = tmp->flushed_depth_texture;
679 }
680
681 endian = r600_colorformat_endian_swap(format);
682
683 offset_level = state->u.tex.first_level;
684 last_level = state->u.tex.last_level - offset_level;
685 width = width_first_level;
686 height = height_first_level;
687 depth = u_minify(texture->depth0, offset_level);
688 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
689
690 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
691 height = 1;
692 depth = texture->array_size;
693 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
694 depth = texture->array_size;
695 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
696 depth = texture->array_size / 6;
697 switch (tmp->surface.level[offset_level].mode) {
698 case RADEON_SURF_MODE_LINEAR_ALIGNED:
699 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
700 break;
701 case RADEON_SURF_MODE_1D:
702 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
703 break;
704 case RADEON_SURF_MODE_2D:
705 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
706 break;
707 case RADEON_SURF_MODE_LINEAR:
708 default:
709 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
710 break;
711 }
712
713 view->tex_resource = &tmp->resource;
714 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
715 S_038000_TILE_MODE(array_mode) |
716 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
717 S_038000_PITCH((pitch / 8) - 1) |
718 S_038000_TEX_WIDTH(width - 1));
719 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
720 S_038004_TEX_DEPTH(depth - 1) |
721 S_038004_DATA_FORMAT(format));
722 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
723 if (offset_level >= tmp->surface.last_level) {
724 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
725 } else {
726 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
727 }
728 view->tex_resource_words[4] = (word4 |
729 S_038010_REQUEST_SIZE(1) |
730 S_038010_ENDIAN_SWAP(endian) |
731 S_038010_BASE_LEVEL(0));
732 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
733 S_038014_LAST_ARRAY(state->u.tex.last_layer));
734 if (texture->nr_samples > 1) {
735 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
736 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
737 } else {
738 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
739 }
740 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
741 S_038018_MAX_ANISO(4 /* max 16 samples */));
742 return &view->base;
743 }
744
745 static struct pipe_sampler_view *
746 r600_create_sampler_view(struct pipe_context *ctx,
747 struct pipe_resource *tex,
748 const struct pipe_sampler_view *state)
749 {
750 return r600_create_sampler_view_custom(ctx, tex, state,
751 u_minify(tex->width0, state->u.tex.first_level),
752 u_minify(tex->height0, state->u.tex.first_level));
753 }
754
755 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
756 {
757 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
758 struct pipe_clip_state *state = &rctx->clip_state.state;
759
760 r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
761 radeon_emit_array(cs, (unsigned*)state, 6*4);
762 }
763
764 static void r600_set_polygon_stipple(struct pipe_context *ctx,
765 const struct pipe_poly_stipple *state)
766 {
767 }
768
769 static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
770 {
771 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
772 struct r600_scissor_state *rstate = (struct r600_scissor_state *)atom;
773 struct pipe_scissor_state *state = &rstate->scissor;
774 unsigned offset = rstate->idx * 4 * 2;
775
776 if (rctx->b.chip_class != R600 || rctx->scissor[0].enable) {
777 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
778 radeon_emit(cs, S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
779 S_028240_WINDOW_OFFSET_DISABLE(1));
780 radeon_emit(cs, S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy));
781 } else {
782 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
783 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
784 S_028240_WINDOW_OFFSET_DISABLE(1));
785 radeon_emit(cs, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
786 }
787 }
788
789 static void r600_set_scissor_states(struct pipe_context *ctx,
790 unsigned start_slot,
791 unsigned num_scissors,
792 const struct pipe_scissor_state *state)
793 {
794 struct r600_context *rctx = (struct r600_context *)ctx;
795 int i;
796
797 for (i = start_slot ; i < start_slot + num_scissors; i++) {
798 rctx->scissor[i].scissor = state[i - start_slot];
799 }
800
801 if (rctx->b.chip_class == R600 && !rctx->scissor[0].enable)
802 return;
803
804 for (i = start_slot ; i < start_slot + num_scissors; i++) {
805 rctx->scissor[i].atom.dirty = true;
806 }
807 }
808
809 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
810 unsigned size, unsigned alignment)
811 {
812 struct pipe_resource buffer;
813
814 memset(&buffer, 0, sizeof buffer);
815 buffer.target = PIPE_BUFFER;
816 buffer.format = PIPE_FORMAT_R8_UNORM;
817 buffer.bind = PIPE_BIND_CUSTOM;
818 buffer.usage = PIPE_USAGE_DEFAULT;
819 buffer.flags = 0;
820 buffer.width0 = size;
821 buffer.height0 = 1;
822 buffer.depth0 = 1;
823 buffer.array_size = 1;
824
825 return (struct r600_resource*)
826 r600_buffer_create(&rscreen->b.b, &buffer, alignment);
827 }
828
829 static void r600_init_color_surface(struct r600_context *rctx,
830 struct r600_surface *surf,
831 bool force_cmask_fmask)
832 {
833 struct r600_screen *rscreen = rctx->screen;
834 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
835 unsigned level = surf->base.u.tex.level;
836 unsigned pitch, slice;
837 unsigned color_info;
838 unsigned color_view;
839 unsigned format, swap, ntype, endian;
840 unsigned offset;
841 const struct util_format_description *desc;
842 int i;
843 bool blend_bypass = 0, blend_clamp = 1;
844
845 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
846 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
847 rtex = rtex->flushed_depth_texture;
848 assert(rtex);
849 }
850
851 offset = rtex->surface.level[level].offset;
852 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
853 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
854 offset += rtex->surface.level[level].slice_size *
855 surf->base.u.tex.first_layer;
856 color_view = 0;
857 } else
858 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
859 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
860
861 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
862 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
863 if (slice) {
864 slice = slice - 1;
865 }
866 color_info = 0;
867 switch (rtex->surface.level[level].mode) {
868 case RADEON_SURF_MODE_LINEAR_ALIGNED:
869 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
870 break;
871 case RADEON_SURF_MODE_1D:
872 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
873 break;
874 case RADEON_SURF_MODE_2D:
875 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
876 break;
877 case RADEON_SURF_MODE_LINEAR:
878 default:
879 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
880 break;
881 }
882
883 desc = util_format_description(surf->base.format);
884
885 for (i = 0; i < 4; i++) {
886 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
887 break;
888 }
889 }
890
891 ntype = V_0280A0_NUMBER_UNORM;
892 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
893 ntype = V_0280A0_NUMBER_SRGB;
894 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
895 if (desc->channel[i].normalized)
896 ntype = V_0280A0_NUMBER_SNORM;
897 else if (desc->channel[i].pure_integer)
898 ntype = V_0280A0_NUMBER_SINT;
899 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
900 if (desc->channel[i].normalized)
901 ntype = V_0280A0_NUMBER_UNORM;
902 else if (desc->channel[i].pure_integer)
903 ntype = V_0280A0_NUMBER_UINT;
904 }
905
906 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
907 assert(format != ~0);
908
909 swap = r600_translate_colorswap(surf->base.format);
910 assert(swap != ~0);
911
912 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
913 endian = ENDIAN_NONE;
914 } else {
915 endian = r600_colorformat_endian_swap(format);
916 }
917
918 /* set blend bypass according to docs if SINT/UINT or
919 8/24 COLOR variants */
920 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
921 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
922 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
923 blend_clamp = 0;
924 blend_bypass = 1;
925 }
926
927 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
928
929 color_info |= S_0280A0_FORMAT(format) |
930 S_0280A0_COMP_SWAP(swap) |
931 S_0280A0_BLEND_BYPASS(blend_bypass) |
932 S_0280A0_BLEND_CLAMP(blend_clamp) |
933 S_0280A0_NUMBER_TYPE(ntype) |
934 S_0280A0_ENDIAN(endian);
935
936 /* EXPORT_NORM is an optimzation that can be enabled for better
937 * performance in certain cases
938 */
939 if (rctx->b.chip_class == R600) {
940 /* EXPORT_NORM can be enabled if:
941 * - 11-bit or smaller UNORM/SNORM/SRGB
942 * - BLEND_CLAMP is enabled
943 * - BLEND_FLOAT32 is disabled
944 */
945 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
946 (desc->channel[i].size < 12 &&
947 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
948 ntype != V_0280A0_NUMBER_UINT &&
949 ntype != V_0280A0_NUMBER_SINT) &&
950 G_0280A0_BLEND_CLAMP(color_info) &&
951 !G_0280A0_BLEND_FLOAT32(color_info)) {
952 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
953 surf->export_16bpc = true;
954 }
955 } else {
956 /* EXPORT_NORM can be enabled if:
957 * - 11-bit or smaller UNORM/SNORM/SRGB
958 * - 16-bit or smaller FLOAT
959 */
960 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
961 ((desc->channel[i].size < 12 &&
962 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
963 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
964 (desc->channel[i].size < 17 &&
965 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
966 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
967 surf->export_16bpc = true;
968 }
969 }
970
971 /* These might not always be initialized to zero. */
972 surf->cb_color_base = offset >> 8;
973 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
974 S_028060_SLICE_TILE_MAX(slice);
975 surf->cb_color_fmask = surf->cb_color_base;
976 surf->cb_color_cmask = surf->cb_color_base;
977 surf->cb_color_mask = 0;
978
979 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
980 &rtex->resource.b.b);
981 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
982 &rtex->resource.b.b);
983
984 if (rtex->cmask.size) {
985 surf->cb_color_cmask = rtex->cmask.offset >> 8;
986 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
987
988 if (rtex->fmask.size) {
989 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
990 surf->cb_color_fmask = rtex->fmask.offset >> 8;
991 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
992 } else { /* cmask only */
993 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
994 }
995 } else if (force_cmask_fmask) {
996 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
997 *
998 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
999 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1000 * because it's not an MSAA buffer.
1001 */
1002 struct r600_cmask_info cmask;
1003 struct r600_fmask_info fmask;
1004
1005 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
1006 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
1007
1008 /* CMASK. */
1009 if (!rctx->dummy_cmask ||
1010 rctx->dummy_cmask->buf->size < cmask.size ||
1011 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1012 struct pipe_transfer *transfer;
1013 void *ptr;
1014
1015 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1016 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1017
1018 /* Set the contents to 0xCC. */
1019 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1020 memset(ptr, 0xCC, cmask.size);
1021 pipe_buffer_unmap(&rctx->b.b, transfer);
1022 }
1023 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1024 &rctx->dummy_cmask->b.b);
1025
1026 /* FMASK. */
1027 if (!rctx->dummy_fmask ||
1028 rctx->dummy_fmask->buf->size < fmask.size ||
1029 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1030 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1031 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1032
1033 }
1034 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1035 &rctx->dummy_fmask->b.b);
1036
1037 /* Init the registers. */
1038 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1039 surf->cb_color_cmask = 0;
1040 surf->cb_color_fmask = 0;
1041 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1042 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1043 }
1044
1045 surf->cb_color_info = color_info;
1046 surf->cb_color_view = color_view;
1047 surf->color_initialized = true;
1048 }
1049
1050 static void r600_init_depth_surface(struct r600_context *rctx,
1051 struct r600_surface *surf)
1052 {
1053 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1054 unsigned level, pitch, slice, format, offset, array_mode;
1055
1056 level = surf->base.u.tex.level;
1057 offset = rtex->surface.level[level].offset;
1058 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1059 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1060 if (slice) {
1061 slice = slice - 1;
1062 }
1063 switch (rtex->surface.level[level].mode) {
1064 case RADEON_SURF_MODE_2D:
1065 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1066 break;
1067 case RADEON_SURF_MODE_1D:
1068 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1069 case RADEON_SURF_MODE_LINEAR:
1070 default:
1071 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1072 break;
1073 }
1074
1075 format = r600_translate_dbformat(surf->base.format);
1076 assert(format != ~0);
1077
1078 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1079 surf->db_depth_base = offset >> 8;
1080 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1081 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1082 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1083 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1084
1085 switch (surf->base.format) {
1086 case PIPE_FORMAT_Z24X8_UNORM:
1087 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1088 surf->pa_su_poly_offset_db_fmt_cntl =
1089 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1090 break;
1091 case PIPE_FORMAT_Z32_FLOAT:
1092 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1093 surf->pa_su_poly_offset_db_fmt_cntl =
1094 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1095 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1096 break;
1097 case PIPE_FORMAT_Z16_UNORM:
1098 surf->pa_su_poly_offset_db_fmt_cntl =
1099 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1100 break;
1101 default:;
1102 }
1103
1104 /* use htile only for first level */
1105 if (rtex->htile_buffer && !level) {
1106 surf->db_htile_data_base = 0;
1107 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1108 S_028D24_HTILE_HEIGHT(1) |
1109 S_028D24_FULL_CACHE(1);
1110 /* preload is not working properly on r6xx/r7xx */
1111 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1112 }
1113
1114 surf->depth_initialized = true;
1115 }
1116
1117 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1118 const struct pipe_framebuffer_state *state)
1119 {
1120 struct r600_context *rctx = (struct r600_context *)ctx;
1121 struct r600_surface *surf;
1122 struct r600_texture *rtex;
1123 unsigned i;
1124
1125 if (rctx->framebuffer.state.nr_cbufs) {
1126 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1127 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1128 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1129 }
1130 if (rctx->framebuffer.state.zsbuf) {
1131 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1132 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1133
1134 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1135 if (rctx->b.chip_class >= R700 && rtex->htile_buffer) {
1136 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1137 }
1138 }
1139
1140 /* Set the new state. */
1141 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1142
1143 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1144 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1145 util_format_is_pure_integer(state->cbufs[0]->format);
1146 rctx->framebuffer.compressed_cb_mask = 0;
1147 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1148 state->cbufs[0] && state->cbufs[1] &&
1149 state->cbufs[0]->texture->nr_samples > 1 &&
1150 state->cbufs[1]->texture->nr_samples <= 1;
1151 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1152
1153 /* Colorbuffers. */
1154 for (i = 0; i < state->nr_cbufs; i++) {
1155 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1156 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1157 rctx->framebuffer.is_msaa_resolve &&
1158 i == 1;
1159
1160 surf = (struct r600_surface*)state->cbufs[i];
1161 if (!surf)
1162 continue;
1163
1164 rtex = (struct r600_texture*)surf->base.texture;
1165 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1166
1167 if (!surf->color_initialized || force_cmask_fmask) {
1168 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1169 if (force_cmask_fmask) {
1170 /* re-initialize later without compression */
1171 surf->color_initialized = false;
1172 }
1173 }
1174
1175 if (!surf->export_16bpc) {
1176 rctx->framebuffer.export_16bpc = false;
1177 }
1178
1179 if (rtex->fmask.size && rtex->cmask.size) {
1180 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1181 }
1182 }
1183
1184 /* Update alpha-test state dependencies.
1185 * Alpha-test is done on the first colorbuffer only. */
1186 if (state->nr_cbufs) {
1187 bool alphatest_bypass = false;
1188
1189 surf = (struct r600_surface*)state->cbufs[0];
1190 if (surf) {
1191 alphatest_bypass = surf->alphatest_bypass;
1192 }
1193
1194 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1195 rctx->alphatest_state.bypass = alphatest_bypass;
1196 rctx->alphatest_state.atom.dirty = true;
1197 }
1198 }
1199
1200 /* ZS buffer. */
1201 if (state->zsbuf) {
1202 surf = (struct r600_surface*)state->zsbuf;
1203
1204 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1205
1206 if (!surf->depth_initialized) {
1207 r600_init_depth_surface(rctx, surf);
1208 }
1209
1210 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1211 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1212 rctx->poly_offset_state.atom.dirty = true;
1213 }
1214
1215 if (rctx->db_state.rsurf != surf) {
1216 rctx->db_state.rsurf = surf;
1217 rctx->db_state.atom.dirty = true;
1218 rctx->db_misc_state.atom.dirty = true;
1219 }
1220 } else if (rctx->db_state.rsurf) {
1221 rctx->db_state.rsurf = NULL;
1222 rctx->db_state.atom.dirty = true;
1223 rctx->db_misc_state.atom.dirty = true;
1224 }
1225
1226 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1227 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1228 rctx->cb_misc_state.atom.dirty = true;
1229 }
1230
1231 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1232 rctx->alphatest_state.bypass = false;
1233 rctx->alphatest_state.atom.dirty = true;
1234 }
1235
1236 /* Calculate the CS size. */
1237 rctx->framebuffer.atom.num_dw =
1238 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1239
1240 if (rctx->framebuffer.state.nr_cbufs) {
1241 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1242 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1243 }
1244 if (rctx->framebuffer.state.zsbuf) {
1245 rctx->framebuffer.atom.num_dw += 16;
1246 } else if (rctx->screen->b.info.drm_minor >= 18) {
1247 rctx->framebuffer.atom.num_dw += 3;
1248 }
1249 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1250 rctx->framebuffer.atom.num_dw += 2;
1251 }
1252
1253 rctx->framebuffer.atom.dirty = true;
1254
1255 r600_set_sample_locations_constant_buffer(rctx);
1256 }
1257
1258 static uint32_t sample_locs_2x[] = {
1259 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1260 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1261 };
1262 static unsigned max_dist_2x = 4;
1263
1264 static uint32_t sample_locs_4x[] = {
1265 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1266 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1267 };
1268 static unsigned max_dist_4x = 6;
1269 static uint32_t sample_locs_8x[] = {
1270 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1271 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1272 };
1273 static unsigned max_dist_8x = 7;
1274
1275 static void r600_get_sample_position(struct pipe_context *ctx,
1276 unsigned sample_count,
1277 unsigned sample_index,
1278 float *out_value)
1279 {
1280 int offset, index;
1281 struct {
1282 int idx:4;
1283 } val;
1284 switch (sample_count) {
1285 case 1:
1286 default:
1287 out_value[0] = out_value[1] = 0.5;
1288 break;
1289 case 2:
1290 offset = 4 * (sample_index * 2);
1291 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1292 out_value[0] = (float)(val.idx + 8) / 16.0f;
1293 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1294 out_value[1] = (float)(val.idx + 8) / 16.0f;
1295 break;
1296 case 4:
1297 offset = 4 * (sample_index * 2);
1298 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1299 out_value[0] = (float)(val.idx + 8) / 16.0f;
1300 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1301 out_value[1] = (float)(val.idx + 8) / 16.0f;
1302 break;
1303 case 8:
1304 offset = 4 * (sample_index % 4 * 2);
1305 index = (sample_index / 4);
1306 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1307 out_value[0] = (float)(val.idx + 8) / 16.0f;
1308 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1309 out_value[1] = (float)(val.idx + 8) / 16.0f;
1310 break;
1311 }
1312 }
1313
1314 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1315 {
1316 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1317 unsigned max_dist = 0;
1318
1319 if (rctx->b.family == CHIP_R600) {
1320 switch (nr_samples) {
1321 default:
1322 nr_samples = 0;
1323 break;
1324 case 2:
1325 r600_write_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1326 max_dist = max_dist_2x;
1327 break;
1328 case 4:
1329 r600_write_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1330 max_dist = max_dist_4x;
1331 break;
1332 case 8:
1333 r600_write_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1334 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1335 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1336 max_dist = max_dist_8x;
1337 break;
1338 }
1339 } else {
1340 switch (nr_samples) {
1341 default:
1342 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1343 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1344 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1345 nr_samples = 0;
1346 break;
1347 case 2:
1348 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1349 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1350 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1351 max_dist = max_dist_2x;
1352 break;
1353 case 4:
1354 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1355 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1356 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1357 max_dist = max_dist_4x;
1358 break;
1359 case 8:
1360 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1361 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1362 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1363 max_dist = max_dist_8x;
1364 break;
1365 }
1366 }
1367
1368 if (nr_samples > 1) {
1369 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1370 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1371 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1372 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1373 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1374 } else {
1375 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1376 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1377 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1378 }
1379 }
1380
1381 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1382 {
1383 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1384 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1385 unsigned nr_cbufs = state->nr_cbufs;
1386 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1387 unsigned i, sbu = 0;
1388
1389 /* Colorbuffers. */
1390 r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1391 for (i = 0; i < nr_cbufs; i++) {
1392 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1393 }
1394 /* set CB_COLOR1_INFO for possible dual-src blending */
1395 if (i == 1 && cb[0]) {
1396 radeon_emit(cs, cb[0]->cb_color_info);
1397 i++;
1398 }
1399 for (; i < 8; i++) {
1400 radeon_emit(cs, 0);
1401 }
1402
1403 if (nr_cbufs) {
1404 for (i = 0; i < nr_cbufs; i++) {
1405 unsigned reloc;
1406
1407 if (!cb[i])
1408 continue;
1409
1410 /* COLOR_BASE */
1411 r600_write_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1412
1413 reloc = r600_context_bo_reloc(&rctx->b,
1414 &rctx->b.rings.gfx,
1415 (struct r600_resource*)cb[i]->base.texture,
1416 RADEON_USAGE_READWRITE,
1417 cb[i]->base.texture->nr_samples > 1 ?
1418 RADEON_PRIO_COLOR_BUFFER_MSAA :
1419 RADEON_PRIO_COLOR_BUFFER);
1420 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1421 radeon_emit(cs, reloc);
1422
1423 /* FMASK */
1424 r600_write_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1425
1426 reloc = r600_context_bo_reloc(&rctx->b,
1427 &rctx->b.rings.gfx,
1428 cb[i]->cb_buffer_fmask,
1429 RADEON_USAGE_READWRITE,
1430 cb[i]->base.texture->nr_samples > 1 ?
1431 RADEON_PRIO_COLOR_BUFFER_MSAA :
1432 RADEON_PRIO_COLOR_BUFFER);
1433 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1434 radeon_emit(cs, reloc);
1435
1436 /* CMASK */
1437 r600_write_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1438
1439 reloc = r600_context_bo_reloc(&rctx->b,
1440 &rctx->b.rings.gfx,
1441 cb[i]->cb_buffer_cmask,
1442 RADEON_USAGE_READWRITE,
1443 cb[i]->base.texture->nr_samples > 1 ?
1444 RADEON_PRIO_COLOR_BUFFER_MSAA :
1445 RADEON_PRIO_COLOR_BUFFER);
1446 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1447 radeon_emit(cs, reloc);
1448 }
1449
1450 r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1451 for (i = 0; i < nr_cbufs; i++) {
1452 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1453 }
1454
1455 r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1456 for (i = 0; i < nr_cbufs; i++) {
1457 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1458 }
1459
1460 r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1461 for (i = 0; i < nr_cbufs; i++) {
1462 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1463 }
1464
1465 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1466 }
1467
1468 /* SURFACE_BASE_UPDATE */
1469 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1470 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1471 radeon_emit(cs, sbu);
1472 sbu = 0;
1473 }
1474
1475 /* Zbuffer. */
1476 if (state->zsbuf) {
1477 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1478 unsigned reloc = r600_context_bo_reloc(&rctx->b,
1479 &rctx->b.rings.gfx,
1480 (struct r600_resource*)state->zsbuf->texture,
1481 RADEON_USAGE_READWRITE,
1482 surf->base.texture->nr_samples > 1 ?
1483 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1484 RADEON_PRIO_DEPTH_BUFFER);
1485
1486 r600_write_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1487 surf->pa_su_poly_offset_db_fmt_cntl);
1488
1489 r600_write_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1490 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1491 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1492 r600_write_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1493 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1494 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1495
1496 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1497 radeon_emit(cs, reloc);
1498
1499 r600_write_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1500
1501 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1502 } else if (rctx->screen->b.info.drm_minor >= 18) {
1503 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1504 * Older kernels are out of luck. */
1505 r600_write_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1506 }
1507
1508 /* SURFACE_BASE_UPDATE */
1509 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1510 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1511 radeon_emit(cs, sbu);
1512 sbu = 0;
1513 }
1514
1515 /* Framebuffer dimensions. */
1516 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1517 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1518 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1519 radeon_emit(cs, S_028244_BR_X(state->width) |
1520 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1521
1522 if (rctx->framebuffer.is_msaa_resolve) {
1523 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1524 } else {
1525 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1526 * will assure that the alpha-test will work even if there is
1527 * no colorbuffer bound. */
1528 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1529 (1ull << MAX2(nr_cbufs, 1)) - 1);
1530 }
1531
1532 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1533 }
1534
1535 static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1536 {
1537 struct r600_context *rctx = (struct r600_context *)ctx;
1538
1539 if (rctx->ps_iter_samples == min_samples)
1540 return;
1541
1542 rctx->ps_iter_samples = min_samples;
1543 if (rctx->framebuffer.nr_samples > 1) {
1544 rctx->rasterizer_state.atom.dirty = true;
1545 if (rctx->b.chip_class == R600)
1546 rctx->db_misc_state.atom.dirty = true;
1547 }
1548 }
1549
1550 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1551 {
1552 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1553 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1554
1555 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1556 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1557 if (rctx->b.chip_class == R600) {
1558 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1559 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1560 } else {
1561 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1562 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1563 }
1564 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1565 } else {
1566 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1567 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1568 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1569
1570 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1571 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1572 /* Always enable the first color output to make sure alpha-test works even without one. */
1573 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1574 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1575 a->cb_color_control |
1576 S_028808_MULTIWRITE_ENABLE(multiwrite));
1577 }
1578 }
1579
1580 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1581 {
1582 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1583 struct r600_db_state *a = (struct r600_db_state*)atom;
1584
1585 if (a->rsurf && a->rsurf->db_htile_surface) {
1586 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1587 unsigned reloc_idx;
1588
1589 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1590 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1591 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1592 reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer,
1593 RADEON_USAGE_READWRITE, RADEON_PRIO_DEPTH_META);
1594 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1595 cs->buf[cs->cdw++] = reloc_idx;
1596 } else {
1597 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1598 }
1599 }
1600
1601 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1602 {
1603 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1604 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1605 unsigned db_render_control = 0;
1606 unsigned db_render_override =
1607 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1608 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1609
1610 if (a->occlusion_query_enabled) {
1611 if (rctx->b.chip_class >= R700) {
1612 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1613 }
1614 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1615 }
1616 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1617 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1618 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1619 /* This is to fix a lockup when hyperz and alpha test are enabled at
1620 * the same time somehow GPU get confuse on which order to pick for
1621 * z test
1622 */
1623 if (rctx->alphatest_state.sx_alpha_test_control) {
1624 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1625 }
1626 } else {
1627 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1628 }
1629 if (rctx->b.chip_class == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) {
1630 /* sample shading and hyperz causes lockups on R6xx chips */
1631 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1632 }
1633 if (a->flush_depthstencil_through_cb) {
1634 assert(a->copy_depth || a->copy_stencil);
1635
1636 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1637 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1638 S_028D0C_COPY_CENTROID(1) |
1639 S_028D0C_COPY_SAMPLE(a->copy_sample);
1640
1641 if (rctx->b.chip_class == R600)
1642 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1643
1644 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
1645 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
1646 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1647 } else if (a->flush_depthstencil_in_place) {
1648 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(1) |
1649 S_028D0C_STENCIL_COMPRESS_DISABLE(1);
1650 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1651 }
1652 if (a->htile_clear) {
1653 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1654 }
1655
1656 /* RV770 workaround for a hang with 8x MSAA. */
1657 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1658 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
1659 }
1660
1661 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1662 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1663 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1664 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1665 }
1666
1667 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1668 {
1669 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1670 struct r600_config_state *a = (struct r600_config_state*)atom;
1671
1672 r600_write_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1673 r600_write_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1674 }
1675
1676 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1677 {
1678 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1679 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1680
1681 while (dirty_mask) {
1682 struct pipe_vertex_buffer *vb;
1683 struct r600_resource *rbuffer;
1684 unsigned offset;
1685 unsigned buffer_index = u_bit_scan(&dirty_mask);
1686
1687 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1688 rbuffer = (struct r600_resource*)vb->buffer;
1689 assert(rbuffer);
1690
1691 offset = vb->buffer_offset;
1692
1693 /* fetch resources start at index 320 */
1694 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1695 radeon_emit(cs, (320 + buffer_index) * 7);
1696 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1697 radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1698 radeon_emit(cs, /* RESOURCEi_WORD2 */
1699 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1700 S_038008_STRIDE(vb->stride));
1701 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1702 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1703 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1704 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1705
1706 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1707 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1708 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1709 }
1710 }
1711
1712 static void r600_emit_constant_buffers(struct r600_context *rctx,
1713 struct r600_constbuf_state *state,
1714 unsigned buffer_id_base,
1715 unsigned reg_alu_constbuf_size,
1716 unsigned reg_alu_const_cache)
1717 {
1718 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1719 uint32_t dirty_mask = state->dirty_mask;
1720
1721 while (dirty_mask) {
1722 struct pipe_constant_buffer *cb;
1723 struct r600_resource *rbuffer;
1724 unsigned offset;
1725 unsigned buffer_index = ffs(dirty_mask) - 1;
1726 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1727 cb = &state->cb[buffer_index];
1728 rbuffer = (struct r600_resource*)cb->buffer;
1729 assert(rbuffer);
1730
1731 offset = cb->buffer_offset;
1732
1733 if (!gs_ring_buffer) {
1734 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1735 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1736 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1737 }
1738
1739 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1740 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1741 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1742
1743 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1744 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1745 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1746 radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1747 radeon_emit(cs, /* RESOURCEi_WORD2 */
1748 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1749 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1750 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1751 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1752 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1753 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1754
1755 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1756 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1757 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1758
1759 dirty_mask &= ~(1 << buffer_index);
1760 }
1761 state->dirty_mask = 0;
1762 }
1763
1764 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1765 {
1766 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
1767 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1768 R_028980_ALU_CONST_CACHE_VS_0);
1769 }
1770
1771 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1772 {
1773 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
1774 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1775 R_0289C0_ALU_CONST_CACHE_GS_0);
1776 }
1777
1778 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1779 {
1780 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
1781 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1782 R_028940_ALU_CONST_CACHE_PS_0);
1783 }
1784
1785 static void r600_emit_sampler_views(struct r600_context *rctx,
1786 struct r600_samplerview_state *state,
1787 unsigned resource_id_base)
1788 {
1789 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1790 uint32_t dirty_mask = state->dirty_mask;
1791
1792 while (dirty_mask) {
1793 struct r600_pipe_sampler_view *rview;
1794 unsigned resource_index = u_bit_scan(&dirty_mask);
1795 unsigned reloc;
1796
1797 rview = state->views[resource_index];
1798 assert(rview);
1799
1800 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1801 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1802 radeon_emit_array(cs, rview->tex_resource_words, 7);
1803
1804 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
1805 RADEON_USAGE_READ,
1806 rview->tex_resource->b.b.nr_samples > 1 ?
1807 RADEON_PRIO_SHADER_TEXTURE_MSAA :
1808 RADEON_PRIO_SHADER_TEXTURE_RO);
1809 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1810 radeon_emit(cs, reloc);
1811 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1812 radeon_emit(cs, reloc);
1813 }
1814 state->dirty_mask = 0;
1815 }
1816
1817 /* Resource IDs:
1818 * PS: 0 .. +160
1819 * VS: 160 .. +160
1820 * FS: 320 .. +16
1821 * GS: 336 .. +160
1822 */
1823
1824 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1825 {
1826 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
1827 }
1828
1829 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1830 {
1831 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
1832 }
1833
1834 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1835 {
1836 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
1837 }
1838
1839 static void r600_emit_sampler_states(struct r600_context *rctx,
1840 struct r600_textures_info *texinfo,
1841 unsigned resource_id_base,
1842 unsigned border_color_reg)
1843 {
1844 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1845 uint32_t dirty_mask = texinfo->states.dirty_mask;
1846
1847 while (dirty_mask) {
1848 struct r600_pipe_sampler_state *rstate;
1849 struct r600_pipe_sampler_view *rview;
1850 unsigned i = u_bit_scan(&dirty_mask);
1851
1852 rstate = texinfo->states.states[i];
1853 assert(rstate);
1854 rview = texinfo->views.views[i];
1855
1856 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1857 * filtering between layers.
1858 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1859 */
1860 if (rview) {
1861 enum pipe_texture_target target = rview->base.texture->target;
1862 if (target == PIPE_TEXTURE_1D_ARRAY ||
1863 target == PIPE_TEXTURE_2D_ARRAY) {
1864 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1865 texinfo->is_array_sampler[i] = true;
1866 } else {
1867 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1868 texinfo->is_array_sampler[i] = false;
1869 }
1870 }
1871
1872 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1873 radeon_emit(cs, (resource_id_base + i) * 3);
1874 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1875
1876 if (rstate->border_color_use) {
1877 unsigned offset;
1878
1879 offset = border_color_reg;
1880 offset += i * 16;
1881 r600_write_config_reg_seq(cs, offset, 4);
1882 radeon_emit_array(cs, rstate->border_color.ui, 4);
1883 }
1884 }
1885 texinfo->states.dirty_mask = 0;
1886 }
1887
1888 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1889 {
1890 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1891 }
1892
1893 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1894 {
1895 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1896 }
1897
1898 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1899 {
1900 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1901 }
1902
1903 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1904 {
1905 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1906 unsigned tmp;
1907
1908 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1909 S_009508_SYNC_GRADIENT(1) |
1910 S_009508_SYNC_WALKER(1) |
1911 S_009508_SYNC_ALIGNER(1);
1912 if (!rctx->seamless_cube_map.enabled) {
1913 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1914 }
1915 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1916 }
1917
1918 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1919 {
1920 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1921 uint8_t mask = s->sample_mask;
1922
1923 r600_write_context_reg(rctx->b.rings.gfx.cs, R_028C48_PA_SC_AA_MASK,
1924 mask | (mask << 8) | (mask << 16) | (mask << 24));
1925 }
1926
1927 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1928 {
1929 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1930 struct r600_cso_state *state = (struct r600_cso_state*)a;
1931 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1932
1933 r600_write_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1934 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1935 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer,
1936 RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
1937 }
1938
1939 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1940 {
1941 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1942 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1943
1944 uint32_t v2 = 0, primid = 0;
1945
1946 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
1947 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1948 primid = 1;
1949 }
1950
1951 if (state->geom_enable) {
1952 uint32_t cut_val;
1953
1954 if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 128)
1955 cut_val = V_028A40_GS_CUT_128;
1956 else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 256)
1957 cut_val = V_028A40_GS_CUT_256;
1958 else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 512)
1959 cut_val = V_028A40_GS_CUT_512;
1960 else
1961 cut_val = V_028A40_GS_CUT_1024;
1962
1963 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1964 S_028A40_CUT_MODE(cut_val);
1965
1966 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1967 primid = 1;
1968 }
1969
1970 r600_write_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1971 r600_write_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
1972 }
1973
1974 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1975 {
1976 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1977 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
1978 struct r600_resource *rbuffer;
1979
1980 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1981 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1982 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1983
1984 if (state->enable) {
1985 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
1986 r600_write_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
1987 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1988 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1989 RADEON_USAGE_READWRITE,
1990 RADEON_PRIO_SHADER_RESOURCE_RW));
1991 r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1992 state->esgs_ring.buffer_size >> 8);
1993
1994 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
1995 r600_write_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
1996 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1997 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1998 RADEON_USAGE_READWRITE,
1999 RADEON_PRIO_SHADER_RESOURCE_RW));
2000 r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2001 state->gsvs_ring.buffer_size >> 8);
2002 } else {
2003 r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2004 r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2005 }
2006
2007 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2008 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2009 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2010 }
2011
2012 /* Adjust GPR allocation on R6xx/R7xx */
2013 bool r600_adjust_gprs(struct r600_context *rctx)
2014 {
2015 unsigned num_ps_gprs = rctx->ps_shader->current->shader.bc.ngpr;
2016 unsigned num_vs_gprs, num_es_gprs, num_gs_gprs;
2017 unsigned new_num_ps_gprs = num_ps_gprs;
2018 unsigned new_num_vs_gprs, new_num_es_gprs, new_num_gs_gprs;
2019 unsigned cur_num_ps_gprs = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2020 unsigned cur_num_vs_gprs = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2021 unsigned cur_num_gs_gprs = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2022 unsigned cur_num_es_gprs = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2023 unsigned def_num_ps_gprs = rctx->default_ps_gprs;
2024 unsigned def_num_vs_gprs = rctx->default_vs_gprs;
2025 unsigned def_num_gs_gprs = 0;
2026 unsigned def_num_es_gprs = 0;
2027 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2028 /* hardware will reserve twice num_clause_temp_gprs */
2029 unsigned max_gprs = def_num_gs_gprs + def_num_es_gprs + def_num_ps_gprs + def_num_vs_gprs + def_num_clause_temp_gprs * 2;
2030 unsigned tmp, tmp2;
2031
2032 if (rctx->gs_shader) {
2033 num_es_gprs = rctx->vs_shader->current->shader.bc.ngpr;
2034 num_gs_gprs = rctx->gs_shader->current->shader.bc.ngpr;
2035 num_vs_gprs = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2036 } else {
2037 num_es_gprs = 0;
2038 num_gs_gprs = 0;
2039 num_vs_gprs = rctx->vs_shader->current->shader.bc.ngpr;
2040 }
2041 new_num_vs_gprs = num_vs_gprs;
2042 new_num_es_gprs = num_es_gprs;
2043 new_num_gs_gprs = num_gs_gprs;
2044
2045 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2046 if (new_num_ps_gprs > cur_num_ps_gprs || new_num_vs_gprs > cur_num_vs_gprs ||
2047 new_num_es_gprs > cur_num_es_gprs || new_num_gs_gprs > cur_num_gs_gprs) {
2048 /* try to use switch back to default */
2049 if (new_num_ps_gprs > def_num_ps_gprs || new_num_vs_gprs > def_num_vs_gprs ||
2050 new_num_gs_gprs > def_num_gs_gprs || new_num_es_gprs > def_num_es_gprs) {
2051 /* always privilege vs stage so that at worst we have the
2052 * pixel stage producing wrong output (not the vertex
2053 * stage) */
2054 new_num_ps_gprs = max_gprs - ((new_num_vs_gprs - new_num_es_gprs - new_num_gs_gprs) + def_num_clause_temp_gprs * 2);
2055 new_num_vs_gprs = num_vs_gprs;
2056 new_num_gs_gprs = num_gs_gprs;
2057 new_num_es_gprs = num_es_gprs;
2058 } else {
2059 new_num_ps_gprs = def_num_ps_gprs;
2060 new_num_vs_gprs = def_num_vs_gprs;
2061 new_num_es_gprs = def_num_es_gprs;
2062 new_num_gs_gprs = def_num_gs_gprs;
2063 }
2064 } else {
2065 return true;
2066 }
2067
2068 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2069 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2070 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2071 * it will lockup. So in this case just discard the draw command
2072 * and don't change the current gprs repartitions.
2073 */
2074 if (num_ps_gprs > new_num_ps_gprs || num_vs_gprs > new_num_vs_gprs ||
2075 num_gs_gprs > new_num_gs_gprs || num_es_gprs > new_num_es_gprs) {
2076 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2077 "for a combined maximum of %d\n",
2078 num_ps_gprs, num_vs_gprs, num_es_gprs, num_gs_gprs, max_gprs);
2079 return false;
2080 }
2081
2082 /* in some case we endup recomputing the current value */
2083 tmp = S_008C04_NUM_PS_GPRS(new_num_ps_gprs) |
2084 S_008C04_NUM_VS_GPRS(new_num_vs_gprs) |
2085 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2086
2087 tmp2 = S_008C08_NUM_ES_GPRS(new_num_es_gprs) |
2088 S_008C08_NUM_GS_GPRS(new_num_gs_gprs);
2089 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2090 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2091 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2092 rctx->config_state.atom.dirty = true;
2093 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2094 }
2095 return true;
2096 }
2097
2098 void r600_init_atom_start_cs(struct r600_context *rctx)
2099 {
2100 int ps_prio;
2101 int vs_prio;
2102 int gs_prio;
2103 int es_prio;
2104 int num_ps_gprs;
2105 int num_vs_gprs;
2106 int num_gs_gprs;
2107 int num_es_gprs;
2108 int num_temp_gprs;
2109 int num_ps_threads;
2110 int num_vs_threads;
2111 int num_gs_threads;
2112 int num_es_threads;
2113 int num_ps_stack_entries;
2114 int num_vs_stack_entries;
2115 int num_gs_stack_entries;
2116 int num_es_stack_entries;
2117 enum radeon_family family;
2118 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2119 uint32_t tmp, i;
2120
2121 r600_init_command_buffer(cb, 256);
2122
2123 /* R6xx requires this packet at the start of each command buffer */
2124 if (rctx->b.chip_class == R600) {
2125 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2126 r600_store_value(cb, 0);
2127 }
2128 /* All asics require this one */
2129 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2130 r600_store_value(cb, 0x80000000);
2131 r600_store_value(cb, 0x80000000);
2132
2133 /* We're setting config registers here. */
2134 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2135 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2136
2137 family = rctx->b.family;
2138 ps_prio = 0;
2139 vs_prio = 1;
2140 gs_prio = 2;
2141 es_prio = 3;
2142 switch (family) {
2143 case CHIP_R600:
2144 num_ps_gprs = 192;
2145 num_vs_gprs = 56;
2146 num_temp_gprs = 4;
2147 num_gs_gprs = 0;
2148 num_es_gprs = 0;
2149 num_ps_threads = 136;
2150 num_vs_threads = 48;
2151 num_gs_threads = 4;
2152 num_es_threads = 4;
2153 num_ps_stack_entries = 128;
2154 num_vs_stack_entries = 128;
2155 num_gs_stack_entries = 0;
2156 num_es_stack_entries = 0;
2157 break;
2158 case CHIP_RV630:
2159 case CHIP_RV635:
2160 num_ps_gprs = 84;
2161 num_vs_gprs = 36;
2162 num_temp_gprs = 4;
2163 num_gs_gprs = 0;
2164 num_es_gprs = 0;
2165 num_ps_threads = 144;
2166 num_vs_threads = 40;
2167 num_gs_threads = 4;
2168 num_es_threads = 4;
2169 num_ps_stack_entries = 40;
2170 num_vs_stack_entries = 40;
2171 num_gs_stack_entries = 32;
2172 num_es_stack_entries = 16;
2173 break;
2174 case CHIP_RV610:
2175 case CHIP_RV620:
2176 case CHIP_RS780:
2177 case CHIP_RS880:
2178 default:
2179 num_ps_gprs = 84;
2180 num_vs_gprs = 36;
2181 num_temp_gprs = 4;
2182 num_gs_gprs = 0;
2183 num_es_gprs = 0;
2184 num_ps_threads = 136;
2185 num_vs_threads = 48;
2186 num_gs_threads = 4;
2187 num_es_threads = 4;
2188 num_ps_stack_entries = 40;
2189 num_vs_stack_entries = 40;
2190 num_gs_stack_entries = 32;
2191 num_es_stack_entries = 16;
2192 break;
2193 case CHIP_RV670:
2194 num_ps_gprs = 144;
2195 num_vs_gprs = 40;
2196 num_temp_gprs = 4;
2197 num_gs_gprs = 0;
2198 num_es_gprs = 0;
2199 num_ps_threads = 136;
2200 num_vs_threads = 48;
2201 num_gs_threads = 4;
2202 num_es_threads = 4;
2203 num_ps_stack_entries = 40;
2204 num_vs_stack_entries = 40;
2205 num_gs_stack_entries = 32;
2206 num_es_stack_entries = 16;
2207 break;
2208 case CHIP_RV770:
2209 num_ps_gprs = 130;
2210 num_vs_gprs = 56;
2211 num_temp_gprs = 4;
2212 num_gs_gprs = 31;
2213 num_es_gprs = 31;
2214 num_ps_threads = 180;
2215 num_vs_threads = 60;
2216 num_gs_threads = 4;
2217 num_es_threads = 4;
2218 num_ps_stack_entries = 128;
2219 num_vs_stack_entries = 128;
2220 num_gs_stack_entries = 128;
2221 num_es_stack_entries = 128;
2222 break;
2223 case CHIP_RV730:
2224 case CHIP_RV740:
2225 num_ps_gprs = 84;
2226 num_vs_gprs = 36;
2227 num_temp_gprs = 4;
2228 num_gs_gprs = 0;
2229 num_es_gprs = 0;
2230 num_ps_threads = 180;
2231 num_vs_threads = 60;
2232 num_gs_threads = 4;
2233 num_es_threads = 4;
2234 num_ps_stack_entries = 128;
2235 num_vs_stack_entries = 128;
2236 num_gs_stack_entries = 0;
2237 num_es_stack_entries = 0;
2238 break;
2239 case CHIP_RV710:
2240 num_ps_gprs = 192;
2241 num_vs_gprs = 56;
2242 num_temp_gprs = 4;
2243 num_gs_gprs = 0;
2244 num_es_gprs = 0;
2245 num_ps_threads = 136;
2246 num_vs_threads = 48;
2247 num_gs_threads = 4;
2248 num_es_threads = 4;
2249 num_ps_stack_entries = 128;
2250 num_vs_stack_entries = 128;
2251 num_gs_stack_entries = 0;
2252 num_es_stack_entries = 0;
2253 break;
2254 }
2255
2256 rctx->default_ps_gprs = num_ps_gprs;
2257 rctx->default_vs_gprs = num_vs_gprs;
2258 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2259
2260 /* SQ_CONFIG */
2261 tmp = 0;
2262 switch (family) {
2263 case CHIP_RV610:
2264 case CHIP_RV620:
2265 case CHIP_RS780:
2266 case CHIP_RS880:
2267 case CHIP_RV710:
2268 break;
2269 default:
2270 tmp |= S_008C00_VC_ENABLE(1);
2271 break;
2272 }
2273 tmp |= S_008C00_DX9_CONSTS(0);
2274 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2275 tmp |= S_008C00_PS_PRIO(ps_prio);
2276 tmp |= S_008C00_VS_PRIO(vs_prio);
2277 tmp |= S_008C00_GS_PRIO(gs_prio);
2278 tmp |= S_008C00_ES_PRIO(es_prio);
2279 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2280
2281 /* SQ_GPR_RESOURCE_MGMT_2 */
2282 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2283 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2284 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2285 r600_store_value(cb, tmp);
2286
2287 /* SQ_THREAD_RESOURCE_MGMT */
2288 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2289 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2290 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2291 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2292 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2293
2294 /* SQ_STACK_RESOURCE_MGMT_1 */
2295 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2296 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2297 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2298
2299 /* SQ_STACK_RESOURCE_MGMT_2 */
2300 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2301 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2302 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2303
2304 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2305
2306 if (rctx->b.chip_class >= R700) {
2307 r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4);
2308 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2309 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2310 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2311 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2312 } else {
2313 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2314 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2315 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2316 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2317 }
2318 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2319 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2320 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2321 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2322 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2323 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2324 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2325 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2326 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2327 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2328
2329 /* to avoid GPU doing any preloading of constant from random address */
2330 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2331 for (i = 0; i < 16; i++)
2332 r600_store_value(cb, 0);
2333
2334 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2335 for (i = 0; i < 16; i++)
2336 r600_store_value(cb, 0);
2337
2338 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2339 for (i = 0; i < 16; i++)
2340 r600_store_value(cb, 0);
2341
2342 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2343 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2344 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2345 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2346 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2347 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2348 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2349 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2350 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2351 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2352 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2353 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2354 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2355 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2356
2357 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2358 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2359 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2360
2361 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2362 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2363 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2364
2365 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2366
2367 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2368
2369 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2370
2371 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2372 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2373 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2374 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2375
2376 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2377 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2378 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2379 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2380
2381 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2382 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2383
2384 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2385 r600_store_value(cb, fui(1.0)); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2386 r600_store_value(cb, fui(1.0)); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2387 r600_store_value(cb, fui(1.0)); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2388 r600_store_value(cb, fui(1.0)); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2389
2390 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * 16);
2391 for (tmp = 0; tmp < 16; tmp++) {
2392 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2393 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2394 }
2395
2396 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2397 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2398
2399 if (rctx->b.chip_class >= R700) {
2400 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2401 }
2402
2403 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2404 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2405 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2406 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2407 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2408
2409 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2410 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2411 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2412
2413 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2414 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2415 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2416
2417 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2418 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2419 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2420 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2421 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2422 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2423
2424 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2425
2426 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2427 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2428 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2429
2430 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2431
2432 if (rctx->b.chip_class == R700)
2433 r600_store_context_reg(cb, R_028350_SX_MISC, 0);
2434 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2435 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2436
2437 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2438 if (rctx->screen->b.has_streamout) {
2439 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2440 }
2441
2442 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2443 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2444 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2445 }
2446
2447 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2448 {
2449 struct r600_context *rctx = (struct r600_context *)ctx;
2450 struct r600_command_buffer *cb = &shader->command_buffer;
2451 struct r600_shader *rshader = &shader->shader;
2452 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2453 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2454 unsigned tmp, sid, ufi = 0;
2455 int need_linear = 0;
2456 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2457 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2458
2459 if (!cb->buf) {
2460 r600_init_command_buffer(cb, 64);
2461 } else {
2462 cb->num_dw = 0;
2463 }
2464
2465 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2466 for (i = 0; i < rshader->ninput; i++) {
2467 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2468 pos_index = i;
2469 if (rshader->input[i].name == TGSI_SEMANTIC_FACE && face_index == -1)
2470 face_index = i;
2471 if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID)
2472 fixed_pt_position_index = i;
2473
2474 sid = rshader->input[i].spi_sid;
2475
2476 tmp = S_028644_SEMANTIC(sid);
2477
2478 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2479 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2480 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2481 rctx->rasterizer && rctx->rasterizer->flatshade))
2482 tmp |= S_028644_FLAT_SHADE(1);
2483
2484 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2485 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2486 tmp |= S_028644_PT_SPRITE_TEX(1);
2487 }
2488
2489 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID)
2490 tmp |= S_028644_SEL_CENTROID(1);
2491
2492 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE)
2493 tmp |= S_028644_SEL_SAMPLE(1);
2494
2495 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2496 need_linear = 1;
2497 tmp |= S_028644_SEL_LINEAR(1);
2498 }
2499
2500 r600_store_value(cb, tmp);
2501 }
2502
2503 db_shader_control = 0;
2504 for (i = 0; i < rshader->noutput; i++) {
2505 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2506 z_export = 1;
2507 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2508 stencil_export = 1;
2509 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
2510 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
2511 mask_export = 1;
2512 }
2513 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2514 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2515 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
2516 if (rshader->uses_kill)
2517 db_shader_control |= S_02880C_KILL_ENABLE(1);
2518
2519 exports_ps = 0;
2520 for (i = 0; i < rshader->noutput; i++) {
2521 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2522 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
2523 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2524 exports_ps |= 1;
2525 }
2526 }
2527 num_cout = rshader->nr_ps_color_exports;
2528 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2529 if (!exports_ps) {
2530 /* always at least export 1 component per pixel */
2531 exports_ps = 2;
2532 }
2533
2534 shader->nr_ps_color_outputs = num_cout;
2535
2536 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2537 S_0286CC_PERSP_GRADIENT_ENA(1)|
2538 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2539 spi_input_z = 0;
2540 if (pos_index != -1) {
2541 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2542 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
2543 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2544 S_0286CC_BARYC_SAMPLE_CNTL(1)) |
2545 S_0286CC_POSITION_SAMPLE(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE);
2546 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2547 }
2548
2549 spi_ps_in_control_1 = 0;
2550 if (face_index != -1) {
2551 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2552 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2553 }
2554 if (fixed_pt_position_index != -1) {
2555 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2556 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
2557 }
2558
2559 /* HW bug in original R600 */
2560 if (rctx->b.family == CHIP_R600)
2561 ufi = 1;
2562
2563 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2564 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2565 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2566
2567 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2568
2569 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2570 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2571 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2572 S_028850_STACK_SIZE(rshader->bc.nstack) |
2573 S_028850_UNCACHED_FIRST_INST(ufi));
2574 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2575
2576 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2577 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2578
2579 /* only set some bits here, the other bits are set in the dsa state */
2580 shader->db_shader_control = db_shader_control;
2581 shader->ps_depth_export = z_export | stencil_export | mask_export;
2582
2583 shader->sprite_coord_enable = sprite_coord_enable;
2584 if (rctx->rasterizer)
2585 shader->flatshade = rctx->rasterizer->flatshade;
2586 }
2587
2588 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2589 {
2590 struct r600_command_buffer *cb = &shader->command_buffer;
2591 struct r600_shader *rshader = &shader->shader;
2592 unsigned spi_vs_out_id[10] = {};
2593 unsigned i, tmp, nparams = 0;
2594
2595 for (i = 0; i < rshader->noutput; i++) {
2596 if (rshader->output[i].spi_sid) {
2597 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2598 spi_vs_out_id[nparams / 4] |= tmp;
2599 nparams++;
2600 }
2601 }
2602
2603 r600_init_command_buffer(cb, 32);
2604
2605 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2606 for (i = 0; i < 10; i++) {
2607 r600_store_value(cb, spi_vs_out_id[i]);
2608 }
2609
2610 /* Certain attributes (position, psize, etc.) don't count as params.
2611 * VS is required to export at least one param and r600_shader_from_tgsi()
2612 * takes care of adding a dummy export.
2613 */
2614 if (nparams < 1)
2615 nparams = 1;
2616
2617 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2618 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2619 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2620 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2621 S_028868_STACK_SIZE(rshader->bc.nstack));
2622 if (rshader->vs_position_window_space) {
2623 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2624 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2625 } else {
2626 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2627 S_028818_VTX_W0_FMT(1) |
2628 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2629 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2630 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2631
2632 }
2633 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2634 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2635
2636 shader->pa_cl_vs_out_cntl =
2637 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2638 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2639 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2640 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2641 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2642 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2643 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2644 }
2645
2646 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2647 {
2648 struct r600_context *rctx = (struct r600_context *)ctx;
2649 struct r600_command_buffer *cb = &shader->command_buffer;
2650 struct r600_shader *rshader = &shader->shader;
2651 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2652 unsigned gsvs_itemsize =
2653 (cp_shader->ring_item_size * rshader->gs_max_out_vertices) >> 2;
2654
2655 r600_init_command_buffer(cb, 64);
2656
2657 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2658 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2659
2660 if (rctx->b.chip_class >= R700) {
2661 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2662 S_028B38_MAX_VERT_OUT(rshader->gs_max_out_vertices));
2663 }
2664 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2665 r600_conv_prim_to_gs_out(rshader->gs_output_prim));
2666
2667 r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE,
2668 cp_shader->ring_item_size >> 2);
2669
2670 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2671 (rshader->ring_item_size) >> 2);
2672
2673 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2674 gsvs_itemsize);
2675
2676 /* FIXME calculate these values somehow ??? */
2677 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2678 r600_store_value(cb, 0x80); /* GS_PER_ES */
2679 r600_store_value(cb, 0x100); /* ES_PER_GS */
2680 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2681 r600_store_value(cb, 0x2); /* GS_PER_VS */
2682
2683 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2684 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2685 S_02887C_STACK_SIZE(rshader->bc.nstack));
2686 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0);
2687 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2688 }
2689
2690 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2691 {
2692 struct r600_command_buffer *cb = &shader->command_buffer;
2693 struct r600_shader *rshader = &shader->shader;
2694
2695 r600_init_command_buffer(cb, 32);
2696
2697 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2698 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2699 S_028890_STACK_SIZE(rshader->bc.nstack));
2700 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0);
2701 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2702 }
2703
2704
2705 void *r600_create_resolve_blend(struct r600_context *rctx)
2706 {
2707 struct pipe_blend_state blend;
2708 unsigned i;
2709
2710 memset(&blend, 0, sizeof(blend));
2711 blend.independent_blend_enable = true;
2712 for (i = 0; i < 2; i++) {
2713 blend.rt[i].colormask = 0xf;
2714 blend.rt[i].blend_enable = 1;
2715 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2716 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2717 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2718 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2719 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2720 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2721 }
2722 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2723 }
2724
2725 void *r700_create_resolve_blend(struct r600_context *rctx)
2726 {
2727 struct pipe_blend_state blend;
2728
2729 memset(&blend, 0, sizeof(blend));
2730 blend.independent_blend_enable = true;
2731 blend.rt[0].colormask = 0xf;
2732 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2733 }
2734
2735 void *r600_create_decompress_blend(struct r600_context *rctx)
2736 {
2737 struct pipe_blend_state blend;
2738
2739 memset(&blend, 0, sizeof(blend));
2740 blend.independent_blend_enable = true;
2741 blend.rt[0].colormask = 0xf;
2742 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2743 }
2744
2745 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2746 {
2747 struct pipe_depth_stencil_alpha_state dsa;
2748 boolean quirk = false;
2749
2750 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2751 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2752 quirk = true;
2753
2754 memset(&dsa, 0, sizeof(dsa));
2755
2756 if (quirk) {
2757 dsa.depth.enabled = 1;
2758 dsa.depth.func = PIPE_FUNC_LEQUAL;
2759 dsa.stencil[0].enabled = 1;
2760 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2761 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2762 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2763 dsa.stencil[0].writemask = 0xff;
2764 }
2765
2766 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2767 }
2768
2769 void r600_update_db_shader_control(struct r600_context * rctx)
2770 {
2771 bool dual_export;
2772 unsigned db_shader_control;
2773
2774 if (!rctx->ps_shader) {
2775 return;
2776 }
2777
2778 dual_export = rctx->framebuffer.export_16bpc &&
2779 !rctx->ps_shader->current->ps_depth_export;
2780
2781 db_shader_control = rctx->ps_shader->current->db_shader_control |
2782 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2783
2784 /* When alpha test is enabled we can't trust the hw to make the proper
2785 * decision on the order in which ztest should be run related to fragment
2786 * shader execution.
2787 *
2788 * If alpha test is enabled perform z test after fragment. RE_Z (early
2789 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2790 */
2791 if (rctx->alphatest_state.sx_alpha_test_control) {
2792 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2793 } else {
2794 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2795 }
2796
2797 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
2798 rctx->db_misc_state.db_shader_control = db_shader_control;
2799 rctx->db_misc_state.atom.dirty = true;
2800 }
2801 }
2802
2803 static INLINE unsigned r600_array_mode(unsigned mode)
2804 {
2805 switch (mode) {
2806 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2807 break;
2808 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2809 break;
2810 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2811 default:
2812 case RADEON_SURF_MODE_LINEAR: return V_0280A0_ARRAY_LINEAR_GENERAL;
2813 }
2814 }
2815
2816 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2817 struct pipe_resource *dst,
2818 unsigned dst_level,
2819 unsigned dst_x,
2820 unsigned dst_y,
2821 unsigned dst_z,
2822 struct pipe_resource *src,
2823 unsigned src_level,
2824 unsigned src_x,
2825 unsigned src_y,
2826 unsigned src_z,
2827 unsigned copy_height,
2828 unsigned pitch,
2829 unsigned bpp)
2830 {
2831 struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
2832 struct r600_texture *rsrc = (struct r600_texture*)src;
2833 struct r600_texture *rdst = (struct r600_texture*)dst;
2834 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2835 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2836 uint64_t base, addr;
2837
2838 dst_mode = rdst->surface.level[dst_level].mode;
2839 src_mode = rsrc->surface.level[src_level].mode;
2840 /* downcast linear aligned to linear to simplify test */
2841 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2842 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2843 assert(dst_mode != src_mode);
2844
2845 y = 0;
2846 lbpp = util_logbase2(bpp);
2847 pitch_tile_max = ((pitch / bpp) / 8) - 1;
2848
2849 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
2850 /* T2L */
2851 array_mode = r600_array_mode(src_mode);
2852 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
2853 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2854 /* linear height must be the same as the slice tile max height, it's ok even
2855 * if the linear destination/source have smaller heigh as the size of the
2856 * dma packet will be using the copy_height which is always smaller or equal
2857 * to the linear height
2858 */
2859 height = rsrc->surface.level[src_level].npix_y;
2860 detile = 1;
2861 x = src_x;
2862 y = src_y;
2863 z = src_z;
2864 base = rsrc->surface.level[src_level].offset;
2865 addr = rdst->surface.level[dst_level].offset;
2866 addr += rdst->surface.level[dst_level].slice_size * dst_z;
2867 addr += dst_y * pitch + dst_x * bpp;
2868 } else {
2869 /* L2T */
2870 array_mode = r600_array_mode(dst_mode);
2871 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
2872 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2873 /* linear height must be the same as the slice tile max height, it's ok even
2874 * if the linear destination/source have smaller heigh as the size of the
2875 * dma packet will be using the copy_height which is always smaller or equal
2876 * to the linear height
2877 */
2878 height = rdst->surface.level[dst_level].npix_y;
2879 detile = 0;
2880 x = dst_x;
2881 y = dst_y;
2882 z = dst_z;
2883 base = rdst->surface.level[dst_level].offset;
2884 addr = rsrc->surface.level[src_level].offset;
2885 addr += rsrc->surface.level[src_level].slice_size * src_z;
2886 addr += src_y * pitch + src_x * bpp;
2887 }
2888 /* check that we are in dw/base alignment constraint */
2889 if (addr % 4 || base % 256) {
2890 return FALSE;
2891 }
2892
2893 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2894 * line in the blit. Compute max 8 line we can copy in the size limit
2895 */
2896 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2897 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2898 r600_need_dma_space(&rctx->b, ncopy * 7);
2899
2900 for (i = 0; i < ncopy; i++) {
2901 cheight = cheight > copy_height ? copy_height : cheight;
2902 size = (cheight * pitch) / 4;
2903 /* emit reloc before writting cs so that cs is always in consistent state */
2904 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ,
2905 RADEON_PRIO_MIN);
2906 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE,
2907 RADEON_PRIO_MIN);
2908 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
2909 cs->buf[cs->cdw++] = base >> 8;
2910 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
2911 (lbpp << 24) | ((height - 1) << 10) |
2912 pitch_tile_max;
2913 cs->buf[cs->cdw++] = (slice_tile_max << 12) | (z << 0);
2914 cs->buf[cs->cdw++] = (x << 3) | (y << 17);
2915 cs->buf[cs->cdw++] = addr & 0xfffffffc;
2916 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
2917 copy_height -= cheight;
2918 addr += cheight * pitch;
2919 y += cheight;
2920 }
2921 return TRUE;
2922 }
2923
2924 static void r600_dma_copy(struct pipe_context *ctx,
2925 struct pipe_resource *dst,
2926 unsigned dst_level,
2927 unsigned dstx, unsigned dsty, unsigned dstz,
2928 struct pipe_resource *src,
2929 unsigned src_level,
2930 const struct pipe_box *src_box)
2931 {
2932 struct r600_context *rctx = (struct r600_context *)ctx;
2933 struct r600_texture *rsrc = (struct r600_texture*)src;
2934 struct r600_texture *rdst = (struct r600_texture*)dst;
2935 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2936 unsigned src_w, dst_w;
2937 unsigned src_x, src_y;
2938 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
2939
2940 if (rctx->b.rings.dma.cs == NULL) {
2941 goto fallback;
2942 }
2943
2944 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
2945 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
2946 goto fallback;
2947
2948 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
2949 return;
2950 }
2951
2952 if (src->format != dst->format || src_box->depth > 1) {
2953 goto fallback;
2954 }
2955
2956 src_x = util_format_get_nblocksx(src->format, src_box->x);
2957 dst_x = util_format_get_nblocksx(src->format, dst_x);
2958 src_y = util_format_get_nblocksy(src->format, src_box->y);
2959 dst_y = util_format_get_nblocksy(src->format, dst_y);
2960
2961 bpp = rdst->surface.bpe;
2962 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
2963 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
2964 src_w = rsrc->surface.level[src_level].npix_x;
2965 dst_w = rdst->surface.level[dst_level].npix_x;
2966 copy_height = src_box->height / rsrc->surface.blk_h;
2967
2968 dst_mode = rdst->surface.level[dst_level].mode;
2969 src_mode = rsrc->surface.level[src_level].mode;
2970 /* downcast linear aligned to linear to simplify test */
2971 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2972 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2973
2974 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
2975 /* strict requirement on r6xx/r7xx */
2976 goto fallback;
2977 }
2978 /* lot of constraint on alignment this should capture them all */
2979 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
2980 goto fallback;
2981 }
2982
2983 if (src_mode == dst_mode) {
2984 uint64_t dst_offset, src_offset, size;
2985
2986 /* simple dma blit would do NOTE code here assume :
2987 * src_box.x/y == 0
2988 * dst_x/y == 0
2989 * dst_pitch == src_pitch
2990 */
2991 src_offset= rsrc->surface.level[src_level].offset;
2992 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
2993 src_offset += src_y * src_pitch + src_x * bpp;
2994 dst_offset = rdst->surface.level[dst_level].offset;
2995 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
2996 dst_offset += dst_y * dst_pitch + dst_x * bpp;
2997 size = src_box->height * src_pitch;
2998 /* must be dw aligned */
2999 if (dst_offset % 4 || src_offset % 4 || size % 4) {
3000 goto fallback;
3001 }
3002 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
3003 } else {
3004 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3005 src, src_level, src_x, src_y, src_box->z,
3006 copy_height, dst_pitch, bpp)) {
3007 goto fallback;
3008 }
3009 }
3010 return;
3011
3012 fallback:
3013 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3014 src, src_level, src_box);
3015 }
3016
3017 void r600_init_state_functions(struct r600_context *rctx)
3018 {
3019 unsigned id = 4;
3020 int i;
3021
3022 /* !!!
3023 * To avoid GPU lockup registers must be emited in a specific order
3024 * (no kidding ...). The order below is important and have been
3025 * partialy infered from analyzing fglrx command stream.
3026 *
3027 * Don't reorder atom without carefully checking the effect (GPU lockup
3028 * or piglit regression).
3029 * !!!
3030 */
3031
3032 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3033
3034 /* shader const */
3035 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3036 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3037 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3038
3039 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3040 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3041 */
3042 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3043 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3044 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3045 /* resource */
3046 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3047 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3048 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3049 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3050
3051 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3052
3053 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3054 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3055 rctx->sample_mask.sample_mask = ~0;
3056
3057 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3058 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3059 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3060 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3061 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3062 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3063 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3064 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3065 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3066 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
3067 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3068 for (i = 0;i < 16; i++) {
3069 r600_init_atom(rctx, &rctx->scissor[i].atom, id++, r600_emit_scissor_state, 4);
3070 r600_init_atom(rctx, &rctx->viewport[i].atom, id++, r600_emit_viewport_state, 8);
3071 rctx->scissor[i].idx = i;
3072 rctx->viewport[i].idx = i;
3073 }
3074 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3075 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3076 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3077 rctx->atoms[id++] = &rctx->b.streamout.begin_atom;
3078 rctx->atoms[id++] = &rctx->b.streamout.enable_atom;
3079 r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader, 23);
3080 r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader, 0);
3081 r600_init_atom(rctx, &rctx->geometry_shader.atom, id++, r600_emit_shader, 0);
3082 r600_init_atom(rctx, &rctx->export_shader.atom, id++, r600_emit_shader, 0);
3083 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3084 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3085
3086 rctx->b.b.create_blend_state = r600_create_blend_state;
3087 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3088 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3089 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3090 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3091 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3092 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3093 rctx->b.b.set_min_samples = r600_set_min_samples;
3094 rctx->b.b.set_scissor_states = r600_set_scissor_states;
3095 rctx->b.b.get_sample_position = r600_get_sample_position;
3096 rctx->b.dma_copy = r600_dma_copy;
3097 }
3098 /* this function must be last */