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2ba15b818aaf460fd7e22d8f362027c10ba41022
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_upload_mgr.h>
40 #include <util/u_framebuffer.h>
41 #include <pipebuffer/pb_buffer.h>
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_state_inlines.h"
48
49 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
50 {
51 struct r600_pipe_state state;
52
53 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
54 state.nregs = 0;
55 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
56 float offset_units = rctx->rasterizer->offset_units;
57 unsigned offset_db_fmt_cntl = 0, depth;
58
59 switch (rctx->framebuffer.zsbuf->texture->format) {
60 case PIPE_FORMAT_Z24X8_UNORM:
61 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
62 depth = -24;
63 offset_units *= 2.0f;
64 break;
65 case PIPE_FORMAT_Z32_FLOAT:
66 depth = -23;
67 offset_units *= 1.0f;
68 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
69 break;
70 case PIPE_FORMAT_Z16_UNORM:
71 depth = -16;
72 offset_units *= 4.0f;
73 break;
74 default:
75 return;
76 }
77 /* FIXME some of those reg can be computed with cso */
78 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
79 r600_pipe_state_add_reg(&state,
80 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
81 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
82 r600_pipe_state_add_reg(&state,
83 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
84 fui(offset_units), 0xFFFFFFFF, NULL);
85 r600_pipe_state_add_reg(&state,
86 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
87 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
88 r600_pipe_state_add_reg(&state,
89 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
90 fui(offset_units), 0xFFFFFFFF, NULL);
91 r600_pipe_state_add_reg(&state,
92 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
93 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
94 r600_context_pipe_state_set(&rctx->ctx, &state);
95 }
96 }
97
98 /* FIXME optimize away spi update when it's not needed */
99 static void r600_spi_update(struct r600_pipe_context *rctx)
100 {
101 struct r600_pipe_shader *shader = rctx->ps_shader;
102 struct r600_pipe_state rstate;
103 struct r600_shader *rshader = &shader->shader;
104 unsigned i, tmp;
105
106 rstate.nregs = 0;
107 for (i = 0; i < rshader->ninput; i++) {
108 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
109 if (rshader->input[i].centroid)
110 tmp |= S_028644_SEL_CENTROID(1);
111 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
112 tmp |= S_028644_SEL_LINEAR(1);
113
114 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
115 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
116 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
117 tmp |= S_028644_FLAT_SHADE(rctx->flatshade);
118 }
119 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
120 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
121 tmp |= S_028644_PT_SPRITE_TEX(1);
122 }
123 r600_pipe_state_add_reg(&rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
124 }
125 r600_context_pipe_state_set(&rctx->ctx, &rstate);
126 }
127
128 void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
129 {
130 struct r600_pipe_state *rstate;
131 struct r600_resource *rbuffer;
132 struct pipe_vertex_buffer *vertex_buffer;
133 unsigned i, offset;
134
135 /* we don't update until we know vertex elements */
136 if (rctx->vertex_elements == NULL || !rctx->nvertex_buffer)
137 return;
138
139 /* delete previous translated vertex elements */
140 if (rctx->tran.new_velems) {
141 r600_end_vertex_translate(rctx);
142 }
143
144 if (rctx->vertex_elements->incompatible_layout) {
145 /* translate rebind new vertex elements so
146 * return once translated
147 */
148 r600_begin_vertex_translate(rctx);
149 return;
150 }
151
152 if (rctx->any_user_vbs) {
153 r600_upload_user_buffers(rctx);
154 rctx->any_user_vbs = FALSE;
155 }
156
157 if (rctx->vertex_elements->vbuffer_need_offset) {
158 /* one resource per vertex elements */
159 rctx->nvs_resource = rctx->vertex_elements->count;
160 } else {
161 /* bind vertex buffer once */
162 rctx->nvs_resource = rctx->nvertex_buffer;
163 }
164
165 for (i = 0 ; i < rctx->nvs_resource; i++) {
166 rstate = &rctx->vs_resource[i];
167 rstate->id = R600_PIPE_STATE_RESOURCE;
168 rstate->nregs = 0;
169
170 if (rctx->vertex_elements->vbuffer_need_offset) {
171 /* one resource per vertex elements */
172 unsigned vbuffer_index;
173 vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
174 vertex_buffer = &rctx->vertex_buffer[vbuffer_index];
175 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
176 offset = rctx->vertex_elements->vbuffer_offset[i] +
177 vertex_buffer->buffer_offset +
178 r600_bo_offset(rbuffer->bo);
179 } else {
180 /* bind vertex buffer once */
181 vertex_buffer = &rctx->vertex_buffer[i];
182 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
183 offset = vertex_buffer->buffer_offset +
184 r600_bo_offset(rbuffer->bo);
185 }
186
187 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
188 offset, 0xFFFFFFFF, rbuffer->bo);
189 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
190 rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
191 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
192 S_038008_STRIDE(vertex_buffer->stride),
193 0xFFFFFFFF, NULL);
194 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
195 0x00000000, 0xFFFFFFFF, NULL);
196 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
197 0x00000000, 0xFFFFFFFF, NULL);
198 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
199 0x00000000, 0xFFFFFFFF, NULL);
200 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
201 0xC0000000, 0xFFFFFFFF, NULL);
202 r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
203 }
204 }
205
206 static void r600_draw_common(struct r600_drawl *draw)
207 {
208 struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
209 struct r600_pipe_state *rstate;
210 struct r600_resource *rbuffer;
211 unsigned i, j, offset, prim;
212 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
213 struct pipe_vertex_buffer *vertex_buffer;
214 struct r600_draw rdraw;
215 struct r600_pipe_state vgt;
216
217 switch (draw->index_size) {
218 case 2:
219 vgt_draw_initiator = 0;
220 vgt_dma_index_type = 0;
221 break;
222 case 4:
223 vgt_draw_initiator = 0;
224 vgt_dma_index_type = 1;
225 break;
226 case 0:
227 vgt_draw_initiator = 2;
228 vgt_dma_index_type = 0;
229 break;
230 default:
231 R600_ERR("unsupported index size %d\n", draw->index_size);
232 return;
233 }
234 if (r600_conv_pipe_prim(draw->mode, &prim))
235 return;
236 if (unlikely(rctx->ps_shader == NULL)) {
237 R600_ERR("missing vertex shader\n");
238 return;
239 }
240 if (unlikely(rctx->vs_shader == NULL)) {
241 R600_ERR("missing vertex shader\n");
242 return;
243 }
244 /* there should be enough input */
245 if (rctx->vertex_elements->count < rctx->vs_shader->shader.bc.nresource) {
246 R600_ERR("%d resources provided, expecting %d\n",
247 rctx->vertex_elements->count, rctx->vs_shader->shader.bc.nresource);
248 return;
249 }
250
251 #if 0
252 /* rebuild vertex shader if input format changed */
253 if (r600_pipe_shader_update(&rctx->context, rctx->vs_shader))
254 return;
255 if (r600_pipe_shader_update(&rctx->context, rctx->ps_shader))
256 return;
257 #endif
258
259 r600_spi_update(rctx);
260
261 #if 0
262 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
263 uint32_t word2, format;
264
265 rstate = &rctx->vs_resource[i];
266 rstate->id = R600_PIPE_STATE_RESOURCE;
267 rstate->nregs = 0;
268
269 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
270 vertex_buffer = &rctx->vertex_buffer[j];
271 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
272 offset = rctx->vertex_elements->elements[i].src_offset +
273 vertex_buffer->buffer_offset +
274 r600_bo_offset(rbuffer->bo);
275
276 format = r600_translate_vertex_data_type(rctx->vertex_elements->hw_format[i]);
277
278 word2 = format | S_038008_STRIDE(vertex_buffer->stride);
279
280 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
281 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
282 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2, word2, 0xFFFFFFFF, NULL);
283 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3, 0x00000000, 0xFFFFFFFF, NULL);
284 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
285 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
286 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6, 0xC0000000, 0xFFFFFFFF, NULL);
287 r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
288 }
289 #endif
290
291 mask = 0;
292 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
293 mask |= (0xF << (i * 4));
294 }
295
296 vgt.id = R600_PIPE_STATE_VGT;
297 vgt.nregs = 0;
298 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
299 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw->index_bias, 0xFFFFFFFF, NULL);
300 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw->max_index, 0xFFFFFFFF, NULL);
301 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw->min_index, 0xFFFFFFFF, NULL);
302 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
303 r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
304 r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
305 r600_context_pipe_state_set(&rctx->ctx, &vgt);
306
307 rdraw.vgt_num_indices = draw->count;
308 rdraw.vgt_num_instances = 1;
309 rdraw.vgt_index_type = vgt_dma_index_type;
310 rdraw.vgt_draw_initiator = vgt_draw_initiator;
311 rdraw.indices = NULL;
312 if (draw->index_buffer) {
313 rbuffer = (struct r600_resource*)draw->index_buffer;
314 rdraw.indices = rbuffer->bo;
315 rdraw.indices_bo_offset = draw->index_buffer_offset;
316 }
317 r600_context_draw(&rctx->ctx, &rdraw);
318 }
319
320 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
321 {
322 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
323 struct r600_drawl draw;
324 boolean translate = FALSE;
325
326 #if 0
327 if (rctx->vertex_elements->incompatible_layout) {
328 r600_begin_vertex_translate(rctx);
329 translate = TRUE;
330 }
331
332 if (rctx->any_user_vbs) {
333 r600_upload_user_buffers(rctx);
334 rctx->any_user_vbs = FALSE;
335 }
336 #endif
337
338 memset(&draw, 0, sizeof(struct r600_drawl));
339 draw.ctx = ctx;
340 draw.mode = info->mode;
341 draw.start = info->start;
342 draw.count = info->count;
343 if (info->indexed && rctx->index_buffer.buffer) {
344 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
345 draw.min_index = info->min_index;
346 draw.max_index = info->max_index;
347 draw.index_bias = info->index_bias;
348
349 r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
350 &rctx->index_buffer.index_size,
351 &draw.start,
352 info->count);
353
354 draw.index_size = rctx->index_buffer.index_size;
355 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
356 draw.index_buffer_offset = draw.start * draw.index_size;
357 draw.start = 0;
358 r600_upload_index_buffer(rctx, &draw);
359 } else {
360 draw.index_size = 0;
361 draw.index_buffer = NULL;
362 draw.min_index = info->min_index;
363 draw.max_index = info->max_index;
364 draw.index_bias = info->start;
365 }
366 r600_draw_common(&draw);
367
368 if (translate)
369 r600_end_vertex_translate(rctx);
370
371 pipe_resource_reference(&draw.index_buffer, NULL);
372 }
373
374 static void r600_set_blend_color(struct pipe_context *ctx,
375 const struct pipe_blend_color *state)
376 {
377 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
378 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
379
380 if (rstate == NULL)
381 return;
382
383 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
384 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
385 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
386 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
387 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
388 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
389 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
390 r600_context_pipe_state_set(&rctx->ctx, rstate);
391 }
392
393 static void *r600_create_blend_state(struct pipe_context *ctx,
394 const struct pipe_blend_state *state)
395 {
396 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
397 struct r600_pipe_state *rstate;
398 u32 color_control, target_mask;
399
400 if (blend == NULL) {
401 return NULL;
402 }
403 rstate = &blend->rstate;
404
405 rstate->id = R600_PIPE_STATE_BLEND;
406
407 target_mask = 0;
408 color_control = S_028808_PER_MRT_BLEND(1);
409 if (state->logicop_enable) {
410 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
411 } else {
412 color_control |= (0xcc << 16);
413 }
414 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
415 if (state->independent_blend_enable) {
416 for (int i = 0; i < 8; i++) {
417 if (state->rt[i].blend_enable) {
418 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
419 }
420 target_mask |= (state->rt[i].colormask << (4 * i));
421 }
422 } else {
423 for (int i = 0; i < 8; i++) {
424 if (state->rt[0].blend_enable) {
425 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
426 }
427 target_mask |= (state->rt[0].colormask << (4 * i));
428 }
429 }
430 blend->cb_target_mask = target_mask;
431 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
432 color_control, 0xFFFFFFFF, NULL);
433
434 for (int i = 0; i < 8; i++) {
435 unsigned eqRGB = state->rt[i].rgb_func;
436 unsigned srcRGB = state->rt[i].rgb_src_factor;
437 unsigned dstRGB = state->rt[i].rgb_dst_factor;
438
439 unsigned eqA = state->rt[i].alpha_func;
440 unsigned srcA = state->rt[i].alpha_src_factor;
441 unsigned dstA = state->rt[i].alpha_dst_factor;
442 uint32_t bc = 0;
443
444 if (!state->rt[i].blend_enable)
445 continue;
446
447 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
448 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
449 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
450
451 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
452 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
453 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
454 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
455 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
456 }
457
458 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
459 if (i == 0) {
460 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
461 }
462 }
463 return rstate;
464 }
465
466 static void *r600_create_dsa_state(struct pipe_context *ctx,
467 const struct pipe_depth_stencil_alpha_state *state)
468 {
469 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
470 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
471 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
472
473 if (rstate == NULL) {
474 return NULL;
475 }
476
477 rstate->id = R600_PIPE_STATE_DSA;
478 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
479 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
480 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
481 * be set if shader use texkill instruction
482 */
483 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
484 stencil_ref_mask = 0;
485 stencil_ref_mask_bf = 0;
486 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
487 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
488 S_028800_ZFUNC(state->depth.func);
489
490 /* stencil */
491 if (state->stencil[0].enabled) {
492 db_depth_control |= S_028800_STENCIL_ENABLE(1);
493 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
494 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
495 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
496 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
497
498
499 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
500 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
501 if (state->stencil[1].enabled) {
502 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
503 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
504 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
505 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
506 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
507 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
508 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
509 }
510 }
511
512 /* alpha */
513 alpha_test_control = 0;
514 alpha_ref = 0;
515 if (state->alpha.enabled) {
516 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
517 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
518 alpha_ref = fui(state->alpha.ref_value);
519 }
520
521 /* misc */
522 db_render_control = 0;
523 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
524 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
525 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
526 /* TODO db_render_override depends on query */
527 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
528 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
529 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
530 r600_pipe_state_add_reg(rstate,
531 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
532 0xFFFFFFFF & C_028430_STENCILREF, NULL);
533 r600_pipe_state_add_reg(rstate,
534 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
535 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
536 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
537 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
538 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
539 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
540 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
541 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
542 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
543 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
544 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
545 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
546 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
547
548 return rstate;
549 }
550
551 static void *r600_create_rs_state(struct pipe_context *ctx,
552 const struct pipe_rasterizer_state *state)
553 {
554 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
555 struct r600_pipe_state *rstate;
556 unsigned tmp;
557 unsigned prov_vtx = 1, polygon_dual_mode;
558 unsigned clip_rule;
559
560 if (rs == NULL) {
561 return NULL;
562 }
563
564 rstate = &rs->rstate;
565 rs->flatshade = state->flatshade;
566 rs->sprite_coord_enable = state->sprite_coord_enable;
567
568 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
569 /* offset */
570 rs->offset_units = state->offset_units;
571 rs->offset_scale = state->offset_scale * 12.0f;
572
573 rstate->id = R600_PIPE_STATE_RASTERIZER;
574 if (state->flatshade_first)
575 prov_vtx = 0;
576 tmp = S_0286D4_FLAT_SHADE_ENA(1);
577 if (state->sprite_coord_enable) {
578 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
579 S_0286D4_PNT_SPRITE_OVRD_X(2) |
580 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
581 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
582 S_0286D4_PNT_SPRITE_OVRD_W(1);
583 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
584 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
585 }
586 }
587 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
588
589 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
590 state->fill_back != PIPE_POLYGON_MODE_FILL);
591 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
592 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
593 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
594 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
595 S_028814_FACE(!state->front_ccw) |
596 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
597 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
598 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
599 S_028814_POLY_MODE(polygon_dual_mode) |
600 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
601 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
602 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
603 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
604 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
605 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
606 /* point size 12.4 fixed point */
607 tmp = (unsigned)(state->point_size * 8.0);
608 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
609 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
610
611 tmp = (unsigned)state->line_width * 8;
612 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
613
614 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
615 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
616 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
617
618 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
619 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
620 0xFFFFFFFF, NULL);
621
622 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
623 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
624 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
625 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
626 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
627 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
628
629 return rstate;
630 }
631
632 static void *r600_create_sampler_state(struct pipe_context *ctx,
633 const struct pipe_sampler_state *state)
634 {
635 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
636 union util_color uc;
637
638 if (rstate == NULL) {
639 return NULL;
640 }
641
642 rstate->id = R600_PIPE_STATE_SAMPLER;
643 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
644 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
645 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
646 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
647 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
648 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
649 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
650 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
651 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
652 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
653 /* FIXME LOD it depends on texture base level ... */
654 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
655 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
656 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
657 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
658 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
659 if (uc.ui) {
660 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
661 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
662 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
663 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
664 }
665 return rstate;
666 }
667
668 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
669 struct pipe_resource *texture,
670 const struct pipe_sampler_view *state)
671 {
672 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
673 struct r600_pipe_state *rstate;
674 const struct util_format_description *desc;
675 struct r600_resource_texture *tmp;
676 struct r600_resource *rbuffer;
677 unsigned format;
678 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
679 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
680 struct r600_bo *bo[2];
681
682 if (resource == NULL)
683 return NULL;
684 rstate = &resource->state;
685
686 /* initialize base object */
687 resource->base = *state;
688 resource->base.texture = NULL;
689 pipe_reference(NULL, &texture->reference);
690 resource->base.texture = texture;
691 resource->base.reference.count = 1;
692 resource->base.context = ctx;
693
694 swizzle[0] = state->swizzle_r;
695 swizzle[1] = state->swizzle_g;
696 swizzle[2] = state->swizzle_b;
697 swizzle[3] = state->swizzle_a;
698 format = r600_translate_texformat(state->format,
699 swizzle,
700 &word4, &yuv_format);
701 if (format == ~0) {
702 format = 0;
703 }
704 desc = util_format_description(state->format);
705 if (desc == NULL) {
706 R600_ERR("unknow format %d\n", state->format);
707 }
708 tmp = (struct r600_resource_texture*)texture;
709 rbuffer = &tmp->resource;
710 bo[0] = rbuffer->bo;
711 bo[1] = rbuffer->bo;
712 /* FIXME depth texture decompression */
713 if (tmp->depth) {
714 r600_texture_depth_flush(ctx, texture);
715 tmp = (struct r600_resource_texture*)texture;
716 rbuffer = &tmp->flushed_depth_texture->resource;
717 bo[0] = rbuffer->bo;
718 bo[1] = rbuffer->bo;
719 }
720 pitch = align(tmp->pitch_in_pixels[0], 8);
721 if (tmp->tiled) {
722 array_mode = tmp->array_mode[0];
723 tile_type = tmp->tile_type;
724 }
725
726 /* FIXME properly handle first level != 0 */
727 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
728 S_038000_DIM(r600_tex_dim(texture->target)) |
729 S_038000_TILE_MODE(array_mode) |
730 S_038000_TILE_TYPE(tile_type) |
731 S_038000_PITCH((pitch / 8) - 1) |
732 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
733 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
734 S_038004_TEX_HEIGHT(texture->height0 - 1) |
735 S_038004_TEX_DEPTH(texture->depth0 - 1) |
736 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
737 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
738 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
739 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
740 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
741 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
742 word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
743 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
744 S_038010_REQUEST_SIZE(1) |
745 S_038010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
746 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
747 S_038014_LAST_LEVEL(state->u.tex.last_level) |
748 S_038014_BASE_ARRAY(0) |
749 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
750 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
751 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
752
753 return &resource->base;
754 }
755
756 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
757 struct pipe_sampler_view **views)
758 {
759 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
760 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
761
762 for (int i = 0; i < count; i++) {
763 if (resource[i]) {
764 r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i);
765 }
766 }
767 }
768
769 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
770 struct pipe_sampler_view **views)
771 {
772 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
773 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
774 int i;
775
776 for (i = 0; i < count; i++) {
777 if (&rctx->ps_samplers.views[i]->base != views[i]) {
778 if (resource[i])
779 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
780 else
781 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
782
783 pipe_sampler_view_reference(
784 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
785 views[i]);
786
787 }
788 }
789 for (i = count; i < NUM_TEX_UNITS; i++) {
790 if (rctx->ps_samplers.views[i]) {
791 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
792 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
793 }
794 }
795 rctx->ps_samplers.n_views = count;
796 }
797
798 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
799 {
800 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
801 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
802
803 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
804 rctx->ps_samplers.n_samplers = count;
805
806 for (int i = 0; i < count; i++) {
807 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
808 }
809 }
810
811 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
812 {
813 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
814 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
815
816 for (int i = 0; i < count; i++) {
817 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
818 }
819 }
820
821 static void r600_set_clip_state(struct pipe_context *ctx,
822 const struct pipe_clip_state *state)
823 {
824 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
825 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
826
827 if (rstate == NULL)
828 return;
829
830 rctx->clip = *state;
831 rstate->id = R600_PIPE_STATE_CLIP;
832 for (int i = 0; i < state->nr; i++) {
833 r600_pipe_state_add_reg(rstate,
834 R_028E20_PA_CL_UCP0_X + i * 16,
835 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
836 r600_pipe_state_add_reg(rstate,
837 R_028E24_PA_CL_UCP0_Y + i * 16,
838 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
839 r600_pipe_state_add_reg(rstate,
840 R_028E28_PA_CL_UCP0_Z + i * 16,
841 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
842 r600_pipe_state_add_reg(rstate,
843 R_028E2C_PA_CL_UCP0_W + i * 16,
844 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
845 }
846 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
847 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
848 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
849 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
850
851 free(rctx->states[R600_PIPE_STATE_CLIP]);
852 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
853 r600_context_pipe_state_set(&rctx->ctx, rstate);
854 }
855
856 static void r600_set_polygon_stipple(struct pipe_context *ctx,
857 const struct pipe_poly_stipple *state)
858 {
859 }
860
861 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
862 {
863 }
864
865 static void r600_set_scissor_state(struct pipe_context *ctx,
866 const struct pipe_scissor_state *state)
867 {
868 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
869 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
870 u32 tl, br;
871
872 if (rstate == NULL)
873 return;
874
875 rstate->id = R600_PIPE_STATE_SCISSOR;
876 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
877 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
878 r600_pipe_state_add_reg(rstate,
879 R_028210_PA_SC_CLIPRECT_0_TL, tl,
880 0xFFFFFFFF, NULL);
881 r600_pipe_state_add_reg(rstate,
882 R_028214_PA_SC_CLIPRECT_0_BR, br,
883 0xFFFFFFFF, NULL);
884 r600_pipe_state_add_reg(rstate,
885 R_028218_PA_SC_CLIPRECT_1_TL, tl,
886 0xFFFFFFFF, NULL);
887 r600_pipe_state_add_reg(rstate,
888 R_02821C_PA_SC_CLIPRECT_1_BR, br,
889 0xFFFFFFFF, NULL);
890 r600_pipe_state_add_reg(rstate,
891 R_028220_PA_SC_CLIPRECT_2_TL, tl,
892 0xFFFFFFFF, NULL);
893 r600_pipe_state_add_reg(rstate,
894 R_028224_PA_SC_CLIPRECT_2_BR, br,
895 0xFFFFFFFF, NULL);
896 r600_pipe_state_add_reg(rstate,
897 R_028228_PA_SC_CLIPRECT_3_TL, tl,
898 0xFFFFFFFF, NULL);
899 r600_pipe_state_add_reg(rstate,
900 R_02822C_PA_SC_CLIPRECT_3_BR, br,
901 0xFFFFFFFF, NULL);
902
903 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
904 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
905 r600_context_pipe_state_set(&rctx->ctx, rstate);
906 }
907
908 static void r600_set_stencil_ref(struct pipe_context *ctx,
909 const struct pipe_stencil_ref *state)
910 {
911 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
912 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
913 u32 tmp;
914
915 if (rstate == NULL)
916 return;
917
918 rctx->stencil_ref = *state;
919 rstate->id = R600_PIPE_STATE_STENCIL_REF;
920 tmp = S_028430_STENCILREF(state->ref_value[0]);
921 r600_pipe_state_add_reg(rstate,
922 R_028430_DB_STENCILREFMASK, tmp,
923 ~C_028430_STENCILREF, NULL);
924 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
925 r600_pipe_state_add_reg(rstate,
926 R_028434_DB_STENCILREFMASK_BF, tmp,
927 ~C_028434_STENCILREF_BF, NULL);
928
929 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
930 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
931 r600_context_pipe_state_set(&rctx->ctx, rstate);
932 }
933
934 static void r600_set_viewport_state(struct pipe_context *ctx,
935 const struct pipe_viewport_state *state)
936 {
937 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
938 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
939
940 if (rstate == NULL)
941 return;
942
943 rctx->viewport = *state;
944 rstate->id = R600_PIPE_STATE_VIEWPORT;
945 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
946 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
947 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
948 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
949 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
950 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
951 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
952 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
953 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
954
955 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
956 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
957 r600_context_pipe_state_set(&rctx->ctx, rstate);
958 }
959
960 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
961 const struct pipe_framebuffer_state *state, int cb)
962 {
963 struct r600_resource_texture *rtex;
964 struct r600_resource *rbuffer;
965 struct r600_surface *surf;
966 unsigned level = state->cbufs[cb]->u.tex.level;
967 unsigned pitch, slice;
968 unsigned color_info;
969 unsigned format, swap, ntype;
970 unsigned offset;
971 const struct util_format_description *desc;
972 struct r600_bo *bo[3];
973
974 surf = (struct r600_surface *)state->cbufs[cb];
975 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
976 rbuffer = &rtex->resource;
977 bo[0] = rbuffer->bo;
978 bo[1] = rbuffer->bo;
979 bo[2] = rbuffer->bo;
980
981 /* XXX quite sure for dx10+ hw don't need any offset hacks */
982 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
983 level, state->cbufs[cb]->u.tex.first_layer);
984 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
985 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
986 ntype = 0;
987 desc = util_format_description(rtex->resource.base.b.format);
988 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
989 ntype = V_0280A0_NUMBER_SRGB;
990
991 format = r600_translate_colorformat(rtex->resource.base.b.format);
992 swap = r600_translate_colorswap(rtex->resource.base.b.format);
993 color_info = S_0280A0_FORMAT(format) |
994 S_0280A0_COMP_SWAP(swap) |
995 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
996 S_0280A0_BLEND_CLAMP(1) |
997 S_0280A0_NUMBER_TYPE(ntype);
998 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
999 color_info |= S_0280A0_SOURCE_FORMAT(1);
1000
1001 r600_pipe_state_add_reg(rstate,
1002 R_028040_CB_COLOR0_BASE + cb * 4,
1003 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
1004 r600_pipe_state_add_reg(rstate,
1005 R_0280A0_CB_COLOR0_INFO + cb * 4,
1006 color_info, 0xFFFFFFFF, bo[0]);
1007 r600_pipe_state_add_reg(rstate,
1008 R_028060_CB_COLOR0_SIZE + cb * 4,
1009 S_028060_PITCH_TILE_MAX(pitch) |
1010 S_028060_SLICE_TILE_MAX(slice),
1011 0xFFFFFFFF, NULL);
1012 r600_pipe_state_add_reg(rstate,
1013 R_028080_CB_COLOR0_VIEW + cb * 4,
1014 0x00000000, 0xFFFFFFFF, NULL);
1015 r600_pipe_state_add_reg(rstate,
1016 R_0280E0_CB_COLOR0_FRAG + cb * 4,
1017 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
1018 r600_pipe_state_add_reg(rstate,
1019 R_0280C0_CB_COLOR0_TILE + cb * 4,
1020 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
1021 r600_pipe_state_add_reg(rstate,
1022 R_028100_CB_COLOR0_MASK + cb * 4,
1023 0x00000000, 0xFFFFFFFF, NULL);
1024 }
1025
1026 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1027 const struct pipe_framebuffer_state *state)
1028 {
1029 struct r600_resource_texture *rtex;
1030 struct r600_resource *rbuffer;
1031 struct r600_surface *surf;
1032 unsigned level;
1033 unsigned pitch, slice, format;
1034 unsigned offset;
1035
1036 if (state->zsbuf == NULL)
1037 return;
1038
1039 level = state->zsbuf->u.tex.level;
1040
1041 surf = (struct r600_surface *)state->zsbuf;
1042 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1043 rtex->tiled = 1;
1044 rtex->array_mode[level] = 2;
1045 rtex->tile_type = 1;
1046 rtex->depth = 1;
1047 rbuffer = &rtex->resource;
1048
1049 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1050 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1051 level, state->zsbuf->u.tex.first_layer);
1052 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
1053 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
1054 format = r600_translate_dbformat(state->zsbuf->texture->format);
1055
1056 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1057 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
1058 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1059 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1060 0xFFFFFFFF, NULL);
1061 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
1062 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1063 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
1064 0xFFFFFFFF, rbuffer->bo);
1065 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1066 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL);
1067 }
1068
1069 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1070 const struct pipe_framebuffer_state *state)
1071 {
1072 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1073 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1074 u32 shader_mask, tl, br, shader_control, target_mask;
1075
1076 if (rstate == NULL)
1077 return;
1078
1079 /* unreference old buffer and reference new one */
1080 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1081
1082 util_copy_framebuffer_state(&rctx->framebuffer, state);
1083
1084 rctx->pframebuffer = &rctx->framebuffer;
1085
1086 /* build states */
1087 for (int i = 0; i < state->nr_cbufs; i++) {
1088 r600_cb(rctx, rstate, state, i);
1089 }
1090 if (state->zsbuf) {
1091 r600_db(rctx, rstate, state);
1092 }
1093
1094 target_mask = 0x00000000;
1095 target_mask = 0xFFFFFFFF;
1096 shader_mask = 0;
1097 shader_control = 0;
1098 for (int i = 0; i < state->nr_cbufs; i++) {
1099 target_mask ^= 0xf << (i * 4);
1100 shader_mask |= 0xf << (i * 4);
1101 shader_control |= 1 << i;
1102 }
1103 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1104 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1105
1106 r600_pipe_state_add_reg(rstate,
1107 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1108 0xFFFFFFFF, NULL);
1109 r600_pipe_state_add_reg(rstate,
1110 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1111 0xFFFFFFFF, NULL);
1112 r600_pipe_state_add_reg(rstate,
1113 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1114 0xFFFFFFFF, NULL);
1115 r600_pipe_state_add_reg(rstate,
1116 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1117 0xFFFFFFFF, NULL);
1118 r600_pipe_state_add_reg(rstate,
1119 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1120 0xFFFFFFFF, NULL);
1121 r600_pipe_state_add_reg(rstate,
1122 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1123 0xFFFFFFFF, NULL);
1124 r600_pipe_state_add_reg(rstate,
1125 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1126 0xFFFFFFFF, NULL);
1127 r600_pipe_state_add_reg(rstate,
1128 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1129 0xFFFFFFFF, NULL);
1130 r600_pipe_state_add_reg(rstate,
1131 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1132 0xFFFFFFFF, NULL);
1133 if (rctx->family >= CHIP_RV770) {
1134 r600_pipe_state_add_reg(rstate,
1135 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1136 0xFFFFFFFF, NULL);
1137 }
1138
1139 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1140 shader_control, 0xFFFFFFFF, NULL);
1141 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1142 0x00000000, target_mask, NULL);
1143 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1144 shader_mask, 0xFFFFFFFF, NULL);
1145 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1146 0x00000000, 0xFFFFFFFF, NULL);
1147 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1148 0x00000000, 0xFFFFFFFF, NULL);
1149 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1150 0x00000000, 0xFFFFFFFF, NULL);
1151 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1152 0x01000000, 0xFFFFFFFF, NULL);
1153 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1154 0x00000000, 0xFFFFFFFF, NULL);
1155 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1156 0x000000FF, 0xFFFFFFFF, NULL);
1157 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1158 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1159 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1160 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1161
1162 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1163 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1164 r600_context_pipe_state_set(&rctx->ctx, rstate);
1165
1166 if (state->zsbuf) {
1167 r600_polygon_offset_update(rctx);
1168 }
1169 }
1170
1171 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
1172 struct pipe_resource *buffer)
1173 {
1174 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1175 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
1176
1177 /* Note that the state tracker can unbind constant buffers by
1178 * passing NULL here.
1179 */
1180 if (buffer == NULL) {
1181 return;
1182 }
1183
1184 switch (shader) {
1185 case PIPE_SHADER_VERTEX:
1186 rctx->vs_const_buffer.nregs = 0;
1187 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1188 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1189 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1190 0xFFFFFFFF, NULL);
1191 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1192 R_028980_ALU_CONST_CACHE_VS_0,
1193 r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
1194 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
1195 break;
1196 case PIPE_SHADER_FRAGMENT:
1197 rctx->ps_const_buffer.nregs = 0;
1198 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1199 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1200 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1201 0xFFFFFFFF, NULL);
1202 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1203 R_028940_ALU_CONST_CACHE_PS_0,
1204 r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
1205 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
1206 break;
1207 default:
1208 R600_ERR("unsupported %d\n", shader);
1209 return;
1210 }
1211 }
1212
1213 void r600_init_state_functions(struct r600_pipe_context *rctx)
1214 {
1215 rctx->context.create_blend_state = r600_create_blend_state;
1216 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1217 rctx->context.create_fs_state = r600_create_shader_state;
1218 rctx->context.create_rasterizer_state = r600_create_rs_state;
1219 rctx->context.create_sampler_state = r600_create_sampler_state;
1220 rctx->context.create_sampler_view = r600_create_sampler_view;
1221 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1222 rctx->context.create_vs_state = r600_create_shader_state;
1223 rctx->context.bind_blend_state = r600_bind_blend_state;
1224 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
1225 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
1226 rctx->context.bind_fs_state = r600_bind_ps_shader;
1227 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1228 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1229 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
1230 rctx->context.bind_vs_state = r600_bind_vs_shader;
1231 rctx->context.delete_blend_state = r600_delete_state;
1232 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1233 rctx->context.delete_fs_state = r600_delete_ps_shader;
1234 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1235 rctx->context.delete_sampler_state = r600_delete_state;
1236 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1237 rctx->context.delete_vs_state = r600_delete_vs_shader;
1238 rctx->context.set_blend_color = r600_set_blend_color;
1239 rctx->context.set_clip_state = r600_set_clip_state;
1240 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1241 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1242 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1243 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1244 rctx->context.set_sample_mask = r600_set_sample_mask;
1245 rctx->context.set_scissor_state = r600_set_scissor_state;
1246 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1247 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1248 rctx->context.set_index_buffer = r600_set_index_buffer;
1249 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1250 rctx->context.set_viewport_state = r600_set_viewport_state;
1251 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1252 }
1253
1254 void r600_init_config(struct r600_pipe_context *rctx)
1255 {
1256 int ps_prio;
1257 int vs_prio;
1258 int gs_prio;
1259 int es_prio;
1260 int num_ps_gprs;
1261 int num_vs_gprs;
1262 int num_gs_gprs;
1263 int num_es_gprs;
1264 int num_temp_gprs;
1265 int num_ps_threads;
1266 int num_vs_threads;
1267 int num_gs_threads;
1268 int num_es_threads;
1269 int num_ps_stack_entries;
1270 int num_vs_stack_entries;
1271 int num_gs_stack_entries;
1272 int num_es_stack_entries;
1273 enum radeon_family family;
1274 struct r600_pipe_state *rstate = &rctx->config;
1275 u32 tmp;
1276
1277 family = r600_get_family(rctx->radeon);
1278 ps_prio = 0;
1279 vs_prio = 1;
1280 gs_prio = 2;
1281 es_prio = 3;
1282 switch (family) {
1283 case CHIP_R600:
1284 num_ps_gprs = 192;
1285 num_vs_gprs = 56;
1286 num_temp_gprs = 4;
1287 num_gs_gprs = 0;
1288 num_es_gprs = 0;
1289 num_ps_threads = 136;
1290 num_vs_threads = 48;
1291 num_gs_threads = 4;
1292 num_es_threads = 4;
1293 num_ps_stack_entries = 128;
1294 num_vs_stack_entries = 128;
1295 num_gs_stack_entries = 0;
1296 num_es_stack_entries = 0;
1297 break;
1298 case CHIP_RV630:
1299 case CHIP_RV635:
1300 num_ps_gprs = 84;
1301 num_vs_gprs = 36;
1302 num_temp_gprs = 4;
1303 num_gs_gprs = 0;
1304 num_es_gprs = 0;
1305 num_ps_threads = 144;
1306 num_vs_threads = 40;
1307 num_gs_threads = 4;
1308 num_es_threads = 4;
1309 num_ps_stack_entries = 40;
1310 num_vs_stack_entries = 40;
1311 num_gs_stack_entries = 32;
1312 num_es_stack_entries = 16;
1313 break;
1314 case CHIP_RV610:
1315 case CHIP_RV620:
1316 case CHIP_RS780:
1317 case CHIP_RS880:
1318 default:
1319 num_ps_gprs = 84;
1320 num_vs_gprs = 36;
1321 num_temp_gprs = 4;
1322 num_gs_gprs = 0;
1323 num_es_gprs = 0;
1324 num_ps_threads = 136;
1325 num_vs_threads = 48;
1326 num_gs_threads = 4;
1327 num_es_threads = 4;
1328 num_ps_stack_entries = 40;
1329 num_vs_stack_entries = 40;
1330 num_gs_stack_entries = 32;
1331 num_es_stack_entries = 16;
1332 break;
1333 case CHIP_RV670:
1334 num_ps_gprs = 144;
1335 num_vs_gprs = 40;
1336 num_temp_gprs = 4;
1337 num_gs_gprs = 0;
1338 num_es_gprs = 0;
1339 num_ps_threads = 136;
1340 num_vs_threads = 48;
1341 num_gs_threads = 4;
1342 num_es_threads = 4;
1343 num_ps_stack_entries = 40;
1344 num_vs_stack_entries = 40;
1345 num_gs_stack_entries = 32;
1346 num_es_stack_entries = 16;
1347 break;
1348 case CHIP_RV770:
1349 num_ps_gprs = 192;
1350 num_vs_gprs = 56;
1351 num_temp_gprs = 4;
1352 num_gs_gprs = 0;
1353 num_es_gprs = 0;
1354 num_ps_threads = 188;
1355 num_vs_threads = 60;
1356 num_gs_threads = 0;
1357 num_es_threads = 0;
1358 num_ps_stack_entries = 256;
1359 num_vs_stack_entries = 256;
1360 num_gs_stack_entries = 0;
1361 num_es_stack_entries = 0;
1362 break;
1363 case CHIP_RV730:
1364 case CHIP_RV740:
1365 num_ps_gprs = 84;
1366 num_vs_gprs = 36;
1367 num_temp_gprs = 4;
1368 num_gs_gprs = 0;
1369 num_es_gprs = 0;
1370 num_ps_threads = 188;
1371 num_vs_threads = 60;
1372 num_gs_threads = 0;
1373 num_es_threads = 0;
1374 num_ps_stack_entries = 128;
1375 num_vs_stack_entries = 128;
1376 num_gs_stack_entries = 0;
1377 num_es_stack_entries = 0;
1378 break;
1379 case CHIP_RV710:
1380 num_ps_gprs = 192;
1381 num_vs_gprs = 56;
1382 num_temp_gprs = 4;
1383 num_gs_gprs = 0;
1384 num_es_gprs = 0;
1385 num_ps_threads = 144;
1386 num_vs_threads = 48;
1387 num_gs_threads = 0;
1388 num_es_threads = 0;
1389 num_ps_stack_entries = 128;
1390 num_vs_stack_entries = 128;
1391 num_gs_stack_entries = 0;
1392 num_es_stack_entries = 0;
1393 break;
1394 }
1395
1396 rstate->id = R600_PIPE_STATE_CONFIG;
1397
1398 /* SQ_CONFIG */
1399 tmp = 0;
1400 switch (family) {
1401 case CHIP_RV610:
1402 case CHIP_RV620:
1403 case CHIP_RS780:
1404 case CHIP_RS880:
1405 case CHIP_RV710:
1406 break;
1407 default:
1408 tmp |= S_008C00_VC_ENABLE(1);
1409 break;
1410 }
1411 tmp |= S_008C00_DX9_CONSTS(0);
1412 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1413 tmp |= S_008C00_PS_PRIO(ps_prio);
1414 tmp |= S_008C00_VS_PRIO(vs_prio);
1415 tmp |= S_008C00_GS_PRIO(gs_prio);
1416 tmp |= S_008C00_ES_PRIO(es_prio);
1417 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1418
1419 /* SQ_GPR_RESOURCE_MGMT_1 */
1420 tmp = 0;
1421 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1422 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1423 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1424 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1425
1426 /* SQ_GPR_RESOURCE_MGMT_2 */
1427 tmp = 0;
1428 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1429 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1430 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1431
1432 /* SQ_THREAD_RESOURCE_MGMT */
1433 tmp = 0;
1434 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1435 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1436 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1437 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1438 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1439
1440 /* SQ_STACK_RESOURCE_MGMT_1 */
1441 tmp = 0;
1442 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1443 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1444 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1445
1446 /* SQ_STACK_RESOURCE_MGMT_2 */
1447 tmp = 0;
1448 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1449 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1450 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1451
1452 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1453 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1454
1455 if (family >= CHIP_RV770) {
1456 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1457 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1458 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1459 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1460 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1461 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
1462 } else {
1463 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1464 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1465 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1466 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1467 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1468 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
1469 }
1470 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1471 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1472 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1473 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1474 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1475 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1476 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1477 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1478 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1479 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1480 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1481 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1482 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1483 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1484 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1485 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1486 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1487 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1488 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1489 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1490 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1491 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1492 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1493 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1494 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1495 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1496
1497 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1498 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1499 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1500 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1501 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1502 r600_context_pipe_state_set(&rctx->ctx, rstate);
1503 }
1504
1505 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1506 {
1507 struct pipe_depth_stencil_alpha_state dsa;
1508 struct r600_pipe_state *rstate;
1509 boolean quirk = false;
1510
1511 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1512 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1513 quirk = true;
1514
1515 memset(&dsa, 0, sizeof(dsa));
1516
1517 if (quirk) {
1518 dsa.depth.enabled = 1;
1519 dsa.depth.func = PIPE_FUNC_LEQUAL;
1520 dsa.stencil[0].enabled = 1;
1521 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1522 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1523 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1524 dsa.stencil[0].writemask = 0xff;
1525 }
1526
1527 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1528 r600_pipe_state_add_reg(rstate,
1529 R_02880C_DB_SHADER_CONTROL,
1530 0x0,
1531 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1532 r600_pipe_state_add_reg(rstate,
1533 R_028D0C_DB_RENDER_CONTROL,
1534 S_028D0C_DEPTH_COPY_ENABLE(1) |
1535 S_028D0C_STENCIL_COPY_ENABLE(1) |
1536 S_028D0C_COPY_CENTROID(1),
1537 S_028D0C_DEPTH_COPY_ENABLE(1) |
1538 S_028D0C_STENCIL_COPY_ENABLE(1) |
1539 S_028D0C_COPY_CENTROID(1), NULL);
1540 return rstate;
1541 }