projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: check for PIPE_BIND_BLENDABLE in is_format_supported
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
145 {
146 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
147 }
148
149 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
150 {
151 return r600_translate_colorformat(chip, format) != ~0U &&
152 r600_translate_colorswap(format) != ~0U;
153 }
154
155 static bool r600_is_zs_format_supported(enum pipe_format format)
156 {
157 return r600_translate_dbformat(format) != ~0U;
158 }
159
160 static inline bool r600_is_blending_supported(enum pipe_format format)
161 {
162 return !(util_format_is_pure_integer(format) || util_format_is_depth_or_stencil(format));
163 }
164
165 boolean r600_is_format_supported(struct pipe_screen *screen,
166 enum pipe_format format,
167 enum pipe_texture_target target,
168 unsigned sample_count,
169 unsigned usage)
170 {
171 struct r600_screen *rscreen = (struct r600_screen*)screen;
172 unsigned retval = 0;
173
174 if (target >= PIPE_MAX_TEXTURE_TYPES) {
175 R600_ERR("r600: unsupported texture type %d\n", target);
176 return FALSE;
177 }
178
179 if (!util_format_is_supported(format, usage))
180 return FALSE;
181
182 if (sample_count > 1) {
183 if (!rscreen->has_msaa)
184 return FALSE;
185
186 /* R11G11B10 is broken on R6xx. */
187 if (rscreen->b.chip_class == R600 &&
188 format == PIPE_FORMAT_R11G11B10_FLOAT)
189 return FALSE;
190
191 /* MSAA integer colorbuffers hang. */
192 if (util_format_is_pure_integer(format) &&
193 !util_format_is_depth_or_stencil(format))
194 return FALSE;
195
196 switch (sample_count) {
197 case 2:
198 case 4:
199 case 8:
200 break;
201 default:
202 return FALSE;
203 }
204 }
205
206 if (usage & PIPE_BIND_SAMPLER_VIEW) {
207 if (target == PIPE_BUFFER) {
208 if (r600_is_vertex_format_supported(format))
209 retval |= PIPE_BIND_SAMPLER_VIEW;
210 } else {
211 if (r600_is_sampler_format_supported(screen, format))
212 retval |= PIPE_BIND_SAMPLER_VIEW;
213 }
214 }
215
216 if ((usage & (PIPE_BIND_RENDER_TARGET |
217 PIPE_BIND_DISPLAY_TARGET |
218 PIPE_BIND_SCANOUT |
219 PIPE_BIND_SHARED)) &&
220 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
221 retval |= usage &
222 (PIPE_BIND_RENDER_TARGET |
223 PIPE_BIND_DISPLAY_TARGET |
224 PIPE_BIND_SCANOUT |
225 PIPE_BIND_SHARED);
226 }
227
228 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
229 r600_is_zs_format_supported(format)) {
230 retval |= PIPE_BIND_DEPTH_STENCIL;
231 }
232
233 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
234 r600_is_vertex_format_supported(format)) {
235 retval |= PIPE_BIND_VERTEX_BUFFER;
236 }
237
238 if (usage & PIPE_BIND_TRANSFER_READ)
239 retval |= PIPE_BIND_TRANSFER_READ;
240 if (usage & PIPE_BIND_TRANSFER_WRITE)
241 retval |= PIPE_BIND_TRANSFER_WRITE;
242
243 if ((usage & PIPE_BIND_BLENDABLE) &&
244 r600_is_blending_supported(format))
245 retval |= PIPE_BIND_BLENDABLE;
246
247 return retval == usage;
248 }
249
250 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
251 {
252 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
253 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
254 float offset_units = state->offset_units;
255 float offset_scale = state->offset_scale;
256
257 switch (state->zs_format) {
258 case PIPE_FORMAT_Z24X8_UNORM:
259 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
260 offset_units *= 2.0f;
261 break;
262 case PIPE_FORMAT_Z16_UNORM:
263 offset_units *= 4.0f;
264 break;
265 default:;
266 }
267
268 r600_write_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
269 radeon_emit(cs, fui(offset_scale));
270 radeon_emit(cs, fui(offset_units));
271 radeon_emit(cs, fui(offset_scale));
272 radeon_emit(cs, fui(offset_units));
273 }
274
275 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
276 {
277 int j = state->independent_blend_enable ? i : 0;
278
279 unsigned eqRGB = state->rt[j].rgb_func;
280 unsigned srcRGB = state->rt[j].rgb_src_factor;
281 unsigned dstRGB = state->rt[j].rgb_dst_factor;
282
283 unsigned eqA = state->rt[j].alpha_func;
284 unsigned srcA = state->rt[j].alpha_src_factor;
285 unsigned dstA = state->rt[j].alpha_dst_factor;
286 uint32_t bc = 0;
287
288 if (!state->rt[j].blend_enable)
289 return 0;
290
291 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
292 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
293 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
294
295 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
296 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
297 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
298 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
299 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
300 }
301 return bc;
302 }
303
304 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
305 const struct pipe_blend_state *state,
306 int mode)
307 {
308 struct r600_context *rctx = (struct r600_context *)ctx;
309 uint32_t color_control = 0, target_mask = 0;
310 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
311
312 if (!blend) {
313 return NULL;
314 }
315
316 r600_init_command_buffer(&blend->buffer, 20);
317 r600_init_command_buffer(&blend->buffer_no_blend, 20);
318
319 /* R600 does not support per-MRT blends */
320 if (rctx->b.family > CHIP_R600)
321 color_control |= S_028808_PER_MRT_BLEND(1);
322
323 if (state->logicop_enable) {
324 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
325 } else {
326 color_control |= (0xcc << 16);
327 }
328 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
329 if (state->independent_blend_enable) {
330 for (int i = 0; i < 8; i++) {
331 if (state->rt[i].blend_enable) {
332 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
333 }
334 target_mask |= (state->rt[i].colormask << (4 * i));
335 }
336 } else {
337 for (int i = 0; i < 8; i++) {
338 if (state->rt[0].blend_enable) {
339 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
340 }
341 target_mask |= (state->rt[0].colormask << (4 * i));
342 }
343 }
344
345 if (target_mask)
346 color_control |= S_028808_SPECIAL_OP(mode);
347 else
348 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
349
350 /* only MRT0 has dual src blend */
351 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
352 blend->cb_target_mask = target_mask;
353 blend->cb_color_control = color_control;
354 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
355 blend->alpha_to_one = state->alpha_to_one;
356
357 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
358 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
359 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
360 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
361 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
362 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
363
364 /* Copy over the registers set so far into buffer_no_blend. */
365 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
366 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
367
368 /* Only add blend registers if blending is enabled. */
369 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
370 return blend;
371 }
372
373 /* The first R600 does not support per-MRT blends */
374 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
375 r600_get_blend_control(state, 0));
376
377 if (rctx->b.family > CHIP_R600) {
378 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
379 for (int i = 0; i < 8; i++) {
380 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
381 }
382 }
383 return blend;
384 }
385
386 static void *r600_create_blend_state(struct pipe_context *ctx,
387 const struct pipe_blend_state *state)
388 {
389 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
390 }
391
392 static void *r600_create_dsa_state(struct pipe_context *ctx,
393 const struct pipe_depth_stencil_alpha_state *state)
394 {
395 unsigned db_depth_control, alpha_test_control, alpha_ref;
396 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
397
398 if (dsa == NULL) {
399 return NULL;
400 }
401
402 r600_init_command_buffer(&dsa->buffer, 3);
403
404 dsa->valuemask[0] = state->stencil[0].valuemask;
405 dsa->valuemask[1] = state->stencil[1].valuemask;
406 dsa->writemask[0] = state->stencil[0].writemask;
407 dsa->writemask[1] = state->stencil[1].writemask;
408 dsa->zwritemask = state->depth.writemask;
409
410 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
411 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
412 S_028800_ZFUNC(state->depth.func);
413
414 /* stencil */
415 if (state->stencil[0].enabled) {
416 db_depth_control |= S_028800_STENCIL_ENABLE(1);
417 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
418 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
419 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
420 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
421
422 if (state->stencil[1].enabled) {
423 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
424 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
425 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
426 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
427 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
428 }
429 }
430
431 /* alpha */
432 alpha_test_control = 0;
433 alpha_ref = 0;
434 if (state->alpha.enabled) {
435 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
436 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
437 alpha_ref = fui(state->alpha.ref_value);
438 }
439 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
440 dsa->alpha_ref = alpha_ref;
441
442 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
443 return dsa;
444 }
445
446 static void *r600_create_rs_state(struct pipe_context *ctx,
447 const struct pipe_rasterizer_state *state)
448 {
449 struct r600_context *rctx = (struct r600_context *)ctx;
450 unsigned tmp, sc_mode_cntl, spi_interp;
451 float psize_min, psize_max;
452 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
453
454 if (rs == NULL) {
455 return NULL;
456 }
457
458 r600_init_command_buffer(&rs->buffer, 30);
459
460 rs->flatshade = state->flatshade;
461 rs->sprite_coord_enable = state->sprite_coord_enable;
462 rs->two_side = state->light_twoside;
463 rs->clip_plane_enable = state->clip_plane_enable;
464 rs->pa_sc_line_stipple = state->line_stipple_enable ?
465 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
466 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
467 rs->pa_cl_clip_cntl =
468 S_028810_PS_UCP_MODE(3) |
469 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
470 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
471 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
472 if (rctx->b.chip_class == R700) {
473 rs->pa_cl_clip_cntl |=
474 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
475 }
476 rs->multisample_enable = state->multisample;
477
478 /* offset */
479 rs->offset_units = state->offset_units;
480 rs->offset_scale = state->offset_scale * 12.0f;
481 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
482
483 if (state->point_size_per_vertex) {
484 psize_min = util_get_min_point_size(state);
485 psize_max = 8192;
486 } else {
487 /* Force the point size to be as if the vertex output was disabled. */
488 psize_min = state->point_size;
489 psize_max = state->point_size;
490 }
491
492 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
493 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
494 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
495 if (rctx->b.chip_class >= R700) {
496 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
497 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
498 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
499 } else {
500 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
501 rs->scissor_enable = state->scissor;
502 }
503
504 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
505 if (state->sprite_coord_enable) {
506 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
507 S_0286D4_PNT_SPRITE_OVRD_X(2) |
508 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
509 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
510 S_0286D4_PNT_SPRITE_OVRD_W(1);
511 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
512 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
513 }
514 }
515
516 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
517 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
518 tmp = r600_pack_float_12p4(state->point_size/2);
519 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
520 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
521 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
522 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
523 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
524 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
525 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
526
527 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
528 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
529 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
530 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
531 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
532 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
533
534 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
535 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
536 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
537 S_028814_FACE(!state->front_ccw) |
538 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
539 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
540 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
541 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
542 state->fill_back != PIPE_POLYGON_MODE_FILL) |
543 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
544 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
545 if (rctx->b.chip_class == R700) {
546 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
547 }
548 if (rctx->b.chip_class == R600) {
549 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
550 S_028350_MULTIPASS(state->rasterizer_discard));
551 }
552 return rs;
553 }
554
555 static void *r600_create_sampler_state(struct pipe_context *ctx,
556 const struct pipe_sampler_state *state)
557 {
558 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
559 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
560
561 if (ss == NULL) {
562 return NULL;
563 }
564
565 ss->seamless_cube_map = state->seamless_cube_map;
566 ss->border_color_use = sampler_state_needs_border_color(state);
567
568 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
569 ss->tex_sampler_words[0] =
570 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
571 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
572 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
573 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
574 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
575 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
576 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
577 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
578 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
579 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
580 ss->tex_sampler_words[1] =
581 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
582 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
583 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
584 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
585 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
586
587 if (ss->border_color_use) {
588 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
589 }
590 return ss;
591 }
592
593 static struct pipe_sampler_view *
594 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
595 unsigned width0, unsigned height0)
596
597 {
598 struct pipe_context *ctx = view->base.context;
599 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
600 uint64_t va;
601 int stride = util_format_get_blocksize(view->base.format);
602 unsigned format, num_format, format_comp, endian;
603 unsigned offset = view->base.u.buf.first_element * stride;
604 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
605
606 r600_vertex_data_type(view->base.format,
607 &format, &num_format, &format_comp,
608 &endian);
609
610 va = r600_resource_va(ctx->screen, view->base.texture) + offset;
611 view->tex_resource = &tmp->resource;
612
613 view->skip_mip_address_reloc = true;
614 view->tex_resource_words[0] = va;
615 view->tex_resource_words[1] = size - 1;
616 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(va >> 32UL) |
617 S_038008_STRIDE(stride) |
618 S_038008_DATA_FORMAT(format) |
619 S_038008_NUM_FORMAT_ALL(num_format) |
620 S_038008_FORMAT_COMP_ALL(format_comp) |
621 S_038008_SRF_MODE_ALL(1) |
622 S_038008_ENDIAN_SWAP(endian);
623 view->tex_resource_words[3] = 0;
624 /*
625 * in theory dword 4 is for number of elements, for use with resinfo,
626 * but it seems to utterly fail to work, the amd gpu shader analyser
627 * uses a const buffer to store the element sizes for buffer txq
628 */
629 view->tex_resource_words[4] = 0;
630 view->tex_resource_words[5] = 0;
631 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
632 return &view->base;
633 }
634
635 struct pipe_sampler_view *
636 r600_create_sampler_view_custom(struct pipe_context *ctx,
637 struct pipe_resource *texture,
638 const struct pipe_sampler_view *state,
639 unsigned width_first_level, unsigned height_first_level)
640 {
641 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
642 struct r600_texture *tmp = (struct r600_texture*)texture;
643 unsigned format, endian;
644 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
645 unsigned char swizzle[4], array_mode = 0;
646 unsigned width, height, depth, offset_level, last_level;
647
648 if (view == NULL)
649 return NULL;
650
651 /* initialize base object */
652 view->base = *state;
653 view->base.texture = NULL;
654 pipe_reference(NULL, &texture->reference);
655 view->base.texture = texture;
656 view->base.reference.count = 1;
657 view->base.context = ctx;
658
659 if (texture->target == PIPE_BUFFER)
660 return texture_buffer_sampler_view(view, texture->width0, 1);
661
662 swizzle[0] = state->swizzle_r;
663 swizzle[1] = state->swizzle_g;
664 swizzle[2] = state->swizzle_b;
665 swizzle[3] = state->swizzle_a;
666
667 format = r600_translate_texformat(ctx->screen, state->format,
668 swizzle,
669 &word4, &yuv_format);
670 assert(format != ~0);
671 if (format == ~0) {
672 FREE(view);
673 return NULL;
674 }
675
676 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
677 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
678 FREE(view);
679 return NULL;
680 }
681 tmp = tmp->flushed_depth_texture;
682 }
683
684 endian = r600_colorformat_endian_swap(format);
685
686 offset_level = state->u.tex.first_level;
687 last_level = state->u.tex.last_level - offset_level;
688 width = width_first_level;
689 height = height_first_level;
690 depth = u_minify(texture->depth0, offset_level);
691 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
692
693 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
694 height = 1;
695 depth = texture->array_size;
696 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
697 depth = texture->array_size;
698 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
699 depth = texture->array_size / 6;
700 switch (tmp->surface.level[offset_level].mode) {
701 case RADEON_SURF_MODE_LINEAR_ALIGNED:
702 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
703 break;
704 case RADEON_SURF_MODE_1D:
705 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
706 break;
707 case RADEON_SURF_MODE_2D:
708 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
709 break;
710 case RADEON_SURF_MODE_LINEAR:
711 default:
712 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
713 break;
714 }
715
716 view->tex_resource = &tmp->resource;
717 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
718 S_038000_TILE_MODE(array_mode) |
719 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
720 S_038000_PITCH((pitch / 8) - 1) |
721 S_038000_TEX_WIDTH(width - 1));
722 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
723 S_038004_TEX_DEPTH(depth - 1) |
724 S_038004_DATA_FORMAT(format));
725 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
726 if (offset_level >= tmp->surface.last_level) {
727 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
728 } else {
729 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
730 }
731 view->tex_resource_words[4] = (word4 |
732 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
733 S_038010_REQUEST_SIZE(1) |
734 S_038010_ENDIAN_SWAP(endian) |
735 S_038010_BASE_LEVEL(0));
736 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
737 S_038014_LAST_ARRAY(state->u.tex.last_layer));
738 if (texture->nr_samples > 1) {
739 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
740 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
741 } else {
742 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
743 }
744 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
745 S_038018_MAX_ANISO(4 /* max 16 samples */));
746 return &view->base;
747 }
748
749 static struct pipe_sampler_view *
750 r600_create_sampler_view(struct pipe_context *ctx,
751 struct pipe_resource *tex,
752 const struct pipe_sampler_view *state)
753 {
754 return r600_create_sampler_view_custom(ctx, tex, state,
755 u_minify(tex->width0, state->u.tex.first_level),
756 u_minify(tex->height0, state->u.tex.first_level));
757 }
758
759 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
760 {
761 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
762 struct pipe_clip_state *state = &rctx->clip_state.state;
763
764 r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
765 radeon_emit_array(cs, (unsigned*)state, 6*4);
766 }
767
768 static void r600_set_polygon_stipple(struct pipe_context *ctx,
769 const struct pipe_poly_stipple *state)
770 {
771 }
772
773 static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
774 {
775 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
776 struct r600_scissor_state *rstate = (struct r600_scissor_state *)atom;
777 struct pipe_scissor_state *state = &rstate->scissor;
778 unsigned offset = rstate->idx * 4 * 2;
779
780 if (rctx->b.chip_class != R600 || rctx->scissor[0].enable) {
781 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
782 radeon_emit(cs, S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
783 S_028240_WINDOW_OFFSET_DISABLE(1));
784 radeon_emit(cs, S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy));
785 } else {
786 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
787 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
788 S_028240_WINDOW_OFFSET_DISABLE(1));
789 radeon_emit(cs, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
790 }
791 }
792
793 static void r600_set_scissor_states(struct pipe_context *ctx,
794 unsigned start_slot,
795 unsigned num_scissors,
796 const struct pipe_scissor_state *state)
797 {
798 struct r600_context *rctx = (struct r600_context *)ctx;
799 int i;
800
801 for (i = start_slot ; i < start_slot + num_scissors; i++) {
802 rctx->scissor[i].scissor = state[i - start_slot];
803 }
804
805 if (rctx->b.chip_class == R600 && !rctx->scissor[0].enable)
806 return;
807
808 for (i = start_slot ; i < start_slot + num_scissors; i++) {
809 rctx->scissor[i].atom.dirty = true;
810 }
811 }
812
813 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
814 unsigned size, unsigned alignment)
815 {
816 struct pipe_resource buffer;
817
818 memset(&buffer, 0, sizeof buffer);
819 buffer.target = PIPE_BUFFER;
820 buffer.format = PIPE_FORMAT_R8_UNORM;
821 buffer.bind = PIPE_BIND_CUSTOM;
822 buffer.usage = PIPE_USAGE_DEFAULT;
823 buffer.flags = 0;
824 buffer.width0 = size;
825 buffer.height0 = 1;
826 buffer.depth0 = 1;
827 buffer.array_size = 1;
828
829 return (struct r600_resource*)
830 r600_buffer_create(&rscreen->b.b, &buffer, alignment);
831 }
832
833 static void r600_init_color_surface(struct r600_context *rctx,
834 struct r600_surface *surf,
835 bool force_cmask_fmask)
836 {
837 struct r600_screen *rscreen = rctx->screen;
838 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
839 unsigned level = surf->base.u.tex.level;
840 unsigned pitch, slice;
841 unsigned color_info;
842 unsigned color_view;
843 unsigned format, swap, ntype, endian;
844 unsigned offset;
845 const struct util_format_description *desc;
846 int i;
847 bool blend_bypass = 0, blend_clamp = 1;
848
849 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
850 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
851 rtex = rtex->flushed_depth_texture;
852 assert(rtex);
853 }
854
855 offset = rtex->surface.level[level].offset;
856 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
857 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
858 offset += rtex->surface.level[level].slice_size *
859 surf->base.u.tex.first_layer;
860 color_view = 0;
861 } else
862 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
863 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
864
865 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
866 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
867 if (slice) {
868 slice = slice - 1;
869 }
870 color_info = 0;
871 switch (rtex->surface.level[level].mode) {
872 case RADEON_SURF_MODE_LINEAR_ALIGNED:
873 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
874 break;
875 case RADEON_SURF_MODE_1D:
876 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
877 break;
878 case RADEON_SURF_MODE_2D:
879 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
880 break;
881 case RADEON_SURF_MODE_LINEAR:
882 default:
883 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
884 break;
885 }
886
887 desc = util_format_description(surf->base.format);
888
889 for (i = 0; i < 4; i++) {
890 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
891 break;
892 }
893 }
894
895 ntype = V_0280A0_NUMBER_UNORM;
896 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
897 ntype = V_0280A0_NUMBER_SRGB;
898 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
899 if (desc->channel[i].normalized)
900 ntype = V_0280A0_NUMBER_SNORM;
901 else if (desc->channel[i].pure_integer)
902 ntype = V_0280A0_NUMBER_SINT;
903 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
904 if (desc->channel[i].normalized)
905 ntype = V_0280A0_NUMBER_UNORM;
906 else if (desc->channel[i].pure_integer)
907 ntype = V_0280A0_NUMBER_UINT;
908 }
909
910 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
911 assert(format != ~0);
912
913 swap = r600_translate_colorswap(surf->base.format);
914 assert(swap != ~0);
915
916 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
917 endian = ENDIAN_NONE;
918 } else {
919 endian = r600_colorformat_endian_swap(format);
920 }
921
922 /* set blend bypass according to docs if SINT/UINT or
923 8/24 COLOR variants */
924 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
925 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
926 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
927 blend_clamp = 0;
928 blend_bypass = 1;
929 }
930
931 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
932
933 color_info |= S_0280A0_FORMAT(format) |
934 S_0280A0_COMP_SWAP(swap) |
935 S_0280A0_BLEND_BYPASS(blend_bypass) |
936 S_0280A0_BLEND_CLAMP(blend_clamp) |
937 S_0280A0_NUMBER_TYPE(ntype) |
938 S_0280A0_ENDIAN(endian);
939
940 /* EXPORT_NORM is an optimzation that can be enabled for better
941 * performance in certain cases
942 */
943 if (rctx->b.chip_class == R600) {
944 /* EXPORT_NORM can be enabled if:
945 * - 11-bit or smaller UNORM/SNORM/SRGB
946 * - BLEND_CLAMP is enabled
947 * - BLEND_FLOAT32 is disabled
948 */
949 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
950 (desc->channel[i].size < 12 &&
951 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
952 ntype != V_0280A0_NUMBER_UINT &&
953 ntype != V_0280A0_NUMBER_SINT) &&
954 G_0280A0_BLEND_CLAMP(color_info) &&
955 !G_0280A0_BLEND_FLOAT32(color_info)) {
956 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
957 surf->export_16bpc = true;
958 }
959 } else {
960 /* EXPORT_NORM can be enabled if:
961 * - 11-bit or smaller UNORM/SNORM/SRGB
962 * - 16-bit or smaller FLOAT
963 */
964 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
965 ((desc->channel[i].size < 12 &&
966 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
967 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
968 (desc->channel[i].size < 17 &&
969 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
970 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
971 surf->export_16bpc = true;
972 }
973 }
974
975 /* These might not always be initialized to zero. */
976 surf->cb_color_base = offset >> 8;
977 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
978 S_028060_SLICE_TILE_MAX(slice);
979 surf->cb_color_fmask = surf->cb_color_base;
980 surf->cb_color_cmask = surf->cb_color_base;
981 surf->cb_color_mask = 0;
982
983 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
984 &rtex->resource.b.b);
985 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
986 &rtex->resource.b.b);
987
988 if (rtex->cmask.size) {
989 surf->cb_color_cmask = rtex->cmask.offset >> 8;
990 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
991
992 if (rtex->fmask.size) {
993 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
994 surf->cb_color_fmask = rtex->fmask.offset >> 8;
995 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
996 } else { /* cmask only */
997 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
998 }
999 } else if (force_cmask_fmask) {
1000 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1001 *
1002 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1003 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1004 * because it's not an MSAA buffer.
1005 */
1006 struct r600_cmask_info cmask;
1007 struct r600_fmask_info fmask;
1008
1009 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
1010 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
1011
1012 /* CMASK. */
1013 if (!rctx->dummy_cmask ||
1014 rctx->dummy_cmask->buf->size < cmask.size ||
1015 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1016 struct pipe_transfer *transfer;
1017 void *ptr;
1018
1019 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1020 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1021
1022 /* Set the contents to 0xCC. */
1023 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1024 memset(ptr, 0xCC, cmask.size);
1025 pipe_buffer_unmap(&rctx->b.b, transfer);
1026 }
1027 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1028 &rctx->dummy_cmask->b.b);
1029
1030 /* FMASK. */
1031 if (!rctx->dummy_fmask ||
1032 rctx->dummy_fmask->buf->size < fmask.size ||
1033 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1034 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1035 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1036
1037 }
1038 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1039 &rctx->dummy_fmask->b.b);
1040
1041 /* Init the registers. */
1042 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1043 surf->cb_color_cmask = 0;
1044 surf->cb_color_fmask = 0;
1045 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1046 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1047 }
1048
1049 surf->cb_color_info = color_info;
1050 surf->cb_color_view = color_view;
1051 surf->color_initialized = true;
1052 }
1053
1054 static void r600_init_depth_surface(struct r600_context *rctx,
1055 struct r600_surface *surf)
1056 {
1057 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1058 unsigned level, pitch, slice, format, offset, array_mode;
1059
1060 level = surf->base.u.tex.level;
1061 offset = rtex->surface.level[level].offset;
1062 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1063 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1064 if (slice) {
1065 slice = slice - 1;
1066 }
1067 switch (rtex->surface.level[level].mode) {
1068 case RADEON_SURF_MODE_2D:
1069 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1070 break;
1071 case RADEON_SURF_MODE_1D:
1072 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1073 case RADEON_SURF_MODE_LINEAR:
1074 default:
1075 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1076 break;
1077 }
1078
1079 format = r600_translate_dbformat(surf->base.format);
1080 assert(format != ~0);
1081
1082 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1083 surf->db_depth_base = offset >> 8;
1084 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1085 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1086 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1087 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1088
1089 switch (surf->base.format) {
1090 case PIPE_FORMAT_Z24X8_UNORM:
1091 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1092 surf->pa_su_poly_offset_db_fmt_cntl =
1093 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1094 break;
1095 case PIPE_FORMAT_Z32_FLOAT:
1096 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1097 surf->pa_su_poly_offset_db_fmt_cntl =
1098 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1099 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1100 break;
1101 case PIPE_FORMAT_Z16_UNORM:
1102 surf->pa_su_poly_offset_db_fmt_cntl =
1103 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1104 break;
1105 default:;
1106 }
1107
1108 /* use htile only for first level */
1109 if (rtex->htile_buffer && !level) {
1110 uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b);
1111 surf->db_htile_data_base = va >> 8;
1112 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1113 S_028D24_HTILE_HEIGHT(1) |
1114 S_028D24_FULL_CACHE(1) |
1115 S_028D24_LINEAR(1);
1116 /* preload is not working properly on r6xx/r7xx */
1117 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1118 }
1119
1120 surf->depth_initialized = true;
1121 }
1122
1123 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1124 const struct pipe_framebuffer_state *state)
1125 {
1126 struct r600_context *rctx = (struct r600_context *)ctx;
1127 struct r600_surface *surf;
1128 struct r600_texture *rtex;
1129 unsigned i;
1130
1131 if (rctx->framebuffer.state.nr_cbufs) {
1132 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1133 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1134 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1135 }
1136 if (rctx->framebuffer.state.zsbuf) {
1137 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1138 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1139
1140 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1141 if (rctx->b.chip_class >= R700 && rtex->htile_buffer) {
1142 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1143 }
1144 }
1145
1146 /* Set the new state. */
1147 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1148
1149 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1150 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1151 util_format_is_pure_integer(state->cbufs[0]->format);
1152 rctx->framebuffer.compressed_cb_mask = 0;
1153 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1154 state->cbufs[0] && state->cbufs[1] &&
1155 state->cbufs[0]->texture->nr_samples > 1 &&
1156 state->cbufs[1]->texture->nr_samples <= 1;
1157 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1158
1159 /* Colorbuffers. */
1160 for (i = 0; i < state->nr_cbufs; i++) {
1161 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1162 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1163 rctx->framebuffer.is_msaa_resolve &&
1164 i == 1;
1165
1166 surf = (struct r600_surface*)state->cbufs[i];
1167 if (!surf)
1168 continue;
1169
1170 rtex = (struct r600_texture*)surf->base.texture;
1171 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1172
1173 if (!surf->color_initialized || force_cmask_fmask) {
1174 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1175 if (force_cmask_fmask) {
1176 /* re-initialize later without compression */
1177 surf->color_initialized = false;
1178 }
1179 }
1180
1181 if (!surf->export_16bpc) {
1182 rctx->framebuffer.export_16bpc = false;
1183 }
1184
1185 if (rtex->fmask.size && rtex->cmask.size) {
1186 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1187 }
1188 }
1189
1190 /* Update alpha-test state dependencies.
1191 * Alpha-test is done on the first colorbuffer only. */
1192 if (state->nr_cbufs) {
1193 bool alphatest_bypass = false;
1194
1195 surf = (struct r600_surface*)state->cbufs[0];
1196 if (surf) {
1197 alphatest_bypass = surf->alphatest_bypass;
1198 }
1199
1200 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1201 rctx->alphatest_state.bypass = alphatest_bypass;
1202 rctx->alphatest_state.atom.dirty = true;
1203 }
1204 }
1205
1206 /* ZS buffer. */
1207 if (state->zsbuf) {
1208 surf = (struct r600_surface*)state->zsbuf;
1209
1210 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1211
1212 if (!surf->depth_initialized) {
1213 r600_init_depth_surface(rctx, surf);
1214 }
1215
1216 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1217 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1218 rctx->poly_offset_state.atom.dirty = true;
1219 }
1220
1221 if (rctx->db_state.rsurf != surf) {
1222 rctx->db_state.rsurf = surf;
1223 rctx->db_state.atom.dirty = true;
1224 rctx->db_misc_state.atom.dirty = true;
1225 }
1226 } else if (rctx->db_state.rsurf) {
1227 rctx->db_state.rsurf = NULL;
1228 rctx->db_state.atom.dirty = true;
1229 rctx->db_misc_state.atom.dirty = true;
1230 }
1231
1232 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1233 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1234 rctx->cb_misc_state.atom.dirty = true;
1235 }
1236
1237 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1238 rctx->alphatest_state.bypass = false;
1239 rctx->alphatest_state.atom.dirty = true;
1240 }
1241
1242 /* Calculate the CS size. */
1243 rctx->framebuffer.atom.num_dw =
1244 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1245
1246 if (rctx->framebuffer.state.nr_cbufs) {
1247 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1248 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1249 }
1250 if (rctx->framebuffer.state.zsbuf) {
1251 rctx->framebuffer.atom.num_dw += 16;
1252 } else if (rctx->screen->b.info.drm_minor >= 18) {
1253 rctx->framebuffer.atom.num_dw += 3;
1254 }
1255 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1256 rctx->framebuffer.atom.num_dw += 2;
1257 }
1258
1259 rctx->framebuffer.atom.dirty = true;
1260 }
1261
1262 static uint32_t sample_locs_2x[] = {
1263 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1264 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1265 };
1266 static unsigned max_dist_2x = 4;
1267
1268 static uint32_t sample_locs_4x[] = {
1269 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1270 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1271 };
1272 static unsigned max_dist_4x = 6;
1273 static uint32_t sample_locs_8x[] = {
1274 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1275 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1276 };
1277 static unsigned max_dist_8x = 7;
1278
1279 static void r600_get_sample_position(struct pipe_context *ctx,
1280 unsigned sample_count,
1281 unsigned sample_index,
1282 float *out_value)
1283 {
1284 int offset, index;
1285 struct {
1286 int idx:4;
1287 } val;
1288 switch (sample_count) {
1289 case 1:
1290 default:
1291 out_value[0] = out_value[1] = 0.5;
1292 break;
1293 case 2:
1294 offset = 4 * (sample_index * 2);
1295 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1296 out_value[0] = (float)(val.idx + 8) / 16.0f;
1297 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1298 out_value[1] = (float)(val.idx + 8) / 16.0f;
1299 break;
1300 case 4:
1301 offset = 4 * (sample_index * 2);
1302 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1303 out_value[0] = (float)(val.idx + 8) / 16.0f;
1304 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1305 out_value[1] = (float)(val.idx + 8) / 16.0f;
1306 break;
1307 case 8:
1308 offset = 4 * (sample_index % 4 * 2);
1309 index = (sample_index / 4);
1310 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1311 out_value[0] = (float)(val.idx + 8) / 16.0f;
1312 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1313 out_value[1] = (float)(val.idx + 8) / 16.0f;
1314 break;
1315 }
1316 }
1317
1318 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1319 {
1320 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1321 unsigned max_dist = 0;
1322
1323 if (rctx->b.family == CHIP_R600) {
1324 switch (nr_samples) {
1325 default:
1326 nr_samples = 0;
1327 break;
1328 case 2:
1329 r600_write_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1330 max_dist = max_dist_2x;
1331 break;
1332 case 4:
1333 r600_write_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1334 max_dist = max_dist_4x;
1335 break;
1336 case 8:
1337 r600_write_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1338 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1339 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1340 max_dist = max_dist_8x;
1341 break;
1342 }
1343 } else {
1344 switch (nr_samples) {
1345 default:
1346 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1347 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1348 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1349 nr_samples = 0;
1350 break;
1351 case 2:
1352 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1353 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1354 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1355 max_dist = max_dist_2x;
1356 break;
1357 case 4:
1358 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1359 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1360 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1361 max_dist = max_dist_4x;
1362 break;
1363 case 8:
1364 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1365 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1366 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1367 max_dist = max_dist_8x;
1368 break;
1369 }
1370 }
1371
1372 if (nr_samples > 1) {
1373 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1374 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1375 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1376 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1377 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1378 } else {
1379 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1380 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1381 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1382 }
1383 }
1384
1385 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1386 {
1387 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1388 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1389 unsigned nr_cbufs = state->nr_cbufs;
1390 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1391 unsigned i, sbu = 0;
1392
1393 /* Colorbuffers. */
1394 r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1395 for (i = 0; i < nr_cbufs; i++) {
1396 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1397 }
1398 /* set CB_COLOR1_INFO for possible dual-src blending */
1399 if (i == 1 && cb[0]) {
1400 radeon_emit(cs, cb[0]->cb_color_info);
1401 i++;
1402 }
1403 for (; i < 8; i++) {
1404 radeon_emit(cs, 0);
1405 }
1406
1407 if (nr_cbufs) {
1408 for (i = 0; i < nr_cbufs; i++) {
1409 unsigned reloc;
1410
1411 if (!cb[i])
1412 continue;
1413
1414 /* COLOR_BASE */
1415 r600_write_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1416
1417 reloc = r600_context_bo_reloc(&rctx->b,
1418 &rctx->b.rings.gfx,
1419 (struct r600_resource*)cb[i]->base.texture,
1420 RADEON_USAGE_READWRITE,
1421 cb[i]->base.texture->nr_samples > 1 ?
1422 RADEON_PRIO_COLOR_BUFFER_MSAA :
1423 RADEON_PRIO_COLOR_BUFFER);
1424 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1425 radeon_emit(cs, reloc);
1426
1427 /* FMASK */
1428 r600_write_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1429
1430 reloc = r600_context_bo_reloc(&rctx->b,
1431 &rctx->b.rings.gfx,
1432 cb[i]->cb_buffer_fmask,
1433 RADEON_USAGE_READWRITE,
1434 cb[i]->base.texture->nr_samples > 1 ?
1435 RADEON_PRIO_COLOR_BUFFER_MSAA :
1436 RADEON_PRIO_COLOR_BUFFER);
1437 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1438 radeon_emit(cs, reloc);
1439
1440 /* CMASK */
1441 r600_write_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1442
1443 reloc = r600_context_bo_reloc(&rctx->b,
1444 &rctx->b.rings.gfx,
1445 cb[i]->cb_buffer_cmask,
1446 RADEON_USAGE_READWRITE,
1447 cb[i]->base.texture->nr_samples > 1 ?
1448 RADEON_PRIO_COLOR_BUFFER_MSAA :
1449 RADEON_PRIO_COLOR_BUFFER);
1450 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1451 radeon_emit(cs, reloc);
1452 }
1453
1454 r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1455 for (i = 0; i < nr_cbufs; i++) {
1456 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1457 }
1458
1459 r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1460 for (i = 0; i < nr_cbufs; i++) {
1461 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1462 }
1463
1464 r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1465 for (i = 0; i < nr_cbufs; i++) {
1466 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1467 }
1468
1469 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1470 }
1471
1472 /* SURFACE_BASE_UPDATE */
1473 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1474 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1475 radeon_emit(cs, sbu);
1476 sbu = 0;
1477 }
1478
1479 /* Zbuffer. */
1480 if (state->zsbuf) {
1481 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1482 unsigned reloc = r600_context_bo_reloc(&rctx->b,
1483 &rctx->b.rings.gfx,
1484 (struct r600_resource*)state->zsbuf->texture,
1485 RADEON_USAGE_READWRITE,
1486 surf->base.texture->nr_samples > 1 ?
1487 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1488 RADEON_PRIO_DEPTH_BUFFER);
1489
1490 r600_write_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1491 surf->pa_su_poly_offset_db_fmt_cntl);
1492
1493 r600_write_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1494 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1495 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1496 r600_write_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1497 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1498 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1499
1500 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1501 radeon_emit(cs, reloc);
1502
1503 r600_write_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1504
1505 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1506 } else if (rctx->screen->b.info.drm_minor >= 18) {
1507 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1508 * Older kernels are out of luck. */
1509 r600_write_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1510 }
1511
1512 /* SURFACE_BASE_UPDATE */
1513 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1514 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1515 radeon_emit(cs, sbu);
1516 sbu = 0;
1517 }
1518
1519 /* Framebuffer dimensions. */
1520 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1521 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1522 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1523 radeon_emit(cs, S_028244_BR_X(state->width) |
1524 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1525
1526 if (rctx->framebuffer.is_msaa_resolve) {
1527 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1528 } else {
1529 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1530 * will assure that the alpha-test will work even if there is
1531 * no colorbuffer bound. */
1532 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1533 (1ull << MAX2(nr_cbufs, 1)) - 1);
1534 }
1535
1536 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1537 }
1538
1539 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1540 {
1541 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1542 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1543
1544 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1545 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1546 if (rctx->b.chip_class == R600) {
1547 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1548 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1549 } else {
1550 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1551 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1552 }
1553 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1554 } else {
1555 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1556 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1557 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1558
1559 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1560 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1561 /* Always enable the first color output to make sure alpha-test works even without one. */
1562 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1563 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1564 a->cb_color_control |
1565 S_028808_MULTIWRITE_ENABLE(multiwrite));
1566 }
1567 }
1568
1569 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1570 {
1571 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1572 struct r600_db_state *a = (struct r600_db_state*)atom;
1573
1574 if (a->rsurf && a->rsurf->db_htile_surface) {
1575 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1576 unsigned reloc_idx;
1577
1578 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1579 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1580 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1581 reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer,
1582 RADEON_USAGE_READWRITE, RADEON_PRIO_DEPTH_META);
1583 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1584 cs->buf[cs->cdw++] = reloc_idx;
1585 } else {
1586 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1587 }
1588 }
1589
1590 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1591 {
1592 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1593 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1594 unsigned db_render_control = 0;
1595 unsigned db_render_override =
1596 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1597 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1598
1599 if (a->occlusion_query_enabled) {
1600 if (rctx->b.chip_class >= R700) {
1601 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1602 }
1603 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1604 }
1605 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1606 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1607 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1608 /* This is to fix a lockup when hyperz and alpha test are enabled at
1609 * the same time somehow GPU get confuse on which order to pick for
1610 * z test
1611 */
1612 if (rctx->alphatest_state.sx_alpha_test_control) {
1613 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1614 }
1615 } else {
1616 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1617 }
1618 if (a->flush_depthstencil_through_cb) {
1619 assert(a->copy_depth || a->copy_stencil);
1620
1621 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1622 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1623 S_028D0C_COPY_CENTROID(1) |
1624 S_028D0C_COPY_SAMPLE(a->copy_sample);
1625 } else if (a->flush_depthstencil_in_place) {
1626 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(1) |
1627 S_028D0C_STENCIL_COMPRESS_DISABLE(1);
1628 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1629 }
1630 if (a->htile_clear) {
1631 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1632 }
1633
1634 /* RV770 workaround for a hang with 8x MSAA. */
1635 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1636 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
1637 }
1638
1639 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1640 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1641 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1642 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1643 }
1644
1645 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1646 {
1647 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1648 struct r600_config_state *a = (struct r600_config_state*)atom;
1649
1650 r600_write_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1651 r600_write_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1652 }
1653
1654 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1655 {
1656 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1657 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1658
1659 while (dirty_mask) {
1660 struct pipe_vertex_buffer *vb;
1661 struct r600_resource *rbuffer;
1662 unsigned offset;
1663 unsigned buffer_index = u_bit_scan(&dirty_mask);
1664
1665 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1666 rbuffer = (struct r600_resource*)vb->buffer;
1667 assert(rbuffer);
1668
1669 offset = vb->buffer_offset;
1670
1671 /* fetch resources start at index 320 */
1672 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1673 radeon_emit(cs, (320 + buffer_index) * 7);
1674 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1675 radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1676 radeon_emit(cs, /* RESOURCEi_WORD2 */
1677 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1678 S_038008_STRIDE(vb->stride));
1679 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1680 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1681 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1682 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1683
1684 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1685 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1686 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1687 }
1688 }
1689
1690 static void r600_emit_constant_buffers(struct r600_context *rctx,
1691 struct r600_constbuf_state *state,
1692 unsigned buffer_id_base,
1693 unsigned reg_alu_constbuf_size,
1694 unsigned reg_alu_const_cache)
1695 {
1696 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1697 uint32_t dirty_mask = state->dirty_mask;
1698
1699 while (dirty_mask) {
1700 struct pipe_constant_buffer *cb;
1701 struct r600_resource *rbuffer;
1702 unsigned offset;
1703 unsigned buffer_index = ffs(dirty_mask) - 1;
1704 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1705 cb = &state->cb[buffer_index];
1706 rbuffer = (struct r600_resource*)cb->buffer;
1707 assert(rbuffer);
1708
1709 offset = cb->buffer_offset;
1710
1711 if (!gs_ring_buffer) {
1712 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1713 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1714 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1715 }
1716
1717 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1718 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1719 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1720
1721 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1722 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1723 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1724 radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1725 radeon_emit(cs, /* RESOURCEi_WORD2 */
1726 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1727 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1728 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1729 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1730 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1731 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1732
1733 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1734 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1735 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1736
1737 dirty_mask &= ~(1 << buffer_index);
1738 }
1739 state->dirty_mask = 0;
1740 }
1741
1742 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1743 {
1744 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
1745 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1746 R_028980_ALU_CONST_CACHE_VS_0);
1747 }
1748
1749 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1750 {
1751 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
1752 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1753 R_0289C0_ALU_CONST_CACHE_GS_0);
1754 }
1755
1756 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1757 {
1758 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
1759 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1760 R_028940_ALU_CONST_CACHE_PS_0);
1761 }
1762
1763 static void r600_emit_sampler_views(struct r600_context *rctx,
1764 struct r600_samplerview_state *state,
1765 unsigned resource_id_base)
1766 {
1767 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1768 uint32_t dirty_mask = state->dirty_mask;
1769
1770 while (dirty_mask) {
1771 struct r600_pipe_sampler_view *rview;
1772 unsigned resource_index = u_bit_scan(&dirty_mask);
1773 unsigned reloc;
1774
1775 rview = state->views[resource_index];
1776 assert(rview);
1777
1778 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1779 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1780 radeon_emit_array(cs, rview->tex_resource_words, 7);
1781
1782 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
1783 RADEON_USAGE_READ,
1784 rview->tex_resource->b.b.nr_samples > 1 ?
1785 RADEON_PRIO_SHADER_TEXTURE_MSAA :
1786 RADEON_PRIO_SHADER_TEXTURE_RO);
1787 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1788 radeon_emit(cs, reloc);
1789 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1790 radeon_emit(cs, reloc);
1791 }
1792 state->dirty_mask = 0;
1793 }
1794
1795 /* Resource IDs:
1796 * PS: 0 .. +160
1797 * VS: 160 .. +160
1798 * FS: 320 .. +16
1799 * GS: 336 .. +160
1800 */
1801
1802 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1803 {
1804 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
1805 }
1806
1807 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1808 {
1809 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
1810 }
1811
1812 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1813 {
1814 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
1815 }
1816
1817 static void r600_emit_sampler_states(struct r600_context *rctx,
1818 struct r600_textures_info *texinfo,
1819 unsigned resource_id_base,
1820 unsigned border_color_reg)
1821 {
1822 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1823 uint32_t dirty_mask = texinfo->states.dirty_mask;
1824
1825 while (dirty_mask) {
1826 struct r600_pipe_sampler_state *rstate;
1827 struct r600_pipe_sampler_view *rview;
1828 unsigned i = u_bit_scan(&dirty_mask);
1829
1830 rstate = texinfo->states.states[i];
1831 assert(rstate);
1832 rview = texinfo->views.views[i];
1833
1834 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1835 * filtering between layers.
1836 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1837 */
1838 if (rview) {
1839 enum pipe_texture_target target = rview->base.texture->target;
1840 if (target == PIPE_TEXTURE_1D_ARRAY ||
1841 target == PIPE_TEXTURE_2D_ARRAY) {
1842 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1843 texinfo->is_array_sampler[i] = true;
1844 } else {
1845 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1846 texinfo->is_array_sampler[i] = false;
1847 }
1848 }
1849
1850 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1851 radeon_emit(cs, (resource_id_base + i) * 3);
1852 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1853
1854 if (rstate->border_color_use) {
1855 unsigned offset;
1856
1857 offset = border_color_reg;
1858 offset += i * 16;
1859 r600_write_config_reg_seq(cs, offset, 4);
1860 radeon_emit_array(cs, rstate->border_color.ui, 4);
1861 }
1862 }
1863 texinfo->states.dirty_mask = 0;
1864 }
1865
1866 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1867 {
1868 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1869 }
1870
1871 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1872 {
1873 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1874 }
1875
1876 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1877 {
1878 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1879 }
1880
1881 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1882 {
1883 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1884 unsigned tmp;
1885
1886 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1887 S_009508_SYNC_GRADIENT(1) |
1888 S_009508_SYNC_WALKER(1) |
1889 S_009508_SYNC_ALIGNER(1);
1890 if (!rctx->seamless_cube_map.enabled) {
1891 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1892 }
1893 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1894 }
1895
1896 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1897 {
1898 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1899 uint8_t mask = s->sample_mask;
1900
1901 r600_write_context_reg(rctx->b.rings.gfx.cs, R_028C48_PA_SC_AA_MASK,
1902 mask | (mask << 8) | (mask << 16) | (mask << 24));
1903 }
1904
1905 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1906 {
1907 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1908 struct r600_cso_state *state = (struct r600_cso_state*)a;
1909 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1910
1911 r600_write_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1912 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1913 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer,
1914 RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
1915 }
1916
1917 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1918 {
1919 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1920 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1921
1922 uint32_t v2 = 0, primid = 0;
1923
1924 if (state->geom_enable) {
1925 uint32_t cut_val;
1926
1927 if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 128)
1928 cut_val = V_028A40_GS_CUT_128;
1929 else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 256)
1930 cut_val = V_028A40_GS_CUT_256;
1931 else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 512)
1932 cut_val = V_028A40_GS_CUT_512;
1933 else
1934 cut_val = V_028A40_GS_CUT_1024;
1935
1936 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1937 S_028A40_CUT_MODE(cut_val);
1938
1939 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1940 primid = 1;
1941 }
1942
1943 r600_write_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1944 r600_write_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
1945 }
1946
1947 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1948 {
1949 struct pipe_screen *screen = rctx->b.b.screen;
1950 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1951 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
1952 struct r600_resource *rbuffer;
1953
1954 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1955 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1956 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1957
1958 if (state->enable) {
1959 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
1960 r600_write_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
1961 (r600_resource_va(screen, &rbuffer->b.b)) >> 8);
1962 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1963 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1964 RADEON_USAGE_READWRITE,
1965 RADEON_PRIO_SHADER_RESOURCE_RW));
1966 r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1967 state->esgs_ring.buffer_size >> 8);
1968
1969 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
1970 r600_write_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
1971 (r600_resource_va(screen, &rbuffer->b.b)) >> 8);
1972 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1973 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1974 RADEON_USAGE_READWRITE,
1975 RADEON_PRIO_SHADER_RESOURCE_RW));
1976 r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
1977 state->gsvs_ring.buffer_size >> 8);
1978 } else {
1979 r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
1980 r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
1981 }
1982
1983 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1984 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1985 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1986 }
1987
1988 /* Adjust GPR allocation on R6xx/R7xx */
1989 bool r600_adjust_gprs(struct r600_context *rctx)
1990 {
1991 unsigned num_ps_gprs = rctx->ps_shader->current->shader.bc.ngpr;
1992 unsigned num_vs_gprs, num_es_gprs, num_gs_gprs;
1993 unsigned new_num_ps_gprs = num_ps_gprs;
1994 unsigned new_num_vs_gprs, new_num_es_gprs, new_num_gs_gprs;
1995 unsigned cur_num_ps_gprs = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
1996 unsigned cur_num_vs_gprs = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
1997 unsigned cur_num_gs_gprs = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
1998 unsigned cur_num_es_gprs = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
1999 unsigned def_num_ps_gprs = rctx->default_ps_gprs;
2000 unsigned def_num_vs_gprs = rctx->default_vs_gprs;
2001 unsigned def_num_gs_gprs = 0;
2002 unsigned def_num_es_gprs = 0;
2003 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2004 /* hardware will reserve twice num_clause_temp_gprs */
2005 unsigned max_gprs = def_num_gs_gprs + def_num_es_gprs + def_num_ps_gprs + def_num_vs_gprs + def_num_clause_temp_gprs * 2;
2006 unsigned tmp, tmp2;
2007
2008 if (rctx->gs_shader) {
2009 num_es_gprs = rctx->vs_shader->current->shader.bc.ngpr;
2010 num_gs_gprs = rctx->gs_shader->current->shader.bc.ngpr;
2011 num_vs_gprs = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2012 } else {
2013 num_es_gprs = 0;
2014 num_gs_gprs = 0;
2015 num_vs_gprs = rctx->vs_shader->current->shader.bc.ngpr;
2016 }
2017 new_num_vs_gprs = num_vs_gprs;
2018 new_num_es_gprs = num_es_gprs;
2019 new_num_gs_gprs = num_gs_gprs;
2020
2021 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2022 if (new_num_ps_gprs > cur_num_ps_gprs || new_num_vs_gprs > cur_num_vs_gprs ||
2023 new_num_es_gprs > cur_num_es_gprs || new_num_gs_gprs > cur_num_gs_gprs) {
2024 /* try to use switch back to default */
2025 if (new_num_ps_gprs > def_num_ps_gprs || new_num_vs_gprs > def_num_vs_gprs ||
2026 new_num_gs_gprs > def_num_gs_gprs || new_num_es_gprs > def_num_es_gprs) {
2027 /* always privilege vs stage so that at worst we have the
2028 * pixel stage producing wrong output (not the vertex
2029 * stage) */
2030 new_num_ps_gprs = max_gprs - ((new_num_vs_gprs - new_num_es_gprs - new_num_gs_gprs) + def_num_clause_temp_gprs * 2);
2031 new_num_vs_gprs = num_vs_gprs;
2032 new_num_gs_gprs = num_gs_gprs;
2033 new_num_es_gprs = num_es_gprs;
2034 } else {
2035 new_num_ps_gprs = def_num_ps_gprs;
2036 new_num_vs_gprs = def_num_vs_gprs;
2037 new_num_es_gprs = def_num_es_gprs;
2038 new_num_gs_gprs = def_num_gs_gprs;
2039 }
2040 } else {
2041 return true;
2042 }
2043
2044 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2045 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2046 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2047 * it will lockup. So in this case just discard the draw command
2048 * and don't change the current gprs repartitions.
2049 */
2050 if (num_ps_gprs > new_num_ps_gprs || num_vs_gprs > new_num_vs_gprs ||
2051 num_gs_gprs > new_num_gs_gprs || num_es_gprs > new_num_es_gprs) {
2052 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2053 "for a combined maximum of %d\n",
2054 num_ps_gprs, num_vs_gprs, num_es_gprs, num_gs_gprs, max_gprs);
2055 return false;
2056 }
2057
2058 /* in some case we endup recomputing the current value */
2059 tmp = S_008C04_NUM_PS_GPRS(new_num_ps_gprs) |
2060 S_008C04_NUM_VS_GPRS(new_num_vs_gprs) |
2061 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2062
2063 tmp2 = S_008C08_NUM_ES_GPRS(new_num_es_gprs) |
2064 S_008C08_NUM_GS_GPRS(new_num_gs_gprs);
2065 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2066 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2067 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2068 rctx->config_state.atom.dirty = true;
2069 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2070 }
2071 return true;
2072 }
2073
2074 void r600_init_atom_start_cs(struct r600_context *rctx)
2075 {
2076 int ps_prio;
2077 int vs_prio;
2078 int gs_prio;
2079 int es_prio;
2080 int num_ps_gprs;
2081 int num_vs_gprs;
2082 int num_gs_gprs;
2083 int num_es_gprs;
2084 int num_temp_gprs;
2085 int num_ps_threads;
2086 int num_vs_threads;
2087 int num_gs_threads;
2088 int num_es_threads;
2089 int num_ps_stack_entries;
2090 int num_vs_stack_entries;
2091 int num_gs_stack_entries;
2092 int num_es_stack_entries;
2093 enum radeon_family family;
2094 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2095 uint32_t tmp;
2096
2097 r600_init_command_buffer(cb, 256);
2098
2099 /* R6xx requires this packet at the start of each command buffer */
2100 if (rctx->b.chip_class == R600) {
2101 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2102 r600_store_value(cb, 0);
2103 }
2104 /* All asics require this one */
2105 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2106 r600_store_value(cb, 0x80000000);
2107 r600_store_value(cb, 0x80000000);
2108
2109 /* We're setting config registers here. */
2110 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2111 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2112
2113 family = rctx->b.family;
2114 ps_prio = 0;
2115 vs_prio = 1;
2116 gs_prio = 2;
2117 es_prio = 3;
2118 switch (family) {
2119 case CHIP_R600:
2120 num_ps_gprs = 192;
2121 num_vs_gprs = 56;
2122 num_temp_gprs = 4;
2123 num_gs_gprs = 0;
2124 num_es_gprs = 0;
2125 num_ps_threads = 136;
2126 num_vs_threads = 48;
2127 num_gs_threads = 4;
2128 num_es_threads = 4;
2129 num_ps_stack_entries = 128;
2130 num_vs_stack_entries = 128;
2131 num_gs_stack_entries = 0;
2132 num_es_stack_entries = 0;
2133 break;
2134 case CHIP_RV630:
2135 case CHIP_RV635:
2136 num_ps_gprs = 84;
2137 num_vs_gprs = 36;
2138 num_temp_gprs = 4;
2139 num_gs_gprs = 0;
2140 num_es_gprs = 0;
2141 num_ps_threads = 144;
2142 num_vs_threads = 40;
2143 num_gs_threads = 4;
2144 num_es_threads = 4;
2145 num_ps_stack_entries = 40;
2146 num_vs_stack_entries = 40;
2147 num_gs_stack_entries = 32;
2148 num_es_stack_entries = 16;
2149 break;
2150 case CHIP_RV610:
2151 case CHIP_RV620:
2152 case CHIP_RS780:
2153 case CHIP_RS880:
2154 default:
2155 num_ps_gprs = 84;
2156 num_vs_gprs = 36;
2157 num_temp_gprs = 4;
2158 num_gs_gprs = 0;
2159 num_es_gprs = 0;
2160 num_ps_threads = 136;
2161 num_vs_threads = 48;
2162 num_gs_threads = 4;
2163 num_es_threads = 4;
2164 num_ps_stack_entries = 40;
2165 num_vs_stack_entries = 40;
2166 num_gs_stack_entries = 32;
2167 num_es_stack_entries = 16;
2168 break;
2169 case CHIP_RV670:
2170 num_ps_gprs = 144;
2171 num_vs_gprs = 40;
2172 num_temp_gprs = 4;
2173 num_gs_gprs = 0;
2174 num_es_gprs = 0;
2175 num_ps_threads = 136;
2176 num_vs_threads = 48;
2177 num_gs_threads = 4;
2178 num_es_threads = 4;
2179 num_ps_stack_entries = 40;
2180 num_vs_stack_entries = 40;
2181 num_gs_stack_entries = 32;
2182 num_es_stack_entries = 16;
2183 break;
2184 case CHIP_RV770:
2185 num_ps_gprs = 130;
2186 num_vs_gprs = 56;
2187 num_temp_gprs = 4;
2188 num_gs_gprs = 31;
2189 num_es_gprs = 31;
2190 num_ps_threads = 180;
2191 num_vs_threads = 60;
2192 num_gs_threads = 4;
2193 num_es_threads = 4;
2194 num_ps_stack_entries = 128;
2195 num_vs_stack_entries = 128;
2196 num_gs_stack_entries = 128;
2197 num_es_stack_entries = 128;
2198 break;
2199 case CHIP_RV730:
2200 case CHIP_RV740:
2201 num_ps_gprs = 84;
2202 num_vs_gprs = 36;
2203 num_temp_gprs = 4;
2204 num_gs_gprs = 0;
2205 num_es_gprs = 0;
2206 num_ps_threads = 180;
2207 num_vs_threads = 60;
2208 num_gs_threads = 4;
2209 num_es_threads = 4;
2210 num_ps_stack_entries = 128;
2211 num_vs_stack_entries = 128;
2212 num_gs_stack_entries = 0;
2213 num_es_stack_entries = 0;
2214 break;
2215 case CHIP_RV710:
2216 num_ps_gprs = 192;
2217 num_vs_gprs = 56;
2218 num_temp_gprs = 4;
2219 num_gs_gprs = 0;
2220 num_es_gprs = 0;
2221 num_ps_threads = 136;
2222 num_vs_threads = 48;
2223 num_gs_threads = 4;
2224 num_es_threads = 4;
2225 num_ps_stack_entries = 128;
2226 num_vs_stack_entries = 128;
2227 num_gs_stack_entries = 0;
2228 num_es_stack_entries = 0;
2229 break;
2230 }
2231
2232 rctx->default_ps_gprs = num_ps_gprs;
2233 rctx->default_vs_gprs = num_vs_gprs;
2234 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2235
2236 /* SQ_CONFIG */
2237 tmp = 0;
2238 switch (family) {
2239 case CHIP_RV610:
2240 case CHIP_RV620:
2241 case CHIP_RS780:
2242 case CHIP_RS880:
2243 case CHIP_RV710:
2244 break;
2245 default:
2246 tmp |= S_008C00_VC_ENABLE(1);
2247 break;
2248 }
2249 tmp |= S_008C00_DX9_CONSTS(0);
2250 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2251 tmp |= S_008C00_PS_PRIO(ps_prio);
2252 tmp |= S_008C00_VS_PRIO(vs_prio);
2253 tmp |= S_008C00_GS_PRIO(gs_prio);
2254 tmp |= S_008C00_ES_PRIO(es_prio);
2255 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2256
2257 /* SQ_GPR_RESOURCE_MGMT_2 */
2258 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2259 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2260 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2261 r600_store_value(cb, tmp);
2262
2263 /* SQ_THREAD_RESOURCE_MGMT */
2264 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2265 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2266 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2267 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2268 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2269
2270 /* SQ_STACK_RESOURCE_MGMT_1 */
2271 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2272 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2273 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2274
2275 /* SQ_STACK_RESOURCE_MGMT_2 */
2276 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2277 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2278 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2279
2280 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2281
2282 if (rctx->b.chip_class >= R700) {
2283 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2284 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2285 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2286 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2287 } else {
2288 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2289 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2290 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2291 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2292 }
2293 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2294 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2295 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2296 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2297 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2298 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2299 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2300 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2301 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2302 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2303
2304 /* to avoid GPU doing any preloading of constant from random address */
2305 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2306 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2307 r600_store_value(cb, 0);
2308 r600_store_value(cb, 0);
2309 r600_store_value(cb, 0);
2310 r600_store_value(cb, 0);
2311 r600_store_value(cb, 0);
2312 r600_store_value(cb, 0);
2313 r600_store_value(cb, 0);
2314 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2315 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2316 r600_store_value(cb, 0);
2317 r600_store_value(cb, 0);
2318 r600_store_value(cb, 0);
2319 r600_store_value(cb, 0);
2320 r600_store_value(cb, 0);
2321 r600_store_value(cb, 0);
2322 r600_store_value(cb, 0);
2323
2324 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2325 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2326 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2327 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2328 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2329 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2330 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2331 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2332 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2333 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2334 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2335 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2336 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2337 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2338
2339 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2340 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2341 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2342
2343 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2344 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2345 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2346
2347 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2348
2349 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2350
2351 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2352
2353 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2354 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2355 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2356 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2357
2358 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2359 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2360 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2361 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2362
2363 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2364 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2365
2366 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2367 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2368 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2369 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2370 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2371
2372 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * 16);
2373 for (tmp = 0; tmp < 16; tmp++) {
2374 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2375 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2376 }
2377
2378 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2379
2380 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2381 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2382
2383 if (rctx->b.chip_class >= R700) {
2384 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2385 }
2386
2387 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2388 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2389 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2390 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2391 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2392
2393 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2394 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2395 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2396
2397 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2398 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2399 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2400
2401 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2402 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2403 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2404 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2405 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2406 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2407
2408 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2409
2410 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2411 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2412 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2413
2414 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2415
2416 if (rctx->b.chip_class == R700)
2417 r600_store_context_reg(cb, R_028350_SX_MISC, 0);
2418 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2419 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2420
2421 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2422 if (rctx->screen->b.has_streamout) {
2423 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2424 }
2425
2426 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2427 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2428 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2429 }
2430
2431 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2432 {
2433 struct r600_context *rctx = (struct r600_context *)ctx;
2434 struct r600_command_buffer *cb = &shader->command_buffer;
2435 struct r600_shader *rshader = &shader->shader;
2436 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2437 int pos_index = -1, face_index = -1;
2438 unsigned tmp, sid, ufi = 0;
2439 int need_linear = 0;
2440 unsigned z_export = 0, stencil_export = 0;
2441 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2442
2443 if (!cb->buf) {
2444 r600_init_command_buffer(cb, 64);
2445 } else {
2446 cb->num_dw = 0;
2447 }
2448
2449 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2450 for (i = 0; i < rshader->ninput; i++) {
2451 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2452 pos_index = i;
2453 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2454 face_index = i;
2455
2456 sid = rshader->input[i].spi_sid;
2457
2458 tmp = S_028644_SEMANTIC(sid);
2459
2460 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2461 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2462 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2463 rctx->rasterizer && rctx->rasterizer->flatshade))
2464 tmp |= S_028644_FLAT_SHADE(1);
2465
2466 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2467 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2468 tmp |= S_028644_PT_SPRITE_TEX(1);
2469 }
2470
2471 if (rshader->input[i].centroid)
2472 tmp |= S_028644_SEL_CENTROID(1);
2473
2474 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2475 need_linear = 1;
2476 tmp |= S_028644_SEL_LINEAR(1);
2477 }
2478
2479 r600_store_value(cb, tmp);
2480 }
2481
2482 db_shader_control = 0;
2483 for (i = 0; i < rshader->noutput; i++) {
2484 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2485 z_export = 1;
2486 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2487 stencil_export = 1;
2488 }
2489 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2490 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2491 if (rshader->uses_kill)
2492 db_shader_control |= S_02880C_KILL_ENABLE(1);
2493
2494 exports_ps = 0;
2495 for (i = 0; i < rshader->noutput; i++) {
2496 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2497 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2498 exports_ps |= 1;
2499 }
2500 }
2501 num_cout = rshader->nr_ps_color_exports;
2502 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2503 if (!exports_ps) {
2504 /* always at least export 1 component per pixel */
2505 exports_ps = 2;
2506 }
2507
2508 shader->nr_ps_color_outputs = num_cout;
2509
2510 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2511 S_0286CC_PERSP_GRADIENT_ENA(1)|
2512 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2513 spi_input_z = 0;
2514 if (pos_index != -1) {
2515 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2516 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2517 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2518 S_0286CC_BARYC_SAMPLE_CNTL(1));
2519 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2520 }
2521
2522 spi_ps_in_control_1 = 0;
2523 if (face_index != -1) {
2524 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2525 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2526 }
2527
2528 /* HW bug in original R600 */
2529 if (rctx->b.family == CHIP_R600)
2530 ufi = 1;
2531
2532 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2533 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2534 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2535
2536 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2537
2538 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2539 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2540 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2541 S_028850_STACK_SIZE(rshader->bc.nstack) |
2542 S_028850_UNCACHED_FIRST_INST(ufi));
2543 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2544
2545 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2546 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2547
2548 /* only set some bits here, the other bits are set in the dsa state */
2549 shader->db_shader_control = db_shader_control;
2550 shader->ps_depth_export = z_export | stencil_export;
2551
2552 shader->sprite_coord_enable = sprite_coord_enable;
2553 if (rctx->rasterizer)
2554 shader->flatshade = rctx->rasterizer->flatshade;
2555 }
2556
2557 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2558 {
2559 struct r600_command_buffer *cb = &shader->command_buffer;
2560 struct r600_shader *rshader = &shader->shader;
2561 unsigned spi_vs_out_id[10] = {};
2562 unsigned i, tmp, nparams = 0;
2563
2564 for (i = 0; i < rshader->noutput; i++) {
2565 if (rshader->output[i].spi_sid) {
2566 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2567 spi_vs_out_id[nparams / 4] |= tmp;
2568 nparams++;
2569 }
2570 }
2571
2572 r600_init_command_buffer(cb, 32);
2573
2574 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2575 for (i = 0; i < 10; i++) {
2576 r600_store_value(cb, spi_vs_out_id[i]);
2577 }
2578
2579 /* Certain attributes (position, psize, etc.) don't count as params.
2580 * VS is required to export at least one param and r600_shader_from_tgsi()
2581 * takes care of adding a dummy export.
2582 */
2583 if (nparams < 1)
2584 nparams = 1;
2585
2586 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2587 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2588 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2589 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2590 S_028868_STACK_SIZE(rshader->bc.nstack));
2591 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2592 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2593
2594 shader->pa_cl_vs_out_cntl =
2595 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2596 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2597 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2598 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2599 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2600 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2601 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2602 }
2603
2604 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2605 {
2606 struct r600_context *rctx = (struct r600_context *)ctx;
2607 struct r600_command_buffer *cb = &shader->command_buffer;
2608 struct r600_shader *rshader = &shader->shader;
2609 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2610 unsigned gsvs_itemsize =
2611 (cp_shader->ring_item_size * rshader->gs_max_out_vertices) >> 2;
2612
2613 r600_init_command_buffer(cb, 64);
2614
2615 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2616 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2617
2618 if (rctx->b.chip_class >= R700) {
2619 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2620 S_028B38_MAX_VERT_OUT(rshader->gs_max_out_vertices));
2621 }
2622 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2623 r600_conv_prim_to_gs_out(rshader->gs_output_prim));
2624
2625 r600_store_context_reg_seq(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE, 4);
2626 r600_store_value(cb, cp_shader->ring_item_size >> 2);
2627 r600_store_value(cb, 0);
2628 r600_store_value(cb, 0);
2629 r600_store_value(cb, 0);
2630
2631 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2632 (rshader->ring_item_size) >> 2);
2633
2634 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2635 gsvs_itemsize);
2636
2637 /* FIXME calculate these values somehow ??? */
2638 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2639 r600_store_value(cb, 0x80); /* GS_PER_ES */
2640 r600_store_value(cb, 0x100); /* ES_PER_GS */
2641 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2642 r600_store_value(cb, 0x2); /* GS_PER_VS */
2643
2644 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2645 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2646 S_02887C_STACK_SIZE(rshader->bc.nstack));
2647 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS,
2648 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
2649 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2650 }
2651
2652 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2653 {
2654 struct r600_command_buffer *cb = &shader->command_buffer;
2655 struct r600_shader *rshader = &shader->shader;
2656
2657 r600_init_command_buffer(cb, 32);
2658
2659 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2660 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2661 S_028890_STACK_SIZE(rshader->bc.nstack));
2662 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES,
2663 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
2664 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2665 }
2666
2667
2668 void *r600_create_resolve_blend(struct r600_context *rctx)
2669 {
2670 struct pipe_blend_state blend;
2671 unsigned i;
2672
2673 memset(&blend, 0, sizeof(blend));
2674 blend.independent_blend_enable = true;
2675 for (i = 0; i < 2; i++) {
2676 blend.rt[i].colormask = 0xf;
2677 blend.rt[i].blend_enable = 1;
2678 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2679 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2680 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2681 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2682 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2683 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2684 }
2685 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2686 }
2687
2688 void *r700_create_resolve_blend(struct r600_context *rctx)
2689 {
2690 struct pipe_blend_state blend;
2691
2692 memset(&blend, 0, sizeof(blend));
2693 blend.independent_blend_enable = true;
2694 blend.rt[0].colormask = 0xf;
2695 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2696 }
2697
2698 void *r600_create_decompress_blend(struct r600_context *rctx)
2699 {
2700 struct pipe_blend_state blend;
2701
2702 memset(&blend, 0, sizeof(blend));
2703 blend.independent_blend_enable = true;
2704 blend.rt[0].colormask = 0xf;
2705 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2706 }
2707
2708 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2709 {
2710 struct pipe_depth_stencil_alpha_state dsa;
2711 boolean quirk = false;
2712
2713 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2714 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2715 quirk = true;
2716
2717 memset(&dsa, 0, sizeof(dsa));
2718
2719 if (quirk) {
2720 dsa.depth.enabled = 1;
2721 dsa.depth.func = PIPE_FUNC_LEQUAL;
2722 dsa.stencil[0].enabled = 1;
2723 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2724 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2725 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2726 dsa.stencil[0].writemask = 0xff;
2727 }
2728
2729 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2730 }
2731
2732 void r600_update_db_shader_control(struct r600_context * rctx)
2733 {
2734 bool dual_export;
2735 unsigned db_shader_control;
2736
2737 if (!rctx->ps_shader) {
2738 return;
2739 }
2740
2741 dual_export = rctx->framebuffer.export_16bpc &&
2742 !rctx->ps_shader->current->ps_depth_export;
2743
2744 db_shader_control = rctx->ps_shader->current->db_shader_control |
2745 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2746
2747 /* When alpha test is enabled we can't trust the hw to make the proper
2748 * decision on the order in which ztest should be run related to fragment
2749 * shader execution.
2750 *
2751 * If alpha test is enabled perform z test after fragment. RE_Z (early
2752 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2753 */
2754 if (rctx->alphatest_state.sx_alpha_test_control) {
2755 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2756 } else {
2757 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2758 }
2759
2760 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
2761 rctx->db_misc_state.db_shader_control = db_shader_control;
2762 rctx->db_misc_state.atom.dirty = true;
2763 }
2764 }
2765
2766 static INLINE unsigned r600_array_mode(unsigned mode)
2767 {
2768 switch (mode) {
2769 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2770 break;
2771 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2772 break;
2773 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2774 default:
2775 case RADEON_SURF_MODE_LINEAR: return V_0280A0_ARRAY_LINEAR_GENERAL;
2776 }
2777 }
2778
2779 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2780 struct pipe_resource *dst,
2781 unsigned dst_level,
2782 unsigned dst_x,
2783 unsigned dst_y,
2784 unsigned dst_z,
2785 struct pipe_resource *src,
2786 unsigned src_level,
2787 unsigned src_x,
2788 unsigned src_y,
2789 unsigned src_z,
2790 unsigned copy_height,
2791 unsigned pitch,
2792 unsigned bpp)
2793 {
2794 struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
2795 struct r600_texture *rsrc = (struct r600_texture*)src;
2796 struct r600_texture *rdst = (struct r600_texture*)dst;
2797 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2798 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2799 uint64_t base, addr;
2800
2801 dst_mode = rdst->surface.level[dst_level].mode;
2802 src_mode = rsrc->surface.level[src_level].mode;
2803 /* downcast linear aligned to linear to simplify test */
2804 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2805 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2806 assert(dst_mode != src_mode);
2807
2808 y = 0;
2809 lbpp = util_logbase2(bpp);
2810 pitch_tile_max = ((pitch / bpp) / 8) - 1;
2811
2812 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
2813 /* T2L */
2814 array_mode = r600_array_mode(src_mode);
2815 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
2816 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2817 /* linear height must be the same as the slice tile max height, it's ok even
2818 * if the linear destination/source have smaller heigh as the size of the
2819 * dma packet will be using the copy_height which is always smaller or equal
2820 * to the linear height
2821 */
2822 height = rsrc->surface.level[src_level].npix_y;
2823 detile = 1;
2824 x = src_x;
2825 y = src_y;
2826 z = src_z;
2827 base = rsrc->surface.level[src_level].offset;
2828 addr = rdst->surface.level[dst_level].offset;
2829 addr += rdst->surface.level[dst_level].slice_size * dst_z;
2830 addr += dst_y * pitch + dst_x * bpp;
2831 } else {
2832 /* L2T */
2833 array_mode = r600_array_mode(dst_mode);
2834 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
2835 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2836 /* linear height must be the same as the slice tile max height, it's ok even
2837 * if the linear destination/source have smaller heigh as the size of the
2838 * dma packet will be using the copy_height which is always smaller or equal
2839 * to the linear height
2840 */
2841 height = rdst->surface.level[dst_level].npix_y;
2842 detile = 0;
2843 x = dst_x;
2844 y = dst_y;
2845 z = dst_z;
2846 base = rdst->surface.level[dst_level].offset;
2847 addr = rsrc->surface.level[src_level].offset;
2848 addr += rsrc->surface.level[src_level].slice_size * src_z;
2849 addr += src_y * pitch + src_x * bpp;
2850 }
2851 /* check that we are in dw/base alignment constraint */
2852 if (addr % 4 || base % 256) {
2853 return FALSE;
2854 }
2855
2856 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2857 * line in the blit. Compute max 8 line we can copy in the size limit
2858 */
2859 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2860 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2861 r600_need_dma_space(&rctx->b, ncopy * 7);
2862
2863 for (i = 0; i < ncopy; i++) {
2864 cheight = cheight > copy_height ? copy_height : cheight;
2865 size = (cheight * pitch) / 4;
2866 /* emit reloc before writting cs so that cs is always in consistent state */
2867 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ,
2868 RADEON_PRIO_MIN);
2869 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE,
2870 RADEON_PRIO_MIN);
2871 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
2872 cs->buf[cs->cdw++] = base >> 8;
2873 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
2874 (lbpp << 24) | ((height - 1) << 10) |
2875 pitch_tile_max;
2876 cs->buf[cs->cdw++] = (slice_tile_max << 12) | (z << 0);
2877 cs->buf[cs->cdw++] = (x << 3) | (y << 17);
2878 cs->buf[cs->cdw++] = addr & 0xfffffffc;
2879 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
2880 copy_height -= cheight;
2881 addr += cheight * pitch;
2882 y += cheight;
2883 }
2884 return TRUE;
2885 }
2886
2887 static void r600_dma_copy(struct pipe_context *ctx,
2888 struct pipe_resource *dst,
2889 unsigned dst_level,
2890 unsigned dstx, unsigned dsty, unsigned dstz,
2891 struct pipe_resource *src,
2892 unsigned src_level,
2893 const struct pipe_box *src_box)
2894 {
2895 struct r600_context *rctx = (struct r600_context *)ctx;
2896 struct r600_texture *rsrc = (struct r600_texture*)src;
2897 struct r600_texture *rdst = (struct r600_texture*)dst;
2898 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2899 unsigned src_w, dst_w;
2900 unsigned src_x, src_y;
2901 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
2902
2903 if (rctx->b.rings.dma.cs == NULL) {
2904 goto fallback;
2905 }
2906
2907 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
2908 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
2909 goto fallback;
2910
2911 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
2912 return;
2913 }
2914
2915 if (src->format != dst->format || src_box->depth > 1) {
2916 goto fallback;
2917 }
2918
2919 src_x = util_format_get_nblocksx(src->format, src_box->x);
2920 dst_x = util_format_get_nblocksx(src->format, dst_x);
2921 src_y = util_format_get_nblocksy(src->format, src_box->y);
2922 dst_y = util_format_get_nblocksy(src->format, dst_y);
2923
2924 bpp = rdst->surface.bpe;
2925 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
2926 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
2927 src_w = rsrc->surface.level[src_level].npix_x;
2928 dst_w = rdst->surface.level[dst_level].npix_x;
2929 copy_height = src_box->height / rsrc->surface.blk_h;
2930
2931 dst_mode = rdst->surface.level[dst_level].mode;
2932 src_mode = rsrc->surface.level[src_level].mode;
2933 /* downcast linear aligned to linear to simplify test */
2934 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2935 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2936
2937 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
2938 /* strict requirement on r6xx/r7xx */
2939 goto fallback;
2940 }
2941 /* lot of constraint on alignment this should capture them all */
2942 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
2943 goto fallback;
2944 }
2945
2946 if (src_mode == dst_mode) {
2947 uint64_t dst_offset, src_offset, size;
2948
2949 /* simple dma blit would do NOTE code here assume :
2950 * src_box.x/y == 0
2951 * dst_x/y == 0
2952 * dst_pitch == src_pitch
2953 */
2954 src_offset= rsrc->surface.level[src_level].offset;
2955 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
2956 src_offset += src_y * src_pitch + src_x * bpp;
2957 dst_offset = rdst->surface.level[dst_level].offset;
2958 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
2959 dst_offset += dst_y * dst_pitch + dst_x * bpp;
2960 size = src_box->height * src_pitch;
2961 /* must be dw aligned */
2962 if (dst_offset % 4 || src_offset % 4 || size % 4) {
2963 goto fallback;
2964 }
2965 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
2966 } else {
2967 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
2968 src, src_level, src_x, src_y, src_box->z,
2969 copy_height, dst_pitch, bpp)) {
2970 goto fallback;
2971 }
2972 }
2973 return;
2974
2975 fallback:
2976 ctx->resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
2977 src, src_level, src_box);
2978 }
2979
2980 void r600_init_state_functions(struct r600_context *rctx)
2981 {
2982 unsigned id = 4;
2983 int i;
2984
2985 /* !!!
2986 * To avoid GPU lockup registers must be emited in a specific order
2987 * (no kidding ...). The order below is important and have been
2988 * partialy infered from analyzing fglrx command stream.
2989 *
2990 * Don't reorder atom without carefully checking the effect (GPU lockup
2991 * or piglit regression).
2992 * !!!
2993 */
2994
2995 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
2996
2997 /* shader const */
2998 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
2999 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3000 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3001
3002 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3003 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3004 */
3005 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3006 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3007 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3008 /* resource */
3009 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3010 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3011 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3012 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3013
3014 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 7);
3015
3016 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3017 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3018 rctx->sample_mask.sample_mask = ~0;
3019
3020 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3021 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3022 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3023 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3024 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3025 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3026 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3027 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3028 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3029 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
3030 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3031 for (i = 0;i < 16; i++) {
3032 r600_init_atom(rctx, &rctx->scissor[i].atom, id++, r600_emit_scissor_state, 4);
3033 r600_init_atom(rctx, &rctx->viewport[i].atom, id++, r600_emit_viewport_state, 8);
3034 rctx->scissor[i].idx = i;
3035 rctx->viewport[i].idx = i;
3036 }
3037 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3038 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3039 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3040 rctx->atoms[id++] = &rctx->b.streamout.begin_atom;
3041 rctx->atoms[id++] = &rctx->b.streamout.enable_atom;
3042 r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader, 23);
3043 r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader, 0);
3044 r600_init_atom(rctx, &rctx->geometry_shader.atom, id++, r600_emit_shader, 0);
3045 r600_init_atom(rctx, &rctx->export_shader.atom, id++, r600_emit_shader, 0);
3046 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3047 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3048
3049 rctx->b.b.create_blend_state = r600_create_blend_state;
3050 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3051 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3052 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3053 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3054 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3055 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3056 rctx->b.b.set_scissor_states = r600_set_scissor_states;
3057 rctx->b.b.get_sample_position = r600_get_sample_position;
3058 rctx->b.dma_copy = r600_dma_copy;
3059 }
3060 /* this function must be last */