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[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_framebuffer.h>
40 #include "util/u_transfer.h"
41 #include <pipebuffer/pb_buffer.h>
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_state_inlines.h"
48
49 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
50 {
51 struct r600_pipe_state state;
52
53 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
54 state.nregs = 0;
55 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
56 float offset_units = rctx->rasterizer->offset_units;
57 unsigned offset_db_fmt_cntl = 0, depth;
58
59 switch (rctx->framebuffer.zsbuf->texture->format) {
60 case PIPE_FORMAT_Z24X8_UNORM:
61 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
62 depth = -24;
63 offset_units *= 2.0f;
64 break;
65 case PIPE_FORMAT_Z32_FLOAT:
66 depth = -23;
67 offset_units *= 1.0f;
68 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
69 break;
70 case PIPE_FORMAT_Z16_UNORM:
71 depth = -16;
72 offset_units *= 4.0f;
73 break;
74 default:
75 return;
76 }
77 /* FIXME some of those reg can be computed with cso */
78 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
79 r600_pipe_state_add_reg(&state,
80 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
81 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
82 r600_pipe_state_add_reg(&state,
83 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
84 fui(offset_units), 0xFFFFFFFF, NULL);
85 r600_pipe_state_add_reg(&state,
86 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
87 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
88 r600_pipe_state_add_reg(&state,
89 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
90 fui(offset_units), 0xFFFFFFFF, NULL);
91 r600_pipe_state_add_reg(&state,
92 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
93 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
94 r600_context_pipe_state_set(&rctx->ctx, &state);
95 }
96 }
97
98 static void r600_set_blend_color(struct pipe_context *ctx,
99 const struct pipe_blend_color *state)
100 {
101 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
102 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
103
104 if (rstate == NULL)
105 return;
106
107 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
108 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
109 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
110 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
111 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
112 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
113 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
114 r600_context_pipe_state_set(&rctx->ctx, rstate);
115 }
116
117 static void *r600_create_blend_state(struct pipe_context *ctx,
118 const struct pipe_blend_state *state)
119 {
120 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
121 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
122 struct r600_pipe_state *rstate;
123 u32 color_control = 0, target_mask;
124
125 if (blend == NULL) {
126 return NULL;
127 }
128 rstate = &blend->rstate;
129
130 rstate->id = R600_PIPE_STATE_BLEND;
131
132 target_mask = 0;
133
134 /* R600 does not support per-MRT blends */
135 if (rctx->family > CHIP_R600)
136 color_control |= S_028808_PER_MRT_BLEND(1);
137 if (state->logicop_enable) {
138 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
139 } else {
140 color_control |= (0xcc << 16);
141 }
142 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
143 if (state->independent_blend_enable) {
144 for (int i = 0; i < 8; i++) {
145 if (state->rt[i].blend_enable) {
146 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
147 }
148 target_mask |= (state->rt[i].colormask << (4 * i));
149 }
150 } else {
151 for (int i = 0; i < 8; i++) {
152 if (state->rt[0].blend_enable) {
153 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
154 }
155 target_mask |= (state->rt[0].colormask << (4 * i));
156 }
157 }
158 blend->cb_target_mask = target_mask;
159 /* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */
160 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
161 color_control, 0xFFFFFFFD, NULL);
162
163 for (int i = 0; i < 8; i++) {
164 /* state->rt entries > 0 only written if independent blending */
165 const int j = state->independent_blend_enable ? i : 0;
166
167 unsigned eqRGB = state->rt[j].rgb_func;
168 unsigned srcRGB = state->rt[j].rgb_src_factor;
169 unsigned dstRGB = state->rt[j].rgb_dst_factor;
170
171 unsigned eqA = state->rt[j].alpha_func;
172 unsigned srcA = state->rt[j].alpha_src_factor;
173 unsigned dstA = state->rt[j].alpha_dst_factor;
174 uint32_t bc = 0;
175
176 if (!state->rt[j].blend_enable)
177 continue;
178
179 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
180 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
181 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
182
183 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
184 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
185 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
186 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
187 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
188 }
189
190 /* R600 does not support per-MRT blends */
191 if (rctx->family > CHIP_R600)
192 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
193 if (i == 0)
194 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
195 }
196 return rstate;
197 }
198
199 static void *r600_create_dsa_state(struct pipe_context *ctx,
200 const struct pipe_depth_stencil_alpha_state *state)
201 {
202 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
203 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
204 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
205
206 if (rstate == NULL) {
207 return NULL;
208 }
209
210 rstate->id = R600_PIPE_STATE_DSA;
211 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
212 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
213 stencil_ref_mask = 0;
214 stencil_ref_mask_bf = 0;
215 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
216 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
217 S_028800_ZFUNC(state->depth.func);
218
219 /* stencil */
220 if (state->stencil[0].enabled) {
221 db_depth_control |= S_028800_STENCIL_ENABLE(1);
222 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
223 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
224 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
225 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
226
227
228 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
229 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
230 if (state->stencil[1].enabled) {
231 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
232 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
233 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
234 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
235 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
236 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
237 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
238 }
239 }
240
241 /* alpha */
242 alpha_test_control = 0;
243 alpha_ref = 0;
244 if (state->alpha.enabled) {
245 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
246 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
247 alpha_ref = fui(state->alpha.ref_value);
248 }
249
250 /* misc */
251 db_render_control = 0;
252 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
253 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
254 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
255 /* TODO db_render_override depends on query */
256 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
257 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
258 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
259 r600_pipe_state_add_reg(rstate,
260 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
261 0xFFFFFFFF & C_028430_STENCILREF, NULL);
262 r600_pipe_state_add_reg(rstate,
263 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
264 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
265 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
266 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
267 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
268 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
269 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
270 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
271 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
272 * r600_pipe_shader_ps().*/
273 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL);
274 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
275 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
276 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
277 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
278 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
279
280 return rstate;
281 }
282
283 static void *r600_create_rs_state(struct pipe_context *ctx,
284 const struct pipe_rasterizer_state *state)
285 {
286 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
287 struct r600_pipe_state *rstate;
288 unsigned tmp;
289 unsigned prov_vtx = 1, polygon_dual_mode;
290 unsigned clip_rule;
291
292 if (rs == NULL) {
293 return NULL;
294 }
295
296 rstate = &rs->rstate;
297 rs->flatshade = state->flatshade;
298 rs->sprite_coord_enable = state->sprite_coord_enable;
299
300 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
301 /* offset */
302 rs->offset_units = state->offset_units;
303 rs->offset_scale = state->offset_scale * 12.0f;
304
305 rstate->id = R600_PIPE_STATE_RASTERIZER;
306 if (state->flatshade_first)
307 prov_vtx = 0;
308 tmp = S_0286D4_FLAT_SHADE_ENA(1);
309 if (state->sprite_coord_enable) {
310 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
311 S_0286D4_PNT_SPRITE_OVRD_X(2) |
312 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
313 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
314 S_0286D4_PNT_SPRITE_OVRD_W(1);
315 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
316 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
317 }
318 }
319 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
320
321 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
322 state->fill_back != PIPE_POLYGON_MODE_FILL);
323 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
324 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
325 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
326 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
327 S_028814_FACE(!state->front_ccw) |
328 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
329 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
330 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
331 S_028814_POLY_MODE(polygon_dual_mode) |
332 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
333 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
334 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
335 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
336 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
337 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
338 /* point size 12.4 fixed point */
339 tmp = (unsigned)(state->point_size * 8.0);
340 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
341 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
342
343 tmp = (unsigned)state->line_width * 8;
344 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
345
346 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
347 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
348 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
349
350 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
351 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
352 0xFFFFFFFF, NULL);
353
354 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
355 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
356 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
357 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
358 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
359 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
360
361 return rstate;
362 }
363
364 static void *r600_create_sampler_state(struct pipe_context *ctx,
365 const struct pipe_sampler_state *state)
366 {
367 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
368 union util_color uc;
369
370 if (rstate == NULL) {
371 return NULL;
372 }
373
374 rstate->id = R600_PIPE_STATE_SAMPLER;
375 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
376 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
377 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
378 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
379 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
380 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
381 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
382 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
383 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
384 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
385 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
386 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
387 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
388 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
389 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
390 if (uc.ui) {
391 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
392 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
393 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
394 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
395 }
396 return rstate;
397 }
398
399 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
400 struct pipe_resource *texture,
401 const struct pipe_sampler_view *state)
402 {
403 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
404 struct r600_pipe_state *rstate;
405 const struct util_format_description *desc;
406 struct r600_resource_texture *tmp;
407 struct r600_resource *rbuffer;
408 unsigned format, endian;
409 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
410 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
411 struct r600_bo *bo[2];
412 unsigned height, depth;
413
414 if (resource == NULL)
415 return NULL;
416 rstate = &resource->state;
417
418 /* initialize base object */
419 resource->base = *state;
420 resource->base.texture = NULL;
421 pipe_reference(NULL, &texture->reference);
422 resource->base.texture = texture;
423 resource->base.reference.count = 1;
424 resource->base.context = ctx;
425
426 swizzle[0] = state->swizzle_r;
427 swizzle[1] = state->swizzle_g;
428 swizzle[2] = state->swizzle_b;
429 swizzle[3] = state->swizzle_a;
430 format = r600_translate_texformat(ctx->screen, state->format,
431 swizzle,
432 &word4, &yuv_format);
433 if (format == ~0) {
434 format = 0;
435 }
436 desc = util_format_description(state->format);
437 if (desc == NULL) {
438 R600_ERR("unknow format %d\n", state->format);
439 }
440 tmp = (struct r600_resource_texture *)texture;
441 if (tmp->depth && !tmp->is_flushing_texture) {
442 r600_texture_depth_flush(ctx, texture, TRUE);
443 tmp = tmp->flushed_depth_texture;
444 }
445 endian = r600_colorformat_endian_swap(format);
446
447 if (tmp->force_int_type) {
448 word4 &= C_038010_NUM_FORMAT_ALL;
449 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
450 }
451 rbuffer = &tmp->resource;
452 bo[0] = rbuffer->bo;
453 bo[1] = rbuffer->bo;
454 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8);
455 array_mode = tmp->array_mode[0];
456 tile_type = tmp->tile_type;
457
458 height = texture->height0;
459 depth = texture->depth0;
460 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
461 height = 1;
462 depth = texture->array_size;
463 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
464 depth = texture->array_size;
465 }
466
467 /* FIXME properly handle first level != 0 */
468 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
469 S_038000_DIM(r600_tex_dim(texture->target)) |
470 S_038000_TILE_MODE(array_mode) |
471 S_038000_TILE_TYPE(tile_type) |
472 S_038000_PITCH((pitch / 8) - 1) |
473 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
474 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
475 S_038004_TEX_HEIGHT(height - 1) |
476 S_038004_TEX_DEPTH(depth - 1) |
477 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
478 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
479 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
480 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
481 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
482 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
483 word4 |
484 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_NO_ZERO) |
485 S_038010_REQUEST_SIZE(1) |
486 S_038010_ENDIAN_SWAP(endian) |
487 S_038010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
488 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
489 S_038014_LAST_LEVEL(state->u.tex.last_level) |
490 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
491 S_038014_LAST_ARRAY(state->u.tex.last_layer), 0xFFFFFFFF, NULL);
492 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
493 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
494
495 return &resource->base;
496 }
497
498 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
499 struct pipe_sampler_view **views)
500 {
501 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
502 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
503
504 for (int i = 0; i < count; i++) {
505 if (resource[i]) {
506 r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
507 i + R600_MAX_CONST_BUFFERS);
508 }
509 }
510 }
511
512 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
513 struct pipe_sampler_view **views)
514 {
515 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
516 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
517 int i;
518
519 for (i = 0; i < count; i++) {
520 if (&rctx->ps_samplers.views[i]->base != views[i]) {
521 if (resource[i])
522 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
523 i + R600_MAX_CONST_BUFFERS);
524 else
525 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
526 i + R600_MAX_CONST_BUFFERS);
527
528 pipe_sampler_view_reference(
529 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
530 views[i]);
531
532 }
533 }
534 for (i = count; i < NUM_TEX_UNITS; i++) {
535 if (rctx->ps_samplers.views[i]) {
536 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
537 i + R600_MAX_CONST_BUFFERS);
538 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
539 }
540 }
541 rctx->ps_samplers.n_views = count;
542 }
543
544 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
545 {
546 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
547 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
548
549 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
550 rctx->ps_samplers.n_samplers = count;
551
552 for (int i = 0; i < count; i++) {
553 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
554 }
555 }
556
557 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
558 {
559 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
560 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
561
562 for (int i = 0; i < count; i++) {
563 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
564 }
565 }
566
567 static void r600_set_clip_state(struct pipe_context *ctx,
568 const struct pipe_clip_state *state)
569 {
570 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
571 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
572
573 if (rstate == NULL)
574 return;
575
576 rctx->clip = *state;
577 rstate->id = R600_PIPE_STATE_CLIP;
578 for (int i = 0; i < state->nr; i++) {
579 r600_pipe_state_add_reg(rstate,
580 R_028E20_PA_CL_UCP0_X + i * 16,
581 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
582 r600_pipe_state_add_reg(rstate,
583 R_028E24_PA_CL_UCP0_Y + i * 16,
584 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
585 r600_pipe_state_add_reg(rstate,
586 R_028E28_PA_CL_UCP0_Z + i * 16,
587 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
588 r600_pipe_state_add_reg(rstate,
589 R_028E2C_PA_CL_UCP0_W + i * 16,
590 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
591 }
592 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
593 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
594 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
595 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
596
597 free(rctx->states[R600_PIPE_STATE_CLIP]);
598 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
599 r600_context_pipe_state_set(&rctx->ctx, rstate);
600 }
601
602 static void r600_set_polygon_stipple(struct pipe_context *ctx,
603 const struct pipe_poly_stipple *state)
604 {
605 }
606
607 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
608 {
609 }
610
611 static void r600_set_scissor_state(struct pipe_context *ctx,
612 const struct pipe_scissor_state *state)
613 {
614 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
615 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
616 u32 tl, br;
617
618 if (rstate == NULL)
619 return;
620
621 rstate->id = R600_PIPE_STATE_SCISSOR;
622 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
623 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
624 r600_pipe_state_add_reg(rstate,
625 R_028210_PA_SC_CLIPRECT_0_TL, tl,
626 0xFFFFFFFF, NULL);
627 r600_pipe_state_add_reg(rstate,
628 R_028214_PA_SC_CLIPRECT_0_BR, br,
629 0xFFFFFFFF, NULL);
630 r600_pipe_state_add_reg(rstate,
631 R_028218_PA_SC_CLIPRECT_1_TL, tl,
632 0xFFFFFFFF, NULL);
633 r600_pipe_state_add_reg(rstate,
634 R_02821C_PA_SC_CLIPRECT_1_BR, br,
635 0xFFFFFFFF, NULL);
636 r600_pipe_state_add_reg(rstate,
637 R_028220_PA_SC_CLIPRECT_2_TL, tl,
638 0xFFFFFFFF, NULL);
639 r600_pipe_state_add_reg(rstate,
640 R_028224_PA_SC_CLIPRECT_2_BR, br,
641 0xFFFFFFFF, NULL);
642 r600_pipe_state_add_reg(rstate,
643 R_028228_PA_SC_CLIPRECT_3_TL, tl,
644 0xFFFFFFFF, NULL);
645 r600_pipe_state_add_reg(rstate,
646 R_02822C_PA_SC_CLIPRECT_3_BR, br,
647 0xFFFFFFFF, NULL);
648
649 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
650 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
651 r600_context_pipe_state_set(&rctx->ctx, rstate);
652 }
653
654 static void r600_set_stencil_ref(struct pipe_context *ctx,
655 const struct pipe_stencil_ref *state)
656 {
657 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
658 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
659 u32 tmp;
660
661 if (rstate == NULL)
662 return;
663
664 rctx->stencil_ref = *state;
665 rstate->id = R600_PIPE_STATE_STENCIL_REF;
666 tmp = S_028430_STENCILREF(state->ref_value[0]);
667 r600_pipe_state_add_reg(rstate,
668 R_028430_DB_STENCILREFMASK, tmp,
669 ~C_028430_STENCILREF, NULL);
670 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
671 r600_pipe_state_add_reg(rstate,
672 R_028434_DB_STENCILREFMASK_BF, tmp,
673 ~C_028434_STENCILREF_BF, NULL);
674
675 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
676 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
677 r600_context_pipe_state_set(&rctx->ctx, rstate);
678 }
679
680 static void r600_set_viewport_state(struct pipe_context *ctx,
681 const struct pipe_viewport_state *state)
682 {
683 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
684 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
685
686 if (rstate == NULL)
687 return;
688
689 rctx->viewport = *state;
690 rstate->id = R600_PIPE_STATE_VIEWPORT;
691 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
692 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
693 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
694 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
695 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
696 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
697 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
698 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
699 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
700
701 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
702 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
703 r600_context_pipe_state_set(&rctx->ctx, rstate);
704 }
705
706 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
707 const struct pipe_framebuffer_state *state, int cb)
708 {
709 struct r600_resource_texture *rtex;
710 struct r600_resource *rbuffer;
711 struct r600_surface *surf;
712 unsigned level = state->cbufs[cb]->u.tex.level;
713 unsigned pitch, slice;
714 unsigned color_info;
715 unsigned format, swap, ntype, endian;
716 unsigned offset;
717 const struct util_format_description *desc;
718 struct r600_bo *bo[3];
719 int i;
720
721 surf = (struct r600_surface *)state->cbufs[cb];
722 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
723
724 if (rtex->depth && !rtex->is_flushing_texture) {
725 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
726 rtex = rtex->flushed_depth_texture;
727 }
728
729 rbuffer = &rtex->resource;
730 bo[0] = rbuffer->bo;
731 bo[1] = rbuffer->bo;
732 bo[2] = rbuffer->bo;
733
734 /* XXX quite sure for dx10+ hw don't need any offset hacks */
735 offset = r600_texture_get_offset(rtex,
736 level, state->cbufs[cb]->u.tex.first_layer);
737 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
738 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
739 desc = util_format_description(surf->base.format);
740
741 for (i = 0; i < 4; i++) {
742 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
743 break;
744 }
745 }
746 ntype = V_0280A0_NUMBER_UNORM;
747 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
748 ntype = V_0280A0_NUMBER_SRGB;
749 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED)
750 ntype = V_0280A0_NUMBER_SNORM;
751
752 format = r600_translate_colorformat(surf->base.format);
753 swap = r600_translate_colorswap(surf->base.format);
754 if(rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
755 endian = ENDIAN_NONE;
756 } else {
757 endian = r600_colorformat_endian_swap(format);
758 }
759
760 /* disable when gallium grows int textures */
761 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
762 ntype = V_0280A0_NUMBER_UINT;
763
764 color_info = S_0280A0_FORMAT(format) |
765 S_0280A0_COMP_SWAP(swap) |
766 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
767 S_0280A0_BLEND_CLAMP(1) |
768 S_0280A0_NUMBER_TYPE(ntype) |
769 S_0280A0_ENDIAN(endian);
770
771 /* on R600 this can't be set if BLEND_CLAMP isn't set,
772 if BLEND_FLOAT32 is set of > 11 bits in a UNORM or SNORM */
773 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
774 desc->channel[i].size < 12)
775 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
776
777 r600_pipe_state_add_reg(rstate,
778 R_028040_CB_COLOR0_BASE + cb * 4,
779 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
780 r600_pipe_state_add_reg(rstate,
781 R_0280A0_CB_COLOR0_INFO + cb * 4,
782 color_info, 0xFFFFFFFF, bo[0]);
783 r600_pipe_state_add_reg(rstate,
784 R_028060_CB_COLOR0_SIZE + cb * 4,
785 S_028060_PITCH_TILE_MAX(pitch) |
786 S_028060_SLICE_TILE_MAX(slice),
787 0xFFFFFFFF, NULL);
788 r600_pipe_state_add_reg(rstate,
789 R_028080_CB_COLOR0_VIEW + cb * 4,
790 0x00000000, 0xFFFFFFFF, NULL);
791 r600_pipe_state_add_reg(rstate,
792 R_0280E0_CB_COLOR0_FRAG + cb * 4,
793 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
794 r600_pipe_state_add_reg(rstate,
795 R_0280C0_CB_COLOR0_TILE + cb * 4,
796 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
797 r600_pipe_state_add_reg(rstate,
798 R_028100_CB_COLOR0_MASK + cb * 4,
799 0x00000000, 0xFFFFFFFF, NULL);
800 }
801
802 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
803 const struct pipe_framebuffer_state *state)
804 {
805 struct r600_resource_texture *rtex;
806 struct r600_resource *rbuffer;
807 struct r600_surface *surf;
808 unsigned level;
809 unsigned pitch, slice, format;
810 unsigned offset;
811
812 if (state->zsbuf == NULL)
813 return;
814
815 level = state->zsbuf->u.tex.level;
816
817 surf = (struct r600_surface *)state->zsbuf;
818 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
819
820 rbuffer = &rtex->resource;
821
822 /* XXX quite sure for dx10+ hw don't need any offset hacks */
823 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
824 level, state->zsbuf->u.tex.first_layer);
825 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
826 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
827 format = r600_translate_dbformat(state->zsbuf->texture->format);
828
829 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
830 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
831 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
832 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
833 0xFFFFFFFF, NULL);
834 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
835 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
836 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
837 0xFFFFFFFF, rbuffer->bo);
838 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
839 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL);
840 }
841
842 static void r600_set_framebuffer_state(struct pipe_context *ctx,
843 const struct pipe_framebuffer_state *state)
844 {
845 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
846 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
847 u32 shader_mask, tl, br, shader_control, target_mask;
848
849 if (rstate == NULL)
850 return;
851
852 r600_context_flush_dest_caches(&rctx->ctx);
853 rctx->ctx.num_dest_buffers = state->nr_cbufs;
854
855 /* unreference old buffer and reference new one */
856 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
857
858 util_copy_framebuffer_state(&rctx->framebuffer, state);
859
860 /* build states */
861 for (int i = 0; i < state->nr_cbufs; i++) {
862 r600_cb(rctx, rstate, state, i);
863 }
864 if (state->zsbuf) {
865 r600_db(rctx, rstate, state);
866 rctx->ctx.num_dest_buffers++;
867 }
868
869 target_mask = 0x00000000;
870 target_mask = 0xFFFFFFFF;
871 shader_mask = 0;
872 shader_control = 0;
873 for (int i = 0; i < state->nr_cbufs; i++) {
874 target_mask ^= 0xf << (i * 4);
875 shader_mask |= 0xf << (i * 4);
876 shader_control |= 1 << i;
877 }
878 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
879 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
880
881 r600_pipe_state_add_reg(rstate,
882 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
883 0xFFFFFFFF, NULL);
884 r600_pipe_state_add_reg(rstate,
885 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
886 0xFFFFFFFF, NULL);
887 r600_pipe_state_add_reg(rstate,
888 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
889 0xFFFFFFFF, NULL);
890 r600_pipe_state_add_reg(rstate,
891 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
892 0xFFFFFFFF, NULL);
893 r600_pipe_state_add_reg(rstate,
894 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
895 0xFFFFFFFF, NULL);
896 r600_pipe_state_add_reg(rstate,
897 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
898 0xFFFFFFFF, NULL);
899 r600_pipe_state_add_reg(rstate,
900 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
901 0xFFFFFFFF, NULL);
902 r600_pipe_state_add_reg(rstate,
903 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
904 0xFFFFFFFF, NULL);
905 r600_pipe_state_add_reg(rstate,
906 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
907 0xFFFFFFFF, NULL);
908 if (rctx->family >= CHIP_RV770) {
909 r600_pipe_state_add_reg(rstate,
910 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
911 0xFFFFFFFF, NULL);
912 }
913
914 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
915 shader_control, 0xFFFFFFFF, NULL);
916 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
917 0x00000000, target_mask, NULL);
918 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
919 shader_mask, 0xFFFFFFFF, NULL);
920 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
921 0x00000000, 0xFFFFFFFF, NULL);
922 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
923 0x00000000, 0xFFFFFFFF, NULL);
924 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
925 0x00000000, 0xFFFFFFFF, NULL);
926 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
927 0x01000000, 0xFFFFFFFF, NULL);
928 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
929 0x00000000, 0xFFFFFFFF, NULL);
930 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
931 0x000000FF, 0xFFFFFFFF, NULL);
932 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
933 0xFFFFFFFF, 0xFFFFFFFF, NULL);
934 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
935 0xFFFFFFFF, 0xFFFFFFFF, NULL);
936
937 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
938 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
939 r600_context_pipe_state_set(&rctx->ctx, rstate);
940
941 if (state->zsbuf) {
942 r600_polygon_offset_update(rctx);
943 }
944 }
945
946 static void r600_texture_barrier(struct pipe_context *ctx)
947 {
948 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
949
950 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
951 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
952 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
953 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
954 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1));
955 }
956
957 void r600_init_state_functions(struct r600_pipe_context *rctx)
958 {
959 rctx->context.create_blend_state = r600_create_blend_state;
960 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
961 rctx->context.create_fs_state = r600_create_shader_state;
962 rctx->context.create_rasterizer_state = r600_create_rs_state;
963 rctx->context.create_sampler_state = r600_create_sampler_state;
964 rctx->context.create_sampler_view = r600_create_sampler_view;
965 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
966 rctx->context.create_vs_state = r600_create_shader_state;
967 rctx->context.bind_blend_state = r600_bind_blend_state;
968 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
969 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
970 rctx->context.bind_fs_state = r600_bind_ps_shader;
971 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
972 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
973 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
974 rctx->context.bind_vs_state = r600_bind_vs_shader;
975 rctx->context.delete_blend_state = r600_delete_state;
976 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
977 rctx->context.delete_fs_state = r600_delete_ps_shader;
978 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
979 rctx->context.delete_sampler_state = r600_delete_state;
980 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
981 rctx->context.delete_vs_state = r600_delete_vs_shader;
982 rctx->context.set_blend_color = r600_set_blend_color;
983 rctx->context.set_clip_state = r600_set_clip_state;
984 rctx->context.set_constant_buffer = r600_set_constant_buffer;
985 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
986 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
987 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
988 rctx->context.set_sample_mask = r600_set_sample_mask;
989 rctx->context.set_scissor_state = r600_set_scissor_state;
990 rctx->context.set_stencil_ref = r600_set_stencil_ref;
991 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
992 rctx->context.set_index_buffer = r600_set_index_buffer;
993 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
994 rctx->context.set_viewport_state = r600_set_viewport_state;
995 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
996 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
997 rctx->context.texture_barrier = r600_texture_barrier;
998 }
999
1000 void r600_init_config(struct r600_pipe_context *rctx)
1001 {
1002 int ps_prio;
1003 int vs_prio;
1004 int gs_prio;
1005 int es_prio;
1006 int num_ps_gprs;
1007 int num_vs_gprs;
1008 int num_gs_gprs;
1009 int num_es_gprs;
1010 int num_temp_gprs;
1011 int num_ps_threads;
1012 int num_vs_threads;
1013 int num_gs_threads;
1014 int num_es_threads;
1015 int num_ps_stack_entries;
1016 int num_vs_stack_entries;
1017 int num_gs_stack_entries;
1018 int num_es_stack_entries;
1019 enum radeon_family family;
1020 struct r600_pipe_state *rstate = &rctx->config;
1021 u32 tmp;
1022
1023 family = r600_get_family(rctx->radeon);
1024 ps_prio = 0;
1025 vs_prio = 1;
1026 gs_prio = 2;
1027 es_prio = 3;
1028 switch (family) {
1029 case CHIP_R600:
1030 num_ps_gprs = 192;
1031 num_vs_gprs = 56;
1032 num_temp_gprs = 4;
1033 num_gs_gprs = 0;
1034 num_es_gprs = 0;
1035 num_ps_threads = 136;
1036 num_vs_threads = 48;
1037 num_gs_threads = 4;
1038 num_es_threads = 4;
1039 num_ps_stack_entries = 128;
1040 num_vs_stack_entries = 128;
1041 num_gs_stack_entries = 0;
1042 num_es_stack_entries = 0;
1043 break;
1044 case CHIP_RV630:
1045 case CHIP_RV635:
1046 num_ps_gprs = 84;
1047 num_vs_gprs = 36;
1048 num_temp_gprs = 4;
1049 num_gs_gprs = 0;
1050 num_es_gprs = 0;
1051 num_ps_threads = 144;
1052 num_vs_threads = 40;
1053 num_gs_threads = 4;
1054 num_es_threads = 4;
1055 num_ps_stack_entries = 40;
1056 num_vs_stack_entries = 40;
1057 num_gs_stack_entries = 32;
1058 num_es_stack_entries = 16;
1059 break;
1060 case CHIP_RV610:
1061 case CHIP_RV620:
1062 case CHIP_RS780:
1063 case CHIP_RS880:
1064 default:
1065 num_ps_gprs = 84;
1066 num_vs_gprs = 36;
1067 num_temp_gprs = 4;
1068 num_gs_gprs = 0;
1069 num_es_gprs = 0;
1070 num_ps_threads = 136;
1071 num_vs_threads = 48;
1072 num_gs_threads = 4;
1073 num_es_threads = 4;
1074 num_ps_stack_entries = 40;
1075 num_vs_stack_entries = 40;
1076 num_gs_stack_entries = 32;
1077 num_es_stack_entries = 16;
1078 break;
1079 case CHIP_RV670:
1080 num_ps_gprs = 144;
1081 num_vs_gprs = 40;
1082 num_temp_gprs = 4;
1083 num_gs_gprs = 0;
1084 num_es_gprs = 0;
1085 num_ps_threads = 136;
1086 num_vs_threads = 48;
1087 num_gs_threads = 4;
1088 num_es_threads = 4;
1089 num_ps_stack_entries = 40;
1090 num_vs_stack_entries = 40;
1091 num_gs_stack_entries = 32;
1092 num_es_stack_entries = 16;
1093 break;
1094 case CHIP_RV770:
1095 num_ps_gprs = 192;
1096 num_vs_gprs = 56;
1097 num_temp_gprs = 4;
1098 num_gs_gprs = 0;
1099 num_es_gprs = 0;
1100 num_ps_threads = 188;
1101 num_vs_threads = 60;
1102 num_gs_threads = 0;
1103 num_es_threads = 0;
1104 num_ps_stack_entries = 256;
1105 num_vs_stack_entries = 256;
1106 num_gs_stack_entries = 0;
1107 num_es_stack_entries = 0;
1108 break;
1109 case CHIP_RV730:
1110 case CHIP_RV740:
1111 num_ps_gprs = 84;
1112 num_vs_gprs = 36;
1113 num_temp_gprs = 4;
1114 num_gs_gprs = 0;
1115 num_es_gprs = 0;
1116 num_ps_threads = 188;
1117 num_vs_threads = 60;
1118 num_gs_threads = 0;
1119 num_es_threads = 0;
1120 num_ps_stack_entries = 128;
1121 num_vs_stack_entries = 128;
1122 num_gs_stack_entries = 0;
1123 num_es_stack_entries = 0;
1124 break;
1125 case CHIP_RV710:
1126 num_ps_gprs = 192;
1127 num_vs_gprs = 56;
1128 num_temp_gprs = 4;
1129 num_gs_gprs = 0;
1130 num_es_gprs = 0;
1131 num_ps_threads = 144;
1132 num_vs_threads = 48;
1133 num_gs_threads = 0;
1134 num_es_threads = 0;
1135 num_ps_stack_entries = 128;
1136 num_vs_stack_entries = 128;
1137 num_gs_stack_entries = 0;
1138 num_es_stack_entries = 0;
1139 break;
1140 }
1141
1142 rstate->id = R600_PIPE_STATE_CONFIG;
1143
1144 /* SQ_CONFIG */
1145 tmp = 0;
1146 switch (family) {
1147 case CHIP_RV610:
1148 case CHIP_RV620:
1149 case CHIP_RS780:
1150 case CHIP_RS880:
1151 case CHIP_RV710:
1152 break;
1153 default:
1154 tmp |= S_008C00_VC_ENABLE(1);
1155 break;
1156 }
1157 tmp |= S_008C00_DX9_CONSTS(0);
1158 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1159 tmp |= S_008C00_PS_PRIO(ps_prio);
1160 tmp |= S_008C00_VS_PRIO(vs_prio);
1161 tmp |= S_008C00_GS_PRIO(gs_prio);
1162 tmp |= S_008C00_ES_PRIO(es_prio);
1163 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1164
1165 /* SQ_GPR_RESOURCE_MGMT_1 */
1166 tmp = 0;
1167 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1168 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1169 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1170 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1171
1172 /* SQ_GPR_RESOURCE_MGMT_2 */
1173 tmp = 0;
1174 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1175 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1176 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1177
1178 /* SQ_THREAD_RESOURCE_MGMT */
1179 tmp = 0;
1180 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1181 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1182 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1183 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1184 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1185
1186 /* SQ_STACK_RESOURCE_MGMT_1 */
1187 tmp = 0;
1188 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1189 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1190 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1191
1192 /* SQ_STACK_RESOURCE_MGMT_2 */
1193 tmp = 0;
1194 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1195 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1196 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1197
1198 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1199 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1200
1201 if (family >= CHIP_RV770) {
1202 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1203 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1204 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1205 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1206 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1207 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
1208 } else {
1209 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1210 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1211 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1212 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1213 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1214 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
1215 }
1216 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1217 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1218 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1219 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1220 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1221 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1222 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1223 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1224 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1225 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1226 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1227 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1228 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1229 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1230 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1231 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1232 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1233 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1234 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1235 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1236 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1237 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1238 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1239 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1240 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1241 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1242
1243 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1244 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1245 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1246 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1247 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1248 r600_context_pipe_state_set(&rctx->ctx, rstate);
1249 }
1250
1251 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1252 {
1253 struct r600_pipe_state *rstate = &shader->rstate;
1254 struct r600_shader *rshader = &shader->shader;
1255 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
1256 int pos_index = -1, face_index = -1;
1257
1258 rstate->nregs = 0;
1259
1260 for (i = 0; i < rshader->ninput; i++) {
1261 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1262 pos_index = i;
1263 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1264 face_index = i;
1265 }
1266
1267 db_shader_control = 0;
1268 for (i = 0; i < rshader->noutput; i++) {
1269 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1270 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1271 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1272 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
1273 }
1274 if (rshader->uses_kill)
1275 db_shader_control |= S_02880C_KILL_ENABLE(1);
1276
1277 exports_ps = 0;
1278 num_cout = 0;
1279 for (i = 0; i < rshader->noutput; i++) {
1280 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1281 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1282 exports_ps |= 1;
1283 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1284 num_cout++;
1285 }
1286 }
1287 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
1288 if (!exports_ps) {
1289 /* always at least export 1 component per pixel */
1290 exports_ps = 2;
1291 }
1292
1293 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
1294 S_0286CC_PERSP_GRADIENT_ENA(1);
1295 spi_input_z = 0;
1296 if (pos_index != -1) {
1297 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
1298 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1299 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
1300 S_0286CC_BARYC_SAMPLE_CNTL(1));
1301 spi_input_z |= 1;
1302 }
1303
1304 spi_ps_in_control_1 = 0;
1305 if (face_index != -1) {
1306 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1307 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1308 }
1309
1310 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1311 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1312 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1313 r600_pipe_state_add_reg(rstate,
1314 R_028840_SQ_PGM_START_PS,
1315 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
1316 r600_pipe_state_add_reg(rstate,
1317 R_028850_SQ_PGM_RESOURCES_PS,
1318 S_028868_NUM_GPRS(rshader->bc.ngpr) |
1319 S_028868_STACK_SIZE(rshader->bc.nstack),
1320 0xFFFFFFFF, NULL);
1321 r600_pipe_state_add_reg(rstate,
1322 R_028854_SQ_PGM_EXPORTS_PS,
1323 exports_ps, 0xFFFFFFFF, NULL);
1324 r600_pipe_state_add_reg(rstate,
1325 R_0288CC_SQ_PGM_CF_OFFSET_PS,
1326 0x00000000, 0xFFFFFFFF, NULL);
1327 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
1328 S_028808_MULTIWRITE_ENABLE(!!rshader->fs_write_all),
1329 S_028808_MULTIWRITE_ENABLE(1),
1330 NULL);
1331 /* only set some bits here, the other bits are set in the dsa state */
1332 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
1333 db_shader_control,
1334 S_02880C_Z_EXPORT_ENABLE(1) |
1335 S_02880C_STENCIL_REF_EXPORT_ENABLE(1) |
1336 S_02880C_KILL_ENABLE(1),
1337 NULL);
1338
1339 r600_pipe_state_add_reg(rstate,
1340 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
1341 0xFFFFFFFF, NULL);
1342 }
1343
1344 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1345 {
1346 struct r600_pipe_state *rstate = &shader->rstate;
1347 struct r600_shader *rshader = &shader->shader;
1348 unsigned spi_vs_out_id[10];
1349 unsigned i, tmp;
1350
1351 /* clear previous register */
1352 rstate->nregs = 0;
1353
1354 /* so far never got proper semantic id from tgsi */
1355 /* FIXME better to move this in config things so they get emited
1356 * only one time per cs
1357 */
1358 for (i = 0; i < 10; i++) {
1359 spi_vs_out_id[i] = 0;
1360 }
1361 for (i = 0; i < 32; i++) {
1362 tmp = i << ((i & 3) * 8);
1363 spi_vs_out_id[i / 4] |= tmp;
1364 }
1365 for (i = 0; i < 10; i++) {
1366 r600_pipe_state_add_reg(rstate,
1367 R_028614_SPI_VS_OUT_ID_0 + i * 4,
1368 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1369 }
1370
1371 r600_pipe_state_add_reg(rstate,
1372 R_0286C4_SPI_VS_OUT_CONFIG,
1373 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1374 0xFFFFFFFF, NULL);
1375 r600_pipe_state_add_reg(rstate,
1376 R_028868_SQ_PGM_RESOURCES_VS,
1377 S_028868_NUM_GPRS(rshader->bc.ngpr) |
1378 S_028868_STACK_SIZE(rshader->bc.nstack),
1379 0xFFFFFFFF, NULL);
1380 r600_pipe_state_add_reg(rstate,
1381 R_0288D0_SQ_PGM_CF_OFFSET_VS,
1382 0x00000000, 0xFFFFFFFF, NULL);
1383 r600_pipe_state_add_reg(rstate,
1384 R_028858_SQ_PGM_START_VS,
1385 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
1386
1387 r600_pipe_state_add_reg(rstate,
1388 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1389 0xFFFFFFFF, NULL);
1390 }
1391
1392 void r600_fetch_shader(struct r600_vertex_element *ve)
1393 {
1394 struct r600_pipe_state *rstate;
1395
1396 rstate = &ve->rstate;
1397 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1398 rstate->nregs = 0;
1399 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1400 0x00000000, 0xFFFFFFFF, NULL);
1401 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1402 0x00000000, 0xFFFFFFFF, NULL);
1403 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1404 r600_bo_offset(ve->fetch_shader) >> 8,
1405 0xFFFFFFFF, ve->fetch_shader);
1406 }
1407
1408 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1409 {
1410 struct pipe_depth_stencil_alpha_state dsa;
1411 struct r600_pipe_state *rstate;
1412 boolean quirk = false;
1413
1414 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1415 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1416 quirk = true;
1417
1418 memset(&dsa, 0, sizeof(dsa));
1419
1420 if (quirk) {
1421 dsa.depth.enabled = 1;
1422 dsa.depth.func = PIPE_FUNC_LEQUAL;
1423 dsa.stencil[0].enabled = 1;
1424 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1425 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1426 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1427 dsa.stencil[0].writemask = 0xff;
1428 }
1429
1430 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1431 r600_pipe_state_add_reg(rstate,
1432 R_02880C_DB_SHADER_CONTROL,
1433 0x0,
1434 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1435 r600_pipe_state_add_reg(rstate,
1436 R_028D0C_DB_RENDER_CONTROL,
1437 S_028D0C_DEPTH_COPY_ENABLE(1) |
1438 S_028D0C_STENCIL_COPY_ENABLE(1) |
1439 S_028D0C_COPY_CENTROID(1),
1440 S_028D0C_DEPTH_COPY_ENABLE(1) |
1441 S_028D0C_STENCIL_COPY_ENABLE(1) |
1442 S_028D0C_COPY_CENTROID(1), NULL);
1443 return rstate;
1444 }
1445
1446 void r600_pipe_set_buffer_resource(struct r600_pipe_context *rctx,
1447 struct r600_pipe_state *rstate,
1448 struct r600_resource *rbuffer,
1449 unsigned offset, unsigned stride)
1450 {
1451 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
1452 offset, 0xFFFFFFFF, rbuffer->bo);
1453 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
1454 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
1455 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
1456 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1457 S_038008_STRIDE(stride), 0xFFFFFFFF, NULL);
1458 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
1459 0x00000000, 0xFFFFFFFF, NULL);
1460 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
1461 0x00000000, 0xFFFFFFFF, NULL);
1462 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
1463 0x00000000, 0xFFFFFFFF, NULL);
1464 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
1465 0xC0000000, 0xFFFFFFFF, NULL);
1466 }