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r600g: add occlusion query support
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <stdio.h>
27 #include <errno.h>
28 #include "util/u_inlines.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "r600_screen.h"
32 #include "r600_context.h"
33 #include "r600_resource.h"
34 #include "r600d.h"
35 #include "r600_state_inlines.h"
36
37 static void *r600_create_blend_state(struct pipe_context *ctx,
38 const struct pipe_blend_state *state)
39 {
40 struct r600_context *rctx = r600_context(ctx);
41
42 return r600_context_state(rctx, pipe_blend_type, state);
43 }
44
45 static void *r600_create_dsa_state(struct pipe_context *ctx,
46 const struct pipe_depth_stencil_alpha_state *state)
47 {
48 struct r600_context *rctx = r600_context(ctx);
49
50 return r600_context_state(rctx, pipe_dsa_type, state);
51 }
52
53 static void *r600_create_rs_state(struct pipe_context *ctx,
54 const struct pipe_rasterizer_state *state)
55 {
56 struct r600_context *rctx = r600_context(ctx);
57
58 return r600_context_state(rctx, pipe_rasterizer_type, state);
59 }
60
61 static void *r600_create_sampler_state(struct pipe_context *ctx,
62 const struct pipe_sampler_state *state)
63 {
64 struct r600_context *rctx = r600_context(ctx);
65
66 return r600_context_state(rctx, pipe_sampler_type, state);
67 }
68
69 static void r600_sampler_view_destroy(struct pipe_context *ctx,
70 struct pipe_sampler_view *state)
71 {
72 struct r600_context_state *rstate = (struct r600_context_state *)state;
73
74 r600_context_state_decref(rstate);
75 }
76
77 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
78 struct pipe_resource *texture,
79 const struct pipe_sampler_view *state)
80 {
81 struct r600_context *rctx = r600_context(ctx);
82 struct r600_context_state *rstate;
83
84 rstate = r600_context_state(rctx, pipe_sampler_type, state);
85 pipe_reference(NULL, &texture->reference);
86 rstate->state.sampler_view.texture = texture;
87 rstate->state.sampler_view.reference.count = 1;
88 rstate->state.sampler_view.context = ctx;
89 return &rstate->state.sampler_view;
90 }
91
92 static void *r600_create_shader_state(struct pipe_context *ctx,
93 const struct pipe_shader_state *state)
94 {
95 struct r600_context *rctx = r600_context(ctx);
96
97 return r600_context_state(rctx, pipe_shader_type, state);
98 }
99
100 static void *r600_create_vertex_elements(struct pipe_context *ctx,
101 unsigned count,
102 const struct pipe_vertex_element *elements)
103 {
104 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
105
106 assert(count < 32);
107 v->count = count;
108 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
109 v->refcount = 1;
110 return v;
111 }
112
113 static void r600_bind_state(struct pipe_context *ctx, void *state)
114 {
115 struct r600_context *rctx = r600_context(ctx);
116 struct r600_context_state *rstate = (struct r600_context_state *)state;
117
118 if (state == NULL)
119 return;
120 switch (rstate->type) {
121 case pipe_rasterizer_type:
122 rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
123 rctx->rasterizer = r600_context_state_incref(rstate);
124 break;
125 case pipe_poly_stipple_type:
126 rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
127 rctx->poly_stipple = r600_context_state_incref(rstate);
128 break;
129 case pipe_scissor_type:
130 rctx->scissor = r600_context_state_decref(rctx->scissor);
131 rctx->scissor = r600_context_state_incref(rstate);
132 break;
133 case pipe_clip_type:
134 rctx->clip = r600_context_state_decref(rctx->clip);
135 rctx->clip = r600_context_state_incref(rstate);
136 break;
137 case pipe_depth_type:
138 rctx->depth = r600_context_state_decref(rctx->depth);
139 rctx->depth = r600_context_state_incref(rstate);
140 break;
141 case pipe_stencil_type:
142 rctx->stencil = r600_context_state_decref(rctx->stencil);
143 rctx->stencil = r600_context_state_incref(rstate);
144 break;
145 case pipe_alpha_type:
146 rctx->alpha = r600_context_state_decref(rctx->alpha);
147 rctx->alpha = r600_context_state_incref(rstate);
148 break;
149 case pipe_dsa_type:
150 rctx->dsa = r600_context_state_decref(rctx->dsa);
151 rctx->dsa = r600_context_state_incref(rstate);
152 break;
153 case pipe_blend_type:
154 rctx->blend = r600_context_state_decref(rctx->blend);
155 rctx->blend = r600_context_state_incref(rstate);
156 break;
157 case pipe_framebuffer_type:
158 rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
159 rctx->framebuffer = r600_context_state_incref(rstate);
160 break;
161 case pipe_stencil_ref_type:
162 rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
163 rctx->stencil_ref = r600_context_state_incref(rstate);
164 break;
165 case pipe_viewport_type:
166 rctx->viewport = r600_context_state_decref(rctx->viewport);
167 rctx->viewport = r600_context_state_incref(rstate);
168 break;
169 case pipe_shader_type:
170 case pipe_sampler_type:
171 case pipe_sampler_view_type:
172 default:
173 R600_ERR("invalid type %d\n", rstate->type);
174 return;
175 }
176 }
177
178 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
179 {
180 struct r600_context *rctx = r600_context(ctx);
181 struct r600_context_state *rstate = (struct r600_context_state *)state;
182
183 rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
184 rctx->ps_shader = r600_context_state_incref(rstate);
185 }
186
187 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
188 {
189 struct r600_context *rctx = r600_context(ctx);
190 struct r600_context_state *rstate = (struct r600_context_state *)state;
191
192 rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
193 rctx->vs_shader = r600_context_state_incref(rstate);
194 }
195
196 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
197 {
198 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
199
200 if (v == NULL)
201 return;
202 if (--v->refcount)
203 return;
204 free(v);
205 }
206
207 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
208 {
209 struct r600_context *rctx = r600_context(ctx);
210 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
211
212 r600_delete_vertex_element(ctx, rctx->vertex_elements);
213 rctx->vertex_elements = v;
214 if (v) {
215 v->refcount++;
216 }
217 }
218
219 static void r600_bind_ps_sampler(struct pipe_context *ctx,
220 unsigned count, void **states)
221 {
222 struct r600_context *rctx = r600_context(ctx);
223 struct r600_context_state *rstate;
224 unsigned i;
225
226 for (i = 0; i < rctx->ps_nsampler; i++) {
227 rctx->ps_sampler[i] = r600_context_state_decref(rctx->ps_sampler[i]);
228 }
229 for (i = 0; i < count; i++) {
230 rstate = (struct r600_context_state *)states[i];
231 rctx->ps_sampler[i] = r600_context_state_incref(rstate);
232 }
233 rctx->ps_nsampler = count;
234 }
235
236 static void r600_bind_vs_sampler(struct pipe_context *ctx,
237 unsigned count, void **states)
238 {
239 struct r600_context *rctx = r600_context(ctx);
240 struct r600_context_state *rstate;
241 unsigned i;
242
243 for (i = 0; i < rctx->vs_nsampler; i++) {
244 rctx->vs_sampler[i] = r600_context_state_decref(rctx->vs_sampler[i]);
245 }
246 for (i = 0; i < count; i++) {
247 rstate = (struct r600_context_state *)states[i];
248 rctx->vs_sampler[i] = r600_context_state_incref(rstate);
249 }
250 rctx->vs_nsampler = count;
251 }
252
253 static void r600_delete_state(struct pipe_context *ctx, void *state)
254 {
255 struct r600_context_state *rstate = (struct r600_context_state *)state;
256
257 r600_context_state_decref(rstate);
258 }
259
260 static void r600_set_blend_color(struct pipe_context *ctx,
261 const struct pipe_blend_color *color)
262 {
263 struct r600_context *rctx = r600_context(ctx);
264
265 rctx->blend_color = *color;
266 }
267
268 static void r600_set_clip_state(struct pipe_context *ctx,
269 const struct pipe_clip_state *state)
270 {
271 struct r600_context *rctx = r600_context(ctx);
272 struct r600_context_state *rstate;
273
274 rstate = r600_context_state(rctx, pipe_clip_type, state);
275 r600_bind_state(ctx, rstate);
276 /* refcount is taken care of this */
277 r600_delete_state(ctx, rstate);
278 }
279
280 static void r600_set_constant_buffer(struct pipe_context *ctx,
281 uint shader, uint index,
282 struct pipe_resource *buffer)
283 {
284 struct r600_screen *rscreen = r600_screen(ctx->screen);
285 struct r600_context *rctx = r600_context(ctx);
286 unsigned nconstant = 0, i, type, id;
287 struct radeon_state *rstate;
288 struct pipe_transfer *transfer;
289 u32 *ptr;
290
291 switch (shader) {
292 case PIPE_SHADER_VERTEX:
293 id = R600_VS_CONSTANT;
294 type = R600_VS_CONSTANT_TYPE;
295 break;
296 case PIPE_SHADER_FRAGMENT:
297 id = R600_PS_CONSTANT;
298 type = R600_PS_CONSTANT_TYPE;
299 break;
300 default:
301 R600_ERR("unsupported %d\n", shader);
302 return;
303 }
304 if (buffer && buffer->width0 > 0) {
305 nconstant = buffer->width0 / 16;
306 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
307 if (ptr == NULL)
308 return;
309 for (i = 0; i < nconstant; i++) {
310 rstate = radeon_state(rscreen->rw, type, id + i);
311 if (rstate == NULL)
312 return;
313 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
314 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
315 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
316 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
317 if (radeon_state_pm4(rstate))
318 return;
319 if (radeon_draw_set_new(rctx->draw, rstate))
320 return;
321 }
322 pipe_buffer_unmap(ctx, buffer, transfer);
323 }
324 }
325
326 static void r600_set_ps_sampler_view(struct pipe_context *ctx,
327 unsigned count,
328 struct pipe_sampler_view **views)
329 {
330 struct r600_context *rctx = r600_context(ctx);
331 struct r600_context_state *rstate;
332 unsigned i;
333
334 for (i = 0; i < rctx->ps_nsampler_view; i++) {
335 rctx->ps_sampler_view[i] = r600_context_state_decref(rctx->ps_sampler_view[i]);
336 }
337 for (i = 0; i < count; i++) {
338 rstate = (struct r600_context_state *)views[i];
339 rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
340 }
341 rctx->ps_nsampler_view = count;
342 }
343
344 static void r600_set_vs_sampler_view(struct pipe_context *ctx,
345 unsigned count,
346 struct pipe_sampler_view **views)
347 {
348 struct r600_context *rctx = r600_context(ctx);
349 struct r600_context_state *rstate;
350 unsigned i;
351
352 for (i = 0; i < rctx->vs_nsampler_view; i++) {
353 rctx->vs_sampler_view[i] = r600_context_state_decref(rctx->vs_sampler_view[i]);
354 }
355 for (i = 0; i < count; i++) {
356 rstate = (struct r600_context_state *)views[i];
357 rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
358 }
359 rctx->vs_nsampler_view = count;
360 }
361
362 static void r600_set_framebuffer_state(struct pipe_context *ctx,
363 const struct pipe_framebuffer_state *state)
364 {
365 struct r600_context *rctx = r600_context(ctx);
366 struct r600_context_state *rstate;
367
368 rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
369 r600_bind_state(ctx, rstate);
370 }
371
372 static void r600_set_polygon_stipple(struct pipe_context *ctx,
373 const struct pipe_poly_stipple *state)
374 {
375 }
376
377 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
378 {
379 }
380
381 static void r600_set_scissor_state(struct pipe_context *ctx,
382 const struct pipe_scissor_state *state)
383 {
384 struct r600_context *rctx = r600_context(ctx);
385 struct r600_context_state *rstate;
386
387 rstate = r600_context_state(rctx, pipe_scissor_type, state);
388 r600_bind_state(ctx, rstate);
389 /* refcount is taken care of this */
390 r600_delete_state(ctx, rstate);
391 }
392
393 static void r600_set_stencil_ref(struct pipe_context *ctx,
394 const struct pipe_stencil_ref *state)
395 {
396 struct r600_context *rctx = r600_context(ctx);
397 struct r600_context_state *rstate;
398
399 rstate = r600_context_state(rctx, pipe_stencil_ref_type, state);
400 r600_bind_state(ctx, rstate);
401 /* refcount is taken care of this */
402 r600_delete_state(ctx, rstate);
403 }
404
405 static void r600_set_vertex_buffers(struct pipe_context *ctx,
406 unsigned count,
407 const struct pipe_vertex_buffer *buffers)
408 {
409 struct r600_context *rctx = r600_context(ctx);
410 unsigned i;
411
412 for (i = 0; i < rctx->nvertex_buffer; i++) {
413 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
414 }
415 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
416 for (i = 0; i < count; i++) {
417 rctx->vertex_buffer[i].buffer = NULL;
418 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
419 }
420 rctx->nvertex_buffer = count;
421 }
422
423 static void r600_set_index_buffer(struct pipe_context *ctx,
424 const struct pipe_index_buffer *ib)
425 {
426 struct r600_context *rctx = r600_context(ctx);
427
428 if (ib) {
429 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
430 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
431 } else {
432 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
433 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
434 }
435
436 /* TODO make this more like a state */
437 }
438
439 static void r600_set_viewport_state(struct pipe_context *ctx,
440 const struct pipe_viewport_state *state)
441 {
442 struct r600_context *rctx = r600_context(ctx);
443 struct r600_context_state *rstate;
444
445 rstate = r600_context_state(rctx, pipe_viewport_type, state);
446 r600_bind_state(ctx, rstate);
447 r600_delete_state(ctx, rstate);
448 }
449
450 void r600_init_state_functions(struct r600_context *rctx)
451 {
452 rctx->context.create_blend_state = r600_create_blend_state;
453 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
454 rctx->context.create_fs_state = r600_create_shader_state;
455 rctx->context.create_rasterizer_state = r600_create_rs_state;
456 rctx->context.create_sampler_state = r600_create_sampler_state;
457 rctx->context.create_sampler_view = r600_create_sampler_view;
458 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
459 rctx->context.create_vs_state = r600_create_shader_state;
460 rctx->context.bind_blend_state = r600_bind_state;
461 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
462 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
463 rctx->context.bind_fs_state = r600_bind_ps_shader;
464 rctx->context.bind_rasterizer_state = r600_bind_state;
465 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
466 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
467 rctx->context.bind_vs_state = r600_bind_vs_shader;
468 rctx->context.delete_blend_state = r600_delete_state;
469 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
470 rctx->context.delete_fs_state = r600_delete_state;
471 rctx->context.delete_rasterizer_state = r600_delete_state;
472 rctx->context.delete_sampler_state = r600_delete_state;
473 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
474 rctx->context.delete_vs_state = r600_delete_state;
475 rctx->context.set_blend_color = r600_set_blend_color;
476 rctx->context.set_clip_state = r600_set_clip_state;
477 rctx->context.set_constant_buffer = r600_set_constant_buffer;
478 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
479 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
480 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
481 rctx->context.set_sample_mask = r600_set_sample_mask;
482 rctx->context.set_scissor_state = r600_set_scissor_state;
483 rctx->context.set_stencil_ref = r600_set_stencil_ref;
484 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
485 rctx->context.set_index_buffer = r600_set_index_buffer;
486 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
487 rctx->context.set_viewport_state = r600_set_viewport_state;
488 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
489 }
490
491 struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate)
492 {
493 if (rstate == NULL)
494 return NULL;
495 rstate->refcount++;
496 return rstate;
497 }
498
499 struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate)
500 {
501 unsigned i;
502
503 if (rstate == NULL)
504 return NULL;
505 if (--rstate->refcount)
506 return NULL;
507 switch (rstate->type) {
508 case pipe_sampler_view_type:
509 pipe_resource_reference(&rstate->state.sampler_view.texture, NULL);
510 break;
511 case pipe_framebuffer_type:
512 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
513 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
514 }
515 pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
516 break;
517 case pipe_viewport_type:
518 case pipe_depth_type:
519 case pipe_rasterizer_type:
520 case pipe_poly_stipple_type:
521 case pipe_scissor_type:
522 case pipe_clip_type:
523 case pipe_stencil_type:
524 case pipe_alpha_type:
525 case pipe_dsa_type:
526 case pipe_blend_type:
527 case pipe_stencil_ref_type:
528 case pipe_shader_type:
529 case pipe_sampler_type:
530 break;
531 default:
532 R600_ERR("invalid type %d\n", rstate->type);
533 return NULL;
534 }
535 radeon_state_decref(rstate->rstate);
536 FREE(rstate);
537 return NULL;
538 }
539
540 struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state)
541 {
542 struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
543 const union pipe_states *states = state;
544 unsigned i;
545 int r;
546
547 if (rstate == NULL)
548 return NULL;
549 rstate->type = type;
550 rstate->refcount = 1;
551
552 switch (rstate->type) {
553 case pipe_sampler_view_type:
554 rstate->state.sampler_view = (*states).sampler_view;
555 rstate->state.sampler_view.texture = NULL;
556 break;
557 case pipe_framebuffer_type:
558 rstate->state.framebuffer = (*states).framebuffer;
559 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
560 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i],
561 (*states).framebuffer.cbufs[i]);
562 }
563 pipe_surface_reference(&rstate->state.framebuffer.zsbuf,
564 (*states).framebuffer.zsbuf);
565 break;
566 case pipe_viewport_type:
567 rstate->state.viewport = (*states).viewport;
568 break;
569 case pipe_depth_type:
570 rstate->state.depth = (*states).depth;
571 break;
572 case pipe_rasterizer_type:
573 rstate->state.rasterizer = (*states).rasterizer;
574 break;
575 case pipe_poly_stipple_type:
576 rstate->state.poly_stipple = (*states).poly_stipple;
577 break;
578 case pipe_scissor_type:
579 rstate->state.scissor = (*states).scissor;
580 break;
581 case pipe_clip_type:
582 rstate->state.clip = (*states).clip;
583 break;
584 case pipe_stencil_type:
585 rstate->state.stencil = (*states).stencil;
586 break;
587 case pipe_alpha_type:
588 rstate->state.alpha = (*states).alpha;
589 break;
590 case pipe_dsa_type:
591 rstate->state.dsa = (*states).dsa;
592 break;
593 case pipe_blend_type:
594 rstate->state.blend = (*states).blend;
595 break;
596 case pipe_stencil_ref_type:
597 rstate->state.stencil_ref = (*states).stencil_ref;
598 break;
599 case pipe_shader_type:
600 rstate->state.shader = (*states).shader;
601 r = r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
602 if (r) {
603 r600_context_state_decref(rstate);
604 return NULL;
605 }
606 break;
607 case pipe_sampler_type:
608 rstate->state.sampler = (*states).sampler;
609 break;
610 default:
611 R600_ERR("invalid type %d\n", rstate->type);
612 FREE(rstate);
613 return NULL;
614 }
615 return rstate;
616 }
617
618 static struct radeon_state *r600_blend(struct r600_context *rctx)
619 {
620 struct r600_screen *rscreen = rctx->screen;
621 struct radeon_state *rstate;
622 const struct pipe_blend_state *state = &rctx->blend->state.blend;
623 int i;
624
625 rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
626 if (rstate == NULL)
627 return NULL;
628 rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
629 rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
630 rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
631 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
632 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
633 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
634 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
635 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
636 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
637 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
638 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
639 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
640 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
641
642 for (i = 0; i < 8; i++) {
643 unsigned eqRGB = state->rt[i].rgb_func;
644 unsigned srcRGB = state->rt[i].rgb_src_factor;
645 unsigned dstRGB = state->rt[i].rgb_dst_factor;
646
647 unsigned eqA = state->rt[i].alpha_func;
648 unsigned srcA = state->rt[i].alpha_src_factor;
649 unsigned dstA = state->rt[i].alpha_dst_factor;
650 uint32_t bc = 0;
651
652 if (!state->rt[i].blend_enable)
653 continue;
654
655 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
656 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
657 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
658
659 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
660 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
661 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
662 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
663 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
664 }
665
666 rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
667 if (i == 0)
668 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
669 }
670
671 if (radeon_state_pm4(rstate)) {
672 radeon_state_decref(rstate);
673 return NULL;
674 }
675 return rstate;
676 }
677
678 static struct radeon_state *r600_ucp(struct r600_context *rctx, int clip)
679 {
680 struct r600_screen *rscreen = rctx->screen;
681 struct radeon_state *rstate;
682 const struct pipe_clip_state *state = &rctx->clip->state.clip;
683
684 rstate = radeon_state(rscreen->rw, R600_CLIP_TYPE, R600_CLIP + clip);
685 if (rstate == NULL)
686 return NULL;
687
688 rstate->states[R600_CLIP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]);
689 rstate->states[R600_CLIP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]);
690 rstate->states[R600_CLIP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]);
691 rstate->states[R600_CLIP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]);
692
693 if (radeon_state_pm4(rstate)) {
694 radeon_state_decref(rstate);
695 return NULL;
696 }
697 return rstate;
698
699 }
700
701 static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
702 {
703 struct r600_screen *rscreen = rctx->screen;
704 struct r600_resource_texture *rtex;
705 struct r600_resource *rbuffer;
706 struct radeon_state *rstate;
707 const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
708 unsigned level = state->cbufs[cb]->level;
709 unsigned pitch, slice;
710 unsigned color_info;
711 unsigned format, swap, ntype;
712 const struct util_format_description *desc;
713
714 rstate = radeon_state(rscreen->rw, R600_CB0_TYPE + cb, R600_CB0 + cb);
715 if (rstate == NULL)
716 return NULL;
717 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
718 rbuffer = &rtex->resource;
719 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
720 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
721 rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
722 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
723 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
724 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
725 rstate->nbo = 3;
726 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
727 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
728
729 ntype = 0;
730 desc = util_format_description(rtex->resource.base.b.format);
731 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
732 ntype = V_0280A0_NUMBER_SRGB;
733
734 format = r600_translate_colorformat(rtex->resource.base.b.format);
735 swap = r600_translate_colorswap(rtex->resource.base.b.format);
736
737 color_info = S_0280A0_FORMAT(format) |
738 S_0280A0_COMP_SWAP(swap) |
739 S_0280A0_BLEND_CLAMP(1) |
740 S_0280A0_SOURCE_FORMAT(1) |
741 S_0280A0_NUMBER_TYPE(ntype);
742
743 rstate->states[R600_CB0__CB_COLOR0_BASE] = rtex->offset[level] >> 8;
744 rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
745 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
746 S_028060_SLICE_TILE_MAX(slice);
747 rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
748 rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
749 rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
750 rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
751 if (radeon_state_pm4(rstate)) {
752 radeon_state_decref(rstate);
753 return NULL;
754 }
755 return rstate;
756 }
757
758 static struct radeon_state *r600_db(struct r600_context *rctx)
759 {
760 struct r600_screen *rscreen = rctx->screen;
761 struct r600_resource_texture *rtex;
762 struct r600_resource *rbuffer;
763 struct radeon_state *rstate;
764 const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
765 unsigned level;
766 unsigned pitch, slice, format;
767
768 if (state->zsbuf == NULL)
769 return NULL;
770
771 rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
772 if (rstate == NULL)
773 return NULL;
774
775 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
776 rbuffer = &rtex->resource;
777 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
778 rstate->nbo = 1;
779 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
780 level = state->zsbuf->level;
781 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
782 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
783 format = r600_translate_dbformat(state->zsbuf->texture->format);
784 rstate->states[R600_DB__DB_DEPTH_BASE] = rtex->offset[level] >> 8;
785 rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010000 |
786 S_028010_FORMAT(format);
787 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
788 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
789 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
790 S_028000_SLICE_TILE_MAX(slice);
791 if (radeon_state_pm4(rstate)) {
792 radeon_state_decref(rstate);
793 return NULL;
794 }
795 return rstate;
796 }
797
798 static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
799 {
800 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
801 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
802 const struct pipe_clip_state *clip = NULL;
803 struct r600_screen *rscreen = rctx->screen;
804 struct radeon_state *rstate;
805 float offset_units = 0, offset_scale = 0;
806 char depth = 0;
807 unsigned offset_db_fmt_cntl = 0;
808 unsigned tmp;
809 unsigned prov_vtx = 1;
810
811 if (rctx->clip)
812 clip = &rctx->clip->state.clip;
813 if (fb->zsbuf) {
814 offset_units = state->offset_units;
815 offset_scale = state->offset_scale * 12.0f;
816 switch (fb->zsbuf->texture->format) {
817 case PIPE_FORMAT_Z24X8_UNORM:
818 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
819 depth = -24;
820 offset_units *= 2.0f;
821 break;
822 case PIPE_FORMAT_Z32_FLOAT:
823 depth = -23;
824 offset_units *= 1.0f;
825 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
826 break;
827 case PIPE_FORMAT_Z16_UNORM:
828 depth = -16;
829 offset_units *= 4.0f;
830 break;
831 default:
832 R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
833 return NULL;
834 }
835 }
836 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
837
838 if (state->flatshade_first)
839 prov_vtx = 0;
840
841 rctx->flat_shade = state->flatshade;
842 rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
843 if (rstate == NULL)
844 return NULL;
845 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
846 if (state->sprite_coord_enable) {
847 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
848 S_0286D4_PNT_SPRITE_ENA(1) |
849 S_0286D4_PNT_SPRITE_OVRD_X(2) |
850 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
851 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
852 S_0286D4_PNT_SPRITE_OVRD_W(1);
853 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
854 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
855 S_0286D4_PNT_SPRITE_TOP_1(1);
856 }
857 }
858 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
859 if (clip && clip->nr) {
860 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
861 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_CLIP_DISABLE(clip->depth_clamp);
862 }
863 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] =
864 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
865 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
866 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
867 S_028814_FACE(!state->front_ccw) |
868 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
869 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
870 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
871 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] =
872 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
873 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
874 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
875 /* point size 12.4 fixed point */
876 tmp = (unsigned)(state->point_size * 8.0);
877 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
878 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
879 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
880 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
881 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
882 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
883 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
884 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
885 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
886 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
887 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
888 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
889 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
890 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
891 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
892 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
893 if (radeon_state_pm4(rstate)) {
894 radeon_state_decref(rstate);
895 return NULL;
896 }
897 return rstate;
898 }
899
900 static struct radeon_state *r600_scissor(struct r600_context *rctx)
901 {
902 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
903 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
904 struct r600_screen *rscreen = rctx->screen;
905 struct radeon_state *rstate;
906 unsigned minx, maxx, miny, maxy;
907 u32 tl, br;
908
909 if (state == NULL) {
910 minx = 0;
911 miny = 0;
912 maxx = fb->cbufs[0]->width;
913 maxy = fb->cbufs[0]->height;
914 } else {
915 minx = state->minx;
916 miny = state->miny;
917 maxx = state->maxx;
918 maxy = state->maxy;
919 }
920 tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
921 br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
922 rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
923 if (rstate == NULL)
924 return NULL;
925 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
926 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
927 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
928 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
929 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
930 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
931 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
932 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
933 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
934 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
935 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
936 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
937 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
938 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
939 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
940 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
941 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
942 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
943 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
944 if (radeon_state_pm4(rstate)) {
945 radeon_state_decref(rstate);
946 return NULL;
947 }
948 return rstate;
949 }
950
951 static struct radeon_state *r600_viewport(struct r600_context *rctx)
952 {
953 const struct pipe_viewport_state *state = &rctx->viewport->state.viewport;
954 struct r600_screen *rscreen = rctx->screen;
955 struct radeon_state *rstate;
956
957 rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
958 if (rstate == NULL)
959 return NULL;
960 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
961 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
962 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
963 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
964 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
965 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
966 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
967 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
968 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
969 if (radeon_state_pm4(rstate)) {
970 radeon_state_decref(rstate);
971 return NULL;
972 }
973 return rstate;
974 }
975
976 static struct radeon_state *r600_dsa(struct r600_context *rctx)
977 {
978 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
979 const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
980 struct r600_screen *rscreen = rctx->screen;
981 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
982 unsigned stencil_ref_mask, stencil_ref_mask_bf;
983 struct r600_shader *rshader = &rctx->ps_shader->shader;
984 struct radeon_state *rstate;
985 int i;
986
987 rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
988 if (rstate == NULL)
989 return NULL;
990
991 db_shader_control = 0x210;
992 for (i = 0; i < rshader->noutput; i++) {
993 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
994 db_shader_control |= 1;
995 }
996 stencil_ref_mask = 0;
997 stencil_ref_mask_bf = 0;
998 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
999 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1000 S_028800_ZFUNC(state->depth.func);
1001 /* set stencil enable */
1002
1003 if (state->stencil[0].enabled) {
1004 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1005 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
1006 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
1007 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
1008 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
1009
1010 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
1011 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
1012 stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
1013 if (state->stencil[1].enabled) {
1014 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1015 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
1016 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
1017 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
1018 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
1019 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
1020 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
1021 stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
1022 }
1023 }
1024
1025 alpha_test_control = 0;
1026 alpha_ref = 0;
1027 if (state->alpha.enabled) {
1028 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
1029 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
1030 alpha_ref = fui(state->alpha.ref_value);
1031 }
1032
1033 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
1034 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
1035 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
1036 rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
1037 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
1038 rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
1039 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
1040 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
1041 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
1042 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
1043 rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control;
1044 rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
1045 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
1046 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
1047 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
1048 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
1049 if (radeon_state_pm4(rstate)) {
1050 radeon_state_decref(rstate);
1051 return NULL;
1052 }
1053 return rstate;
1054 }
1055
1056 static inline unsigned r600_tex_wrap(unsigned wrap)
1057 {
1058 switch (wrap) {
1059 default:
1060 case PIPE_TEX_WRAP_REPEAT:
1061 return V_03C000_SQ_TEX_WRAP;
1062 case PIPE_TEX_WRAP_CLAMP:
1063 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1064 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1065 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1066 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1067 return V_03C000_SQ_TEX_CLAMP_BORDER;
1068 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1069 return V_03C000_SQ_TEX_MIRROR;
1070 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1071 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1072 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1073 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1074 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1075 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1076 }
1077 }
1078
1079 static inline unsigned r600_tex_filter(unsigned filter)
1080 {
1081 switch (filter) {
1082 default:
1083 case PIPE_TEX_FILTER_NEAREST:
1084 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1085 case PIPE_TEX_FILTER_LINEAR:
1086 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1087 }
1088 }
1089
1090 static inline unsigned r600_tex_mipfilter(unsigned filter)
1091 {
1092 switch (filter) {
1093 case PIPE_TEX_MIPFILTER_NEAREST:
1094 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1095 case PIPE_TEX_MIPFILTER_LINEAR:
1096 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1097 default:
1098 case PIPE_TEX_MIPFILTER_NONE:
1099 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1100 }
1101 }
1102
1103 static inline unsigned r600_tex_compare(unsigned compare)
1104 {
1105 switch (compare) {
1106 default:
1107 case PIPE_FUNC_NEVER:
1108 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1109 case PIPE_FUNC_LESS:
1110 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1111 case PIPE_FUNC_EQUAL:
1112 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1113 case PIPE_FUNC_LEQUAL:
1114 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1115 case PIPE_FUNC_GREATER:
1116 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1117 case PIPE_FUNC_NOTEQUAL:
1118 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1119 case PIPE_FUNC_GEQUAL:
1120 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1121 case PIPE_FUNC_ALWAYS:
1122 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1123 }
1124 }
1125
1126 static INLINE u32 S_FIXED(float value, u32 frac_bits)
1127 {
1128 return value * (1 << frac_bits);
1129 }
1130
1131 static struct radeon_state *r600_sampler(struct r600_context *rctx,
1132 const struct pipe_sampler_state *state,
1133 unsigned id)
1134 {
1135 struct r600_screen *rscreen = rctx->screen;
1136 struct radeon_state *rstate;
1137
1138 rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
1139 if (rstate == NULL)
1140 return NULL;
1141 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
1142 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1143 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1144 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1145 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
1146 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
1147 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1148 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func));
1149 /* FIXME LOD it depends on texture base level ... */
1150 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
1151 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1152 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1153 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
1154 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
1155 if (radeon_state_pm4(rstate)) {
1156 radeon_state_decref(rstate);
1157 return NULL;
1158 }
1159 return rstate;
1160 }
1161
1162 static inline unsigned r600_tex_swizzle(unsigned swizzle)
1163 {
1164 switch (swizzle) {
1165 case PIPE_SWIZZLE_RED:
1166 return V_038010_SQ_SEL_X;
1167 case PIPE_SWIZZLE_GREEN:
1168 return V_038010_SQ_SEL_Y;
1169 case PIPE_SWIZZLE_BLUE:
1170 return V_038010_SQ_SEL_Z;
1171 case PIPE_SWIZZLE_ALPHA:
1172 return V_038010_SQ_SEL_W;
1173 case PIPE_SWIZZLE_ZERO:
1174 return V_038010_SQ_SEL_0;
1175 default:
1176 case PIPE_SWIZZLE_ONE:
1177 return V_038010_SQ_SEL_1;
1178 }
1179 }
1180
1181 static inline unsigned r600_format_type(unsigned format_type)
1182 {
1183 switch (format_type) {
1184 default:
1185 case UTIL_FORMAT_TYPE_UNSIGNED:
1186 return V_038010_SQ_FORMAT_COMP_UNSIGNED;
1187 case UTIL_FORMAT_TYPE_SIGNED:
1188 return V_038010_SQ_FORMAT_COMP_SIGNED;
1189 case UTIL_FORMAT_TYPE_FIXED:
1190 return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
1191 }
1192 }
1193
1194 static inline unsigned r600_tex_dim(unsigned dim)
1195 {
1196 switch (dim) {
1197 default:
1198 case PIPE_TEXTURE_1D:
1199 return V_038000_SQ_TEX_DIM_1D;
1200 case PIPE_TEXTURE_2D:
1201 case PIPE_TEXTURE_RECT:
1202 return V_038000_SQ_TEX_DIM_2D;
1203 case PIPE_TEXTURE_3D:
1204 return V_038000_SQ_TEX_DIM_3D;
1205 case PIPE_TEXTURE_CUBE:
1206 return V_038000_SQ_TEX_DIM_CUBEMAP;
1207 }
1208 }
1209
1210 static struct radeon_state *r600_resource(struct r600_context *rctx,
1211 const struct pipe_sampler_view *view,
1212 unsigned id)
1213 {
1214 struct r600_screen *rscreen = rctx->screen;
1215 const struct util_format_description *desc;
1216 struct r600_resource_texture *tmp;
1217 struct r600_resource *rbuffer;
1218 struct radeon_state *rstate;
1219 unsigned format;
1220 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1221 unsigned char swizzle[4];
1222
1223 swizzle[0] = view->swizzle_r;
1224 swizzle[1] = view->swizzle_g;
1225 swizzle[2] = view->swizzle_b;
1226 swizzle[3] = view->swizzle_a;
1227 format = r600_translate_texformat(view->texture->format,
1228 swizzle,
1229 &word4, &yuv_format);
1230 if (format == ~0)
1231 return NULL;
1232 desc = util_format_description(view->texture->format);
1233 if (desc == NULL) {
1234 R600_ERR("unknow format %d\n", view->texture->format);
1235 return NULL;
1236 }
1237 rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
1238 if (rstate == NULL) {
1239 return NULL;
1240 }
1241 tmp = (struct r600_resource_texture*)view->texture;
1242 rbuffer = &tmp->resource;
1243 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1244 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1245 rstate->nbo = 2;
1246 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
1247 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
1248 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
1249 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
1250
1251 pitch = (tmp->pitch[0] / tmp->bpt);
1252 pitch = (pitch + 0x7) & ~0x7;
1253
1254 /* FIXME properly handle first level != 0 */
1255 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
1256 S_038000_DIM(r600_tex_dim(view->texture->target)) |
1257 S_038000_PITCH((pitch / 8) - 1) |
1258 S_038000_TEX_WIDTH(view->texture->width0 - 1);
1259 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
1260 S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
1261 S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
1262 S_038004_DATA_FORMAT(format);
1263 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
1264 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
1265 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
1266 word4 |
1267 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
1268 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
1269 S_038010_REQUEST_SIZE(1) |
1270 S_038010_BASE_LEVEL(view->first_level);
1271 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
1272 S_038014_LAST_LEVEL(view->last_level) |
1273 S_038014_BASE_ARRAY(0) |
1274 S_038014_LAST_ARRAY(0);
1275 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
1276 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
1277 if (radeon_state_pm4(rstate)) {
1278 radeon_state_decref(rstate);
1279 return NULL;
1280 }
1281 return rstate;
1282 }
1283
1284 static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
1285 {
1286 struct r600_screen *rscreen = rctx->screen;
1287 struct radeon_state *rstate;
1288 const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
1289 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
1290 uint32_t color_control, target_mask, shader_mask;
1291 int i;
1292
1293 target_mask = 0;
1294 shader_mask = 0;
1295 color_control = S_028808_PER_MRT_BLEND(1);
1296
1297 for (i = 0; i < nr_cbufs; i++) {
1298 shader_mask |= 0xf << (i * 4);
1299 }
1300
1301 if (pbs->logicop_enable) {
1302 color_control |= (pbs->logicop_func) << 16;
1303 } else {
1304 color_control |= (0xcc << 16);
1305 }
1306
1307 if (pbs->independent_blend_enable) {
1308 for (i = 0; i < nr_cbufs; i++) {
1309 if (pbs->rt[i].blend_enable) {
1310 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1311 }
1312 target_mask |= (pbs->rt[i].colormask << (4 * i));
1313 }
1314 } else {
1315 for (i = 0; i < nr_cbufs; i++) {
1316 if (pbs->rt[0].blend_enable) {
1317 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1318 }
1319 target_mask |= (pbs->rt[0].colormask << (4 * i));
1320 }
1321 }
1322 rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
1323 rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
1324 rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
1325 rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
1326 rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
1327 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
1328 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
1329 rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
1330 rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
1331 rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
1332 rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
1333 rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
1334 if (radeon_state_pm4(rstate)) {
1335 radeon_state_decref(rstate);
1336 return NULL;
1337 }
1338 return rstate;
1339 }
1340
1341 int r600_context_hw_states(struct r600_context *rctx)
1342 {
1343 unsigned i;
1344 int r;
1345 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
1346 int ucp_nclip = 0;
1347
1348 if (rctx->clip)
1349 ucp_nclip = rctx->clip->state.clip.nr;
1350
1351 /* free previous TODO determine what need to be updated, what
1352 * doesn't
1353 */
1354 //radeon_state_decref(rctx->hw_states.config);
1355 rctx->hw_states.cb_cntl = radeon_state_decref(rctx->hw_states.cb_cntl);
1356 rctx->hw_states.db = radeon_state_decref(rctx->hw_states.db);
1357 rctx->hw_states.rasterizer = radeon_state_decref(rctx->hw_states.rasterizer);
1358 rctx->hw_states.scissor = radeon_state_decref(rctx->hw_states.scissor);
1359 rctx->hw_states.dsa = radeon_state_decref(rctx->hw_states.dsa);
1360 rctx->hw_states.blend = radeon_state_decref(rctx->hw_states.blend);
1361 rctx->hw_states.viewport = radeon_state_decref(rctx->hw_states.viewport);
1362 for (i = 0; i < 8; i++) {
1363 rctx->hw_states.cb[i] = radeon_state_decref(rctx->hw_states.cb[i]);
1364 }
1365 for (i = 0; i < 6; i++) {
1366 rctx->hw_states.ucp[i] = radeon_state_decref(rctx->hw_states.ucp[i]);
1367 }
1368 for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
1369 radeon_state_decref(rctx->hw_states.ps_resource[i]);
1370 rctx->hw_states.ps_resource[i] = NULL;
1371 }
1372 rctx->hw_states.ps_nresource = 0;
1373 for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
1374 radeon_state_decref(rctx->hw_states.ps_sampler[i]);
1375 rctx->hw_states.ps_sampler[i] = NULL;
1376 }
1377 rctx->hw_states.ps_nsampler = 0;
1378
1379 /* build new states */
1380 rctx->hw_states.rasterizer = r600_rasterizer(rctx);
1381 rctx->hw_states.scissor = r600_scissor(rctx);
1382 rctx->hw_states.dsa = r600_dsa(rctx);
1383 rctx->hw_states.blend = r600_blend(rctx);
1384 rctx->hw_states.viewport = r600_viewport(rctx);
1385 for (i = 0; i < nr_cbufs; i++) {
1386 rctx->hw_states.cb[i] = r600_cb(rctx, i);
1387 }
1388 for (i = 0; i < ucp_nclip; i++) {
1389 rctx->hw_states.ucp[i] = r600_ucp(rctx, i);
1390 }
1391 rctx->hw_states.db = r600_db(rctx);
1392 rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
1393
1394 for (i = 0; i < rctx->ps_nsampler; i++) {
1395 if (rctx->ps_sampler[i]) {
1396 rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
1397 &rctx->ps_sampler[i]->state.sampler,
1398 R600_PS_SAMPLER + i);
1399 }
1400 }
1401 rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
1402 for (i = 0; i < rctx->ps_nsampler_view; i++) {
1403 if (rctx->ps_sampler_view[i]) {
1404 rctx->hw_states.ps_resource[i] = r600_resource(rctx,
1405 &rctx->ps_sampler_view[i]->state.sampler_view,
1406 R600_PS_RESOURCE + i);
1407 }
1408 }
1409 rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
1410
1411 /* bind states */
1412 for (i = 0; i < ucp_nclip; i++) {
1413 r = radeon_draw_set(rctx->draw, rctx->hw_states.ucp[i]);
1414 if (r)
1415 return r;
1416 }
1417 r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
1418 if (r)
1419 return r;
1420 r = radeon_draw_set(rctx->draw, rctx->hw_states.rasterizer);
1421 if (r)
1422 return r;
1423 r = radeon_draw_set(rctx->draw, rctx->hw_states.scissor);
1424 if (r)
1425 return r;
1426 r = radeon_draw_set(rctx->draw, rctx->hw_states.dsa);
1427 if (r)
1428 return r;
1429 r = radeon_draw_set(rctx->draw, rctx->hw_states.blend);
1430 if (r)
1431 return r;
1432 r = radeon_draw_set(rctx->draw, rctx->hw_states.viewport);
1433 if (r)
1434 return r;
1435 for (i = 0; i < nr_cbufs; i++) {
1436 r = radeon_draw_set(rctx->draw, rctx->hw_states.cb[i]);
1437 if (r)
1438 return r;
1439 }
1440 r = radeon_draw_set(rctx->draw, rctx->hw_states.config);
1441 if (r)
1442 return r;
1443 r = radeon_draw_set(rctx->draw, rctx->hw_states.cb_cntl);
1444 if (r)
1445 return r;
1446 for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
1447 if (rctx->hw_states.ps_resource[i]) {
1448 r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_resource[i]);
1449 if (r)
1450 return r;
1451 }
1452 }
1453 for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
1454 if (rctx->hw_states.ps_sampler[i]) {
1455 r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_sampler[i]);
1456 if (r)
1457 return r;
1458 }
1459 }
1460 return 0;
1461 }