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3e5958af2a3bcaf7f16970529f207c2365a85316
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600d.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31
32 static uint32_t r600_translate_blend_function(int blend_func)
33 {
34 switch (blend_func) {
35 case PIPE_BLEND_ADD:
36 return V_028804_COMB_DST_PLUS_SRC;
37 case PIPE_BLEND_SUBTRACT:
38 return V_028804_COMB_SRC_MINUS_DST;
39 case PIPE_BLEND_REVERSE_SUBTRACT:
40 return V_028804_COMB_DST_MINUS_SRC;
41 case PIPE_BLEND_MIN:
42 return V_028804_COMB_MIN_DST_SRC;
43 case PIPE_BLEND_MAX:
44 return V_028804_COMB_MAX_DST_SRC;
45 default:
46 R600_ERR("Unknown blend function %d\n", blend_func);
47 assert(0);
48 break;
49 }
50 return 0;
51 }
52
53 static uint32_t r600_translate_blend_factor(int blend_fact)
54 {
55 switch (blend_fact) {
56 case PIPE_BLENDFACTOR_ONE:
57 return V_028804_BLEND_ONE;
58 case PIPE_BLENDFACTOR_SRC_COLOR:
59 return V_028804_BLEND_SRC_COLOR;
60 case PIPE_BLENDFACTOR_SRC_ALPHA:
61 return V_028804_BLEND_SRC_ALPHA;
62 case PIPE_BLENDFACTOR_DST_ALPHA:
63 return V_028804_BLEND_DST_ALPHA;
64 case PIPE_BLENDFACTOR_DST_COLOR:
65 return V_028804_BLEND_DST_COLOR;
66 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
67 return V_028804_BLEND_SRC_ALPHA_SATURATE;
68 case PIPE_BLENDFACTOR_CONST_COLOR:
69 return V_028804_BLEND_CONST_COLOR;
70 case PIPE_BLENDFACTOR_CONST_ALPHA:
71 return V_028804_BLEND_CONST_ALPHA;
72 case PIPE_BLENDFACTOR_ZERO:
73 return V_028804_BLEND_ZERO;
74 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
75 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
76 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
77 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
78 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
79 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
80 case PIPE_BLENDFACTOR_INV_DST_COLOR:
81 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
82 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
83 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
84 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
85 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
86 case PIPE_BLENDFACTOR_SRC1_COLOR:
87 return V_028804_BLEND_SRC1_COLOR;
88 case PIPE_BLENDFACTOR_SRC1_ALPHA:
89 return V_028804_BLEND_SRC1_ALPHA;
90 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
91 return V_028804_BLEND_INV_SRC1_COLOR;
92 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
93 return V_028804_BLEND_INV_SRC1_ALPHA;
94 default:
95 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
96 assert(0);
97 break;
98 }
99 return 0;
100 }
101
102 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
103 {
104 switch (dim) {
105 default:
106 case PIPE_TEXTURE_1D:
107 return V_038000_SQ_TEX_DIM_1D;
108 case PIPE_TEXTURE_1D_ARRAY:
109 return V_038000_SQ_TEX_DIM_1D_ARRAY;
110 case PIPE_TEXTURE_2D:
111 case PIPE_TEXTURE_RECT:
112 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
113 V_038000_SQ_TEX_DIM_2D;
114 case PIPE_TEXTURE_2D_ARRAY:
115 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
116 V_038000_SQ_TEX_DIM_2D_ARRAY;
117 case PIPE_TEXTURE_3D:
118 return V_038000_SQ_TEX_DIM_3D;
119 case PIPE_TEXTURE_CUBE:
120 return V_038000_SQ_TEX_DIM_CUBEMAP;
121 }
122 }
123
124 static uint32_t r600_translate_dbformat(enum pipe_format format)
125 {
126 switch (format) {
127 case PIPE_FORMAT_Z16_UNORM:
128 return V_028010_DEPTH_16;
129 case PIPE_FORMAT_Z24X8_UNORM:
130 return V_028010_DEPTH_X8_24;
131 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
132 return V_028010_DEPTH_8_24;
133 case PIPE_FORMAT_Z32_FLOAT:
134 return V_028010_DEPTH_32_FLOAT;
135 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
136 return V_028010_DEPTH_X24_8_32_FLOAT;
137 default:
138 return ~0U;
139 }
140 }
141
142 static uint32_t r600_translate_colorswap(enum pipe_format format)
143 {
144 switch (format) {
145 /* 8-bit buffers. */
146 case PIPE_FORMAT_A8_UNORM:
147 case PIPE_FORMAT_A8_SNORM:
148 case PIPE_FORMAT_A8_UINT:
149 case PIPE_FORMAT_A8_SINT:
150 case PIPE_FORMAT_A16_UNORM:
151 case PIPE_FORMAT_A16_SNORM:
152 case PIPE_FORMAT_A16_UINT:
153 case PIPE_FORMAT_A16_SINT:
154 case PIPE_FORMAT_A16_FLOAT:
155 case PIPE_FORMAT_A32_UINT:
156 case PIPE_FORMAT_A32_SINT:
157 case PIPE_FORMAT_A32_FLOAT:
158 case PIPE_FORMAT_R4A4_UNORM:
159 return V_0280A0_SWAP_ALT_REV;
160 case PIPE_FORMAT_I8_UNORM:
161 case PIPE_FORMAT_I8_SNORM:
162 case PIPE_FORMAT_I8_UINT:
163 case PIPE_FORMAT_I8_SINT:
164 case PIPE_FORMAT_L8_UNORM:
165 case PIPE_FORMAT_L8_SNORM:
166 case PIPE_FORMAT_L8_UINT:
167 case PIPE_FORMAT_L8_SINT:
168 case PIPE_FORMAT_L8_SRGB:
169 case PIPE_FORMAT_L16_UNORM:
170 case PIPE_FORMAT_L16_SNORM:
171 case PIPE_FORMAT_L16_UINT:
172 case PIPE_FORMAT_L16_SINT:
173 case PIPE_FORMAT_L16_FLOAT:
174 case PIPE_FORMAT_L32_UINT:
175 case PIPE_FORMAT_L32_SINT:
176 case PIPE_FORMAT_L32_FLOAT:
177 case PIPE_FORMAT_I16_UNORM:
178 case PIPE_FORMAT_I16_SNORM:
179 case PIPE_FORMAT_I16_UINT:
180 case PIPE_FORMAT_I16_SINT:
181 case PIPE_FORMAT_I16_FLOAT:
182 case PIPE_FORMAT_I32_UINT:
183 case PIPE_FORMAT_I32_SINT:
184 case PIPE_FORMAT_I32_FLOAT:
185 case PIPE_FORMAT_R8_UNORM:
186 case PIPE_FORMAT_R8_SNORM:
187 case PIPE_FORMAT_R8_UINT:
188 case PIPE_FORMAT_R8_SINT:
189 return V_0280A0_SWAP_STD;
190
191 case PIPE_FORMAT_L4A4_UNORM:
192 case PIPE_FORMAT_A4R4_UNORM:
193 return V_0280A0_SWAP_ALT;
194
195 /* 16-bit buffers. */
196 case PIPE_FORMAT_B5G6R5_UNORM:
197 return V_0280A0_SWAP_STD_REV;
198
199 case PIPE_FORMAT_B5G5R5A1_UNORM:
200 case PIPE_FORMAT_B5G5R5X1_UNORM:
201 return V_0280A0_SWAP_ALT;
202
203 case PIPE_FORMAT_B4G4R4A4_UNORM:
204 case PIPE_FORMAT_B4G4R4X4_UNORM:
205 return V_0280A0_SWAP_ALT;
206
207 case PIPE_FORMAT_Z16_UNORM:
208 return V_0280A0_SWAP_STD;
209
210 case PIPE_FORMAT_L8A8_UNORM:
211 case PIPE_FORMAT_L8A8_SNORM:
212 case PIPE_FORMAT_L8A8_UINT:
213 case PIPE_FORMAT_L8A8_SINT:
214 case PIPE_FORMAT_L8A8_SRGB:
215 case PIPE_FORMAT_L16A16_UNORM:
216 case PIPE_FORMAT_L16A16_SNORM:
217 case PIPE_FORMAT_L16A16_UINT:
218 case PIPE_FORMAT_L16A16_SINT:
219 case PIPE_FORMAT_L16A16_FLOAT:
220 case PIPE_FORMAT_L32A32_UINT:
221 case PIPE_FORMAT_L32A32_SINT:
222 case PIPE_FORMAT_L32A32_FLOAT:
223 return V_0280A0_SWAP_ALT;
224 case PIPE_FORMAT_R8G8_UNORM:
225 case PIPE_FORMAT_R8G8_SNORM:
226 case PIPE_FORMAT_R8G8_UINT:
227 case PIPE_FORMAT_R8G8_SINT:
228 return V_0280A0_SWAP_STD;
229
230 case PIPE_FORMAT_R16_UNORM:
231 case PIPE_FORMAT_R16_SNORM:
232 case PIPE_FORMAT_R16_UINT:
233 case PIPE_FORMAT_R16_SINT:
234 case PIPE_FORMAT_R16_FLOAT:
235 return V_0280A0_SWAP_STD;
236
237 /* 32-bit buffers. */
238
239 case PIPE_FORMAT_A8B8G8R8_SRGB:
240 return V_0280A0_SWAP_STD_REV;
241 case PIPE_FORMAT_B8G8R8A8_SRGB:
242 return V_0280A0_SWAP_ALT;
243
244 case PIPE_FORMAT_B8G8R8A8_UNORM:
245 case PIPE_FORMAT_B8G8R8X8_UNORM:
246 return V_0280A0_SWAP_ALT;
247
248 case PIPE_FORMAT_A8R8G8B8_UNORM:
249 case PIPE_FORMAT_X8R8G8B8_UNORM:
250 return V_0280A0_SWAP_ALT_REV;
251 case PIPE_FORMAT_R8G8B8A8_SNORM:
252 case PIPE_FORMAT_R8G8B8A8_UNORM:
253 case PIPE_FORMAT_R8G8B8X8_UNORM:
254 case PIPE_FORMAT_R8G8B8A8_SINT:
255 case PIPE_FORMAT_R8G8B8A8_UINT:
256 return V_0280A0_SWAP_STD;
257
258 case PIPE_FORMAT_A8B8G8R8_UNORM:
259 case PIPE_FORMAT_X8B8G8R8_UNORM:
260 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
261 return V_0280A0_SWAP_STD_REV;
262
263 case PIPE_FORMAT_Z24X8_UNORM:
264 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
265 return V_0280A0_SWAP_STD;
266
267 case PIPE_FORMAT_X8Z24_UNORM:
268 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
269 return V_0280A0_SWAP_STD;
270
271 case PIPE_FORMAT_R10G10B10A2_UNORM:
272 case PIPE_FORMAT_R10G10B10X2_SNORM:
273 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
274 return V_0280A0_SWAP_STD;
275
276 case PIPE_FORMAT_B10G10R10A2_UNORM:
277 case PIPE_FORMAT_B10G10R10A2_UINT:
278 return V_0280A0_SWAP_ALT;
279
280 case PIPE_FORMAT_R11G11B10_FLOAT:
281 case PIPE_FORMAT_R16G16_UNORM:
282 case PIPE_FORMAT_R16G16_SNORM:
283 case PIPE_FORMAT_R16G16_FLOAT:
284 case PIPE_FORMAT_R16G16_UINT:
285 case PIPE_FORMAT_R16G16_SINT:
286 case PIPE_FORMAT_R32_UINT:
287 case PIPE_FORMAT_R32_SINT:
288 case PIPE_FORMAT_R32_FLOAT:
289 case PIPE_FORMAT_Z32_FLOAT:
290 return V_0280A0_SWAP_STD;
291
292 /* 64-bit buffers. */
293 case PIPE_FORMAT_R32G32_FLOAT:
294 case PIPE_FORMAT_R32G32_UINT:
295 case PIPE_FORMAT_R32G32_SINT:
296 case PIPE_FORMAT_R16G16B16A16_UNORM:
297 case PIPE_FORMAT_R16G16B16A16_SNORM:
298 case PIPE_FORMAT_R16G16B16A16_UINT:
299 case PIPE_FORMAT_R16G16B16A16_SINT:
300 case PIPE_FORMAT_R16G16B16A16_FLOAT:
301 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
302
303 /* 128-bit buffers. */
304 case PIPE_FORMAT_R32G32B32A32_FLOAT:
305 case PIPE_FORMAT_R32G32B32A32_SNORM:
306 case PIPE_FORMAT_R32G32B32A32_UNORM:
307 case PIPE_FORMAT_R32G32B32A32_SINT:
308 case PIPE_FORMAT_R32G32B32A32_UINT:
309 return V_0280A0_SWAP_STD;
310 default:
311 R600_ERR("unsupported colorswap format %d\n", format);
312 return ~0U;
313 }
314 return ~0U;
315 }
316
317 static uint32_t r600_translate_colorformat(enum pipe_format format)
318 {
319 switch (format) {
320 case PIPE_FORMAT_L4A4_UNORM:
321 case PIPE_FORMAT_R4A4_UNORM:
322 case PIPE_FORMAT_A4R4_UNORM:
323 return V_0280A0_COLOR_4_4;
324
325 /* 8-bit buffers. */
326 case PIPE_FORMAT_A8_UNORM:
327 case PIPE_FORMAT_A8_SNORM:
328 case PIPE_FORMAT_A8_UINT:
329 case PIPE_FORMAT_A8_SINT:
330 case PIPE_FORMAT_I8_UNORM:
331 case PIPE_FORMAT_I8_SNORM:
332 case PIPE_FORMAT_I8_UINT:
333 case PIPE_FORMAT_I8_SINT:
334 case PIPE_FORMAT_L8_UNORM:
335 case PIPE_FORMAT_L8_SNORM:
336 case PIPE_FORMAT_L8_UINT:
337 case PIPE_FORMAT_L8_SINT:
338 case PIPE_FORMAT_L8_SRGB:
339 case PIPE_FORMAT_R8_UNORM:
340 case PIPE_FORMAT_R8_SNORM:
341 case PIPE_FORMAT_R8_UINT:
342 case PIPE_FORMAT_R8_SINT:
343 return V_0280A0_COLOR_8;
344
345 /* 16-bit buffers. */
346 case PIPE_FORMAT_B5G6R5_UNORM:
347 return V_0280A0_COLOR_5_6_5;
348
349 case PIPE_FORMAT_B5G5R5A1_UNORM:
350 case PIPE_FORMAT_B5G5R5X1_UNORM:
351 return V_0280A0_COLOR_1_5_5_5;
352
353 case PIPE_FORMAT_B4G4R4A4_UNORM:
354 case PIPE_FORMAT_B4G4R4X4_UNORM:
355 return V_0280A0_COLOR_4_4_4_4;
356
357 case PIPE_FORMAT_Z16_UNORM:
358 return V_0280A0_COLOR_16;
359
360 case PIPE_FORMAT_L8A8_UNORM:
361 case PIPE_FORMAT_L8A8_SNORM:
362 case PIPE_FORMAT_L8A8_UINT:
363 case PIPE_FORMAT_L8A8_SINT:
364 case PIPE_FORMAT_L8A8_SRGB:
365 case PIPE_FORMAT_R8G8_UNORM:
366 case PIPE_FORMAT_R8G8_SNORM:
367 case PIPE_FORMAT_R8G8_UINT:
368 case PIPE_FORMAT_R8G8_SINT:
369 return V_0280A0_COLOR_8_8;
370
371 case PIPE_FORMAT_R16_UNORM:
372 case PIPE_FORMAT_R16_SNORM:
373 case PIPE_FORMAT_R16_UINT:
374 case PIPE_FORMAT_R16_SINT:
375 case PIPE_FORMAT_A16_UNORM:
376 case PIPE_FORMAT_A16_SNORM:
377 case PIPE_FORMAT_A16_UINT:
378 case PIPE_FORMAT_A16_SINT:
379 case PIPE_FORMAT_L16_UNORM:
380 case PIPE_FORMAT_L16_SNORM:
381 case PIPE_FORMAT_L16_UINT:
382 case PIPE_FORMAT_L16_SINT:
383 case PIPE_FORMAT_I16_UNORM:
384 case PIPE_FORMAT_I16_SNORM:
385 case PIPE_FORMAT_I16_UINT:
386 case PIPE_FORMAT_I16_SINT:
387 return V_0280A0_COLOR_16;
388
389 case PIPE_FORMAT_R16_FLOAT:
390 case PIPE_FORMAT_A16_FLOAT:
391 case PIPE_FORMAT_L16_FLOAT:
392 case PIPE_FORMAT_I16_FLOAT:
393 return V_0280A0_COLOR_16_FLOAT;
394
395 /* 32-bit buffers. */
396 case PIPE_FORMAT_A8B8G8R8_SRGB:
397 case PIPE_FORMAT_A8B8G8R8_UNORM:
398 case PIPE_FORMAT_A8R8G8B8_UNORM:
399 case PIPE_FORMAT_B8G8R8A8_SRGB:
400 case PIPE_FORMAT_B8G8R8A8_UNORM:
401 case PIPE_FORMAT_B8G8R8X8_UNORM:
402 case PIPE_FORMAT_R8G8B8A8_SNORM:
403 case PIPE_FORMAT_R8G8B8A8_UNORM:
404 case PIPE_FORMAT_R8G8B8X8_UNORM:
405 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
406 case PIPE_FORMAT_X8B8G8R8_UNORM:
407 case PIPE_FORMAT_X8R8G8B8_UNORM:
408 case PIPE_FORMAT_R8G8B8A8_SINT:
409 case PIPE_FORMAT_R8G8B8A8_UINT:
410 return V_0280A0_COLOR_8_8_8_8;
411
412 case PIPE_FORMAT_R10G10B10A2_UNORM:
413 case PIPE_FORMAT_R10G10B10X2_SNORM:
414 case PIPE_FORMAT_B10G10R10A2_UNORM:
415 case PIPE_FORMAT_B10G10R10A2_UINT:
416 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
417 return V_0280A0_COLOR_2_10_10_10;
418
419 case PIPE_FORMAT_Z24X8_UNORM:
420 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
421 return V_0280A0_COLOR_8_24;
422
423 case PIPE_FORMAT_X8Z24_UNORM:
424 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
425 return V_0280A0_COLOR_24_8;
426
427 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
428 return V_0280A0_COLOR_X24_8_32_FLOAT;
429
430 case PIPE_FORMAT_R32_UINT:
431 case PIPE_FORMAT_R32_SINT:
432 case PIPE_FORMAT_A32_UINT:
433 case PIPE_FORMAT_A32_SINT:
434 case PIPE_FORMAT_L32_UINT:
435 case PIPE_FORMAT_L32_SINT:
436 case PIPE_FORMAT_I32_UINT:
437 case PIPE_FORMAT_I32_SINT:
438 return V_0280A0_COLOR_32;
439
440 case PIPE_FORMAT_R32_FLOAT:
441 case PIPE_FORMAT_A32_FLOAT:
442 case PIPE_FORMAT_L32_FLOAT:
443 case PIPE_FORMAT_I32_FLOAT:
444 case PIPE_FORMAT_Z32_FLOAT:
445 return V_0280A0_COLOR_32_FLOAT;
446
447 case PIPE_FORMAT_R16G16_FLOAT:
448 case PIPE_FORMAT_L16A16_FLOAT:
449 return V_0280A0_COLOR_16_16_FLOAT;
450
451 case PIPE_FORMAT_R16G16_UNORM:
452 case PIPE_FORMAT_R16G16_SNORM:
453 case PIPE_FORMAT_R16G16_UINT:
454 case PIPE_FORMAT_R16G16_SINT:
455 case PIPE_FORMAT_L16A16_UNORM:
456 case PIPE_FORMAT_L16A16_SNORM:
457 case PIPE_FORMAT_L16A16_UINT:
458 case PIPE_FORMAT_L16A16_SINT:
459 return V_0280A0_COLOR_16_16;
460
461 case PIPE_FORMAT_R11G11B10_FLOAT:
462 return V_0280A0_COLOR_10_11_11_FLOAT;
463
464 /* 64-bit buffers. */
465 case PIPE_FORMAT_R16G16B16A16_UINT:
466 case PIPE_FORMAT_R16G16B16A16_SINT:
467 case PIPE_FORMAT_R16G16B16A16_UNORM:
468 case PIPE_FORMAT_R16G16B16A16_SNORM:
469 return V_0280A0_COLOR_16_16_16_16;
470
471 case PIPE_FORMAT_R16G16B16A16_FLOAT:
472 return V_0280A0_COLOR_16_16_16_16_FLOAT;
473
474 case PIPE_FORMAT_R32G32_FLOAT:
475 case PIPE_FORMAT_L32A32_FLOAT:
476 return V_0280A0_COLOR_32_32_FLOAT;
477
478 case PIPE_FORMAT_R32G32_SINT:
479 case PIPE_FORMAT_R32G32_UINT:
480 case PIPE_FORMAT_L32A32_UINT:
481 case PIPE_FORMAT_L32A32_SINT:
482 return V_0280A0_COLOR_32_32;
483
484 /* 128-bit buffers. */
485 case PIPE_FORMAT_R32G32B32A32_FLOAT:
486 return V_0280A0_COLOR_32_32_32_32_FLOAT;
487 case PIPE_FORMAT_R32G32B32A32_SNORM:
488 case PIPE_FORMAT_R32G32B32A32_UNORM:
489 case PIPE_FORMAT_R32G32B32A32_SINT:
490 case PIPE_FORMAT_R32G32B32A32_UINT:
491 return V_0280A0_COLOR_32_32_32_32;
492
493 /* YUV buffers. */
494 case PIPE_FORMAT_UYVY:
495 case PIPE_FORMAT_YUYV:
496 default:
497 return ~0U; /* Unsupported. */
498 }
499 }
500
501 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
502 {
503 if (R600_BIG_ENDIAN) {
504 switch(colorformat) {
505 case V_0280A0_COLOR_4_4:
506 return ENDIAN_NONE;
507
508 /* 8-bit buffers. */
509 case V_0280A0_COLOR_8:
510 return ENDIAN_NONE;
511
512 /* 16-bit buffers. */
513 case V_0280A0_COLOR_5_6_5:
514 case V_0280A0_COLOR_1_5_5_5:
515 case V_0280A0_COLOR_4_4_4_4:
516 case V_0280A0_COLOR_16:
517 case V_0280A0_COLOR_8_8:
518 return ENDIAN_8IN16;
519
520 /* 32-bit buffers. */
521 case V_0280A0_COLOR_8_8_8_8:
522 case V_0280A0_COLOR_2_10_10_10:
523 case V_0280A0_COLOR_8_24:
524 case V_0280A0_COLOR_24_8:
525 case V_0280A0_COLOR_32_FLOAT:
526 case V_0280A0_COLOR_16_16_FLOAT:
527 case V_0280A0_COLOR_16_16:
528 return ENDIAN_8IN32;
529
530 /* 64-bit buffers. */
531 case V_0280A0_COLOR_16_16_16_16:
532 case V_0280A0_COLOR_16_16_16_16_FLOAT:
533 return ENDIAN_8IN16;
534
535 case V_0280A0_COLOR_32_32_FLOAT:
536 case V_0280A0_COLOR_32_32:
537 case V_0280A0_COLOR_X24_8_32_FLOAT:
538 return ENDIAN_8IN32;
539
540 /* 128-bit buffers. */
541 case V_0280A0_COLOR_32_32_32_FLOAT:
542 case V_0280A0_COLOR_32_32_32_32_FLOAT:
543 case V_0280A0_COLOR_32_32_32_32:
544 return ENDIAN_8IN32;
545 default:
546 return ENDIAN_NONE; /* Unsupported. */
547 }
548 } else {
549 return ENDIAN_NONE;
550 }
551 }
552
553 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
554 {
555 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
556 }
557
558 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
559 {
560 return r600_translate_colorformat(format) != ~0U &&
561 r600_translate_colorswap(format) != ~0U;
562 }
563
564 static bool r600_is_zs_format_supported(enum pipe_format format)
565 {
566 return r600_translate_dbformat(format) != ~0U;
567 }
568
569 boolean r600_is_format_supported(struct pipe_screen *screen,
570 enum pipe_format format,
571 enum pipe_texture_target target,
572 unsigned sample_count,
573 unsigned usage)
574 {
575 struct r600_screen *rscreen = (struct r600_screen*)screen;
576 unsigned retval = 0;
577
578 if (target >= PIPE_MAX_TEXTURE_TYPES) {
579 R600_ERR("r600: unsupported texture type %d\n", target);
580 return FALSE;
581 }
582
583 if (!util_format_is_supported(format, usage))
584 return FALSE;
585
586 if (sample_count > 1) {
587 if (rscreen->info.drm_minor < 21)
588 return FALSE;
589 if (rscreen->chip_class != R700)
590 return FALSE;
591
592 switch (sample_count) {
593 case 2:
594 case 4:
595 case 8:
596 break;
597 default:
598 return FALSE;
599 }
600
601 /* require render-target support for multisample resources */
602 if (util_format_is_depth_or_stencil(format)) {
603 usage |= PIPE_BIND_DEPTH_STENCIL;
604 } else if (util_format_is_pure_integer(format)) {
605 return FALSE;
606 } else {
607 usage |= PIPE_BIND_RENDER_TARGET;
608 }
609 }
610
611 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
612 r600_is_sampler_format_supported(screen, format)) {
613 retval |= PIPE_BIND_SAMPLER_VIEW;
614 }
615
616 if ((usage & (PIPE_BIND_RENDER_TARGET |
617 PIPE_BIND_DISPLAY_TARGET |
618 PIPE_BIND_SCANOUT |
619 PIPE_BIND_SHARED)) &&
620 r600_is_colorbuffer_format_supported(format)) {
621 retval |= usage &
622 (PIPE_BIND_RENDER_TARGET |
623 PIPE_BIND_DISPLAY_TARGET |
624 PIPE_BIND_SCANOUT |
625 PIPE_BIND_SHARED);
626 }
627
628 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
629 r600_is_zs_format_supported(format)) {
630 retval |= PIPE_BIND_DEPTH_STENCIL;
631 }
632
633 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
634 r600_is_vertex_format_supported(format)) {
635 retval |= PIPE_BIND_VERTEX_BUFFER;
636 }
637
638 if (usage & PIPE_BIND_TRANSFER_READ)
639 retval |= PIPE_BIND_TRANSFER_READ;
640 if (usage & PIPE_BIND_TRANSFER_WRITE)
641 retval |= PIPE_BIND_TRANSFER_WRITE;
642
643 return retval == usage;
644 }
645
646 void r600_polygon_offset_update(struct r600_context *rctx)
647 {
648 struct r600_pipe_state state;
649
650 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
651 state.nregs = 0;
652 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
653 float offset_units = rctx->rasterizer->offset_units;
654 unsigned offset_db_fmt_cntl = 0, depth;
655
656 switch (rctx->framebuffer.zsbuf->format) {
657 case PIPE_FORMAT_Z24X8_UNORM:
658 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
659 depth = -24;
660 offset_units *= 2.0f;
661 break;
662 case PIPE_FORMAT_Z32_FLOAT:
663 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
664 depth = -23;
665 offset_units *= 1.0f;
666 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
667 break;
668 case PIPE_FORMAT_Z16_UNORM:
669 depth = -16;
670 offset_units *= 4.0f;
671 break;
672 default:
673 return;
674 }
675 /* XXX some of those reg can be computed with cso */
676 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
677 r600_pipe_state_add_reg(&state,
678 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
679 fui(rctx->rasterizer->offset_scale));
680 r600_pipe_state_add_reg(&state,
681 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
682 fui(offset_units));
683 r600_pipe_state_add_reg(&state,
684 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
685 fui(rctx->rasterizer->offset_scale));
686 r600_pipe_state_add_reg(&state,
687 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
688 fui(offset_units));
689 r600_pipe_state_add_reg(&state,
690 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
691 offset_db_fmt_cntl);
692 r600_context_pipe_state_set(rctx, &state);
693 }
694 }
695
696 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
697 const struct pipe_blend_state *state,
698 int mode)
699 {
700 struct r600_context *rctx = (struct r600_context *)ctx;
701 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
702 struct r600_pipe_state *rstate;
703 uint32_t color_control = 0, target_mask = 0;
704
705 if (blend == NULL) {
706 return NULL;
707 }
708 rstate = &blend->rstate;
709
710 rstate->id = R600_PIPE_STATE_BLEND;
711
712 /* R600 does not support per-MRT blends */
713 if (rctx->family > CHIP_R600)
714 color_control |= S_028808_PER_MRT_BLEND(1);
715
716 if (state->logicop_enable) {
717 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
718 } else {
719 color_control |= (0xcc << 16);
720 }
721 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
722 if (state->independent_blend_enable) {
723 for (int i = 0; i < 8; i++) {
724 if (state->rt[i].blend_enable) {
725 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
726 }
727 target_mask |= (state->rt[i].colormask << (4 * i));
728 }
729 } else {
730 for (int i = 0; i < 8; i++) {
731 if (state->rt[0].blend_enable) {
732 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
733 }
734 target_mask |= (state->rt[0].colormask << (4 * i));
735 }
736 }
737
738 if (target_mask)
739 color_control |= S_028808_SPECIAL_OP(mode);
740 else
741 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
742
743 blend->cb_target_mask = target_mask;
744 blend->cb_color_control = color_control;
745 /* only MRT0 has dual src blend */
746 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
747 for (int i = 0; i < 8; i++) {
748 /* state->rt entries > 0 only written if independent blending */
749 const int j = state->independent_blend_enable ? i : 0;
750
751 unsigned eqRGB = state->rt[j].rgb_func;
752 unsigned srcRGB = state->rt[j].rgb_src_factor;
753 unsigned dstRGB = state->rt[j].rgb_dst_factor;
754
755 unsigned eqA = state->rt[j].alpha_func;
756 unsigned srcA = state->rt[j].alpha_src_factor;
757 unsigned dstA = state->rt[j].alpha_dst_factor;
758 uint32_t bc = 0;
759
760 if (!state->rt[j].blend_enable)
761 continue;
762
763 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
764 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
765 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
766
767 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
768 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
769 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
770 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
771 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
772 }
773
774 /* R600 does not support per-MRT blends */
775 if (rctx->family > CHIP_R600)
776 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc);
777 if (i == 0)
778 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
779 }
780
781 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK,
782 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
783 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
784 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
785 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
786 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
787
788 blend->alpha_to_one = state->alpha_to_one;
789 return rstate;
790 }
791
792
793 static void *r600_create_blend_state(struct pipe_context *ctx,
794 const struct pipe_blend_state *state)
795 {
796 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
797 }
798
799 static void *r600_create_dsa_state(struct pipe_context *ctx,
800 const struct pipe_depth_stencil_alpha_state *state)
801 {
802 struct r600_context *rctx = (struct r600_context *)ctx;
803 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
804 unsigned db_depth_control, alpha_test_control, alpha_ref;
805 struct r600_pipe_state *rstate;
806
807 if (dsa == NULL) {
808 return NULL;
809 }
810
811 dsa->valuemask[0] = state->stencil[0].valuemask;
812 dsa->valuemask[1] = state->stencil[1].valuemask;
813 dsa->writemask[0] = state->stencil[0].writemask;
814 dsa->writemask[1] = state->stencil[1].writemask;
815
816 rstate = &dsa->rstate;
817
818 rstate->id = R600_PIPE_STATE_DSA;
819 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
820 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
821 S_028800_ZFUNC(state->depth.func);
822
823 /* stencil */
824 if (state->stencil[0].enabled) {
825 db_depth_control |= S_028800_STENCIL_ENABLE(1);
826 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
827 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
828 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
829 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
830
831 if (state->stencil[1].enabled) {
832 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
833 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
834 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
835 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
836 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
837 }
838 }
839
840 /* alpha */
841 alpha_test_control = 0;
842 alpha_ref = 0;
843 if (state->alpha.enabled) {
844 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
845 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
846 alpha_ref = fui(state->alpha.ref_value);
847 }
848 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
849 dsa->alpha_ref = alpha_ref;
850
851 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
852 return rstate;
853 }
854
855 static void *r600_create_rs_state(struct pipe_context *ctx,
856 const struct pipe_rasterizer_state *state)
857 {
858 struct r600_context *rctx = (struct r600_context *)ctx;
859 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
860 struct r600_pipe_state *rstate;
861 unsigned tmp;
862 unsigned prov_vtx = 1, polygon_dual_mode;
863 unsigned sc_mode_cntl;
864 float psize_min, psize_max;
865
866 if (rs == NULL) {
867 return NULL;
868 }
869
870 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
871 state->fill_back != PIPE_POLYGON_MODE_FILL);
872
873 if (state->flatshade_first)
874 prov_vtx = 0;
875
876 rstate = &rs->rstate;
877 rs->flatshade = state->flatshade;
878 rs->sprite_coord_enable = state->sprite_coord_enable;
879 rs->two_side = state->light_twoside;
880 rs->clip_plane_enable = state->clip_plane_enable;
881 rs->pa_sc_line_stipple = state->line_stipple_enable ?
882 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
883 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
884 rs->pa_cl_clip_cntl =
885 S_028810_PS_UCP_MODE(3) |
886 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
887 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
888 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
889 rs->multisample_enable = state->multisample;
890
891 /* offset */
892 rs->offset_units = state->offset_units;
893 rs->offset_scale = state->offset_scale * 12.0f;
894
895 rstate->id = R600_PIPE_STATE_RASTERIZER;
896 tmp = S_0286D4_FLAT_SHADE_ENA(1);
897 if (state->sprite_coord_enable) {
898 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
899 S_0286D4_PNT_SPRITE_OVRD_X(2) |
900 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
901 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
902 S_0286D4_PNT_SPRITE_OVRD_W(1);
903 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
904 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
905 }
906 }
907 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
908
909 /* point size 12.4 fixed point */
910 tmp = r600_pack_float_12p4(state->point_size/2);
911 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
912
913 if (state->point_size_per_vertex) {
914 psize_min = util_get_min_point_size(state);
915 psize_max = 8192;
916 } else {
917 /* Force the point size to be as if the vertex output was disabled. */
918 psize_min = state->point_size;
919 psize_max = state->point_size;
920 }
921 /* Divide by two, because 0.5 = 1 pixel. */
922 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
923 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
924 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
925
926 tmp = r600_pack_float_12p4(state->line_width/2);
927 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
928
929 if (rctx->chip_class >= R700) {
930 sc_mode_cntl =
931 S_028A4C_MSAA_ENABLE(state->multisample) |
932 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
933 S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
934 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
935 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
936 } else {
937 sc_mode_cntl =
938 S_028A4C_MSAA_ENABLE(state->multisample) |
939 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
940 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
941 rs->scissor_enable = state->scissor;
942 }
943 sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
944
945 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
946
947 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
948 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
949
950 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
951 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
952 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
953 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
954 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
955 S_028814_FACE(!state->front_ccw) |
956 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
957 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
958 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
959 S_028814_POLY_MODE(polygon_dual_mode) |
960 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
961 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
962 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
963 return rstate;
964 }
965
966 static void *r600_create_sampler_state(struct pipe_context *ctx,
967 const struct pipe_sampler_state *state)
968 {
969 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
970 union util_color uc;
971 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
972
973 if (ss == NULL) {
974 return NULL;
975 }
976
977 ss->seamless_cube_map = state->seamless_cube_map;
978 ss->border_color_use = false;
979 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
980 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
981 ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
982 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
983 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
984 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
985 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
986 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
987 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
988 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
989 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
990 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
991 ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
992 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
993 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
994 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
995 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
996 if (uc.ui) {
997 ss->border_color_use = true;
998 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
999 ss->border_color[0] = fui(state->border_color.f[0]);
1000 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
1001 ss->border_color[1] = fui(state->border_color.f[1]);
1002 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
1003 ss->border_color[2] = fui(state->border_color.f[2]);
1004 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
1005 ss->border_color[3] = fui(state->border_color.f[3]);
1006 }
1007 return ss;
1008 }
1009
1010 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1011 struct pipe_resource *texture,
1012 const struct pipe_sampler_view *state)
1013 {
1014 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1015 struct r600_texture *tmp = (struct r600_texture*)texture;
1016 unsigned format, endian;
1017 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1018 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1019 unsigned width, height, depth, offset_level, last_level;
1020
1021 if (view == NULL)
1022 return NULL;
1023
1024 /* initialize base object */
1025 view->base = *state;
1026 view->base.texture = NULL;
1027 pipe_reference(NULL, &texture->reference);
1028 view->base.texture = texture;
1029 view->base.reference.count = 1;
1030 view->base.context = ctx;
1031
1032 swizzle[0] = state->swizzle_r;
1033 swizzle[1] = state->swizzle_g;
1034 swizzle[2] = state->swizzle_b;
1035 swizzle[3] = state->swizzle_a;
1036
1037 format = r600_translate_texformat(ctx->screen, state->format,
1038 swizzle,
1039 &word4, &yuv_format);
1040 assert(format != ~0);
1041 if (format == ~0) {
1042 FREE(view);
1043 return NULL;
1044 }
1045
1046 if (tmp->is_depth && !tmp->is_flushing_texture) {
1047 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1048 FREE(view);
1049 return NULL;
1050 }
1051 tmp = tmp->flushed_depth_texture;
1052 }
1053
1054 endian = r600_colorformat_endian_swap(format);
1055
1056 offset_level = state->u.tex.first_level;
1057 last_level = state->u.tex.last_level - offset_level;
1058 width = tmp->surface.level[offset_level].npix_x;
1059 height = tmp->surface.level[offset_level].npix_y;
1060 depth = tmp->surface.level[offset_level].npix_z;
1061 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1062 tile_type = tmp->tile_type;
1063
1064 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1065 height = 1;
1066 depth = texture->array_size;
1067 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1068 depth = texture->array_size;
1069 }
1070 switch (tmp->surface.level[offset_level].mode) {
1071 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1072 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1073 break;
1074 case RADEON_SURF_MODE_1D:
1075 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1076 break;
1077 case RADEON_SURF_MODE_2D:
1078 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1079 break;
1080 case RADEON_SURF_MODE_LINEAR:
1081 default:
1082 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1083 break;
1084 }
1085
1086 view->tex_resource = &tmp->resource;
1087 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1088 S_038000_TILE_MODE(array_mode) |
1089 S_038000_TILE_TYPE(tile_type) |
1090 S_038000_PITCH((pitch / 8) - 1) |
1091 S_038000_TEX_WIDTH(width - 1));
1092 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1093 S_038004_TEX_DEPTH(depth - 1) |
1094 S_038004_DATA_FORMAT(format));
1095 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1096 if (offset_level >= tmp->surface.last_level) {
1097 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1098 } else {
1099 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1100 }
1101 view->tex_resource_words[4] = (word4 |
1102 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1103 S_038010_REQUEST_SIZE(1) |
1104 S_038010_ENDIAN_SWAP(endian) |
1105 S_038010_BASE_LEVEL(0));
1106 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1107 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1108 if (texture->nr_samples > 1) {
1109 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1110 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1111 } else {
1112 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
1113 }
1114 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1115 S_038018_MAX_ANISO(4 /* max 16 samples */));
1116 return &view->base;
1117 }
1118
1119 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1120 struct pipe_sampler_view **views)
1121 {
1122 r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
1123 }
1124
1125 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1126 struct pipe_sampler_view **views)
1127 {
1128 r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
1129 }
1130
1131 static void r600_set_clip_state(struct pipe_context *ctx,
1132 const struct pipe_clip_state *state)
1133 {
1134 struct r600_context *rctx = (struct r600_context *)ctx;
1135 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1136 struct pipe_constant_buffer cb;
1137
1138 if (rstate == NULL)
1139 return;
1140
1141 rctx->clip = *state;
1142 rstate->id = R600_PIPE_STATE_CLIP;
1143 for (int i = 0; i < 6; i++) {
1144 r600_pipe_state_add_reg(rstate,
1145 R_028E20_PA_CL_UCP0_X + i * 16,
1146 fui(state->ucp[i][0]));
1147 r600_pipe_state_add_reg(rstate,
1148 R_028E24_PA_CL_UCP0_Y + i * 16,
1149 fui(state->ucp[i][1]) );
1150 r600_pipe_state_add_reg(rstate,
1151 R_028E28_PA_CL_UCP0_Z + i * 16,
1152 fui(state->ucp[i][2]));
1153 r600_pipe_state_add_reg(rstate,
1154 R_028E2C_PA_CL_UCP0_W + i * 16,
1155 fui(state->ucp[i][3]));
1156 }
1157
1158 free(rctx->states[R600_PIPE_STATE_CLIP]);
1159 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1160 r600_context_pipe_state_set(rctx, rstate);
1161
1162 cb.buffer = NULL;
1163 cb.user_buffer = state->ucp;
1164 cb.buffer_offset = 0;
1165 cb.buffer_size = 4*4*8;
1166 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1167 pipe_resource_reference(&cb.buffer, NULL);
1168 }
1169
1170 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1171 const struct pipe_poly_stipple *state)
1172 {
1173 }
1174
1175 void r600_set_scissor_state(struct r600_context *rctx,
1176 const struct pipe_scissor_state *state)
1177 {
1178 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1179 uint32_t tl, br;
1180
1181 if (rstate == NULL)
1182 return;
1183
1184 rstate->id = R600_PIPE_STATE_SCISSOR;
1185 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1186 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1187 r600_pipe_state_add_reg(rstate,
1188 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1189 r600_pipe_state_add_reg(rstate,
1190 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1191
1192 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1193 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1194 r600_context_pipe_state_set(rctx, rstate);
1195 }
1196
1197 static void r600_pipe_set_scissor_state(struct pipe_context *ctx,
1198 const struct pipe_scissor_state *state)
1199 {
1200 struct r600_context *rctx = (struct r600_context *)ctx;
1201
1202 if (rctx->chip_class == R600) {
1203 rctx->scissor_state = *state;
1204
1205 if (!rctx->scissor_enable)
1206 return;
1207 }
1208
1209 r600_set_scissor_state(rctx, state);
1210 }
1211
1212 static void r600_set_viewport_state(struct pipe_context *ctx,
1213 const struct pipe_viewport_state *state)
1214 {
1215 struct r600_context *rctx = (struct r600_context *)ctx;
1216 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1217
1218 if (rstate == NULL)
1219 return;
1220
1221 rctx->viewport = *state;
1222 rstate->id = R600_PIPE_STATE_VIEWPORT;
1223 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1224 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1225 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1226 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1227 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1228 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1229
1230 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1231 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1232 r600_context_pipe_state_set(rctx, rstate);
1233 }
1234
1235 static void r600_init_color_surface(struct r600_context *rctx,
1236 struct r600_surface *surf)
1237 {
1238 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1239 unsigned level = surf->base.u.tex.level;
1240 unsigned pitch, slice;
1241 unsigned color_info;
1242 unsigned format, swap, ntype, endian;
1243 unsigned offset;
1244 const struct util_format_description *desc;
1245 int i;
1246 bool blend_bypass = 0, blend_clamp = 1;
1247
1248 if (rtex->is_depth && !rtex->is_flushing_texture) {
1249 r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL);
1250 rtex = rtex->flushed_depth_texture;
1251 assert(rtex);
1252 }
1253
1254 offset = rtex->surface.level[level].offset;
1255 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1256 offset += rtex->surface.level[level].slice_size *
1257 surf->base.u.tex.first_layer;
1258 }
1259 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1260 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1261 if (slice) {
1262 slice = slice - 1;
1263 }
1264 color_info = 0;
1265 switch (rtex->surface.level[level].mode) {
1266 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1267 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1268 break;
1269 case RADEON_SURF_MODE_1D:
1270 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1271 break;
1272 case RADEON_SURF_MODE_2D:
1273 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1274 break;
1275 case RADEON_SURF_MODE_LINEAR:
1276 default:
1277 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1278 break;
1279 }
1280
1281 desc = util_format_description(surf->base.format);
1282
1283 for (i = 0; i < 4; i++) {
1284 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1285 break;
1286 }
1287 }
1288
1289 ntype = V_0280A0_NUMBER_UNORM;
1290 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1291 ntype = V_0280A0_NUMBER_SRGB;
1292 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1293 if (desc->channel[i].normalized)
1294 ntype = V_0280A0_NUMBER_SNORM;
1295 else if (desc->channel[i].pure_integer)
1296 ntype = V_0280A0_NUMBER_SINT;
1297 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1298 if (desc->channel[i].normalized)
1299 ntype = V_0280A0_NUMBER_UNORM;
1300 else if (desc->channel[i].pure_integer)
1301 ntype = V_0280A0_NUMBER_UINT;
1302 }
1303
1304 format = r600_translate_colorformat(surf->base.format);
1305 assert(format != ~0);
1306
1307 swap = r600_translate_colorswap(surf->base.format);
1308 assert(swap != ~0);
1309
1310 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1311 endian = ENDIAN_NONE;
1312 } else {
1313 endian = r600_colorformat_endian_swap(format);
1314 }
1315
1316 /* set blend bypass according to docs if SINT/UINT or
1317 8/24 COLOR variants */
1318 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1319 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1320 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1321 blend_clamp = 0;
1322 blend_bypass = 1;
1323 }
1324
1325 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1326
1327 color_info |= S_0280A0_FORMAT(format) |
1328 S_0280A0_COMP_SWAP(swap) |
1329 S_0280A0_BLEND_BYPASS(blend_bypass) |
1330 S_0280A0_BLEND_CLAMP(blend_clamp) |
1331 S_0280A0_NUMBER_TYPE(ntype) |
1332 S_0280A0_ENDIAN(endian);
1333
1334 /* EXPORT_NORM is an optimzation that can be enabled for better
1335 * performance in certain cases
1336 */
1337 if (rctx->chip_class == R600) {
1338 /* EXPORT_NORM can be enabled if:
1339 * - 11-bit or smaller UNORM/SNORM/SRGB
1340 * - BLEND_CLAMP is enabled
1341 * - BLEND_FLOAT32 is disabled
1342 */
1343 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1344 (desc->channel[i].size < 12 &&
1345 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1346 ntype != V_0280A0_NUMBER_UINT &&
1347 ntype != V_0280A0_NUMBER_SINT) &&
1348 G_0280A0_BLEND_CLAMP(color_info) &&
1349 !G_0280A0_BLEND_FLOAT32(color_info)) {
1350 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1351 surf->export_16bpc = true;
1352 }
1353 } else {
1354 /* EXPORT_NORM can be enabled if:
1355 * - 11-bit or smaller UNORM/SNORM/SRGB
1356 * - 16-bit or smaller FLOAT
1357 */
1358 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1359 ((desc->channel[i].size < 12 &&
1360 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1361 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1362 (desc->channel[i].size < 17 &&
1363 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1364 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1365 surf->export_16bpc = true;
1366 }
1367 }
1368
1369 surf->cb_color_base = offset >> 8;
1370 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1371 S_028060_SLICE_TILE_MAX(slice);
1372 surf->cb_color_fmask = surf->cb_color_base;
1373 surf->cb_color_cmask = surf->cb_color_base;
1374
1375 if (rtex->cmask_size) {
1376 surf->cb_color_cmask = rtex->cmask_offset >> 8;
1377 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask_slice_tile_max);
1378
1379 if (rtex->fmask_size) {
1380 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1381 surf->cb_color_fmask = rtex->fmask_offset >> 8;
1382 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(slice);
1383 } else { /* cmask only */
1384 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1385 }
1386 }
1387 surf->cb_color_info = color_info;
1388
1389 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1390 surf->cb_color_view = 0;
1391 } else {
1392 surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1393 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1394 }
1395
1396 surf->color_initialized = true;
1397 }
1398
1399 static void r600_init_depth_surface(struct r600_context *rctx,
1400 struct r600_surface *surf)
1401 {
1402 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1403 unsigned level, pitch, slice, format, offset, array_mode;
1404
1405 level = surf->base.u.tex.level;
1406 offset = rtex->surface.level[level].offset;
1407 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1408 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1409 if (slice) {
1410 slice = slice - 1;
1411 }
1412 switch (rtex->surface.level[level].mode) {
1413 case RADEON_SURF_MODE_2D:
1414 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1415 break;
1416 case RADEON_SURF_MODE_1D:
1417 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1418 case RADEON_SURF_MODE_LINEAR:
1419 default:
1420 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1421 break;
1422 }
1423
1424 format = r600_translate_dbformat(surf->base.format);
1425 assert(format != ~0);
1426
1427 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1428 surf->db_depth_base = offset >> 8;
1429 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1430 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1431 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1432 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1433
1434 surf->depth_initialized = true;
1435 }
1436
1437 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1438 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1439 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1440 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1441 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1442
1443 static uint32_t r600_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1444 {
1445 static uint32_t sample_locs_2x[] = {
1446 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1447 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1448 };
1449 static unsigned max_dist_2x = 4;
1450 static uint32_t sample_locs_4x[] = {
1451 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1452 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1453 };
1454 static unsigned max_dist_4x = 6;
1455 static uint32_t sample_locs_8x[] = {
1456 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1457 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1458 };
1459 static unsigned max_dist_8x = 8;
1460 struct r600_context *rctx = (struct r600_context *)ctx;
1461
1462 if (rctx->family == CHIP_R600) {
1463 switch (nsample) {
1464 case 0:
1465 case 1:
1466 return 0;
1467 case 2:
1468 r600_pipe_state_add_reg(rstate, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1469 return max_dist_2x;
1470 case 4:
1471 r600_pipe_state_add_reg(rstate, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1472 return max_dist_4x;
1473 case 8:
1474 r600_pipe_state_add_reg(rstate, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, sample_locs_8x[0]);
1475 r600_pipe_state_add_reg(rstate, R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1, sample_locs_8x[1]);
1476 return max_dist_8x;
1477 }
1478 } else {
1479 switch (nsample) {
1480 case 0:
1481 case 1:
1482 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0);
1483 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, 0);
1484 return 0;
1485 case 2:
1486 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_2x[0]);
1487 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_2x[1]);
1488 return max_dist_2x;
1489 case 4:
1490 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_4x[0]);
1491 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_4x[1]);
1492 return max_dist_4x;
1493 case 8:
1494 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_8x[0]);
1495 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_8x[1]);
1496 return max_dist_8x;
1497 }
1498 }
1499 R600_ERR("Invalid nr_samples %i\n", nsample);
1500 return 0;
1501 }
1502
1503 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1504 const struct pipe_framebuffer_state *state)
1505 {
1506 struct r600_context *rctx = (struct r600_context *)ctx;
1507 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1508 struct r600_surface *surf;
1509 struct r600_resource *res;
1510 struct r600_texture *rtex;
1511 uint32_t tl, br, i, nr_samples, max_dist;
1512
1513 if (rstate == NULL)
1514 return;
1515
1516 r600_flush_framebuffer(rctx, false);
1517
1518 /* unreference old buffer and reference new one */
1519 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1520
1521 util_copy_framebuffer_state(&rctx->framebuffer, state);
1522
1523 /* Colorbuffers. */
1524 rctx->export_16bpc = true;
1525 rctx->nr_cbufs = state->nr_cbufs;
1526 rctx->cb0_is_integer = state->nr_cbufs &&
1527 util_format_is_pure_integer(state->cbufs[0]->format);
1528 rctx->compressed_cb_mask = 0;
1529
1530 for (i = 0; i < state->nr_cbufs; i++) {
1531 surf = (struct r600_surface*)state->cbufs[i];
1532 res = (struct r600_resource*)surf->base.texture;
1533 rtex = (struct r600_texture*)res;
1534
1535 if (!surf->color_initialized) {
1536 r600_init_color_surface(rctx, surf);
1537 }
1538
1539 if (!surf->export_16bpc) {
1540 rctx->export_16bpc = false;
1541 }
1542
1543 r600_pipe_state_add_reg_bo(rstate, R_028040_CB_COLOR0_BASE + i * 4,
1544 surf->cb_color_base, res, RADEON_USAGE_READWRITE);
1545 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + i * 4,
1546 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1547 r600_pipe_state_add_reg(rstate, R_028060_CB_COLOR0_SIZE + i * 4,
1548 surf->cb_color_size);
1549 r600_pipe_state_add_reg(rstate, R_028080_CB_COLOR0_VIEW + i * 4,
1550 surf->cb_color_view);
1551 r600_pipe_state_add_reg_bo(rstate, R_0280E0_CB_COLOR0_FRAG + i * 4,
1552 surf->cb_color_fmask, res, RADEON_USAGE_READWRITE);
1553 r600_pipe_state_add_reg_bo(rstate, R_0280C0_CB_COLOR0_TILE + i * 4,
1554 surf->cb_color_cmask, res, RADEON_USAGE_READWRITE);
1555 r600_pipe_state_add_reg(rstate, R_028100_CB_COLOR0_MASK + i * 4,
1556 surf->cb_color_mask);
1557
1558 if (rtex->fmask_size && rtex->cmask_size) {
1559 rctx->compressed_cb_mask |= 1 << i;
1560 }
1561 }
1562 /* set CB_COLOR1_INFO for possible dual-src blending */
1563 if (i == 1) {
1564 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + 1 * 4,
1565 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1566 i++;
1567 }
1568 for (; i < 8 ; i++) {
1569 r600_pipe_state_add_reg(rstate, R_0280A0_CB_COLOR0_INFO + i * 4, 0);
1570 }
1571
1572 /* Update alpha-test state dependencies.
1573 * Alpha-test is done on the first colorbuffer only. */
1574 if (state->nr_cbufs) {
1575 surf = (struct r600_surface*)state->cbufs[0];
1576 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1577 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1578 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1579 }
1580 }
1581
1582 /* ZS buffer. */
1583 if (state->zsbuf) {
1584 surf = (struct r600_surface*)state->zsbuf;
1585 res = (struct r600_resource*)surf->base.texture;
1586
1587 if (!surf->depth_initialized) {
1588 r600_init_depth_surface(rctx, surf);
1589 }
1590
1591 r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE, surf->db_depth_base,
1592 res, RADEON_USAGE_READWRITE);
1593 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, surf->db_depth_size);
1594 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, surf->db_depth_view);
1595 r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO, surf->db_depth_info,
1596 res, RADEON_USAGE_READWRITE);
1597 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1598 }
1599
1600 /* Framebuffer dimensions. */
1601 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1602 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1603
1604 r600_pipe_state_add_reg(rstate,
1605 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1606 r600_pipe_state_add_reg(rstate,
1607 R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1608
1609 /* If we're doing MSAA resolve... */
1610 if (state->nr_cbufs == 2 &&
1611 state->cbufs[0]->texture->nr_samples > 1 &&
1612 state->cbufs[1]->texture->nr_samples <= 1) {
1613 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL, 1);
1614 } else {
1615 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1616 * will assure that the alpha-test will work even if there is
1617 * no colorbuffer bound. */
1618 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1619 (1ull << MAX2(state->nr_cbufs, 1)) - 1);
1620 }
1621
1622 /* Multisampling */
1623 if (state->nr_cbufs)
1624 nr_samples = state->cbufs[0]->texture->nr_samples;
1625 else if (state->zsbuf)
1626 nr_samples = state->zsbuf->texture->nr_samples;
1627 else
1628 nr_samples = 0;
1629
1630 max_dist = r600_set_ms_pos(ctx, rstate, nr_samples);
1631
1632 if (nr_samples > 1) {
1633 unsigned log_samples = util_logbase2(nr_samples);
1634
1635 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL,
1636 S_028C00_LAST_PIXEL(1) |
1637 S_028C00_EXPAND_LINE_WIDTH(1));
1638 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1639 S_028C04_MSAA_NUM_SAMPLES(log_samples) |
1640 S_028C04_MAX_SAMPLE_DIST(max_dist));
1641 } else {
1642 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1643 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 0);
1644 }
1645
1646 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1647 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1648 r600_context_pipe_state_set(rctx, rstate);
1649
1650 if (state->zsbuf) {
1651 r600_polygon_offset_update(rctx);
1652 }
1653
1654 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1655 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1656 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1657 }
1658
1659 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1660 rctx->alphatest_state.bypass = false;
1661 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1662 }
1663 }
1664
1665 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1666 {
1667 struct radeon_winsys_cs *cs = rctx->cs;
1668 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1669
1670 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1671 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1672 if (rctx->chip_class == R600) {
1673 r600_write_value(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1674 r600_write_value(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1675 } else {
1676 r600_write_value(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1677 r600_write_value(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1678 }
1679 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1680 } else {
1681 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1682 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1683 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1684
1685 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1686 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1687 /* Always enable the first color output to make sure alpha-test works even without one. */
1688 r600_write_value(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1689 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1690 a->cb_color_control |
1691 S_028808_MULTIWRITE_ENABLE(multiwrite));
1692 }
1693 }
1694
1695 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1696 {
1697 struct radeon_winsys_cs *cs = rctx->cs;
1698 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1699 unsigned db_render_control = 0;
1700 unsigned db_render_override =
1701 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1702 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1703 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1704
1705 if (a->occlusion_query_enabled) {
1706 if (rctx->chip_class >= R700) {
1707 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1708 }
1709 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1710 }
1711 if (a->flush_depthstencil_through_cb) {
1712 assert(a->copy_depth || a->copy_stencil);
1713
1714 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1715 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1716 S_028D0C_COPY_CENTROID(1) |
1717 S_028D0C_COPY_SAMPLE(a->copy_sample);
1718 }
1719
1720 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1721 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1722 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1723 }
1724
1725 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1726 {
1727 struct radeon_winsys_cs *cs = rctx->cs;
1728 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1729
1730 while (dirty_mask) {
1731 struct pipe_vertex_buffer *vb;
1732 struct r600_resource *rbuffer;
1733 unsigned offset;
1734 unsigned buffer_index = u_bit_scan(&dirty_mask);
1735
1736 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1737 rbuffer = (struct r600_resource*)vb->buffer;
1738 assert(rbuffer);
1739
1740 offset = vb->buffer_offset;
1741
1742 /* fetch resources start at index 320 */
1743 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1744 r600_write_value(cs, (320 + buffer_index) * 7);
1745 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1746 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1747 r600_write_value(cs, /* RESOURCEi_WORD2 */
1748 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1749 S_038008_STRIDE(vb->stride));
1750 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1751 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1752 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1753 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1754
1755 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1756 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1757 }
1758 }
1759
1760 static void r600_emit_constant_buffers(struct r600_context *rctx,
1761 struct r600_constbuf_state *state,
1762 unsigned buffer_id_base,
1763 unsigned reg_alu_constbuf_size,
1764 unsigned reg_alu_const_cache)
1765 {
1766 struct radeon_winsys_cs *cs = rctx->cs;
1767 uint32_t dirty_mask = state->dirty_mask;
1768
1769 while (dirty_mask) {
1770 struct pipe_constant_buffer *cb;
1771 struct r600_resource *rbuffer;
1772 unsigned offset;
1773 unsigned buffer_index = ffs(dirty_mask) - 1;
1774
1775 cb = &state->cb[buffer_index];
1776 rbuffer = (struct r600_resource*)cb->buffer;
1777 assert(rbuffer);
1778
1779 offset = cb->buffer_offset;
1780
1781 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1782 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1783 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1784
1785 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1786 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1787
1788 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1789 r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1790 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1791 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1792 r600_write_value(cs, /* RESOURCEi_WORD2 */
1793 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1794 S_038008_STRIDE(16));
1795 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1796 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1797 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1798 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1799
1800 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1801 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1802
1803 dirty_mask &= ~(1 << buffer_index);
1804 }
1805 state->dirty_mask = 0;
1806 }
1807
1808 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1809 {
1810 r600_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 160,
1811 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1812 R_028980_ALU_CONST_CACHE_VS_0);
1813 }
1814
1815 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1816 {
1817 r600_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1818 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1819 R_028940_ALU_CONST_CACHE_PS_0);
1820 }
1821
1822 static void r600_emit_sampler_views(struct r600_context *rctx,
1823 struct r600_samplerview_state *state,
1824 unsigned resource_id_base)
1825 {
1826 struct radeon_winsys_cs *cs = rctx->cs;
1827 uint32_t dirty_mask = state->dirty_mask;
1828
1829 while (dirty_mask) {
1830 struct r600_pipe_sampler_view *rview;
1831 unsigned resource_index = u_bit_scan(&dirty_mask);
1832 unsigned reloc;
1833
1834 rview = state->views[resource_index];
1835 assert(rview);
1836
1837 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1838 r600_write_value(cs, (resource_id_base + resource_index) * 7);
1839 r600_write_array(cs, 7, rview->tex_resource_words);
1840
1841 /* XXX The kernel needs two relocations. This is stupid. */
1842 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1843 RADEON_USAGE_READ);
1844 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1845 r600_write_value(cs, reloc);
1846 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1847 r600_write_value(cs, reloc);
1848 }
1849 state->dirty_mask = 0;
1850 }
1851
1852 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1853 {
1854 r600_emit_sampler_views(rctx, &rctx->vs_samplers.views, 160 + R600_MAX_CONST_BUFFERS);
1855 }
1856
1857 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1858 {
1859 r600_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
1860 }
1861
1862 static void r600_emit_sampler(struct r600_context *rctx,
1863 struct r600_textures_info *texinfo,
1864 unsigned resource_id_base,
1865 unsigned border_color_reg)
1866 {
1867 struct radeon_winsys_cs *cs = rctx->cs;
1868 unsigned i;
1869
1870 for (i = 0; i < texinfo->n_samplers; i++) {
1871
1872 if (texinfo->samplers[i] == NULL) {
1873 continue;
1874 }
1875
1876 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1877 * filtering between layers.
1878 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1879 */
1880 if (texinfo->views.views[i]) {
1881 if (texinfo->views.views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1882 texinfo->views.views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1883 texinfo->samplers[i]->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1884 texinfo->is_array_sampler[i] = true;
1885 } else {
1886 texinfo->samplers[i]->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1887 texinfo->is_array_sampler[i] = false;
1888 }
1889 }
1890
1891 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1892 r600_write_value(cs, (resource_id_base + i) * 3);
1893 r600_write_array(cs, 3, texinfo->samplers[i]->tex_sampler_words);
1894
1895 if (texinfo->samplers[i]->border_color_use) {
1896 unsigned offset;
1897
1898 offset = border_color_reg;
1899 offset += i * 16;
1900 r600_write_config_reg_seq(cs, offset, 4);
1901 r600_write_array(cs, 4, texinfo->samplers[i]->border_color);
1902 }
1903 }
1904 }
1905
1906 static void r600_emit_vs_sampler(struct r600_context *rctx, struct r600_atom *atom)
1907 {
1908 r600_emit_sampler(rctx, &rctx->vs_samplers, 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1909 }
1910
1911 static void r600_emit_ps_sampler(struct r600_context *rctx, struct r600_atom *atom)
1912 {
1913 r600_emit_sampler(rctx, &rctx->ps_samplers, 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1914 }
1915
1916 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1917 {
1918 struct radeon_winsys_cs *cs = rctx->cs;
1919 unsigned tmp;
1920
1921 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1922 S_009508_SYNC_GRADIENT(1) |
1923 S_009508_SYNC_WALKER(1) |
1924 S_009508_SYNC_ALIGNER(1);
1925 if (!rctx->seamless_cube_map.enabled) {
1926 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1927 }
1928 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1929 }
1930
1931 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1932 {
1933 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1934 uint8_t mask = s->sample_mask;
1935
1936 r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
1937 mask | (mask << 8) | (mask << 16) | (mask << 24));
1938 }
1939
1940 void r600_init_state_functions(struct r600_context *rctx)
1941 {
1942 r600_init_atom(&rctx->seamless_cube_map.atom, r600_emit_seamless_cube_map, 3, 0);
1943 r600_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
1944 r600_init_atom(&rctx->cb_misc_state.atom, r600_emit_cb_misc_state, 0, 0);
1945 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1946 r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0);
1947 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1948 r600_init_atom(&rctx->vertex_buffer_state.atom, r600_emit_vertex_buffers, 0, 0);
1949 r600_init_atom(&rctx->vs_constbuf_state.atom, r600_emit_vs_constant_buffers, 0, 0);
1950 r600_init_atom(&rctx->ps_constbuf_state.atom, r600_emit_ps_constant_buffers, 0, 0);
1951 r600_init_atom(&rctx->vs_samplers.views.atom, r600_emit_vs_sampler_views, 0, 0);
1952 r600_init_atom(&rctx->ps_samplers.views.atom, r600_emit_ps_sampler_views, 0, 0);
1953 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
1954 * does not take effect
1955 */
1956 r600_init_atom(&rctx->vs_samplers.atom_sampler, r600_emit_vs_sampler, 0, EMIT_EARLY);
1957 r600_init_atom(&rctx->ps_samplers.atom_sampler, r600_emit_ps_sampler, 0, EMIT_EARLY);
1958
1959 r600_init_atom(&rctx->sample_mask.atom, r600_emit_sample_mask, 3, 0);
1960 rctx->sample_mask.sample_mask = ~0;
1961 r600_atom_dirty(rctx, &rctx->sample_mask.atom);
1962
1963 rctx->context.create_blend_state = r600_create_blend_state;
1964 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1965 rctx->context.create_fs_state = r600_create_shader_state_ps;
1966 rctx->context.create_rasterizer_state = r600_create_rs_state;
1967 rctx->context.create_sampler_state = r600_create_sampler_state;
1968 rctx->context.create_sampler_view = r600_create_sampler_view;
1969 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1970 rctx->context.create_vs_state = r600_create_shader_state_vs;
1971 rctx->context.bind_blend_state = r600_bind_blend_state;
1972 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1973 rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1974 rctx->context.bind_fs_state = r600_bind_ps_shader;
1975 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1976 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1977 rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1978 rctx->context.bind_vs_state = r600_bind_vs_shader;
1979 rctx->context.delete_blend_state = r600_delete_state;
1980 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1981 rctx->context.delete_fs_state = r600_delete_ps_shader;
1982 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1983 rctx->context.delete_sampler_state = r600_delete_sampler;
1984 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1985 rctx->context.delete_vs_state = r600_delete_vs_shader;
1986 rctx->context.set_blend_color = r600_set_blend_color;
1987 rctx->context.set_clip_state = r600_set_clip_state;
1988 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1989 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1990 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1991 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1992 rctx->context.set_sample_mask = r600_set_sample_mask;
1993 rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
1994 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1995 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1996 rctx->context.set_index_buffer = r600_set_index_buffer;
1997 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1998 rctx->context.set_viewport_state = r600_set_viewport_state;
1999 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
2000 rctx->context.texture_barrier = r600_texture_barrier;
2001 rctx->context.create_stream_output_target = r600_create_so_target;
2002 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
2003 rctx->context.set_stream_output_targets = r600_set_so_targets;
2004 }
2005
2006 /* Adjust GPR allocation on R6xx/R7xx */
2007 void r600_adjust_gprs(struct r600_context *rctx)
2008 {
2009 struct r600_pipe_state rstate;
2010 unsigned num_ps_gprs = rctx->default_ps_gprs;
2011 unsigned num_vs_gprs = rctx->default_vs_gprs;
2012 unsigned tmp;
2013 int diff;
2014
2015 /* XXX: Following call moved from r600_bind_[ps|vs]_shader,
2016 * it seems eg+ doesn't need it, r6xx/7xx probably need it only for
2017 * adjusting the GPR allocation?
2018 * Do we need this if we aren't really changing config below? */
2019 r600_inval_shader_cache(rctx);
2020
2021 if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs)
2022 {
2023 diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
2024 num_vs_gprs -= diff;
2025 num_ps_gprs += diff;
2026 }
2027
2028 if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
2029 {
2030 diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
2031 num_ps_gprs -= diff;
2032 num_vs_gprs += diff;
2033 }
2034
2035 tmp = 0;
2036 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2037 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2038 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
2039 rstate.nregs = 0;
2040 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
2041
2042 r600_context_pipe_state_set(rctx, &rstate);
2043 }
2044
2045 void r600_init_atom_start_cs(struct r600_context *rctx)
2046 {
2047 int ps_prio;
2048 int vs_prio;
2049 int gs_prio;
2050 int es_prio;
2051 int num_ps_gprs;
2052 int num_vs_gprs;
2053 int num_gs_gprs;
2054 int num_es_gprs;
2055 int num_temp_gprs;
2056 int num_ps_threads;
2057 int num_vs_threads;
2058 int num_gs_threads;
2059 int num_es_threads;
2060 int num_ps_stack_entries;
2061 int num_vs_stack_entries;
2062 int num_gs_stack_entries;
2063 int num_es_stack_entries;
2064 enum radeon_family family;
2065 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2066 uint32_t tmp;
2067
2068 r600_init_command_buffer(cb, 256, EMIT_EARLY);
2069
2070 /* R6xx requires this packet at the start of each command buffer */
2071 if (rctx->chip_class == R600) {
2072 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2073 r600_store_value(cb, 0);
2074 }
2075 /* All asics require this one */
2076 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2077 r600_store_value(cb, 0x80000000);
2078 r600_store_value(cb, 0x80000000);
2079
2080 family = rctx->family;
2081 ps_prio = 0;
2082 vs_prio = 1;
2083 gs_prio = 2;
2084 es_prio = 3;
2085 switch (family) {
2086 case CHIP_R600:
2087 num_ps_gprs = 192;
2088 num_vs_gprs = 56;
2089 num_temp_gprs = 4;
2090 num_gs_gprs = 0;
2091 num_es_gprs = 0;
2092 num_ps_threads = 136;
2093 num_vs_threads = 48;
2094 num_gs_threads = 4;
2095 num_es_threads = 4;
2096 num_ps_stack_entries = 128;
2097 num_vs_stack_entries = 128;
2098 num_gs_stack_entries = 0;
2099 num_es_stack_entries = 0;
2100 break;
2101 case CHIP_RV630:
2102 case CHIP_RV635:
2103 num_ps_gprs = 84;
2104 num_vs_gprs = 36;
2105 num_temp_gprs = 4;
2106 num_gs_gprs = 0;
2107 num_es_gprs = 0;
2108 num_ps_threads = 144;
2109 num_vs_threads = 40;
2110 num_gs_threads = 4;
2111 num_es_threads = 4;
2112 num_ps_stack_entries = 40;
2113 num_vs_stack_entries = 40;
2114 num_gs_stack_entries = 32;
2115 num_es_stack_entries = 16;
2116 break;
2117 case CHIP_RV610:
2118 case CHIP_RV620:
2119 case CHIP_RS780:
2120 case CHIP_RS880:
2121 default:
2122 num_ps_gprs = 84;
2123 num_vs_gprs = 36;
2124 num_temp_gprs = 4;
2125 num_gs_gprs = 0;
2126 num_es_gprs = 0;
2127 num_ps_threads = 136;
2128 num_vs_threads = 48;
2129 num_gs_threads = 4;
2130 num_es_threads = 4;
2131 num_ps_stack_entries = 40;
2132 num_vs_stack_entries = 40;
2133 num_gs_stack_entries = 32;
2134 num_es_stack_entries = 16;
2135 break;
2136 case CHIP_RV670:
2137 num_ps_gprs = 144;
2138 num_vs_gprs = 40;
2139 num_temp_gprs = 4;
2140 num_gs_gprs = 0;
2141 num_es_gprs = 0;
2142 num_ps_threads = 136;
2143 num_vs_threads = 48;
2144 num_gs_threads = 4;
2145 num_es_threads = 4;
2146 num_ps_stack_entries = 40;
2147 num_vs_stack_entries = 40;
2148 num_gs_stack_entries = 32;
2149 num_es_stack_entries = 16;
2150 break;
2151 case CHIP_RV770:
2152 num_ps_gprs = 192;
2153 num_vs_gprs = 56;
2154 num_temp_gprs = 4;
2155 num_gs_gprs = 0;
2156 num_es_gprs = 0;
2157 num_ps_threads = 188;
2158 num_vs_threads = 60;
2159 num_gs_threads = 0;
2160 num_es_threads = 0;
2161 num_ps_stack_entries = 256;
2162 num_vs_stack_entries = 256;
2163 num_gs_stack_entries = 0;
2164 num_es_stack_entries = 0;
2165 break;
2166 case CHIP_RV730:
2167 case CHIP_RV740:
2168 num_ps_gprs = 84;
2169 num_vs_gprs = 36;
2170 num_temp_gprs = 4;
2171 num_gs_gprs = 0;
2172 num_es_gprs = 0;
2173 num_ps_threads = 188;
2174 num_vs_threads = 60;
2175 num_gs_threads = 0;
2176 num_es_threads = 0;
2177 num_ps_stack_entries = 128;
2178 num_vs_stack_entries = 128;
2179 num_gs_stack_entries = 0;
2180 num_es_stack_entries = 0;
2181 break;
2182 case CHIP_RV710:
2183 num_ps_gprs = 192;
2184 num_vs_gprs = 56;
2185 num_temp_gprs = 4;
2186 num_gs_gprs = 0;
2187 num_es_gprs = 0;
2188 num_ps_threads = 144;
2189 num_vs_threads = 48;
2190 num_gs_threads = 0;
2191 num_es_threads = 0;
2192 num_ps_stack_entries = 128;
2193 num_vs_stack_entries = 128;
2194 num_gs_stack_entries = 0;
2195 num_es_stack_entries = 0;
2196 break;
2197 }
2198
2199 rctx->default_ps_gprs = num_ps_gprs;
2200 rctx->default_vs_gprs = num_vs_gprs;
2201 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2202
2203 /* SQ_CONFIG */
2204 tmp = 0;
2205 switch (family) {
2206 case CHIP_RV610:
2207 case CHIP_RV620:
2208 case CHIP_RS780:
2209 case CHIP_RS880:
2210 case CHIP_RV710:
2211 break;
2212 default:
2213 tmp |= S_008C00_VC_ENABLE(1);
2214 break;
2215 }
2216 tmp |= S_008C00_DX9_CONSTS(0);
2217 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2218 tmp |= S_008C00_PS_PRIO(ps_prio);
2219 tmp |= S_008C00_VS_PRIO(vs_prio);
2220 tmp |= S_008C00_GS_PRIO(gs_prio);
2221 tmp |= S_008C00_ES_PRIO(es_prio);
2222 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2223
2224 /* SQ_GPR_RESOURCE_MGMT_2 */
2225 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2226 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2227 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2228 r600_store_value(cb, tmp);
2229
2230 /* SQ_THREAD_RESOURCE_MGMT */
2231 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2232 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2233 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2234 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2235 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2236
2237 /* SQ_STACK_RESOURCE_MGMT_1 */
2238 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2239 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2240 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2241
2242 /* SQ_STACK_RESOURCE_MGMT_2 */
2243 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2244 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2245 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2246
2247 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2248
2249 if (rctx->chip_class >= R700) {
2250 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2251 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2252 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2253 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2254 } else {
2255 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2256 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2257 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2258 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2259 }
2260 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2261 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2262 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2263 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2264 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2265 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2266 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2267 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2268 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2269 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2270
2271 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2272 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2273 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2274 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2275 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2276 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2277 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2278 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2279 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2280 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2281 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2282 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2283 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2284 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2285
2286 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2287 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2288 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2289
2290 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2291 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2292 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2293 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2294
2295 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2296
2297 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2298 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2299 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2300
2301 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2302
2303 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2304 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2305 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2306
2307 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2308 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2309 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2310 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2311
2312 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2313 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2314 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2315
2316 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2317 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2318
2319 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2320 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2321 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2322 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2323 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2324
2325 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2326 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2327 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2328
2329 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2330
2331 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2332 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2333
2334 if (rctx->chip_class >= R700) {
2335 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2336 }
2337
2338 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2339 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2340 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2341 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2342 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2343
2344 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2345 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2346 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2347
2348 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2349 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2350 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2351
2352 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2353 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2354 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2355
2356 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2357 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2358
2359 if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2360 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2361 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2362 if (rctx->screen->has_streamout) {
2363 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2364 }
2365
2366 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2367 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2368 }
2369
2370 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2371 {
2372 struct r600_context *rctx = (struct r600_context *)ctx;
2373 struct r600_pipe_state *rstate = &shader->rstate;
2374 struct r600_shader *rshader = &shader->shader;
2375 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2376 int pos_index = -1, face_index = -1;
2377 unsigned tmp, sid, ufi = 0;
2378 int need_linear = 0;
2379 unsigned z_export = 0, stencil_export = 0;
2380
2381 rstate->nregs = 0;
2382
2383 for (i = 0; i < rshader->ninput; i++) {
2384 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2385 pos_index = i;
2386 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2387 face_index = i;
2388
2389 sid = rshader->input[i].spi_sid;
2390
2391 tmp = S_028644_SEMANTIC(sid);
2392
2393 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2394 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2395 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2396 rctx->rasterizer && rctx->rasterizer->flatshade))
2397 tmp |= S_028644_FLAT_SHADE(1);
2398
2399 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2400 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2401 tmp |= S_028644_PT_SPRITE_TEX(1);
2402 }
2403
2404 if (rshader->input[i].centroid)
2405 tmp |= S_028644_SEL_CENTROID(1);
2406
2407 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2408 need_linear = 1;
2409 tmp |= S_028644_SEL_LINEAR(1);
2410 }
2411
2412 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2413 tmp);
2414 }
2415
2416 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2417 for (i = 0; i < rshader->noutput; i++) {
2418 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2419 z_export = 1;
2420 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2421 stencil_export = 1;
2422 }
2423 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2424 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2425 if (rshader->uses_kill)
2426 db_shader_control |= S_02880C_KILL_ENABLE(1);
2427
2428 exports_ps = 0;
2429 for (i = 0; i < rshader->noutput; i++) {
2430 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2431 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2432 exports_ps |= 1;
2433 }
2434 }
2435 num_cout = rshader->nr_ps_color_exports;
2436 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2437 if (!exports_ps) {
2438 /* always at least export 1 component per pixel */
2439 exports_ps = 2;
2440 }
2441
2442 shader->nr_ps_color_outputs = num_cout;
2443
2444 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2445 S_0286CC_PERSP_GRADIENT_ENA(1)|
2446 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2447 spi_input_z = 0;
2448 if (pos_index != -1) {
2449 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2450 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2451 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2452 S_0286CC_BARYC_SAMPLE_CNTL(1));
2453 spi_input_z |= 1;
2454 }
2455
2456 spi_ps_in_control_1 = 0;
2457 if (face_index != -1) {
2458 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2459 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2460 }
2461
2462 /* HW bug in original R600 */
2463 if (rctx->family == CHIP_R600)
2464 ufi = 1;
2465
2466 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2467 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2468 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2469 r600_pipe_state_add_reg_bo(rstate,
2470 R_028840_SQ_PGM_START_PS,
2471 0, shader->bo, RADEON_USAGE_READ);
2472 r600_pipe_state_add_reg(rstate,
2473 R_028850_SQ_PGM_RESOURCES_PS,
2474 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2475 S_028850_STACK_SIZE(rshader->bc.nstack) |
2476 S_028850_UNCACHED_FIRST_INST(ufi));
2477 r600_pipe_state_add_reg(rstate,
2478 R_028854_SQ_PGM_EXPORTS_PS,
2479 exports_ps);
2480 /* only set some bits here, the other bits are set in the dsa state */
2481 shader->db_shader_control = db_shader_control;
2482 shader->ps_depth_export = z_export | stencil_export;
2483
2484 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2485 if (rctx->rasterizer)
2486 shader->flatshade = rctx->rasterizer->flatshade;
2487 }
2488
2489 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2490 {
2491 struct r600_context *rctx = (struct r600_context *)ctx;
2492 struct r600_pipe_state *rstate = &shader->rstate;
2493 struct r600_shader *rshader = &shader->shader;
2494 unsigned spi_vs_out_id[10] = {};
2495 unsigned i, tmp, nparams = 0;
2496
2497 /* clear previous register */
2498 rstate->nregs = 0;
2499
2500 for (i = 0; i < rshader->noutput; i++) {
2501 if (rshader->output[i].spi_sid) {
2502 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2503 spi_vs_out_id[nparams / 4] |= tmp;
2504 nparams++;
2505 }
2506 }
2507
2508 for (i = 0; i < 10; i++) {
2509 r600_pipe_state_add_reg(rstate,
2510 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2511 spi_vs_out_id[i]);
2512 }
2513
2514 /* Certain attributes (position, psize, etc.) don't count as params.
2515 * VS is required to export at least one param and r600_shader_from_tgsi()
2516 * takes care of adding a dummy export.
2517 */
2518 if (nparams < 1)
2519 nparams = 1;
2520
2521 r600_pipe_state_add_reg(rstate,
2522 R_0286C4_SPI_VS_OUT_CONFIG,
2523 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2524 r600_pipe_state_add_reg(rstate,
2525 R_028868_SQ_PGM_RESOURCES_VS,
2526 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2527 S_028868_STACK_SIZE(rshader->bc.nstack));
2528 r600_pipe_state_add_reg_bo(rstate,
2529 R_028858_SQ_PGM_START_VS,
2530 0, shader->bo, RADEON_USAGE_READ);
2531
2532 shader->pa_cl_vs_out_cntl =
2533 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2534 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2535 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2536 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2537 }
2538
2539 void r600_fetch_shader(struct pipe_context *ctx,
2540 struct r600_vertex_element *ve)
2541 {
2542 struct r600_pipe_state *rstate;
2543 struct r600_context *rctx = (struct r600_context *)ctx;
2544
2545 rstate = &ve->rstate;
2546 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2547 rstate->nregs = 0;
2548 r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS,
2549 0,
2550 ve->fetch_shader, RADEON_USAGE_READ);
2551 }
2552
2553 void *r600_create_resolve_blend(struct r600_context *rctx)
2554 {
2555 struct pipe_blend_state blend;
2556 struct r600_pipe_state *rstate;
2557
2558 memset(&blend, 0, sizeof(blend));
2559 blend.independent_blend_enable = true;
2560 blend.rt[0].colormask = 0xf;
2561 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2562 return rstate;
2563 }
2564
2565 void *r600_create_decompress_blend(struct r600_context *rctx)
2566 {
2567 struct pipe_blend_state blend;
2568 struct r600_pipe_state *rstate;
2569
2570 memset(&blend, 0, sizeof(blend));
2571 blend.independent_blend_enable = true;
2572 blend.rt[0].colormask = 0xf;
2573 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2574 return rstate;
2575 }
2576
2577 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2578 {
2579 struct pipe_depth_stencil_alpha_state dsa;
2580 boolean quirk = false;
2581
2582 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2583 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2584 quirk = true;
2585
2586 memset(&dsa, 0, sizeof(dsa));
2587
2588 if (quirk) {
2589 dsa.depth.enabled = 1;
2590 dsa.depth.func = PIPE_FUNC_LEQUAL;
2591 dsa.stencil[0].enabled = 1;
2592 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2593 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2594 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2595 dsa.stencil[0].writemask = 0xff;
2596 }
2597
2598 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2599 }
2600
2601 void r600_update_dual_export_state(struct r600_context * rctx)
2602 {
2603 unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2604 !rctx->ps_shader->current->ps_depth_export;
2605 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2606 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2607
2608 if (db_shader_control != rctx->db_shader_control) {
2609 struct r600_pipe_state rstate;
2610
2611 rctx->db_shader_control = db_shader_control;
2612 rstate.nregs = 0;
2613 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2614 r600_context_pipe_state_set(rctx, &rstate);
2615 }
2616 }