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r600g: fix up the rules for enabling SOURCE_FORMAT(EXPORT_NORM)
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_framebuffer.h>
40 #include "util/u_transfer.h"
41 #include <pipebuffer/pb_buffer.h>
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_state_inlines.h"
48
49 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
50 {
51 struct r600_pipe_state state;
52
53 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
54 state.nregs = 0;
55 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
56 float offset_units = rctx->rasterizer->offset_units;
57 unsigned offset_db_fmt_cntl = 0, depth;
58
59 switch (rctx->framebuffer.zsbuf->texture->format) {
60 case PIPE_FORMAT_Z24X8_UNORM:
61 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
62 depth = -24;
63 offset_units *= 2.0f;
64 break;
65 case PIPE_FORMAT_Z32_FLOAT:
66 depth = -23;
67 offset_units *= 1.0f;
68 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
69 break;
70 case PIPE_FORMAT_Z16_UNORM:
71 depth = -16;
72 offset_units *= 4.0f;
73 break;
74 default:
75 return;
76 }
77 /* FIXME some of those reg can be computed with cso */
78 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
79 r600_pipe_state_add_reg(&state,
80 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
81 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
82 r600_pipe_state_add_reg(&state,
83 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
84 fui(offset_units), 0xFFFFFFFF, NULL);
85 r600_pipe_state_add_reg(&state,
86 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
87 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
88 r600_pipe_state_add_reg(&state,
89 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
90 fui(offset_units), 0xFFFFFFFF, NULL);
91 r600_pipe_state_add_reg(&state,
92 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
93 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
94 r600_context_pipe_state_set(&rctx->ctx, &state);
95 }
96 }
97
98 static void r600_set_blend_color(struct pipe_context *ctx,
99 const struct pipe_blend_color *state)
100 {
101 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
102 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
103
104 if (rstate == NULL)
105 return;
106
107 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
108 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
109 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
110 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
111 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
112 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
113 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
114 r600_context_pipe_state_set(&rctx->ctx, rstate);
115 }
116
117 static void *r600_create_blend_state(struct pipe_context *ctx,
118 const struct pipe_blend_state *state)
119 {
120 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
121 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
122 struct r600_pipe_state *rstate;
123 u32 color_control = 0, target_mask;
124
125 if (blend == NULL) {
126 return NULL;
127 }
128 rstate = &blend->rstate;
129
130 rstate->id = R600_PIPE_STATE_BLEND;
131
132 target_mask = 0;
133
134 /* R600 does not support per-MRT blends */
135 if (rctx->family > CHIP_R600)
136 color_control |= S_028808_PER_MRT_BLEND(1);
137 if (state->logicop_enable) {
138 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
139 } else {
140 color_control |= (0xcc << 16);
141 }
142 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
143 if (state->independent_blend_enable) {
144 for (int i = 0; i < 8; i++) {
145 if (state->rt[i].blend_enable) {
146 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
147 }
148 target_mask |= (state->rt[i].colormask << (4 * i));
149 }
150 } else {
151 for (int i = 0; i < 8; i++) {
152 if (state->rt[0].blend_enable) {
153 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
154 }
155 target_mask |= (state->rt[0].colormask << (4 * i));
156 }
157 }
158 blend->cb_target_mask = target_mask;
159 /* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */
160 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
161 color_control, 0xFFFFFFFD, NULL);
162
163 for (int i = 0; i < 8; i++) {
164 /* state->rt entries > 0 only written if independent blending */
165 const int j = state->independent_blend_enable ? i : 0;
166
167 unsigned eqRGB = state->rt[j].rgb_func;
168 unsigned srcRGB = state->rt[j].rgb_src_factor;
169 unsigned dstRGB = state->rt[j].rgb_dst_factor;
170
171 unsigned eqA = state->rt[j].alpha_func;
172 unsigned srcA = state->rt[j].alpha_src_factor;
173 unsigned dstA = state->rt[j].alpha_dst_factor;
174 uint32_t bc = 0;
175
176 if (!state->rt[j].blend_enable)
177 continue;
178
179 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
180 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
181 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
182
183 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
184 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
185 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
186 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
187 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
188 }
189
190 /* R600 does not support per-MRT blends */
191 if (rctx->family > CHIP_R600)
192 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
193 if (i == 0)
194 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
195 }
196 return rstate;
197 }
198
199 static void *r600_create_dsa_state(struct pipe_context *ctx,
200 const struct pipe_depth_stencil_alpha_state *state)
201 {
202 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
203 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
204 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
205 struct r600_pipe_state *rstate;
206
207 if (dsa == NULL) {
208 return NULL;
209 }
210
211 rstate = &dsa->rstate;
212
213 rstate->id = R600_PIPE_STATE_DSA;
214 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
215 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
216 stencil_ref_mask = 0;
217 stencil_ref_mask_bf = 0;
218 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
219 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
220 S_028800_ZFUNC(state->depth.func);
221
222 /* stencil */
223 if (state->stencil[0].enabled) {
224 db_depth_control |= S_028800_STENCIL_ENABLE(1);
225 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
226 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
227 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
228 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
229
230
231 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
232 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
233 if (state->stencil[1].enabled) {
234 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
235 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
236 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
237 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
238 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
239 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
240 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
241 }
242 }
243
244 /* alpha */
245 alpha_test_control = 0;
246 alpha_ref = 0;
247 if (state->alpha.enabled) {
248 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
249 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
250 alpha_ref = fui(state->alpha.ref_value);
251 }
252 dsa->alpha_ref = alpha_ref;
253
254 /* misc */
255 db_render_control = 0;
256 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
257 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
258 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
259 /* TODO db_render_override depends on query */
260 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
261 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
262 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
263 r600_pipe_state_add_reg(rstate,
264 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
265 0xFFFFFFFF & C_028430_STENCILREF, NULL);
266 r600_pipe_state_add_reg(rstate,
267 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
268 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
269 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
270 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
271 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
272 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
273 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
274 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
275 * r600_pipe_shader_ps().*/
276 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL);
277 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
278 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
279 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
280 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
281 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
282
283 return rstate;
284 }
285
286 static void *r600_create_rs_state(struct pipe_context *ctx,
287 const struct pipe_rasterizer_state *state)
288 {
289 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
290 struct r600_pipe_state *rstate;
291 unsigned tmp;
292 unsigned prov_vtx = 1, polygon_dual_mode;
293 unsigned clip_rule;
294
295 if (rs == NULL) {
296 return NULL;
297 }
298
299 rstate = &rs->rstate;
300 rs->flatshade = state->flatshade;
301 rs->sprite_coord_enable = state->sprite_coord_enable;
302
303 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
304 /* offset */
305 rs->offset_units = state->offset_units;
306 rs->offset_scale = state->offset_scale * 12.0f;
307
308 rstate->id = R600_PIPE_STATE_RASTERIZER;
309 if (state->flatshade_first)
310 prov_vtx = 0;
311 tmp = S_0286D4_FLAT_SHADE_ENA(1);
312 if (state->sprite_coord_enable) {
313 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
314 S_0286D4_PNT_SPRITE_OVRD_X(2) |
315 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
316 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
317 S_0286D4_PNT_SPRITE_OVRD_W(1);
318 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
319 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
320 }
321 }
322 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
323
324 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
325 state->fill_back != PIPE_POLYGON_MODE_FILL);
326 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
327 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
328 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
329 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
330 S_028814_FACE(!state->front_ccw) |
331 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
332 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
333 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
334 S_028814_POLY_MODE(polygon_dual_mode) |
335 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
336 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
337 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
338 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
339 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
340 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
341 /* point size 12.4 fixed point */
342 tmp = (unsigned)(state->point_size * 8.0);
343 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
344 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
345
346 tmp = (unsigned)state->line_width * 8;
347 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
348
349 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
350 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
351 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
352
353 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
354 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
355 0xFFFFFFFF, NULL);
356
357 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
358 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
359 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
360 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
361 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
362 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
363
364 return rstate;
365 }
366
367 static void *r600_create_sampler_state(struct pipe_context *ctx,
368 const struct pipe_sampler_state *state)
369 {
370 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
371 union util_color uc;
372
373 if (rstate == NULL) {
374 return NULL;
375 }
376
377 rstate->id = R600_PIPE_STATE_SAMPLER;
378 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
379 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
380 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
381 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
382 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
383 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
384 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
385 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
386 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
387 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
388 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
389 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
390 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
391 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
392 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
393 if (uc.ui) {
394 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
395 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
396 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
397 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
398 }
399 return rstate;
400 }
401
402 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
403 struct pipe_resource *texture,
404 const struct pipe_sampler_view *state)
405 {
406 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
407 struct r600_pipe_state *rstate;
408 const struct util_format_description *desc;
409 struct r600_resource_texture *tmp;
410 struct r600_resource *rbuffer;
411 unsigned format, endian;
412 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
413 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
414 struct r600_bo *bo[2];
415 unsigned height, depth;
416
417 if (resource == NULL)
418 return NULL;
419 rstate = &resource->state;
420
421 /* initialize base object */
422 resource->base = *state;
423 resource->base.texture = NULL;
424 pipe_reference(NULL, &texture->reference);
425 resource->base.texture = texture;
426 resource->base.reference.count = 1;
427 resource->base.context = ctx;
428
429 swizzle[0] = state->swizzle_r;
430 swizzle[1] = state->swizzle_g;
431 swizzle[2] = state->swizzle_b;
432 swizzle[3] = state->swizzle_a;
433 format = r600_translate_texformat(ctx->screen, state->format,
434 swizzle,
435 &word4, &yuv_format);
436 if (format == ~0) {
437 format = 0;
438 }
439 desc = util_format_description(state->format);
440 if (desc == NULL) {
441 R600_ERR("unknow format %d\n", state->format);
442 }
443 tmp = (struct r600_resource_texture *)texture;
444 if (tmp->depth && !tmp->is_flushing_texture) {
445 r600_texture_depth_flush(ctx, texture, TRUE);
446 tmp = tmp->flushed_depth_texture;
447 }
448 endian = r600_colorformat_endian_swap(format);
449
450 if (tmp->force_int_type) {
451 word4 &= C_038010_NUM_FORMAT_ALL;
452 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
453 }
454 rbuffer = &tmp->resource;
455 bo[0] = rbuffer->bo;
456 bo[1] = rbuffer->bo;
457 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8);
458 array_mode = tmp->array_mode[0];
459 tile_type = tmp->tile_type;
460
461 height = texture->height0;
462 depth = texture->depth0;
463 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
464 height = 1;
465 depth = texture->array_size;
466 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
467 depth = texture->array_size;
468 }
469
470 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
471 S_038000_DIM(r600_tex_dim(texture->target)) |
472 S_038000_TILE_MODE(array_mode) |
473 S_038000_TILE_TYPE(tile_type) |
474 S_038000_PITCH((pitch / 8) - 1) |
475 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
476 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
477 S_038004_TEX_HEIGHT(height - 1) |
478 S_038004_TEX_DEPTH(depth - 1) |
479 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
480 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
481 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
482 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
483 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
484 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
485 word4 |
486 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_NO_ZERO) |
487 S_038010_REQUEST_SIZE(1) |
488 S_038010_ENDIAN_SWAP(endian) |
489 S_038010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
490 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
491 S_038014_LAST_LEVEL(state->u.tex.last_level) |
492 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
493 S_038014_LAST_ARRAY(state->u.tex.last_layer), 0xFFFFFFFF, NULL);
494 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
495 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
496
497 return &resource->base;
498 }
499
500 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
501 struct pipe_sampler_view **views)
502 {
503 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
504 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
505
506 for (int i = 0; i < count; i++) {
507 if (resource[i]) {
508 r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
509 i + R600_MAX_CONST_BUFFERS);
510 }
511 }
512 }
513
514 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
515 struct pipe_sampler_view **views)
516 {
517 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
518 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
519 int i;
520
521 for (i = 0; i < count; i++) {
522 if (&rctx->ps_samplers.views[i]->base != views[i]) {
523 if (resource[i])
524 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
525 i + R600_MAX_CONST_BUFFERS);
526 else
527 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
528 i + R600_MAX_CONST_BUFFERS);
529
530 pipe_sampler_view_reference(
531 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
532 views[i]);
533
534 }
535 }
536 for (i = count; i < NUM_TEX_UNITS; i++) {
537 if (rctx->ps_samplers.views[i]) {
538 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
539 i + R600_MAX_CONST_BUFFERS);
540 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
541 }
542 }
543 rctx->ps_samplers.n_views = count;
544 }
545
546 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
547 {
548 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
549 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
550
551 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
552 rctx->ps_samplers.n_samplers = count;
553
554 for (int i = 0; i < count; i++) {
555 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
556 }
557 }
558
559 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
560 {
561 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
562 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
563
564 for (int i = 0; i < count; i++) {
565 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
566 }
567 }
568
569 static void r600_set_clip_state(struct pipe_context *ctx,
570 const struct pipe_clip_state *state)
571 {
572 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
573 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
574
575 if (rstate == NULL)
576 return;
577
578 rctx->clip = *state;
579 rstate->id = R600_PIPE_STATE_CLIP;
580 for (int i = 0; i < state->nr; i++) {
581 r600_pipe_state_add_reg(rstate,
582 R_028E20_PA_CL_UCP0_X + i * 16,
583 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
584 r600_pipe_state_add_reg(rstate,
585 R_028E24_PA_CL_UCP0_Y + i * 16,
586 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
587 r600_pipe_state_add_reg(rstate,
588 R_028E28_PA_CL_UCP0_Z + i * 16,
589 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
590 r600_pipe_state_add_reg(rstate,
591 R_028E2C_PA_CL_UCP0_W + i * 16,
592 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
593 }
594 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
595 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
596 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
597 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
598
599 free(rctx->states[R600_PIPE_STATE_CLIP]);
600 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
601 r600_context_pipe_state_set(&rctx->ctx, rstate);
602 }
603
604 static void r600_set_polygon_stipple(struct pipe_context *ctx,
605 const struct pipe_poly_stipple *state)
606 {
607 }
608
609 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
610 {
611 }
612
613 static void r600_set_scissor_state(struct pipe_context *ctx,
614 const struct pipe_scissor_state *state)
615 {
616 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
617 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
618 u32 tl, br;
619
620 if (rstate == NULL)
621 return;
622
623 rstate->id = R600_PIPE_STATE_SCISSOR;
624 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
625 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
626 r600_pipe_state_add_reg(rstate,
627 R_028210_PA_SC_CLIPRECT_0_TL, tl,
628 0xFFFFFFFF, NULL);
629 r600_pipe_state_add_reg(rstate,
630 R_028214_PA_SC_CLIPRECT_0_BR, br,
631 0xFFFFFFFF, NULL);
632 r600_pipe_state_add_reg(rstate,
633 R_028218_PA_SC_CLIPRECT_1_TL, tl,
634 0xFFFFFFFF, NULL);
635 r600_pipe_state_add_reg(rstate,
636 R_02821C_PA_SC_CLIPRECT_1_BR, br,
637 0xFFFFFFFF, NULL);
638 r600_pipe_state_add_reg(rstate,
639 R_028220_PA_SC_CLIPRECT_2_TL, tl,
640 0xFFFFFFFF, NULL);
641 r600_pipe_state_add_reg(rstate,
642 R_028224_PA_SC_CLIPRECT_2_BR, br,
643 0xFFFFFFFF, NULL);
644 r600_pipe_state_add_reg(rstate,
645 R_028228_PA_SC_CLIPRECT_3_TL, tl,
646 0xFFFFFFFF, NULL);
647 r600_pipe_state_add_reg(rstate,
648 R_02822C_PA_SC_CLIPRECT_3_BR, br,
649 0xFFFFFFFF, NULL);
650
651 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
652 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
653 r600_context_pipe_state_set(&rctx->ctx, rstate);
654 }
655
656 static void r600_set_stencil_ref(struct pipe_context *ctx,
657 const struct pipe_stencil_ref *state)
658 {
659 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
660 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
661 u32 tmp;
662
663 if (rstate == NULL)
664 return;
665
666 rctx->stencil_ref = *state;
667 rstate->id = R600_PIPE_STATE_STENCIL_REF;
668 tmp = S_028430_STENCILREF(state->ref_value[0]);
669 r600_pipe_state_add_reg(rstate,
670 R_028430_DB_STENCILREFMASK, tmp,
671 ~C_028430_STENCILREF, NULL);
672 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
673 r600_pipe_state_add_reg(rstate,
674 R_028434_DB_STENCILREFMASK_BF, tmp,
675 ~C_028434_STENCILREF_BF, NULL);
676
677 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
678 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
679 r600_context_pipe_state_set(&rctx->ctx, rstate);
680 }
681
682 static void r600_set_viewport_state(struct pipe_context *ctx,
683 const struct pipe_viewport_state *state)
684 {
685 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
686 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
687
688 if (rstate == NULL)
689 return;
690
691 rctx->viewport = *state;
692 rstate->id = R600_PIPE_STATE_VIEWPORT;
693 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
694 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
695 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
696 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
697 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
698 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
699 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
700 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
701 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
702
703 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
704 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
705 r600_context_pipe_state_set(&rctx->ctx, rstate);
706 }
707
708 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
709 const struct pipe_framebuffer_state *state, int cb)
710 {
711 struct r600_resource_texture *rtex;
712 struct r600_resource *rbuffer;
713 struct r600_surface *surf;
714 unsigned level = state->cbufs[cb]->u.tex.level;
715 unsigned pitch, slice;
716 unsigned color_info;
717 unsigned format, swap, ntype, endian;
718 unsigned offset;
719 const struct util_format_description *desc;
720 struct r600_bo *bo[3];
721 int i;
722
723 surf = (struct r600_surface *)state->cbufs[cb];
724 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
725
726 if (rtex->depth && !rtex->is_flushing_texture) {
727 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
728 rtex = rtex->flushed_depth_texture;
729 }
730
731 rbuffer = &rtex->resource;
732 bo[0] = rbuffer->bo;
733 bo[1] = rbuffer->bo;
734 bo[2] = rbuffer->bo;
735
736 /* XXX quite sure for dx10+ hw don't need any offset hacks */
737 offset = r600_texture_get_offset(rtex,
738 level, state->cbufs[cb]->u.tex.first_layer);
739 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
740 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
741 desc = util_format_description(surf->base.format);
742
743 for (i = 0; i < 4; i++) {
744 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
745 break;
746 }
747 }
748 ntype = V_0280A0_NUMBER_UNORM;
749 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
750 ntype = V_0280A0_NUMBER_SRGB;
751 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED)
752 ntype = V_0280A0_NUMBER_SNORM;
753
754 format = r600_translate_colorformat(surf->base.format);
755 swap = r600_translate_colorswap(surf->base.format);
756 if(rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
757 endian = ENDIAN_NONE;
758 } else {
759 endian = r600_colorformat_endian_swap(format);
760 }
761
762 /* disable when gallium grows int textures */
763 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
764 ntype = V_0280A0_NUMBER_UINT;
765
766 color_info = S_0280A0_FORMAT(format) |
767 S_0280A0_COMP_SWAP(swap) |
768 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
769 S_0280A0_BLEND_CLAMP(1) |
770 S_0280A0_NUMBER_TYPE(ntype) |
771 S_0280A0_ENDIAN(endian);
772
773 /* EXPORT_NORM is an optimzation that can be enabled for better
774 * performance in certain cases
775 */
776 if (rctx->family < CHIP_RV770) {
777 /* EXPORT_NORM can be enabled if:
778 * - 11-bit or smaller UNORM/SNORM/SRGB
779 * - BLEND_CLAMP is enabled
780 * - BLEND_FLOAT32 is disabled
781 */
782 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
783 (desc->channel[i].size < 12 &&
784 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
785 ntype != V_0280A0_NUMBER_UINT &&
786 ntype != V_0280A0_NUMBER_SINT) &&
787 G_0280A0_BLEND_CLAMP(color_info) &&
788 !G_0280A0_BLEND_FLOAT32(color_info))
789 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
790 } else {
791 /* EXPORT_NORM can be enabled if:
792 * - 11-bit or smaller UNORM/SNORM/SRGB
793 * - 16-bit or smaller FLOAT
794 */
795 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
796 ((desc->channel[i].size < 12 &&
797 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
798 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
799 (desc->channel[i].size < 17 &&
800 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)))
801 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
802 }
803
804 r600_pipe_state_add_reg(rstate,
805 R_028040_CB_COLOR0_BASE + cb * 4,
806 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
807 r600_pipe_state_add_reg(rstate,
808 R_0280A0_CB_COLOR0_INFO + cb * 4,
809 color_info, 0xFFFFFFFF, bo[0]);
810 r600_pipe_state_add_reg(rstate,
811 R_028060_CB_COLOR0_SIZE + cb * 4,
812 S_028060_PITCH_TILE_MAX(pitch) |
813 S_028060_SLICE_TILE_MAX(slice),
814 0xFFFFFFFF, NULL);
815 r600_pipe_state_add_reg(rstate,
816 R_028080_CB_COLOR0_VIEW + cb * 4,
817 0x00000000, 0xFFFFFFFF, NULL);
818 r600_pipe_state_add_reg(rstate,
819 R_0280E0_CB_COLOR0_FRAG + cb * 4,
820 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
821 r600_pipe_state_add_reg(rstate,
822 R_0280C0_CB_COLOR0_TILE + cb * 4,
823 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
824 r600_pipe_state_add_reg(rstate,
825 R_028100_CB_COLOR0_MASK + cb * 4,
826 0x00000000, 0xFFFFFFFF, NULL);
827 }
828
829 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
830 const struct pipe_framebuffer_state *state)
831 {
832 struct r600_resource_texture *rtex;
833 struct r600_resource *rbuffer;
834 struct r600_surface *surf;
835 unsigned level;
836 unsigned pitch, slice, format;
837 unsigned offset;
838
839 if (state->zsbuf == NULL)
840 return;
841
842 level = state->zsbuf->u.tex.level;
843
844 surf = (struct r600_surface *)state->zsbuf;
845 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
846
847 rbuffer = &rtex->resource;
848
849 /* XXX quite sure for dx10+ hw don't need any offset hacks */
850 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
851 level, state->zsbuf->u.tex.first_layer);
852 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
853 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
854 format = r600_translate_dbformat(state->zsbuf->texture->format);
855
856 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
857 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
858 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
859 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
860 0xFFFFFFFF, NULL);
861 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
862 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
863 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
864 0xFFFFFFFF, rbuffer->bo);
865 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
866 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL);
867 }
868
869 static void r600_set_framebuffer_state(struct pipe_context *ctx,
870 const struct pipe_framebuffer_state *state)
871 {
872 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
873 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
874 u32 shader_mask, tl, br, shader_control, target_mask;
875
876 if (rstate == NULL)
877 return;
878
879 r600_context_flush_dest_caches(&rctx->ctx);
880 rctx->ctx.num_dest_buffers = state->nr_cbufs;
881
882 /* unreference old buffer and reference new one */
883 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
884
885 util_copy_framebuffer_state(&rctx->framebuffer, state);
886
887 /* build states */
888 for (int i = 0; i < state->nr_cbufs; i++) {
889 r600_cb(rctx, rstate, state, i);
890 }
891 if (state->zsbuf) {
892 r600_db(rctx, rstate, state);
893 rctx->ctx.num_dest_buffers++;
894 }
895
896 target_mask = 0x00000000;
897 target_mask = 0xFFFFFFFF;
898 shader_mask = 0;
899 shader_control = 0;
900 for (int i = 0; i < state->nr_cbufs; i++) {
901 target_mask ^= 0xf << (i * 4);
902 shader_mask |= 0xf << (i * 4);
903 shader_control |= 1 << i;
904 }
905 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
906 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
907
908 r600_pipe_state_add_reg(rstate,
909 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
910 0xFFFFFFFF, NULL);
911 r600_pipe_state_add_reg(rstate,
912 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
913 0xFFFFFFFF, NULL);
914 r600_pipe_state_add_reg(rstate,
915 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
916 0xFFFFFFFF, NULL);
917 r600_pipe_state_add_reg(rstate,
918 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
919 0xFFFFFFFF, NULL);
920 r600_pipe_state_add_reg(rstate,
921 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
922 0xFFFFFFFF, NULL);
923 r600_pipe_state_add_reg(rstate,
924 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
925 0xFFFFFFFF, NULL);
926 r600_pipe_state_add_reg(rstate,
927 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
928 0xFFFFFFFF, NULL);
929 r600_pipe_state_add_reg(rstate,
930 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
931 0xFFFFFFFF, NULL);
932 r600_pipe_state_add_reg(rstate,
933 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
934 0xFFFFFFFF, NULL);
935 if (rctx->family >= CHIP_RV770) {
936 r600_pipe_state_add_reg(rstate,
937 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
938 0xFFFFFFFF, NULL);
939 }
940
941 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
942 shader_control, 0xFFFFFFFF, NULL);
943 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
944 0x00000000, target_mask, NULL);
945 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
946 shader_mask, 0xFFFFFFFF, NULL);
947 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
948 0x00000000, 0xFFFFFFFF, NULL);
949 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
950 0x00000000, 0xFFFFFFFF, NULL);
951 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
952 0x00000000, 0xFFFFFFFF, NULL);
953 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
954 0x01000000, 0xFFFFFFFF, NULL);
955 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
956 0x00000000, 0xFFFFFFFF, NULL);
957 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
958 0x000000FF, 0xFFFFFFFF, NULL);
959 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
960 0xFFFFFFFF, 0xFFFFFFFF, NULL);
961 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
962 0xFFFFFFFF, 0xFFFFFFFF, NULL);
963
964 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
965 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
966 r600_context_pipe_state_set(&rctx->ctx, rstate);
967
968 if (state->zsbuf) {
969 r600_polygon_offset_update(rctx);
970 }
971 }
972
973 static void r600_texture_barrier(struct pipe_context *ctx)
974 {
975 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
976
977 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
978 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
979 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
980 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
981 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1));
982 }
983
984 void r600_init_state_functions(struct r600_pipe_context *rctx)
985 {
986 rctx->context.create_blend_state = r600_create_blend_state;
987 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
988 rctx->context.create_fs_state = r600_create_shader_state;
989 rctx->context.create_rasterizer_state = r600_create_rs_state;
990 rctx->context.create_sampler_state = r600_create_sampler_state;
991 rctx->context.create_sampler_view = r600_create_sampler_view;
992 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
993 rctx->context.create_vs_state = r600_create_shader_state;
994 rctx->context.bind_blend_state = r600_bind_blend_state;
995 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
996 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
997 rctx->context.bind_fs_state = r600_bind_ps_shader;
998 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
999 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1000 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
1001 rctx->context.bind_vs_state = r600_bind_vs_shader;
1002 rctx->context.delete_blend_state = r600_delete_state;
1003 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1004 rctx->context.delete_fs_state = r600_delete_ps_shader;
1005 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1006 rctx->context.delete_sampler_state = r600_delete_state;
1007 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1008 rctx->context.delete_vs_state = r600_delete_vs_shader;
1009 rctx->context.set_blend_color = r600_set_blend_color;
1010 rctx->context.set_clip_state = r600_set_clip_state;
1011 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1012 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1013 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1014 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1015 rctx->context.set_sample_mask = r600_set_sample_mask;
1016 rctx->context.set_scissor_state = r600_set_scissor_state;
1017 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1018 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1019 rctx->context.set_index_buffer = r600_set_index_buffer;
1020 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1021 rctx->context.set_viewport_state = r600_set_viewport_state;
1022 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1023 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1024 rctx->context.texture_barrier = r600_texture_barrier;
1025 }
1026
1027 void r600_init_config(struct r600_pipe_context *rctx)
1028 {
1029 int ps_prio;
1030 int vs_prio;
1031 int gs_prio;
1032 int es_prio;
1033 int num_ps_gprs;
1034 int num_vs_gprs;
1035 int num_gs_gprs;
1036 int num_es_gprs;
1037 int num_temp_gprs;
1038 int num_ps_threads;
1039 int num_vs_threads;
1040 int num_gs_threads;
1041 int num_es_threads;
1042 int num_ps_stack_entries;
1043 int num_vs_stack_entries;
1044 int num_gs_stack_entries;
1045 int num_es_stack_entries;
1046 enum radeon_family family;
1047 struct r600_pipe_state *rstate = &rctx->config;
1048 u32 tmp;
1049
1050 family = r600_get_family(rctx->radeon);
1051 ps_prio = 0;
1052 vs_prio = 1;
1053 gs_prio = 2;
1054 es_prio = 3;
1055 switch (family) {
1056 case CHIP_R600:
1057 num_ps_gprs = 192;
1058 num_vs_gprs = 56;
1059 num_temp_gprs = 4;
1060 num_gs_gprs = 0;
1061 num_es_gprs = 0;
1062 num_ps_threads = 136;
1063 num_vs_threads = 48;
1064 num_gs_threads = 4;
1065 num_es_threads = 4;
1066 num_ps_stack_entries = 128;
1067 num_vs_stack_entries = 128;
1068 num_gs_stack_entries = 0;
1069 num_es_stack_entries = 0;
1070 break;
1071 case CHIP_RV630:
1072 case CHIP_RV635:
1073 num_ps_gprs = 84;
1074 num_vs_gprs = 36;
1075 num_temp_gprs = 4;
1076 num_gs_gprs = 0;
1077 num_es_gprs = 0;
1078 num_ps_threads = 144;
1079 num_vs_threads = 40;
1080 num_gs_threads = 4;
1081 num_es_threads = 4;
1082 num_ps_stack_entries = 40;
1083 num_vs_stack_entries = 40;
1084 num_gs_stack_entries = 32;
1085 num_es_stack_entries = 16;
1086 break;
1087 case CHIP_RV610:
1088 case CHIP_RV620:
1089 case CHIP_RS780:
1090 case CHIP_RS880:
1091 default:
1092 num_ps_gprs = 84;
1093 num_vs_gprs = 36;
1094 num_temp_gprs = 4;
1095 num_gs_gprs = 0;
1096 num_es_gprs = 0;
1097 num_ps_threads = 136;
1098 num_vs_threads = 48;
1099 num_gs_threads = 4;
1100 num_es_threads = 4;
1101 num_ps_stack_entries = 40;
1102 num_vs_stack_entries = 40;
1103 num_gs_stack_entries = 32;
1104 num_es_stack_entries = 16;
1105 break;
1106 case CHIP_RV670:
1107 num_ps_gprs = 144;
1108 num_vs_gprs = 40;
1109 num_temp_gprs = 4;
1110 num_gs_gprs = 0;
1111 num_es_gprs = 0;
1112 num_ps_threads = 136;
1113 num_vs_threads = 48;
1114 num_gs_threads = 4;
1115 num_es_threads = 4;
1116 num_ps_stack_entries = 40;
1117 num_vs_stack_entries = 40;
1118 num_gs_stack_entries = 32;
1119 num_es_stack_entries = 16;
1120 break;
1121 case CHIP_RV770:
1122 num_ps_gprs = 192;
1123 num_vs_gprs = 56;
1124 num_temp_gprs = 4;
1125 num_gs_gprs = 0;
1126 num_es_gprs = 0;
1127 num_ps_threads = 188;
1128 num_vs_threads = 60;
1129 num_gs_threads = 0;
1130 num_es_threads = 0;
1131 num_ps_stack_entries = 256;
1132 num_vs_stack_entries = 256;
1133 num_gs_stack_entries = 0;
1134 num_es_stack_entries = 0;
1135 break;
1136 case CHIP_RV730:
1137 case CHIP_RV740:
1138 num_ps_gprs = 84;
1139 num_vs_gprs = 36;
1140 num_temp_gprs = 4;
1141 num_gs_gprs = 0;
1142 num_es_gprs = 0;
1143 num_ps_threads = 188;
1144 num_vs_threads = 60;
1145 num_gs_threads = 0;
1146 num_es_threads = 0;
1147 num_ps_stack_entries = 128;
1148 num_vs_stack_entries = 128;
1149 num_gs_stack_entries = 0;
1150 num_es_stack_entries = 0;
1151 break;
1152 case CHIP_RV710:
1153 num_ps_gprs = 192;
1154 num_vs_gprs = 56;
1155 num_temp_gprs = 4;
1156 num_gs_gprs = 0;
1157 num_es_gprs = 0;
1158 num_ps_threads = 144;
1159 num_vs_threads = 48;
1160 num_gs_threads = 0;
1161 num_es_threads = 0;
1162 num_ps_stack_entries = 128;
1163 num_vs_stack_entries = 128;
1164 num_gs_stack_entries = 0;
1165 num_es_stack_entries = 0;
1166 break;
1167 }
1168
1169 rstate->id = R600_PIPE_STATE_CONFIG;
1170
1171 /* SQ_CONFIG */
1172 tmp = 0;
1173 switch (family) {
1174 case CHIP_RV610:
1175 case CHIP_RV620:
1176 case CHIP_RS780:
1177 case CHIP_RS880:
1178 case CHIP_RV710:
1179 break;
1180 default:
1181 tmp |= S_008C00_VC_ENABLE(1);
1182 break;
1183 }
1184 tmp |= S_008C00_DX9_CONSTS(0);
1185 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1186 tmp |= S_008C00_PS_PRIO(ps_prio);
1187 tmp |= S_008C00_VS_PRIO(vs_prio);
1188 tmp |= S_008C00_GS_PRIO(gs_prio);
1189 tmp |= S_008C00_ES_PRIO(es_prio);
1190 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1191
1192 /* SQ_GPR_RESOURCE_MGMT_1 */
1193 tmp = 0;
1194 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1195 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1196 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1197 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1198
1199 /* SQ_GPR_RESOURCE_MGMT_2 */
1200 tmp = 0;
1201 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1202 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1203 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1204
1205 /* SQ_THREAD_RESOURCE_MGMT */
1206 tmp = 0;
1207 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1208 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1209 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1210 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1211 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1212
1213 /* SQ_STACK_RESOURCE_MGMT_1 */
1214 tmp = 0;
1215 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1216 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1217 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1218
1219 /* SQ_STACK_RESOURCE_MGMT_2 */
1220 tmp = 0;
1221 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1222 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1223 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1224
1225 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1226 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1227
1228 if (family >= CHIP_RV770) {
1229 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1230 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1231 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1232 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1233 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1234 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
1235 } else {
1236 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1237 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1238 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1239 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1240 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1241 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
1242 }
1243 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1244 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1245 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1246 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1247 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1248 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1249 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1250 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1251 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1252 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1253 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1254 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1255 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1256 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1257 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1258 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1259 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1260 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1261 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1262 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1263 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1264 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1265 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1266 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1267 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1268 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1269
1270 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1271 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1272 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1273 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1274 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1275 r600_context_pipe_state_set(&rctx->ctx, rstate);
1276 }
1277
1278 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1279 {
1280 struct r600_pipe_state *rstate = &shader->rstate;
1281 struct r600_shader *rshader = &shader->shader;
1282 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
1283 int pos_index = -1, face_index = -1;
1284
1285 rstate->nregs = 0;
1286
1287 for (i = 0; i < rshader->ninput; i++) {
1288 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1289 pos_index = i;
1290 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1291 face_index = i;
1292 }
1293
1294 db_shader_control = 0;
1295 for (i = 0; i < rshader->noutput; i++) {
1296 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1297 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1298 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1299 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
1300 }
1301 if (rshader->uses_kill)
1302 db_shader_control |= S_02880C_KILL_ENABLE(1);
1303
1304 exports_ps = 0;
1305 num_cout = 0;
1306 for (i = 0; i < rshader->noutput; i++) {
1307 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1308 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1309 exports_ps |= 1;
1310 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1311 num_cout++;
1312 }
1313 }
1314 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
1315 if (!exports_ps) {
1316 /* always at least export 1 component per pixel */
1317 exports_ps = 2;
1318 }
1319
1320 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
1321 S_0286CC_PERSP_GRADIENT_ENA(1);
1322 spi_input_z = 0;
1323 if (pos_index != -1) {
1324 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
1325 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1326 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
1327 S_0286CC_BARYC_SAMPLE_CNTL(1));
1328 spi_input_z |= 1;
1329 }
1330
1331 spi_ps_in_control_1 = 0;
1332 if (face_index != -1) {
1333 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1334 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1335 }
1336
1337 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1338 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1339 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1340 r600_pipe_state_add_reg(rstate,
1341 R_028840_SQ_PGM_START_PS,
1342 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
1343 r600_pipe_state_add_reg(rstate,
1344 R_028850_SQ_PGM_RESOURCES_PS,
1345 S_028868_NUM_GPRS(rshader->bc.ngpr) |
1346 S_028868_STACK_SIZE(rshader->bc.nstack),
1347 0xFFFFFFFF, NULL);
1348 r600_pipe_state_add_reg(rstate,
1349 R_028854_SQ_PGM_EXPORTS_PS,
1350 exports_ps, 0xFFFFFFFF, NULL);
1351 r600_pipe_state_add_reg(rstate,
1352 R_0288CC_SQ_PGM_CF_OFFSET_PS,
1353 0x00000000, 0xFFFFFFFF, NULL);
1354 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
1355 S_028808_MULTIWRITE_ENABLE(!!rshader->fs_write_all),
1356 S_028808_MULTIWRITE_ENABLE(1),
1357 NULL);
1358 /* only set some bits here, the other bits are set in the dsa state */
1359 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
1360 db_shader_control,
1361 S_02880C_Z_EXPORT_ENABLE(1) |
1362 S_02880C_STENCIL_REF_EXPORT_ENABLE(1) |
1363 S_02880C_KILL_ENABLE(1),
1364 NULL);
1365
1366 r600_pipe_state_add_reg(rstate,
1367 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
1368 0xFFFFFFFF, NULL);
1369 }
1370
1371 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1372 {
1373 struct r600_pipe_state *rstate = &shader->rstate;
1374 struct r600_shader *rshader = &shader->shader;
1375 unsigned spi_vs_out_id[10];
1376 unsigned i, tmp;
1377
1378 /* clear previous register */
1379 rstate->nregs = 0;
1380
1381 /* so far never got proper semantic id from tgsi */
1382 /* FIXME better to move this in config things so they get emited
1383 * only one time per cs
1384 */
1385 for (i = 0; i < 10; i++) {
1386 spi_vs_out_id[i] = 0;
1387 }
1388 for (i = 0; i < 32; i++) {
1389 tmp = i << ((i & 3) * 8);
1390 spi_vs_out_id[i / 4] |= tmp;
1391 }
1392 for (i = 0; i < 10; i++) {
1393 r600_pipe_state_add_reg(rstate,
1394 R_028614_SPI_VS_OUT_ID_0 + i * 4,
1395 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1396 }
1397
1398 r600_pipe_state_add_reg(rstate,
1399 R_0286C4_SPI_VS_OUT_CONFIG,
1400 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1401 0xFFFFFFFF, NULL);
1402 r600_pipe_state_add_reg(rstate,
1403 R_028868_SQ_PGM_RESOURCES_VS,
1404 S_028868_NUM_GPRS(rshader->bc.ngpr) |
1405 S_028868_STACK_SIZE(rshader->bc.nstack),
1406 0xFFFFFFFF, NULL);
1407 r600_pipe_state_add_reg(rstate,
1408 R_0288D0_SQ_PGM_CF_OFFSET_VS,
1409 0x00000000, 0xFFFFFFFF, NULL);
1410 r600_pipe_state_add_reg(rstate,
1411 R_028858_SQ_PGM_START_VS,
1412 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
1413
1414 r600_pipe_state_add_reg(rstate,
1415 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1416 0xFFFFFFFF, NULL);
1417 }
1418
1419 void r600_fetch_shader(struct r600_vertex_element *ve)
1420 {
1421 struct r600_pipe_state *rstate;
1422
1423 rstate = &ve->rstate;
1424 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1425 rstate->nregs = 0;
1426 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1427 0x00000000, 0xFFFFFFFF, NULL);
1428 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1429 0x00000000, 0xFFFFFFFF, NULL);
1430 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1431 r600_bo_offset(ve->fetch_shader) >> 8,
1432 0xFFFFFFFF, ve->fetch_shader);
1433 }
1434
1435 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1436 {
1437 struct pipe_depth_stencil_alpha_state dsa;
1438 struct r600_pipe_state *rstate;
1439 boolean quirk = false;
1440
1441 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1442 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1443 quirk = true;
1444
1445 memset(&dsa, 0, sizeof(dsa));
1446
1447 if (quirk) {
1448 dsa.depth.enabled = 1;
1449 dsa.depth.func = PIPE_FUNC_LEQUAL;
1450 dsa.stencil[0].enabled = 1;
1451 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1452 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1453 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1454 dsa.stencil[0].writemask = 0xff;
1455 }
1456
1457 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1458 r600_pipe_state_add_reg(rstate,
1459 R_02880C_DB_SHADER_CONTROL,
1460 0x0,
1461 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1462 r600_pipe_state_add_reg(rstate,
1463 R_028D0C_DB_RENDER_CONTROL,
1464 S_028D0C_DEPTH_COPY_ENABLE(1) |
1465 S_028D0C_STENCIL_COPY_ENABLE(1) |
1466 S_028D0C_COPY_CENTROID(1),
1467 S_028D0C_DEPTH_COPY_ENABLE(1) |
1468 S_028D0C_STENCIL_COPY_ENABLE(1) |
1469 S_028D0C_COPY_CENTROID(1), NULL);
1470 return rstate;
1471 }
1472
1473 void r600_pipe_set_buffer_resource(struct r600_pipe_context *rctx,
1474 struct r600_pipe_state *rstate,
1475 struct r600_resource *rbuffer,
1476 unsigned offset, unsigned stride)
1477 {
1478 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
1479 offset, 0xFFFFFFFF, rbuffer->bo);
1480 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
1481 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
1482 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
1483 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1484 S_038008_STRIDE(stride), 0xFFFFFFFF, NULL);
1485 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
1486 0x00000000, 0xFFFFFFFF, NULL);
1487 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
1488 0x00000000, 0xFFFFFFFF, NULL);
1489 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
1490 0x00000000, 0xFFFFFFFF, NULL);
1491 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
1492 0xC0000000, 0xFFFFFFFF, NULL);
1493 }