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3fd77daae7d8fa0091db4e21138480acf1f3f233
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600d.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31
32 static uint32_t r600_translate_blend_function(int blend_func)
33 {
34 switch (blend_func) {
35 case PIPE_BLEND_ADD:
36 return V_028804_COMB_DST_PLUS_SRC;
37 case PIPE_BLEND_SUBTRACT:
38 return V_028804_COMB_SRC_MINUS_DST;
39 case PIPE_BLEND_REVERSE_SUBTRACT:
40 return V_028804_COMB_DST_MINUS_SRC;
41 case PIPE_BLEND_MIN:
42 return V_028804_COMB_MIN_DST_SRC;
43 case PIPE_BLEND_MAX:
44 return V_028804_COMB_MAX_DST_SRC;
45 default:
46 R600_ERR("Unknown blend function %d\n", blend_func);
47 assert(0);
48 break;
49 }
50 return 0;
51 }
52
53 static uint32_t r600_translate_blend_factor(int blend_fact)
54 {
55 switch (blend_fact) {
56 case PIPE_BLENDFACTOR_ONE:
57 return V_028804_BLEND_ONE;
58 case PIPE_BLENDFACTOR_SRC_COLOR:
59 return V_028804_BLEND_SRC_COLOR;
60 case PIPE_BLENDFACTOR_SRC_ALPHA:
61 return V_028804_BLEND_SRC_ALPHA;
62 case PIPE_BLENDFACTOR_DST_ALPHA:
63 return V_028804_BLEND_DST_ALPHA;
64 case PIPE_BLENDFACTOR_DST_COLOR:
65 return V_028804_BLEND_DST_COLOR;
66 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
67 return V_028804_BLEND_SRC_ALPHA_SATURATE;
68 case PIPE_BLENDFACTOR_CONST_COLOR:
69 return V_028804_BLEND_CONST_COLOR;
70 case PIPE_BLENDFACTOR_CONST_ALPHA:
71 return V_028804_BLEND_CONST_ALPHA;
72 case PIPE_BLENDFACTOR_ZERO:
73 return V_028804_BLEND_ZERO;
74 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
75 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
76 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
77 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
78 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
79 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
80 case PIPE_BLENDFACTOR_INV_DST_COLOR:
81 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
82 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
83 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
84 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
85 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
86 case PIPE_BLENDFACTOR_SRC1_COLOR:
87 return V_028804_BLEND_SRC1_COLOR;
88 case PIPE_BLENDFACTOR_SRC1_ALPHA:
89 return V_028804_BLEND_SRC1_ALPHA;
90 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
91 return V_028804_BLEND_INV_SRC1_COLOR;
92 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
93 return V_028804_BLEND_INV_SRC1_ALPHA;
94 default:
95 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
96 assert(0);
97 break;
98 }
99 return 0;
100 }
101
102 static unsigned r600_tex_dim(unsigned dim)
103 {
104 switch (dim) {
105 default:
106 case PIPE_TEXTURE_1D:
107 return V_038000_SQ_TEX_DIM_1D;
108 case PIPE_TEXTURE_1D_ARRAY:
109 return V_038000_SQ_TEX_DIM_1D_ARRAY;
110 case PIPE_TEXTURE_2D:
111 case PIPE_TEXTURE_RECT:
112 return V_038000_SQ_TEX_DIM_2D;
113 case PIPE_TEXTURE_2D_ARRAY:
114 return V_038000_SQ_TEX_DIM_2D_ARRAY;
115 case PIPE_TEXTURE_3D:
116 return V_038000_SQ_TEX_DIM_3D;
117 case PIPE_TEXTURE_CUBE:
118 return V_038000_SQ_TEX_DIM_CUBEMAP;
119 }
120 }
121
122 static uint32_t r600_translate_dbformat(enum pipe_format format)
123 {
124 switch (format) {
125 case PIPE_FORMAT_Z16_UNORM:
126 return V_028010_DEPTH_16;
127 case PIPE_FORMAT_Z24X8_UNORM:
128 return V_028010_DEPTH_X8_24;
129 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
130 return V_028010_DEPTH_8_24;
131 case PIPE_FORMAT_Z32_FLOAT:
132 return V_028010_DEPTH_32_FLOAT;
133 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
134 return V_028010_DEPTH_X24_8_32_FLOAT;
135 default:
136 return ~0U;
137 }
138 }
139
140 static uint32_t r600_translate_colorswap(enum pipe_format format)
141 {
142 switch (format) {
143 /* 8-bit buffers. */
144 case PIPE_FORMAT_A8_UNORM:
145 case PIPE_FORMAT_A8_SNORM:
146 case PIPE_FORMAT_A8_UINT:
147 case PIPE_FORMAT_A8_SINT:
148 case PIPE_FORMAT_A16_UNORM:
149 case PIPE_FORMAT_A16_SNORM:
150 case PIPE_FORMAT_A16_UINT:
151 case PIPE_FORMAT_A16_SINT:
152 case PIPE_FORMAT_A16_FLOAT:
153 case PIPE_FORMAT_A32_UINT:
154 case PIPE_FORMAT_A32_SINT:
155 case PIPE_FORMAT_A32_FLOAT:
156 case PIPE_FORMAT_R4A4_UNORM:
157 return V_0280A0_SWAP_ALT_REV;
158 case PIPE_FORMAT_I8_UNORM:
159 case PIPE_FORMAT_I8_SNORM:
160 case PIPE_FORMAT_I8_UINT:
161 case PIPE_FORMAT_I8_SINT:
162 case PIPE_FORMAT_L8_UNORM:
163 case PIPE_FORMAT_L8_SNORM:
164 case PIPE_FORMAT_L8_UINT:
165 case PIPE_FORMAT_L8_SINT:
166 case PIPE_FORMAT_L8_SRGB:
167 case PIPE_FORMAT_L16_UNORM:
168 case PIPE_FORMAT_L16_SNORM:
169 case PIPE_FORMAT_L16_UINT:
170 case PIPE_FORMAT_L16_SINT:
171 case PIPE_FORMAT_L16_FLOAT:
172 case PIPE_FORMAT_L32_UINT:
173 case PIPE_FORMAT_L32_SINT:
174 case PIPE_FORMAT_L32_FLOAT:
175 case PIPE_FORMAT_I16_UNORM:
176 case PIPE_FORMAT_I16_SNORM:
177 case PIPE_FORMAT_I16_UINT:
178 case PIPE_FORMAT_I16_SINT:
179 case PIPE_FORMAT_I16_FLOAT:
180 case PIPE_FORMAT_I32_UINT:
181 case PIPE_FORMAT_I32_SINT:
182 case PIPE_FORMAT_I32_FLOAT:
183 case PIPE_FORMAT_R8_UNORM:
184 case PIPE_FORMAT_R8_SNORM:
185 case PIPE_FORMAT_R8_UINT:
186 case PIPE_FORMAT_R8_SINT:
187 return V_0280A0_SWAP_STD;
188
189 case PIPE_FORMAT_L4A4_UNORM:
190 case PIPE_FORMAT_A4R4_UNORM:
191 return V_0280A0_SWAP_ALT;
192
193 /* 16-bit buffers. */
194 case PIPE_FORMAT_B5G6R5_UNORM:
195 return V_0280A0_SWAP_STD_REV;
196
197 case PIPE_FORMAT_B5G5R5A1_UNORM:
198 case PIPE_FORMAT_B5G5R5X1_UNORM:
199 return V_0280A0_SWAP_ALT;
200
201 case PIPE_FORMAT_B4G4R4A4_UNORM:
202 case PIPE_FORMAT_B4G4R4X4_UNORM:
203 return V_0280A0_SWAP_ALT;
204
205 case PIPE_FORMAT_Z16_UNORM:
206 return V_0280A0_SWAP_STD;
207
208 case PIPE_FORMAT_L8A8_UNORM:
209 case PIPE_FORMAT_L8A8_SNORM:
210 case PIPE_FORMAT_L8A8_UINT:
211 case PIPE_FORMAT_L8A8_SINT:
212 case PIPE_FORMAT_L8A8_SRGB:
213 case PIPE_FORMAT_L16A16_UNORM:
214 case PIPE_FORMAT_L16A16_SNORM:
215 case PIPE_FORMAT_L16A16_UINT:
216 case PIPE_FORMAT_L16A16_SINT:
217 case PIPE_FORMAT_L16A16_FLOAT:
218 case PIPE_FORMAT_L32A32_UINT:
219 case PIPE_FORMAT_L32A32_SINT:
220 case PIPE_FORMAT_L32A32_FLOAT:
221 return V_0280A0_SWAP_ALT;
222 case PIPE_FORMAT_R8G8_UNORM:
223 case PIPE_FORMAT_R8G8_SNORM:
224 case PIPE_FORMAT_R8G8_UINT:
225 case PIPE_FORMAT_R8G8_SINT:
226 return V_0280A0_SWAP_STD;
227
228 case PIPE_FORMAT_R16_UNORM:
229 case PIPE_FORMAT_R16_SNORM:
230 case PIPE_FORMAT_R16_UINT:
231 case PIPE_FORMAT_R16_SINT:
232 case PIPE_FORMAT_R16_FLOAT:
233 return V_0280A0_SWAP_STD;
234
235 /* 32-bit buffers. */
236
237 case PIPE_FORMAT_A8B8G8R8_SRGB:
238 return V_0280A0_SWAP_STD_REV;
239 case PIPE_FORMAT_B8G8R8A8_SRGB:
240 return V_0280A0_SWAP_ALT;
241
242 case PIPE_FORMAT_B8G8R8A8_UNORM:
243 case PIPE_FORMAT_B8G8R8X8_UNORM:
244 return V_0280A0_SWAP_ALT;
245
246 case PIPE_FORMAT_A8R8G8B8_UNORM:
247 case PIPE_FORMAT_X8R8G8B8_UNORM:
248 return V_0280A0_SWAP_ALT_REV;
249 case PIPE_FORMAT_R8G8B8A8_SNORM:
250 case PIPE_FORMAT_R8G8B8A8_UNORM:
251 case PIPE_FORMAT_R8G8B8X8_UNORM:
252 case PIPE_FORMAT_R8G8B8A8_SINT:
253 case PIPE_FORMAT_R8G8B8A8_UINT:
254 return V_0280A0_SWAP_STD;
255
256 case PIPE_FORMAT_A8B8G8R8_UNORM:
257 case PIPE_FORMAT_X8B8G8R8_UNORM:
258 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
259 return V_0280A0_SWAP_STD_REV;
260
261 case PIPE_FORMAT_Z24X8_UNORM:
262 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
263 return V_0280A0_SWAP_STD;
264
265 case PIPE_FORMAT_X8Z24_UNORM:
266 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
267 return V_0280A0_SWAP_STD;
268
269 case PIPE_FORMAT_R10G10B10A2_UNORM:
270 case PIPE_FORMAT_R10G10B10X2_SNORM:
271 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
272 return V_0280A0_SWAP_STD;
273
274 case PIPE_FORMAT_B10G10R10A2_UNORM:
275 case PIPE_FORMAT_B10G10R10A2_UINT:
276 return V_0280A0_SWAP_ALT;
277
278 case PIPE_FORMAT_R11G11B10_FLOAT:
279 case PIPE_FORMAT_R16G16_UNORM:
280 case PIPE_FORMAT_R16G16_SNORM:
281 case PIPE_FORMAT_R16G16_FLOAT:
282 case PIPE_FORMAT_R16G16_UINT:
283 case PIPE_FORMAT_R16G16_SINT:
284 case PIPE_FORMAT_R16G16B16_FLOAT:
285 case PIPE_FORMAT_R32G32B32_FLOAT:
286 case PIPE_FORMAT_R32_UINT:
287 case PIPE_FORMAT_R32_SINT:
288 case PIPE_FORMAT_R32_FLOAT:
289 case PIPE_FORMAT_Z32_FLOAT:
290 return V_0280A0_SWAP_STD;
291
292 /* 64-bit buffers. */
293 case PIPE_FORMAT_R32G32_FLOAT:
294 case PIPE_FORMAT_R32G32_UINT:
295 case PIPE_FORMAT_R32G32_SINT:
296 case PIPE_FORMAT_R16G16B16A16_UNORM:
297 case PIPE_FORMAT_R16G16B16A16_SNORM:
298 case PIPE_FORMAT_R16G16B16A16_UINT:
299 case PIPE_FORMAT_R16G16B16A16_SINT:
300 case PIPE_FORMAT_R16G16B16A16_FLOAT:
301 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
302
303 /* 128-bit buffers. */
304 case PIPE_FORMAT_R32G32B32A32_FLOAT:
305 case PIPE_FORMAT_R32G32B32A32_SNORM:
306 case PIPE_FORMAT_R32G32B32A32_UNORM:
307 case PIPE_FORMAT_R32G32B32A32_SINT:
308 case PIPE_FORMAT_R32G32B32A32_UINT:
309 return V_0280A0_SWAP_STD;
310 default:
311 R600_ERR("unsupported colorswap format %d\n", format);
312 return ~0U;
313 }
314 return ~0U;
315 }
316
317 static uint32_t r600_translate_colorformat(enum pipe_format format)
318 {
319 switch (format) {
320 case PIPE_FORMAT_L4A4_UNORM:
321 case PIPE_FORMAT_R4A4_UNORM:
322 case PIPE_FORMAT_A4R4_UNORM:
323 return V_0280A0_COLOR_4_4;
324
325 /* 8-bit buffers. */
326 case PIPE_FORMAT_A8_UNORM:
327 case PIPE_FORMAT_A8_SNORM:
328 case PIPE_FORMAT_A8_UINT:
329 case PIPE_FORMAT_A8_SINT:
330 case PIPE_FORMAT_I8_UNORM:
331 case PIPE_FORMAT_I8_SNORM:
332 case PIPE_FORMAT_I8_UINT:
333 case PIPE_FORMAT_I8_SINT:
334 case PIPE_FORMAT_L8_UNORM:
335 case PIPE_FORMAT_L8_SNORM:
336 case PIPE_FORMAT_L8_UINT:
337 case PIPE_FORMAT_L8_SINT:
338 case PIPE_FORMAT_L8_SRGB:
339 case PIPE_FORMAT_R8_UNORM:
340 case PIPE_FORMAT_R8_SNORM:
341 case PIPE_FORMAT_R8_UINT:
342 case PIPE_FORMAT_R8_SINT:
343 return V_0280A0_COLOR_8;
344
345 /* 16-bit buffers. */
346 case PIPE_FORMAT_B5G6R5_UNORM:
347 return V_0280A0_COLOR_5_6_5;
348
349 case PIPE_FORMAT_B5G5R5A1_UNORM:
350 case PIPE_FORMAT_B5G5R5X1_UNORM:
351 return V_0280A0_COLOR_1_5_5_5;
352
353 case PIPE_FORMAT_B4G4R4A4_UNORM:
354 case PIPE_FORMAT_B4G4R4X4_UNORM:
355 return V_0280A0_COLOR_4_4_4_4;
356
357 case PIPE_FORMAT_Z16_UNORM:
358 return V_0280A0_COLOR_16;
359
360 case PIPE_FORMAT_L8A8_UNORM:
361 case PIPE_FORMAT_L8A8_SNORM:
362 case PIPE_FORMAT_L8A8_UINT:
363 case PIPE_FORMAT_L8A8_SINT:
364 case PIPE_FORMAT_L8A8_SRGB:
365 case PIPE_FORMAT_R8G8_UNORM:
366 case PIPE_FORMAT_R8G8_SNORM:
367 case PIPE_FORMAT_R8G8_UINT:
368 case PIPE_FORMAT_R8G8_SINT:
369 return V_0280A0_COLOR_8_8;
370
371 case PIPE_FORMAT_R16_UNORM:
372 case PIPE_FORMAT_R16_SNORM:
373 case PIPE_FORMAT_R16_UINT:
374 case PIPE_FORMAT_R16_SINT:
375 case PIPE_FORMAT_A16_UNORM:
376 case PIPE_FORMAT_A16_SNORM:
377 case PIPE_FORMAT_A16_UINT:
378 case PIPE_FORMAT_A16_SINT:
379 case PIPE_FORMAT_L16_UNORM:
380 case PIPE_FORMAT_L16_SNORM:
381 case PIPE_FORMAT_L16_UINT:
382 case PIPE_FORMAT_L16_SINT:
383 case PIPE_FORMAT_I16_UNORM:
384 case PIPE_FORMAT_I16_SNORM:
385 case PIPE_FORMAT_I16_UINT:
386 case PIPE_FORMAT_I16_SINT:
387 return V_0280A0_COLOR_16;
388
389 case PIPE_FORMAT_R16_FLOAT:
390 case PIPE_FORMAT_A16_FLOAT:
391 case PIPE_FORMAT_L16_FLOAT:
392 case PIPE_FORMAT_I16_FLOAT:
393 return V_0280A0_COLOR_16_FLOAT;
394
395 /* 32-bit buffers. */
396 case PIPE_FORMAT_A8B8G8R8_SRGB:
397 case PIPE_FORMAT_A8B8G8R8_UNORM:
398 case PIPE_FORMAT_A8R8G8B8_UNORM:
399 case PIPE_FORMAT_B8G8R8A8_SRGB:
400 case PIPE_FORMAT_B8G8R8A8_UNORM:
401 case PIPE_FORMAT_B8G8R8X8_UNORM:
402 case PIPE_FORMAT_R8G8B8A8_SNORM:
403 case PIPE_FORMAT_R8G8B8A8_UNORM:
404 case PIPE_FORMAT_R8G8B8X8_UNORM:
405 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
406 case PIPE_FORMAT_X8B8G8R8_UNORM:
407 case PIPE_FORMAT_X8R8G8B8_UNORM:
408 case PIPE_FORMAT_R8G8B8_UNORM:
409 case PIPE_FORMAT_R8G8B8A8_SINT:
410 case PIPE_FORMAT_R8G8B8A8_UINT:
411 return V_0280A0_COLOR_8_8_8_8;
412
413 case PIPE_FORMAT_R10G10B10A2_UNORM:
414 case PIPE_FORMAT_R10G10B10X2_SNORM:
415 case PIPE_FORMAT_B10G10R10A2_UNORM:
416 case PIPE_FORMAT_B10G10R10A2_UINT:
417 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
418 return V_0280A0_COLOR_2_10_10_10;
419
420 case PIPE_FORMAT_Z24X8_UNORM:
421 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
422 return V_0280A0_COLOR_8_24;
423
424 case PIPE_FORMAT_X8Z24_UNORM:
425 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
426 return V_0280A0_COLOR_24_8;
427
428 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
429 return V_0280A0_COLOR_X24_8_32_FLOAT;
430
431 case PIPE_FORMAT_R32_UINT:
432 case PIPE_FORMAT_R32_SINT:
433 case PIPE_FORMAT_A32_UINT:
434 case PIPE_FORMAT_A32_SINT:
435 case PIPE_FORMAT_L32_UINT:
436 case PIPE_FORMAT_L32_SINT:
437 case PIPE_FORMAT_I32_UINT:
438 case PIPE_FORMAT_I32_SINT:
439 return V_0280A0_COLOR_32;
440
441 case PIPE_FORMAT_R32_FLOAT:
442 case PIPE_FORMAT_A32_FLOAT:
443 case PIPE_FORMAT_L32_FLOAT:
444 case PIPE_FORMAT_I32_FLOAT:
445 case PIPE_FORMAT_Z32_FLOAT:
446 return V_0280A0_COLOR_32_FLOAT;
447
448 case PIPE_FORMAT_R16G16_FLOAT:
449 case PIPE_FORMAT_L16A16_FLOAT:
450 return V_0280A0_COLOR_16_16_FLOAT;
451
452 case PIPE_FORMAT_R16G16_UNORM:
453 case PIPE_FORMAT_R16G16_SNORM:
454 case PIPE_FORMAT_R16G16_UINT:
455 case PIPE_FORMAT_R16G16_SINT:
456 case PIPE_FORMAT_L16A16_UNORM:
457 case PIPE_FORMAT_L16A16_SNORM:
458 case PIPE_FORMAT_L16A16_UINT:
459 case PIPE_FORMAT_L16A16_SINT:
460 return V_0280A0_COLOR_16_16;
461
462 case PIPE_FORMAT_R11G11B10_FLOAT:
463 return V_0280A0_COLOR_10_11_11_FLOAT;
464
465 /* 64-bit buffers. */
466 case PIPE_FORMAT_R16G16B16A16_UINT:
467 case PIPE_FORMAT_R16G16B16A16_SINT:
468 case PIPE_FORMAT_R16G16B16A16_UNORM:
469 case PIPE_FORMAT_R16G16B16A16_SNORM:
470 return V_0280A0_COLOR_16_16_16_16;
471
472 case PIPE_FORMAT_R16G16B16_FLOAT:
473 case PIPE_FORMAT_R16G16B16A16_FLOAT:
474 return V_0280A0_COLOR_16_16_16_16_FLOAT;
475
476 case PIPE_FORMAT_R32G32_FLOAT:
477 case PIPE_FORMAT_L32A32_FLOAT:
478 return V_0280A0_COLOR_32_32_FLOAT;
479
480 case PIPE_FORMAT_R32G32_SINT:
481 case PIPE_FORMAT_R32G32_UINT:
482 case PIPE_FORMAT_L32A32_UINT:
483 case PIPE_FORMAT_L32A32_SINT:
484 return V_0280A0_COLOR_32_32;
485
486 /* 96-bit buffers. */
487 case PIPE_FORMAT_R32G32B32_FLOAT:
488 return V_0280A0_COLOR_32_32_32_FLOAT;
489
490 /* 128-bit buffers. */
491 case PIPE_FORMAT_R32G32B32A32_FLOAT:
492 return V_0280A0_COLOR_32_32_32_32_FLOAT;
493 case PIPE_FORMAT_R32G32B32A32_SNORM:
494 case PIPE_FORMAT_R32G32B32A32_UNORM:
495 case PIPE_FORMAT_R32G32B32A32_SINT:
496 case PIPE_FORMAT_R32G32B32A32_UINT:
497 return V_0280A0_COLOR_32_32_32_32;
498
499 /* YUV buffers. */
500 case PIPE_FORMAT_UYVY:
501 case PIPE_FORMAT_YUYV:
502 default:
503 return ~0U; /* Unsupported. */
504 }
505 }
506
507 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
508 {
509 if (R600_BIG_ENDIAN) {
510 switch(colorformat) {
511 case V_0280A0_COLOR_4_4:
512 return ENDIAN_NONE;
513
514 /* 8-bit buffers. */
515 case V_0280A0_COLOR_8:
516 return ENDIAN_NONE;
517
518 /* 16-bit buffers. */
519 case V_0280A0_COLOR_5_6_5:
520 case V_0280A0_COLOR_1_5_5_5:
521 case V_0280A0_COLOR_4_4_4_4:
522 case V_0280A0_COLOR_16:
523 case V_0280A0_COLOR_8_8:
524 return ENDIAN_8IN16;
525
526 /* 32-bit buffers. */
527 case V_0280A0_COLOR_8_8_8_8:
528 case V_0280A0_COLOR_2_10_10_10:
529 case V_0280A0_COLOR_8_24:
530 case V_0280A0_COLOR_24_8:
531 case V_0280A0_COLOR_32_FLOAT:
532 case V_0280A0_COLOR_16_16_FLOAT:
533 case V_0280A0_COLOR_16_16:
534 return ENDIAN_8IN32;
535
536 /* 64-bit buffers. */
537 case V_0280A0_COLOR_16_16_16_16:
538 case V_0280A0_COLOR_16_16_16_16_FLOAT:
539 return ENDIAN_8IN16;
540
541 case V_0280A0_COLOR_32_32_FLOAT:
542 case V_0280A0_COLOR_32_32:
543 case V_0280A0_COLOR_X24_8_32_FLOAT:
544 return ENDIAN_8IN32;
545
546 /* 128-bit buffers. */
547 case V_0280A0_COLOR_32_32_32_FLOAT:
548 case V_0280A0_COLOR_32_32_32_32_FLOAT:
549 case V_0280A0_COLOR_32_32_32_32:
550 return ENDIAN_8IN32;
551 default:
552 return ENDIAN_NONE; /* Unsupported. */
553 }
554 } else {
555 return ENDIAN_NONE;
556 }
557 }
558
559 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
560 {
561 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
562 }
563
564 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
565 {
566 return r600_translate_colorformat(format) != ~0U &&
567 r600_translate_colorswap(format) != ~0U;
568 }
569
570 static bool r600_is_zs_format_supported(enum pipe_format format)
571 {
572 return r600_translate_dbformat(format) != ~0U;
573 }
574
575 boolean r600_is_format_supported(struct pipe_screen *screen,
576 enum pipe_format format,
577 enum pipe_texture_target target,
578 unsigned sample_count,
579 unsigned usage)
580 {
581 unsigned retval = 0;
582
583 if (target >= PIPE_MAX_TEXTURE_TYPES) {
584 R600_ERR("r600: unsupported texture type %d\n", target);
585 return FALSE;
586 }
587
588 if (!util_format_is_supported(format, usage))
589 return FALSE;
590
591 /* Multisample */
592 if (sample_count > 1)
593 return FALSE;
594
595 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
596 r600_is_sampler_format_supported(screen, format)) {
597 retval |= PIPE_BIND_SAMPLER_VIEW;
598 }
599
600 if ((usage & (PIPE_BIND_RENDER_TARGET |
601 PIPE_BIND_DISPLAY_TARGET |
602 PIPE_BIND_SCANOUT |
603 PIPE_BIND_SHARED)) &&
604 r600_is_colorbuffer_format_supported(format)) {
605 retval |= usage &
606 (PIPE_BIND_RENDER_TARGET |
607 PIPE_BIND_DISPLAY_TARGET |
608 PIPE_BIND_SCANOUT |
609 PIPE_BIND_SHARED);
610 }
611
612 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
613 r600_is_zs_format_supported(format)) {
614 retval |= PIPE_BIND_DEPTH_STENCIL;
615 }
616
617 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
618 r600_is_vertex_format_supported(format)) {
619 retval |= PIPE_BIND_VERTEX_BUFFER;
620 }
621
622 if (usage & PIPE_BIND_TRANSFER_READ)
623 retval |= PIPE_BIND_TRANSFER_READ;
624 if (usage & PIPE_BIND_TRANSFER_WRITE)
625 retval |= PIPE_BIND_TRANSFER_WRITE;
626
627 return retval == usage;
628 }
629
630 void r600_polygon_offset_update(struct r600_context *rctx)
631 {
632 struct r600_pipe_state state;
633
634 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
635 state.nregs = 0;
636 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
637 float offset_units = rctx->rasterizer->offset_units;
638 unsigned offset_db_fmt_cntl = 0, depth;
639
640 switch (rctx->framebuffer.zsbuf->format) {
641 case PIPE_FORMAT_Z24X8_UNORM:
642 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
643 depth = -24;
644 offset_units *= 2.0f;
645 break;
646 case PIPE_FORMAT_Z32_FLOAT:
647 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
648 depth = -23;
649 offset_units *= 1.0f;
650 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
651 break;
652 case PIPE_FORMAT_Z16_UNORM:
653 depth = -16;
654 offset_units *= 4.0f;
655 break;
656 default:
657 return;
658 }
659 /* XXX some of those reg can be computed with cso */
660 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
661 r600_pipe_state_add_reg(&state,
662 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
663 fui(rctx->rasterizer->offset_scale));
664 r600_pipe_state_add_reg(&state,
665 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
666 fui(offset_units));
667 r600_pipe_state_add_reg(&state,
668 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
669 fui(rctx->rasterizer->offset_scale));
670 r600_pipe_state_add_reg(&state,
671 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
672 fui(offset_units));
673 r600_pipe_state_add_reg(&state,
674 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
675 offset_db_fmt_cntl);
676 r600_context_pipe_state_set(rctx, &state);
677 }
678 }
679
680 static void *r600_create_blend_state(struct pipe_context *ctx,
681 const struct pipe_blend_state *state)
682 {
683 struct r600_context *rctx = (struct r600_context *)ctx;
684 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
685 struct r600_pipe_state *rstate;
686 uint32_t color_control = 0, target_mask;
687
688 if (blend == NULL) {
689 return NULL;
690 }
691 rstate = &blend->rstate;
692
693 rstate->id = R600_PIPE_STATE_BLEND;
694
695 target_mask = 0;
696
697 /* R600 does not support per-MRT blends */
698 if (rctx->family > CHIP_R600)
699 color_control |= S_028808_PER_MRT_BLEND(1);
700 if (state->logicop_enable) {
701 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
702 } else {
703 color_control |= (0xcc << 16);
704 }
705 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
706 if (state->independent_blend_enable) {
707 for (int i = 0; i < 8; i++) {
708 if (state->rt[i].blend_enable) {
709 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
710 }
711 target_mask |= (state->rt[i].colormask << (4 * i));
712 }
713 } else {
714 for (int i = 0; i < 8; i++) {
715 if (state->rt[0].blend_enable) {
716 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
717 }
718 target_mask |= (state->rt[0].colormask << (4 * i));
719 }
720 }
721 blend->cb_target_mask = target_mask;
722 blend->cb_color_control = color_control;
723 /* only MRT0 has dual src blend */
724 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
725 for (int i = 0; i < 8; i++) {
726 /* state->rt entries > 0 only written if independent blending */
727 const int j = state->independent_blend_enable ? i : 0;
728
729 unsigned eqRGB = state->rt[j].rgb_func;
730 unsigned srcRGB = state->rt[j].rgb_src_factor;
731 unsigned dstRGB = state->rt[j].rgb_dst_factor;
732
733 unsigned eqA = state->rt[j].alpha_func;
734 unsigned srcA = state->rt[j].alpha_src_factor;
735 unsigned dstA = state->rt[j].alpha_dst_factor;
736 uint32_t bc = 0;
737
738 if (!state->rt[j].blend_enable)
739 continue;
740
741 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
742 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
743 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
744
745 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
746 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
747 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
748 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
749 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
750 }
751
752 /* R600 does not support per-MRT blends */
753 if (rctx->family > CHIP_R600)
754 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc);
755 if (i == 0)
756 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
757 }
758 return rstate;
759 }
760
761 static void *r600_create_dsa_state(struct pipe_context *ctx,
762 const struct pipe_depth_stencil_alpha_state *state)
763 {
764 struct r600_context *rctx = (struct r600_context *)ctx;
765 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
766 unsigned db_depth_control, alpha_test_control, alpha_ref;
767 struct r600_pipe_state *rstate;
768
769 if (dsa == NULL) {
770 return NULL;
771 }
772
773 dsa->valuemask[0] = state->stencil[0].valuemask;
774 dsa->valuemask[1] = state->stencil[1].valuemask;
775 dsa->writemask[0] = state->stencil[0].writemask;
776 dsa->writemask[1] = state->stencil[1].writemask;
777
778 rstate = &dsa->rstate;
779
780 rstate->id = R600_PIPE_STATE_DSA;
781 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
782 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
783 S_028800_ZFUNC(state->depth.func);
784
785 /* stencil */
786 if (state->stencil[0].enabled) {
787 db_depth_control |= S_028800_STENCIL_ENABLE(1);
788 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
789 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
790 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
791 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
792
793 if (state->stencil[1].enabled) {
794 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
795 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
796 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
797 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
798 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
799 }
800 }
801
802 /* alpha */
803 alpha_test_control = 0;
804 alpha_ref = 0;
805 if (state->alpha.enabled) {
806 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
807 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
808 alpha_ref = fui(state->alpha.ref_value);
809 }
810 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
811 dsa->alpha_ref = alpha_ref;
812
813 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
814 return rstate;
815 }
816
817 static void *r600_create_rs_state(struct pipe_context *ctx,
818 const struct pipe_rasterizer_state *state)
819 {
820 struct r600_context *rctx = (struct r600_context *)ctx;
821 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
822 struct r600_pipe_state *rstate;
823 unsigned tmp;
824 unsigned prov_vtx = 1, polygon_dual_mode;
825 unsigned sc_mode_cntl;
826 float psize_min, psize_max;
827
828 if (rs == NULL) {
829 return NULL;
830 }
831
832 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
833 state->fill_back != PIPE_POLYGON_MODE_FILL);
834
835 if (state->flatshade_first)
836 prov_vtx = 0;
837
838 rstate = &rs->rstate;
839 rs->flatshade = state->flatshade;
840 rs->sprite_coord_enable = state->sprite_coord_enable;
841 rs->two_side = state->light_twoside;
842 rs->clip_plane_enable = state->clip_plane_enable;
843 rs->pa_sc_line_stipple = state->line_stipple_enable ?
844 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
845 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
846 rs->pa_cl_clip_cntl =
847 S_028810_PS_UCP_MODE(3) |
848 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
849 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
850 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
851
852 /* offset */
853 rs->offset_units = state->offset_units;
854 rs->offset_scale = state->offset_scale * 12.0f;
855
856 rstate->id = R600_PIPE_STATE_RASTERIZER;
857 tmp = S_0286D4_FLAT_SHADE_ENA(1);
858 if (state->sprite_coord_enable) {
859 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
860 S_0286D4_PNT_SPRITE_OVRD_X(2) |
861 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
862 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
863 S_0286D4_PNT_SPRITE_OVRD_W(1);
864 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
865 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
866 }
867 }
868 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
869
870 /* point size 12.4 fixed point */
871 tmp = r600_pack_float_12p4(state->point_size/2);
872 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
873
874 if (state->point_size_per_vertex) {
875 psize_min = util_get_min_point_size(state);
876 psize_max = 8192;
877 } else {
878 /* Force the point size to be as if the vertex output was disabled. */
879 psize_min = state->point_size;
880 psize_max = state->point_size;
881 }
882 /* Divide by two, because 0.5 = 1 pixel. */
883 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
884 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
885 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
886
887 tmp = r600_pack_float_12p4(state->line_width/2);
888 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
889
890 if (rctx->chip_class >= R700) {
891 sc_mode_cntl =
892 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
893 S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
894 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
895 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
896 } else {
897 sc_mode_cntl =
898 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
899 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
900 rs->scissor_enable = state->scissor;
901 }
902 sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
903
904 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
905
906 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
907 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
908
909 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
910 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
911 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
912 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
913 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
914 S_028814_FACE(!state->front_ccw) |
915 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
916 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
917 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
918 S_028814_POLY_MODE(polygon_dual_mode) |
919 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
920 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
921 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
922 return rstate;
923 }
924
925 static void *r600_create_sampler_state(struct pipe_context *ctx,
926 const struct pipe_sampler_state *state)
927 {
928 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
929 struct r600_pipe_state *rstate;
930 union util_color uc;
931 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
932
933 if (ss == NULL) {
934 return NULL;
935 }
936
937 ss->seamless_cube_map = state->seamless_cube_map;
938 rstate = &ss->rstate;
939 rstate->id = R600_PIPE_STATE_SAMPLER;
940 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
941 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
942 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
943 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
944 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
945 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
946 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
947 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
948 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
949 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
950 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
951 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
952 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
953 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
954 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), NULL, 0);
955 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), NULL, 0);
956 if (uc.ui) {
957 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
958 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
959 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
960 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
961 }
962 return rstate;
963 }
964
965 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
966 struct pipe_resource *texture,
967 const struct pipe_sampler_view *state)
968 {
969 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
970 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
971 struct r600_pipe_resource_state *rstate;
972 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
973 unsigned format, endian;
974 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
975 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
976 unsigned width, height, depth, offset_level, last_level;
977
978 if (view == NULL)
979 return NULL;
980 rstate = &view->state;
981
982 /* initialize base object */
983 view->base = *state;
984 view->base.texture = NULL;
985 pipe_reference(NULL, &texture->reference);
986 view->base.texture = texture;
987 view->base.reference.count = 1;
988 view->base.context = ctx;
989
990 swizzle[0] = state->swizzle_r;
991 swizzle[1] = state->swizzle_g;
992 swizzle[2] = state->swizzle_b;
993 swizzle[3] = state->swizzle_a;
994
995 format = r600_translate_texformat(ctx->screen, state->format,
996 swizzle,
997 &word4, &yuv_format);
998 if (format == ~0) {
999 format = 0;
1000 }
1001
1002 if (tmp->is_depth && !tmp->is_flushing_texture) {
1003 r600_init_flushed_depth_texture(ctx, texture);
1004 tmp = tmp->flushed_depth_texture;
1005 if (!tmp) {
1006 FREE(view);
1007 return NULL;
1008 }
1009 }
1010
1011 endian = r600_colorformat_endian_swap(format);
1012
1013 offset_level = state->u.tex.first_level;
1014 last_level = state->u.tex.last_level - offset_level;
1015 if (!rscreen->use_surface_alloc) {
1016 width = u_minify(texture->width0, offset_level);
1017 height = u_minify(texture->height0, offset_level);
1018 depth = u_minify(texture->depth0, offset_level);
1019
1020 pitch = align(tmp->pitch_in_blocks[offset_level] *
1021 util_format_get_blockwidth(state->format), 8);
1022 array_mode = tmp->array_mode[offset_level];
1023 tile_type = tmp->tile_type;
1024
1025 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1026 height = 1;
1027 depth = texture->array_size;
1028 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1029 depth = texture->array_size;
1030 }
1031
1032 rstate->bo[0] = &tmp->resource;
1033 rstate->bo[1] = &tmp->resource;
1034 rstate->bo_usage[0] = RADEON_USAGE_READ;
1035 rstate->bo_usage[1] = RADEON_USAGE_READ;
1036
1037 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1038 S_038000_TILE_MODE(array_mode) |
1039 S_038000_TILE_TYPE(tile_type) |
1040 S_038000_PITCH((pitch / 8) - 1) |
1041 S_038000_TEX_WIDTH(width - 1));
1042 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1043 S_038004_TEX_DEPTH(depth - 1) |
1044 S_038004_DATA_FORMAT(format));
1045 rstate->val[2] = tmp->offset[offset_level] >> 8;
1046 rstate->val[3] = tmp->offset[offset_level+1] >> 8;
1047 rstate->val[4] = (word4 |
1048 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1049 S_038010_REQUEST_SIZE(1) |
1050 S_038010_ENDIAN_SWAP(endian) |
1051 S_038010_BASE_LEVEL(0));
1052 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1053 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1054 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1055 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1056 S_038018_MAX_ANISO(4 /* max 16 samples */));
1057 } else {
1058 width = tmp->surface.level[offset_level].npix_x;
1059 height = tmp->surface.level[offset_level].npix_y;
1060 depth = tmp->surface.level[offset_level].npix_z;
1061 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1062 tile_type = tmp->tile_type;
1063
1064 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1065 height = 1;
1066 depth = texture->array_size;
1067 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1068 depth = texture->array_size;
1069 }
1070 switch (tmp->surface.level[offset_level].mode) {
1071 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1072 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1073 break;
1074 case RADEON_SURF_MODE_1D:
1075 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1076 break;
1077 case RADEON_SURF_MODE_2D:
1078 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1079 break;
1080 case RADEON_SURF_MODE_LINEAR:
1081 default:
1082 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1083 break;
1084 }
1085
1086 rstate->bo[0] = &tmp->resource;
1087 rstate->bo[1] = &tmp->resource;
1088 rstate->bo_usage[0] = RADEON_USAGE_READ;
1089 rstate->bo_usage[1] = RADEON_USAGE_READ;
1090
1091 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1092 S_038000_TILE_MODE(array_mode) |
1093 S_038000_TILE_TYPE(tile_type) |
1094 S_038000_PITCH((pitch / 8) - 1) |
1095 S_038000_TEX_WIDTH(width - 1));
1096 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1097 S_038004_TEX_DEPTH(depth - 1) |
1098 S_038004_DATA_FORMAT(format));
1099 rstate->val[2] = tmp->surface.level[offset_level].offset >> 8;
1100 if (offset_level >= tmp->surface.last_level) {
1101 rstate->val[3] = tmp->surface.level[offset_level].offset >> 8;
1102 } else {
1103 rstate->val[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1104 }
1105 rstate->val[4] = (word4 |
1106 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1107 S_038010_REQUEST_SIZE(1) |
1108 S_038010_ENDIAN_SWAP(endian) |
1109 S_038010_BASE_LEVEL(0));
1110 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1111 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1112 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1113 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1114 S_038018_MAX_ANISO(4 /* max 16 samples */));
1115 }
1116 return &view->base;
1117 }
1118
1119 static void r600_set_sampler_views(struct r600_context *rctx,
1120 struct r600_textures_info *dst,
1121 unsigned count,
1122 struct pipe_sampler_view **views,
1123 void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned))
1124 {
1125 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
1126 unsigned i;
1127
1128 if (count)
1129 r600_inval_texture_cache(rctx);
1130
1131 for (i = 0; i < count; i++) {
1132 if (rviews[i]) {
1133 if (((struct r600_resource_texture *)rviews[i]->base.texture)->is_depth)
1134 rctx->have_depth_texture = true;
1135
1136 /* Changing from array to non-arrays textures and vice versa requires updating TEX_ARRAY_OVERRIDE. */
1137 if ((rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1138 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i])
1139 dst->samplers_dirty = true;
1140
1141 set_resource(rctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS);
1142 } else {
1143 set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
1144 }
1145
1146 pipe_sampler_view_reference(
1147 (struct pipe_sampler_view **)&dst->views[i],
1148 views[i]);
1149 }
1150
1151 for (i = count; i < dst->n_views; i++) {
1152 if (dst->views[i]) {
1153 set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
1154 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL);
1155 }
1156 }
1157
1158 dst->n_views = count;
1159 }
1160
1161 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1162 struct pipe_sampler_view **views)
1163 {
1164 struct r600_context *rctx = (struct r600_context *)ctx;
1165 r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views,
1166 r600_context_pipe_state_set_vs_resource);
1167 }
1168
1169 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1170 struct pipe_sampler_view **views)
1171 {
1172 struct r600_context *rctx = (struct r600_context *)ctx;
1173 r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views,
1174 r600_context_pipe_state_set_ps_resource);
1175 }
1176
1177 static void r600_set_seamless_cubemap(struct r600_context *rctx, boolean enable)
1178 {
1179 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1180 if (rstate == NULL)
1181 return;
1182
1183 rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP;
1184 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1185 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)) |
1186 S_009508_DISABLE_CUBE_ANISO(1) |
1187 S_009508_SYNC_GRADIENT(1) |
1188 S_009508_SYNC_WALKER(1) |
1189 S_009508_SYNC_ALIGNER(1));
1190
1191 free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]);
1192 rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate;
1193 r600_context_pipe_state_set(rctx, rstate);
1194 }
1195
1196 static void r600_bind_samplers(struct r600_context *rctx,
1197 struct r600_textures_info *dst,
1198 unsigned count, void **states)
1199 {
1200 memcpy(dst->samplers, states, sizeof(void*) * count);
1201 dst->n_samplers = count;
1202 dst->samplers_dirty = true;
1203 }
1204
1205 static void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
1206 {
1207 struct r600_context *rctx = (struct r600_context *)ctx;
1208 r600_bind_samplers(rctx, &rctx->vs_samplers, count, states);
1209 }
1210
1211 static void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
1212 {
1213 struct r600_context *rctx = (struct r600_context *)ctx;
1214 r600_bind_samplers(rctx, &rctx->ps_samplers, count, states);
1215 }
1216
1217 static void r600_update_samplers(struct r600_context *rctx,
1218 struct r600_textures_info *tex,
1219 void (*set_sampler)(struct r600_context*, struct r600_pipe_state*, unsigned))
1220 {
1221 unsigned i;
1222
1223 if (tex->samplers_dirty) {
1224 int seamless = -1;
1225 for (i = 0; i < tex->n_samplers; i++) {
1226 if (!tex->samplers[i])
1227 continue;
1228
1229 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1230 * filtering between layers.
1231 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */
1232 if (tex->views[i]) {
1233 if (tex->views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1234 tex->views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1235 tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1236 tex->is_array_sampler[i] = true;
1237 } else {
1238 tex->samplers[i]->rstate.regs[0].value &= C_03C000_TEX_ARRAY_OVERRIDE;
1239 tex->is_array_sampler[i] = false;
1240 }
1241 }
1242
1243 set_sampler(rctx, &tex->samplers[i]->rstate, i);
1244
1245 if (tex->samplers[i])
1246 seamless = tex->samplers[i]->seamless_cube_map;
1247 }
1248
1249 if (seamless != -1)
1250 r600_set_seamless_cubemap(rctx, seamless);
1251
1252 tex->samplers_dirty = false;
1253 }
1254 }
1255
1256 void r600_update_sampler_states(struct r600_context *rctx)
1257 {
1258 r600_update_samplers(rctx, &rctx->vs_samplers,
1259 r600_context_pipe_state_set_vs_sampler);
1260 r600_update_samplers(rctx, &rctx->ps_samplers,
1261 r600_context_pipe_state_set_ps_sampler);
1262 }
1263
1264 static void r600_set_clip_state(struct pipe_context *ctx,
1265 const struct pipe_clip_state *state)
1266 {
1267 struct r600_context *rctx = (struct r600_context *)ctx;
1268 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1269 struct pipe_constant_buffer cb;
1270
1271 if (rstate == NULL)
1272 return;
1273
1274 rctx->clip = *state;
1275 rstate->id = R600_PIPE_STATE_CLIP;
1276 for (int i = 0; i < 6; i++) {
1277 r600_pipe_state_add_reg(rstate,
1278 R_028E20_PA_CL_UCP0_X + i * 16,
1279 fui(state->ucp[i][0]));
1280 r600_pipe_state_add_reg(rstate,
1281 R_028E24_PA_CL_UCP0_Y + i * 16,
1282 fui(state->ucp[i][1]) );
1283 r600_pipe_state_add_reg(rstate,
1284 R_028E28_PA_CL_UCP0_Z + i * 16,
1285 fui(state->ucp[i][2]));
1286 r600_pipe_state_add_reg(rstate,
1287 R_028E2C_PA_CL_UCP0_W + i * 16,
1288 fui(state->ucp[i][3]));
1289 }
1290
1291 free(rctx->states[R600_PIPE_STATE_CLIP]);
1292 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1293 r600_context_pipe_state_set(rctx, rstate);
1294
1295 cb.buffer = NULL;
1296 cb.user_buffer = state->ucp;
1297 cb.buffer_offset = 0;
1298 cb.buffer_size = 4*4*8;
1299 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1300 pipe_resource_reference(&cb.buffer, NULL);
1301 }
1302
1303 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1304 const struct pipe_poly_stipple *state)
1305 {
1306 }
1307
1308 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1309 {
1310 }
1311
1312 void r600_set_scissor_state(struct r600_context *rctx,
1313 const struct pipe_scissor_state *state)
1314 {
1315 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1316 uint32_t tl, br;
1317
1318 if (rstate == NULL)
1319 return;
1320
1321 rstate->id = R600_PIPE_STATE_SCISSOR;
1322 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1323 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1324 r600_pipe_state_add_reg(rstate,
1325 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1326 r600_pipe_state_add_reg(rstate,
1327 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1328
1329 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1330 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1331 r600_context_pipe_state_set(rctx, rstate);
1332 }
1333
1334 static void r600_pipe_set_scissor_state(struct pipe_context *ctx,
1335 const struct pipe_scissor_state *state)
1336 {
1337 struct r600_context *rctx = (struct r600_context *)ctx;
1338
1339 if (rctx->chip_class == R600) {
1340 rctx->scissor_state = *state;
1341
1342 if (!rctx->scissor_enable)
1343 return;
1344 }
1345
1346 r600_set_scissor_state(rctx, state);
1347 }
1348
1349 static void r600_set_viewport_state(struct pipe_context *ctx,
1350 const struct pipe_viewport_state *state)
1351 {
1352 struct r600_context *rctx = (struct r600_context *)ctx;
1353 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1354
1355 if (rstate == NULL)
1356 return;
1357
1358 rctx->viewport = *state;
1359 rstate->id = R600_PIPE_STATE_VIEWPORT;
1360 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1361 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1362 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1363 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1364 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1365 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1366
1367 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1368 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1369 r600_context_pipe_state_set(rctx, rstate);
1370 }
1371
1372 static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1373 const struct pipe_framebuffer_state *state, int cb)
1374 {
1375 struct r600_screen *rscreen = rctx->screen;
1376 struct r600_resource_texture *rtex;
1377 struct r600_surface *surf;
1378 unsigned level = state->cbufs[cb]->u.tex.level;
1379 unsigned pitch, slice;
1380 unsigned color_info;
1381 unsigned format, swap, ntype, endian;
1382 unsigned offset;
1383 const struct util_format_description *desc;
1384 int i;
1385 unsigned blend_bypass = 0, blend_clamp = 1;
1386
1387 surf = (struct r600_surface *)state->cbufs[cb];
1388 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1389
1390 if (rtex->is_depth)
1391 rctx->have_depth_fb = TRUE;
1392
1393 if (rtex->is_depth && !rtex->is_flushing_texture) {
1394 rtex = rtex->flushed_depth_texture;
1395 }
1396
1397 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1398 if (!rscreen->use_surface_alloc) {
1399 offset = r600_texture_get_offset(rtex,
1400 level, state->cbufs[cb]->u.tex.first_layer);
1401 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1402 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1403 if (slice) {
1404 slice = slice - 1;
1405 }
1406 color_info = S_0280A0_ARRAY_MODE(rtex->array_mode[level]);
1407 } else {
1408 offset = rtex->surface.level[level].offset;
1409 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1410 offset += rtex->surface.level[level].slice_size *
1411 state->cbufs[cb]->u.tex.first_layer;
1412 }
1413 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1414 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1415 if (slice) {
1416 slice = slice - 1;
1417 }
1418 color_info = 0;
1419 switch (rtex->surface.level[level].mode) {
1420 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1421 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1422 break;
1423 case RADEON_SURF_MODE_1D:
1424 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1425 break;
1426 case RADEON_SURF_MODE_2D:
1427 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1428 break;
1429 case RADEON_SURF_MODE_LINEAR:
1430 default:
1431 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1432 break;
1433 }
1434 }
1435 desc = util_format_description(surf->base.format);
1436
1437 for (i = 0; i < 4; i++) {
1438 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1439 break;
1440 }
1441 }
1442
1443 ntype = V_0280A0_NUMBER_UNORM;
1444 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1445 ntype = V_0280A0_NUMBER_SRGB;
1446 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1447 if (desc->channel[i].normalized)
1448 ntype = V_0280A0_NUMBER_SNORM;
1449 else if (desc->channel[i].pure_integer)
1450 ntype = V_0280A0_NUMBER_SINT;
1451 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1452 if (desc->channel[i].normalized)
1453 ntype = V_0280A0_NUMBER_UNORM;
1454 else if (desc->channel[i].pure_integer)
1455 ntype = V_0280A0_NUMBER_UINT;
1456 }
1457
1458 format = r600_translate_colorformat(surf->base.format);
1459 swap = r600_translate_colorswap(surf->base.format);
1460 if(rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1461 endian = ENDIAN_NONE;
1462 } else {
1463 endian = r600_colorformat_endian_swap(format);
1464 }
1465
1466 /* set blend bypass according to docs if SINT/UINT or
1467 8/24 COLOR variants */
1468 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1469 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1470 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1471 blend_clamp = 0;
1472 blend_bypass = 1;
1473 }
1474
1475 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT)
1476 rctx->sx_alpha_test_control |= S_028410_ALPHA_TEST_BYPASS(1);
1477 else
1478 rctx->sx_alpha_test_control &= C_028410_ALPHA_TEST_BYPASS;
1479
1480 color_info |= S_0280A0_FORMAT(format) |
1481 S_0280A0_COMP_SWAP(swap) |
1482 S_0280A0_BLEND_BYPASS(blend_bypass) |
1483 S_0280A0_BLEND_CLAMP(blend_clamp) |
1484 S_0280A0_NUMBER_TYPE(ntype) |
1485 S_0280A0_ENDIAN(endian);
1486
1487 /* EXPORT_NORM is an optimzation that can be enabled for better
1488 * performance in certain cases
1489 */
1490 if (rctx->chip_class == R600) {
1491 /* EXPORT_NORM can be enabled if:
1492 * - 11-bit or smaller UNORM/SNORM/SRGB
1493 * - BLEND_CLAMP is enabled
1494 * - BLEND_FLOAT32 is disabled
1495 */
1496 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1497 (desc->channel[i].size < 12 &&
1498 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1499 ntype != V_0280A0_NUMBER_UINT &&
1500 ntype != V_0280A0_NUMBER_SINT) &&
1501 G_0280A0_BLEND_CLAMP(color_info) &&
1502 !G_0280A0_BLEND_FLOAT32(color_info)) {
1503 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1504 } else {
1505 rctx->export_16bpc = false;
1506 }
1507 } else {
1508 /* EXPORT_NORM can be enabled if:
1509 * - 11-bit or smaller UNORM/SNORM/SRGB
1510 * - 16-bit or smaller FLOAT
1511 */
1512 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1513 ((desc->channel[i].size < 12 &&
1514 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1515 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1516 (desc->channel[i].size < 17 &&
1517 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1518 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1519 } else {
1520 rctx->export_16bpc = false;
1521 }
1522 }
1523
1524 /* for possible dual-src MRT write color info 1 */
1525 if (cb == 0 && rctx->framebuffer.nr_cbufs == 1) {
1526 r600_pipe_state_add_reg_bo(rstate,
1527 R_0280A0_CB_COLOR0_INFO + 1 * 4,
1528 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1529 }
1530
1531 r600_pipe_state_add_reg_bo(rstate,
1532 R_028040_CB_COLOR0_BASE + cb * 4,
1533 offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
1534 r600_pipe_state_add_reg_bo(rstate,
1535 R_0280A0_CB_COLOR0_INFO + cb * 4,
1536 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1537 r600_pipe_state_add_reg(rstate,
1538 R_028060_CB_COLOR0_SIZE + cb * 4,
1539 S_028060_PITCH_TILE_MAX(pitch) |
1540 S_028060_SLICE_TILE_MAX(slice));
1541 if (!rscreen->use_surface_alloc) {
1542 r600_pipe_state_add_reg(rstate,
1543 R_028080_CB_COLOR0_VIEW + cb * 4,
1544 0x00000000);
1545 } else {
1546 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1547 r600_pipe_state_add_reg(rstate,
1548 R_028080_CB_COLOR0_VIEW + cb * 4,
1549 0x00000000);
1550 } else {
1551 r600_pipe_state_add_reg(rstate,
1552 R_028080_CB_COLOR0_VIEW + cb * 4,
1553 S_028080_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1554 S_028080_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1555 }
1556 }
1557 r600_pipe_state_add_reg_bo(rstate,
1558 R_0280E0_CB_COLOR0_FRAG + cb * 4,
1559 0, &rtex->resource, RADEON_USAGE_READWRITE);
1560 r600_pipe_state_add_reg_bo(rstate,
1561 R_0280C0_CB_COLOR0_TILE + cb * 4,
1562 0, &rtex->resource, RADEON_USAGE_READWRITE);
1563 }
1564
1565 static void r600_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1566 const struct pipe_framebuffer_state *state)
1567 {
1568 struct r600_screen *rscreen = rctx->screen;
1569 struct r600_resource_texture *rtex;
1570 struct r600_surface *surf;
1571 unsigned level, pitch, slice, format, offset, array_mode;
1572
1573 if (state->zsbuf == NULL)
1574 return;
1575
1576 level = state->zsbuf->u.tex.level;
1577
1578 surf = (struct r600_surface *)state->zsbuf;
1579 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1580
1581 if (!rscreen->use_surface_alloc) {
1582 /* XXX remove this once tiling is properly supported */
1583 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1584 V_0280A0_ARRAY_1D_TILED_THIN1;
1585
1586 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1587 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1588 level, state->zsbuf->u.tex.first_layer);
1589 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1590 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1591 if (slice) {
1592 slice = slice - 1;
1593 }
1594 } else {
1595 offset = rtex->surface.level[level].offset;
1596 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1597 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1598 if (slice) {
1599 slice = slice - 1;
1600 }
1601 switch (rtex->surface.level[level].mode) {
1602 case RADEON_SURF_MODE_2D:
1603 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1604 break;
1605 case RADEON_SURF_MODE_1D:
1606 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1607 case RADEON_SURF_MODE_LINEAR:
1608 default:
1609 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1610 break;
1611 }
1612 }
1613
1614 format = r600_translate_dbformat(state->zsbuf->format);
1615
1616 r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE,
1617 offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
1618 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1619 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice));
1620 if (!rscreen->use_surface_alloc) {
1621 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000);
1622 } else {
1623 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW,
1624 S_028004_SLICE_START(state->zsbuf->u.tex.first_layer) |
1625 S_028004_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1626 }
1627 r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO,
1628 S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format),
1629 &rtex->resource, RADEON_USAGE_READWRITE);
1630 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1631 (surf->aligned_height / 8) - 1);
1632 }
1633
1634 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1635 const struct pipe_framebuffer_state *state)
1636 {
1637 struct r600_context *rctx = (struct r600_context *)ctx;
1638 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1639 uint32_t tl, br, shader_control;
1640
1641 if (rstate == NULL)
1642 return;
1643
1644 r600_flush_framebuffer(rctx, false);
1645
1646 /* unreference old buffer and reference new one */
1647 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1648
1649 util_copy_framebuffer_state(&rctx->framebuffer, state);
1650
1651 /* build states */
1652 rctx->have_depth_fb = 0;
1653 rctx->export_16bpc = true;
1654 rctx->nr_cbufs = state->nr_cbufs;
1655
1656 for (int i = 0; i < state->nr_cbufs; i++) {
1657 r600_cb(rctx, rstate, state, i);
1658 }
1659 if (state->zsbuf) {
1660 r600_db(rctx, rstate, state);
1661 }
1662
1663 shader_control = 0;
1664 rctx->fb_cb_shader_mask = 0;
1665 for (int i = 0; i < state->nr_cbufs; i++) {
1666 shader_control |= 1 << i;
1667 rctx->fb_cb_shader_mask |= 0xf << (i * 4);
1668 }
1669 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1670 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1671
1672 r600_pipe_state_add_reg(rstate,
1673 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1674 r600_pipe_state_add_reg(rstate,
1675 R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1676
1677 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1678 shader_control);
1679
1680 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1681 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1682 r600_context_pipe_state_set(rctx, rstate);
1683
1684 if (state->zsbuf) {
1685 r600_polygon_offset_update(rctx);
1686 }
1687 }
1688
1689 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1690 {
1691 struct radeon_winsys_cs *cs = rctx->cs;
1692 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1693 unsigned db_render_control = 0;
1694 unsigned db_render_override =
1695 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1696 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1697 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1698
1699 if (a->occlusion_query_enabled) {
1700 if (rctx->chip_class >= R700) {
1701 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1702 }
1703 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1704 }
1705 if (a->flush_depthstencil_enabled) {
1706 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(1) |
1707 S_028D0C_STENCIL_COPY_ENABLE(1) |
1708 S_028D0C_COPY_CENTROID(1);
1709 }
1710
1711 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1712 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1713 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1714 }
1715
1716 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1717 {
1718 struct radeon_winsys_cs *cs = rctx->cs;
1719 struct pipe_vertex_buffer *vb = rctx->vertex_buffer;
1720 unsigned count = rctx->nr_vertex_buffers;
1721 unsigned i, offset;
1722
1723 for (i = 0; i < count; i++) {
1724 struct r600_resource *rbuffer = (struct r600_resource*)vb[i].buffer;
1725
1726 if (!rbuffer) {
1727 continue;
1728 }
1729
1730 offset = vb[i].buffer_offset;
1731
1732 /* fetch resources start at index 320 */
1733 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1734 r600_write_value(cs, (320 + i) * 7);
1735 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1736 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1737 r600_write_value(cs, /* RESOURCEi_WORD2 */
1738 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1739 S_038008_STRIDE(vb[i].stride));
1740 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1741 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1742 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1743 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1744
1745 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1746 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1747 }
1748 }
1749
1750 static void r600_emit_constant_buffers(struct r600_context *rctx,
1751 struct r600_constbuf_state *state,
1752 unsigned buffer_id_base,
1753 unsigned reg_alu_constbuf_size,
1754 unsigned reg_alu_const_cache)
1755 {
1756 struct radeon_winsys_cs *cs = rctx->cs;
1757 uint32_t dirty_mask = state->dirty_mask;
1758
1759 while (dirty_mask) {
1760 struct pipe_constant_buffer *cb;
1761 struct r600_resource *rbuffer;
1762 unsigned offset;
1763 unsigned buffer_index = ffs(dirty_mask) - 1;
1764
1765 cb = &state->cb[buffer_index];
1766 rbuffer = (struct r600_resource*)cb->buffer;
1767 assert(rbuffer);
1768
1769 offset = cb->buffer_offset;
1770
1771 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1772 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1773 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1774
1775 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1776 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1777
1778 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1779 r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1780 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1781 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1782 r600_write_value(cs, /* RESOURCEi_WORD2 */
1783 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1784 S_038008_STRIDE(16));
1785 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1786 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1787 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1788 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1789
1790 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1791 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1792
1793 dirty_mask &= ~(1 << buffer_index);
1794 }
1795 state->dirty_mask = 0;
1796 }
1797
1798 static void r600_emit_vs_constant_buffer(struct r600_context *rctx, struct r600_atom *atom)
1799 {
1800 r600_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 160,
1801 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1802 R_028980_ALU_CONST_CACHE_VS_0);
1803 }
1804
1805 static void r600_emit_ps_constant_buffer(struct r600_context *rctx, struct r600_atom *atom)
1806 {
1807 r600_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1808 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1809 R_028940_ALU_CONST_CACHE_PS_0);
1810 }
1811
1812 void r600_init_state_functions(struct r600_context *rctx)
1813 {
1814 r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0);
1815 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1816 r600_init_atom(&rctx->vertex_buffer_state, r600_emit_vertex_buffers, 0, 0);
1817 r600_init_atom(&rctx->vs_constbuf_state.atom, r600_emit_vs_constant_buffer, 0, 0);
1818 r600_init_atom(&rctx->ps_constbuf_state.atom, r600_emit_ps_constant_buffer, 0, 0);
1819
1820 rctx->context.create_blend_state = r600_create_blend_state;
1821 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1822 rctx->context.create_fs_state = r600_create_shader_state_ps;
1823 rctx->context.create_rasterizer_state = r600_create_rs_state;
1824 rctx->context.create_sampler_state = r600_create_sampler_state;
1825 rctx->context.create_sampler_view = r600_create_sampler_view;
1826 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1827 rctx->context.create_vs_state = r600_create_shader_state_vs;
1828 rctx->context.bind_blend_state = r600_bind_blend_state;
1829 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1830 rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1831 rctx->context.bind_fs_state = r600_bind_ps_shader;
1832 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1833 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1834 rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1835 rctx->context.bind_vs_state = r600_bind_vs_shader;
1836 rctx->context.delete_blend_state = r600_delete_state;
1837 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1838 rctx->context.delete_fs_state = r600_delete_ps_shader;
1839 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1840 rctx->context.delete_sampler_state = r600_delete_state;
1841 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1842 rctx->context.delete_vs_state = r600_delete_vs_shader;
1843 rctx->context.set_blend_color = r600_set_blend_color;
1844 rctx->context.set_clip_state = r600_set_clip_state;
1845 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1846 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1847 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1848 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1849 rctx->context.set_sample_mask = r600_set_sample_mask;
1850 rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
1851 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1852 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1853 rctx->context.set_index_buffer = r600_set_index_buffer;
1854 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1855 rctx->context.set_viewport_state = r600_set_viewport_state;
1856 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1857 rctx->context.texture_barrier = r600_texture_barrier;
1858 rctx->context.create_stream_output_target = r600_create_so_target;
1859 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1860 rctx->context.set_stream_output_targets = r600_set_so_targets;
1861 }
1862
1863 /* Adjust GPR allocation on R6xx/R7xx */
1864 void r600_adjust_gprs(struct r600_context *rctx)
1865 {
1866 struct r600_pipe_state rstate;
1867 unsigned num_ps_gprs = rctx->default_ps_gprs;
1868 unsigned num_vs_gprs = rctx->default_vs_gprs;
1869 unsigned tmp;
1870 int diff;
1871
1872 /* XXX: Following call moved from r600_bind_[ps|vs]_shader,
1873 * it seems eg+ doesn't need it, r6xx/7xx probably need it only for
1874 * adjusting the GPR allocation?
1875 * Do we need this if we aren't really changing config below? */
1876 r600_inval_shader_cache(rctx);
1877
1878 if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs)
1879 {
1880 diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
1881 num_vs_gprs -= diff;
1882 num_ps_gprs += diff;
1883 }
1884
1885 if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
1886 {
1887 diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
1888 num_ps_gprs -= diff;
1889 num_vs_gprs += diff;
1890 }
1891
1892 tmp = 0;
1893 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1894 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1895 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
1896 rstate.nregs = 0;
1897 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
1898
1899 r600_context_pipe_state_set(rctx, &rstate);
1900 }
1901
1902 void r600_init_atom_start_cs(struct r600_context *rctx)
1903 {
1904 int ps_prio;
1905 int vs_prio;
1906 int gs_prio;
1907 int es_prio;
1908 int num_ps_gprs;
1909 int num_vs_gprs;
1910 int num_gs_gprs;
1911 int num_es_gprs;
1912 int num_temp_gprs;
1913 int num_ps_threads;
1914 int num_vs_threads;
1915 int num_gs_threads;
1916 int num_es_threads;
1917 int num_ps_stack_entries;
1918 int num_vs_stack_entries;
1919 int num_gs_stack_entries;
1920 int num_es_stack_entries;
1921 enum radeon_family family;
1922 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1923 uint32_t tmp;
1924 unsigned i;
1925
1926 r600_init_command_buffer(cb, 256, EMIT_EARLY);
1927
1928 /* R6xx requires this packet at the start of each command buffer */
1929 if (rctx->chip_class == R600) {
1930 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
1931 r600_store_value(cb, 0);
1932 }
1933 /* All asics require this one */
1934 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1935 r600_store_value(cb, 0x80000000);
1936 r600_store_value(cb, 0x80000000);
1937
1938 family = rctx->family;
1939 ps_prio = 0;
1940 vs_prio = 1;
1941 gs_prio = 2;
1942 es_prio = 3;
1943 switch (family) {
1944 case CHIP_R600:
1945 num_ps_gprs = 192;
1946 num_vs_gprs = 56;
1947 num_temp_gprs = 4;
1948 num_gs_gprs = 0;
1949 num_es_gprs = 0;
1950 num_ps_threads = 136;
1951 num_vs_threads = 48;
1952 num_gs_threads = 4;
1953 num_es_threads = 4;
1954 num_ps_stack_entries = 128;
1955 num_vs_stack_entries = 128;
1956 num_gs_stack_entries = 0;
1957 num_es_stack_entries = 0;
1958 break;
1959 case CHIP_RV630:
1960 case CHIP_RV635:
1961 num_ps_gprs = 84;
1962 num_vs_gprs = 36;
1963 num_temp_gprs = 4;
1964 num_gs_gprs = 0;
1965 num_es_gprs = 0;
1966 num_ps_threads = 144;
1967 num_vs_threads = 40;
1968 num_gs_threads = 4;
1969 num_es_threads = 4;
1970 num_ps_stack_entries = 40;
1971 num_vs_stack_entries = 40;
1972 num_gs_stack_entries = 32;
1973 num_es_stack_entries = 16;
1974 break;
1975 case CHIP_RV610:
1976 case CHIP_RV620:
1977 case CHIP_RS780:
1978 case CHIP_RS880:
1979 default:
1980 num_ps_gprs = 84;
1981 num_vs_gprs = 36;
1982 num_temp_gprs = 4;
1983 num_gs_gprs = 0;
1984 num_es_gprs = 0;
1985 num_ps_threads = 136;
1986 num_vs_threads = 48;
1987 num_gs_threads = 4;
1988 num_es_threads = 4;
1989 num_ps_stack_entries = 40;
1990 num_vs_stack_entries = 40;
1991 num_gs_stack_entries = 32;
1992 num_es_stack_entries = 16;
1993 break;
1994 case CHIP_RV670:
1995 num_ps_gprs = 144;
1996 num_vs_gprs = 40;
1997 num_temp_gprs = 4;
1998 num_gs_gprs = 0;
1999 num_es_gprs = 0;
2000 num_ps_threads = 136;
2001 num_vs_threads = 48;
2002 num_gs_threads = 4;
2003 num_es_threads = 4;
2004 num_ps_stack_entries = 40;
2005 num_vs_stack_entries = 40;
2006 num_gs_stack_entries = 32;
2007 num_es_stack_entries = 16;
2008 break;
2009 case CHIP_RV770:
2010 num_ps_gprs = 192;
2011 num_vs_gprs = 56;
2012 num_temp_gprs = 4;
2013 num_gs_gprs = 0;
2014 num_es_gprs = 0;
2015 num_ps_threads = 188;
2016 num_vs_threads = 60;
2017 num_gs_threads = 0;
2018 num_es_threads = 0;
2019 num_ps_stack_entries = 256;
2020 num_vs_stack_entries = 256;
2021 num_gs_stack_entries = 0;
2022 num_es_stack_entries = 0;
2023 break;
2024 case CHIP_RV730:
2025 case CHIP_RV740:
2026 num_ps_gprs = 84;
2027 num_vs_gprs = 36;
2028 num_temp_gprs = 4;
2029 num_gs_gprs = 0;
2030 num_es_gprs = 0;
2031 num_ps_threads = 188;
2032 num_vs_threads = 60;
2033 num_gs_threads = 0;
2034 num_es_threads = 0;
2035 num_ps_stack_entries = 128;
2036 num_vs_stack_entries = 128;
2037 num_gs_stack_entries = 0;
2038 num_es_stack_entries = 0;
2039 break;
2040 case CHIP_RV710:
2041 num_ps_gprs = 192;
2042 num_vs_gprs = 56;
2043 num_temp_gprs = 4;
2044 num_gs_gprs = 0;
2045 num_es_gprs = 0;
2046 num_ps_threads = 144;
2047 num_vs_threads = 48;
2048 num_gs_threads = 0;
2049 num_es_threads = 0;
2050 num_ps_stack_entries = 128;
2051 num_vs_stack_entries = 128;
2052 num_gs_stack_entries = 0;
2053 num_es_stack_entries = 0;
2054 break;
2055 }
2056
2057 rctx->default_ps_gprs = num_ps_gprs;
2058 rctx->default_vs_gprs = num_vs_gprs;
2059 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2060
2061 /* SQ_CONFIG */
2062 tmp = 0;
2063 switch (family) {
2064 case CHIP_RV610:
2065 case CHIP_RV620:
2066 case CHIP_RS780:
2067 case CHIP_RS880:
2068 case CHIP_RV710:
2069 break;
2070 default:
2071 tmp |= S_008C00_VC_ENABLE(1);
2072 break;
2073 }
2074 tmp |= S_008C00_DX9_CONSTS(0);
2075 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2076 tmp |= S_008C00_PS_PRIO(ps_prio);
2077 tmp |= S_008C00_VS_PRIO(vs_prio);
2078 tmp |= S_008C00_GS_PRIO(gs_prio);
2079 tmp |= S_008C00_ES_PRIO(es_prio);
2080 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2081
2082 /* SQ_GPR_RESOURCE_MGMT_2 */
2083 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2084 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2085 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2086 r600_store_value(cb, tmp);
2087
2088 /* SQ_THREAD_RESOURCE_MGMT */
2089 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2090 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2091 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2092 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2093 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2094
2095 /* SQ_STACK_RESOURCE_MGMT_1 */
2096 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2097 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2098 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2099
2100 /* SQ_STACK_RESOURCE_MGMT_2 */
2101 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2102 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2103 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2104
2105 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2106
2107 if (rctx->chip_class >= R700) {
2108 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2109 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2110 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2111 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2112 } else {
2113 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2114 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2115 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2116 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2117 }
2118 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2119 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2120 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2121 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2122 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2123 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2124 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2125 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2126 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2127 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2128
2129 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2130 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2131 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2132 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2133 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2134 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2135 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2136 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2137 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2138 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2139 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2140 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2141 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2142 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2143
2144 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2145 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2146 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2147
2148 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2149 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2150 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2151 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2152
2153 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2154
2155 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2156 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2157 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2158
2159 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2160
2161 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2162 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2163 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2164
2165 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2166 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2167 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2168 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2169
2170 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2171 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2172 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2173
2174 r600_store_context_reg(cb, R_028D44_DB_ALPHA_TO_MASK, 0xAA00);
2175
2176 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2177 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2178
2179 r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2180 r600_store_value(cb, 0x400); /* R_028C00_PA_SC_LINE_CNTL */
2181 r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2182
2183 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 6);
2184 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2185 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2186 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2187 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2188 r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
2189 r600_store_value(cb, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX */
2190
2191 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2192 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2193 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2194
2195 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2196
2197 r600_store_context_reg_seq(cb, R_028100_CB_COLOR0_MASK, 8);
2198 for (i = 0; i < 8; i++) {
2199 r600_store_value(cb, 0);
2200 }
2201
2202 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2203 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2204
2205 if (rctx->chip_class >= R700) {
2206 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2207 }
2208
2209 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2210 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2211 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2212 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2213 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2214
2215 r600_store_context_reg(cb, R_028C48_PA_SC_AA_MASK, 0xFFFFFFFF);
2216
2217 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2218 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2219 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2220
2221 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2222 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2223 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2224
2225 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2226 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2227 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2228
2229 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2230 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2231
2232 if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2233 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2234 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2235
2236 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2237 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2238 }
2239
2240 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2241 {
2242 struct r600_context *rctx = (struct r600_context *)ctx;
2243 struct r600_pipe_state *rstate = &shader->rstate;
2244 struct r600_shader *rshader = &shader->shader;
2245 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2246 int pos_index = -1, face_index = -1;
2247 unsigned tmp, sid, ufi = 0;
2248 int need_linear = 0;
2249 unsigned z_export = 0, stencil_export = 0;
2250
2251 rstate->nregs = 0;
2252
2253 for (i = 0; i < rshader->ninput; i++) {
2254 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2255 pos_index = i;
2256 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2257 face_index = i;
2258
2259 sid = rshader->input[i].spi_sid;
2260
2261 tmp = S_028644_SEMANTIC(sid);
2262
2263 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2264 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2265 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2266 rctx->rasterizer && rctx->rasterizer->flatshade))
2267 tmp |= S_028644_FLAT_SHADE(1);
2268
2269 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2270 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2271 tmp |= S_028644_PT_SPRITE_TEX(1);
2272 }
2273
2274 if (rshader->input[i].centroid)
2275 tmp |= S_028644_SEL_CENTROID(1);
2276
2277 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2278 need_linear = 1;
2279 tmp |= S_028644_SEL_LINEAR(1);
2280 }
2281
2282 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2283 tmp);
2284 }
2285
2286 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2287 for (i = 0; i < rshader->noutput; i++) {
2288 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2289 z_export = 1;
2290 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2291 stencil_export = 1;
2292 }
2293 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2294 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2295 if (rshader->uses_kill)
2296 db_shader_control |= S_02880C_KILL_ENABLE(1);
2297
2298 exports_ps = 0;
2299 for (i = 0; i < rshader->noutput; i++) {
2300 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2301 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2302 exports_ps |= 1;
2303 }
2304 }
2305 num_cout = rshader->nr_ps_color_exports;
2306 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2307 if (!exports_ps) {
2308 /* always at least export 1 component per pixel */
2309 exports_ps = 2;
2310 }
2311
2312 shader->ps_cb_shader_mask = (1ULL << ((unsigned)num_cout * 4)) - 1;
2313
2314 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2315 S_0286CC_PERSP_GRADIENT_ENA(1)|
2316 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2317 spi_input_z = 0;
2318 if (pos_index != -1) {
2319 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2320 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2321 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2322 S_0286CC_BARYC_SAMPLE_CNTL(1));
2323 spi_input_z |= 1;
2324 }
2325
2326 spi_ps_in_control_1 = 0;
2327 if (face_index != -1) {
2328 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2329 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2330 }
2331
2332 /* HW bug in original R600 */
2333 if (rctx->family == CHIP_R600)
2334 ufi = 1;
2335
2336 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2337 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2338 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2339 r600_pipe_state_add_reg_bo(rstate,
2340 R_028840_SQ_PGM_START_PS,
2341 0, shader->bo, RADEON_USAGE_READ);
2342 r600_pipe_state_add_reg(rstate,
2343 R_028850_SQ_PGM_RESOURCES_PS,
2344 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2345 S_028850_STACK_SIZE(rshader->bc.nstack) |
2346 S_028850_UNCACHED_FIRST_INST(ufi));
2347 r600_pipe_state_add_reg(rstate,
2348 R_028854_SQ_PGM_EXPORTS_PS,
2349 exports_ps);
2350 /* only set some bits here, the other bits are set in the dsa state */
2351 shader->db_shader_control = db_shader_control;
2352 shader->ps_depth_export = z_export | stencil_export;
2353
2354 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2355 if (rctx->rasterizer)
2356 shader->flatshade = rctx->rasterizer->flatshade;
2357 }
2358
2359 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2360 {
2361 struct r600_context *rctx = (struct r600_context *)ctx;
2362 struct r600_pipe_state *rstate = &shader->rstate;
2363 struct r600_shader *rshader = &shader->shader;
2364 unsigned spi_vs_out_id[10] = {};
2365 unsigned i, tmp, nparams = 0;
2366
2367 /* clear previous register */
2368 rstate->nregs = 0;
2369
2370 for (i = 0; i < rshader->noutput; i++) {
2371 if (rshader->output[i].spi_sid) {
2372 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2373 spi_vs_out_id[nparams / 4] |= tmp;
2374 nparams++;
2375 }
2376 }
2377
2378 for (i = 0; i < 10; i++) {
2379 r600_pipe_state_add_reg(rstate,
2380 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2381 spi_vs_out_id[i]);
2382 }
2383
2384 /* Certain attributes (position, psize, etc.) don't count as params.
2385 * VS is required to export at least one param and r600_shader_from_tgsi()
2386 * takes care of adding a dummy export.
2387 */
2388 if (nparams < 1)
2389 nparams = 1;
2390
2391 r600_pipe_state_add_reg(rstate,
2392 R_0286C4_SPI_VS_OUT_CONFIG,
2393 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2394 r600_pipe_state_add_reg(rstate,
2395 R_028868_SQ_PGM_RESOURCES_VS,
2396 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2397 S_028868_STACK_SIZE(rshader->bc.nstack));
2398 r600_pipe_state_add_reg_bo(rstate,
2399 R_028858_SQ_PGM_START_VS,
2400 0, shader->bo, RADEON_USAGE_READ);
2401
2402 shader->pa_cl_vs_out_cntl =
2403 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2404 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2405 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2406 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2407 }
2408
2409 void r600_fetch_shader(struct pipe_context *ctx,
2410 struct r600_vertex_element *ve)
2411 {
2412 struct r600_pipe_state *rstate;
2413 struct r600_context *rctx = (struct r600_context *)ctx;
2414
2415 rstate = &ve->rstate;
2416 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2417 rstate->nregs = 0;
2418 r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS,
2419 0,
2420 ve->fetch_shader, RADEON_USAGE_READ);
2421 }
2422
2423 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2424 {
2425 struct pipe_depth_stencil_alpha_state dsa;
2426 struct r600_pipe_state *rstate;
2427 struct r600_pipe_dsa *dsa_state;
2428 boolean quirk = false;
2429
2430 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2431 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2432 quirk = true;
2433
2434 memset(&dsa, 0, sizeof(dsa));
2435
2436 if (quirk) {
2437 dsa.depth.enabled = 1;
2438 dsa.depth.func = PIPE_FUNC_LEQUAL;
2439 dsa.stencil[0].enabled = 1;
2440 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2441 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2442 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2443 dsa.stencil[0].writemask = 0xff;
2444 }
2445
2446 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2447 dsa_state = (struct r600_pipe_dsa*)rstate;
2448 dsa_state->is_flush = true;
2449 return rstate;
2450 }
2451
2452 void r600_update_dual_export_state(struct r600_context * rctx)
2453 {
2454 unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2455 !rctx->ps_shader->current->ps_depth_export;
2456 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2457 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2458
2459 if (db_shader_control != rctx->db_shader_control) {
2460 struct r600_pipe_state rstate;
2461
2462 rctx->db_shader_control = db_shader_control;
2463 rstate.nregs = 0;
2464 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2465 r600_context_pipe_state_set(rctx, &rstate);
2466 }
2467 }