2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * - fix mask for depth control & cull for query
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_framebuffer.h>
40 #include "util/u_transfer.h"
41 #include <pipebuffer/pb_buffer.h>
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_state_inlines.h"
49 void r600_polygon_offset_update(struct r600_pipe_context
*rctx
)
51 struct r600_pipe_state state
;
53 state
.id
= R600_PIPE_STATE_POLYGON_OFFSET
;
55 if (rctx
->rasterizer
&& rctx
->framebuffer
.zsbuf
) {
56 float offset_units
= rctx
->rasterizer
->offset_units
;
57 unsigned offset_db_fmt_cntl
= 0, depth
;
59 switch (rctx
->framebuffer
.zsbuf
->texture
->format
) {
60 case PIPE_FORMAT_Z24X8_UNORM
:
61 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
65 case PIPE_FORMAT_Z32_FLOAT
:
68 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
70 case PIPE_FORMAT_Z16_UNORM
:
77 /* FIXME some of those reg can be computed with cso */
78 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
79 r600_pipe_state_add_reg(&state
,
80 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE
,
81 fui(rctx
->rasterizer
->offset_scale
), 0xFFFFFFFF, NULL
);
82 r600_pipe_state_add_reg(&state
,
83 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
84 fui(offset_units
), 0xFFFFFFFF, NULL
);
85 r600_pipe_state_add_reg(&state
,
86 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE
,
87 fui(rctx
->rasterizer
->offset_scale
), 0xFFFFFFFF, NULL
);
88 r600_pipe_state_add_reg(&state
,
89 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
90 fui(offset_units
), 0xFFFFFFFF, NULL
);
91 r600_pipe_state_add_reg(&state
,
92 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
93 offset_db_fmt_cntl
, 0xFFFFFFFF, NULL
);
94 r600_context_pipe_state_set(&rctx
->ctx
, &state
);
98 static void r600_set_blend_color(struct pipe_context
*ctx
,
99 const struct pipe_blend_color
*state
)
101 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
102 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
107 rstate
->id
= R600_PIPE_STATE_BLEND_COLOR
;
108 r600_pipe_state_add_reg(rstate
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]), 0xFFFFFFFF, NULL
);
109 r600_pipe_state_add_reg(rstate
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]), 0xFFFFFFFF, NULL
);
110 r600_pipe_state_add_reg(rstate
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]), 0xFFFFFFFF, NULL
);
111 r600_pipe_state_add_reg(rstate
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]), 0xFFFFFFFF, NULL
);
112 free(rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
]);
113 rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
] = rstate
;
114 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
117 static void *r600_create_blend_state(struct pipe_context
*ctx
,
118 const struct pipe_blend_state
*state
)
120 struct r600_pipe_blend
*blend
= CALLOC_STRUCT(r600_pipe_blend
);
121 struct r600_pipe_state
*rstate
;
122 u32 color_control
, target_mask
;
127 rstate
= &blend
->rstate
;
129 rstate
->id
= R600_PIPE_STATE_BLEND
;
132 color_control
= S_028808_PER_MRT_BLEND(1);
133 if (state
->logicop_enable
) {
134 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
136 color_control
|= (0xcc << 16);
138 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
139 if (state
->independent_blend_enable
) {
140 for (int i
= 0; i
< 8; i
++) {
141 if (state
->rt
[i
].blend_enable
) {
142 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
144 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
147 for (int i
= 0; i
< 8; i
++) {
148 if (state
->rt
[0].blend_enable
) {
149 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
151 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
154 blend
->cb_target_mask
= target_mask
;
155 r600_pipe_state_add_reg(rstate
, R_028808_CB_COLOR_CONTROL
,
156 color_control
, 0xFFFFFFFF, NULL
);
158 for (int i
= 0; i
< 8; i
++) {
159 unsigned eqRGB
= state
->rt
[i
].rgb_func
;
160 unsigned srcRGB
= state
->rt
[i
].rgb_src_factor
;
161 unsigned dstRGB
= state
->rt
[i
].rgb_dst_factor
;
163 unsigned eqA
= state
->rt
[i
].alpha_func
;
164 unsigned srcA
= state
->rt
[i
].alpha_src_factor
;
165 unsigned dstA
= state
->rt
[i
].alpha_dst_factor
;
168 if (!state
->rt
[i
].blend_enable
)
171 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
172 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
173 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
175 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
176 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
177 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
178 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
179 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
182 r600_pipe_state_add_reg(rstate
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, bc
, 0xFFFFFFFF, NULL
);
184 r600_pipe_state_add_reg(rstate
, R_028804_CB_BLEND_CONTROL
, bc
, 0xFFFFFFFF, NULL
);
190 static void *r600_create_dsa_state(struct pipe_context
*ctx
,
191 const struct pipe_depth_stencil_alpha_state
*state
)
193 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
194 unsigned db_depth_control
, alpha_test_control
, alpha_ref
, db_shader_control
;
195 unsigned stencil_ref_mask
, stencil_ref_mask_bf
, db_render_override
, db_render_control
;
197 if (rstate
== NULL
) {
201 rstate
->id
= R600_PIPE_STATE_DSA
;
202 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
203 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
204 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
205 * be set if shader use texkill instruction
207 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
208 stencil_ref_mask
= 0;
209 stencil_ref_mask_bf
= 0;
210 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
211 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
212 S_028800_ZFUNC(state
->depth
.func
);
215 if (state
->stencil
[0].enabled
) {
216 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
217 db_depth_control
|= S_028800_STENCILFUNC(r600_translate_ds_func(state
->stencil
[0].func
));
218 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
219 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
220 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
223 stencil_ref_mask
= S_028430_STENCILMASK(state
->stencil
[0].valuemask
) |
224 S_028430_STENCILWRITEMASK(state
->stencil
[0].writemask
);
225 if (state
->stencil
[1].enabled
) {
226 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
227 db_depth_control
|= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state
->stencil
[1].func
));
228 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
229 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
230 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
231 stencil_ref_mask_bf
= S_028434_STENCILMASK_BF(state
->stencil
[1].valuemask
) |
232 S_028434_STENCILWRITEMASK_BF(state
->stencil
[1].writemask
);
237 alpha_test_control
= 0;
239 if (state
->alpha
.enabled
) {
240 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
241 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
242 alpha_ref
= fui(state
->alpha
.ref_value
);
246 db_render_control
= 0;
247 db_render_override
= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
) |
248 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE
) |
249 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE
);
250 /* TODO db_render_override depends on query */
251 r600_pipe_state_add_reg(rstate
, R_028028_DB_STENCIL_CLEAR
, 0x00000000, 0xFFFFFFFF, NULL
);
252 r600_pipe_state_add_reg(rstate
, R_02802C_DB_DEPTH_CLEAR
, 0x3F800000, 0xFFFFFFFF, NULL
);
253 r600_pipe_state_add_reg(rstate
, R_028410_SX_ALPHA_TEST_CONTROL
, alpha_test_control
, 0xFFFFFFFF, NULL
);
254 r600_pipe_state_add_reg(rstate
,
255 R_028430_DB_STENCILREFMASK
, stencil_ref_mask
,
256 0xFFFFFFFF & C_028430_STENCILREF
, NULL
);
257 r600_pipe_state_add_reg(rstate
,
258 R_028434_DB_STENCILREFMASK_BF
, stencil_ref_mask_bf
,
259 0xFFFFFFFF & C_028434_STENCILREF_BF
, NULL
);
260 r600_pipe_state_add_reg(rstate
, R_028438_SX_ALPHA_REF
, alpha_ref
, 0xFFFFFFFF, NULL
);
261 r600_pipe_state_add_reg(rstate
, R_0286E0_SPI_FOG_FUNC_SCALE
, 0x00000000, 0xFFFFFFFF, NULL
);
262 r600_pipe_state_add_reg(rstate
, R_0286E4_SPI_FOG_FUNC_BIAS
, 0x00000000, 0xFFFFFFFF, NULL
);
263 r600_pipe_state_add_reg(rstate
, R_0286DC_SPI_FOG_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
264 r600_pipe_state_add_reg(rstate
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
, 0xFFFFFFFF, NULL
);
265 r600_pipe_state_add_reg(rstate
, R_02880C_DB_SHADER_CONTROL
, db_shader_control
, 0xFFFFFFBE, NULL
);
266 r600_pipe_state_add_reg(rstate
, R_028D0C_DB_RENDER_CONTROL
, db_render_control
, 0xFFFFFFFF, NULL
);
267 r600_pipe_state_add_reg(rstate
, R_028D10_DB_RENDER_OVERRIDE
, db_render_override
, 0xFFFFFFFF, NULL
);
268 r600_pipe_state_add_reg(rstate
, R_028D2C_DB_SRESULTS_COMPARE_STATE1
, 0x00000000, 0xFFFFFFFF, NULL
);
269 r600_pipe_state_add_reg(rstate
, R_028D30_DB_PRELOAD_CONTROL
, 0x00000000, 0xFFFFFFFF, NULL
);
270 r600_pipe_state_add_reg(rstate
, R_028D44_DB_ALPHA_TO_MASK
, 0x0000AA00, 0xFFFFFFFF, NULL
);
275 static void *r600_create_rs_state(struct pipe_context
*ctx
,
276 const struct pipe_rasterizer_state
*state
)
278 struct r600_pipe_rasterizer
*rs
= CALLOC_STRUCT(r600_pipe_rasterizer
);
279 struct r600_pipe_state
*rstate
;
281 unsigned prov_vtx
= 1, polygon_dual_mode
;
288 rstate
= &rs
->rstate
;
289 rs
->flatshade
= state
->flatshade
;
290 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
292 clip_rule
= state
->scissor
? 0xAAAA : 0xFFFF;
294 rs
->offset_units
= state
->offset_units
;
295 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
297 rstate
->id
= R600_PIPE_STATE_RASTERIZER
;
298 if (state
->flatshade_first
)
300 tmp
= S_0286D4_FLAT_SHADE_ENA(1);
301 if (state
->sprite_coord_enable
) {
302 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
303 S_0286D4_PNT_SPRITE_OVRD_X(2) |
304 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
305 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
306 S_0286D4_PNT_SPRITE_OVRD_W(1);
307 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
308 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
311 r600_pipe_state_add_reg(rstate
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
, 0xFFFFFFFF, NULL
);
313 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
314 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
315 r600_pipe_state_add_reg(rstate
, R_028814_PA_SU_SC_MODE_CNTL
,
316 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
317 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
318 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
319 S_028814_FACE(!state
->front_ccw
) |
320 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
321 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
322 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
323 S_028814_POLY_MODE(polygon_dual_mode
) |
324 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
325 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)), 0xFFFFFFFF, NULL
);
326 r600_pipe_state_add_reg(rstate
, R_02881C_PA_CL_VS_OUT_CNTL
,
327 S_02881C_USE_VTX_POINT_SIZE(state
->point_size_per_vertex
) |
328 S_02881C_VS_OUT_MISC_VEC_ENA(state
->point_size_per_vertex
), 0xFFFFFFFF, NULL
);
329 r600_pipe_state_add_reg(rstate
, R_028820_PA_CL_NANINF_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
330 /* point size 12.4 fixed point */
331 tmp
= (unsigned)(state
->point_size
* 8.0);
332 r600_pipe_state_add_reg(rstate
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
), 0xFFFFFFFF, NULL
);
333 r600_pipe_state_add_reg(rstate
, R_028A04_PA_SU_POINT_MINMAX
, 0x80000000, 0xFFFFFFFF, NULL
);
335 tmp
= (unsigned)state
->line_width
* 8;
336 r600_pipe_state_add_reg(rstate
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
), 0xFFFFFFFF, NULL
);
338 r600_pipe_state_add_reg(rstate
, R_028A0C_PA_SC_LINE_STIPPLE
, 0x00000005, 0xFFFFFFFF, NULL
);
339 r600_pipe_state_add_reg(rstate
, R_028A48_PA_SC_MPASS_PS_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
340 r600_pipe_state_add_reg(rstate
, R_028C00_PA_SC_LINE_CNTL
, 0x00000400, 0xFFFFFFFF, NULL
);
342 r600_pipe_state_add_reg(rstate
, R_028C08_PA_SU_VTX_CNTL
,
343 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
),
346 r600_pipe_state_add_reg(rstate
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
347 r600_pipe_state_add_reg(rstate
, R_028C10_PA_CL_GB_VERT_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
348 r600_pipe_state_add_reg(rstate
, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
349 r600_pipe_state_add_reg(rstate
, R_028C18_PA_CL_GB_HORZ_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
350 r600_pipe_state_add_reg(rstate
, R_028DFC_PA_SU_POLY_OFFSET_CLAMP
, 0x00000000, 0xFFFFFFFF, NULL
);
351 r600_pipe_state_add_reg(rstate
, R_02820C_PA_SC_CLIPRECT_RULE
, clip_rule
, 0xFFFFFFFF, NULL
);
356 static void *r600_create_sampler_state(struct pipe_context
*ctx
,
357 const struct pipe_sampler_state
*state
)
359 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
362 if (rstate
== NULL
) {
366 rstate
->id
= R600_PIPE_STATE_SAMPLER
;
367 util_pack_color(state
->border_color
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
368 r600_pipe_state_add_reg(rstate
, R_03C000_SQ_TEX_SAMPLER_WORD0_0
,
369 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
370 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
371 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
372 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
)) |
373 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
)) |
374 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
375 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
376 S_03C000_BORDER_COLOR_TYPE(uc
.ui
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0), 0xFFFFFFFF, NULL
);
377 /* FIXME LOD it depends on texture base level ... */
378 r600_pipe_state_add_reg(rstate
, R_03C004_SQ_TEX_SAMPLER_WORD1_0
,
379 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
380 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
381 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6)), 0xFFFFFFFF, NULL
);
382 r600_pipe_state_add_reg(rstate
, R_03C008_SQ_TEX_SAMPLER_WORD2_0
, S_03C008_TYPE(1), 0xFFFFFFFF, NULL
);
384 r600_pipe_state_add_reg(rstate
, R_00A400_TD_PS_SAMPLER0_BORDER_RED
, fui(state
->border_color
[0]), 0xFFFFFFFF, NULL
);
385 r600_pipe_state_add_reg(rstate
, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN
, fui(state
->border_color
[1]), 0xFFFFFFFF, NULL
);
386 r600_pipe_state_add_reg(rstate
, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE
, fui(state
->border_color
[2]), 0xFFFFFFFF, NULL
);
387 r600_pipe_state_add_reg(rstate
, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA
, fui(state
->border_color
[3]), 0xFFFFFFFF, NULL
);
392 static struct pipe_sampler_view
*r600_create_sampler_view(struct pipe_context
*ctx
,
393 struct pipe_resource
*texture
,
394 const struct pipe_sampler_view
*state
)
396 struct r600_pipe_sampler_view
*resource
= CALLOC_STRUCT(r600_pipe_sampler_view
);
397 struct r600_pipe_state
*rstate
;
398 const struct util_format_description
*desc
;
399 struct r600_resource_texture
*tmp
;
400 struct r600_resource
*rbuffer
;
402 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
403 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
404 struct r600_bo
*bo
[2];
406 if (resource
== NULL
)
408 rstate
= &resource
->state
;
410 /* initialize base object */
411 resource
->base
= *state
;
412 resource
->base
.texture
= NULL
;
413 pipe_reference(NULL
, &texture
->reference
);
414 resource
->base
.texture
= texture
;
415 resource
->base
.reference
.count
= 1;
416 resource
->base
.context
= ctx
;
418 swizzle
[0] = state
->swizzle_r
;
419 swizzle
[1] = state
->swizzle_g
;
420 swizzle
[2] = state
->swizzle_b
;
421 swizzle
[3] = state
->swizzle_a
;
422 format
= r600_translate_texformat(state
->format
,
424 &word4
, &yuv_format
);
428 desc
= util_format_description(state
->format
);
430 R600_ERR("unknow format %d\n", state
->format
);
432 tmp
= (struct r600_resource_texture
*)texture
;
433 if (tmp
->depth
&& !tmp
->is_flushing_texture
) {
434 r600_texture_depth_flush(ctx
, texture
, TRUE
);
435 tmp
= tmp
->flushed_depth_texture
;
437 rbuffer
= &tmp
->resource
;
440 pitch
= align(tmp
->pitch_in_blocks
[0] * util_format_get_blockwidth(state
->format
), 8);
441 array_mode
= tmp
->array_mode
[0];
442 tile_type
= tmp
->tile_type
;
444 /* FIXME properly handle first level != 0 */
445 r600_pipe_state_add_reg(rstate
, R_038000_RESOURCE0_WORD0
,
446 S_038000_DIM(r600_tex_dim(texture
->target
)) |
447 S_038000_TILE_MODE(array_mode
) |
448 S_038000_TILE_TYPE(tile_type
) |
449 S_038000_PITCH((pitch
/ 8) - 1) |
450 S_038000_TEX_WIDTH(texture
->width0
- 1), 0xFFFFFFFF, NULL
);
451 r600_pipe_state_add_reg(rstate
, R_038004_RESOURCE0_WORD1
,
452 S_038004_TEX_HEIGHT(texture
->height0
- 1) |
453 S_038004_TEX_DEPTH(texture
->depth0
- 1) |
454 S_038004_DATA_FORMAT(format
), 0xFFFFFFFF, NULL
);
455 r600_pipe_state_add_reg(rstate
, R_038008_RESOURCE0_WORD2
,
456 (tmp
->offset
[0] + r600_bo_offset(bo
[0])) >> 8, 0xFFFFFFFF, bo
[0]);
457 r600_pipe_state_add_reg(rstate
, R_03800C_RESOURCE0_WORD3
,
458 (tmp
->offset
[1] + r600_bo_offset(bo
[1])) >> 8, 0xFFFFFFFF, bo
[1]);
459 r600_pipe_state_add_reg(rstate
, R_038010_RESOURCE0_WORD4
,
461 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_NO_ZERO
) |
462 S_038010_REQUEST_SIZE(1) |
463 S_038010_BASE_LEVEL(state
->u
.tex
.first_level
), 0xFFFFFFFF, NULL
);
464 r600_pipe_state_add_reg(rstate
, R_038014_RESOURCE0_WORD5
,
465 S_038014_LAST_LEVEL(state
->u
.tex
.last_level
) |
466 S_038014_BASE_ARRAY(0) |
467 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL
);
468 r600_pipe_state_add_reg(rstate
, R_038018_RESOURCE0_WORD6
,
469 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
), 0xFFFFFFFF, NULL
);
471 return &resource
->base
;
474 static void r600_set_vs_sampler_view(struct pipe_context
*ctx
, unsigned count
,
475 struct pipe_sampler_view
**views
)
477 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
478 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
480 for (int i
= 0; i
< count
; i
++) {
482 r600_context_pipe_state_set_vs_resource(&rctx
->ctx
, &resource
[i
]->state
, i
);
487 static void r600_set_ps_sampler_view(struct pipe_context
*ctx
, unsigned count
,
488 struct pipe_sampler_view
**views
)
490 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
491 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
494 for (i
= 0; i
< count
; i
++) {
495 if (&rctx
->ps_samplers
.views
[i
]->base
!= views
[i
]) {
497 r600_context_pipe_state_set_ps_resource(&rctx
->ctx
, &resource
[i
]->state
,
498 i
+ R600_MAX_CONST_BUFFERS
);
500 r600_context_pipe_state_set_ps_resource(&rctx
->ctx
, NULL
,
501 i
+ R600_MAX_CONST_BUFFERS
);
503 pipe_sampler_view_reference(
504 (struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
],
509 for (i
= count
; i
< NUM_TEX_UNITS
; i
++) {
510 if (rctx
->ps_samplers
.views
[i
]) {
511 r600_context_pipe_state_set_ps_resource(&rctx
->ctx
, NULL
,
512 i
+ R600_MAX_CONST_BUFFERS
);
513 pipe_sampler_view_reference((struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
], NULL
);
516 rctx
->ps_samplers
.n_views
= count
;
519 static void r600_bind_ps_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
521 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
522 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
524 memcpy(rctx
->ps_samplers
.samplers
, states
, sizeof(void*) * count
);
525 rctx
->ps_samplers
.n_samplers
= count
;
527 for (int i
= 0; i
< count
; i
++) {
528 r600_context_pipe_state_set_ps_sampler(&rctx
->ctx
, rstates
[i
], i
);
532 static void r600_bind_vs_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
534 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
535 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
537 for (int i
= 0; i
< count
; i
++) {
538 r600_context_pipe_state_set_vs_sampler(&rctx
->ctx
, rstates
[i
], i
);
542 static void r600_set_clip_state(struct pipe_context
*ctx
,
543 const struct pipe_clip_state
*state
)
545 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
546 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
552 rstate
->id
= R600_PIPE_STATE_CLIP
;
553 for (int i
= 0; i
< state
->nr
; i
++) {
554 r600_pipe_state_add_reg(rstate
,
555 R_028E20_PA_CL_UCP0_X
+ i
* 16,
556 fui(state
->ucp
[i
][0]), 0xFFFFFFFF, NULL
);
557 r600_pipe_state_add_reg(rstate
,
558 R_028E24_PA_CL_UCP0_Y
+ i
* 16,
559 fui(state
->ucp
[i
][1]) , 0xFFFFFFFF, NULL
);
560 r600_pipe_state_add_reg(rstate
,
561 R_028E28_PA_CL_UCP0_Z
+ i
* 16,
562 fui(state
->ucp
[i
][2]), 0xFFFFFFFF, NULL
);
563 r600_pipe_state_add_reg(rstate
,
564 R_028E2C_PA_CL_UCP0_W
+ i
* 16,
565 fui(state
->ucp
[i
][3]), 0xFFFFFFFF, NULL
);
567 r600_pipe_state_add_reg(rstate
, R_028810_PA_CL_CLIP_CNTL
,
568 S_028810_PS_UCP_MODE(3) | ((1 << state
->nr
) - 1) |
569 S_028810_ZCLIP_NEAR_DISABLE(state
->depth_clamp
) |
570 S_028810_ZCLIP_FAR_DISABLE(state
->depth_clamp
), 0xFFFFFFFF, NULL
);
572 free(rctx
->states
[R600_PIPE_STATE_CLIP
]);
573 rctx
->states
[R600_PIPE_STATE_CLIP
] = rstate
;
574 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
577 static void r600_set_polygon_stipple(struct pipe_context
*ctx
,
578 const struct pipe_poly_stipple
*state
)
582 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
586 static void r600_set_scissor_state(struct pipe_context
*ctx
,
587 const struct pipe_scissor_state
*state
)
589 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
590 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
596 rstate
->id
= R600_PIPE_STATE_SCISSOR
;
597 tl
= S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
) | S_028240_WINDOW_OFFSET_DISABLE(1);
598 br
= S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
);
599 r600_pipe_state_add_reg(rstate
,
600 R_028210_PA_SC_CLIPRECT_0_TL
, tl
,
602 r600_pipe_state_add_reg(rstate
,
603 R_028214_PA_SC_CLIPRECT_0_BR
, br
,
605 r600_pipe_state_add_reg(rstate
,
606 R_028218_PA_SC_CLIPRECT_1_TL
, tl
,
608 r600_pipe_state_add_reg(rstate
,
609 R_02821C_PA_SC_CLIPRECT_1_BR
, br
,
611 r600_pipe_state_add_reg(rstate
,
612 R_028220_PA_SC_CLIPRECT_2_TL
, tl
,
614 r600_pipe_state_add_reg(rstate
,
615 R_028224_PA_SC_CLIPRECT_2_BR
, br
,
617 r600_pipe_state_add_reg(rstate
,
618 R_028228_PA_SC_CLIPRECT_3_TL
, tl
,
620 r600_pipe_state_add_reg(rstate
,
621 R_02822C_PA_SC_CLIPRECT_3_BR
, br
,
624 free(rctx
->states
[R600_PIPE_STATE_SCISSOR
]);
625 rctx
->states
[R600_PIPE_STATE_SCISSOR
] = rstate
;
626 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
629 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
630 const struct pipe_stencil_ref
*state
)
632 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
633 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
639 rctx
->stencil_ref
= *state
;
640 rstate
->id
= R600_PIPE_STATE_STENCIL_REF
;
641 tmp
= S_028430_STENCILREF(state
->ref_value
[0]);
642 r600_pipe_state_add_reg(rstate
,
643 R_028430_DB_STENCILREFMASK
, tmp
,
644 ~C_028430_STENCILREF
, NULL
);
645 tmp
= S_028434_STENCILREF_BF(state
->ref_value
[1]);
646 r600_pipe_state_add_reg(rstate
,
647 R_028434_DB_STENCILREFMASK_BF
, tmp
,
648 ~C_028434_STENCILREF_BF
, NULL
);
650 free(rctx
->states
[R600_PIPE_STATE_STENCIL_REF
]);
651 rctx
->states
[R600_PIPE_STATE_STENCIL_REF
] = rstate
;
652 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
655 static void r600_set_viewport_state(struct pipe_context
*ctx
,
656 const struct pipe_viewport_state
*state
)
658 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
659 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
664 rctx
->viewport
= *state
;
665 rstate
->id
= R600_PIPE_STATE_VIEWPORT
;
666 r600_pipe_state_add_reg(rstate
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 0x00000000, 0xFFFFFFFF, NULL
);
667 r600_pipe_state_add_reg(rstate
, R_0282D4_PA_SC_VPORT_ZMAX_0
, 0x3F800000, 0xFFFFFFFF, NULL
);
668 r600_pipe_state_add_reg(rstate
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]), 0xFFFFFFFF, NULL
);
669 r600_pipe_state_add_reg(rstate
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]), 0xFFFFFFFF, NULL
);
670 r600_pipe_state_add_reg(rstate
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]), 0xFFFFFFFF, NULL
);
671 r600_pipe_state_add_reg(rstate
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]), 0xFFFFFFFF, NULL
);
672 r600_pipe_state_add_reg(rstate
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]), 0xFFFFFFFF, NULL
);
673 r600_pipe_state_add_reg(rstate
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]), 0xFFFFFFFF, NULL
);
674 r600_pipe_state_add_reg(rstate
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F, 0xFFFFFFFF, NULL
);
676 free(rctx
->states
[R600_PIPE_STATE_VIEWPORT
]);
677 rctx
->states
[R600_PIPE_STATE_VIEWPORT
] = rstate
;
678 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
681 static void r600_cb(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
,
682 const struct pipe_framebuffer_state
*state
, int cb
)
684 struct r600_resource_texture
*rtex
;
685 struct r600_resource
*rbuffer
;
686 struct r600_surface
*surf
;
687 unsigned level
= state
->cbufs
[cb
]->u
.tex
.level
;
688 unsigned pitch
, slice
;
690 unsigned format
, swap
, ntype
;
692 const struct util_format_description
*desc
;
693 struct r600_bo
*bo
[3];
696 surf
= (struct r600_surface
*)state
->cbufs
[cb
];
697 rtex
= (struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
;
699 if (rtex
->depth
&& !rtex
->is_flushing_texture
) {
700 r600_texture_depth_flush(&rctx
->context
, state
->cbufs
[cb
]->texture
, TRUE
);
701 rtex
= rtex
->flushed_depth_texture
;
704 rbuffer
= &rtex
->resource
;
709 /* XXX quite sure for dx10+ hw don't need any offset hacks */
710 offset
= r600_texture_get_offset(rtex
,
711 level
, state
->cbufs
[cb
]->u
.tex
.first_layer
);
712 pitch
= rtex
->pitch_in_blocks
[level
] / 8 - 1;
713 slice
= rtex
->pitch_in_blocks
[level
] * surf
->aligned_height
/ 64 - 1;
715 desc
= util_format_description(surf
->base
.format
);
716 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
717 ntype
= V_0280A0_NUMBER_SRGB
;
719 for (i
= 0; i
< 4; i
++) {
720 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
725 format
= r600_translate_colorformat(surf
->base
.format
);
726 swap
= r600_translate_colorswap(surf
->base
.format
);
727 color_info
= S_0280A0_FORMAT(format
) |
728 S_0280A0_COMP_SWAP(swap
) |
729 S_0280A0_ARRAY_MODE(rtex
->array_mode
[level
]) |
730 S_0280A0_BLEND_CLAMP(1) |
731 S_0280A0_NUMBER_TYPE(ntype
);
733 /* on R600 this can't be set if BLEND_CLAMP isn't set,
734 if BLEND_FLOAT32 is set of > 11 bits in a UNORM or SNORM */
735 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
736 desc
->channel
[i
].size
< 12)
737 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
739 r600_pipe_state_add_reg(rstate
,
740 R_028040_CB_COLOR0_BASE
+ cb
* 4,
741 (offset
+ r600_bo_offset(bo
[0])) >> 8, 0xFFFFFFFF, bo
[0]);
742 r600_pipe_state_add_reg(rstate
,
743 R_0280A0_CB_COLOR0_INFO
+ cb
* 4,
744 color_info
, 0xFFFFFFFF, bo
[0]);
745 r600_pipe_state_add_reg(rstate
,
746 R_028060_CB_COLOR0_SIZE
+ cb
* 4,
747 S_028060_PITCH_TILE_MAX(pitch
) |
748 S_028060_SLICE_TILE_MAX(slice
),
750 r600_pipe_state_add_reg(rstate
,
751 R_028080_CB_COLOR0_VIEW
+ cb
* 4,
752 0x00000000, 0xFFFFFFFF, NULL
);
753 r600_pipe_state_add_reg(rstate
,
754 R_0280E0_CB_COLOR0_FRAG
+ cb
* 4,
755 r600_bo_offset(bo
[1]) >> 8, 0xFFFFFFFF, bo
[1]);
756 r600_pipe_state_add_reg(rstate
,
757 R_0280C0_CB_COLOR0_TILE
+ cb
* 4,
758 r600_bo_offset(bo
[2]) >> 8, 0xFFFFFFFF, bo
[2]);
759 r600_pipe_state_add_reg(rstate
,
760 R_028100_CB_COLOR0_MASK
+ cb
* 4,
761 0x00000000, 0xFFFFFFFF, NULL
);
764 static void r600_db(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
,
765 const struct pipe_framebuffer_state
*state
)
767 struct r600_resource_texture
*rtex
;
768 struct r600_resource
*rbuffer
;
769 struct r600_surface
*surf
;
771 unsigned pitch
, slice
, format
;
774 if (state
->zsbuf
== NULL
)
777 level
= state
->zsbuf
->u
.tex
.level
;
779 surf
= (struct r600_surface
*)state
->zsbuf
;
780 rtex
= (struct r600_resource_texture
*)state
->zsbuf
->texture
;
782 rbuffer
= &rtex
->resource
;
784 /* XXX quite sure for dx10+ hw don't need any offset hacks */
785 offset
= r600_texture_get_offset((struct r600_resource_texture
*)state
->zsbuf
->texture
,
786 level
, state
->zsbuf
->u
.tex
.first_layer
);
787 pitch
= rtex
->pitch_in_blocks
[level
] / 8 - 1;
788 slice
= rtex
->pitch_in_blocks
[level
] * surf
->aligned_height
/ 64 - 1;
789 format
= r600_translate_dbformat(state
->zsbuf
->texture
->format
);
791 r600_pipe_state_add_reg(rstate
, R_02800C_DB_DEPTH_BASE
,
792 (offset
+ r600_bo_offset(rbuffer
->bo
)) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
793 r600_pipe_state_add_reg(rstate
, R_028000_DB_DEPTH_SIZE
,
794 S_028000_PITCH_TILE_MAX(pitch
) | S_028000_SLICE_TILE_MAX(slice
),
796 r600_pipe_state_add_reg(rstate
, R_028004_DB_DEPTH_VIEW
, 0x00000000, 0xFFFFFFFF, NULL
);
797 r600_pipe_state_add_reg(rstate
, R_028010_DB_DEPTH_INFO
,
798 S_028010_ARRAY_MODE(rtex
->array_mode
[level
]) | S_028010_FORMAT(format
),
799 0xFFFFFFFF, rbuffer
->bo
);
800 r600_pipe_state_add_reg(rstate
, R_028D34_DB_PREFETCH_LIMIT
,
801 (surf
->aligned_height
/ 8) - 1, 0xFFFFFFFF, NULL
);
804 static void r600_set_framebuffer_state(struct pipe_context
*ctx
,
805 const struct pipe_framebuffer_state
*state
)
807 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
808 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
809 u32 shader_mask
, tl
, br
, shader_control
, target_mask
;
814 /* unreference old buffer and reference new one */
815 rstate
->id
= R600_PIPE_STATE_FRAMEBUFFER
;
817 util_copy_framebuffer_state(&rctx
->framebuffer
, state
);
820 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
821 r600_cb(rctx
, rstate
, state
, i
);
824 r600_db(rctx
, rstate
, state
);
827 target_mask
= 0x00000000;
828 target_mask
= 0xFFFFFFFF;
831 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
832 target_mask
^= 0xf << (i
* 4);
833 shader_mask
|= 0xf << (i
* 4);
834 shader_control
|= 1 << i
;
836 tl
= S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
837 br
= S_028244_BR_X(state
->width
) | S_028244_BR_Y(state
->height
);
839 r600_pipe_state_add_reg(rstate
,
840 R_028030_PA_SC_SCREEN_SCISSOR_TL
, tl
,
842 r600_pipe_state_add_reg(rstate
,
843 R_028034_PA_SC_SCREEN_SCISSOR_BR
, br
,
845 r600_pipe_state_add_reg(rstate
,
846 R_028204_PA_SC_WINDOW_SCISSOR_TL
, tl
,
848 r600_pipe_state_add_reg(rstate
,
849 R_028208_PA_SC_WINDOW_SCISSOR_BR
, br
,
851 r600_pipe_state_add_reg(rstate
,
852 R_028240_PA_SC_GENERIC_SCISSOR_TL
, tl
,
854 r600_pipe_state_add_reg(rstate
,
855 R_028244_PA_SC_GENERIC_SCISSOR_BR
, br
,
857 r600_pipe_state_add_reg(rstate
,
858 R_028250_PA_SC_VPORT_SCISSOR_0_TL
, tl
,
860 r600_pipe_state_add_reg(rstate
,
861 R_028254_PA_SC_VPORT_SCISSOR_0_BR
, br
,
863 r600_pipe_state_add_reg(rstate
,
864 R_028200_PA_SC_WINDOW_OFFSET
, 0x00000000,
866 if (rctx
->family
>= CHIP_RV770
) {
867 r600_pipe_state_add_reg(rstate
,
868 R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA,
872 r600_pipe_state_add_reg(rstate
, R_0287A0_CB_SHADER_CONTROL
,
873 shader_control
, 0xFFFFFFFF, NULL
);
874 r600_pipe_state_add_reg(rstate
, R_028238_CB_TARGET_MASK
,
875 0x00000000, target_mask
, NULL
);
876 r600_pipe_state_add_reg(rstate
, R_02823C_CB_SHADER_MASK
,
877 shader_mask
, 0xFFFFFFFF, NULL
);
878 r600_pipe_state_add_reg(rstate
, R_028C04_PA_SC_AA_CONFIG
,
879 0x00000000, 0xFFFFFFFF, NULL
);
880 r600_pipe_state_add_reg(rstate
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
,
881 0x00000000, 0xFFFFFFFF, NULL
);
882 r600_pipe_state_add_reg(rstate
, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX
,
883 0x00000000, 0xFFFFFFFF, NULL
);
884 r600_pipe_state_add_reg(rstate
, R_028C30_CB_CLRCMP_CONTROL
,
885 0x01000000, 0xFFFFFFFF, NULL
);
886 r600_pipe_state_add_reg(rstate
, R_028C34_CB_CLRCMP_SRC
,
887 0x00000000, 0xFFFFFFFF, NULL
);
888 r600_pipe_state_add_reg(rstate
, R_028C38_CB_CLRCMP_DST
,
889 0x000000FF, 0xFFFFFFFF, NULL
);
890 r600_pipe_state_add_reg(rstate
, R_028C3C_CB_CLRCMP_MSK
,
891 0xFFFFFFFF, 0xFFFFFFFF, NULL
);
892 r600_pipe_state_add_reg(rstate
, R_028C48_PA_SC_AA_MASK
,
893 0xFFFFFFFF, 0xFFFFFFFF, NULL
);
895 free(rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
]);
896 rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
] = rstate
;
897 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
900 r600_polygon_offset_update(rctx
);
904 void r600_init_state_functions(struct r600_pipe_context
*rctx
)
906 rctx
->context
.create_blend_state
= r600_create_blend_state
;
907 rctx
->context
.create_depth_stencil_alpha_state
= r600_create_dsa_state
;
908 rctx
->context
.create_fs_state
= r600_create_shader_state
;
909 rctx
->context
.create_rasterizer_state
= r600_create_rs_state
;
910 rctx
->context
.create_sampler_state
= r600_create_sampler_state
;
911 rctx
->context
.create_sampler_view
= r600_create_sampler_view
;
912 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
913 rctx
->context
.create_vs_state
= r600_create_shader_state
;
914 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
915 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_state
;
916 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_sampler
;
917 rctx
->context
.bind_fs_state
= r600_bind_ps_shader
;
918 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
919 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
920 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_sampler
;
921 rctx
->context
.bind_vs_state
= r600_bind_vs_shader
;
922 rctx
->context
.delete_blend_state
= r600_delete_state
;
923 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
924 rctx
->context
.delete_fs_state
= r600_delete_ps_shader
;
925 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
926 rctx
->context
.delete_sampler_state
= r600_delete_state
;
927 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_element
;
928 rctx
->context
.delete_vs_state
= r600_delete_vs_shader
;
929 rctx
->context
.set_blend_color
= r600_set_blend_color
;
930 rctx
->context
.set_clip_state
= r600_set_clip_state
;
931 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
932 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_view
;
933 rctx
->context
.set_framebuffer_state
= r600_set_framebuffer_state
;
934 rctx
->context
.set_polygon_stipple
= r600_set_polygon_stipple
;
935 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
936 rctx
->context
.set_scissor_state
= r600_set_scissor_state
;
937 rctx
->context
.set_stencil_ref
= r600_set_stencil_ref
;
938 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
939 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
940 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_view
;
941 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
942 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
943 rctx
->context
.redefine_user_buffer
= u_default_redefine_user_buffer
;
946 void r600_init_config(struct r600_pipe_context
*rctx
)
961 int num_ps_stack_entries
;
962 int num_vs_stack_entries
;
963 int num_gs_stack_entries
;
964 int num_es_stack_entries
;
965 enum radeon_family family
;
966 struct r600_pipe_state
*rstate
= &rctx
->config
;
969 family
= r600_get_family(rctx
->radeon
);
981 num_ps_threads
= 136;
985 num_ps_stack_entries
= 128;
986 num_vs_stack_entries
= 128;
987 num_gs_stack_entries
= 0;
988 num_es_stack_entries
= 0;
997 num_ps_threads
= 144;
1001 num_ps_stack_entries
= 40;
1002 num_vs_stack_entries
= 40;
1003 num_gs_stack_entries
= 32;
1004 num_es_stack_entries
= 16;
1016 num_ps_threads
= 136;
1017 num_vs_threads
= 48;
1020 num_ps_stack_entries
= 40;
1021 num_vs_stack_entries
= 40;
1022 num_gs_stack_entries
= 32;
1023 num_es_stack_entries
= 16;
1031 num_ps_threads
= 136;
1032 num_vs_threads
= 48;
1035 num_ps_stack_entries
= 40;
1036 num_vs_stack_entries
= 40;
1037 num_gs_stack_entries
= 32;
1038 num_es_stack_entries
= 16;
1046 num_ps_threads
= 188;
1047 num_vs_threads
= 60;
1050 num_ps_stack_entries
= 256;
1051 num_vs_stack_entries
= 256;
1052 num_gs_stack_entries
= 0;
1053 num_es_stack_entries
= 0;
1062 num_ps_threads
= 188;
1063 num_vs_threads
= 60;
1066 num_ps_stack_entries
= 128;
1067 num_vs_stack_entries
= 128;
1068 num_gs_stack_entries
= 0;
1069 num_es_stack_entries
= 0;
1077 num_ps_threads
= 144;
1078 num_vs_threads
= 48;
1081 num_ps_stack_entries
= 128;
1082 num_vs_stack_entries
= 128;
1083 num_gs_stack_entries
= 0;
1084 num_es_stack_entries
= 0;
1088 rstate
->id
= R600_PIPE_STATE_CONFIG
;
1100 tmp
|= S_008C00_VC_ENABLE(1);
1103 tmp
|= S_008C00_DX9_CONSTS(0);
1104 tmp
|= S_008C00_ALU_INST_PREFER_VECTOR(1);
1105 tmp
|= S_008C00_PS_PRIO(ps_prio
);
1106 tmp
|= S_008C00_VS_PRIO(vs_prio
);
1107 tmp
|= S_008C00_GS_PRIO(gs_prio
);
1108 tmp
|= S_008C00_ES_PRIO(es_prio
);
1109 r600_pipe_state_add_reg(rstate
, R_008C00_SQ_CONFIG
, tmp
, 0xFFFFFFFF, NULL
);
1111 /* SQ_GPR_RESOURCE_MGMT_1 */
1113 tmp
|= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
1114 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
1115 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
1116 r600_pipe_state_add_reg(rstate
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
);
1118 /* SQ_GPR_RESOURCE_MGMT_2 */
1120 tmp
|= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
1121 tmp
|= S_008C08_NUM_GS_GPRS(num_es_gprs
);
1122 r600_pipe_state_add_reg(rstate
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
);
1124 /* SQ_THREAD_RESOURCE_MGMT */
1126 tmp
|= S_008C0C_NUM_PS_THREADS(num_ps_threads
);
1127 tmp
|= S_008C0C_NUM_VS_THREADS(num_vs_threads
);
1128 tmp
|= S_008C0C_NUM_GS_THREADS(num_gs_threads
);
1129 tmp
|= S_008C0C_NUM_ES_THREADS(num_es_threads
);
1130 r600_pipe_state_add_reg(rstate
, R_008C0C_SQ_THREAD_RESOURCE_MGMT
, tmp
, 0xFFFFFFFF, NULL
);
1132 /* SQ_STACK_RESOURCE_MGMT_1 */
1134 tmp
|= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
1135 tmp
|= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
1136 r600_pipe_state_add_reg(rstate
, R_008C10_SQ_STACK_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
);
1138 /* SQ_STACK_RESOURCE_MGMT_2 */
1140 tmp
|= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
1141 tmp
|= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
1142 r600_pipe_state_add_reg(rstate
, R_008C14_SQ_STACK_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
);
1144 r600_pipe_state_add_reg(rstate
, R_009714_VC_ENHANCE
, 0x00000000, 0xFFFFFFFF, NULL
);
1145 r600_pipe_state_add_reg(rstate
, R_028350_SX_MISC
, 0x00000000, 0xFFFFFFFF, NULL
);
1147 if (family
>= CHIP_RV770
) {
1148 r600_pipe_state_add_reg(rstate
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x00004000, 0xFFFFFFFF, NULL
);
1149 r600_pipe_state_add_reg(rstate
, R_009508_TA_CNTL_AUX
, 0x07000002, 0xFFFFFFFF, NULL
);
1150 r600_pipe_state_add_reg(rstate
, R_009830_DB_DEBUG
, 0x00000000, 0xFFFFFFFF, NULL
);
1151 r600_pipe_state_add_reg(rstate
, R_009838_DB_WATERMARKS
, 0x00420204, 0xFFFFFFFF, NULL
);
1152 r600_pipe_state_add_reg(rstate
, R_0286C8_SPI_THREAD_GROUPING
, 0x00000000, 0xFFFFFFFF, NULL
);
1153 r600_pipe_state_add_reg(rstate
, R_028A4C_PA_SC_MODE_CNTL
, 0x00514002, 0xFFFFFFFF, NULL
);
1155 r600_pipe_state_add_reg(rstate
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x00000000, 0xFFFFFFFF, NULL
);
1156 r600_pipe_state_add_reg(rstate
, R_009508_TA_CNTL_AUX
, 0x07000003, 0xFFFFFFFF, NULL
);
1157 r600_pipe_state_add_reg(rstate
, R_009830_DB_DEBUG
, 0x82000000, 0xFFFFFFFF, NULL
);
1158 r600_pipe_state_add_reg(rstate
, R_009838_DB_WATERMARKS
, 0x01020204, 0xFFFFFFFF, NULL
);
1159 r600_pipe_state_add_reg(rstate
, R_0286C8_SPI_THREAD_GROUPING
, 0x00000001, 0xFFFFFFFF, NULL
);
1160 r600_pipe_state_add_reg(rstate
, R_028A4C_PA_SC_MODE_CNTL
, 0x00004012, 0xFFFFFFFF, NULL
);
1162 r600_pipe_state_add_reg(rstate
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1163 r600_pipe_state_add_reg(rstate
, R_0288AC_SQ_GSVS_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1164 r600_pipe_state_add_reg(rstate
, R_0288B0_SQ_ESTMP_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1165 r600_pipe_state_add_reg(rstate
, R_0288B4_SQ_GSTMP_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1166 r600_pipe_state_add_reg(rstate
, R_0288B8_SQ_VSTMP_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1167 r600_pipe_state_add_reg(rstate
, R_0288BC_SQ_PSTMP_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1168 r600_pipe_state_add_reg(rstate
, R_0288C0_SQ_FBUF_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1169 r600_pipe_state_add_reg(rstate
, R_0288C4_SQ_REDUC_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1170 r600_pipe_state_add_reg(rstate
, R_0288C8_SQ_GS_VERT_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1171 r600_pipe_state_add_reg(rstate
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1172 r600_pipe_state_add_reg(rstate
, R_028A14_VGT_HOS_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1173 r600_pipe_state_add_reg(rstate
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0x00000000, 0xFFFFFFFF, NULL
);
1174 r600_pipe_state_add_reg(rstate
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0x00000000, 0xFFFFFFFF, NULL
);
1175 r600_pipe_state_add_reg(rstate
, R_028A20_VGT_HOS_REUSE_DEPTH
, 0x00000000, 0xFFFFFFFF, NULL
);
1176 r600_pipe_state_add_reg(rstate
, R_028A24_VGT_GROUP_PRIM_TYPE
, 0x00000000, 0xFFFFFFFF, NULL
);
1177 r600_pipe_state_add_reg(rstate
, R_028A28_VGT_GROUP_FIRST_DECR
, 0x00000000, 0xFFFFFFFF, NULL
);
1178 r600_pipe_state_add_reg(rstate
, R_028A2C_VGT_GROUP_DECR
, 0x00000000, 0xFFFFFFFF, NULL
);
1179 r600_pipe_state_add_reg(rstate
, R_028A30_VGT_GROUP_VECT_0_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1180 r600_pipe_state_add_reg(rstate
, R_028A34_VGT_GROUP_VECT_1_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1181 r600_pipe_state_add_reg(rstate
, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1182 r600_pipe_state_add_reg(rstate
, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1183 r600_pipe_state_add_reg(rstate
, R_028A40_VGT_GS_MODE
, 0x00000000, 0xFFFFFFFF, NULL
);
1184 r600_pipe_state_add_reg(rstate
, R_028AB0_VGT_STRMOUT_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
1185 r600_pipe_state_add_reg(rstate
, R_028AB4_VGT_REUSE_OFF
, 0x00000001, 0xFFFFFFFF, NULL
);
1186 r600_pipe_state_add_reg(rstate
, R_028AB8_VGT_VTX_CNT_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
1187 r600_pipe_state_add_reg(rstate
, R_028B20_VGT_STRMOUT_BUFFER_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
1189 r600_pipe_state_add_reg(rstate
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, 0x00000000, 0xFFFFFFFF, NULL
);
1190 r600_pipe_state_add_reg(rstate
, R_028A84_VGT_PRIMITIVEID_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
1191 r600_pipe_state_add_reg(rstate
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
1192 r600_pipe_state_add_reg(rstate
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 0x00000000, 0xFFFFFFFF, NULL
);
1193 r600_pipe_state_add_reg(rstate
, R_028AA4_VGT_INSTANCE_STEP_RATE_1
, 0x00000000, 0xFFFFFFFF, NULL
);
1194 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1197 void *r600_create_db_flush_dsa(struct r600_pipe_context
*rctx
)
1199 struct pipe_depth_stencil_alpha_state dsa
;
1200 struct r600_pipe_state
*rstate
;
1201 boolean quirk
= false;
1203 if (rctx
->family
== CHIP_RV610
|| rctx
->family
== CHIP_RV630
||
1204 rctx
->family
== CHIP_RV620
|| rctx
->family
== CHIP_RV635
)
1207 memset(&dsa
, 0, sizeof(dsa
));
1210 dsa
.depth
.enabled
= 1;
1211 dsa
.depth
.func
= PIPE_FUNC_LEQUAL
;
1212 dsa
.stencil
[0].enabled
= 1;
1213 dsa
.stencil
[0].func
= PIPE_FUNC_ALWAYS
;
1214 dsa
.stencil
[0].zpass_op
= PIPE_STENCIL_OP_KEEP
;
1215 dsa
.stencil
[0].zfail_op
= PIPE_STENCIL_OP_INCR
;
1216 dsa
.stencil
[0].writemask
= 0xff;
1219 rstate
= rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
1220 r600_pipe_state_add_reg(rstate
,
1221 R_02880C_DB_SHADER_CONTROL
,
1223 S_02880C_DUAL_EXPORT_ENABLE(1), NULL
);
1224 r600_pipe_state_add_reg(rstate
,
1225 R_028D0C_DB_RENDER_CONTROL
,
1226 S_028D0C_DEPTH_COPY_ENABLE(1) |
1227 S_028D0C_STENCIL_COPY_ENABLE(1) |
1228 S_028D0C_COPY_CENTROID(1),
1229 S_028D0C_DEPTH_COPY_ENABLE(1) |
1230 S_028D0C_STENCIL_COPY_ENABLE(1) |
1231 S_028D0C_COPY_CENTROID(1), NULL
);
1235 void r600_pipe_set_buffer_resource(struct r600_pipe_context
*rctx
,
1236 struct r600_pipe_state
*rstate
,
1237 struct r600_resource
*rbuffer
,
1238 unsigned offset
, unsigned stride
)
1240 r600_pipe_state_add_reg(rstate
, R_038000_RESOURCE0_WORD0
,
1241 offset
, 0xFFFFFFFF, rbuffer
->bo
);
1242 r600_pipe_state_add_reg(rstate
, R_038004_RESOURCE0_WORD1
,
1243 rbuffer
->bo_size
- offset
- 1, 0xFFFFFFFF, NULL
);
1244 r600_pipe_state_add_reg(rstate
, R_038008_RESOURCE0_WORD2
,
1245 S_038008_STRIDE(stride
),
1247 r600_pipe_state_add_reg(rstate
, R_03800C_RESOURCE0_WORD3
,
1248 0x00000000, 0xFFFFFFFF, NULL
);
1249 r600_pipe_state_add_reg(rstate
, R_038010_RESOURCE0_WORD4
,
1250 0x00000000, 0xFFFFFFFF, NULL
);
1251 r600_pipe_state_add_reg(rstate
, R_038014_RESOURCE0_WORD5
,
1252 0x00000000, 0xFFFFFFFF, NULL
);
1253 r600_pipe_state_add_reg(rstate
, R_038018_RESOURCE0_WORD6
,
1254 0xC0000000, 0xFFFFFFFF, NULL
);