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r600g: cleanup setting DB_SHADER_CONTROL
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include "pipe/p_defines.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_util.h"
35 #include "util/u_double_list.h"
36 #include "util/u_pack_color.h"
37 #include "util/u_memory.h"
38 #include "util/u_inlines.h"
39 #include "util/u_framebuffer.h"
40 #include "util/u_transfer.h"
41 #include "pipebuffer/pb_buffer.h"
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_formats.h"
48
49 static uint32_t r600_translate_blend_function(int blend_func)
50 {
51 switch (blend_func) {
52 case PIPE_BLEND_ADD:
53 return V_028804_COMB_DST_PLUS_SRC;
54 case PIPE_BLEND_SUBTRACT:
55 return V_028804_COMB_SRC_MINUS_DST;
56 case PIPE_BLEND_REVERSE_SUBTRACT:
57 return V_028804_COMB_DST_MINUS_SRC;
58 case PIPE_BLEND_MIN:
59 return V_028804_COMB_MIN_DST_SRC;
60 case PIPE_BLEND_MAX:
61 return V_028804_COMB_MAX_DST_SRC;
62 default:
63 R600_ERR("Unknown blend function %d\n", blend_func);
64 assert(0);
65 break;
66 }
67 return 0;
68 }
69
70 static uint32_t r600_translate_blend_factor(int blend_fact)
71 {
72 switch (blend_fact) {
73 case PIPE_BLENDFACTOR_ONE:
74 return V_028804_BLEND_ONE;
75 case PIPE_BLENDFACTOR_SRC_COLOR:
76 return V_028804_BLEND_SRC_COLOR;
77 case PIPE_BLENDFACTOR_SRC_ALPHA:
78 return V_028804_BLEND_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_DST_ALPHA:
80 return V_028804_BLEND_DST_ALPHA;
81 case PIPE_BLENDFACTOR_DST_COLOR:
82 return V_028804_BLEND_DST_COLOR;
83 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
84 return V_028804_BLEND_SRC_ALPHA_SATURATE;
85 case PIPE_BLENDFACTOR_CONST_COLOR:
86 return V_028804_BLEND_CONST_COLOR;
87 case PIPE_BLENDFACTOR_CONST_ALPHA:
88 return V_028804_BLEND_CONST_ALPHA;
89 case PIPE_BLENDFACTOR_ZERO:
90 return V_028804_BLEND_ZERO;
91 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
92 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
94 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
95 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
96 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
97 case PIPE_BLENDFACTOR_INV_DST_COLOR:
98 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
99 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
100 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
101 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
102 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
103 case PIPE_BLENDFACTOR_SRC1_COLOR:
104 return V_028804_BLEND_SRC1_COLOR;
105 case PIPE_BLENDFACTOR_SRC1_ALPHA:
106 return V_028804_BLEND_SRC1_ALPHA;
107 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
108 return V_028804_BLEND_INV_SRC1_COLOR;
109 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
110 return V_028804_BLEND_INV_SRC1_ALPHA;
111 default:
112 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
113 assert(0);
114 break;
115 }
116 return 0;
117 }
118
119 static uint32_t r600_translate_stencil_op(int s_op)
120 {
121 switch (s_op) {
122 case PIPE_STENCIL_OP_KEEP:
123 return V_028800_STENCIL_KEEP;
124 case PIPE_STENCIL_OP_ZERO:
125 return V_028800_STENCIL_ZERO;
126 case PIPE_STENCIL_OP_REPLACE:
127 return V_028800_STENCIL_REPLACE;
128 case PIPE_STENCIL_OP_INCR:
129 return V_028800_STENCIL_INCR;
130 case PIPE_STENCIL_OP_DECR:
131 return V_028800_STENCIL_DECR;
132 case PIPE_STENCIL_OP_INCR_WRAP:
133 return V_028800_STENCIL_INCR_WRAP;
134 case PIPE_STENCIL_OP_DECR_WRAP:
135 return V_028800_STENCIL_DECR_WRAP;
136 case PIPE_STENCIL_OP_INVERT:
137 return V_028800_STENCIL_INVERT;
138 default:
139 R600_ERR("Unknown stencil op %d", s_op);
140 assert(0);
141 break;
142 }
143 return 0;
144 }
145
146 static uint32_t r600_translate_fill(uint32_t func)
147 {
148 switch(func) {
149 case PIPE_POLYGON_MODE_FILL:
150 return 2;
151 case PIPE_POLYGON_MODE_LINE:
152 return 1;
153 case PIPE_POLYGON_MODE_POINT:
154 return 0;
155 default:
156 assert(0);
157 return 0;
158 }
159 }
160
161 /* translates straight */
162 static uint32_t r600_translate_ds_func(int func)
163 {
164 return func;
165 }
166
167 static unsigned r600_tex_wrap(unsigned wrap)
168 {
169 switch (wrap) {
170 default:
171 case PIPE_TEX_WRAP_REPEAT:
172 return V_03C000_SQ_TEX_WRAP;
173 case PIPE_TEX_WRAP_CLAMP:
174 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
175 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
176 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
177 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
178 return V_03C000_SQ_TEX_CLAMP_BORDER;
179 case PIPE_TEX_WRAP_MIRROR_REPEAT:
180 return V_03C000_SQ_TEX_MIRROR;
181 case PIPE_TEX_WRAP_MIRROR_CLAMP:
182 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
183 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
184 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
185 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
186 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
187 }
188 }
189
190 static unsigned r600_tex_filter(unsigned filter)
191 {
192 switch (filter) {
193 default:
194 case PIPE_TEX_FILTER_NEAREST:
195 return V_03C000_SQ_TEX_XY_FILTER_POINT;
196 case PIPE_TEX_FILTER_LINEAR:
197 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
198 }
199 }
200
201 static unsigned r600_tex_mipfilter(unsigned filter)
202 {
203 switch (filter) {
204 case PIPE_TEX_MIPFILTER_NEAREST:
205 return V_03C000_SQ_TEX_Z_FILTER_POINT;
206 case PIPE_TEX_MIPFILTER_LINEAR:
207 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
208 default:
209 case PIPE_TEX_MIPFILTER_NONE:
210 return V_03C000_SQ_TEX_Z_FILTER_NONE;
211 }
212 }
213
214 static unsigned r600_tex_compare(unsigned compare)
215 {
216 switch (compare) {
217 default:
218 case PIPE_FUNC_NEVER:
219 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
220 case PIPE_FUNC_LESS:
221 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
222 case PIPE_FUNC_EQUAL:
223 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
224 case PIPE_FUNC_LEQUAL:
225 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
226 case PIPE_FUNC_GREATER:
227 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
228 case PIPE_FUNC_NOTEQUAL:
229 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
230 case PIPE_FUNC_GEQUAL:
231 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
232 case PIPE_FUNC_ALWAYS:
233 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
234 }
235 }
236
237 static unsigned r600_tex_dim(unsigned dim)
238 {
239 switch (dim) {
240 default:
241 case PIPE_TEXTURE_1D:
242 return V_038000_SQ_TEX_DIM_1D;
243 case PIPE_TEXTURE_1D_ARRAY:
244 return V_038000_SQ_TEX_DIM_1D_ARRAY;
245 case PIPE_TEXTURE_2D:
246 case PIPE_TEXTURE_RECT:
247 return V_038000_SQ_TEX_DIM_2D;
248 case PIPE_TEXTURE_2D_ARRAY:
249 return V_038000_SQ_TEX_DIM_2D_ARRAY;
250 case PIPE_TEXTURE_3D:
251 return V_038000_SQ_TEX_DIM_3D;
252 case PIPE_TEXTURE_CUBE:
253 return V_038000_SQ_TEX_DIM_CUBEMAP;
254 }
255 }
256
257 static uint32_t r600_translate_dbformat(enum pipe_format format)
258 {
259 switch (format) {
260 case PIPE_FORMAT_Z16_UNORM:
261 return V_028010_DEPTH_16;
262 case PIPE_FORMAT_Z24X8_UNORM:
263 return V_028010_DEPTH_X8_24;
264 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
265 return V_028010_DEPTH_8_24;
266 case PIPE_FORMAT_Z32_FLOAT:
267 return V_028010_DEPTH_32_FLOAT;
268 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
269 return V_028010_DEPTH_X24_8_32_FLOAT;
270 default:
271 return ~0U;
272 }
273 }
274
275 static uint32_t r600_translate_colorswap(enum pipe_format format)
276 {
277 switch (format) {
278 /* 8-bit buffers. */
279 case PIPE_FORMAT_A8_UNORM:
280 case PIPE_FORMAT_A8_UINT:
281 case PIPE_FORMAT_A8_SINT:
282 case PIPE_FORMAT_R4A4_UNORM:
283 return V_0280A0_SWAP_ALT_REV;
284 case PIPE_FORMAT_I8_UNORM:
285 case PIPE_FORMAT_L8_UNORM:
286 case PIPE_FORMAT_I8_UINT:
287 case PIPE_FORMAT_I8_SINT:
288 case PIPE_FORMAT_L8_UINT:
289 case PIPE_FORMAT_L8_SINT:
290 case PIPE_FORMAT_L8_SRGB:
291 case PIPE_FORMAT_R8_UNORM:
292 case PIPE_FORMAT_R8_SNORM:
293 case PIPE_FORMAT_R8_UINT:
294 case PIPE_FORMAT_R8_SINT:
295 return V_0280A0_SWAP_STD;
296
297 case PIPE_FORMAT_L4A4_UNORM:
298 case PIPE_FORMAT_A4R4_UNORM:
299 return V_0280A0_SWAP_ALT;
300
301 /* 16-bit buffers. */
302 case PIPE_FORMAT_B5G6R5_UNORM:
303 return V_0280A0_SWAP_STD_REV;
304
305 case PIPE_FORMAT_B5G5R5A1_UNORM:
306 case PIPE_FORMAT_B5G5R5X1_UNORM:
307 return V_0280A0_SWAP_ALT;
308
309 case PIPE_FORMAT_B4G4R4A4_UNORM:
310 case PIPE_FORMAT_B4G4R4X4_UNORM:
311 return V_0280A0_SWAP_ALT;
312
313 case PIPE_FORMAT_Z16_UNORM:
314 return V_0280A0_SWAP_STD;
315
316 case PIPE_FORMAT_L8A8_UNORM:
317 case PIPE_FORMAT_L8A8_UINT:
318 case PIPE_FORMAT_L8A8_SINT:
319 case PIPE_FORMAT_L8A8_SRGB:
320 return V_0280A0_SWAP_ALT;
321 case PIPE_FORMAT_R8G8_UNORM:
322 case PIPE_FORMAT_R8G8_UINT:
323 case PIPE_FORMAT_R8G8_SINT:
324 return V_0280A0_SWAP_STD;
325
326 case PIPE_FORMAT_R16_UNORM:
327 case PIPE_FORMAT_R16_UINT:
328 case PIPE_FORMAT_R16_SINT:
329 case PIPE_FORMAT_R16_FLOAT:
330 return V_0280A0_SWAP_STD;
331
332 /* 32-bit buffers. */
333
334 case PIPE_FORMAT_A8B8G8R8_SRGB:
335 return V_0280A0_SWAP_STD_REV;
336 case PIPE_FORMAT_B8G8R8A8_SRGB:
337 return V_0280A0_SWAP_ALT;
338
339 case PIPE_FORMAT_B8G8R8A8_UNORM:
340 case PIPE_FORMAT_B8G8R8X8_UNORM:
341 return V_0280A0_SWAP_ALT;
342
343 case PIPE_FORMAT_A8R8G8B8_UNORM:
344 case PIPE_FORMAT_X8R8G8B8_UNORM:
345 return V_0280A0_SWAP_ALT_REV;
346 case PIPE_FORMAT_R8G8B8A8_SNORM:
347 case PIPE_FORMAT_R8G8B8A8_UNORM:
348 case PIPE_FORMAT_R8G8B8X8_UNORM:
349 case PIPE_FORMAT_R8G8B8A8_SSCALED:
350 case PIPE_FORMAT_R8G8B8A8_USCALED:
351 case PIPE_FORMAT_R8G8B8A8_SINT:
352 case PIPE_FORMAT_R8G8B8A8_UINT:
353 return V_0280A0_SWAP_STD;
354
355 case PIPE_FORMAT_A8B8G8R8_UNORM:
356 case PIPE_FORMAT_X8B8G8R8_UNORM:
357 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
358 return V_0280A0_SWAP_STD_REV;
359
360 case PIPE_FORMAT_Z24X8_UNORM:
361 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
362 return V_0280A0_SWAP_STD;
363
364 case PIPE_FORMAT_X8Z24_UNORM:
365 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
366 return V_0280A0_SWAP_STD;
367
368 case PIPE_FORMAT_R10G10B10A2_UNORM:
369 case PIPE_FORMAT_R10G10B10X2_SNORM:
370 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
371 return V_0280A0_SWAP_STD;
372
373 case PIPE_FORMAT_B10G10R10A2_UNORM:
374 case PIPE_FORMAT_B10G10R10A2_UINT:
375 return V_0280A0_SWAP_ALT;
376
377 case PIPE_FORMAT_R11G11B10_FLOAT:
378 case PIPE_FORMAT_R16G16_UNORM:
379 case PIPE_FORMAT_R16G16_FLOAT:
380 case PIPE_FORMAT_R16G16_UINT:
381 case PIPE_FORMAT_R16G16_SINT:
382 case PIPE_FORMAT_R32_UINT:
383 case PIPE_FORMAT_R32_SINT:
384 case PIPE_FORMAT_R32_FLOAT:
385 case PIPE_FORMAT_Z32_FLOAT:
386 return V_0280A0_SWAP_STD;
387
388 /* 64-bit buffers. */
389 case PIPE_FORMAT_R32G32_FLOAT:
390 case PIPE_FORMAT_R32G32_UINT:
391 case PIPE_FORMAT_R32G32_SINT:
392 case PIPE_FORMAT_R16G16B16A16_UNORM:
393 case PIPE_FORMAT_R16G16B16A16_SNORM:
394 case PIPE_FORMAT_R16G16B16A16_USCALED:
395 case PIPE_FORMAT_R16G16B16A16_SSCALED:
396 case PIPE_FORMAT_R16G16B16A16_UINT:
397 case PIPE_FORMAT_R16G16B16A16_SINT:
398 case PIPE_FORMAT_R16G16B16A16_FLOAT:
399 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
400
401 /* 128-bit buffers. */
402 case PIPE_FORMAT_R32G32B32A32_FLOAT:
403 case PIPE_FORMAT_R32G32B32A32_SNORM:
404 case PIPE_FORMAT_R32G32B32A32_UNORM:
405 case PIPE_FORMAT_R32G32B32A32_USCALED:
406 case PIPE_FORMAT_R32G32B32A32_SSCALED:
407 case PIPE_FORMAT_R32G32B32A32_SINT:
408 case PIPE_FORMAT_R32G32B32A32_UINT:
409 return V_0280A0_SWAP_STD;
410 default:
411 R600_ERR("unsupported colorswap format %d\n", format);
412 return ~0U;
413 }
414 return ~0U;
415 }
416
417 static uint32_t r600_translate_colorformat(enum pipe_format format)
418 {
419 switch (format) {
420 case PIPE_FORMAT_L4A4_UNORM:
421 case PIPE_FORMAT_R4A4_UNORM:
422 case PIPE_FORMAT_A4R4_UNORM:
423 return V_0280A0_COLOR_4_4;
424
425 /* 8-bit buffers. */
426 case PIPE_FORMAT_A8_UNORM:
427 case PIPE_FORMAT_A8_UINT:
428 case PIPE_FORMAT_A8_SINT:
429 case PIPE_FORMAT_I8_UNORM:
430 case PIPE_FORMAT_I8_UINT:
431 case PIPE_FORMAT_I8_SINT:
432 case PIPE_FORMAT_L8_UNORM:
433 case PIPE_FORMAT_L8_UINT:
434 case PIPE_FORMAT_L8_SINT:
435 case PIPE_FORMAT_L8_SRGB:
436 case PIPE_FORMAT_R8_UNORM:
437 case PIPE_FORMAT_R8_SNORM:
438 case PIPE_FORMAT_R8_UINT:
439 case PIPE_FORMAT_R8_SINT:
440 return V_0280A0_COLOR_8;
441
442 /* 16-bit buffers. */
443 case PIPE_FORMAT_B5G6R5_UNORM:
444 return V_0280A0_COLOR_5_6_5;
445
446 case PIPE_FORMAT_B5G5R5A1_UNORM:
447 case PIPE_FORMAT_B5G5R5X1_UNORM:
448 return V_0280A0_COLOR_1_5_5_5;
449
450 case PIPE_FORMAT_B4G4R4A4_UNORM:
451 case PIPE_FORMAT_B4G4R4X4_UNORM:
452 return V_0280A0_COLOR_4_4_4_4;
453
454 case PIPE_FORMAT_Z16_UNORM:
455 return V_0280A0_COLOR_16;
456
457 case PIPE_FORMAT_L8A8_UNORM:
458 case PIPE_FORMAT_L8A8_UINT:
459 case PIPE_FORMAT_L8A8_SINT:
460 case PIPE_FORMAT_L8A8_SRGB:
461 case PIPE_FORMAT_R8G8_UNORM:
462 case PIPE_FORMAT_R8G8_UINT:
463 case PIPE_FORMAT_R8G8_SINT:
464 return V_0280A0_COLOR_8_8;
465
466 case PIPE_FORMAT_R16_UNORM:
467 case PIPE_FORMAT_R16_UINT:
468 case PIPE_FORMAT_R16_SINT:
469 return V_0280A0_COLOR_16;
470
471 case PIPE_FORMAT_R16_FLOAT:
472 return V_0280A0_COLOR_16_FLOAT;
473
474 /* 32-bit buffers. */
475 case PIPE_FORMAT_A8B8G8R8_SRGB:
476 case PIPE_FORMAT_A8B8G8R8_UNORM:
477 case PIPE_FORMAT_A8R8G8B8_UNORM:
478 case PIPE_FORMAT_B8G8R8A8_SRGB:
479 case PIPE_FORMAT_B8G8R8A8_UNORM:
480 case PIPE_FORMAT_B8G8R8X8_UNORM:
481 case PIPE_FORMAT_R8G8B8A8_SNORM:
482 case PIPE_FORMAT_R8G8B8A8_UNORM:
483 case PIPE_FORMAT_R8G8B8A8_SSCALED:
484 case PIPE_FORMAT_R8G8B8A8_USCALED:
485 case PIPE_FORMAT_R8G8B8X8_UNORM:
486 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
487 case PIPE_FORMAT_X8B8G8R8_UNORM:
488 case PIPE_FORMAT_X8R8G8B8_UNORM:
489 case PIPE_FORMAT_R8G8B8_UNORM:
490 case PIPE_FORMAT_R8G8B8A8_SINT:
491 case PIPE_FORMAT_R8G8B8A8_UINT:
492 return V_0280A0_COLOR_8_8_8_8;
493
494 case PIPE_FORMAT_R10G10B10A2_UNORM:
495 case PIPE_FORMAT_R10G10B10X2_SNORM:
496 case PIPE_FORMAT_B10G10R10A2_UNORM:
497 case PIPE_FORMAT_B10G10R10A2_UINT:
498 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
499 return V_0280A0_COLOR_2_10_10_10;
500
501 case PIPE_FORMAT_Z24X8_UNORM:
502 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
503 return V_0280A0_COLOR_8_24;
504
505 case PIPE_FORMAT_X8Z24_UNORM:
506 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
507 return V_0280A0_COLOR_24_8;
508
509 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
510 return V_0280A0_COLOR_X24_8_32_FLOAT;
511
512 case PIPE_FORMAT_R32_UINT:
513 case PIPE_FORMAT_R32_SINT:
514 return V_0280A0_COLOR_32;
515
516 case PIPE_FORMAT_R32_FLOAT:
517 case PIPE_FORMAT_Z32_FLOAT:
518 return V_0280A0_COLOR_32_FLOAT;
519
520 case PIPE_FORMAT_R16G16_FLOAT:
521 return V_0280A0_COLOR_16_16_FLOAT;
522
523 case PIPE_FORMAT_R16G16_SSCALED:
524 case PIPE_FORMAT_R16G16_UNORM:
525 case PIPE_FORMAT_R16G16_UINT:
526 case PIPE_FORMAT_R16G16_SINT:
527 return V_0280A0_COLOR_16_16;
528
529 case PIPE_FORMAT_R11G11B10_FLOAT:
530 return V_0280A0_COLOR_10_11_11_FLOAT;
531
532 /* 64-bit buffers. */
533 case PIPE_FORMAT_R16G16B16_USCALED:
534 case PIPE_FORMAT_R16G16B16A16_USCALED:
535 case PIPE_FORMAT_R16G16B16_SSCALED:
536 case PIPE_FORMAT_R16G16B16A16_UINT:
537 case PIPE_FORMAT_R16G16B16A16_SINT:
538 case PIPE_FORMAT_R16G16B16A16_SSCALED:
539 case PIPE_FORMAT_R16G16B16A16_UNORM:
540 case PIPE_FORMAT_R16G16B16A16_SNORM:
541 return V_0280A0_COLOR_16_16_16_16;
542
543 case PIPE_FORMAT_R16G16B16_FLOAT:
544 case PIPE_FORMAT_R16G16B16A16_FLOAT:
545 return V_0280A0_COLOR_16_16_16_16_FLOAT;
546
547 case PIPE_FORMAT_R32G32_FLOAT:
548 return V_0280A0_COLOR_32_32_FLOAT;
549
550 case PIPE_FORMAT_R32G32_USCALED:
551 case PIPE_FORMAT_R32G32_SSCALED:
552 case PIPE_FORMAT_R32G32_SINT:
553 case PIPE_FORMAT_R32G32_UINT:
554 return V_0280A0_COLOR_32_32;
555
556 /* 96-bit buffers. */
557 case PIPE_FORMAT_R32G32B32_FLOAT:
558 return V_0280A0_COLOR_32_32_32_FLOAT;
559
560 /* 128-bit buffers. */
561 case PIPE_FORMAT_R32G32B32A32_FLOAT:
562 return V_0280A0_COLOR_32_32_32_32_FLOAT;
563 case PIPE_FORMAT_R32G32B32A32_SNORM:
564 case PIPE_FORMAT_R32G32B32A32_UNORM:
565 case PIPE_FORMAT_R32G32B32A32_SSCALED:
566 case PIPE_FORMAT_R32G32B32A32_USCALED:
567 case PIPE_FORMAT_R32G32B32A32_SINT:
568 case PIPE_FORMAT_R32G32B32A32_UINT:
569 return V_0280A0_COLOR_32_32_32_32;
570
571 /* YUV buffers. */
572 case PIPE_FORMAT_UYVY:
573 case PIPE_FORMAT_YUYV:
574 default:
575 return ~0U; /* Unsupported. */
576 }
577 }
578
579 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
580 {
581 if (R600_BIG_ENDIAN) {
582 switch(colorformat) {
583 case V_0280A0_COLOR_4_4:
584 return ENDIAN_NONE;
585
586 /* 8-bit buffers. */
587 case V_0280A0_COLOR_8:
588 return ENDIAN_NONE;
589
590 /* 16-bit buffers. */
591 case V_0280A0_COLOR_5_6_5:
592 case V_0280A0_COLOR_1_5_5_5:
593 case V_0280A0_COLOR_4_4_4_4:
594 case V_0280A0_COLOR_16:
595 case V_0280A0_COLOR_8_8:
596 return ENDIAN_8IN16;
597
598 /* 32-bit buffers. */
599 case V_0280A0_COLOR_8_8_8_8:
600 case V_0280A0_COLOR_2_10_10_10:
601 case V_0280A0_COLOR_8_24:
602 case V_0280A0_COLOR_24_8:
603 case V_0280A0_COLOR_32_FLOAT:
604 case V_0280A0_COLOR_16_16_FLOAT:
605 case V_0280A0_COLOR_16_16:
606 return ENDIAN_8IN32;
607
608 /* 64-bit buffers. */
609 case V_0280A0_COLOR_16_16_16_16:
610 case V_0280A0_COLOR_16_16_16_16_FLOAT:
611 return ENDIAN_8IN16;
612
613 case V_0280A0_COLOR_32_32_FLOAT:
614 case V_0280A0_COLOR_32_32:
615 case V_0280A0_COLOR_X24_8_32_FLOAT:
616 return ENDIAN_8IN32;
617
618 /* 128-bit buffers. */
619 case V_0280A0_COLOR_32_32_32_FLOAT:
620 case V_0280A0_COLOR_32_32_32_32_FLOAT:
621 case V_0280A0_COLOR_32_32_32_32:
622 return ENDIAN_8IN32;
623 default:
624 return ENDIAN_NONE; /* Unsupported. */
625 }
626 } else {
627 return ENDIAN_NONE;
628 }
629 }
630
631 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
632 {
633 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
634 }
635
636 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
637 {
638 return r600_translate_colorformat(format) != ~0U &&
639 r600_translate_colorswap(format) != ~0U;
640 }
641
642 static bool r600_is_zs_format_supported(enum pipe_format format)
643 {
644 return r600_translate_dbformat(format) != ~0U;
645 }
646
647 boolean r600_is_format_supported(struct pipe_screen *screen,
648 enum pipe_format format,
649 enum pipe_texture_target target,
650 unsigned sample_count,
651 unsigned usage)
652 {
653 unsigned retval = 0;
654
655 if (target >= PIPE_MAX_TEXTURE_TYPES) {
656 R600_ERR("r600: unsupported texture type %d\n", target);
657 return FALSE;
658 }
659
660 if (!util_format_is_supported(format, usage))
661 return FALSE;
662
663 /* Multisample */
664 if (sample_count > 1)
665 return FALSE;
666
667 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
668 r600_is_sampler_format_supported(screen, format)) {
669 retval |= PIPE_BIND_SAMPLER_VIEW;
670 }
671
672 if ((usage & (PIPE_BIND_RENDER_TARGET |
673 PIPE_BIND_DISPLAY_TARGET |
674 PIPE_BIND_SCANOUT |
675 PIPE_BIND_SHARED)) &&
676 r600_is_colorbuffer_format_supported(format)) {
677 retval |= usage &
678 (PIPE_BIND_RENDER_TARGET |
679 PIPE_BIND_DISPLAY_TARGET |
680 PIPE_BIND_SCANOUT |
681 PIPE_BIND_SHARED);
682 }
683
684 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
685 r600_is_zs_format_supported(format)) {
686 retval |= PIPE_BIND_DEPTH_STENCIL;
687 }
688
689 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
690 r600_is_vertex_format_supported(format)) {
691 retval |= PIPE_BIND_VERTEX_BUFFER;
692 }
693
694 if (usage & PIPE_BIND_TRANSFER_READ)
695 retval |= PIPE_BIND_TRANSFER_READ;
696 if (usage & PIPE_BIND_TRANSFER_WRITE)
697 retval |= PIPE_BIND_TRANSFER_WRITE;
698
699 return retval == usage;
700 }
701
702 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
703 {
704 struct r600_pipe_state state;
705
706 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
707 state.nregs = 0;
708 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
709 float offset_units = rctx->rasterizer->offset_units;
710 unsigned offset_db_fmt_cntl = 0, depth;
711
712 switch (rctx->framebuffer.zsbuf->texture->format) {
713 case PIPE_FORMAT_Z24X8_UNORM:
714 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
715 depth = -24;
716 offset_units *= 2.0f;
717 break;
718 case PIPE_FORMAT_Z32_FLOAT:
719 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
720 depth = -23;
721 offset_units *= 1.0f;
722 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
723 break;
724 case PIPE_FORMAT_Z16_UNORM:
725 depth = -16;
726 offset_units *= 4.0f;
727 break;
728 default:
729 return;
730 }
731 /* FIXME some of those reg can be computed with cso */
732 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
733 r600_pipe_state_add_reg(&state,
734 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
735 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
736 r600_pipe_state_add_reg(&state,
737 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
738 fui(offset_units), 0xFFFFFFFF, NULL, 0);
739 r600_pipe_state_add_reg(&state,
740 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
741 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
742 r600_pipe_state_add_reg(&state,
743 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
744 fui(offset_units), 0xFFFFFFFF, NULL, 0);
745 r600_pipe_state_add_reg(&state,
746 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
747 offset_db_fmt_cntl, 0xFFFFFFFF, NULL, 0);
748 r600_context_pipe_state_set(&rctx->ctx, &state);
749 }
750 }
751
752 static void r600_set_blend_color(struct pipe_context *ctx,
753 const struct pipe_blend_color *state)
754 {
755 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
756 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
757
758 if (rstate == NULL)
759 return;
760
761 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
762 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL, 0);
763 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL, 0);
764 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL, 0);
765 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL, 0);
766 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
767 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
768 r600_context_pipe_state_set(&rctx->ctx, rstate);
769 }
770
771 static void *r600_create_blend_state(struct pipe_context *ctx,
772 const struct pipe_blend_state *state)
773 {
774 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
775 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
776 struct r600_pipe_state *rstate;
777 u32 color_control = 0, target_mask;
778
779 if (blend == NULL) {
780 return NULL;
781 }
782 rstate = &blend->rstate;
783
784 rstate->id = R600_PIPE_STATE_BLEND;
785
786 target_mask = 0;
787
788 /* R600 does not support per-MRT blends */
789 if (rctx->family > CHIP_R600)
790 color_control |= S_028808_PER_MRT_BLEND(1);
791 if (state->logicop_enable) {
792 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
793 } else {
794 color_control |= (0xcc << 16);
795 }
796 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
797 if (state->independent_blend_enable) {
798 for (int i = 0; i < 8; i++) {
799 if (state->rt[i].blend_enable) {
800 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
801 }
802 target_mask |= (state->rt[i].colormask << (4 * i));
803 }
804 } else {
805 for (int i = 0; i < 8; i++) {
806 if (state->rt[0].blend_enable) {
807 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
808 }
809 target_mask |= (state->rt[0].colormask << (4 * i));
810 }
811 }
812 blend->cb_target_mask = target_mask;
813 /* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */
814 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
815 color_control, 0xFFFFFFFD, NULL, 0);
816
817 for (int i = 0; i < 8; i++) {
818 /* state->rt entries > 0 only written if independent blending */
819 const int j = state->independent_blend_enable ? i : 0;
820
821 unsigned eqRGB = state->rt[j].rgb_func;
822 unsigned srcRGB = state->rt[j].rgb_src_factor;
823 unsigned dstRGB = state->rt[j].rgb_dst_factor;
824
825 unsigned eqA = state->rt[j].alpha_func;
826 unsigned srcA = state->rt[j].alpha_src_factor;
827 unsigned dstA = state->rt[j].alpha_dst_factor;
828 uint32_t bc = 0;
829
830 if (!state->rt[j].blend_enable)
831 continue;
832
833 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
834 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
835 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
836
837 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
838 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
839 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
840 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
841 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
842 }
843
844 /* R600 does not support per-MRT blends */
845 if (rctx->family > CHIP_R600)
846 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL, 0);
847 if (i == 0)
848 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL, 0);
849 }
850 return rstate;
851 }
852
853 static void *r600_create_dsa_state(struct pipe_context *ctx,
854 const struct pipe_depth_stencil_alpha_state *state)
855 {
856 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
857 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
858 unsigned db_depth_control, alpha_test_control, alpha_ref;
859 unsigned db_render_override, db_render_control;
860 struct r600_pipe_state *rstate;
861
862 if (dsa == NULL) {
863 return NULL;
864 }
865
866 dsa->valuemask[0] = state->stencil[0].valuemask;
867 dsa->valuemask[1] = state->stencil[1].valuemask;
868 dsa->writemask[0] = state->stencil[0].writemask;
869 dsa->writemask[1] = state->stencil[1].writemask;
870
871 rstate = &dsa->rstate;
872
873 rstate->id = R600_PIPE_STATE_DSA;
874 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
875 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
876 S_028800_ZFUNC(state->depth.func);
877
878 /* stencil */
879 if (state->stencil[0].enabled) {
880 db_depth_control |= S_028800_STENCIL_ENABLE(1);
881 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
882 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
883 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
884 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
885
886 if (state->stencil[1].enabled) {
887 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
888 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
889 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
890 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
891 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
892 }
893 }
894
895 /* alpha */
896 alpha_test_control = 0;
897 alpha_ref = 0;
898 if (state->alpha.enabled) {
899 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
900 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
901 alpha_ref = fui(state->alpha.ref_value);
902 }
903 dsa->alpha_ref = alpha_ref;
904
905 /* misc */
906 db_render_control = 0;
907 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
908 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
909 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
910 /* TODO db_render_override depends on query */
911 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL, 0);
912 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL, 0);
913 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL, 0);
914 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL, 0);
915 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL, 0);
916 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
917 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL, 0);
918 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL, 0);
919 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL, 0);
920 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL, 0);
921 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL, 0);
922 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL, 0);
923
924 return rstate;
925 }
926
927 static void *r600_create_rs_state(struct pipe_context *ctx,
928 const struct pipe_rasterizer_state *state)
929 {
930 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
931 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
932 struct r600_pipe_state *rstate;
933 unsigned tmp;
934 unsigned prov_vtx = 1, polygon_dual_mode;
935 unsigned clip_rule;
936 unsigned sc_mode_cntl;
937 float psize_min, psize_max;
938
939 if (rs == NULL) {
940 return NULL;
941 }
942
943 rstate = &rs->rstate;
944 rs->flatshade = state->flatshade;
945 rs->sprite_coord_enable = state->sprite_coord_enable;
946 rs->two_side = state->light_twoside;
947 rs->clip_plane_enable = state->clip_plane_enable;
948
949 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
950 /* offset */
951 rs->offset_units = state->offset_units;
952 rs->offset_scale = state->offset_scale * 12.0f;
953
954 rstate->id = R600_PIPE_STATE_RASTERIZER;
955 if (state->flatshade_first)
956 prov_vtx = 0;
957 tmp = S_0286D4_FLAT_SHADE_ENA(1);
958 if (state->sprite_coord_enable) {
959 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
960 S_0286D4_PNT_SPRITE_OVRD_X(2) |
961 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
962 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
963 S_0286D4_PNT_SPRITE_OVRD_W(1);
964 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
965 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
966 }
967 }
968 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL, 0);
969
970 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
971 state->fill_back != PIPE_POLYGON_MODE_FILL);
972 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
973 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
974 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
975 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
976 S_028814_FACE(!state->front_ccw) |
977 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
978 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
979 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
980 S_028814_POLY_MODE(polygon_dual_mode) |
981 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
982 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL, 0);
983 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
984 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex),
985 S_02881C_USE_VTX_POINT_SIZE(1), NULL, 0);
986 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
987 /* point size 12.4 fixed point */
988 tmp = (unsigned)(state->point_size * 8.0);
989 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
990
991 psize_min = util_get_min_point_size(state);
992 psize_max = 8192;
993 /* Divide by two, because 0.5 = 1 pixel. */
994 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
995 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
996 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
997 0xFFFFFFFF, NULL, 0);
998
999 tmp = (unsigned)state->line_width * 8;
1000 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
1001
1002 if (state->line_stipple_enable) {
1003 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE,
1004 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
1005 S_028A0C_REPEAT_COUNT(state->line_stipple_factor),
1006 0x9FFFFFFF, NULL, 0);
1007 }
1008
1009 if (rctx->chip_class >= R700)
1010 sc_mode_cntl = 0x514002;
1011 else
1012 sc_mode_cntl = 0x4102;
1013 sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
1014
1015 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl,
1016 0xFFFFFFFF, NULL, 0);
1017 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1018 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
1019
1020 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
1021 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
1022 0xFFFFFFFF, NULL, 0);
1023
1024 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1025 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1026 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1027 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1028 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), 0xFFFFFFFF, NULL, 0);
1029 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL, 0);
1030 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1031 S_028810_PS_UCP_MODE(3) | S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
1032 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
1033 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1),
1034 ~(C_028810_PS_UCP_MODE & C_028810_ZCLIP_NEAR_DISABLE &
1035 C_028810_ZCLIP_FAR_DISABLE &
1036 C_028810_DX_LINEAR_ATTR_CLIP_ENA), NULL, 0);
1037 return rstate;
1038 }
1039
1040 static void *r600_create_sampler_state(struct pipe_context *ctx,
1041 const struct pipe_sampler_state *state)
1042 {
1043 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
1044 struct r600_pipe_state *rstate;
1045 union util_color uc;
1046 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
1047
1048 if (ss == NULL) {
1049 return NULL;
1050 }
1051
1052 ss->seamless_cube_map = state->seamless_cube_map;
1053 rstate = &ss->rstate;
1054 rstate->id = R600_PIPE_STATE_SAMPLER;
1055 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1056 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
1057 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1058 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1059 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1060 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1061 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1062 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1063 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1064 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1065 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL, 0);
1066 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
1067 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1068 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1069 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL, 0);
1070 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL, 0);
1071 if (uc.ui) {
1072 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), 0xFFFFFFFF, NULL, 0);
1073 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), 0xFFFFFFFF, NULL, 0);
1074 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), 0xFFFFFFFF, NULL, 0);
1075 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), 0xFFFFFFFF, NULL, 0);
1076 }
1077 return rstate;
1078 }
1079
1080 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1081 struct pipe_resource *texture,
1082 const struct pipe_sampler_view *state)
1083 {
1084 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1085 struct r600_pipe_resource_state *rstate;
1086 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1087 unsigned format, endian;
1088 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1089 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1090 unsigned width, height, depth, offset_level, last_level;
1091
1092 if (view == NULL)
1093 return NULL;
1094 rstate = &view->state;
1095
1096 /* initialize base object */
1097 view->base = *state;
1098 view->base.texture = NULL;
1099 pipe_reference(NULL, &texture->reference);
1100 view->base.texture = texture;
1101 view->base.reference.count = 1;
1102 view->base.context = ctx;
1103
1104 swizzle[0] = state->swizzle_r;
1105 swizzle[1] = state->swizzle_g;
1106 swizzle[2] = state->swizzle_b;
1107 swizzle[3] = state->swizzle_a;
1108
1109 format = r600_translate_texformat(ctx->screen, state->format,
1110 swizzle,
1111 &word4, &yuv_format);
1112 if (format == ~0) {
1113 format = 0;
1114 }
1115
1116 if (tmp->depth && !tmp->is_flushing_texture) {
1117 r600_texture_depth_flush(ctx, texture, TRUE);
1118 tmp = tmp->flushed_depth_texture;
1119 }
1120
1121 endian = r600_colorformat_endian_swap(format);
1122
1123 offset_level = state->u.tex.first_level;
1124 last_level = state->u.tex.last_level - offset_level;
1125 width = u_minify(texture->width0, offset_level);
1126 height = u_minify(texture->height0, offset_level);
1127 depth = u_minify(texture->depth0, offset_level);
1128
1129 pitch = align(tmp->pitch_in_blocks[offset_level] *
1130 util_format_get_blockwidth(state->format), 8);
1131 array_mode = tmp->array_mode[offset_level];
1132 tile_type = tmp->tile_type;
1133
1134 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1135 height = 1;
1136 depth = texture->array_size;
1137 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1138 depth = texture->array_size;
1139 }
1140
1141 rstate->bo[0] = &tmp->resource;
1142 rstate->bo[1] = &tmp->resource;
1143 rstate->bo_usage[0] = RADEON_USAGE_READ;
1144 rstate->bo_usage[1] = RADEON_USAGE_READ;
1145
1146 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1147 S_038000_TILE_MODE(array_mode) |
1148 S_038000_TILE_TYPE(tile_type) |
1149 S_038000_PITCH((pitch / 8) - 1) |
1150 S_038000_TEX_WIDTH(width - 1));
1151 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1152 S_038004_TEX_DEPTH(depth - 1) |
1153 S_038004_DATA_FORMAT(format));
1154 rstate->val[2] = tmp->offset[offset_level] >> 8;
1155 rstate->val[3] = tmp->offset[offset_level+1] >> 8;
1156 rstate->val[4] = (word4 |
1157 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1158 S_038010_REQUEST_SIZE(1) |
1159 S_038010_ENDIAN_SWAP(endian) |
1160 S_038010_BASE_LEVEL(0));
1161 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1162 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1163 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1164 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1165 S_038018_MAX_ANISO(4 /* max 16 samples */));
1166
1167 return &view->base;
1168 }
1169
1170 static void r600_set_sampler_views(struct r600_pipe_context *rctx,
1171 struct r600_textures_info *dst,
1172 unsigned count,
1173 struct pipe_sampler_view **views,
1174 void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned))
1175 {
1176 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
1177 unsigned i;
1178
1179 for (i = 0; i < count; i++) {
1180 if (rviews[i]) {
1181 if (((struct r600_resource_texture *)rviews[i]->base.texture)->depth)
1182 rctx->have_depth_texture = true;
1183
1184 /* Changing from array to non-arrays textures and vice versa requires updating TEX_ARRAY_OVERRIDE. */
1185 if ((rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1186 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i])
1187 dst->samplers_dirty = true;
1188
1189 set_resource(&rctx->ctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS);
1190 } else {
1191 set_resource(&rctx->ctx, NULL, i + R600_MAX_CONST_BUFFERS);
1192 }
1193
1194 pipe_sampler_view_reference(
1195 (struct pipe_sampler_view **)&dst->views[i],
1196 views[i]);
1197 }
1198
1199 for (i = count; i < dst->n_views; i++) {
1200 if (dst->views[i]) {
1201 set_resource(&rctx->ctx, NULL, i + R600_MAX_CONST_BUFFERS);
1202 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL);
1203 }
1204 }
1205
1206 dst->n_views = count;
1207 }
1208
1209 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1210 struct pipe_sampler_view **views)
1211 {
1212 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1213 r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views,
1214 r600_context_pipe_state_set_vs_resource);
1215 }
1216
1217 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1218 struct pipe_sampler_view **views)
1219 {
1220 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1221 r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views,
1222 r600_context_pipe_state_set_ps_resource);
1223 }
1224
1225 static void r600_set_seamless_cubemap(struct r600_pipe_context *rctx, boolean enable)
1226 {
1227 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1228 if (rstate == NULL)
1229 return;
1230
1231 rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP;
1232 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1233 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)),
1234 1, NULL, 0);
1235
1236 free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]);
1237 rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate;
1238 r600_context_pipe_state_set(&rctx->ctx, rstate);
1239 }
1240
1241 static void r600_bind_samplers(struct r600_pipe_context *rctx,
1242 struct r600_textures_info *dst,
1243 unsigned count, void **states)
1244 {
1245 memcpy(dst->samplers, states, sizeof(void*) * count);
1246 dst->n_samplers = count;
1247 dst->samplers_dirty = true;
1248 }
1249
1250 static void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
1251 {
1252 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1253 r600_bind_samplers(rctx, &rctx->vs_samplers, count, states);
1254 }
1255
1256 static void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
1257 {
1258 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1259 r600_bind_samplers(rctx, &rctx->ps_samplers, count, states);
1260 }
1261
1262 static void r600_update_samplers(struct r600_pipe_context *rctx,
1263 struct r600_textures_info *tex,
1264 void (*set_sampler)(struct r600_context*, struct r600_pipe_state*, unsigned))
1265 {
1266 unsigned i;
1267
1268 if (tex->samplers_dirty) {
1269 int seamless = -1;
1270 for (i = 0; i < tex->n_samplers; i++) {
1271 if (!tex->samplers[i])
1272 continue;
1273
1274 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1275 * filtering between layers.
1276 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */
1277 if (tex->views[i]) {
1278 if (tex->views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1279 tex->views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1280 tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1281 tex->is_array_sampler[i] = true;
1282 } else {
1283 tex->samplers[i]->rstate.regs[0].value &= C_03C000_TEX_ARRAY_OVERRIDE;
1284 tex->is_array_sampler[i] = false;
1285 }
1286 }
1287
1288 set_sampler(&rctx->ctx, &tex->samplers[i]->rstate, i);
1289
1290 if (tex->samplers[i])
1291 seamless = tex->samplers[i]->seamless_cube_map;
1292 }
1293
1294 if (seamless != -1)
1295 r600_set_seamless_cubemap(rctx, seamless);
1296
1297 tex->samplers_dirty = false;
1298 }
1299 }
1300
1301 void r600_update_sampler_states(struct r600_pipe_context *rctx)
1302 {
1303 r600_update_samplers(rctx, &rctx->vs_samplers,
1304 r600_context_pipe_state_set_vs_sampler);
1305 r600_update_samplers(rctx, &rctx->ps_samplers,
1306 r600_context_pipe_state_set_ps_sampler);
1307 }
1308
1309 static void r600_set_clip_state(struct pipe_context *ctx,
1310 const struct pipe_clip_state *state)
1311 {
1312 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1313 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1314 struct pipe_resource * cbuf;
1315
1316 if (rstate == NULL)
1317 return;
1318
1319 rctx->clip = *state;
1320 rstate->id = R600_PIPE_STATE_CLIP;
1321 for (int i = 0; i < 6; i++) {
1322 r600_pipe_state_add_reg(rstate,
1323 R_028E20_PA_CL_UCP0_X + i * 16,
1324 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL, 0);
1325 r600_pipe_state_add_reg(rstate,
1326 R_028E24_PA_CL_UCP0_Y + i * 16,
1327 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL, 0);
1328 r600_pipe_state_add_reg(rstate,
1329 R_028E28_PA_CL_UCP0_Z + i * 16,
1330 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL, 0);
1331 r600_pipe_state_add_reg(rstate,
1332 R_028E2C_PA_CL_UCP0_W + i * 16,
1333 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL, 0);
1334 }
1335
1336 free(rctx->states[R600_PIPE_STATE_CLIP]);
1337 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1338 r600_context_pipe_state_set(&rctx->ctx, rstate);
1339
1340 cbuf = pipe_user_buffer_create(ctx->screen,
1341 state->ucp,
1342 4*4*8, /* 8*4 floats */
1343 PIPE_BIND_CONSTANT_BUFFER);
1344 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
1345 pipe_resource_reference(&cbuf, NULL);
1346 }
1347
1348 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1349 const struct pipe_poly_stipple *state)
1350 {
1351 }
1352
1353 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1354 {
1355 }
1356
1357 static void r600_set_scissor_state(struct pipe_context *ctx,
1358 const struct pipe_scissor_state *state)
1359 {
1360 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1361 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1362 u32 tl, br;
1363
1364 if (rstate == NULL)
1365 return;
1366
1367 rstate->id = R600_PIPE_STATE_SCISSOR;
1368 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1369 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1370 r600_pipe_state_add_reg(rstate,
1371 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1372 0xFFFFFFFF, NULL, 0);
1373 r600_pipe_state_add_reg(rstate,
1374 R_028214_PA_SC_CLIPRECT_0_BR, br,
1375 0xFFFFFFFF, NULL, 0);
1376 r600_pipe_state_add_reg(rstate,
1377 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1378 0xFFFFFFFF, NULL, 0);
1379 r600_pipe_state_add_reg(rstate,
1380 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1381 0xFFFFFFFF, NULL, 0);
1382 r600_pipe_state_add_reg(rstate,
1383 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1384 0xFFFFFFFF, NULL, 0);
1385 r600_pipe_state_add_reg(rstate,
1386 R_028224_PA_SC_CLIPRECT_2_BR, br,
1387 0xFFFFFFFF, NULL, 0);
1388 r600_pipe_state_add_reg(rstate,
1389 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1390 0xFFFFFFFF, NULL, 0);
1391 r600_pipe_state_add_reg(rstate,
1392 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1393 0xFFFFFFFF, NULL, 0);
1394
1395 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1396 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1397 r600_context_pipe_state_set(&rctx->ctx, rstate);
1398 }
1399
1400 static void r600_set_viewport_state(struct pipe_context *ctx,
1401 const struct pipe_viewport_state *state)
1402 {
1403 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1404 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1405
1406 if (rstate == NULL)
1407 return;
1408
1409 rctx->viewport = *state;
1410 rstate->id = R600_PIPE_STATE_VIEWPORT;
1411 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
1412 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1413 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL, 0);
1414 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL, 0);
1415 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL, 0);
1416 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL, 0);
1417 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL, 0);
1418 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL, 0);
1419 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL, 0);
1420
1421 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1422 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1423 r600_context_pipe_state_set(&rctx->ctx, rstate);
1424 }
1425
1426 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1427 const struct pipe_framebuffer_state *state, int cb)
1428 {
1429 struct r600_resource_texture *rtex;
1430 struct r600_surface *surf;
1431 unsigned level = state->cbufs[cb]->u.tex.level;
1432 unsigned pitch, slice;
1433 unsigned color_info;
1434 unsigned format, swap, ntype, endian;
1435 unsigned offset;
1436 const struct util_format_description *desc;
1437 int i;
1438 unsigned blend_bypass = 0, blend_clamp = 1;
1439
1440 surf = (struct r600_surface *)state->cbufs[cb];
1441 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1442
1443 if (rtex->depth)
1444 rctx->have_depth_fb = TRUE;
1445
1446 if (rtex->depth && !rtex->is_flushing_texture) {
1447 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1448 rtex = rtex->flushed_depth_texture;
1449 }
1450
1451 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1452 offset = r600_texture_get_offset(rtex,
1453 level, state->cbufs[cb]->u.tex.first_layer);
1454 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1455 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1456 desc = util_format_description(surf->base.format);
1457
1458 for (i = 0; i < 4; i++) {
1459 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1460 break;
1461 }
1462 }
1463
1464 ntype = V_0280A0_NUMBER_UNORM;
1465 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1466 ntype = V_0280A0_NUMBER_SRGB;
1467 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1468 if (desc->channel[i].normalized)
1469 ntype = V_0280A0_NUMBER_SNORM;
1470 else if (desc->channel[i].pure_integer)
1471 ntype = V_0280A0_NUMBER_SINT;
1472 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1473 if (desc->channel[i].normalized)
1474 ntype = V_0280A0_NUMBER_UNORM;
1475 else if (desc->channel[i].pure_integer)
1476 ntype = V_0280A0_NUMBER_UINT;
1477 }
1478
1479 format = r600_translate_colorformat(surf->base.format);
1480 swap = r600_translate_colorswap(surf->base.format);
1481 if(rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1482 endian = ENDIAN_NONE;
1483 } else {
1484 endian = r600_colorformat_endian_swap(format);
1485 }
1486
1487 /* set blend bypass according to docs if SINT/UINT or
1488 8/24 COLOR variants */
1489 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1490 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1491 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1492 blend_clamp = 0;
1493 blend_bypass = 1;
1494 }
1495
1496 color_info = S_0280A0_FORMAT(format) |
1497 S_0280A0_COMP_SWAP(swap) |
1498 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
1499 S_0280A0_BLEND_BYPASS(blend_bypass) |
1500 S_0280A0_BLEND_CLAMP(blend_clamp) |
1501 S_0280A0_NUMBER_TYPE(ntype) |
1502 S_0280A0_ENDIAN(endian);
1503
1504 /* EXPORT_NORM is an optimzation that can be enabled for better
1505 * performance in certain cases
1506 */
1507 if (rctx->chip_class == R600) {
1508 /* EXPORT_NORM can be enabled if:
1509 * - 11-bit or smaller UNORM/SNORM/SRGB
1510 * - BLEND_CLAMP is enabled
1511 * - BLEND_FLOAT32 is disabled
1512 */
1513 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1514 (desc->channel[i].size < 12 &&
1515 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1516 ntype != V_0280A0_NUMBER_UINT &&
1517 ntype != V_0280A0_NUMBER_SINT) &&
1518 G_0280A0_BLEND_CLAMP(color_info) &&
1519 !G_0280A0_BLEND_FLOAT32(color_info))
1520 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1521 } else {
1522 /* EXPORT_NORM can be enabled if:
1523 * - 11-bit or smaller UNORM/SNORM/SRGB
1524 * - 16-bit or smaller FLOAT
1525 */
1526 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1527 ((desc->channel[i].size < 12 &&
1528 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1529 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1530 (desc->channel[i].size < 17 &&
1531 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)))
1532 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1533 }
1534
1535 r600_pipe_state_add_reg(rstate,
1536 R_028040_CB_COLOR0_BASE + cb * 4,
1537 offset >> 8, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1538 r600_pipe_state_add_reg(rstate,
1539 R_0280A0_CB_COLOR0_INFO + cb * 4,
1540 color_info, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1541 r600_pipe_state_add_reg(rstate,
1542 R_028060_CB_COLOR0_SIZE + cb * 4,
1543 S_028060_PITCH_TILE_MAX(pitch) |
1544 S_028060_SLICE_TILE_MAX(slice),
1545 0xFFFFFFFF, NULL, 0);
1546 r600_pipe_state_add_reg(rstate,
1547 R_028080_CB_COLOR0_VIEW + cb * 4,
1548 0x00000000, 0xFFFFFFFF, NULL, 0);
1549 r600_pipe_state_add_reg(rstate,
1550 R_0280E0_CB_COLOR0_FRAG + cb * 4,
1551 0, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1552 r600_pipe_state_add_reg(rstate,
1553 R_0280C0_CB_COLOR0_TILE + cb * 4,
1554 0, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1555 r600_pipe_state_add_reg(rstate,
1556 R_028100_CB_COLOR0_MASK + cb * 4,
1557 0x00000000, 0xFFFFFFFF, NULL, 0);
1558 }
1559
1560 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1561 const struct pipe_framebuffer_state *state)
1562 {
1563 struct r600_resource_texture *rtex;
1564 struct r600_surface *surf;
1565 unsigned level, pitch, slice, format, offset, array_mode;
1566
1567 if (state->zsbuf == NULL)
1568 return;
1569
1570 level = state->zsbuf->u.tex.level;
1571
1572 surf = (struct r600_surface *)state->zsbuf;
1573 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1574
1575 /* XXX remove this once tiling is properly supported */
1576 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1577 V_0280A0_ARRAY_1D_TILED_THIN1;
1578
1579 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1580 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1581 level, state->zsbuf->u.tex.first_layer);
1582 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1583 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1584 format = r600_translate_dbformat(state->zsbuf->texture->format);
1585
1586 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1587 offset >> 8, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1588 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1589 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1590 0xFFFFFFFF, NULL, 0);
1591 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL, 0);
1592 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1593 S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format),
1594 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1595 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1596 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL, 0);
1597 }
1598
1599 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1600 const struct pipe_framebuffer_state *state)
1601 {
1602 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1603 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1604 u32 shader_mask, tl, br, shader_control, target_mask;
1605
1606 if (rstate == NULL)
1607 return;
1608
1609 r600_context_flush_dest_caches(&rctx->ctx);
1610 rctx->ctx.num_dest_buffers = state->nr_cbufs;
1611
1612 /* unreference old buffer and reference new one */
1613 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1614
1615 util_copy_framebuffer_state(&rctx->framebuffer, state);
1616
1617 /* build states */
1618 rctx->have_depth_fb = 0;
1619 for (int i = 0; i < state->nr_cbufs; i++) {
1620 r600_cb(rctx, rstate, state, i);
1621 }
1622 if (state->zsbuf) {
1623 r600_db(rctx, rstate, state);
1624 rctx->ctx.num_dest_buffers++;
1625 }
1626
1627 target_mask = 0x00000000;
1628 target_mask = 0xFFFFFFFF;
1629 shader_mask = 0;
1630 shader_control = 0;
1631 for (int i = 0; i < state->nr_cbufs; i++) {
1632 target_mask ^= 0xf << (i * 4);
1633 shader_mask |= 0xf << (i * 4);
1634 shader_control |= 1 << i;
1635 }
1636 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1637 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1638
1639 r600_pipe_state_add_reg(rstate,
1640 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1641 0xFFFFFFFF, NULL, 0);
1642 r600_pipe_state_add_reg(rstate,
1643 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1644 0xFFFFFFFF, NULL, 0);
1645 r600_pipe_state_add_reg(rstate,
1646 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1647 0xFFFFFFFF, NULL, 0);
1648 r600_pipe_state_add_reg(rstate,
1649 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1650 0xFFFFFFFF, NULL, 0);
1651 r600_pipe_state_add_reg(rstate,
1652 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1653 0xFFFFFFFF, NULL, 0);
1654 r600_pipe_state_add_reg(rstate,
1655 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1656 0xFFFFFFFF, NULL, 0);
1657 r600_pipe_state_add_reg(rstate,
1658 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1659 0xFFFFFFFF, NULL, 0);
1660 r600_pipe_state_add_reg(rstate,
1661 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1662 0xFFFFFFFF, NULL, 0);
1663 r600_pipe_state_add_reg(rstate,
1664 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1665 0xFFFFFFFF, NULL, 0);
1666 if (rctx->chip_class >= R700) {
1667 r600_pipe_state_add_reg(rstate,
1668 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1669 0xFFFFFFFF, NULL, 0);
1670 }
1671
1672 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1673 shader_control, 0xFFFFFFFF, NULL, 0);
1674 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1675 0x00000000, target_mask, NULL, 0);
1676 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1677 shader_mask, 0xFFFFFFFF, NULL, 0);
1678 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1679 0x00000000, 0xFFFFFFFF, NULL, 0);
1680 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1681 0x00000000, 0xFFFFFFFF, NULL, 0);
1682 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1683 0x00000000, 0xFFFFFFFF, NULL, 0);
1684 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1685 0x01000000, 0xFFFFFFFF, NULL, 0);
1686 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1687 0x00000000, 0xFFFFFFFF, NULL, 0);
1688 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1689 0x000000FF, 0xFFFFFFFF, NULL, 0);
1690 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1691 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
1692 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1693 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
1694
1695 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1696 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1697 r600_context_pipe_state_set(&rctx->ctx, rstate);
1698
1699 if (state->zsbuf) {
1700 r600_polygon_offset_update(rctx);
1701 }
1702 }
1703
1704 static void r600_texture_barrier(struct pipe_context *ctx)
1705 {
1706 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1707
1708 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1709 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1710 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1711 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1712 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1));
1713 }
1714
1715 void r600_init_state_functions(struct r600_pipe_context *rctx)
1716 {
1717 rctx->context.create_blend_state = r600_create_blend_state;
1718 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1719 rctx->context.create_fs_state = r600_create_shader_state;
1720 rctx->context.create_rasterizer_state = r600_create_rs_state;
1721 rctx->context.create_sampler_state = r600_create_sampler_state;
1722 rctx->context.create_sampler_view = r600_create_sampler_view;
1723 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1724 rctx->context.create_vs_state = r600_create_shader_state;
1725 rctx->context.bind_blend_state = r600_bind_blend_state;
1726 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1727 rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1728 rctx->context.bind_fs_state = r600_bind_ps_shader;
1729 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1730 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1731 rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1732 rctx->context.bind_vs_state = r600_bind_vs_shader;
1733 rctx->context.delete_blend_state = r600_delete_state;
1734 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1735 rctx->context.delete_fs_state = r600_delete_ps_shader;
1736 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1737 rctx->context.delete_sampler_state = r600_delete_state;
1738 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1739 rctx->context.delete_vs_state = r600_delete_vs_shader;
1740 rctx->context.set_blend_color = r600_set_blend_color;
1741 rctx->context.set_clip_state = r600_set_clip_state;
1742 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1743 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1744 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1745 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1746 rctx->context.set_sample_mask = r600_set_sample_mask;
1747 rctx->context.set_scissor_state = r600_set_scissor_state;
1748 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1749 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1750 rctx->context.set_index_buffer = r600_set_index_buffer;
1751 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1752 rctx->context.set_viewport_state = r600_set_viewport_state;
1753 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1754 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1755 rctx->context.texture_barrier = r600_texture_barrier;
1756 rctx->context.create_stream_output_target = r600_create_so_target;
1757 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1758 rctx->context.set_stream_output_targets = r600_set_so_targets;
1759 }
1760
1761 void r600_adjust_gprs(struct r600_pipe_context *rctx)
1762 {
1763 struct r600_pipe_state rstate;
1764 unsigned num_ps_gprs = rctx->default_ps_gprs;
1765 unsigned num_vs_gprs = rctx->default_vs_gprs;
1766 unsigned tmp;
1767 int diff;
1768
1769 if (rctx->chip_class >= EVERGREEN)
1770 return;
1771
1772 if (!rctx->ps_shader || !rctx->vs_shader)
1773 return;
1774
1775 if (rctx->ps_shader->shader.bc.ngpr > rctx->default_ps_gprs)
1776 {
1777 diff = rctx->ps_shader->shader.bc.ngpr - rctx->default_ps_gprs;
1778 num_vs_gprs -= diff;
1779 num_ps_gprs += diff;
1780 }
1781
1782 if (rctx->vs_shader->shader.bc.ngpr > rctx->default_vs_gprs)
1783 {
1784 diff = rctx->vs_shader->shader.bc.ngpr - rctx->default_vs_gprs;
1785 num_ps_gprs -= diff;
1786 num_vs_gprs += diff;
1787 }
1788
1789 tmp = 0;
1790 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1791 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1792 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
1793 rstate.nregs = 0;
1794 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
1795
1796 r600_context_pipe_state_set(&rctx->ctx, &rstate);
1797 }
1798
1799 void r600_init_config(struct r600_pipe_context *rctx)
1800 {
1801 int ps_prio;
1802 int vs_prio;
1803 int gs_prio;
1804 int es_prio;
1805 int num_ps_gprs;
1806 int num_vs_gprs;
1807 int num_gs_gprs;
1808 int num_es_gprs;
1809 int num_temp_gprs;
1810 int num_ps_threads;
1811 int num_vs_threads;
1812 int num_gs_threads;
1813 int num_es_threads;
1814 int num_ps_stack_entries;
1815 int num_vs_stack_entries;
1816 int num_gs_stack_entries;
1817 int num_es_stack_entries;
1818 enum radeon_family family;
1819 struct r600_pipe_state *rstate = &rctx->config;
1820 u32 tmp;
1821
1822 family = rctx->family;
1823 ps_prio = 0;
1824 vs_prio = 1;
1825 gs_prio = 2;
1826 es_prio = 3;
1827 switch (family) {
1828 case CHIP_R600:
1829 num_ps_gprs = 192;
1830 num_vs_gprs = 56;
1831 num_temp_gprs = 4;
1832 num_gs_gprs = 0;
1833 num_es_gprs = 0;
1834 num_ps_threads = 136;
1835 num_vs_threads = 48;
1836 num_gs_threads = 4;
1837 num_es_threads = 4;
1838 num_ps_stack_entries = 128;
1839 num_vs_stack_entries = 128;
1840 num_gs_stack_entries = 0;
1841 num_es_stack_entries = 0;
1842 break;
1843 case CHIP_RV630:
1844 case CHIP_RV635:
1845 num_ps_gprs = 84;
1846 num_vs_gprs = 36;
1847 num_temp_gprs = 4;
1848 num_gs_gprs = 0;
1849 num_es_gprs = 0;
1850 num_ps_threads = 144;
1851 num_vs_threads = 40;
1852 num_gs_threads = 4;
1853 num_es_threads = 4;
1854 num_ps_stack_entries = 40;
1855 num_vs_stack_entries = 40;
1856 num_gs_stack_entries = 32;
1857 num_es_stack_entries = 16;
1858 break;
1859 case CHIP_RV610:
1860 case CHIP_RV620:
1861 case CHIP_RS780:
1862 case CHIP_RS880:
1863 default:
1864 num_ps_gprs = 84;
1865 num_vs_gprs = 36;
1866 num_temp_gprs = 4;
1867 num_gs_gprs = 0;
1868 num_es_gprs = 0;
1869 num_ps_threads = 136;
1870 num_vs_threads = 48;
1871 num_gs_threads = 4;
1872 num_es_threads = 4;
1873 num_ps_stack_entries = 40;
1874 num_vs_stack_entries = 40;
1875 num_gs_stack_entries = 32;
1876 num_es_stack_entries = 16;
1877 break;
1878 case CHIP_RV670:
1879 num_ps_gprs = 144;
1880 num_vs_gprs = 40;
1881 num_temp_gprs = 4;
1882 num_gs_gprs = 0;
1883 num_es_gprs = 0;
1884 num_ps_threads = 136;
1885 num_vs_threads = 48;
1886 num_gs_threads = 4;
1887 num_es_threads = 4;
1888 num_ps_stack_entries = 40;
1889 num_vs_stack_entries = 40;
1890 num_gs_stack_entries = 32;
1891 num_es_stack_entries = 16;
1892 break;
1893 case CHIP_RV770:
1894 num_ps_gprs = 192;
1895 num_vs_gprs = 56;
1896 num_temp_gprs = 4;
1897 num_gs_gprs = 0;
1898 num_es_gprs = 0;
1899 num_ps_threads = 188;
1900 num_vs_threads = 60;
1901 num_gs_threads = 0;
1902 num_es_threads = 0;
1903 num_ps_stack_entries = 256;
1904 num_vs_stack_entries = 256;
1905 num_gs_stack_entries = 0;
1906 num_es_stack_entries = 0;
1907 break;
1908 case CHIP_RV730:
1909 case CHIP_RV740:
1910 num_ps_gprs = 84;
1911 num_vs_gprs = 36;
1912 num_temp_gprs = 4;
1913 num_gs_gprs = 0;
1914 num_es_gprs = 0;
1915 num_ps_threads = 188;
1916 num_vs_threads = 60;
1917 num_gs_threads = 0;
1918 num_es_threads = 0;
1919 num_ps_stack_entries = 128;
1920 num_vs_stack_entries = 128;
1921 num_gs_stack_entries = 0;
1922 num_es_stack_entries = 0;
1923 break;
1924 case CHIP_RV710:
1925 num_ps_gprs = 192;
1926 num_vs_gprs = 56;
1927 num_temp_gprs = 4;
1928 num_gs_gprs = 0;
1929 num_es_gprs = 0;
1930 num_ps_threads = 144;
1931 num_vs_threads = 48;
1932 num_gs_threads = 0;
1933 num_es_threads = 0;
1934 num_ps_stack_entries = 128;
1935 num_vs_stack_entries = 128;
1936 num_gs_stack_entries = 0;
1937 num_es_stack_entries = 0;
1938 break;
1939 }
1940
1941 rctx->default_ps_gprs = num_ps_gprs;
1942 rctx->default_vs_gprs = num_vs_gprs;
1943
1944 rstate->id = R600_PIPE_STATE_CONFIG;
1945
1946 /* SQ_CONFIG */
1947 tmp = 0;
1948 switch (family) {
1949 case CHIP_RV610:
1950 case CHIP_RV620:
1951 case CHIP_RS780:
1952 case CHIP_RS880:
1953 case CHIP_RV710:
1954 break;
1955 default:
1956 tmp |= S_008C00_VC_ENABLE(1);
1957 break;
1958 }
1959 tmp |= S_008C00_DX9_CONSTS(0);
1960 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1961 tmp |= S_008C00_PS_PRIO(ps_prio);
1962 tmp |= S_008C00_VS_PRIO(vs_prio);
1963 tmp |= S_008C00_GS_PRIO(gs_prio);
1964 tmp |= S_008C00_ES_PRIO(es_prio);
1965 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
1966
1967 /* SQ_GPR_RESOURCE_MGMT_1 */
1968 tmp = 0;
1969 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1970 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1971 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1972 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
1973 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
1974
1975 /* SQ_GPR_RESOURCE_MGMT_2 */
1976 tmp = 0;
1977 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1978 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1979 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
1980
1981 /* SQ_THREAD_RESOURCE_MGMT */
1982 tmp = 0;
1983 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1984 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1985 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1986 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1987 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL, 0);
1988
1989 /* SQ_STACK_RESOURCE_MGMT_1 */
1990 tmp = 0;
1991 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1992 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1993 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
1994
1995 /* SQ_STACK_RESOURCE_MGMT_2 */
1996 tmp = 0;
1997 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1998 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1999 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
2000
2001 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2002 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL, 0);
2003
2004 if (rctx->chip_class >= R700) {
2005 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL, 0);
2006 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
2007 S_009508_DISABLE_CUBE_ANISO(1) |
2008 S_009508_SYNC_GRADIENT(1) |
2009 S_009508_SYNC_WALKER(1) |
2010 S_009508_SYNC_ALIGNER(1), 0xFFFFFFFF, NULL, 0);
2011 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL, 0);
2012 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL, 0);
2013 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL, 0);
2014 } else {
2015 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL, 0);
2016 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
2017 S_009508_DISABLE_CUBE_ANISO(1) |
2018 S_009508_SYNC_GRADIENT(1) |
2019 S_009508_SYNC_WALKER(1) |
2020 S_009508_SYNC_ALIGNER(1), 0xFFFFFFFF, NULL, 0);
2021 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL, 0);
2022 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL, 0);
2023 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL, 0);
2024 }
2025 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2026 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2027 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2028 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2029 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2030 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2031 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2032 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2033 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2034 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2035 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2036 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2037 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2038 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL, 0);
2039 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2040 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL, 0);
2041 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL, 0);
2042 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2043 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2044 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2045 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2046 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2047 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2048 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL, 0);
2049 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2050 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2051
2052 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL, 0);
2053 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2054 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2055 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
2056 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL, 0);
2057 r600_context_pipe_state_set(&rctx->ctx, rstate);
2058 }
2059
2060 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2061 {
2062 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2063 struct r600_pipe_state *rstate = &shader->rstate;
2064 struct r600_shader *rshader = &shader->shader;
2065 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2066 int pos_index = -1, face_index = -1;
2067 unsigned tmp, sid, ufi = 0;
2068 int need_linear = 0;
2069
2070 rstate->nregs = 0;
2071
2072 for (i = 0; i < rshader->ninput; i++) {
2073 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2074 pos_index = i;
2075 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2076 face_index = i;
2077
2078 sid = rshader->input[i].spi_sid;
2079
2080 tmp = S_028644_SEMANTIC(sid);
2081
2082 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2083 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2084 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2085 rctx->rasterizer && rctx->rasterizer->flatshade))
2086 tmp |= S_028644_FLAT_SHADE(1);
2087
2088 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2089 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2090 tmp |= S_028644_PT_SPRITE_TEX(1);
2091 }
2092
2093 if (rshader->input[i].centroid)
2094 tmp |= S_028644_SEL_CENTROID(1);
2095
2096 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2097 need_linear = 1;
2098 tmp |= S_028644_SEL_LINEAR(1);
2099 }
2100
2101 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2102 tmp, 0xFFFFFFFF, NULL, 0);
2103 }
2104
2105 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2106 for (i = 0; i < rshader->noutput; i++) {
2107 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2108 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2109 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2110 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
2111 }
2112 if (rshader->uses_kill)
2113 db_shader_control |= S_02880C_KILL_ENABLE(1);
2114
2115 exports_ps = 0;
2116 num_cout = 0;
2117 for (i = 0; i < rshader->noutput; i++) {
2118 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2119 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2120 exports_ps |= 1;
2121 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2122 num_cout++;
2123 }
2124 }
2125 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2126 if (!exports_ps) {
2127 /* always at least export 1 component per pixel */
2128 exports_ps = 2;
2129 }
2130
2131 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2132 S_0286CC_PERSP_GRADIENT_ENA(1)|
2133 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2134 spi_input_z = 0;
2135 if (pos_index != -1) {
2136 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2137 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2138 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2139 S_0286CC_BARYC_SAMPLE_CNTL(1));
2140 spi_input_z |= 1;
2141 }
2142
2143 spi_ps_in_control_1 = 0;
2144 if (face_index != -1) {
2145 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2146 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2147 }
2148
2149 /* HW bug in original R600 */
2150 if (rctx->family == CHIP_R600)
2151 ufi = 1;
2152
2153 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL, 0);
2154 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL, 0);
2155 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL, 0);
2156 r600_pipe_state_add_reg(rstate,
2157 R_028840_SQ_PGM_START_PS,
2158 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2159 r600_pipe_state_add_reg(rstate,
2160 R_028850_SQ_PGM_RESOURCES_PS,
2161 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2162 S_028850_STACK_SIZE(rshader->bc.nstack) |
2163 S_028850_UNCACHED_FIRST_INST(ufi),
2164 0xFFFFFFFF, NULL, 0);
2165 r600_pipe_state_add_reg(rstate,
2166 R_028854_SQ_PGM_EXPORTS_PS,
2167 exports_ps, 0xFFFFFFFF, NULL, 0);
2168 r600_pipe_state_add_reg(rstate,
2169 R_0288CC_SQ_PGM_CF_OFFSET_PS,
2170 0x00000000, 0xFFFFFFFF, NULL, 0);
2171 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
2172 S_028808_MULTIWRITE_ENABLE(!!rshader->fs_write_all),
2173 S_028808_MULTIWRITE_ENABLE(1),
2174 NULL, 0);
2175 /* only set some bits here, the other bits are set in the dsa state */
2176 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2177 db_shader_control,
2178 0xFFFFFFFF, NULL, 0);
2179
2180 r600_pipe_state_add_reg(rstate,
2181 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
2182 0xFFFFFFFF, NULL, 0);
2183
2184 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2185 if (rctx->rasterizer)
2186 shader->flatshade = rctx->rasterizer->flatshade;
2187 }
2188
2189 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2190 {
2191 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2192 struct r600_pipe_state *rstate = &shader->rstate;
2193 struct r600_shader *rshader = &shader->shader;
2194 unsigned spi_vs_out_id[10] = {};
2195 unsigned i, tmp, nparams = 0;
2196
2197 /* clear previous register */
2198 rstate->nregs = 0;
2199
2200 for (i = 0; i < rshader->noutput; i++) {
2201 if (rshader->output[i].spi_sid) {
2202 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2203 spi_vs_out_id[nparams / 4] |= tmp;
2204 nparams++;
2205 }
2206 }
2207
2208 for (i = 0; i < 10; i++) {
2209 r600_pipe_state_add_reg(rstate,
2210 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2211 spi_vs_out_id[i], 0xFFFFFFFF, NULL, 0);
2212 }
2213
2214 /* Certain attributes (position, psize, etc.) don't count as params.
2215 * VS is required to export at least one param and r600_shader_from_tgsi()
2216 * takes care of adding a dummy export.
2217 */
2218 if (nparams < 1)
2219 nparams = 1;
2220
2221 r600_pipe_state_add_reg(rstate,
2222 R_0286C4_SPI_VS_OUT_CONFIG,
2223 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2224 0xFFFFFFFF, NULL, 0);
2225 r600_pipe_state_add_reg(rstate,
2226 R_028868_SQ_PGM_RESOURCES_VS,
2227 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2228 S_028868_STACK_SIZE(rshader->bc.nstack),
2229 0xFFFFFFFF, NULL, 0);
2230 r600_pipe_state_add_reg(rstate,
2231 R_0288D0_SQ_PGM_CF_OFFSET_VS,
2232 0x00000000, 0xFFFFFFFF, NULL, 0);
2233 r600_pipe_state_add_reg(rstate,
2234 R_028858_SQ_PGM_START_VS,
2235 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2236
2237 r600_pipe_state_add_reg(rstate,
2238 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2239 0xFFFFFFFF, NULL, 0);
2240
2241 r600_pipe_state_add_reg(rstate,
2242 R_02881C_PA_CL_VS_OUT_CNTL,
2243 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2244 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2245 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write),
2246 S_02881C_VS_OUT_CCDIST0_VEC_ENA(1) |
2247 S_02881C_VS_OUT_CCDIST1_VEC_ENA(1) |
2248 S_02881C_VS_OUT_MISC_VEC_ENA(1),
2249 NULL, 0);
2250 }
2251
2252 void r600_fetch_shader(struct pipe_context *ctx,
2253 struct r600_vertex_element *ve)
2254 {
2255 struct r600_pipe_state *rstate;
2256 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2257
2258 rstate = &ve->rstate;
2259 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2260 rstate->nregs = 0;
2261 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
2262 0x00000000, 0xFFFFFFFF, NULL, 0);
2263 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
2264 0x00000000, 0xFFFFFFFF, NULL, 0);
2265 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
2266 0,
2267 0xFFFFFFFF, ve->fetch_shader, RADEON_USAGE_READ);
2268 }
2269
2270 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
2271 {
2272 struct pipe_depth_stencil_alpha_state dsa;
2273 struct r600_pipe_state *rstate;
2274 boolean quirk = false;
2275
2276 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2277 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2278 quirk = true;
2279
2280 memset(&dsa, 0, sizeof(dsa));
2281
2282 if (quirk) {
2283 dsa.depth.enabled = 1;
2284 dsa.depth.func = PIPE_FUNC_LEQUAL;
2285 dsa.stencil[0].enabled = 1;
2286 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2287 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2288 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2289 dsa.stencil[0].writemask = 0xff;
2290 }
2291
2292 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2293 r600_pipe_state_add_reg(rstate,
2294 R_028D0C_DB_RENDER_CONTROL,
2295 S_028D0C_DEPTH_COPY_ENABLE(1) |
2296 S_028D0C_STENCIL_COPY_ENABLE(1) |
2297 S_028D0C_COPY_CENTROID(1),
2298 S_028D0C_DEPTH_COPY_ENABLE(1) |
2299 S_028D0C_STENCIL_COPY_ENABLE(1) |
2300 S_028D0C_COPY_CENTROID(1), NULL, 0);
2301 return rstate;
2302 }
2303
2304 void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
2305 struct r600_pipe_resource_state *rstate)
2306 {
2307 rstate->id = R600_PIPE_STATE_RESOURCE;
2308
2309 rstate->bo[0] = NULL;
2310 rstate->val[0] = 0;
2311 rstate->val[1] = 0;
2312 rstate->val[2] = 0;
2313 rstate->val[3] = 0;
2314 rstate->val[4] = 0;
2315 rstate->val[5] = 0;
2316 rstate->val[6] = 0xc0000000;
2317 }
2318
2319 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
2320 struct r600_resource *rbuffer,
2321 unsigned offset, unsigned stride,
2322 enum radeon_bo_usage usage)
2323 {
2324 rstate->val[0] = offset;
2325 rstate->bo[0] = rbuffer;
2326 rstate->bo_usage[0] = usage;
2327 rstate->val[1] = rbuffer->buf->size - offset - 1;
2328 rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2329 S_038008_STRIDE(stride);
2330 }