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gk110/ir: add emission for VSHL
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
145 {
146 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
147 FALSE) != ~0U;
148 }
149
150 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
151 {
152 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
153 r600_translate_colorswap(format, FALSE) != ~0U;
154 }
155
156 static bool r600_is_zs_format_supported(enum pipe_format format)
157 {
158 return r600_translate_dbformat(format) != ~0U;
159 }
160
161 boolean r600_is_format_supported(struct pipe_screen *screen,
162 enum pipe_format format,
163 enum pipe_texture_target target,
164 unsigned sample_count,
165 unsigned usage)
166 {
167 struct r600_screen *rscreen = (struct r600_screen*)screen;
168 unsigned retval = 0;
169
170 if (target >= PIPE_MAX_TEXTURE_TYPES) {
171 R600_ERR("r600: unsupported texture type %d\n", target);
172 return FALSE;
173 }
174
175 if (!util_format_is_supported(format, usage))
176 return FALSE;
177
178 if (sample_count > 1) {
179 if (!rscreen->has_msaa)
180 return FALSE;
181
182 /* R11G11B10 is broken on R6xx. */
183 if (rscreen->b.chip_class == R600 &&
184 format == PIPE_FORMAT_R11G11B10_FLOAT)
185 return FALSE;
186
187 /* MSAA integer colorbuffers hang. */
188 if (util_format_is_pure_integer(format) &&
189 !util_format_is_depth_or_stencil(format))
190 return FALSE;
191
192 switch (sample_count) {
193 case 2:
194 case 4:
195 case 8:
196 break;
197 default:
198 return FALSE;
199 }
200 }
201
202 if (usage & PIPE_BIND_SAMPLER_VIEW) {
203 if (target == PIPE_BUFFER) {
204 if (r600_is_vertex_format_supported(format))
205 retval |= PIPE_BIND_SAMPLER_VIEW;
206 } else {
207 if (r600_is_sampler_format_supported(screen, format))
208 retval |= PIPE_BIND_SAMPLER_VIEW;
209 }
210 }
211
212 if ((usage & (PIPE_BIND_RENDER_TARGET |
213 PIPE_BIND_DISPLAY_TARGET |
214 PIPE_BIND_SCANOUT |
215 PIPE_BIND_SHARED |
216 PIPE_BIND_BLENDABLE)) &&
217 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
218 retval |= usage &
219 (PIPE_BIND_RENDER_TARGET |
220 PIPE_BIND_DISPLAY_TARGET |
221 PIPE_BIND_SCANOUT |
222 PIPE_BIND_SHARED);
223 if (!util_format_is_pure_integer(format) &&
224 !util_format_is_depth_or_stencil(format))
225 retval |= usage & PIPE_BIND_BLENDABLE;
226 }
227
228 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
229 r600_is_zs_format_supported(format)) {
230 retval |= PIPE_BIND_DEPTH_STENCIL;
231 }
232
233 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
234 r600_is_vertex_format_supported(format)) {
235 retval |= PIPE_BIND_VERTEX_BUFFER;
236 }
237
238 if (usage & PIPE_BIND_TRANSFER_READ)
239 retval |= PIPE_BIND_TRANSFER_READ;
240 if (usage & PIPE_BIND_TRANSFER_WRITE)
241 retval |= PIPE_BIND_TRANSFER_WRITE;
242
243 if ((usage & PIPE_BIND_LINEAR) &&
244 !util_format_is_compressed(format) &&
245 !(usage & PIPE_BIND_DEPTH_STENCIL))
246 retval |= PIPE_BIND_LINEAR;
247
248 return retval == usage;
249 }
250
251 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
252 {
253 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
254 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
255 float offset_units = state->offset_units;
256 float offset_scale = state->offset_scale;
257
258 switch (state->zs_format) {
259 case PIPE_FORMAT_Z24X8_UNORM:
260 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
261 offset_units *= 2.0f;
262 break;
263 case PIPE_FORMAT_Z16_UNORM:
264 offset_units *= 4.0f;
265 break;
266 default:;
267 }
268
269 radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
270 radeon_emit(cs, fui(offset_scale));
271 radeon_emit(cs, fui(offset_units));
272 radeon_emit(cs, fui(offset_scale));
273 radeon_emit(cs, fui(offset_units));
274 }
275
276 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
277 {
278 int j = state->independent_blend_enable ? i : 0;
279
280 unsigned eqRGB = state->rt[j].rgb_func;
281 unsigned srcRGB = state->rt[j].rgb_src_factor;
282 unsigned dstRGB = state->rt[j].rgb_dst_factor;
283
284 unsigned eqA = state->rt[j].alpha_func;
285 unsigned srcA = state->rt[j].alpha_src_factor;
286 unsigned dstA = state->rt[j].alpha_dst_factor;
287 uint32_t bc = 0;
288
289 if (!state->rt[j].blend_enable)
290 return 0;
291
292 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
293 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
294 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
295
296 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
297 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
298 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
299 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
300 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
301 }
302 return bc;
303 }
304
305 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
306 const struct pipe_blend_state *state,
307 int mode)
308 {
309 struct r600_context *rctx = (struct r600_context *)ctx;
310 uint32_t color_control = 0, target_mask = 0;
311 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
312
313 if (!blend) {
314 return NULL;
315 }
316
317 r600_init_command_buffer(&blend->buffer, 20);
318 r600_init_command_buffer(&blend->buffer_no_blend, 20);
319
320 /* R600 does not support per-MRT blends */
321 if (rctx->b.family > CHIP_R600)
322 color_control |= S_028808_PER_MRT_BLEND(1);
323
324 if (state->logicop_enable) {
325 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
326 } else {
327 color_control |= (0xcc << 16);
328 }
329 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
330 if (state->independent_blend_enable) {
331 for (int i = 0; i < 8; i++) {
332 if (state->rt[i].blend_enable) {
333 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
334 }
335 target_mask |= (state->rt[i].colormask << (4 * i));
336 }
337 } else {
338 for (int i = 0; i < 8; i++) {
339 if (state->rt[0].blend_enable) {
340 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
341 }
342 target_mask |= (state->rt[0].colormask << (4 * i));
343 }
344 }
345
346 if (target_mask)
347 color_control |= S_028808_SPECIAL_OP(mode);
348 else
349 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
350
351 /* only MRT0 has dual src blend */
352 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
353 blend->cb_target_mask = target_mask;
354 blend->cb_color_control = color_control;
355 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
356 blend->alpha_to_one = state->alpha_to_one;
357
358 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
359 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
360 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
361 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
362 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
363 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
364
365 /* Copy over the registers set so far into buffer_no_blend. */
366 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
367 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
368
369 /* Only add blend registers if blending is enabled. */
370 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
371 return blend;
372 }
373
374 /* The first R600 does not support per-MRT blends */
375 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
376 r600_get_blend_control(state, 0));
377
378 if (rctx->b.family > CHIP_R600) {
379 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
380 for (int i = 0; i < 8; i++) {
381 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
382 }
383 }
384 return blend;
385 }
386
387 static void *r600_create_blend_state(struct pipe_context *ctx,
388 const struct pipe_blend_state *state)
389 {
390 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
391 }
392
393 static void *r600_create_dsa_state(struct pipe_context *ctx,
394 const struct pipe_depth_stencil_alpha_state *state)
395 {
396 unsigned db_depth_control, alpha_test_control, alpha_ref;
397 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
398
399 if (!dsa) {
400 return NULL;
401 }
402
403 r600_init_command_buffer(&dsa->buffer, 3);
404
405 dsa->valuemask[0] = state->stencil[0].valuemask;
406 dsa->valuemask[1] = state->stencil[1].valuemask;
407 dsa->writemask[0] = state->stencil[0].writemask;
408 dsa->writemask[1] = state->stencil[1].writemask;
409 dsa->zwritemask = state->depth.writemask;
410
411 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
412 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
413 S_028800_ZFUNC(state->depth.func);
414
415 /* stencil */
416 if (state->stencil[0].enabled) {
417 db_depth_control |= S_028800_STENCIL_ENABLE(1);
418 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
419 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
420 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
421 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
422
423 if (state->stencil[1].enabled) {
424 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
425 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
426 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
427 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
428 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
429 }
430 }
431
432 /* alpha */
433 alpha_test_control = 0;
434 alpha_ref = 0;
435 if (state->alpha.enabled) {
436 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
437 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
438 alpha_ref = fui(state->alpha.ref_value);
439 }
440 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
441 dsa->alpha_ref = alpha_ref;
442
443 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
444 return dsa;
445 }
446
447 static void *r600_create_rs_state(struct pipe_context *ctx,
448 const struct pipe_rasterizer_state *state)
449 {
450 struct r600_context *rctx = (struct r600_context *)ctx;
451 unsigned tmp, sc_mode_cntl, spi_interp;
452 float psize_min, psize_max;
453 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
454
455 if (!rs) {
456 return NULL;
457 }
458
459 r600_init_command_buffer(&rs->buffer, 30);
460
461 rs->scissor_enable = state->scissor;
462 rs->flatshade = state->flatshade;
463 rs->sprite_coord_enable = state->sprite_coord_enable;
464 rs->two_side = state->light_twoside;
465 rs->clip_plane_enable = state->clip_plane_enable;
466 rs->pa_sc_line_stipple = state->line_stipple_enable ?
467 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
468 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
469 rs->pa_cl_clip_cntl =
470 S_028810_PS_UCP_MODE(3) |
471 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
472 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
473 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
474 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
475 if (rctx->b.chip_class == R700) {
476 rs->pa_cl_clip_cntl |=
477 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
478 }
479 rs->multisample_enable = state->multisample;
480
481 /* offset */
482 rs->offset_units = state->offset_units;
483 rs->offset_scale = state->offset_scale * 16.0f;
484 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
485
486 if (state->point_size_per_vertex) {
487 psize_min = util_get_min_point_size(state);
488 psize_max = 8192;
489 } else {
490 /* Force the point size to be as if the vertex output was disabled. */
491 psize_min = state->point_size;
492 psize_max = state->point_size;
493 }
494
495 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
496 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
497 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
498 S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1);
499 if (rctx->b.family == CHIP_RV770) {
500 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */
501 sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1);
502 }
503 if (rctx->b.chip_class >= R700) {
504 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
505 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
506 S_028A4C_R700_VPORT_SCISSOR_ENABLE(1);
507 } else {
508 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
509 }
510
511 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
512 if (state->sprite_coord_enable) {
513 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
514 S_0286D4_PNT_SPRITE_OVRD_X(2) |
515 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
516 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
517 S_0286D4_PNT_SPRITE_OVRD_W(1);
518 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
519 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
520 }
521 }
522
523 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
524 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
525 tmp = r600_pack_float_12p4(state->point_size/2);
526 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
527 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
528 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
529 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
530 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
531 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
532 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
533
534 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
535 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
536 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
537 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
538 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
539 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
540
541 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
542 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
543 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
544 S_028814_FACE(!state->front_ccw) |
545 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
546 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
547 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
548 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
549 state->fill_back != PIPE_POLYGON_MODE_FILL) |
550 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
551 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
552 if (rctx->b.chip_class == R700) {
553 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
554 }
555 if (rctx->b.chip_class == R600) {
556 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
557 S_028350_MULTIPASS(state->rasterizer_discard));
558 }
559 return rs;
560 }
561
562 static unsigned r600_tex_filter(unsigned filter, unsigned max_aniso)
563 {
564 if (filter == PIPE_TEX_FILTER_LINEAR)
565 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_BILINEAR
566 : V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
567 else
568 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_POINT
569 : V_03C000_SQ_TEX_XY_FILTER_POINT;
570 }
571
572 static void *r600_create_sampler_state(struct pipe_context *ctx,
573 const struct pipe_sampler_state *state)
574 {
575 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
576 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
577 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
578 : state->max_anisotropy;
579 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
580
581 if (!ss) {
582 return NULL;
583 }
584
585 ss->seamless_cube_map = state->seamless_cube_map;
586 ss->border_color_use = sampler_state_needs_border_color(state);
587
588 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
589 ss->tex_sampler_words[0] =
590 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
591 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
592 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
593 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter, max_aniso)) |
594 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter, max_aniso)) |
595 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
596 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
597 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
598 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
599 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
600 ss->tex_sampler_words[1] =
601 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
602 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
603 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
604 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
605 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
606
607 if (ss->border_color_use) {
608 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
609 }
610 return ss;
611 }
612
613 static struct pipe_sampler_view *
614 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
615 unsigned width0, unsigned height0)
616
617 {
618 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
619 int stride = util_format_get_blocksize(view->base.format);
620 unsigned format, num_format, format_comp, endian;
621 uint64_t offset = view->base.u.buf.first_element * stride;
622 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
623
624 r600_vertex_data_type(view->base.format,
625 &format, &num_format, &format_comp,
626 &endian);
627
628 view->tex_resource = &tmp->resource;
629 view->skip_mip_address_reloc = true;
630
631 view->tex_resource_words[0] = offset;
632 view->tex_resource_words[1] = size - 1;
633 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) |
634 S_038008_STRIDE(stride) |
635 S_038008_DATA_FORMAT(format) |
636 S_038008_NUM_FORMAT_ALL(num_format) |
637 S_038008_FORMAT_COMP_ALL(format_comp) |
638 S_038008_ENDIAN_SWAP(endian);
639 view->tex_resource_words[3] = 0;
640 /*
641 * in theory dword 4 is for number of elements, for use with resinfo,
642 * but it seems to utterly fail to work, the amd gpu shader analyser
643 * uses a const buffer to store the element sizes for buffer txq
644 */
645 view->tex_resource_words[4] = 0;
646 view->tex_resource_words[5] = 0;
647 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
648 return &view->base;
649 }
650
651 struct pipe_sampler_view *
652 r600_create_sampler_view_custom(struct pipe_context *ctx,
653 struct pipe_resource *texture,
654 const struct pipe_sampler_view *state,
655 unsigned width_first_level, unsigned height_first_level)
656 {
657 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
658 struct r600_texture *tmp = (struct r600_texture*)texture;
659 unsigned format, endian;
660 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
661 unsigned char swizzle[4], array_mode = 0;
662 unsigned width, height, depth, offset_level, last_level;
663 bool do_endian_swap = FALSE;
664
665 if (!view)
666 return NULL;
667
668 /* initialize base object */
669 view->base = *state;
670 view->base.texture = NULL;
671 pipe_reference(NULL, &texture->reference);
672 view->base.texture = texture;
673 view->base.reference.count = 1;
674 view->base.context = ctx;
675
676 if (texture->target == PIPE_BUFFER)
677 return texture_buffer_sampler_view(view, texture->width0, 1);
678
679 swizzle[0] = state->swizzle_r;
680 swizzle[1] = state->swizzle_g;
681 swizzle[2] = state->swizzle_b;
682 swizzle[3] = state->swizzle_a;
683
684 if (R600_BIG_ENDIAN)
685 do_endian_swap = !(tmp->is_depth && !tmp->is_flushing_texture);
686
687 format = r600_translate_texformat(ctx->screen, state->format,
688 swizzle,
689 &word4, &yuv_format, do_endian_swap);
690 assert(format != ~0);
691 if (format == ~0) {
692 FREE(view);
693 return NULL;
694 }
695
696 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
697 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
698 FREE(view);
699 return NULL;
700 }
701 tmp = tmp->flushed_depth_texture;
702 }
703
704 endian = r600_colorformat_endian_swap(format, do_endian_swap);
705
706 offset_level = state->u.tex.first_level;
707 last_level = state->u.tex.last_level - offset_level;
708 width = width_first_level;
709 height = height_first_level;
710 depth = u_minify(texture->depth0, offset_level);
711 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
712
713 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
714 height = 1;
715 depth = texture->array_size;
716 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
717 depth = texture->array_size;
718 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
719 depth = texture->array_size / 6;
720 switch (tmp->surface.level[offset_level].mode) {
721 case RADEON_SURF_MODE_LINEAR_ALIGNED:
722 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
723 break;
724 case RADEON_SURF_MODE_1D:
725 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
726 break;
727 case RADEON_SURF_MODE_2D:
728 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
729 break;
730 case RADEON_SURF_MODE_LINEAR:
731 default:
732 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
733 break;
734 }
735
736 if (state->format == PIPE_FORMAT_X24S8_UINT ||
737 state->format == PIPE_FORMAT_S8X24_UINT ||
738 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
739 state->format == PIPE_FORMAT_S8_UINT)
740 view->is_stencil_sampler = true;
741
742 view->tex_resource = &tmp->resource;
743 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
744 S_038000_TILE_MODE(array_mode) |
745 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
746 S_038000_PITCH((pitch / 8) - 1) |
747 S_038000_TEX_WIDTH(width - 1));
748 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
749 S_038004_TEX_DEPTH(depth - 1) |
750 S_038004_DATA_FORMAT(format));
751 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
752 if (offset_level >= tmp->surface.last_level) {
753 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
754 } else {
755 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
756 }
757 view->tex_resource_words[4] = (word4 |
758 S_038010_REQUEST_SIZE(1) |
759 S_038010_ENDIAN_SWAP(endian) |
760 S_038010_BASE_LEVEL(0));
761 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
762 S_038014_LAST_ARRAY(state->u.tex.last_layer));
763 if (texture->nr_samples > 1) {
764 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
765 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
766 } else {
767 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
768 }
769 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
770 S_038018_MAX_ANISO(4 /* max 16 samples */));
771 return &view->base;
772 }
773
774 static struct pipe_sampler_view *
775 r600_create_sampler_view(struct pipe_context *ctx,
776 struct pipe_resource *tex,
777 const struct pipe_sampler_view *state)
778 {
779 return r600_create_sampler_view_custom(ctx, tex, state,
780 u_minify(tex->width0, state->u.tex.first_level),
781 u_minify(tex->height0, state->u.tex.first_level));
782 }
783
784 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
785 {
786 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
787 struct pipe_clip_state *state = &rctx->clip_state.state;
788
789 radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
790 radeon_emit_array(cs, (unsigned*)state, 6*4);
791 }
792
793 static void r600_set_polygon_stipple(struct pipe_context *ctx,
794 const struct pipe_poly_stipple *state)
795 {
796 }
797
798 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
799 unsigned size, unsigned alignment)
800 {
801 struct pipe_resource buffer;
802
803 memset(&buffer, 0, sizeof buffer);
804 buffer.target = PIPE_BUFFER;
805 buffer.format = PIPE_FORMAT_R8_UNORM;
806 buffer.bind = PIPE_BIND_CUSTOM;
807 buffer.usage = PIPE_USAGE_DEFAULT;
808 buffer.flags = 0;
809 buffer.width0 = size;
810 buffer.height0 = 1;
811 buffer.depth0 = 1;
812 buffer.array_size = 1;
813
814 return (struct r600_resource*)
815 r600_buffer_create(&rscreen->b.b, &buffer, alignment);
816 }
817
818 static void r600_init_color_surface(struct r600_context *rctx,
819 struct r600_surface *surf,
820 bool force_cmask_fmask)
821 {
822 struct r600_screen *rscreen = rctx->screen;
823 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
824 unsigned level = surf->base.u.tex.level;
825 unsigned pitch, slice;
826 unsigned color_info;
827 unsigned color_view;
828 unsigned format, swap, ntype, endian;
829 unsigned offset;
830 const struct util_format_description *desc;
831 int i;
832 bool blend_bypass = 0, blend_clamp = 1, do_endian_swap = FALSE;
833
834 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
835 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
836 rtex = rtex->flushed_depth_texture;
837 assert(rtex);
838 }
839
840 offset = rtex->surface.level[level].offset;
841 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
842 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
843 offset += rtex->surface.level[level].slice_size *
844 surf->base.u.tex.first_layer;
845 color_view = 0;
846 } else
847 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
848 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
849
850 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
851 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
852 if (slice) {
853 slice = slice - 1;
854 }
855 color_info = 0;
856 switch (rtex->surface.level[level].mode) {
857 case RADEON_SURF_MODE_LINEAR_ALIGNED:
858 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
859 break;
860 case RADEON_SURF_MODE_1D:
861 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
862 break;
863 case RADEON_SURF_MODE_2D:
864 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
865 break;
866 case RADEON_SURF_MODE_LINEAR:
867 default:
868 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
869 break;
870 }
871
872 desc = util_format_description(surf->base.format);
873
874 for (i = 0; i < 4; i++) {
875 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
876 break;
877 }
878 }
879
880 ntype = V_0280A0_NUMBER_UNORM;
881 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
882 ntype = V_0280A0_NUMBER_SRGB;
883 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
884 if (desc->channel[i].normalized)
885 ntype = V_0280A0_NUMBER_SNORM;
886 else if (desc->channel[i].pure_integer)
887 ntype = V_0280A0_NUMBER_SINT;
888 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
889 if (desc->channel[i].normalized)
890 ntype = V_0280A0_NUMBER_UNORM;
891 else if (desc->channel[i].pure_integer)
892 ntype = V_0280A0_NUMBER_UINT;
893 }
894
895 if (R600_BIG_ENDIAN)
896 do_endian_swap = !(rtex->is_depth && !rtex->is_flushing_texture);
897
898 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format,
899 do_endian_swap);
900 assert(format != ~0);
901
902 swap = r600_translate_colorswap(surf->base.format, do_endian_swap);
903 assert(swap != ~0);
904
905 endian = r600_colorformat_endian_swap(format, do_endian_swap);
906
907 /* set blend bypass according to docs if SINT/UINT or
908 8/24 COLOR variants */
909 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
910 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
911 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
912 blend_clamp = 0;
913 blend_bypass = 1;
914 }
915
916 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
917
918 color_info |= S_0280A0_FORMAT(format) |
919 S_0280A0_COMP_SWAP(swap) |
920 S_0280A0_BLEND_BYPASS(blend_bypass) |
921 S_0280A0_BLEND_CLAMP(blend_clamp) |
922 S_0280A0_NUMBER_TYPE(ntype) |
923 S_0280A0_ENDIAN(endian);
924
925 /* EXPORT_NORM is an optimzation that can be enabled for better
926 * performance in certain cases
927 */
928 if (rctx->b.chip_class == R600) {
929 /* EXPORT_NORM can be enabled if:
930 * - 11-bit or smaller UNORM/SNORM/SRGB
931 * - BLEND_CLAMP is enabled
932 * - BLEND_FLOAT32 is disabled
933 */
934 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
935 (desc->channel[i].size < 12 &&
936 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
937 ntype != V_0280A0_NUMBER_UINT &&
938 ntype != V_0280A0_NUMBER_SINT) &&
939 G_0280A0_BLEND_CLAMP(color_info) &&
940 !G_0280A0_BLEND_FLOAT32(color_info)) {
941 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
942 surf->export_16bpc = true;
943 }
944 } else {
945 /* EXPORT_NORM can be enabled if:
946 * - 11-bit or smaller UNORM/SNORM/SRGB
947 * - 16-bit or smaller FLOAT
948 */
949 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
950 ((desc->channel[i].size < 12 &&
951 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
952 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
953 (desc->channel[i].size < 17 &&
954 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
955 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
956 surf->export_16bpc = true;
957 }
958 }
959
960 /* These might not always be initialized to zero. */
961 surf->cb_color_base = offset >> 8;
962 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
963 S_028060_SLICE_TILE_MAX(slice);
964 surf->cb_color_fmask = surf->cb_color_base;
965 surf->cb_color_cmask = surf->cb_color_base;
966 surf->cb_color_mask = 0;
967
968 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
969 &rtex->resource.b.b);
970 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
971 &rtex->resource.b.b);
972
973 if (rtex->cmask.size) {
974 surf->cb_color_cmask = rtex->cmask.offset >> 8;
975 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
976
977 if (rtex->fmask.size) {
978 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
979 surf->cb_color_fmask = rtex->fmask.offset >> 8;
980 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
981 } else { /* cmask only */
982 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
983 }
984 } else if (force_cmask_fmask) {
985 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
986 *
987 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
988 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
989 * because it's not an MSAA buffer.
990 */
991 struct r600_cmask_info cmask;
992 struct r600_fmask_info fmask;
993
994 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
995 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
996
997 /* CMASK. */
998 if (!rctx->dummy_cmask ||
999 rctx->dummy_cmask->b.b.width0 < cmask.size ||
1000 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1001 struct pipe_transfer *transfer;
1002 void *ptr;
1003
1004 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1005 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1006
1007 /* Set the contents to 0xCC. */
1008 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1009 memset(ptr, 0xCC, cmask.size);
1010 pipe_buffer_unmap(&rctx->b.b, transfer);
1011 }
1012 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1013 &rctx->dummy_cmask->b.b);
1014
1015 /* FMASK. */
1016 if (!rctx->dummy_fmask ||
1017 rctx->dummy_fmask->b.b.width0 < fmask.size ||
1018 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1019 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1020 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1021
1022 }
1023 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1024 &rctx->dummy_fmask->b.b);
1025
1026 /* Init the registers. */
1027 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1028 surf->cb_color_cmask = 0;
1029 surf->cb_color_fmask = 0;
1030 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1031 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1032 }
1033
1034 surf->cb_color_info = color_info;
1035 surf->cb_color_view = color_view;
1036 surf->color_initialized = true;
1037 }
1038
1039 static void r600_init_depth_surface(struct r600_context *rctx,
1040 struct r600_surface *surf)
1041 {
1042 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1043 unsigned level, pitch, slice, format, offset, array_mode;
1044
1045 level = surf->base.u.tex.level;
1046 offset = rtex->surface.level[level].offset;
1047 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1048 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1049 if (slice) {
1050 slice = slice - 1;
1051 }
1052 switch (rtex->surface.level[level].mode) {
1053 case RADEON_SURF_MODE_2D:
1054 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1055 break;
1056 case RADEON_SURF_MODE_1D:
1057 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1058 case RADEON_SURF_MODE_LINEAR:
1059 default:
1060 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1061 break;
1062 }
1063
1064 format = r600_translate_dbformat(surf->base.format);
1065 assert(format != ~0);
1066
1067 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1068 surf->db_depth_base = offset >> 8;
1069 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1070 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1071 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1072 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1073
1074 switch (surf->base.format) {
1075 case PIPE_FORMAT_Z24X8_UNORM:
1076 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1077 surf->pa_su_poly_offset_db_fmt_cntl =
1078 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1079 break;
1080 case PIPE_FORMAT_Z32_FLOAT:
1081 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1082 surf->pa_su_poly_offset_db_fmt_cntl =
1083 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1084 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1085 break;
1086 case PIPE_FORMAT_Z16_UNORM:
1087 surf->pa_su_poly_offset_db_fmt_cntl =
1088 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1089 break;
1090 default:;
1091 }
1092
1093 /* use htile only for first level */
1094 if (rtex->htile_buffer && !level) {
1095 surf->db_htile_data_base = 0;
1096 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1097 S_028D24_HTILE_HEIGHT(1) |
1098 S_028D24_FULL_CACHE(1);
1099 /* preload is not working properly on r6xx/r7xx */
1100 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1101 }
1102
1103 surf->depth_initialized = true;
1104 }
1105
1106 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1107 const struct pipe_framebuffer_state *state)
1108 {
1109 struct r600_context *rctx = (struct r600_context *)ctx;
1110 struct r600_surface *surf;
1111 struct r600_texture *rtex;
1112 unsigned i;
1113
1114 if (rctx->framebuffer.state.nr_cbufs) {
1115 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1116 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1117 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1118 }
1119 if (rctx->framebuffer.state.zsbuf) {
1120 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1121 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1122
1123 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1124 if (rctx->b.chip_class >= R700 && rtex->htile_buffer) {
1125 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1126 }
1127 }
1128
1129 /* Set the new state. */
1130 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1131
1132 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1133 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1134 util_format_is_pure_integer(state->cbufs[0]->format);
1135 rctx->framebuffer.compressed_cb_mask = 0;
1136 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1137 state->cbufs[0] && state->cbufs[1] &&
1138 state->cbufs[0]->texture->nr_samples > 1 &&
1139 state->cbufs[1]->texture->nr_samples <= 1;
1140 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1141
1142 /* Colorbuffers. */
1143 for (i = 0; i < state->nr_cbufs; i++) {
1144 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1145 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1146 rctx->framebuffer.is_msaa_resolve &&
1147 i == 1;
1148
1149 surf = (struct r600_surface*)state->cbufs[i];
1150 if (!surf)
1151 continue;
1152
1153 rtex = (struct r600_texture*)surf->base.texture;
1154 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1155
1156 if (!surf->color_initialized || force_cmask_fmask) {
1157 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1158 if (force_cmask_fmask) {
1159 /* re-initialize later without compression */
1160 surf->color_initialized = false;
1161 }
1162 }
1163
1164 if (!surf->export_16bpc) {
1165 rctx->framebuffer.export_16bpc = false;
1166 }
1167
1168 if (rtex->fmask.size && rtex->cmask.size) {
1169 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1170 }
1171 }
1172
1173 /* Update alpha-test state dependencies.
1174 * Alpha-test is done on the first colorbuffer only. */
1175 if (state->nr_cbufs) {
1176 bool alphatest_bypass = false;
1177
1178 surf = (struct r600_surface*)state->cbufs[0];
1179 if (surf) {
1180 alphatest_bypass = surf->alphatest_bypass;
1181 }
1182
1183 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1184 rctx->alphatest_state.bypass = alphatest_bypass;
1185 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1186 }
1187 }
1188
1189 /* ZS buffer. */
1190 if (state->zsbuf) {
1191 surf = (struct r600_surface*)state->zsbuf;
1192
1193 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1194
1195 if (!surf->depth_initialized) {
1196 r600_init_depth_surface(rctx, surf);
1197 }
1198
1199 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1200 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1201 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1202 }
1203
1204 if (rctx->db_state.rsurf != surf) {
1205 rctx->db_state.rsurf = surf;
1206 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1207 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1208 }
1209 } else if (rctx->db_state.rsurf) {
1210 rctx->db_state.rsurf = NULL;
1211 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1212 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1213 }
1214
1215 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1216 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1217 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1218 }
1219
1220 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1221 rctx->alphatest_state.bypass = false;
1222 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1223 }
1224
1225 /* Calculate the CS size. */
1226 rctx->framebuffer.atom.num_dw =
1227 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1228
1229 if (rctx->framebuffer.state.nr_cbufs) {
1230 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1231 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1232 }
1233 if (rctx->framebuffer.state.zsbuf) {
1234 rctx->framebuffer.atom.num_dw += 16;
1235 } else if (rctx->screen->b.info.drm_minor >= 18) {
1236 rctx->framebuffer.atom.num_dw += 3;
1237 }
1238 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1239 rctx->framebuffer.atom.num_dw += 2;
1240 }
1241
1242 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1243
1244 r600_set_sample_locations_constant_buffer(rctx);
1245 }
1246
1247 static uint32_t sample_locs_2x[] = {
1248 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1249 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1250 };
1251 static unsigned max_dist_2x = 4;
1252
1253 static uint32_t sample_locs_4x[] = {
1254 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1255 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1256 };
1257 static unsigned max_dist_4x = 6;
1258 static uint32_t sample_locs_8x[] = {
1259 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1260 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1261 };
1262 static unsigned max_dist_8x = 7;
1263
1264 static void r600_get_sample_position(struct pipe_context *ctx,
1265 unsigned sample_count,
1266 unsigned sample_index,
1267 float *out_value)
1268 {
1269 int offset, index;
1270 struct {
1271 int idx:4;
1272 } val;
1273 switch (sample_count) {
1274 case 1:
1275 default:
1276 out_value[0] = out_value[1] = 0.5;
1277 break;
1278 case 2:
1279 offset = 4 * (sample_index * 2);
1280 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1281 out_value[0] = (float)(val.idx + 8) / 16.0f;
1282 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1283 out_value[1] = (float)(val.idx + 8) / 16.0f;
1284 break;
1285 case 4:
1286 offset = 4 * (sample_index * 2);
1287 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1288 out_value[0] = (float)(val.idx + 8) / 16.0f;
1289 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1290 out_value[1] = (float)(val.idx + 8) / 16.0f;
1291 break;
1292 case 8:
1293 offset = 4 * (sample_index % 4 * 2);
1294 index = (sample_index / 4);
1295 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1296 out_value[0] = (float)(val.idx + 8) / 16.0f;
1297 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1298 out_value[1] = (float)(val.idx + 8) / 16.0f;
1299 break;
1300 }
1301 }
1302
1303 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1304 {
1305 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1306 unsigned max_dist = 0;
1307
1308 if (rctx->b.family == CHIP_R600) {
1309 switch (nr_samples) {
1310 default:
1311 nr_samples = 0;
1312 break;
1313 case 2:
1314 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1315 max_dist = max_dist_2x;
1316 break;
1317 case 4:
1318 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1319 max_dist = max_dist_4x;
1320 break;
1321 case 8:
1322 radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1323 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1324 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1325 max_dist = max_dist_8x;
1326 break;
1327 }
1328 } else {
1329 switch (nr_samples) {
1330 default:
1331 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1332 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1333 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1334 nr_samples = 0;
1335 break;
1336 case 2:
1337 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1338 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1339 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1340 max_dist = max_dist_2x;
1341 break;
1342 case 4:
1343 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1344 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1345 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1346 max_dist = max_dist_4x;
1347 break;
1348 case 8:
1349 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1350 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1351 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1352 max_dist = max_dist_8x;
1353 break;
1354 }
1355 }
1356
1357 if (nr_samples > 1) {
1358 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1359 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1360 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1361 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1362 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1363 } else {
1364 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1365 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1366 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1367 }
1368 }
1369
1370 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1371 {
1372 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1373 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1374 unsigned nr_cbufs = state->nr_cbufs;
1375 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1376 unsigned i, sbu = 0;
1377
1378 /* Colorbuffers. */
1379 radeon_set_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1380 for (i = 0; i < nr_cbufs; i++) {
1381 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1382 }
1383 /* set CB_COLOR1_INFO for possible dual-src blending */
1384 if (i == 1 && cb[0]) {
1385 radeon_emit(cs, cb[0]->cb_color_info);
1386 i++;
1387 }
1388 for (; i < 8; i++) {
1389 radeon_emit(cs, 0);
1390 }
1391
1392 if (nr_cbufs) {
1393 for (i = 0; i < nr_cbufs; i++) {
1394 unsigned reloc;
1395
1396 if (!cb[i])
1397 continue;
1398
1399 /* COLOR_BASE */
1400 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1401
1402 reloc = radeon_add_to_buffer_list(&rctx->b,
1403 &rctx->b.gfx,
1404 (struct r600_resource*)cb[i]->base.texture,
1405 RADEON_USAGE_READWRITE,
1406 cb[i]->base.texture->nr_samples > 1 ?
1407 RADEON_PRIO_COLOR_BUFFER_MSAA :
1408 RADEON_PRIO_COLOR_BUFFER);
1409 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1410 radeon_emit(cs, reloc);
1411
1412 /* FMASK */
1413 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1414
1415 reloc = radeon_add_to_buffer_list(&rctx->b,
1416 &rctx->b.gfx,
1417 cb[i]->cb_buffer_fmask,
1418 RADEON_USAGE_READWRITE,
1419 cb[i]->base.texture->nr_samples > 1 ?
1420 RADEON_PRIO_COLOR_BUFFER_MSAA :
1421 RADEON_PRIO_COLOR_BUFFER);
1422 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1423 radeon_emit(cs, reloc);
1424
1425 /* CMASK */
1426 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1427
1428 reloc = radeon_add_to_buffer_list(&rctx->b,
1429 &rctx->b.gfx,
1430 cb[i]->cb_buffer_cmask,
1431 RADEON_USAGE_READWRITE,
1432 cb[i]->base.texture->nr_samples > 1 ?
1433 RADEON_PRIO_COLOR_BUFFER_MSAA :
1434 RADEON_PRIO_COLOR_BUFFER);
1435 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1436 radeon_emit(cs, reloc);
1437 }
1438
1439 radeon_set_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1440 for (i = 0; i < nr_cbufs; i++) {
1441 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1442 }
1443
1444 radeon_set_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1445 for (i = 0; i < nr_cbufs; i++) {
1446 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1447 }
1448
1449 radeon_set_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1450 for (i = 0; i < nr_cbufs; i++) {
1451 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1452 }
1453
1454 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1455 }
1456
1457 /* SURFACE_BASE_UPDATE */
1458 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1459 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1460 radeon_emit(cs, sbu);
1461 sbu = 0;
1462 }
1463
1464 /* Zbuffer. */
1465 if (state->zsbuf) {
1466 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1467 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1468 &rctx->b.gfx,
1469 (struct r600_resource*)state->zsbuf->texture,
1470 RADEON_USAGE_READWRITE,
1471 surf->base.texture->nr_samples > 1 ?
1472 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1473 RADEON_PRIO_DEPTH_BUFFER);
1474
1475 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1476 surf->pa_su_poly_offset_db_fmt_cntl);
1477
1478 radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1479 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1480 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1481 radeon_set_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1482 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1483 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1484
1485 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1486 radeon_emit(cs, reloc);
1487
1488 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1489
1490 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1491 } else if (rctx->screen->b.info.drm_minor >= 18) {
1492 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1493 * Older kernels are out of luck. */
1494 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1495 }
1496
1497 /* SURFACE_BASE_UPDATE */
1498 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1499 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1500 radeon_emit(cs, sbu);
1501 sbu = 0;
1502 }
1503
1504 /* Framebuffer dimensions. */
1505 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1506 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1507 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1508 radeon_emit(cs, S_028244_BR_X(state->width) |
1509 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1510
1511 if (rctx->framebuffer.is_msaa_resolve) {
1512 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1513 } else {
1514 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1515 * will assure that the alpha-test will work even if there is
1516 * no colorbuffer bound. */
1517 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1518 (1ull << MAX2(nr_cbufs, 1)) - 1);
1519 }
1520
1521 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1522 }
1523
1524 static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1525 {
1526 struct r600_context *rctx = (struct r600_context *)ctx;
1527
1528 if (rctx->ps_iter_samples == min_samples)
1529 return;
1530
1531 rctx->ps_iter_samples = min_samples;
1532 if (rctx->framebuffer.nr_samples > 1) {
1533 r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom);
1534 if (rctx->b.chip_class == R600)
1535 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1536 }
1537 }
1538
1539 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1540 {
1541 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1542 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1543
1544 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1545 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1546 if (rctx->b.chip_class == R600) {
1547 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1548 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1549 } else {
1550 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1551 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1552 }
1553 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1554 } else {
1555 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1556 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1557 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1558
1559 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1560 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1561 /* Always enable the first color output to make sure alpha-test works even without one. */
1562 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1563 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1564 a->cb_color_control |
1565 S_028808_MULTIWRITE_ENABLE(multiwrite));
1566 }
1567 }
1568
1569 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1570 {
1571 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1572 struct r600_db_state *a = (struct r600_db_state*)atom;
1573
1574 if (a->rsurf && a->rsurf->db_htile_surface) {
1575 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1576 unsigned reloc_idx;
1577
1578 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1579 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1580 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1581 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1582 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1583 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1584 cs->buf[cs->cdw++] = reloc_idx;
1585 } else {
1586 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1587 }
1588 }
1589
1590 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1591 {
1592 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1593 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1594 unsigned db_render_control = 0;
1595 unsigned db_render_override =
1596 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1597 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1598
1599 if (rctx->b.chip_class >= R700) {
1600 switch (a->ps_conservative_z) {
1601 default: /* fall through */
1602 case TGSI_FS_DEPTH_LAYOUT_ANY:
1603 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_ANY_Z);
1604 break;
1605 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1606 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_GREATER_THAN_Z);
1607 break;
1608 case TGSI_FS_DEPTH_LAYOUT_LESS:
1609 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_LESS_THAN_Z);
1610 break;
1611 }
1612 }
1613
1614 if (rctx->b.num_occlusion_queries > 0 &&
1615 !a->occlusion_queries_disabled) {
1616 if (rctx->b.chip_class >= R700) {
1617 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1618 }
1619 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1620 } else {
1621 db_render_control |= S_028D0C_ZPASS_INCREMENT_DISABLE(1);
1622 }
1623
1624 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1625 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1626 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1627 /* This is to fix a lockup when hyperz and alpha test are enabled at
1628 * the same time somehow GPU get confuse on which order to pick for
1629 * z test
1630 */
1631 if (rctx->alphatest_state.sx_alpha_test_control) {
1632 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1633 }
1634 } else {
1635 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1636 }
1637 if (rctx->b.chip_class == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) {
1638 /* sample shading and hyperz causes lockups on R6xx chips */
1639 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1640 }
1641 if (a->flush_depthstencil_through_cb) {
1642 assert(a->copy_depth || a->copy_stencil);
1643
1644 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1645 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1646 S_028D0C_COPY_CENTROID(1) |
1647 S_028D0C_COPY_SAMPLE(a->copy_sample);
1648
1649 if (rctx->b.chip_class == R600)
1650 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1651
1652 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
1653 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
1654 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1655 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1656 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1657 S_028D0C_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1658 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1659 }
1660 if (a->htile_clear) {
1661 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1662 }
1663
1664 /* RV770 workaround for a hang with 8x MSAA. */
1665 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1666 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
1667 }
1668
1669 radeon_set_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1670 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1671 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1672 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1673 }
1674
1675 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1676 {
1677 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1678 struct r600_config_state *a = (struct r600_config_state*)atom;
1679
1680 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1681 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1682 }
1683
1684 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1685 {
1686 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1687 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1688
1689 while (dirty_mask) {
1690 struct pipe_vertex_buffer *vb;
1691 struct r600_resource *rbuffer;
1692 unsigned offset;
1693 unsigned buffer_index = u_bit_scan(&dirty_mask);
1694
1695 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1696 rbuffer = (struct r600_resource*)vb->buffer;
1697 assert(rbuffer);
1698
1699 offset = vb->buffer_offset;
1700
1701 /* fetch resources start at index 320 (OFFSET_FS) */
1702 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1703 radeon_emit(cs, (R600_FETCH_CONSTANTS_OFFSET_FS + buffer_index) * 7);
1704 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1705 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1706 radeon_emit(cs, /* RESOURCEi_WORD2 */
1707 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1708 S_038008_STRIDE(vb->stride));
1709 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1710 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1711 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1712 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1713
1714 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1715 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1716 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1717 }
1718 }
1719
1720 static void r600_emit_constant_buffers(struct r600_context *rctx,
1721 struct r600_constbuf_state *state,
1722 unsigned buffer_id_base,
1723 unsigned reg_alu_constbuf_size,
1724 unsigned reg_alu_const_cache)
1725 {
1726 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1727 uint32_t dirty_mask = state->dirty_mask;
1728
1729 while (dirty_mask) {
1730 struct pipe_constant_buffer *cb;
1731 struct r600_resource *rbuffer;
1732 unsigned offset;
1733 unsigned buffer_index = ffs(dirty_mask) - 1;
1734 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1735 cb = &state->cb[buffer_index];
1736 rbuffer = (struct r600_resource*)cb->buffer;
1737 assert(rbuffer);
1738
1739 offset = cb->buffer_offset;
1740
1741 if (!gs_ring_buffer) {
1742 radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1743 DIV_ROUND_UP(cb->buffer_size, 256));
1744 radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1745 }
1746
1747 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1748 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1749 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1750
1751 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1752 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1753 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1754 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1755 radeon_emit(cs, /* RESOURCEi_WORD2 */
1756 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1757 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1758 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1759 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1760 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1761 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1762
1763 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1764 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1765 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1766
1767 dirty_mask &= ~(1 << buffer_index);
1768 }
1769 state->dirty_mask = 0;
1770 }
1771
1772 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1773 {
1774 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1775 R600_FETCH_CONSTANTS_OFFSET_VS,
1776 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1777 R_028980_ALU_CONST_CACHE_VS_0);
1778 }
1779
1780 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1781 {
1782 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1783 R600_FETCH_CONSTANTS_OFFSET_GS,
1784 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1785 R_0289C0_ALU_CONST_CACHE_GS_0);
1786 }
1787
1788 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1789 {
1790 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1791 R600_FETCH_CONSTANTS_OFFSET_PS,
1792 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1793 R_028940_ALU_CONST_CACHE_PS_0);
1794 }
1795
1796 static void r600_emit_sampler_views(struct r600_context *rctx,
1797 struct r600_samplerview_state *state,
1798 unsigned resource_id_base)
1799 {
1800 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1801 uint32_t dirty_mask = state->dirty_mask;
1802
1803 while (dirty_mask) {
1804 struct r600_pipe_sampler_view *rview;
1805 unsigned resource_index = u_bit_scan(&dirty_mask);
1806 unsigned reloc;
1807
1808 rview = state->views[resource_index];
1809 assert(rview);
1810
1811 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1812 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1813 radeon_emit_array(cs, rview->tex_resource_words, 7);
1814
1815 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
1816 RADEON_USAGE_READ,
1817 r600_get_sampler_view_priority(rview->tex_resource));
1818 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1819 radeon_emit(cs, reloc);
1820 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1821 radeon_emit(cs, reloc);
1822 }
1823 state->dirty_mask = 0;
1824 }
1825
1826
1827 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1828 {
1829 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, R600_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS);
1830 }
1831
1832 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1833 {
1834 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, R600_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS);
1835 }
1836
1837 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1838 {
1839 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS);
1840 }
1841
1842 static void r600_emit_sampler_states(struct r600_context *rctx,
1843 struct r600_textures_info *texinfo,
1844 unsigned resource_id_base,
1845 unsigned border_color_reg)
1846 {
1847 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1848 uint32_t dirty_mask = texinfo->states.dirty_mask;
1849
1850 while (dirty_mask) {
1851 struct r600_pipe_sampler_state *rstate;
1852 struct r600_pipe_sampler_view *rview;
1853 unsigned i = u_bit_scan(&dirty_mask);
1854
1855 rstate = texinfo->states.states[i];
1856 assert(rstate);
1857 rview = texinfo->views.views[i];
1858
1859 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1860 * filtering between layers.
1861 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1862 */
1863 if (rview) {
1864 enum pipe_texture_target target = rview->base.texture->target;
1865 if (target == PIPE_TEXTURE_1D_ARRAY ||
1866 target == PIPE_TEXTURE_2D_ARRAY) {
1867 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1868 texinfo->is_array_sampler[i] = true;
1869 } else {
1870 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1871 texinfo->is_array_sampler[i] = false;
1872 }
1873 }
1874
1875 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1876 radeon_emit(cs, (resource_id_base + i) * 3);
1877 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1878
1879 if (rstate->border_color_use) {
1880 unsigned offset;
1881
1882 offset = border_color_reg;
1883 offset += i * 16;
1884 radeon_set_config_reg_seq(cs, offset, 4);
1885 radeon_emit_array(cs, rstate->border_color.ui, 4);
1886 }
1887 }
1888 texinfo->states.dirty_mask = 0;
1889 }
1890
1891 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1892 {
1893 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1894 }
1895
1896 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1897 {
1898 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1899 }
1900
1901 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1902 {
1903 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1904 }
1905
1906 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1907 {
1908 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1909 unsigned tmp;
1910
1911 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1912 S_009508_SYNC_GRADIENT(1) |
1913 S_009508_SYNC_WALKER(1) |
1914 S_009508_SYNC_ALIGNER(1);
1915 if (!rctx->seamless_cube_map.enabled) {
1916 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1917 }
1918 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1919 }
1920
1921 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1922 {
1923 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1924 uint8_t mask = s->sample_mask;
1925
1926 radeon_set_context_reg(rctx->b.gfx.cs, R_028C48_PA_SC_AA_MASK,
1927 mask | (mask << 8) | (mask << 16) | (mask << 24));
1928 }
1929
1930 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1931 {
1932 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1933 struct r600_cso_state *state = (struct r600_cso_state*)a;
1934 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1935
1936 radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1937 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1938 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
1939 RADEON_USAGE_READ,
1940 RADEON_PRIO_INTERNAL_SHADER));
1941 }
1942
1943 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1944 {
1945 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1946 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1947
1948 uint32_t v2 = 0, primid = 0;
1949
1950 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
1951 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1952 primid = 1;
1953 }
1954
1955 if (state->geom_enable) {
1956 uint32_t cut_val;
1957
1958 if (rctx->gs_shader->gs_max_out_vertices <= 128)
1959 cut_val = V_028A40_GS_CUT_128;
1960 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
1961 cut_val = V_028A40_GS_CUT_256;
1962 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
1963 cut_val = V_028A40_GS_CUT_512;
1964 else
1965 cut_val = V_028A40_GS_CUT_1024;
1966
1967 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1968 S_028A40_CUT_MODE(cut_val);
1969
1970 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1971 primid = 1;
1972 }
1973
1974 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1975 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
1976 }
1977
1978 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1979 {
1980 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1981 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
1982 struct r600_resource *rbuffer;
1983
1984 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1985 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1986 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1987
1988 if (state->enable) {
1989 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
1990 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
1991 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1992 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1993 RADEON_USAGE_READWRITE,
1994 RADEON_PRIO_RINGS_STREAMOUT));
1995 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1996 state->esgs_ring.buffer_size >> 8);
1997
1998 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
1999 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
2000 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2001 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2002 RADEON_USAGE_READWRITE,
2003 RADEON_PRIO_RINGS_STREAMOUT));
2004 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2005 state->gsvs_ring.buffer_size >> 8);
2006 } else {
2007 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2008 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2009 }
2010
2011 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2012 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2013 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2014 }
2015
2016 /* Adjust GPR allocation on R6xx/R7xx */
2017 bool r600_adjust_gprs(struct r600_context *rctx)
2018 {
2019 unsigned num_gprs[R600_NUM_HW_STAGES];
2020 unsigned new_gprs[R600_NUM_HW_STAGES];
2021 unsigned cur_gprs[R600_NUM_HW_STAGES];
2022 unsigned def_gprs[R600_NUM_HW_STAGES];
2023 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2024 unsigned max_gprs;
2025 unsigned tmp, tmp2;
2026 unsigned i;
2027 bool need_recalc = false, use_default = true;
2028
2029 /* hardware will reserve twice num_clause_temp_gprs */
2030 max_gprs = def_num_clause_temp_gprs * 2;
2031 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2032 def_gprs[i] = rctx->default_gprs[i];
2033 max_gprs += def_gprs[i];
2034 }
2035
2036 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2037 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2038 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2039 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2040
2041 num_gprs[R600_HW_STAGE_PS] = rctx->ps_shader->current->shader.bc.ngpr;
2042 if (rctx->gs_shader) {
2043 num_gprs[R600_HW_STAGE_ES] = rctx->vs_shader->current->shader.bc.ngpr;
2044 num_gprs[R600_HW_STAGE_GS] = rctx->gs_shader->current->shader.bc.ngpr;
2045 num_gprs[R600_HW_STAGE_VS] = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2046 } else {
2047 num_gprs[R600_HW_STAGE_ES] = 0;
2048 num_gprs[R600_HW_STAGE_GS] = 0;
2049 num_gprs[R600_HW_STAGE_VS] = rctx->vs_shader->current->shader.bc.ngpr;
2050 }
2051
2052 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2053 new_gprs[i] = num_gprs[i];
2054 if (new_gprs[i] > cur_gprs[i])
2055 need_recalc = true;
2056 if (new_gprs[i] > def_gprs[i])
2057 use_default = false;
2058 }
2059
2060 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2061 if (!need_recalc)
2062 return true;
2063
2064 /* try to use switch back to default */
2065 if (!use_default) {
2066 /* always privilege vs stage so that at worst we have the
2067 * pixel stage producing wrong output (not the vertex
2068 * stage) */
2069 new_gprs[R600_HW_STAGE_PS] = max_gprs - def_num_clause_temp_gprs * 2;
2070 for (i = R600_HW_STAGE_VS; i < R600_NUM_HW_STAGES; i++)
2071 new_gprs[R600_HW_STAGE_PS] -= new_gprs[i];
2072 } else {
2073 for (i = 0; i < R600_NUM_HW_STAGES; i++)
2074 new_gprs[i] = def_gprs[i];
2075 }
2076
2077 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2078 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2079 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2080 * it will lockup. So in this case just discard the draw command
2081 * and don't change the current gprs repartitions.
2082 */
2083 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2084 if (num_gprs[i] > new_gprs[i]) {
2085 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2086 "for a combined maximum of %d\n",
2087 num_gprs[R600_HW_STAGE_PS], num_gprs[R600_HW_STAGE_VS], num_gprs[R600_HW_STAGE_ES], num_gprs[R600_HW_STAGE_GS], max_gprs);
2088 return false;
2089 }
2090 }
2091
2092 /* in some case we endup recomputing the current value */
2093 tmp = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
2094 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
2095 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2096
2097 tmp2 = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
2098 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
2099 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2100 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2101 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2102 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
2103 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2104 }
2105 return true;
2106 }
2107
2108 void r600_init_atom_start_cs(struct r600_context *rctx)
2109 {
2110 int ps_prio;
2111 int vs_prio;
2112 int gs_prio;
2113 int es_prio;
2114 int num_ps_gprs;
2115 int num_vs_gprs;
2116 int num_gs_gprs;
2117 int num_es_gprs;
2118 int num_temp_gprs;
2119 int num_ps_threads;
2120 int num_vs_threads;
2121 int num_gs_threads;
2122 int num_es_threads;
2123 int num_ps_stack_entries;
2124 int num_vs_stack_entries;
2125 int num_gs_stack_entries;
2126 int num_es_stack_entries;
2127 enum radeon_family family;
2128 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2129 uint32_t tmp, i;
2130
2131 r600_init_command_buffer(cb, 256);
2132
2133 /* R6xx requires this packet at the start of each command buffer */
2134 if (rctx->b.chip_class == R600) {
2135 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2136 r600_store_value(cb, 0);
2137 }
2138 /* All asics require this one */
2139 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2140 r600_store_value(cb, 0x80000000);
2141 r600_store_value(cb, 0x80000000);
2142
2143 /* We're setting config registers here. */
2144 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2145 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2146
2147 /* This enables pipeline stat & streamout queries.
2148 * They are only disabled by blits.
2149 */
2150 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2151 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2152
2153 family = rctx->b.family;
2154 ps_prio = 0;
2155 vs_prio = 1;
2156 gs_prio = 2;
2157 es_prio = 3;
2158 switch (family) {
2159 case CHIP_R600:
2160 num_ps_gprs = 192;
2161 num_vs_gprs = 56;
2162 num_temp_gprs = 4;
2163 num_gs_gprs = 0;
2164 num_es_gprs = 0;
2165 num_ps_threads = 136;
2166 num_vs_threads = 48;
2167 num_gs_threads = 4;
2168 num_es_threads = 4;
2169 num_ps_stack_entries = 128;
2170 num_vs_stack_entries = 128;
2171 num_gs_stack_entries = 0;
2172 num_es_stack_entries = 0;
2173 break;
2174 case CHIP_RV630:
2175 case CHIP_RV635:
2176 num_ps_gprs = 84;
2177 num_vs_gprs = 36;
2178 num_temp_gprs = 4;
2179 num_gs_gprs = 0;
2180 num_es_gprs = 0;
2181 num_ps_threads = 144;
2182 num_vs_threads = 40;
2183 num_gs_threads = 4;
2184 num_es_threads = 4;
2185 num_ps_stack_entries = 40;
2186 num_vs_stack_entries = 40;
2187 num_gs_stack_entries = 32;
2188 num_es_stack_entries = 16;
2189 break;
2190 case CHIP_RV610:
2191 case CHIP_RV620:
2192 case CHIP_RS780:
2193 case CHIP_RS880:
2194 default:
2195 num_ps_gprs = 84;
2196 num_vs_gprs = 36;
2197 num_temp_gprs = 4;
2198 num_gs_gprs = 0;
2199 num_es_gprs = 0;
2200 /* use limits 40 VS and at least 16 ES/GS */
2201 num_ps_threads = 120;
2202 num_vs_threads = 40;
2203 num_gs_threads = 16;
2204 num_es_threads = 16;
2205 num_ps_stack_entries = 40;
2206 num_vs_stack_entries = 40;
2207 num_gs_stack_entries = 32;
2208 num_es_stack_entries = 16;
2209 break;
2210 case CHIP_RV670:
2211 num_ps_gprs = 144;
2212 num_vs_gprs = 40;
2213 num_temp_gprs = 4;
2214 num_gs_gprs = 0;
2215 num_es_gprs = 0;
2216 num_ps_threads = 136;
2217 num_vs_threads = 48;
2218 num_gs_threads = 4;
2219 num_es_threads = 4;
2220 num_ps_stack_entries = 40;
2221 num_vs_stack_entries = 40;
2222 num_gs_stack_entries = 32;
2223 num_es_stack_entries = 16;
2224 break;
2225 case CHIP_RV770:
2226 num_ps_gprs = 130;
2227 num_vs_gprs = 56;
2228 num_temp_gprs = 4;
2229 num_gs_gprs = 31;
2230 num_es_gprs = 31;
2231 num_ps_threads = 180;
2232 num_vs_threads = 60;
2233 num_gs_threads = 4;
2234 num_es_threads = 4;
2235 num_ps_stack_entries = 128;
2236 num_vs_stack_entries = 128;
2237 num_gs_stack_entries = 128;
2238 num_es_stack_entries = 128;
2239 break;
2240 case CHIP_RV730:
2241 case CHIP_RV740:
2242 num_ps_gprs = 84;
2243 num_vs_gprs = 36;
2244 num_temp_gprs = 4;
2245 num_gs_gprs = 0;
2246 num_es_gprs = 0;
2247 num_ps_threads = 180;
2248 num_vs_threads = 60;
2249 num_gs_threads = 4;
2250 num_es_threads = 4;
2251 num_ps_stack_entries = 128;
2252 num_vs_stack_entries = 128;
2253 num_gs_stack_entries = 0;
2254 num_es_stack_entries = 0;
2255 break;
2256 case CHIP_RV710:
2257 num_ps_gprs = 192;
2258 num_vs_gprs = 56;
2259 num_temp_gprs = 4;
2260 num_gs_gprs = 0;
2261 num_es_gprs = 0;
2262 num_ps_threads = 136;
2263 num_vs_threads = 48;
2264 num_gs_threads = 4;
2265 num_es_threads = 4;
2266 num_ps_stack_entries = 128;
2267 num_vs_stack_entries = 128;
2268 num_gs_stack_entries = 0;
2269 num_es_stack_entries = 0;
2270 break;
2271 }
2272
2273 rctx->default_gprs[R600_HW_STAGE_PS] = num_ps_gprs;
2274 rctx->default_gprs[R600_HW_STAGE_VS] = num_vs_gprs;
2275 rctx->default_gprs[R600_HW_STAGE_GS] = 0;
2276 rctx->default_gprs[R600_HW_STAGE_ES] = 0;
2277
2278 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2279
2280 /* SQ_CONFIG */
2281 tmp = 0;
2282 switch (family) {
2283 case CHIP_RV610:
2284 case CHIP_RV620:
2285 case CHIP_RS780:
2286 case CHIP_RS880:
2287 case CHIP_RV710:
2288 break;
2289 default:
2290 tmp |= S_008C00_VC_ENABLE(1);
2291 break;
2292 }
2293 tmp |= S_008C00_DX9_CONSTS(0);
2294 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2295 tmp |= S_008C00_PS_PRIO(ps_prio);
2296 tmp |= S_008C00_VS_PRIO(vs_prio);
2297 tmp |= S_008C00_GS_PRIO(gs_prio);
2298 tmp |= S_008C00_ES_PRIO(es_prio);
2299 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2300
2301 /* SQ_GPR_RESOURCE_MGMT_2 */
2302 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2303 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2304 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2305 r600_store_value(cb, tmp);
2306
2307 /* SQ_THREAD_RESOURCE_MGMT */
2308 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2309 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2310 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2311 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2312 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2313
2314 /* SQ_STACK_RESOURCE_MGMT_1 */
2315 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2316 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2317 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2318
2319 /* SQ_STACK_RESOURCE_MGMT_2 */
2320 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2321 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2322 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2323
2324 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2325
2326 if (rctx->b.chip_class >= R700) {
2327 r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4);
2328 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2329 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2330 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2331 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2332 } else {
2333 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2334 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2335 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2336 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2337 }
2338 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2339 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2340 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2341 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2342 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2343 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2344 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2345 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2346 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2347 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2348
2349 /* to avoid GPU doing any preloading of constant from random address */
2350 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2351 for (i = 0; i < 16; i++)
2352 r600_store_value(cb, 0);
2353
2354 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2355 for (i = 0; i < 16; i++)
2356 r600_store_value(cb, 0);
2357
2358 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2359 for (i = 0; i < 16; i++)
2360 r600_store_value(cb, 0);
2361
2362 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2363 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2364 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2365 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2366 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2367 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2368 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2369 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2370 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2371 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2372 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2373 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2374 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2375 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2376
2377 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2378 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2379 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2380
2381 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2382 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2383 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2384
2385 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2386
2387 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2388
2389 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2390
2391 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2392 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2393 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2394 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2395
2396 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2397 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2398 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2399 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2400
2401 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2402 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2403
2404 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2405 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2406 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2407 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2408 }
2409
2410 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2411 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2412
2413 if (rctx->b.chip_class >= R700) {
2414 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2415 }
2416
2417 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2418 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2419 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2420 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2421 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2422
2423 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2424 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2425 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2426
2427 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2428 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2429 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2430
2431 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2432 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2433 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2434 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2435 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2436 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2437
2438 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2439
2440 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2441 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2442 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2443
2444 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2445
2446 if (rctx->b.chip_class == R700)
2447 r600_store_context_reg(cb, R_028350_SX_MISC, 0);
2448 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2449 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2450
2451 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2452 if (rctx->screen->b.has_streamout) {
2453 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2454 }
2455
2456 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2457 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2458 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2459 }
2460
2461 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2462 {
2463 struct r600_context *rctx = (struct r600_context *)ctx;
2464 struct r600_command_buffer *cb = &shader->command_buffer;
2465 struct r600_shader *rshader = &shader->shader;
2466 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2467 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2468 unsigned tmp, sid, ufi = 0;
2469 int need_linear = 0;
2470 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2471 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2472
2473 if (!cb->buf) {
2474 r600_init_command_buffer(cb, 64);
2475 } else {
2476 cb->num_dw = 0;
2477 }
2478
2479 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2480 for (i = 0; i < rshader->ninput; i++) {
2481 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2482 pos_index = i;
2483 if (rshader->input[i].name == TGSI_SEMANTIC_FACE && face_index == -1)
2484 face_index = i;
2485 if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID)
2486 fixed_pt_position_index = i;
2487
2488 sid = rshader->input[i].spi_sid;
2489
2490 tmp = S_028644_SEMANTIC(sid);
2491
2492 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2493 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2494 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2495 rctx->rasterizer && rctx->rasterizer->flatshade))
2496 tmp |= S_028644_FLAT_SHADE(1);
2497
2498 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2499 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2500 tmp |= S_028644_PT_SPRITE_TEX(1);
2501 }
2502
2503 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID)
2504 tmp |= S_028644_SEL_CENTROID(1);
2505
2506 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE)
2507 tmp |= S_028644_SEL_SAMPLE(1);
2508
2509 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2510 need_linear = 1;
2511 tmp |= S_028644_SEL_LINEAR(1);
2512 }
2513
2514 r600_store_value(cb, tmp);
2515 }
2516
2517 db_shader_control = 0;
2518 for (i = 0; i < rshader->noutput; i++) {
2519 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2520 z_export = 1;
2521 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2522 stencil_export = 1;
2523 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
2524 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
2525 mask_export = 1;
2526 }
2527 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2528 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2529 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
2530 if (rshader->uses_kill)
2531 db_shader_control |= S_02880C_KILL_ENABLE(1);
2532
2533 exports_ps = 0;
2534 for (i = 0; i < rshader->noutput; i++) {
2535 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2536 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
2537 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2538 exports_ps |= 1;
2539 }
2540 }
2541 num_cout = rshader->nr_ps_color_exports;
2542 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2543 if (!exports_ps) {
2544 /* always at least export 1 component per pixel */
2545 exports_ps = 2;
2546 }
2547
2548 shader->nr_ps_color_outputs = num_cout;
2549
2550 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2551 S_0286CC_PERSP_GRADIENT_ENA(1)|
2552 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2553 spi_input_z = 0;
2554 if (pos_index != -1) {
2555 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2556 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
2557 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2558 S_0286CC_BARYC_SAMPLE_CNTL(1)) |
2559 S_0286CC_POSITION_SAMPLE(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE);
2560 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2561 }
2562
2563 spi_ps_in_control_1 = 0;
2564 if (face_index != -1) {
2565 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2566 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2567 }
2568 if (fixed_pt_position_index != -1) {
2569 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2570 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
2571 }
2572
2573 /* HW bug in original R600 */
2574 if (rctx->b.family == CHIP_R600)
2575 ufi = 1;
2576
2577 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2578 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2579 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2580
2581 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2582
2583 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2584 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2585 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2586 S_028850_STACK_SIZE(rshader->bc.nstack) |
2587 S_028850_UNCACHED_FIRST_INST(ufi));
2588 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2589
2590 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2591 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2592
2593 /* only set some bits here, the other bits are set in the dsa state */
2594 shader->db_shader_control = db_shader_control;
2595 shader->ps_depth_export = z_export | stencil_export | mask_export;
2596
2597 shader->sprite_coord_enable = sprite_coord_enable;
2598 if (rctx->rasterizer)
2599 shader->flatshade = rctx->rasterizer->flatshade;
2600 }
2601
2602 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2603 {
2604 struct r600_command_buffer *cb = &shader->command_buffer;
2605 struct r600_shader *rshader = &shader->shader;
2606 unsigned spi_vs_out_id[10] = {};
2607 unsigned i, tmp, nparams = 0;
2608
2609 for (i = 0; i < rshader->noutput; i++) {
2610 if (rshader->output[i].spi_sid) {
2611 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2612 spi_vs_out_id[nparams / 4] |= tmp;
2613 nparams++;
2614 }
2615 }
2616
2617 r600_init_command_buffer(cb, 32);
2618
2619 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2620 for (i = 0; i < 10; i++) {
2621 r600_store_value(cb, spi_vs_out_id[i]);
2622 }
2623
2624 /* Certain attributes (position, psize, etc.) don't count as params.
2625 * VS is required to export at least one param and r600_shader_from_tgsi()
2626 * takes care of adding a dummy export.
2627 */
2628 if (nparams < 1)
2629 nparams = 1;
2630
2631 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2632 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2633 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2634 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2635 S_028868_STACK_SIZE(rshader->bc.nstack));
2636 if (rshader->vs_position_window_space) {
2637 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2638 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2639 } else {
2640 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2641 S_028818_VTX_W0_FMT(1) |
2642 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2643 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2644 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2645
2646 }
2647 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2648 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2649
2650 shader->pa_cl_vs_out_cntl =
2651 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2652 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2653 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2654 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2655 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2656 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2657 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2658 }
2659
2660 #define RV610_GSVS_ALIGN 32
2661 #define R600_GSVS_ALIGN 16
2662
2663 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2664 {
2665 struct r600_context *rctx = (struct r600_context *)ctx;
2666 struct r600_command_buffer *cb = &shader->command_buffer;
2667 struct r600_shader *rshader = &shader->shader;
2668 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2669 unsigned gsvs_itemsize =
2670 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2;
2671
2672 /* some r600s needs gsvs itemsize aligned to cacheline size
2673 this was fixed in rs780 and above. */
2674 switch (rctx->b.family) {
2675 case CHIP_RV610:
2676 gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN);
2677 break;
2678 case CHIP_R600:
2679 case CHIP_RV630:
2680 case CHIP_RV670:
2681 case CHIP_RV620:
2682 case CHIP_RV635:
2683 gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN);
2684 break;
2685 default:
2686 break;
2687 }
2688
2689 r600_init_command_buffer(cb, 64);
2690
2691 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2692 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2693
2694 if (rctx->b.chip_class >= R700) {
2695 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2696 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
2697 }
2698 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2699 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
2700
2701 r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE,
2702 cp_shader->ring_item_sizes[0] >> 2);
2703
2704 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2705 (rshader->ring_item_sizes[0]) >> 2);
2706
2707 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2708 gsvs_itemsize);
2709
2710 /* FIXME calculate these values somehow ??? */
2711 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2712 r600_store_value(cb, 0x80); /* GS_PER_ES */
2713 r600_store_value(cb, 0x100); /* ES_PER_GS */
2714 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2715 r600_store_value(cb, 0x2); /* GS_PER_VS */
2716
2717 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2718 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2719 S_02887C_STACK_SIZE(rshader->bc.nstack));
2720 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0);
2721 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2722 }
2723
2724 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2725 {
2726 struct r600_command_buffer *cb = &shader->command_buffer;
2727 struct r600_shader *rshader = &shader->shader;
2728
2729 r600_init_command_buffer(cb, 32);
2730
2731 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2732 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2733 S_028890_STACK_SIZE(rshader->bc.nstack));
2734 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0);
2735 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2736 }
2737
2738
2739 void *r600_create_resolve_blend(struct r600_context *rctx)
2740 {
2741 struct pipe_blend_state blend;
2742 unsigned i;
2743
2744 memset(&blend, 0, sizeof(blend));
2745 blend.independent_blend_enable = true;
2746 for (i = 0; i < 2; i++) {
2747 blend.rt[i].colormask = 0xf;
2748 blend.rt[i].blend_enable = 1;
2749 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2750 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2751 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2752 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2753 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2754 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2755 }
2756 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2757 }
2758
2759 void *r700_create_resolve_blend(struct r600_context *rctx)
2760 {
2761 struct pipe_blend_state blend;
2762
2763 memset(&blend, 0, sizeof(blend));
2764 blend.independent_blend_enable = true;
2765 blend.rt[0].colormask = 0xf;
2766 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2767 }
2768
2769 void *r600_create_decompress_blend(struct r600_context *rctx)
2770 {
2771 struct pipe_blend_state blend;
2772
2773 memset(&blend, 0, sizeof(blend));
2774 blend.independent_blend_enable = true;
2775 blend.rt[0].colormask = 0xf;
2776 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2777 }
2778
2779 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2780 {
2781 struct pipe_depth_stencil_alpha_state dsa;
2782 boolean quirk = false;
2783
2784 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2785 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2786 quirk = true;
2787
2788 memset(&dsa, 0, sizeof(dsa));
2789
2790 if (quirk) {
2791 dsa.depth.enabled = 1;
2792 dsa.depth.func = PIPE_FUNC_LEQUAL;
2793 dsa.stencil[0].enabled = 1;
2794 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2795 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2796 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2797 dsa.stencil[0].writemask = 0xff;
2798 }
2799
2800 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2801 }
2802
2803 void r600_update_db_shader_control(struct r600_context * rctx)
2804 {
2805 bool dual_export;
2806 unsigned db_shader_control;
2807 uint8_t ps_conservative_z;
2808
2809 if (!rctx->ps_shader) {
2810 return;
2811 }
2812
2813 dual_export = rctx->framebuffer.export_16bpc &&
2814 !rctx->ps_shader->current->ps_depth_export;
2815
2816 db_shader_control = rctx->ps_shader->current->db_shader_control |
2817 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2818
2819 ps_conservative_z = rctx->ps_shader->current->shader.ps_conservative_z;
2820
2821 /* When alpha test is enabled we can't trust the hw to make the proper
2822 * decision on the order in which ztest should be run related to fragment
2823 * shader execution.
2824 *
2825 * If alpha test is enabled perform z test after fragment. RE_Z (early
2826 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2827 */
2828 if (rctx->alphatest_state.sx_alpha_test_control) {
2829 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2830 } else {
2831 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2832 }
2833
2834 if (db_shader_control != rctx->db_misc_state.db_shader_control ||
2835 ps_conservative_z != rctx->db_misc_state.ps_conservative_z) {
2836 rctx->db_misc_state.db_shader_control = db_shader_control;
2837 rctx->db_misc_state.ps_conservative_z = ps_conservative_z;
2838 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2839 }
2840 }
2841
2842 static inline unsigned r600_array_mode(unsigned mode)
2843 {
2844 switch (mode) {
2845 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2846 break;
2847 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2848 break;
2849 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2850 default:
2851 case RADEON_SURF_MODE_LINEAR: return V_0280A0_ARRAY_LINEAR_GENERAL;
2852 }
2853 }
2854
2855 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2856 struct pipe_resource *dst,
2857 unsigned dst_level,
2858 unsigned dst_x,
2859 unsigned dst_y,
2860 unsigned dst_z,
2861 struct pipe_resource *src,
2862 unsigned src_level,
2863 unsigned src_x,
2864 unsigned src_y,
2865 unsigned src_z,
2866 unsigned copy_height,
2867 unsigned pitch,
2868 unsigned bpp)
2869 {
2870 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
2871 struct r600_texture *rsrc = (struct r600_texture*)src;
2872 struct r600_texture *rdst = (struct r600_texture*)dst;
2873 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2874 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2875 uint64_t base, addr;
2876
2877 dst_mode = rdst->surface.level[dst_level].mode;
2878 src_mode = rsrc->surface.level[src_level].mode;
2879 /* downcast linear aligned to linear to simplify test */
2880 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2881 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2882 assert(dst_mode != src_mode);
2883
2884 y = 0;
2885 lbpp = util_logbase2(bpp);
2886 pitch_tile_max = ((pitch / bpp) / 8) - 1;
2887
2888 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
2889 /* T2L */
2890 array_mode = r600_array_mode(src_mode);
2891 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
2892 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2893 /* linear height must be the same as the slice tile max height, it's ok even
2894 * if the linear destination/source have smaller heigh as the size of the
2895 * dma packet will be using the copy_height which is always smaller or equal
2896 * to the linear height
2897 */
2898 height = rsrc->surface.level[src_level].npix_y;
2899 detile = 1;
2900 x = src_x;
2901 y = src_y;
2902 z = src_z;
2903 base = rsrc->surface.level[src_level].offset;
2904 addr = rdst->surface.level[dst_level].offset;
2905 addr += rdst->surface.level[dst_level].slice_size * dst_z;
2906 addr += dst_y * pitch + dst_x * bpp;
2907 } else {
2908 /* L2T */
2909 array_mode = r600_array_mode(dst_mode);
2910 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
2911 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2912 /* linear height must be the same as the slice tile max height, it's ok even
2913 * if the linear destination/source have smaller heigh as the size of the
2914 * dma packet will be using the copy_height which is always smaller or equal
2915 * to the linear height
2916 */
2917 height = rdst->surface.level[dst_level].npix_y;
2918 detile = 0;
2919 x = dst_x;
2920 y = dst_y;
2921 z = dst_z;
2922 base = rdst->surface.level[dst_level].offset;
2923 addr = rsrc->surface.level[src_level].offset;
2924 addr += rsrc->surface.level[src_level].slice_size * src_z;
2925 addr += src_y * pitch + src_x * bpp;
2926 }
2927 /* check that we are in dw/base alignment constraint */
2928 if (addr % 4 || base % 256) {
2929 return FALSE;
2930 }
2931
2932 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2933 * line in the blit. Compute max 8 line we can copy in the size limit
2934 */
2935 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2936 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2937 r600_need_dma_space(&rctx->b, ncopy * 7);
2938
2939 for (i = 0; i < ncopy; i++) {
2940 cheight = cheight > copy_height ? copy_height : cheight;
2941 size = (cheight * pitch) / 4;
2942 /* emit reloc before writing cs so that cs is always in consistent state */
2943 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ,
2944 RADEON_PRIO_SDMA_TEXTURE);
2945 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE,
2946 RADEON_PRIO_SDMA_TEXTURE);
2947 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
2948 cs->buf[cs->cdw++] = base >> 8;
2949 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
2950 (lbpp << 24) | ((height - 1) << 10) |
2951 pitch_tile_max;
2952 cs->buf[cs->cdw++] = (slice_tile_max << 12) | (z << 0);
2953 cs->buf[cs->cdw++] = (x << 3) | (y << 17);
2954 cs->buf[cs->cdw++] = addr & 0xfffffffc;
2955 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
2956 copy_height -= cheight;
2957 addr += cheight * pitch;
2958 y += cheight;
2959 }
2960 return TRUE;
2961 }
2962
2963 static void r600_dma_copy(struct pipe_context *ctx,
2964 struct pipe_resource *dst,
2965 unsigned dst_level,
2966 unsigned dstx, unsigned dsty, unsigned dstz,
2967 struct pipe_resource *src,
2968 unsigned src_level,
2969 const struct pipe_box *src_box)
2970 {
2971 struct r600_context *rctx = (struct r600_context *)ctx;
2972 struct r600_texture *rsrc = (struct r600_texture*)src;
2973 struct r600_texture *rdst = (struct r600_texture*)dst;
2974 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2975 unsigned src_w, dst_w;
2976 unsigned src_x, src_y;
2977 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
2978
2979 if (rctx->b.dma.cs == NULL) {
2980 goto fallback;
2981 }
2982
2983 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
2984 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
2985 goto fallback;
2986
2987 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
2988 return;
2989 }
2990
2991 if (src->format != dst->format || src_box->depth > 1) {
2992 goto fallback;
2993 }
2994
2995 src_x = util_format_get_nblocksx(src->format, src_box->x);
2996 dst_x = util_format_get_nblocksx(src->format, dst_x);
2997 src_y = util_format_get_nblocksy(src->format, src_box->y);
2998 dst_y = util_format_get_nblocksy(src->format, dst_y);
2999
3000 bpp = rdst->surface.bpe;
3001 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3002 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3003 src_w = rsrc->surface.level[src_level].npix_x;
3004 dst_w = rdst->surface.level[dst_level].npix_x;
3005 copy_height = src_box->height / rsrc->surface.blk_h;
3006
3007 dst_mode = rdst->surface.level[dst_level].mode;
3008 src_mode = rsrc->surface.level[src_level].mode;
3009 /* downcast linear aligned to linear to simplify test */
3010 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3011 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3012
3013 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3014 /* strict requirement on r6xx/r7xx */
3015 goto fallback;
3016 }
3017 /* lot of constraint on alignment this should capture them all */
3018 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
3019 goto fallback;
3020 }
3021
3022 if (src_mode == dst_mode) {
3023 uint64_t dst_offset, src_offset, size;
3024
3025 /* simple dma blit would do NOTE code here assume :
3026 * src_box.x/y == 0
3027 * dst_x/y == 0
3028 * dst_pitch == src_pitch
3029 */
3030 src_offset= rsrc->surface.level[src_level].offset;
3031 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3032 src_offset += src_y * src_pitch + src_x * bpp;
3033 dst_offset = rdst->surface.level[dst_level].offset;
3034 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3035 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3036 size = src_box->height * src_pitch;
3037 /* must be dw aligned */
3038 if (dst_offset % 4 || src_offset % 4 || size % 4) {
3039 goto fallback;
3040 }
3041 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
3042 } else {
3043 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3044 src, src_level, src_x, src_y, src_box->z,
3045 copy_height, dst_pitch, bpp)) {
3046 goto fallback;
3047 }
3048 }
3049 return;
3050
3051 fallback:
3052 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3053 src, src_level, src_box);
3054 }
3055
3056 void r600_init_state_functions(struct r600_context *rctx)
3057 {
3058 unsigned id = 1;
3059 unsigned i;
3060 /* !!!
3061 * To avoid GPU lockup registers must be emited in a specific order
3062 * (no kidding ...). The order below is important and have been
3063 * partialy infered from analyzing fglrx command stream.
3064 *
3065 * Don't reorder atom without carefully checking the effect (GPU lockup
3066 * or piglit regression).
3067 * !!!
3068 */
3069
3070 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3071
3072 /* shader const */
3073 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3074 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3075 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3076
3077 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3078 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3079 */
3080 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3081 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3082 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3083 /* resource */
3084 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3085 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3086 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3087 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3088
3089 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3090
3091 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3092 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3093 rctx->sample_mask.sample_mask = ~0;
3094
3095 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3096 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3097 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3098 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3099 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3100 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3101 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3102 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3103 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3104 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
3105 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3106 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3107 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3108 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3109 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3110 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3111 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3112 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3113 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3114 for (i = 0; i < R600_NUM_HW_STAGES; i++)
3115 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3116 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3117 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3118
3119 rctx->b.b.create_blend_state = r600_create_blend_state;
3120 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3121 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3122 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3123 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3124 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3125 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3126 rctx->b.b.set_min_samples = r600_set_min_samples;
3127 rctx->b.b.get_sample_position = r600_get_sample_position;
3128 rctx->b.dma_copy = r600_dma_copy;
3129 }
3130 /* this function must be last */