src/gallium/drivers/r600/r600_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /* TODO:
  25  *      - fix mask for depth control & cull for query
  26  */
  27 #include <stdio.h>
  28 #include <errno.h>
  29 #include <pipe/p_defines.h>
  30 #include <pipe/p_state.h>
  31 #include <pipe/p_context.h>
  32 #include <tgsi/tgsi_scan.h>
  33 #include <tgsi/tgsi_parse.h>
  34 #include <tgsi/tgsi_util.h>
  35 #include <util/u_double_list.h>
  36 #include <util/u_pack_color.h>
  37 #include <util/u_memory.h>
  38 #include <util/u_inlines.h>
  39 #include <util/u_upload_mgr.h>
  40 #include <util/u_index_modify.h>
  41 #include <pipebuffer/pb_buffer.h>
  42 #include "r600.h"
  43 #include "r600d.h"
  44 #include "r700_sq.h"
  45 #include "r600_resource.h"
  46 #include "r600_shader.h"
  47 #include "r600_pipe.h"
  48 #include "r600_state_inlines.h"
  49
  50 static void r600_draw_common(struct r600_drawl *draw)
  51 {
  52         struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
  53         struct r600_pipe_state *rstate;
  54         struct r600_resource *rbuffer;
  55         unsigned i, j, offset, prim;
  56         u32 vgt_dma_index_type, vgt_draw_initiator, mask;
  57         struct pipe_vertex_buffer *vertex_buffer;
  58         struct r600_draw rdraw;
  59         struct r600_pipe_state vgt;
  60
  61         switch (draw->index_size) {
  62         case 2:
  63                 vgt_draw_initiator = 0;
  64                 vgt_dma_index_type = 0;
  65                 break;
  66         case 4:
  67                 vgt_draw_initiator = 0;
  68                 vgt_dma_index_type = 1;
  69                 break;
  70         case 0:
  71                 vgt_draw_initiator = 2;
  72                 vgt_dma_index_type = 0;
  73                 break;
  74         default:
  75                 R600_ERR("unsupported index size %d\n", draw->index_size);
  76                 return;
  77         }
  78         if (r600_conv_pipe_prim(draw->mode, &prim))
  79                 return;
  80
  81
  82         /* rebuild vertex shader if input format changed */
  83         if (r600_pipe_shader_update(&rctx->context, rctx->vs_shader))
  84                 return;
  85         if (r600_pipe_shader_update(&rctx->context, rctx->ps_shader))
  86                 return;
  87
  88         for (i = 0 ; i < rctx->vertex_elements->count; i++) {
  89                 uint32_t word2, format;
  90
  91                 rstate = &rctx->vs_resource[i];
  92                 rstate->id = R600_PIPE_STATE_RESOURCE;
  93                 rstate->nregs = 0;
  94
  95                 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
  96                 vertex_buffer = &rctx->vertex_buffer[j];
  97                 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
  98                 offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
  99
 100                 format = r600_translate_vertex_data_type(rctx->vertex_elements->elements[i].src_format);
 101
 102                 word2 = format | S_038008_STRIDE(vertex_buffer->stride);
 103
 104                 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
 105                 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
 106                 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2, word2, 0xFFFFFFFF, NULL);
 107                 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3, 0x00000000, 0xFFFFFFFF, NULL);
 108                 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
 109                 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
 110                 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6, 0xC0000000, 0xFFFFFFFF, NULL);
 111                 r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, i);
 112         }
 113
 114         mask = 0;
 115         for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
 116                 mask |= (0xF << (i * 4));
 117         }
 118
 119         vgt.id = R600_PIPE_STATE_VGT;
 120         vgt.nregs = 0;
 121         r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
 122         r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw->index_bias, 0xFFFFFFFF, NULL);
 123         r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw->max_index, 0xFFFFFFFF, NULL);
 124         r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw->min_index, 0xFFFFFFFF, NULL);
 125         r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
 126         r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
 127         r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
 128         /* build late state */
 129         if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
 130                 float offset_units = rctx->rasterizer->offset_units;
 131                 unsigned offset_db_fmt_cntl = 0, depth;
 132
 133                 switch (rctx->framebuffer.zsbuf->texture->format) {
 134                 case PIPE_FORMAT_Z24X8_UNORM:
 135                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 136                         depth = -24;
 137                         offset_units *= 2.0f;
 138                         break;
 139                 case PIPE_FORMAT_Z32_FLOAT:
 140                         depth = -23;
 141                         offset_units *= 1.0f;
 142                         offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
 143                         break;
 144                 case PIPE_FORMAT_Z16_UNORM:
 145                         depth = -16;
 146                         offset_units *= 4.0f;
 147                         break;
 148                 default:
 149                         return;
 150                 }
 151                 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
 152                 r600_pipe_state_add_reg(&vgt,
 153                                 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
 154                                 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
 155                 r600_pipe_state_add_reg(&vgt,
 156                                 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
 157                                 fui(offset_units), 0xFFFFFFFF, NULL);
 158                 r600_pipe_state_add_reg(&vgt,
 159                                 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
 160                                 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
 161                 r600_pipe_state_add_reg(&vgt,
 162                                 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
 163                                 fui(offset_units), 0xFFFFFFFF, NULL);
 164                 r600_pipe_state_add_reg(&vgt,
 165                                 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
 166                                 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
 167         }
 168         r600_context_pipe_state_set(&rctx->ctx, &vgt);
 169
 170         rdraw.vgt_num_indices = draw->count;
 171         rdraw.vgt_num_instances = 1;
 172         rdraw.vgt_index_type = vgt_dma_index_type;
 173         rdraw.vgt_draw_initiator = vgt_draw_initiator;
 174         rdraw.indices = NULL;
 175         if (draw->index_buffer) {
 176                 rbuffer = (struct r600_resource*)draw->index_buffer;
 177                 rdraw.indices = rbuffer->bo;
 178                 rdraw.indices_bo_offset = draw->index_buffer_offset;
 179         }
 180         r600_context_draw(&rctx->ctx, &rdraw);
 181 }
 182
 183 void r600_translate_index_buffer(struct r600_pipe_context *r600,
 184                                         struct pipe_resource **index_buffer,
 185                                         unsigned *index_size,
 186                                         unsigned *start, unsigned count)
 187 {
 188         switch (*index_size) {
 189         case 1:
 190                 util_shorten_ubyte_elts(&r600->context, index_buffer, 0, *start, count);
 191                 *index_size = 2;
 192                 *start = 0;
 193                 break;
 194
 195         case 2:
 196                 if (*start % 2 != 0) {
 197                         util_rebuild_ushort_elts(&r600->context, index_buffer, 0, *start, count);
 198                         *start = 0;
 199                 }
 200                 break;
 201
 202         case 4:
 203                 break;
 204         }
 205 }
 206
 207 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 208 {
 209         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 210         struct r600_drawl draw;
 211
 212         if (rctx->any_user_vbs) {
 213                 r600_upload_user_buffers(rctx);
 214                 rctx->any_user_vbs = FALSE;
 215         }
 216
 217         memset(&draw, 0, sizeof(struct r600_drawl));
 218         draw.ctx = ctx;
 219         draw.mode = info->mode;
 220         draw.start = info->start;
 221         draw.count = info->count;
 222         if (info->indexed && rctx->index_buffer.buffer) {
 223                 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
 224                 draw.min_index = info->min_index;
 225                 draw.max_index = info->max_index;
 226                 draw.index_bias = info->index_bias;
 227
 228                 r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
 229                                             &rctx->index_buffer.index_size,
 230                                             &draw.start,
 231                                             info->count);
 232
 233                 draw.index_size = rctx->index_buffer.index_size;
 234                 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
 235                 draw.index_buffer_offset = draw.start * draw.index_size;
 236                 draw.start = 0;
 237                 r600_upload_index_buffer(rctx, &draw);
 238         } else {
 239                 draw.index_size = 0;
 240                 draw.index_buffer = NULL;
 241                 draw.min_index = info->min_index;
 242                 draw.max_index = info->max_index;
 243                 draw.index_bias = info->start;
 244         }
 245         r600_draw_common(&draw);
 246
 247         pipe_resource_reference(&draw.index_buffer, NULL);
 248 }
 249
 250 static void r600_set_blend_color(struct pipe_context *ctx,
 251                                         const struct pipe_blend_color *state)
 252 {
 253         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 254         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 255
 256         if (rstate == NULL)
 257                 return;
 258
 259         rstate->id = R600_PIPE_STATE_BLEND_COLOR;
 260         r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
 261         r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
 262         r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
 263         r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
 264         free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
 265         rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
 266         r600_context_pipe_state_set(&rctx->ctx, rstate);
 267 }
 268
 269 static void *r600_create_blend_state(struct pipe_context *ctx,
 270                                         const struct pipe_blend_state *state)
 271 {
 272         struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
 273         struct r600_pipe_state *rstate;
 274         u32 color_control, target_mask;
 275
 276         if (blend == NULL) {
 277                 return NULL;
 278         }
 279         rstate = &blend->rstate;
 280
 281         rstate->id = R600_PIPE_STATE_BLEND;
 282
 283         target_mask = 0;
 284         color_control = S_028808_PER_MRT_BLEND(1);
 285         if (state->logicop_enable) {
 286                 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
 287         } else {
 288                 color_control |= (0xcc << 16);
 289         }
 290         /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
 291         if (state->independent_blend_enable) {
 292                 for (int i = 0; i < 8; i++) {
 293                         if (state->rt[i].blend_enable) {
 294                                 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 295                         }
 296                         target_mask |= (state->rt[i].colormask << (4 * i));
 297                 }
 298         } else {
 299                 for (int i = 0; i < 8; i++) {
 300                         if (state->rt[0].blend_enable) {
 301                                 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 302                         }
 303                         target_mask |= (state->rt[0].colormask << (4 * i));
 304                 }
 305         }
 306         blend->cb_target_mask = target_mask;
 307         r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
 308                                 color_control, 0xFFFFFFFF, NULL);
 309
 310         for (int i = 0; i < 8; i++) {
 311                 unsigned eqRGB = state->rt[i].rgb_func;
 312                 unsigned srcRGB = state->rt[i].rgb_src_factor;
 313                 unsigned dstRGB = state->rt[i].rgb_dst_factor;
 314
 315                 unsigned eqA = state->rt[i].alpha_func;
 316                 unsigned srcA = state->rt[i].alpha_src_factor;
 317                 unsigned dstA = state->rt[i].alpha_dst_factor;
 318                 uint32_t bc = 0;
 319
 320                 if (!state->rt[i].blend_enable)
 321                         continue;
 322
 323                 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
 324                 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
 325                 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
 326
 327                 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 328                         bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
 329                         bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
 330                         bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
 331                         bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
 332                 }
 333
 334                 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
 335                 if (i == 0) {
 336                         r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
 337                 }
 338         }
 339         return rstate;
 340 }
 341
 342 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 343 {
 344         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 345         struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
 346         struct r600_pipe_state *rstate;
 347
 348         if (state == NULL)
 349                 return;
 350         rstate = &blend->rstate;
 351         rctx->states[rstate->id] = rstate;
 352         rctx->cb_target_mask = blend->cb_target_mask;
 353         r600_context_pipe_state_set(&rctx->ctx, rstate);
 354 }
 355
 356 static void *r600_create_dsa_state(struct pipe_context *ctx,
 357                                    const struct pipe_depth_stencil_alpha_state *state)
 358 {
 359         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 360         unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
 361         unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
 362
 363         if (rstate == NULL) {
 364                 return NULL;
 365         }
 366
 367         rstate->id = R600_PIPE_STATE_DSA;
 368         /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
 369         /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
 370          * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
 371          * be set if shader use texkill instruction
 372          */
 373         db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
 374         stencil_ref_mask = 0;
 375         stencil_ref_mask_bf = 0;
 376         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 377                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 378                 S_028800_ZFUNC(state->depth.func);
 379
 380         /* stencil */
 381         if (state->stencil[0].enabled) {
 382                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 383                 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
 384                 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 385                 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 386                 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
 387
 388
 389                 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
 390                         S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
 391                 if (state->stencil[1].enabled) {
 392                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 393                         db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
 394                         db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 395                         db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 396                         db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
 397                         stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
 398                                 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
 399                 }
 400         }
 401
 402         /* alpha */
 403         alpha_test_control = 0;
 404         alpha_ref = 0;
 405         if (state->alpha.enabled) {
 406                 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
 407                 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
 408                 alpha_ref = fui(state->alpha.ref_value);
 409         }
 410
 411         /* misc */
 412         db_render_control = 0;
 413         db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
 414                 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
 415                 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
 416         /* TODO db_render_override depends on query */
 417         r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
 418         r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
 419         r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
 420         r600_pipe_state_add_reg(rstate,
 421                                 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
 422                                 0xFFFFFFFF & C_028430_STENCILREF, NULL);
 423         r600_pipe_state_add_reg(rstate,
 424                                 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
 425                                 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
 426         r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
 427         r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
 428         r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
 429         r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
 430         r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
 431         r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
 432         r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
 433         r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
 434         r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
 435         r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
 436         r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
 437
 438         return rstate;
 439 }
 440
 441 static void *r600_create_rs_state(struct pipe_context *ctx,
 442                                         const struct pipe_rasterizer_state *state)
 443 {
 444         struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
 445         struct r600_pipe_state *rstate;
 446         unsigned tmp;
 447         unsigned prov_vtx = 1, polygon_dual_mode;
 448
 449         if (rs == NULL) {
 450                 return NULL;
 451         }
 452
 453         rstate = &rs->rstate;
 454         rs->flatshade = state->flatshade;
 455         rs->sprite_coord_enable = state->sprite_coord_enable;
 456
 457         /* offset */
 458         rs->offset_units = state->offset_units;
 459         rs->offset_scale = state->offset_scale * 12.0f;
 460
 461         rstate->id = R600_PIPE_STATE_RASTERIZER;
 462         if (state->flatshade_first)
 463                 prov_vtx = 0;
 464         tmp = 0x00000001;
 465         if (state->sprite_coord_enable) {
 466                 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
 467                         S_0286D4_PNT_SPRITE_OVRD_X(2) |
 468                         S_0286D4_PNT_SPRITE_OVRD_Y(3) |
 469                         S_0286D4_PNT_SPRITE_OVRD_Z(0) |
 470                         S_0286D4_PNT_SPRITE_OVRD_W(1);
 471                 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
 472                         tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
 473                 }
 474         }
 475         r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
 476
 477         polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
 478                                 state->fill_back != PIPE_POLYGON_MODE_FILL);
 479         r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
 480                 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
 481                 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 482                 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
 483                 S_028814_FACE(!state->front_ccw) |
 484                 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
 485                 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
 486                 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
 487                 S_028814_POLY_MODE(polygon_dual_mode) |
 488                 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
 489                 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
 490         r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
 491                         S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
 492                         S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
 493         r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
 494         /* point size 12.4 fixed point */
 495         tmp = (unsigned)(state->point_size * 8.0);
 496         r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
 497         r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
 498         r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
 499         r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
 500         r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
 501         r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
 502         r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 503         r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 504         r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 505         r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 506         r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
 507         return rstate;
 508 }
 509
 510 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 511 {
 512         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 513         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 514
 515         if (state == NULL)
 516                 return;
 517
 518         rctx->flatshade = rs->flatshade;
 519         rctx->sprite_coord_enable = rs->sprite_coord_enable;
 520         rctx->rasterizer = rs;
 521
 522         rctx->states[rs->rstate.id] = &rs->rstate;
 523         r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
 524 }
 525
 526 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 527 {
 528         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 529         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 530
 531         if (rctx->rasterizer == rs) {
 532                 rctx->rasterizer = NULL;
 533         }
 534         if (rctx->states[rs->rstate.id] == &rs->rstate) {
 535                 rctx->states[rs->rstate.id] = NULL;
 536         }
 537         free(rs);
 538 }
 539
 540 static void *r600_create_sampler_state(struct pipe_context *ctx,
 541                                         const struct pipe_sampler_state *state)
 542 {
 543         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 544         union util_color uc;
 545
 546         if (rstate == NULL) {
 547                 return NULL;
 548         }
 549
 550         rstate->id = R600_PIPE_STATE_SAMPLER;
 551         util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
 552         r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
 553                         S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 554                         S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
 555                         S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
 556                         S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
 557                         S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
 558                         S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
 559                         S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
 560                         S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
 561         /* FIXME LOD it depends on texture base level ... */
 562         r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
 563                         S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
 564                         S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
 565                         S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
 566         r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
 567         if (uc.ui) {
 568                 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
 569                 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
 570                 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
 571                 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
 572         }
 573         return rstate;
 574 }
 575
 576 static void *r600_create_vertex_elements(struct pipe_context *ctx,
 577                                 unsigned count,
 578                                 const struct pipe_vertex_element *elements)
 579 {
 580         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 581
 582         assert(count < 32);
 583         v->count = count;
 584         v->refcount = 1;
 585         memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
 586         return v;
 587 }
 588
 589 static void r600_sampler_view_destroy(struct pipe_context *ctx,
 590                                       struct pipe_sampler_view *state)
 591 {
 592         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 593
 594         pipe_resource_reference(&state->texture, NULL);
 595         FREE(resource);
 596 }
 597
 598 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
 599                                                         struct pipe_resource *texture,
 600                                                         const struct pipe_sampler_view *state)
 601 {
 602         struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
 603         struct r600_pipe_state *rstate;
 604         const struct util_format_description *desc;
 605         struct r600_resource_texture *tmp;
 606         struct r600_resource *rbuffer;
 607         unsigned format;
 608         uint32_t word4 = 0, yuv_format = 0, pitch = 0;
 609         unsigned char swizzle[4], array_mode = 0, tile_type = 0;
 610         struct radeon_ws_bo *bo[2];
 611
 612         if (resource == NULL)
 613                 return NULL;
 614         rstate = &resource->state;
 615
 616         /* initialize base object */
 617         resource->base = *state;
 618         resource->base.texture = NULL;
 619         pipe_reference(NULL, &texture->reference);
 620         resource->base.texture = texture;
 621         resource->base.reference.count = 1;
 622         resource->base.context = ctx;
 623
 624         swizzle[0] = state->swizzle_r;
 625         swizzle[1] = state->swizzle_g;
 626         swizzle[2] = state->swizzle_b;
 627         swizzle[3] = state->swizzle_a;
 628         format = r600_translate_texformat(texture->format,
 629                                           swizzle,
 630                                           &word4, &yuv_format);
 631         if (format == ~0) {
 632                 format = 0;
 633         }
 634         desc = util_format_description(texture->format);
 635         if (desc == NULL) {
 636                 R600_ERR("unknow format %d\n", texture->format);
 637         }
 638         tmp = (struct r600_resource_texture*)texture;
 639         rbuffer = &tmp->resource;
 640         bo[0] = rbuffer->bo;
 641         bo[1] = rbuffer->bo;
 642         /* FIXME depth texture decompression */
 643         if (tmp->depth) {
 644                 r600_texture_depth_flush(ctx, texture);
 645                 tmp = (struct r600_resource_texture*)texture;
 646                 rbuffer = &tmp->flushed_depth_texture->resource;
 647                 bo[0] = rbuffer->bo;
 648                 bo[1] = rbuffer->bo;
 649         }
 650         pitch = align(tmp->pitch[0] / tmp->bpt, 8);
 651
 652         /* FIXME properly handle first level != 0 */
 653         r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
 654                                 S_038000_DIM(r600_tex_dim(texture->target)) |
 655                                 S_038000_TILE_MODE(array_mode) |
 656                                 S_038000_TILE_TYPE(tile_type) |
 657                                 S_038000_PITCH((pitch / 8) - 1) |
 658                                 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
 659         r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
 660                                 S_038004_TEX_HEIGHT(texture->height0 - 1) |
 661                                 S_038004_TEX_DEPTH(texture->depth0 - 1) |
 662                                 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
 663         r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
 664                                 tmp->offset[0] >> 8, 0xFFFFFFFF, bo[0]);
 665         r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
 666                                 tmp->offset[1] >> 8, 0xFFFFFFFF, bo[1]);
 667         r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
 668                                 word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
 669                                 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
 670                                 S_038010_REQUEST_SIZE(1) |
 671                                 S_038010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
 672         r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
 673                                 S_038014_LAST_LEVEL(state->last_level) |
 674                                 S_038014_BASE_ARRAY(0) |
 675                                 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
 676         r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
 677                                 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
 678
 679         return &resource->base;
 680 }
 681
 682 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
 683                                         struct pipe_sampler_view **views)
 684 {
 685         /* TODO */
 686         assert(1);
 687 }
 688
 689 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
 690                                         struct pipe_sampler_view **views)
 691 {
 692         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 693         struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
 694
 695         for (int i = 0; i < count; i++) {
 696                 if (resource[i]) {
 697                         r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
 698                 }
 699         }
 700 }
 701
 702 static void r600_bind_state(struct pipe_context *ctx, void *state)
 703 {
 704         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 705         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 706
 707         if (state == NULL)
 708                 return;
 709         rctx->states[rstate->id] = rstate;
 710         r600_context_pipe_state_set(&rctx->ctx, rstate);
 711 }
 712
 713 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
 714 {
 715         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 716         struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
 717
 718         for (int i = 0; i < count; i++) {
 719                 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
 720         }
 721 }
 722
 723 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
 724 {
 725         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 726         struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
 727
 728         /* TODO implement */
 729         for (int i = 0; i < count; i++) {
 730                 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
 731         }
 732 }
 733
 734 static void r600_delete_state(struct pipe_context *ctx, void *state)
 735 {
 736         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 737         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 738
 739         if (rctx->states[rstate->id] == rstate) {
 740                 rctx->states[rstate->id] = NULL;
 741         }
 742         for (int i = 0; i < rstate->nregs; i++) {
 743                 radeon_ws_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
 744         }
 745         free(rstate);
 746 }
 747
 748 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 749 {
 750         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 751
 752         if (v == NULL)
 753                 return;
 754         if (--v->refcount)
 755                 return;
 756         free(v);
 757 }
 758
 759 static void r600_set_clip_state(struct pipe_context *ctx,
 760                                 const struct pipe_clip_state *state)
 761 {
 762         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 763         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 764
 765         if (rstate == NULL)
 766                 return;
 767
 768         rctx->clip = *state;
 769         rstate->id = R600_PIPE_STATE_CLIP;
 770         for (int i = 0; i < state->nr; i++) {
 771                 r600_pipe_state_add_reg(rstate,
 772                                         R_028E20_PA_CL_UCP0_X + i * 4,
 773                                         fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
 774                 r600_pipe_state_add_reg(rstate,
 775                                         R_028E24_PA_CL_UCP0_Y + i * 4,
 776                                         fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
 777                 r600_pipe_state_add_reg(rstate,
 778                                         R_028E28_PA_CL_UCP0_Z + i * 4,
 779                                         fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
 780                 r600_pipe_state_add_reg(rstate,
 781                                         R_028E2C_PA_CL_UCP0_W + i * 4,
 782                                         fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
 783         }
 784         r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
 785                         S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
 786                         S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
 787                         S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
 788
 789         free(rctx->states[R600_PIPE_STATE_CLIP]);
 790         rctx->states[R600_PIPE_STATE_CLIP] = rstate;
 791         r600_context_pipe_state_set(&rctx->ctx, rstate);
 792 }
 793
 794 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 795 {
 796         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 797         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 798
 799         r600_delete_vertex_element(ctx, rctx->vertex_elements);
 800         rctx->vertex_elements = v;
 801         if (v) {
 802                 v->refcount++;
 803 //              rctx->vs_rebuild = TRUE;
 804         }
 805 }
 806
 807 static void r600_set_polygon_stipple(struct pipe_context *ctx,
 808                                          const struct pipe_poly_stipple *state)
 809 {
 810 }
 811
 812 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
 813 {
 814 }
 815
 816 static void r600_set_scissor_state(struct pipe_context *ctx,
 817                                         const struct pipe_scissor_state *state)
 818 {
 819         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 820         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 821         u32 tl, br;
 822
 823         if (rstate == NULL)
 824                 return;
 825
 826         rstate->id = R600_PIPE_STATE_SCISSOR;
 827         tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
 828         br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
 829         r600_pipe_state_add_reg(rstate,
 830                                 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
 831                                 0xFFFFFFFF, NULL);
 832         r600_pipe_state_add_reg(rstate,
 833                                 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
 834                                 0xFFFFFFFF, NULL);
 835         r600_pipe_state_add_reg(rstate,
 836                                 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
 837                                 0xFFFFFFFF, NULL);
 838         r600_pipe_state_add_reg(rstate,
 839                                 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
 840                                 0xFFFFFFFF, NULL);
 841         r600_pipe_state_add_reg(rstate,
 842                                 R_028210_PA_SC_CLIPRECT_0_TL, tl,
 843                                 0xFFFFFFFF, NULL);
 844         r600_pipe_state_add_reg(rstate,
 845                                 R_028214_PA_SC_CLIPRECT_0_BR, br,
 846                                 0xFFFFFFFF, NULL);
 847         r600_pipe_state_add_reg(rstate,
 848                                 R_028218_PA_SC_CLIPRECT_1_TL, tl,
 849                                 0xFFFFFFFF, NULL);
 850         r600_pipe_state_add_reg(rstate,
 851                                 R_02821C_PA_SC_CLIPRECT_1_BR, br,
 852                                 0xFFFFFFFF, NULL);
 853         r600_pipe_state_add_reg(rstate,
 854                                 R_028220_PA_SC_CLIPRECT_2_TL, tl,
 855                                 0xFFFFFFFF, NULL);
 856         r600_pipe_state_add_reg(rstate,
 857                                 R_028224_PA_SC_CLIPRECT_2_BR, br,
 858                                 0xFFFFFFFF, NULL);
 859         r600_pipe_state_add_reg(rstate,
 860                                 R_028228_PA_SC_CLIPRECT_3_TL, tl,
 861                                 0xFFFFFFFF, NULL);
 862         r600_pipe_state_add_reg(rstate,
 863                                 R_02822C_PA_SC_CLIPRECT_3_BR, br,
 864                                 0xFFFFFFFF, NULL);
 865         r600_pipe_state_add_reg(rstate,
 866                                 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
 867                                 0xFFFFFFFF, NULL);
 868         r600_pipe_state_add_reg(rstate,
 869                                 R_02820C_PA_SC_CLIPRECT_RULE, 0x0000FFFF,
 870                                 0xFFFFFFFF, NULL);
 871         if (rctx->family >= CHIP_RV770) {
 872                 r600_pipe_state_add_reg(rstate,
 873                                         R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
 874                                         0xFFFFFFFF, NULL);
 875         }
 876
 877         free(rctx->states[R600_PIPE_STATE_SCISSOR]);
 878         rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
 879         r600_context_pipe_state_set(&rctx->ctx, rstate);
 880 }
 881
 882 static void r600_set_stencil_ref(struct pipe_context *ctx,
 883                                 const struct pipe_stencil_ref *state)
 884 {
 885         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 886         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 887         u32 tmp;
 888
 889         if (rstate == NULL)
 890                 return;
 891
 892         rctx->stencil_ref = *state;
 893         rstate->id = R600_PIPE_STATE_STENCIL_REF;
 894         tmp = S_028430_STENCILREF(state->ref_value[0]);
 895         r600_pipe_state_add_reg(rstate,
 896                                 R_028430_DB_STENCILREFMASK, tmp,
 897                                 ~C_028430_STENCILREF, NULL);
 898         tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
 899         r600_pipe_state_add_reg(rstate,
 900                                 R_028434_DB_STENCILREFMASK_BF, tmp,
 901                                 ~C_028434_STENCILREF_BF, NULL);
 902
 903         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
 904         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
 905         r600_context_pipe_state_set(&rctx->ctx, rstate);
 906 }
 907
 908 static void r600_set_viewport_state(struct pipe_context *ctx,
 909                                         const struct pipe_viewport_state *state)
 910 {
 911         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 912         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 913
 914         if (rstate == NULL)
 915                 return;
 916
 917         rctx->viewport = *state;
 918         rstate->id = R600_PIPE_STATE_VIEWPORT;
 919         r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
 920         r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
 921         r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
 922         r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
 923         r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
 924         r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
 925         r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
 926         r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
 927         r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
 928
 929         free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
 930         rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
 931         r600_context_pipe_state_set(&rctx->ctx, rstate);
 932 }
 933
 934 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
 935                         const struct pipe_framebuffer_state *state, int cb)
 936 {
 937         struct r600_resource_texture *rtex;
 938         struct r600_resource *rbuffer;
 939         unsigned level = state->cbufs[cb]->level;
 940         unsigned pitch, slice;
 941         unsigned color_info;
 942         unsigned format, swap, ntype;
 943         const struct util_format_description *desc;
 944         struct radeon_ws_bo *bo[3];
 945
 946         rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
 947         rbuffer = &rtex->resource;
 948         bo[0] = rbuffer->bo;
 949         bo[1] = rbuffer->bo;
 950         bo[2] = rbuffer->bo;
 951
 952         pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
 953         slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
 954         ntype = 0;
 955         desc = util_format_description(rtex->resource.base.b.format);
 956         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
 957                 ntype = V_0280A0_NUMBER_SRGB;
 958
 959         format = r600_translate_colorformat(rtex->resource.base.b.format);
 960         swap = r600_translate_colorswap(rtex->resource.base.b.format);
 961         color_info = S_0280A0_FORMAT(format) |
 962                 S_0280A0_COMP_SWAP(swap) |
 963                 S_0280A0_BLEND_CLAMP(1) |
 964                 S_0280A0_NUMBER_TYPE(ntype);
 965         if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
 966                 color_info |= S_0280A0_SOURCE_FORMAT(1);
 967
 968         r600_pipe_state_add_reg(rstate,
 969                                 R_028040_CB_COLOR0_BASE + cb * 4,
 970                                 state->cbufs[cb]->offset >> 8, 0xFFFFFFFF, bo[0]);
 971         r600_pipe_state_add_reg(rstate,
 972                                 R_0280A0_CB_COLOR0_INFO + cb * 4,
 973                                 color_info, 0xFFFFFFFF, bo[0]);
 974         r600_pipe_state_add_reg(rstate,
 975                                 R_028060_CB_COLOR0_SIZE + cb * 4,
 976                                 S_028060_PITCH_TILE_MAX(pitch) |
 977                                 S_028060_SLICE_TILE_MAX(slice),
 978                                 0xFFFFFFFF, NULL);
 979         r600_pipe_state_add_reg(rstate,
 980                                 R_028080_CB_COLOR0_VIEW + cb * 4,
 981                                 0x00000000, 0xFFFFFFFF, NULL);
 982         r600_pipe_state_add_reg(rstate,
 983                                 R_0280E0_CB_COLOR0_FRAG + cb * 4,
 984                                 0x00000000, 0xFFFFFFFF, bo[1]);
 985         r600_pipe_state_add_reg(rstate,
 986                                 R_0280C0_CB_COLOR0_TILE + cb * 4,
 987                                 0x00000000, 0xFFFFFFFF, bo[2]);
 988         r600_pipe_state_add_reg(rstate,
 989                                 R_028100_CB_COLOR0_MASK + cb * 4,
 990                                 0x00000000, 0xFFFFFFFF, NULL);
 991 }
 992
 993 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
 994                         const struct pipe_framebuffer_state *state)
 995 {
 996         struct r600_resource_texture *rtex;
 997         struct r600_resource *rbuffer;
 998         unsigned level;
 999         unsigned pitch, slice, format;
1000
1001         if (state->zsbuf == NULL)
1002                 return;
1003
1004         rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1005         rtex->tiled = 1;
1006         rtex->array_mode = 2;
1007         rtex->tile_type = 1;
1008         rtex->depth = 1;
1009         rbuffer = &rtex->resource;
1010
1011         level = state->zsbuf->level;
1012         pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
1013         slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
1014         format = r600_translate_dbformat(state->zsbuf->texture->format);
1015
1016         r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1017                                 state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
1018         r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1019                                 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1020                                 0xFFFFFFFF, NULL);
1021         r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
1022         r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1023                                 S_028010_ARRAY_MODE(rtex->array_mode) | S_028010_FORMAT(format),
1024                                 0xFFFFFFFF, rbuffer->bo);
1025         r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1026                                 (state->zsbuf->height / 8) - 1, 0xFFFFFFFF, NULL);
1027 }
1028
1029 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1030                                         const struct pipe_framebuffer_state *state)
1031 {
1032         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1033         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1034         u32 shader_mask, tl, br, shader_control, target_mask;
1035
1036         if (rstate == NULL)
1037                 return;
1038
1039         /* unreference old buffer and reference new one */
1040         rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1041         for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
1042                 pipe_surface_reference(&rctx->framebuffer.cbufs[i], NULL);
1043         }
1044         for (int i = 0; i < state->nr_cbufs; i++) {
1045                 pipe_surface_reference(&rctx->framebuffer.cbufs[i], state->cbufs[i]);
1046         }
1047         pipe_surface_reference(&rctx->framebuffer.zsbuf, state->zsbuf);
1048         rctx->framebuffer = *state;
1049         rctx->pframebuffer = &rctx->framebuffer;
1050
1051         /* build states */
1052         for (int i = 0; i < state->nr_cbufs; i++) {
1053                 r600_cb(rctx, rstate, state, i);
1054         }
1055         if (state->zsbuf) {
1056                 r600_db(rctx, rstate, state);
1057         }
1058
1059         target_mask = 0x00000000;
1060         target_mask = 0xFFFFFFFF;
1061         shader_mask = 0;
1062         shader_control = 0;
1063         for (int i = 0; i < state->nr_cbufs; i++) {
1064                 target_mask ^= 0xf << (i * 4);
1065                 shader_mask |= 0xf << (i * 4);
1066                 shader_control |= 1 << i;
1067         }
1068         tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1069         br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1070
1071         r600_pipe_state_add_reg(rstate,
1072                                 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1073                                 0xFFFFFFFF, NULL);
1074         r600_pipe_state_add_reg(rstate,
1075                                 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1076                                 0xFFFFFFFF, NULL);
1077         r600_pipe_state_add_reg(rstate,
1078                                 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1079                                 0xFFFFFFFF, NULL);
1080         r600_pipe_state_add_reg(rstate,
1081                                 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1082                                 0xFFFFFFFF, NULL);
1083
1084         r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1085                                 shader_control, 0xFFFFFFFF, NULL);
1086         r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1087                                 0x00000000, target_mask, NULL);
1088         r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1089                                 shader_mask, 0xFFFFFFFF, NULL);
1090         r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1091                                 0x00000000, 0xFFFFFFFF, NULL);
1092         r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1093                                 0x00000000, 0xFFFFFFFF, NULL);
1094         r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1095                                 0x00000000, 0xFFFFFFFF, NULL);
1096         r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1097                                 0x01000000, 0xFFFFFFFF, NULL);
1098         r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1099                                 0x00000000, 0xFFFFFFFF, NULL);
1100         r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1101                                 0x000000FF, 0xFFFFFFFF, NULL);
1102         r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1103                                 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1104         r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1105                                 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1106
1107         free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1108         rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1109         r600_context_pipe_state_set(&rctx->ctx, rstate);
1110 }
1111
1112 static void r600_set_index_buffer(struct pipe_context *ctx,
1113                                   const struct pipe_index_buffer *ib)
1114 {
1115         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1116
1117         if (ib) {
1118                 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
1119                 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
1120         } else {
1121                 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
1122                 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
1123         }
1124
1125         /* TODO make this more like a state */
1126 }
1127
1128 static void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
1129                                         const struct pipe_vertex_buffer *buffers)
1130 {
1131         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1132
1133         for (int i = 0; i < rctx->nvertex_buffer; i++) {
1134                 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
1135         }
1136         memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
1137         for (int i = 0; i < count; i++) {
1138                 rctx->vertex_buffer[i].buffer = NULL;
1139                 if (r600_buffer_is_user_buffer(buffers[i].buffer))
1140                         rctx->any_user_vbs = TRUE;
1141                 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
1142         }
1143         rctx->nvertex_buffer = count;
1144 }
1145
1146 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
1147                                         struct pipe_resource *buffer)
1148 {
1149         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1150         struct r600_resource *rbuffer = (struct r600_resource*)buffer;
1151
1152         switch (shader) {
1153         case PIPE_SHADER_VERTEX:
1154                 rctx->vs_const_buffer.nregs = 0;
1155                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1156                                         R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1157                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
1158                                         0xFFFFFFFF, NULL);
1159                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1160                                         R_028980_ALU_CONST_CACHE_VS_0,
1161                                         0, 0xFFFFFFFF, rbuffer->bo);
1162                 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
1163                 break;
1164         case PIPE_SHADER_FRAGMENT:
1165                 rctx->ps_const_buffer.nregs = 0;
1166                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1167                                         R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1168                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
1169                                         0xFFFFFFFF, NULL);
1170                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1171                                         R_028940_ALU_CONST_CACHE_PS_0,
1172                                         0, 0xFFFFFFFF, rbuffer->bo);
1173                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
1174                 break;
1175         default:
1176                 R600_ERR("unsupported %d\n", shader);
1177                 return;
1178         }
1179 }
1180
1181 static void *r600_create_shader_state(struct pipe_context *ctx,
1182                                         const struct pipe_shader_state *state)
1183 {
1184         struct r600_pipe_shader *shader =  CALLOC_STRUCT(r600_pipe_shader);
1185         int r;
1186
1187         shader->shader.use_mem_constant = TRUE;
1188         r =  r600_pipe_shader_create(ctx, shader, state->tokens);
1189         if (r) {
1190                 return NULL;
1191         }
1192         return shader;
1193 }
1194
1195 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
1196 {
1197         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1198
1199         /* TODO delete old shader */
1200         rctx->ps_shader = (struct r600_pipe_shader *)state;
1201 }
1202
1203 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
1204 {
1205         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1206
1207         /* TODO delete old shader */
1208         rctx->vs_shader = (struct r600_pipe_shader *)state;
1209 }
1210
1211 static void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
1212 {
1213         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1214         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1215
1216         if (rctx->ps_shader == shader) {
1217                 rctx->ps_shader = NULL;
1218         }
1219         /* TODO proper delete */
1220         free(shader);
1221 }
1222
1223 static void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
1224 {
1225         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1226         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1227
1228         if (rctx->vs_shader == shader) {
1229                 rctx->vs_shader = NULL;
1230         }
1231         /* TODO proper delete */
1232         free(shader);
1233 }
1234
1235 void r600_init_state_functions(struct r600_pipe_context *rctx)
1236 {
1237         rctx->context.create_blend_state = r600_create_blend_state;
1238         rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1239         rctx->context.create_fs_state = r600_create_shader_state;
1240         rctx->context.create_rasterizer_state = r600_create_rs_state;
1241         rctx->context.create_sampler_state = r600_create_sampler_state;
1242         rctx->context.create_sampler_view = r600_create_sampler_view;
1243         rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1244         rctx->context.create_vs_state = r600_create_shader_state;
1245         rctx->context.bind_blend_state = r600_bind_blend_state;
1246         rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
1247         rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
1248         rctx->context.bind_fs_state = r600_bind_ps_shader;
1249         rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1250         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1251         rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
1252         rctx->context.bind_vs_state = r600_bind_vs_shader;
1253         rctx->context.delete_blend_state = r600_delete_state;
1254         rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1255         rctx->context.delete_fs_state = r600_delete_ps_shader;
1256         rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1257         rctx->context.delete_sampler_state = r600_delete_state;
1258         rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1259         rctx->context.delete_vs_state = r600_delete_vs_shader;
1260         rctx->context.set_blend_color = r600_set_blend_color;
1261         rctx->context.set_clip_state = r600_set_clip_state;
1262         rctx->context.set_constant_buffer = r600_set_constant_buffer;
1263         rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1264         rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1265         rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1266         rctx->context.set_sample_mask = r600_set_sample_mask;
1267         rctx->context.set_scissor_state = r600_set_scissor_state;
1268         rctx->context.set_stencil_ref = r600_set_stencil_ref;
1269         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1270         rctx->context.set_index_buffer = r600_set_index_buffer;
1271         rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1272         rctx->context.set_viewport_state = r600_set_viewport_state;
1273         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1274 }
1275
1276 void r600_init_config(struct r600_pipe_context *rctx)
1277 {
1278         int ps_prio;
1279         int vs_prio;
1280         int gs_prio;
1281         int es_prio;
1282         int num_ps_gprs;
1283         int num_vs_gprs;
1284         int num_gs_gprs;
1285         int num_es_gprs;
1286         int num_temp_gprs;
1287         int num_ps_threads;
1288         int num_vs_threads;
1289         int num_gs_threads;
1290         int num_es_threads;
1291         int num_ps_stack_entries;
1292         int num_vs_stack_entries;
1293         int num_gs_stack_entries;
1294         int num_es_stack_entries;
1295         enum radeon_family family;
1296         struct r600_pipe_state *rstate = &rctx->config;
1297         u32 tmp;
1298
1299         family = r600_get_family(rctx->radeon);
1300         ps_prio = 0;
1301         vs_prio = 1;
1302         gs_prio = 2;
1303         es_prio = 3;
1304         switch (family) {
1305         case CHIP_R600:
1306                 num_ps_gprs = 192;
1307                 num_vs_gprs = 56;
1308                 num_temp_gprs = 4;
1309                 num_gs_gprs = 0;
1310                 num_es_gprs = 0;
1311                 num_ps_threads = 136;
1312                 num_vs_threads = 48;
1313                 num_gs_threads = 4;
1314                 num_es_threads = 4;
1315                 num_ps_stack_entries = 128;
1316                 num_vs_stack_entries = 128;
1317                 num_gs_stack_entries = 0;
1318                 num_es_stack_entries = 0;
1319                 break;
1320         case CHIP_RV630:
1321         case CHIP_RV635:
1322                 num_ps_gprs = 84;
1323                 num_vs_gprs = 36;
1324                 num_temp_gprs = 4;
1325                 num_gs_gprs = 0;
1326                 num_es_gprs = 0;
1327                 num_ps_threads = 144;
1328                 num_vs_threads = 40;
1329                 num_gs_threads = 4;
1330                 num_es_threads = 4;
1331                 num_ps_stack_entries = 40;
1332                 num_vs_stack_entries = 40;
1333                 num_gs_stack_entries = 32;
1334                 num_es_stack_entries = 16;
1335                 break;
1336         case CHIP_RV610:
1337         case CHIP_RV620:
1338         case CHIP_RS780:
1339         case CHIP_RS880:
1340         default:
1341                 num_ps_gprs = 84;
1342                 num_vs_gprs = 36;
1343                 num_temp_gprs = 4;
1344                 num_gs_gprs = 0;
1345                 num_es_gprs = 0;
1346                 num_ps_threads = 136;
1347                 num_vs_threads = 48;
1348                 num_gs_threads = 4;
1349                 num_es_threads = 4;
1350                 num_ps_stack_entries = 40;
1351                 num_vs_stack_entries = 40;
1352                 num_gs_stack_entries = 32;
1353                 num_es_stack_entries = 16;
1354                 break;
1355         case CHIP_RV670:
1356                 num_ps_gprs = 144;
1357                 num_vs_gprs = 40;
1358                 num_temp_gprs = 4;
1359                 num_gs_gprs = 0;
1360                 num_es_gprs = 0;
1361                 num_ps_threads = 136;
1362                 num_vs_threads = 48;
1363                 num_gs_threads = 4;
1364                 num_es_threads = 4;
1365                 num_ps_stack_entries = 40;
1366                 num_vs_stack_entries = 40;
1367                 num_gs_stack_entries = 32;
1368                 num_es_stack_entries = 16;
1369                 break;
1370         case CHIP_RV770:
1371                 num_ps_gprs = 192;
1372                 num_vs_gprs = 56;
1373                 num_temp_gprs = 4;
1374                 num_gs_gprs = 0;
1375                 num_es_gprs = 0;
1376                 num_ps_threads = 188;
1377                 num_vs_threads = 60;
1378                 num_gs_threads = 0;
1379                 num_es_threads = 0;
1380                 num_ps_stack_entries = 256;
1381                 num_vs_stack_entries = 256;
1382                 num_gs_stack_entries = 0;
1383                 num_es_stack_entries = 0;
1384                 break;
1385         case CHIP_RV730:
1386         case CHIP_RV740:
1387                 num_ps_gprs = 84;
1388                 num_vs_gprs = 36;
1389                 num_temp_gprs = 4;
1390                 num_gs_gprs = 0;
1391                 num_es_gprs = 0;
1392                 num_ps_threads = 188;
1393                 num_vs_threads = 60;
1394                 num_gs_threads = 0;
1395                 num_es_threads = 0;
1396                 num_ps_stack_entries = 128;
1397                 num_vs_stack_entries = 128;
1398                 num_gs_stack_entries = 0;
1399                 num_es_stack_entries = 0;
1400                 break;
1401         case CHIP_RV710:
1402                 num_ps_gprs = 192;
1403                 num_vs_gprs = 56;
1404                 num_temp_gprs = 4;
1405                 num_gs_gprs = 0;
1406                 num_es_gprs = 0;
1407                 num_ps_threads = 144;
1408                 num_vs_threads = 48;
1409                 num_gs_threads = 0;
1410                 num_es_threads = 0;
1411                 num_ps_stack_entries = 128;
1412                 num_vs_stack_entries = 128;
1413                 num_gs_stack_entries = 0;
1414                 num_es_stack_entries = 0;
1415                 break;
1416         }
1417
1418         rstate->id = R600_PIPE_STATE_CONFIG;
1419
1420         /* SQ_CONFIG */
1421         tmp = 0;
1422         switch (family) {
1423         case CHIP_RV610:
1424         case CHIP_RV620:
1425         case CHIP_RS780:
1426         case CHIP_RS880:
1427         case CHIP_RV710:
1428                 break;
1429         default:
1430                 tmp |= S_008C00_VC_ENABLE(1);
1431                 break;
1432         }
1433         tmp |= S_008C00_DX9_CONSTS(0);
1434         tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1435         tmp |= S_008C00_PS_PRIO(ps_prio);
1436         tmp |= S_008C00_VS_PRIO(vs_prio);
1437         tmp |= S_008C00_GS_PRIO(gs_prio);
1438         tmp |= S_008C00_ES_PRIO(es_prio);
1439         r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1440
1441         /* SQ_GPR_RESOURCE_MGMT_1 */
1442         tmp = 0;
1443         tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1444         tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1445         tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1446         r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1447
1448         /* SQ_GPR_RESOURCE_MGMT_2 */
1449         tmp = 0;
1450         tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1451         tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1452         r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1453
1454         /* SQ_THREAD_RESOURCE_MGMT */
1455         tmp = 0;
1456         tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1457         tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1458         tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1459         tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1460         r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1461
1462         /* SQ_STACK_RESOURCE_MGMT_1 */
1463         tmp = 0;
1464         tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1465         tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1466         r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1467
1468         /* SQ_STACK_RESOURCE_MGMT_2 */
1469         tmp = 0;
1470         tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1471         tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1472         r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1473
1474         r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1475         r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1476
1477         if (family >= CHIP_RV770) {
1478                 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1479                 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1480                 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1481                 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1482                 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1483                 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514000, 0xFFFFFFFF, NULL);
1484         } else {
1485                 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1486                 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1487                 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1488                 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1489                 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1490                 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004010, 0xFFFFFFFF, NULL);
1491         }
1492         r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1493         r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1494         r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1495         r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1496         r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1497         r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1498         r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1499         r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1500         r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1501         r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1502         r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1503         r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1504         r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1505         r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1506         r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1507         r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1508         r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1509         r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1510         r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1511         r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1512         r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1513         r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1514         r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1515         r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1516         r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1517         r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1518
1519         r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1520         r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1521         r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1522         r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1523         r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1524         r600_context_pipe_state_set(&rctx->ctx, rstate);
1525 }
1526
1527 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1528 {
1529         struct pipe_depth_stencil_alpha_state dsa;
1530         struct r600_pipe_state *rstate;
1531         boolean quirk = false;
1532
1533         if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1534                 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1535                 quirk = true;
1536
1537         memset(&dsa, 0, sizeof(dsa));
1538
1539         if (quirk) {
1540                 dsa.depth.enabled = 1;
1541                 dsa.depth.func = PIPE_FUNC_LEQUAL;
1542                 dsa.stencil[0].enabled = 1;
1543                 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1544                 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1545                 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1546                 dsa.stencil[0].writemask = 0xff;
1547         }
1548
1549         rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1550         r600_pipe_state_add_reg(rstate,
1551                                 R_02880C_DB_SHADER_CONTROL,
1552                                 0x0,
1553                                 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1554         r600_pipe_state_add_reg(rstate,
1555                                 R_028D0C_DB_RENDER_CONTROL,
1556                                 S_028D0C_DEPTH_COPY_ENABLE(1) |
1557                                 S_028D0C_STENCIL_COPY_ENABLE(1) |
1558                                 S_028D0C_COPY_CENTROID(1),
1559                                 S_028D0C_DEPTH_COPY_ENABLE(1) |
1560                                 S_028D0C_STENCIL_COPY_ENABLE(1) |
1561                                 S_028D0C_COPY_CENTROID(1), NULL);
1562         return rstate;
1563 }