2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "util/u_inlines.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "r600_screen.h"
32 #include "r600_context.h"
33 #include "r600_resource.h"
35 #include "r600_state_inlines.h"
37 static void *r600_create_blend_state(struct pipe_context
*ctx
,
38 const struct pipe_blend_state
*state
)
40 struct r600_context
*rctx
= r600_context(ctx
);
42 return r600_context_state(rctx
, pipe_blend_type
, state
);
45 static void *r600_create_dsa_state(struct pipe_context
*ctx
,
46 const struct pipe_depth_stencil_alpha_state
*state
)
48 struct r600_context
*rctx
= r600_context(ctx
);
50 return r600_context_state(rctx
, pipe_dsa_type
, state
);
53 static void *r600_create_rs_state(struct pipe_context
*ctx
,
54 const struct pipe_rasterizer_state
*state
)
56 struct r600_context
*rctx
= r600_context(ctx
);
58 return r600_context_state(rctx
, pipe_rasterizer_type
, state
);
61 static void *r600_create_sampler_state(struct pipe_context
*ctx
,
62 const struct pipe_sampler_state
*state
)
64 struct r600_context
*rctx
= r600_context(ctx
);
66 return r600_context_state(rctx
, pipe_sampler_type
, state
);
69 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
70 struct pipe_sampler_view
*state
)
72 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
74 r600_context_state_decref(rstate
);
77 static struct pipe_sampler_view
*r600_create_sampler_view(struct pipe_context
*ctx
,
78 struct pipe_resource
*texture
,
79 const struct pipe_sampler_view
*state
)
81 struct r600_context
*rctx
= r600_context(ctx
);
82 struct r600_context_state
*rstate
;
84 rstate
= r600_context_state(rctx
, pipe_sampler_type
, state
);
85 pipe_reference(NULL
, &texture
->reference
);
86 rstate
->state
.sampler_view
.texture
= texture
;
87 rstate
->state
.sampler_view
.reference
.count
= 1;
88 rstate
->state
.sampler_view
.context
= ctx
;
89 return &rstate
->state
.sampler_view
;
92 static void *r600_create_shader_state(struct pipe_context
*ctx
,
93 const struct pipe_shader_state
*state
)
95 struct r600_context
*rctx
= r600_context(ctx
);
97 return r600_context_state(rctx
, pipe_shader_type
, state
);
100 static void *r600_create_vertex_elements(struct pipe_context
*ctx
,
102 const struct pipe_vertex_element
*elements
)
104 struct r600_vertex_element
*v
= CALLOC_STRUCT(r600_vertex_element
);
108 memcpy(v
->elements
, elements
, count
* sizeof(struct pipe_vertex_element
));
113 static void r600_bind_state(struct pipe_context
*ctx
, void *state
)
115 struct r600_context
*rctx
= r600_context(ctx
);
116 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
120 switch (rstate
->type
) {
121 case pipe_rasterizer_type
:
122 rctx
->rasterizer
= r600_context_state_decref(rctx
->rasterizer
);
123 rctx
->rasterizer
= r600_context_state_incref(rstate
);
125 case pipe_poly_stipple_type
:
126 rctx
->poly_stipple
= r600_context_state_decref(rctx
->poly_stipple
);
127 rctx
->poly_stipple
= r600_context_state_incref(rstate
);
129 case pipe_scissor_type
:
130 rctx
->scissor
= r600_context_state_decref(rctx
->scissor
);
131 rctx
->scissor
= r600_context_state_incref(rstate
);
134 rctx
->clip
= r600_context_state_decref(rctx
->clip
);
135 rctx
->clip
= r600_context_state_incref(rstate
);
137 case pipe_depth_type
:
138 rctx
->depth
= r600_context_state_decref(rctx
->depth
);
139 rctx
->depth
= r600_context_state_incref(rstate
);
141 case pipe_stencil_type
:
142 rctx
->stencil
= r600_context_state_decref(rctx
->stencil
);
143 rctx
->stencil
= r600_context_state_incref(rstate
);
145 case pipe_alpha_type
:
146 rctx
->alpha
= r600_context_state_decref(rctx
->alpha
);
147 rctx
->alpha
= r600_context_state_incref(rstate
);
150 rctx
->dsa
= r600_context_state_decref(rctx
->dsa
);
151 rctx
->dsa
= r600_context_state_incref(rstate
);
153 case pipe_blend_type
:
154 rctx
->blend
= r600_context_state_decref(rctx
->blend
);
155 rctx
->blend
= r600_context_state_incref(rstate
);
157 case pipe_framebuffer_type
:
158 rctx
->framebuffer
= r600_context_state_decref(rctx
->framebuffer
);
159 rctx
->framebuffer
= r600_context_state_incref(rstate
);
161 case pipe_stencil_ref_type
:
162 rctx
->stencil_ref
= r600_context_state_decref(rctx
->stencil_ref
);
163 rctx
->stencil_ref
= r600_context_state_incref(rstate
);
165 case pipe_viewport_type
:
166 rctx
->viewport
= r600_context_state_decref(rctx
->viewport
);
167 rctx
->viewport
= r600_context_state_incref(rstate
);
169 case pipe_shader_type
:
170 case pipe_sampler_type
:
171 case pipe_sampler_view_type
:
173 R600_ERR("invalid type %d\n", rstate
->type
);
178 static void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
180 struct r600_context
*rctx
= r600_context(ctx
);
181 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
183 rctx
->ps_shader
= r600_context_state_decref(rctx
->ps_shader
);
184 rctx
->ps_shader
= r600_context_state_incref(rstate
);
187 static void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
189 struct r600_context
*rctx
= r600_context(ctx
);
190 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
192 rctx
->vs_shader
= r600_context_state_decref(rctx
->vs_shader
);
193 rctx
->vs_shader
= r600_context_state_incref(rstate
);
196 static void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
198 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
207 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
209 struct r600_context
*rctx
= r600_context(ctx
);
210 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
212 r600_delete_vertex_element(ctx
, rctx
->vertex_elements
);
213 rctx
->vertex_elements
= v
;
219 static void r600_bind_ps_sampler(struct pipe_context
*ctx
,
220 unsigned count
, void **states
)
222 struct r600_context
*rctx
= r600_context(ctx
);
223 struct r600_context_state
*rstate
;
226 for (i
= 0; i
< rctx
->ps_nsampler
; i
++) {
227 rctx
->ps_sampler
[i
] = r600_context_state_decref(rctx
->ps_sampler
[i
]);
229 for (i
= 0; i
< count
; i
++) {
230 rstate
= (struct r600_context_state
*)states
[i
];
231 rctx
->ps_sampler
[i
] = r600_context_state_incref(rstate
);
233 rctx
->ps_nsampler
= count
;
236 static void r600_bind_vs_sampler(struct pipe_context
*ctx
,
237 unsigned count
, void **states
)
239 struct r600_context
*rctx
= r600_context(ctx
);
240 struct r600_context_state
*rstate
;
243 for (i
= 0; i
< rctx
->vs_nsampler
; i
++) {
244 rctx
->vs_sampler
[i
] = r600_context_state_decref(rctx
->vs_sampler
[i
]);
246 for (i
= 0; i
< count
; i
++) {
247 rstate
= (struct r600_context_state
*)states
[i
];
248 rctx
->vs_sampler
[i
] = r600_context_state_incref(rstate
);
250 rctx
->vs_nsampler
= count
;
253 static void r600_delete_state(struct pipe_context
*ctx
, void *state
)
255 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
257 r600_context_state_decref(rstate
);
260 static void r600_set_blend_color(struct pipe_context
*ctx
,
261 const struct pipe_blend_color
*color
)
263 struct r600_context
*rctx
= r600_context(ctx
);
265 rctx
->blend_color
= *color
;
268 static void r600_set_clip_state(struct pipe_context
*ctx
,
269 const struct pipe_clip_state
*state
)
273 static void r600_set_constant_buffer(struct pipe_context
*ctx
,
274 uint shader
, uint index
,
275 struct pipe_resource
*buffer
)
277 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
278 struct r600_context
*rctx
= r600_context(ctx
);
279 unsigned nconstant
= 0, i
, type
, id
;
280 struct radeon_state rstate
;
281 struct pipe_transfer
*transfer
;
286 case PIPE_SHADER_VERTEX
:
287 id
= R600_VS_CONSTANT
;
288 type
= R600_VS_CONSTANT_TYPE
;
290 case PIPE_SHADER_FRAGMENT
:
291 id
= R600_PS_CONSTANT
;
292 type
= R600_PS_CONSTANT_TYPE
;
295 R600_ERR("unsupported %d\n", shader
);
298 if (buffer
&& buffer
->width0
> 0) {
299 nconstant
= buffer
->width0
/ 16;
300 ptr
= pipe_buffer_map(ctx
, buffer
, PIPE_TRANSFER_READ
, &transfer
);
303 for (i
= 0; i
< nconstant
; i
++) {
304 r
= radeon_state_init(&rstate
, rscreen
->rw
, type
, id
+ i
);
307 rstate
.states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0
] = ptr
[i
* 4 + 0];
308 rstate
.states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0
] = ptr
[i
* 4 + 1];
309 rstate
.states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0
] = ptr
[i
* 4 + 2];
310 rstate
.states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0
] = ptr
[i
* 4 + 3];
311 if (radeon_state_pm4(&rstate
))
313 if (radeon_draw_set(&rctx
->draw
, &rstate
))
316 pipe_buffer_unmap(ctx
, buffer
, transfer
);
320 static void r600_set_ps_sampler_view(struct pipe_context
*ctx
,
322 struct pipe_sampler_view
**views
)
324 struct r600_context
*rctx
= r600_context(ctx
);
325 struct r600_context_state
*rstate
;
328 for (i
= 0; i
< rctx
->ps_nsampler_view
; i
++) {
329 rctx
->ps_sampler_view
[i
] = r600_context_state_decref(rctx
->ps_sampler_view
[i
]);
331 for (i
= 0; i
< count
; i
++) {
332 rstate
= (struct r600_context_state
*)views
[i
];
333 rctx
->ps_sampler_view
[i
] = r600_context_state_incref(rstate
);
335 rctx
->ps_nsampler_view
= count
;
338 static void r600_set_vs_sampler_view(struct pipe_context
*ctx
,
340 struct pipe_sampler_view
**views
)
342 struct r600_context
*rctx
= r600_context(ctx
);
343 struct r600_context_state
*rstate
;
346 for (i
= 0; i
< rctx
->vs_nsampler_view
; i
++) {
347 rctx
->vs_sampler_view
[i
] = r600_context_state_decref(rctx
->vs_sampler_view
[i
]);
349 for (i
= 0; i
< count
; i
++) {
350 rstate
= (struct r600_context_state
*)views
[i
];
351 rctx
->vs_sampler_view
[i
] = r600_context_state_incref(rstate
);
353 rctx
->vs_nsampler_view
= count
;
356 static void r600_set_framebuffer_state(struct pipe_context
*ctx
,
357 const struct pipe_framebuffer_state
*state
)
359 struct r600_context
*rctx
= r600_context(ctx
);
360 struct r600_context_state
*rstate
;
362 rstate
= r600_context_state(rctx
, pipe_framebuffer_type
, state
);
363 r600_bind_state(ctx
, rstate
);
366 static void r600_set_polygon_stipple(struct pipe_context
*ctx
,
367 const struct pipe_poly_stipple
*state
)
371 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
375 static void r600_set_scissor_state(struct pipe_context
*ctx
,
376 const struct pipe_scissor_state
*state
)
378 struct r600_context
*rctx
= r600_context(ctx
);
379 struct r600_context_state
*rstate
;
381 rstate
= r600_context_state(rctx
, pipe_scissor_type
, state
);
382 r600_bind_state(ctx
, rstate
);
385 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
386 const struct pipe_stencil_ref
*state
)
388 struct r600_context
*rctx
= r600_context(ctx
);
389 struct r600_context_state
*rstate
;
391 rstate
= r600_context_state(rctx
, pipe_stencil_ref_type
, state
);
392 r600_bind_state(ctx
, rstate
);
395 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
397 const struct pipe_vertex_buffer
*buffers
)
399 struct r600_context
*rctx
= r600_context(ctx
);
402 for (i
= 0; i
< rctx
->nvertex_buffer
; i
++) {
403 pipe_resource_reference(&rctx
->vertex_buffer
[i
].buffer
, NULL
);
405 memcpy(rctx
->vertex_buffer
, buffers
, sizeof(struct pipe_vertex_buffer
) * count
);
406 for (i
= 0; i
< count
; i
++) {
407 rctx
->vertex_buffer
[i
].buffer
= NULL
;
408 pipe_resource_reference(&rctx
->vertex_buffer
[i
].buffer
, buffers
[i
].buffer
);
410 rctx
->nvertex_buffer
= count
;
413 static void r600_set_index_buffer(struct pipe_context
*ctx
,
414 const struct pipe_index_buffer
*ib
)
416 struct r600_context
*rctx
= r600_context(ctx
);
419 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
420 memcpy(&rctx
->index_buffer
, ib
, sizeof(rctx
->index_buffer
));
422 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
423 memset(&rctx
->index_buffer
, 0, sizeof(rctx
->index_buffer
));
426 /* TODO make this more like a state */
429 static void r600_set_viewport_state(struct pipe_context
*ctx
,
430 const struct pipe_viewport_state
*state
)
432 struct r600_context
*rctx
= r600_context(ctx
);
433 struct r600_context_state
*rstate
;
435 rstate
= r600_context_state(rctx
, pipe_viewport_type
, state
);
436 r600_bind_state(ctx
, rstate
);
439 void r600_init_state_functions(struct r600_context
*rctx
)
441 rctx
->context
.create_blend_state
= r600_create_blend_state
;
442 rctx
->context
.create_depth_stencil_alpha_state
= r600_create_dsa_state
;
443 rctx
->context
.create_fs_state
= r600_create_shader_state
;
444 rctx
->context
.create_rasterizer_state
= r600_create_rs_state
;
445 rctx
->context
.create_sampler_state
= r600_create_sampler_state
;
446 rctx
->context
.create_sampler_view
= r600_create_sampler_view
;
447 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
448 rctx
->context
.create_vs_state
= r600_create_shader_state
;
449 rctx
->context
.bind_blend_state
= r600_bind_state
;
450 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_state
;
451 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_sampler
;
452 rctx
->context
.bind_fs_state
= r600_bind_ps_shader
;
453 rctx
->context
.bind_rasterizer_state
= r600_bind_state
;
454 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
455 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_sampler
;
456 rctx
->context
.bind_vs_state
= r600_bind_vs_shader
;
457 rctx
->context
.delete_blend_state
= r600_delete_state
;
458 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
459 rctx
->context
.delete_fs_state
= r600_delete_state
;
460 rctx
->context
.delete_rasterizer_state
= r600_delete_state
;
461 rctx
->context
.delete_sampler_state
= r600_delete_state
;
462 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_element
;
463 rctx
->context
.delete_vs_state
= r600_delete_state
;
464 rctx
->context
.set_blend_color
= r600_set_blend_color
;
465 rctx
->context
.set_clip_state
= r600_set_clip_state
;
466 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
467 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_view
;
468 rctx
->context
.set_framebuffer_state
= r600_set_framebuffer_state
;
469 rctx
->context
.set_polygon_stipple
= r600_set_polygon_stipple
;
470 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
471 rctx
->context
.set_scissor_state
= r600_set_scissor_state
;
472 rctx
->context
.set_stencil_ref
= r600_set_stencil_ref
;
473 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
474 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
475 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_view
;
476 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
477 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
480 struct r600_context_state
*r600_context_state_incref(struct r600_context_state
*rstate
)
488 struct r600_context_state
*r600_context_state_decref(struct r600_context_state
*rstate
)
494 if (--rstate
->refcount
)
496 switch (rstate
->type
) {
497 case pipe_sampler_view_type
:
498 pipe_resource_reference(&rstate
->state
.sampler_view
.texture
, NULL
);
500 case pipe_framebuffer_type
:
501 for (i
= 0; i
< rstate
->state
.framebuffer
.nr_cbufs
; i
++) {
502 pipe_surface_reference(&rstate
->state
.framebuffer
.cbufs
[i
], NULL
);
504 pipe_surface_reference(&rstate
->state
.framebuffer
.zsbuf
, NULL
);
506 case pipe_viewport_type
:
507 case pipe_depth_type
:
508 case pipe_rasterizer_type
:
509 case pipe_poly_stipple_type
:
510 case pipe_scissor_type
:
512 case pipe_stencil_type
:
513 case pipe_alpha_type
:
515 case pipe_blend_type
:
516 case pipe_stencil_ref_type
:
517 case pipe_shader_type
:
518 case pipe_sampler_type
:
521 R600_ERR("invalid type %d\n", rstate
->type
);
528 struct r600_context_state
*r600_context_state(struct r600_context
*rctx
, unsigned type
, const void *state
)
530 struct r600_context_state
*rstate
= CALLOC_STRUCT(r600_context_state
);
531 const union pipe_states
*states
= state
;
538 rstate
->refcount
= 1;
540 switch (rstate
->type
) {
541 case pipe_sampler_view_type
:
542 rstate
->state
.sampler_view
= (*states
).sampler_view
;
543 rstate
->state
.sampler_view
.texture
= NULL
;
545 case pipe_framebuffer_type
:
546 rstate
->state
.framebuffer
= (*states
).framebuffer
;
547 for (i
= 0; i
< rstate
->state
.framebuffer
.nr_cbufs
; i
++) {
548 pipe_surface_reference(&rstate
->state
.framebuffer
.cbufs
[i
],
549 (*states
).framebuffer
.cbufs
[i
]);
551 pipe_surface_reference(&rstate
->state
.framebuffer
.zsbuf
,
552 (*states
).framebuffer
.zsbuf
);
554 case pipe_viewport_type
:
555 rstate
->state
.viewport
= (*states
).viewport
;
557 case pipe_depth_type
:
558 rstate
->state
.depth
= (*states
).depth
;
560 case pipe_rasterizer_type
:
561 rstate
->state
.rasterizer
= (*states
).rasterizer
;
563 case pipe_poly_stipple_type
:
564 rstate
->state
.poly_stipple
= (*states
).poly_stipple
;
566 case pipe_scissor_type
:
567 rstate
->state
.scissor
= (*states
).scissor
;
570 rstate
->state
.clip
= (*states
).clip
;
572 case pipe_stencil_type
:
573 rstate
->state
.stencil
= (*states
).stencil
;
575 case pipe_alpha_type
:
576 rstate
->state
.alpha
= (*states
).alpha
;
579 rstate
->state
.dsa
= (*states
).dsa
;
581 case pipe_blend_type
:
582 rstate
->state
.blend
= (*states
).blend
;
584 case pipe_stencil_ref_type
:
585 rstate
->state
.stencil_ref
= (*states
).stencil_ref
;
587 case pipe_shader_type
:
588 rstate
->state
.shader
= (*states
).shader
;
589 r
= r600_pipe_shader_create(&rctx
->context
, rstate
, rstate
->state
.shader
.tokens
);
591 r600_context_state_decref(rstate
);
595 case pipe_sampler_type
:
596 rstate
->state
.sampler
= (*states
).sampler
;
599 R600_ERR("invalid type %d\n", rstate
->type
);
606 static int r600_blend(struct r600_context
*rctx
, struct radeon_state
*rstate
)
608 struct r600_screen
*rscreen
= rctx
->screen
;
609 const struct pipe_blend_state
*state
= &rctx
->blend
->state
.blend
;
613 r
= radeon_state_init(rstate
, rscreen
->rw
, R600_BLEND_TYPE
, R600_BLEND
);
617 rstate
->states
[R600_BLEND__CB_BLEND_RED
] = fui(rctx
->blend_color
.color
[0]);
618 rstate
->states
[R600_BLEND__CB_BLEND_GREEN
] = fui(rctx
->blend_color
.color
[1]);
619 rstate
->states
[R600_BLEND__CB_BLEND_BLUE
] = fui(rctx
->blend_color
.color
[2]);
620 rstate
->states
[R600_BLEND__CB_BLEND_ALPHA
] = fui(rctx
->blend_color
.color
[3]);
621 rstate
->states
[R600_BLEND__CB_BLEND0_CONTROL
] = 0x00000000;
622 rstate
->states
[R600_BLEND__CB_BLEND1_CONTROL
] = 0x00000000;
623 rstate
->states
[R600_BLEND__CB_BLEND2_CONTROL
] = 0x00000000;
624 rstate
->states
[R600_BLEND__CB_BLEND3_CONTROL
] = 0x00000000;
625 rstate
->states
[R600_BLEND__CB_BLEND4_CONTROL
] = 0x00000000;
626 rstate
->states
[R600_BLEND__CB_BLEND5_CONTROL
] = 0x00000000;
627 rstate
->states
[R600_BLEND__CB_BLEND6_CONTROL
] = 0x00000000;
628 rstate
->states
[R600_BLEND__CB_BLEND7_CONTROL
] = 0x00000000;
629 rstate
->states
[R600_BLEND__CB_BLEND_CONTROL
] = 0x00000000;
631 for (i
= 0; i
< 8; i
++) {
632 unsigned eqRGB
= state
->rt
[i
].rgb_func
;
633 unsigned srcRGB
= state
->rt
[i
].rgb_src_factor
;
634 unsigned dstRGB
= state
->rt
[i
].rgb_dst_factor
;
636 unsigned eqA
= state
->rt
[i
].alpha_func
;
637 unsigned srcA
= state
->rt
[i
].alpha_src_factor
;
638 unsigned dstA
= state
->rt
[i
].alpha_dst_factor
;
641 if (!state
->rt
[i
].blend_enable
)
644 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
645 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
646 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
648 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
649 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
650 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
651 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
652 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
655 rstate
->states
[R600_BLEND__CB_BLEND0_CONTROL
+ i
] = bc
;
657 rstate
->states
[R600_BLEND__CB_BLEND_CONTROL
] = bc
;
660 return radeon_state_pm4(rstate
);
663 static int r600_cb0(struct r600_context
*rctx
, struct radeon_state
*rstate
)
665 struct r600_screen
*rscreen
= rctx
->screen
;
666 struct r600_resource_texture
*rtex
;
667 struct r600_resource
*rbuffer
;
668 const struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
->state
.framebuffer
;
669 unsigned level
= state
->cbufs
[0]->level
;
670 unsigned pitch
, slice
;
673 r
= radeon_state_init(rstate
, rscreen
->rw
, R600_CB0_TYPE
, R600_CB0
);
677 rtex
= (struct r600_resource_texture
*)state
->cbufs
[0]->texture
;
678 rbuffer
= &rtex
->resource
;
679 rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
680 rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
681 rstate
->bo
[2] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
682 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
683 rstate
->placement
[2] = RADEON_GEM_DOMAIN_GTT
;
684 rstate
->placement
[4] = RADEON_GEM_DOMAIN_GTT
;
686 pitch
= (rtex
->pitch
[level
] / rtex
->bpt
) / 8 - 1;
687 slice
= (rtex
->pitch
[level
] / rtex
->bpt
) * state
->cbufs
[0]->height
/ 64 - 1;
688 rstate
->states
[R600_CB0__CB_COLOR0_BASE
] = 0x00000000;
689 rstate
->states
[R600_CB0__CB_COLOR0_INFO
] = 0x08110068;
690 rstate
->states
[R600_CB0__CB_COLOR0_SIZE
] = S_028060_PITCH_TILE_MAX(pitch
) |
691 S_028060_SLICE_TILE_MAX(slice
);
692 rstate
->states
[R600_CB0__CB_COLOR0_VIEW
] = 0x00000000;
693 rstate
->states
[R600_CB0__CB_COLOR0_FRAG
] = 0x00000000;
694 rstate
->states
[R600_CB0__CB_COLOR0_TILE
] = 0x00000000;
695 rstate
->states
[R600_CB0__CB_COLOR0_MASK
] = 0x00000000;
696 return radeon_state_pm4(rstate
);
699 static int r600_db_format(unsigned pformat
, unsigned *format
)
702 case PIPE_FORMAT_Z24X8_UNORM
:
703 *format
= V_028010_DEPTH_X8_24
;
705 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
706 *format
= V_028010_DEPTH_8_24
;
709 *format
= V_028010_DEPTH_INVALID
;
710 R600_ERR("unsupported %d\n", pformat
);
715 static int r600_db(struct r600_context
*rctx
, struct radeon_state
*rstate
)
717 struct r600_screen
*rscreen
= rctx
->screen
;
718 struct r600_resource_texture
*rtex
;
719 struct r600_resource
*rbuffer
;
720 const struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
->state
.framebuffer
;
721 unsigned level
= state
->cbufs
[0]->level
;
722 unsigned pitch
, slice
, format
;
725 r
= radeon_state_init(rstate
, rscreen
->rw
, R600_DB_TYPE
, R600_DB
);
729 if (state
->zsbuf
== NULL
)
731 rtex
= (struct r600_resource_texture
*)state
->zsbuf
->texture
;
732 rbuffer
= &rtex
->resource
;
733 rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
735 rstate
->placement
[0] = RADEON_GEM_DOMAIN_VRAM
;
736 level
= state
->zsbuf
->level
;
737 pitch
= (rtex
->pitch
[level
] / rtex
->bpt
) / 8 - 1;
738 slice
= (rtex
->pitch
[level
] / rtex
->bpt
) * state
->zsbuf
->height
/ 64 - 1;
739 if (r600_db_format(state
->zsbuf
->texture
->format
, &format
)) {
742 rstate
->states
[R600_DB__DB_DEPTH_BASE
] = 0x00000000;
743 rstate
->states
[R600_DB__DB_DEPTH_INFO
] = 0x00010000 |
744 S_028010_FORMAT(format
);
745 rstate
->states
[R600_DB__DB_DEPTH_VIEW
] = 0x00000000;
746 rstate
->states
[R600_DB__DB_PREFETCH_LIMIT
] = (state
->zsbuf
->height
/ 8) -1;
747 rstate
->states
[R600_DB__DB_DEPTH_SIZE
] = S_028000_PITCH_TILE_MAX(pitch
) |
748 S_028000_SLICE_TILE_MAX(slice
);
749 return radeon_state_pm4(rstate
);
752 static int r600_rasterizer(struct r600_context
*rctx
, struct radeon_state
*rstate
)
754 const struct pipe_rasterizer_state
*state
= &rctx
->rasterizer
->state
.rasterizer
;
755 const struct pipe_framebuffer_state
*fb
= &rctx
->framebuffer
->state
.framebuffer
;
756 struct r600_screen
*rscreen
= rctx
->screen
;
757 float offset_units
= 0, offset_scale
= 0;
759 unsigned offset_db_fmt_cntl
= 0;
762 r
= radeon_state_init(rstate
, rscreen
->rw
, R600_RASTERIZER_TYPE
, R600_RASTERIZER
);
766 offset_units
= state
->offset_units
;
767 offset_scale
= state
->offset_scale
* 12.0f
;
768 switch (fb
->zsbuf
->texture
->format
) {
769 case PIPE_FORMAT_Z24X8_UNORM
:
770 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
772 offset_units
*= 2.0f
;
774 case PIPE_FORMAT_Z32_FLOAT
:
776 offset_units
*= 1.0f
;
777 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
779 case PIPE_FORMAT_Z16_UNORM
:
781 offset_units
*= 4.0f
;
784 R600_ERR("unsupported %d\n", fb
->zsbuf
->texture
->format
);
788 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
790 rctx
->flat_shade
= state
->flatshade
;
791 rstate
->states
[R600_RASTERIZER__SPI_INTERP_CONTROL_0
] = 0x00000001;
792 rstate
->states
[R600_RASTERIZER__PA_CL_CLIP_CNTL
] = 0x00000000;
793 rstate
->states
[R600_RASTERIZER__PA_SU_SC_MODE_CNTL
] = 0x00080000 |
794 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
795 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
796 S_028814_FACE(!state
->front_ccw
) |
797 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
798 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
799 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
);
800 rstate
->states
[R600_RASTERIZER__PA_CL_VS_OUT_CNTL
] = 0x00000000;
801 rstate
->states
[R600_RASTERIZER__PA_CL_NANINF_CNTL
] = 0x00000000;
802 rstate
->states
[R600_RASTERIZER__PA_SU_POINT_SIZE
] = 0x00080008;
803 rstate
->states
[R600_RASTERIZER__PA_SU_POINT_MINMAX
] = 0x00000000;
804 rstate
->states
[R600_RASTERIZER__PA_SU_LINE_CNTL
] = 0x00000008;
805 rstate
->states
[R600_RASTERIZER__PA_SC_LINE_STIPPLE
] = 0x00000005;
806 rstate
->states
[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL
] = 0x00000000;
807 rstate
->states
[R600_RASTERIZER__PA_SC_LINE_CNTL
] = 0x00000400;
808 rstate
->states
[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ
] = 0x3F800000;
809 rstate
->states
[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ
] = 0x3F800000;
810 rstate
->states
[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ
] = 0x3F800000;
811 rstate
->states
[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ
] = 0x3F800000;
812 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL
] = offset_db_fmt_cntl
;
813 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP
] = 0x00000000;
814 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE
] = fui(offset_scale
);
815 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET
] = fui(offset_units
);
816 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE
] = fui(offset_scale
);
817 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET
] = fui(offset_units
);
818 return radeon_state_pm4(rstate
);
821 static int r600_scissor(struct r600_context
*rctx
, struct radeon_state
*rstate
)
823 const struct pipe_scissor_state
*state
= &rctx
->scissor
->state
.scissor
;
824 struct r600_screen
*rscreen
= rctx
->screen
;
828 r
= radeon_state_init(rstate
, rscreen
->rw
, R600_SCISSOR_TYPE
, R600_SCISSOR
);
831 tl
= S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
) | S_028240_WINDOW_OFFSET_DISABLE(1);
832 br
= S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
);
833 rstate
->states
[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL
] = tl
;
834 rstate
->states
[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR
] = br
;
835 rstate
->states
[R600_SCISSOR__PA_SC_WINDOW_OFFSET
] = 0x00000000;
836 rstate
->states
[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL
] = tl
;
837 rstate
->states
[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR
] = br
;
838 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_RULE
] = 0x0000FFFF;
839 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_0_TL
] = tl
;
840 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_0_BR
] = br
;
841 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_1_TL
] = tl
;
842 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_1_BR
] = br
;
843 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_2_TL
] = tl
;
844 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_2_BR
] = br
;
845 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_3_TL
] = tl
;
846 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_3_BR
] = br
;
847 rstate
->states
[R600_SCISSOR__PA_SC_EDGERULE
] = 0xAAAAAAAA;
848 rstate
->states
[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL
] = tl
;
849 rstate
->states
[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR
] = br
;
850 rstate
->states
[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL
] = tl
;
851 rstate
->states
[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR
] = br
;
852 return radeon_state_pm4(rstate
);
855 static int r600_viewport(struct r600_context
*rctx
, struct radeon_state
*rstate
)
857 const struct pipe_viewport_state
*state
= &rctx
->viewport
->state
.viewport
;
858 struct r600_screen
*rscreen
= rctx
->screen
;
861 r
= radeon_state_init(rstate
, rscreen
->rw
, R600_VIEWPORT_TYPE
, R600_VIEWPORT
);
864 rstate
->states
[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0
] = 0x00000000;
865 rstate
->states
[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0
] = 0x3F800000;
866 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0
] = fui(state
->scale
[0]);
867 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0
] = fui(state
->scale
[1]);
868 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0
] = fui(state
->scale
[2]);
869 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0
] = fui(state
->translate
[0]);
870 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0
] = fui(state
->translate
[1]);
871 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0
] = fui(state
->translate
[2]);
872 rstate
->states
[R600_VIEWPORT__PA_CL_VTE_CNTL
] = 0x0000043F;
873 return radeon_state_pm4(rstate
);
876 static int r600_dsa(struct r600_context
*rctx
, struct radeon_state
*rstate
)
878 const struct pipe_depth_stencil_alpha_state
*state
= &rctx
->dsa
->state
.dsa
;
879 const struct pipe_stencil_ref
*stencil_ref
= &rctx
->stencil_ref
->state
.stencil_ref
;
880 struct r600_screen
*rscreen
= rctx
->screen
;
881 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
882 unsigned stencil_ref_mask
, stencil_ref_mask_bf
;
885 r
= radeon_state_init(rstate
, rscreen
->rw
, R600_DSA_TYPE
, R600_DSA
);
889 stencil_ref_mask
= 0;
890 stencil_ref_mask_bf
= 0;
891 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
892 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
893 S_028800_ZFUNC(state
->depth
.func
);
895 /* set stencil enable */
896 if (state
->stencil
[0].enabled
) {
897 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
898 db_depth_control
|= S_028800_STENCILFUNC(r600_translate_ds_func(state
->stencil
[0].func
));
899 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
900 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
901 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
903 stencil_ref_mask
= S_028430_STENCILMASK(state
->stencil
[0].valuemask
) |
904 S_028430_STENCILWRITEMASK(state
->stencil
[0].writemask
);
905 stencil_ref_mask
|= S_028430_STENCILREF(stencil_ref
->ref_value
[0]);
906 if (state
->stencil
[1].enabled
) {
907 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
908 db_depth_control
|= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state
->stencil
[1].func
));
909 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
910 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
911 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
912 stencil_ref_mask_bf
= S_028434_STENCILMASK_BF(state
->stencil
[1].valuemask
) |
913 S_028434_STENCILWRITEMASK_BF(state
->stencil
[1].writemask
);
914 stencil_ref_mask_bf
|= S_028430_STENCILREF(stencil_ref
->ref_value
[1]);
918 alpha_test_control
= 0;
920 if (state
->alpha
.enabled
) {
921 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
922 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
923 alpha_ref
= fui(state
->alpha
.ref_value
);
926 rstate
->states
[R600_DSA__DB_STENCIL_CLEAR
] = 0x00000000;
927 rstate
->states
[R600_DSA__DB_DEPTH_CLEAR
] = 0x3F800000;
928 rstate
->states
[R600_DSA__SX_ALPHA_TEST_CONTROL
] = alpha_test_control
;
929 rstate
->states
[R600_DSA__DB_STENCILREFMASK
] = stencil_ref_mask
;
930 rstate
->states
[R600_DSA__DB_STENCILREFMASK_BF
] = stencil_ref_mask_bf
;
931 rstate
->states
[R600_DSA__SX_ALPHA_REF
] = alpha_ref
;
932 rstate
->states
[R600_DSA__SPI_FOG_FUNC_SCALE
] = 0x00000000;
933 rstate
->states
[R600_DSA__SPI_FOG_FUNC_BIAS
] = 0x00000000;
934 rstate
->states
[R600_DSA__SPI_FOG_CNTL
] = 0x00000000;
935 rstate
->states
[R600_DSA__DB_DEPTH_CONTROL
] = db_depth_control
;
936 rstate
->states
[R600_DSA__DB_SHADER_CONTROL
] = 0x00000210;
937 rstate
->states
[R600_DSA__DB_RENDER_CONTROL
] = 0x00000060;
938 rstate
->states
[R600_DSA__DB_RENDER_OVERRIDE
] = 0x0000002A;
939 rstate
->states
[R600_DSA__DB_SRESULTS_COMPARE_STATE1
] = 0x00000000;
940 rstate
->states
[R600_DSA__DB_PRELOAD_CONTROL
] = 0x00000000;
941 rstate
->states
[R600_DSA__DB_ALPHA_TO_MASK
] = 0x0000AA00;
942 return radeon_state_pm4(rstate
);
945 static inline unsigned r600_tex_wrap(unsigned wrap
)
949 case PIPE_TEX_WRAP_REPEAT
:
950 return V_03C000_SQ_TEX_WRAP
;
951 case PIPE_TEX_WRAP_CLAMP
:
952 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
953 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
954 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
955 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
956 return V_03C000_SQ_TEX_CLAMP_BORDER
;
957 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
958 return V_03C000_SQ_TEX_MIRROR
;
959 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
960 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
961 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
962 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
963 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
964 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
968 static inline unsigned r600_tex_filter(unsigned filter
)
972 case PIPE_TEX_FILTER_NEAREST
:
973 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
974 case PIPE_TEX_FILTER_LINEAR
:
975 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
979 static inline unsigned r600_tex_mipfilter(unsigned filter
)
982 case PIPE_TEX_MIPFILTER_NEAREST
:
983 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
984 case PIPE_TEX_MIPFILTER_LINEAR
:
985 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
987 case PIPE_TEX_MIPFILTER_NONE
:
988 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
992 static inline unsigned r600_tex_compare(unsigned compare
)
996 case PIPE_FUNC_NEVER
:
997 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
999 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1000 case PIPE_FUNC_EQUAL
:
1001 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1002 case PIPE_FUNC_LEQUAL
:
1003 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1004 case PIPE_FUNC_GREATER
:
1005 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1006 case PIPE_FUNC_NOTEQUAL
:
1007 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1008 case PIPE_FUNC_GEQUAL
:
1009 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1010 case PIPE_FUNC_ALWAYS
:
1011 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1015 static INLINE u32
S_FIXED(float value
, u32 frac_bits
)
1017 return value
* (1 << frac_bits
);
1020 static int r600_sampler(struct r600_context
*rctx
, struct radeon_state
*rstate
,
1021 const struct pipe_sampler_state
*state
, unsigned id
)
1023 struct r600_screen
*rscreen
= rctx
->screen
;
1026 r
= radeon_state_init(rstate
, rscreen
->rw
, R600_PS_SAMPLER_TYPE
, id
);
1029 rstate
->states
[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0
] =
1030 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
1031 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
1032 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
1033 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
)) |
1034 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
)) |
1035 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
1036 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
));
1037 /* FIXME LOD it depends on texture base level ... */
1038 rstate
->states
[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0
] =
1039 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
1040 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
1041 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6));
1042 rstate
->states
[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0
] = S_03C008_TYPE(1);
1043 return radeon_state_pm4(rstate
);
1046 static inline unsigned r600_tex_swizzle(unsigned swizzle
)
1049 case PIPE_SWIZZLE_RED
:
1050 return V_038010_SQ_SEL_X
;
1051 case PIPE_SWIZZLE_GREEN
:
1052 return V_038010_SQ_SEL_Y
;
1053 case PIPE_SWIZZLE_BLUE
:
1054 return V_038010_SQ_SEL_Z
;
1055 case PIPE_SWIZZLE_ALPHA
:
1056 return V_038010_SQ_SEL_W
;
1057 case PIPE_SWIZZLE_ZERO
:
1058 return V_038010_SQ_SEL_0
;
1060 case PIPE_SWIZZLE_ONE
:
1061 return V_038010_SQ_SEL_1
;
1065 static inline unsigned r600_format_type(unsigned format_type
)
1067 switch (format_type
) {
1069 case UTIL_FORMAT_TYPE_UNSIGNED
:
1070 return V_038010_SQ_FORMAT_COMP_UNSIGNED
;
1071 case UTIL_FORMAT_TYPE_SIGNED
:
1072 return V_038010_SQ_FORMAT_COMP_SIGNED
;
1073 case UTIL_FORMAT_TYPE_FIXED
:
1074 return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED
;
1078 static inline unsigned r600_tex_dim(unsigned dim
)
1082 case PIPE_TEXTURE_1D
:
1083 return V_038000_SQ_TEX_DIM_1D
;
1084 case PIPE_TEXTURE_2D
:
1085 return V_038000_SQ_TEX_DIM_2D
;
1086 case PIPE_TEXTURE_3D
:
1087 return V_038000_SQ_TEX_DIM_3D
;
1088 case PIPE_TEXTURE_CUBE
:
1089 return V_038000_SQ_TEX_DIM_CUBEMAP
;
1093 static int r600_resource(struct r600_context
*rctx
, struct radeon_state
*rstate
,
1094 const struct pipe_sampler_view
*view
, unsigned id
)
1096 struct r600_screen
*rscreen
= rctx
->screen
;
1097 const struct util_format_description
*desc
;
1098 struct r600_resource_texture
*tmp
;
1099 struct r600_resource
*rbuffer
;
1103 r
= radeon_state_init(rstate
, rscreen
->rw
, R600_PS_RESOURCE_TYPE
, id
);
1106 if (r600_conv_pipe_format(view
->texture
->format
, &format
))
1108 desc
= util_format_description(view
->texture
->format
);
1110 R600_ERR("unknow format %d\n", view
->texture
->format
);
1113 tmp
= (struct r600_resource_texture
*)view
->texture
;
1114 rbuffer
= &tmp
->resource
;
1115 rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
1116 rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
1118 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
1119 rstate
->placement
[1] = RADEON_GEM_DOMAIN_GTT
;
1120 rstate
->placement
[2] = RADEON_GEM_DOMAIN_GTT
;
1121 rstate
->placement
[3] = RADEON_GEM_DOMAIN_GTT
;
1123 /* FIXME properly handle first level != 0 */
1124 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD0
] =
1125 S_038000_DIM(r600_tex_dim(view
->texture
->target
)) |
1126 S_038000_PITCH(((tmp
->pitch
[0] / tmp
->bpt
) / 8) - 1) |
1127 S_038000_TEX_WIDTH(view
->texture
->width0
- 1);
1128 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD1
] =
1129 S_038004_TEX_HEIGHT(view
->texture
->height0
- 1) |
1130 S_038004_TEX_DEPTH(view
->texture
->depth0
- 1) |
1131 S_038004_DATA_FORMAT(format
);
1132 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD2
] = 0;
1133 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD3
] = tmp
->offset
[1] >> 8;
1134 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD4
] =
1135 S_038010_FORMAT_COMP_X(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED
)) |
1136 S_038010_FORMAT_COMP_Y(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED
)) |
1137 S_038010_FORMAT_COMP_Z(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED
)) |
1138 S_038010_FORMAT_COMP_W(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED
)) |
1139 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM
) |
1140 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO
) |
1141 S_038010_REQUEST_SIZE(1) |
1142 S_038010_DST_SEL_X(r600_tex_swizzle(view
->swizzle_b
)) |
1143 S_038010_DST_SEL_Y(r600_tex_swizzle(view
->swizzle_g
)) |
1144 S_038010_DST_SEL_Z(r600_tex_swizzle(view
->swizzle_r
)) |
1145 S_038010_DST_SEL_W(r600_tex_swizzle(view
->swizzle_a
)) |
1146 S_038010_BASE_LEVEL(view
->first_level
);
1147 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD5
] =
1148 S_038014_LAST_LEVEL(view
->last_level
) |
1149 S_038014_BASE_ARRAY(0) |
1150 S_038014_LAST_ARRAY(0);
1151 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD6
] =
1152 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
);
1153 return radeon_state_pm4(rstate
);
1156 static int r600_cb_cntl(struct r600_context
*rctx
, struct radeon_state
*rstate
)
1158 struct r600_screen
*rscreen
= rctx
->screen
;
1159 const struct pipe_blend_state
*pbs
= &rctx
->blend
->state
.blend
;
1160 uint32_t color_control
, target_mask
;
1164 color_control
= S_028808_PER_MRT_BLEND(1);
1166 if (pbs
->logicop_enable
) {
1167 color_control
|= (pbs
->logicop_func
) << 16;
1169 color_control
|= (0xcc << 16);
1171 target_mask
|= (pbs
->rt
[0].colormask
);
1172 for (i
= 0; i
< 8; i
++) {
1173 if (pbs
->rt
[i
].blend_enable
) {
1174 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
1175 target_mask
|= (pbs
->rt
[0].colormask
<< (4 * i
));
1178 r
= radeon_state_init(rstate
, rscreen
->rw
, R600_CB_CNTL_TYPE
, R600_CB_CNTL
);
1181 rstate
->states
[R600_CB_CNTL__CB_SHADER_MASK
] = 0x0000000F;
1182 rstate
->states
[R600_CB_CNTL__CB_TARGET_MASK
] = target_mask
;
1183 rstate
->states
[R600_CB_CNTL__CB_COLOR_CONTROL
] = color_control
;
1184 rstate
->states
[R600_CB_CNTL__PA_SC_AA_CONFIG
] = 0x00000000;
1185 rstate
->states
[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX
] = 0x00000000;
1186 rstate
->states
[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX
] = 0x00000000;
1187 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_CONTROL
] = 0x01000000;
1188 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_SRC
] = 0x00000000;
1189 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_DST
] = 0x000000FF;
1190 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_MSK
] = 0xFFFFFFFF;
1191 rstate
->states
[R600_CB_CNTL__PA_SC_AA_MASK
] = 0xFFFFFFFF;
1192 return radeon_state_pm4(rstate
);
1195 int r600_context_hw_states(struct r600_context
*rctx
)
1200 /* free previous TODO determine what need to be updated, what
1203 memset(&rctx
->hw_states
, 0, sizeof(struct r600_context_hw_states
));
1205 /* build new states */
1206 rctx
->hw_states
.config
= rctx
->config
;
1207 r600_rasterizer(rctx
, &rctx
->hw_states
.rasterizer
);
1208 r600_scissor(rctx
, &rctx
->hw_states
.scissor
);
1209 r600_dsa(rctx
, &rctx
->hw_states
.dsa
);
1210 r600_blend(rctx
, &rctx
->hw_states
.blend
);
1211 r600_viewport(rctx
, &rctx
->hw_states
.viewport
);
1212 r600_cb0(rctx
, &rctx
->hw_states
.cb0
);
1213 r600_db(rctx
, &rctx
->hw_states
.db
);
1214 r600_cb_cntl(rctx
, &rctx
->hw_states
.cb_cntl
);
1216 for (i
= 0; i
< rctx
->ps_nsampler
; i
++) {
1217 if (rctx
->ps_sampler
[i
]) {
1218 r600_sampler(rctx
, &rctx
->hw_states
.ps_sampler
[i
],
1219 &rctx
->ps_sampler
[i
]->state
.sampler
,
1220 R600_PS_SAMPLER
+ i
);
1223 rctx
->hw_states
.ps_nsampler
= rctx
->ps_nsampler
;
1224 for (i
= 0; i
< rctx
->ps_nsampler_view
; i
++) {
1225 if (rctx
->ps_sampler_view
[i
]) {
1226 r600_resource(rctx
, &rctx
->hw_states
.ps_resource
[i
],
1227 &rctx
->ps_sampler_view
[i
]->state
.sampler_view
,
1228 R600_PS_RESOURCE
+ i
);
1231 rctx
->hw_states
.ps_nresource
= rctx
->ps_nsampler_view
;
1234 r
= radeon_draw_set(&rctx
->draw
, &rctx
->hw_states
.db
);
1237 r
= radeon_draw_set(&rctx
->draw
, &rctx
->hw_states
.rasterizer
);
1240 r
= radeon_draw_set(&rctx
->draw
, &rctx
->hw_states
.scissor
);
1243 r
= radeon_draw_set(&rctx
->draw
, &rctx
->hw_states
.dsa
);
1246 r
= radeon_draw_set(&rctx
->draw
, &rctx
->hw_states
.blend
);
1249 r
= radeon_draw_set(&rctx
->draw
, &rctx
->hw_states
.viewport
);
1252 r
= radeon_draw_set(&rctx
->draw
, &rctx
->hw_states
.cb0
);
1255 r
= radeon_draw_set(&rctx
->draw
, &rctx
->hw_states
.config
);
1258 r
= radeon_draw_set(&rctx
->draw
, &rctx
->hw_states
.cb_cntl
);
1261 for (i
= 0; i
< rctx
->hw_states
.ps_nresource
; i
++) {
1262 if (rctx
->hw_states
.ps_resource
[i
].valid
) {
1263 r
= radeon_draw_set(&rctx
->draw
, &rctx
->hw_states
.ps_resource
[i
]);
1268 for (i
= 0; i
< rctx
->hw_states
.ps_nsampler
; i
++) {
1269 if (rctx
->hw_states
.ps_sampler
[i
].valid
) {
1270 r
= radeon_draw_set(&rctx
->draw
, &rctx
->hw_states
.ps_sampler
[i
]);