2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "pipe/p_defines.h"
27 #include "pipe/p_state.h"
28 #include "pipe/p_context.h"
29 #include "tgsi/tgsi_scan.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "tgsi/tgsi_util.h"
32 #include "util/u_double_list.h"
33 #include "util/u_pack_color.h"
34 #include "util/u_memory.h"
35 #include "util/u_inlines.h"
36 #include "util/u_framebuffer.h"
37 #include "util/u_transfer.h"
38 #include "pipebuffer/pb_buffer.h"
41 #include "r600_resource.h"
42 #include "r600_shader.h"
43 #include "r600_pipe.h"
44 #include "r600_formats.h"
46 static uint32_t r600_translate_blend_function(int blend_func
)
50 return V_028804_COMB_DST_PLUS_SRC
;
51 case PIPE_BLEND_SUBTRACT
:
52 return V_028804_COMB_SRC_MINUS_DST
;
53 case PIPE_BLEND_REVERSE_SUBTRACT
:
54 return V_028804_COMB_DST_MINUS_SRC
;
56 return V_028804_COMB_MIN_DST_SRC
;
58 return V_028804_COMB_MAX_DST_SRC
;
60 R600_ERR("Unknown blend function %d\n", blend_func
);
67 static uint32_t r600_translate_blend_factor(int blend_fact
)
70 case PIPE_BLENDFACTOR_ONE
:
71 return V_028804_BLEND_ONE
;
72 case PIPE_BLENDFACTOR_SRC_COLOR
:
73 return V_028804_BLEND_SRC_COLOR
;
74 case PIPE_BLENDFACTOR_SRC_ALPHA
:
75 return V_028804_BLEND_SRC_ALPHA
;
76 case PIPE_BLENDFACTOR_DST_ALPHA
:
77 return V_028804_BLEND_DST_ALPHA
;
78 case PIPE_BLENDFACTOR_DST_COLOR
:
79 return V_028804_BLEND_DST_COLOR
;
80 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
81 return V_028804_BLEND_SRC_ALPHA_SATURATE
;
82 case PIPE_BLENDFACTOR_CONST_COLOR
:
83 return V_028804_BLEND_CONST_COLOR
;
84 case PIPE_BLENDFACTOR_CONST_ALPHA
:
85 return V_028804_BLEND_CONST_ALPHA
;
86 case PIPE_BLENDFACTOR_ZERO
:
87 return V_028804_BLEND_ZERO
;
88 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
89 return V_028804_BLEND_ONE_MINUS_SRC_COLOR
;
90 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
91 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA
;
92 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
93 return V_028804_BLEND_ONE_MINUS_DST_ALPHA
;
94 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
95 return V_028804_BLEND_ONE_MINUS_DST_COLOR
;
96 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
97 return V_028804_BLEND_ONE_MINUS_CONST_COLOR
;
98 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
99 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA
;
100 case PIPE_BLENDFACTOR_SRC1_COLOR
:
101 return V_028804_BLEND_SRC1_COLOR
;
102 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
103 return V_028804_BLEND_SRC1_ALPHA
;
104 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
105 return V_028804_BLEND_INV_SRC1_COLOR
;
106 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
107 return V_028804_BLEND_INV_SRC1_ALPHA
;
109 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
116 static unsigned r600_tex_dim(unsigned dim
)
120 case PIPE_TEXTURE_1D
:
121 return V_038000_SQ_TEX_DIM_1D
;
122 case PIPE_TEXTURE_1D_ARRAY
:
123 return V_038000_SQ_TEX_DIM_1D_ARRAY
;
124 case PIPE_TEXTURE_2D
:
125 case PIPE_TEXTURE_RECT
:
126 return V_038000_SQ_TEX_DIM_2D
;
127 case PIPE_TEXTURE_2D_ARRAY
:
128 return V_038000_SQ_TEX_DIM_2D_ARRAY
;
129 case PIPE_TEXTURE_3D
:
130 return V_038000_SQ_TEX_DIM_3D
;
131 case PIPE_TEXTURE_CUBE
:
132 return V_038000_SQ_TEX_DIM_CUBEMAP
;
136 static uint32_t r600_translate_dbformat(enum pipe_format format
)
139 case PIPE_FORMAT_Z16_UNORM
:
140 return V_028010_DEPTH_16
;
141 case PIPE_FORMAT_Z24X8_UNORM
:
142 return V_028010_DEPTH_X8_24
;
143 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
144 return V_028010_DEPTH_8_24
;
145 case PIPE_FORMAT_Z32_FLOAT
:
146 return V_028010_DEPTH_32_FLOAT
;
147 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
148 return V_028010_DEPTH_X24_8_32_FLOAT
;
154 static uint32_t r600_translate_colorswap(enum pipe_format format
)
158 case PIPE_FORMAT_A8_UNORM
:
159 case PIPE_FORMAT_A8_SNORM
:
160 case PIPE_FORMAT_A8_UINT
:
161 case PIPE_FORMAT_A8_SINT
:
162 case PIPE_FORMAT_A16_UNORM
:
163 case PIPE_FORMAT_A16_SNORM
:
164 case PIPE_FORMAT_A16_UINT
:
165 case PIPE_FORMAT_A16_SINT
:
166 case PIPE_FORMAT_A16_FLOAT
:
167 case PIPE_FORMAT_A32_UINT
:
168 case PIPE_FORMAT_A32_SINT
:
169 case PIPE_FORMAT_A32_FLOAT
:
170 case PIPE_FORMAT_R4A4_UNORM
:
171 return V_0280A0_SWAP_ALT_REV
;
172 case PIPE_FORMAT_I8_UNORM
:
173 case PIPE_FORMAT_I8_SNORM
:
174 case PIPE_FORMAT_I8_UINT
:
175 case PIPE_FORMAT_I8_SINT
:
176 case PIPE_FORMAT_L8_UNORM
:
177 case PIPE_FORMAT_L8_SNORM
:
178 case PIPE_FORMAT_L8_UINT
:
179 case PIPE_FORMAT_L8_SINT
:
180 case PIPE_FORMAT_L8_SRGB
:
181 case PIPE_FORMAT_L16_UNORM
:
182 case PIPE_FORMAT_L16_SNORM
:
183 case PIPE_FORMAT_L16_UINT
:
184 case PIPE_FORMAT_L16_SINT
:
185 case PIPE_FORMAT_L16_FLOAT
:
186 case PIPE_FORMAT_L32_UINT
:
187 case PIPE_FORMAT_L32_SINT
:
188 case PIPE_FORMAT_L32_FLOAT
:
189 case PIPE_FORMAT_I16_UNORM
:
190 case PIPE_FORMAT_I16_SNORM
:
191 case PIPE_FORMAT_I16_UINT
:
192 case PIPE_FORMAT_I16_SINT
:
193 case PIPE_FORMAT_I16_FLOAT
:
194 case PIPE_FORMAT_I32_UINT
:
195 case PIPE_FORMAT_I32_SINT
:
196 case PIPE_FORMAT_I32_FLOAT
:
197 case PIPE_FORMAT_R8_UNORM
:
198 case PIPE_FORMAT_R8_SNORM
:
199 case PIPE_FORMAT_R8_UINT
:
200 case PIPE_FORMAT_R8_SINT
:
201 return V_0280A0_SWAP_STD
;
203 case PIPE_FORMAT_L4A4_UNORM
:
204 case PIPE_FORMAT_A4R4_UNORM
:
205 return V_0280A0_SWAP_ALT
;
207 /* 16-bit buffers. */
208 case PIPE_FORMAT_B5G6R5_UNORM
:
209 return V_0280A0_SWAP_STD_REV
;
211 case PIPE_FORMAT_B5G5R5A1_UNORM
:
212 case PIPE_FORMAT_B5G5R5X1_UNORM
:
213 return V_0280A0_SWAP_ALT
;
215 case PIPE_FORMAT_B4G4R4A4_UNORM
:
216 case PIPE_FORMAT_B4G4R4X4_UNORM
:
217 return V_0280A0_SWAP_ALT
;
219 case PIPE_FORMAT_Z16_UNORM
:
220 return V_0280A0_SWAP_STD
;
222 case PIPE_FORMAT_L8A8_UNORM
:
223 case PIPE_FORMAT_L8A8_SNORM
:
224 case PIPE_FORMAT_L8A8_UINT
:
225 case PIPE_FORMAT_L8A8_SINT
:
226 case PIPE_FORMAT_L8A8_SRGB
:
227 case PIPE_FORMAT_L16A16_UNORM
:
228 case PIPE_FORMAT_L16A16_SNORM
:
229 case PIPE_FORMAT_L16A16_UINT
:
230 case PIPE_FORMAT_L16A16_SINT
:
231 case PIPE_FORMAT_L16A16_FLOAT
:
232 case PIPE_FORMAT_L32A32_UINT
:
233 case PIPE_FORMAT_L32A32_SINT
:
234 case PIPE_FORMAT_L32A32_FLOAT
:
235 return V_0280A0_SWAP_ALT
;
236 case PIPE_FORMAT_R8G8_UNORM
:
237 case PIPE_FORMAT_R8G8_SNORM
:
238 case PIPE_FORMAT_R8G8_UINT
:
239 case PIPE_FORMAT_R8G8_SINT
:
240 return V_0280A0_SWAP_STD
;
242 case PIPE_FORMAT_R16_UNORM
:
243 case PIPE_FORMAT_R16_SNORM
:
244 case PIPE_FORMAT_R16_UINT
:
245 case PIPE_FORMAT_R16_SINT
:
246 case PIPE_FORMAT_R16_FLOAT
:
247 return V_0280A0_SWAP_STD
;
249 /* 32-bit buffers. */
251 case PIPE_FORMAT_A8B8G8R8_SRGB
:
252 return V_0280A0_SWAP_STD_REV
;
253 case PIPE_FORMAT_B8G8R8A8_SRGB
:
254 return V_0280A0_SWAP_ALT
;
256 case PIPE_FORMAT_B8G8R8A8_UNORM
:
257 case PIPE_FORMAT_B8G8R8X8_UNORM
:
258 return V_0280A0_SWAP_ALT
;
260 case PIPE_FORMAT_A8R8G8B8_UNORM
:
261 case PIPE_FORMAT_X8R8G8B8_UNORM
:
262 return V_0280A0_SWAP_ALT_REV
;
263 case PIPE_FORMAT_R8G8B8A8_SNORM
:
264 case PIPE_FORMAT_R8G8B8A8_UNORM
:
265 case PIPE_FORMAT_R8G8B8X8_UNORM
:
266 case PIPE_FORMAT_R8G8B8A8_SINT
:
267 case PIPE_FORMAT_R8G8B8A8_UINT
:
268 return V_0280A0_SWAP_STD
;
270 case PIPE_FORMAT_A8B8G8R8_UNORM
:
271 case PIPE_FORMAT_X8B8G8R8_UNORM
:
272 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
273 return V_0280A0_SWAP_STD_REV
;
275 case PIPE_FORMAT_Z24X8_UNORM
:
276 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
277 return V_0280A0_SWAP_STD
;
279 case PIPE_FORMAT_X8Z24_UNORM
:
280 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
281 return V_0280A0_SWAP_STD
;
283 case PIPE_FORMAT_R10G10B10A2_UNORM
:
284 case PIPE_FORMAT_R10G10B10X2_SNORM
:
285 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
286 return V_0280A0_SWAP_STD
;
288 case PIPE_FORMAT_B10G10R10A2_UNORM
:
289 case PIPE_FORMAT_B10G10R10A2_UINT
:
290 return V_0280A0_SWAP_ALT
;
292 case PIPE_FORMAT_R11G11B10_FLOAT
:
293 case PIPE_FORMAT_R16G16_UNORM
:
294 case PIPE_FORMAT_R16G16_SNORM
:
295 case PIPE_FORMAT_R16G16_FLOAT
:
296 case PIPE_FORMAT_R16G16_UINT
:
297 case PIPE_FORMAT_R16G16_SINT
:
298 case PIPE_FORMAT_R32_UINT
:
299 case PIPE_FORMAT_R32_SINT
:
300 case PIPE_FORMAT_R32_FLOAT
:
301 case PIPE_FORMAT_Z32_FLOAT
:
302 return V_0280A0_SWAP_STD
;
304 /* 64-bit buffers. */
305 case PIPE_FORMAT_R32G32_FLOAT
:
306 case PIPE_FORMAT_R32G32_UINT
:
307 case PIPE_FORMAT_R32G32_SINT
:
308 case PIPE_FORMAT_R16G16B16A16_UNORM
:
309 case PIPE_FORMAT_R16G16B16A16_SNORM
:
310 case PIPE_FORMAT_R16G16B16A16_UINT
:
311 case PIPE_FORMAT_R16G16B16A16_SINT
:
312 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
313 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
315 /* 128-bit buffers. */
316 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
317 case PIPE_FORMAT_R32G32B32A32_SNORM
:
318 case PIPE_FORMAT_R32G32B32A32_UNORM
:
319 case PIPE_FORMAT_R32G32B32A32_SINT
:
320 case PIPE_FORMAT_R32G32B32A32_UINT
:
321 return V_0280A0_SWAP_STD
;
323 R600_ERR("unsupported colorswap format %d\n", format
);
329 static uint32_t r600_translate_colorformat(enum pipe_format format
)
332 case PIPE_FORMAT_L4A4_UNORM
:
333 case PIPE_FORMAT_R4A4_UNORM
:
334 case PIPE_FORMAT_A4R4_UNORM
:
335 return V_0280A0_COLOR_4_4
;
338 case PIPE_FORMAT_A8_UNORM
:
339 case PIPE_FORMAT_A8_SNORM
:
340 case PIPE_FORMAT_A8_UINT
:
341 case PIPE_FORMAT_A8_SINT
:
342 case PIPE_FORMAT_I8_UNORM
:
343 case PIPE_FORMAT_I8_SNORM
:
344 case PIPE_FORMAT_I8_UINT
:
345 case PIPE_FORMAT_I8_SINT
:
346 case PIPE_FORMAT_L8_UNORM
:
347 case PIPE_FORMAT_L8_SNORM
:
348 case PIPE_FORMAT_L8_UINT
:
349 case PIPE_FORMAT_L8_SINT
:
350 case PIPE_FORMAT_L8_SRGB
:
351 case PIPE_FORMAT_R8_UNORM
:
352 case PIPE_FORMAT_R8_SNORM
:
353 case PIPE_FORMAT_R8_UINT
:
354 case PIPE_FORMAT_R8_SINT
:
355 return V_0280A0_COLOR_8
;
357 /* 16-bit buffers. */
358 case PIPE_FORMAT_B5G6R5_UNORM
:
359 return V_0280A0_COLOR_5_6_5
;
361 case PIPE_FORMAT_B5G5R5A1_UNORM
:
362 case PIPE_FORMAT_B5G5R5X1_UNORM
:
363 return V_0280A0_COLOR_1_5_5_5
;
365 case PIPE_FORMAT_B4G4R4A4_UNORM
:
366 case PIPE_FORMAT_B4G4R4X4_UNORM
:
367 return V_0280A0_COLOR_4_4_4_4
;
369 case PIPE_FORMAT_Z16_UNORM
:
370 return V_0280A0_COLOR_16
;
372 case PIPE_FORMAT_L8A8_UNORM
:
373 case PIPE_FORMAT_L8A8_SNORM
:
374 case PIPE_FORMAT_L8A8_UINT
:
375 case PIPE_FORMAT_L8A8_SINT
:
376 case PIPE_FORMAT_L8A8_SRGB
:
377 case PIPE_FORMAT_R8G8_UNORM
:
378 case PIPE_FORMAT_R8G8_SNORM
:
379 case PIPE_FORMAT_R8G8_UINT
:
380 case PIPE_FORMAT_R8G8_SINT
:
381 return V_0280A0_COLOR_8_8
;
383 case PIPE_FORMAT_R16_UNORM
:
384 case PIPE_FORMAT_R16_SNORM
:
385 case PIPE_FORMAT_R16_UINT
:
386 case PIPE_FORMAT_R16_SINT
:
387 case PIPE_FORMAT_A16_UNORM
:
388 case PIPE_FORMAT_A16_SNORM
:
389 case PIPE_FORMAT_A16_UINT
:
390 case PIPE_FORMAT_A16_SINT
:
391 case PIPE_FORMAT_L16_UNORM
:
392 case PIPE_FORMAT_L16_SNORM
:
393 case PIPE_FORMAT_L16_UINT
:
394 case PIPE_FORMAT_L16_SINT
:
395 case PIPE_FORMAT_I16_UNORM
:
396 case PIPE_FORMAT_I16_SNORM
:
397 case PIPE_FORMAT_I16_UINT
:
398 case PIPE_FORMAT_I16_SINT
:
399 return V_0280A0_COLOR_16
;
401 case PIPE_FORMAT_R16_FLOAT
:
402 case PIPE_FORMAT_A16_FLOAT
:
403 case PIPE_FORMAT_L16_FLOAT
:
404 case PIPE_FORMAT_I16_FLOAT
:
405 return V_0280A0_COLOR_16_FLOAT
;
407 /* 32-bit buffers. */
408 case PIPE_FORMAT_A8B8G8R8_SRGB
:
409 case PIPE_FORMAT_A8B8G8R8_UNORM
:
410 case PIPE_FORMAT_A8R8G8B8_UNORM
:
411 case PIPE_FORMAT_B8G8R8A8_SRGB
:
412 case PIPE_FORMAT_B8G8R8A8_UNORM
:
413 case PIPE_FORMAT_B8G8R8X8_UNORM
:
414 case PIPE_FORMAT_R8G8B8A8_SNORM
:
415 case PIPE_FORMAT_R8G8B8A8_UNORM
:
416 case PIPE_FORMAT_R8G8B8X8_UNORM
:
417 case PIPE_FORMAT_R8SG8SB8UX8U_NORM
:
418 case PIPE_FORMAT_X8B8G8R8_UNORM
:
419 case PIPE_FORMAT_X8R8G8B8_UNORM
:
420 case PIPE_FORMAT_R8G8B8_UNORM
:
421 case PIPE_FORMAT_R8G8B8A8_SINT
:
422 case PIPE_FORMAT_R8G8B8A8_UINT
:
423 return V_0280A0_COLOR_8_8_8_8
;
425 case PIPE_FORMAT_R10G10B10A2_UNORM
:
426 case PIPE_FORMAT_R10G10B10X2_SNORM
:
427 case PIPE_FORMAT_B10G10R10A2_UNORM
:
428 case PIPE_FORMAT_B10G10R10A2_UINT
:
429 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
430 return V_0280A0_COLOR_2_10_10_10
;
432 case PIPE_FORMAT_Z24X8_UNORM
:
433 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
434 return V_0280A0_COLOR_8_24
;
436 case PIPE_FORMAT_X8Z24_UNORM
:
437 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
438 return V_0280A0_COLOR_24_8
;
440 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
441 return V_0280A0_COLOR_X24_8_32_FLOAT
;
443 case PIPE_FORMAT_R32_UINT
:
444 case PIPE_FORMAT_R32_SINT
:
445 case PIPE_FORMAT_A32_UINT
:
446 case PIPE_FORMAT_A32_SINT
:
447 case PIPE_FORMAT_L32_UINT
:
448 case PIPE_FORMAT_L32_SINT
:
449 case PIPE_FORMAT_I32_UINT
:
450 case PIPE_FORMAT_I32_SINT
:
451 return V_0280A0_COLOR_32
;
453 case PIPE_FORMAT_R32_FLOAT
:
454 case PIPE_FORMAT_A32_FLOAT
:
455 case PIPE_FORMAT_L32_FLOAT
:
456 case PIPE_FORMAT_I32_FLOAT
:
457 case PIPE_FORMAT_Z32_FLOAT
:
458 return V_0280A0_COLOR_32_FLOAT
;
460 case PIPE_FORMAT_R16G16_FLOAT
:
461 case PIPE_FORMAT_L16A16_FLOAT
:
462 return V_0280A0_COLOR_16_16_FLOAT
;
464 case PIPE_FORMAT_R16G16_UNORM
:
465 case PIPE_FORMAT_R16G16_SNORM
:
466 case PIPE_FORMAT_R16G16_UINT
:
467 case PIPE_FORMAT_R16G16_SINT
:
468 case PIPE_FORMAT_L16A16_UNORM
:
469 case PIPE_FORMAT_L16A16_SNORM
:
470 case PIPE_FORMAT_L16A16_UINT
:
471 case PIPE_FORMAT_L16A16_SINT
:
472 return V_0280A0_COLOR_16_16
;
474 case PIPE_FORMAT_R11G11B10_FLOAT
:
475 return V_0280A0_COLOR_10_11_11_FLOAT
;
477 /* 64-bit buffers. */
478 case PIPE_FORMAT_R16G16B16A16_UINT
:
479 case PIPE_FORMAT_R16G16B16A16_SINT
:
480 case PIPE_FORMAT_R16G16B16A16_UNORM
:
481 case PIPE_FORMAT_R16G16B16A16_SNORM
:
482 return V_0280A0_COLOR_16_16_16_16
;
484 case PIPE_FORMAT_R16G16B16_FLOAT
:
485 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
486 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
488 case PIPE_FORMAT_R32G32_FLOAT
:
489 case PIPE_FORMAT_L32A32_FLOAT
:
490 return V_0280A0_COLOR_32_32_FLOAT
;
492 case PIPE_FORMAT_R32G32_SINT
:
493 case PIPE_FORMAT_R32G32_UINT
:
494 case PIPE_FORMAT_L32A32_UINT
:
495 case PIPE_FORMAT_L32A32_SINT
:
496 return V_0280A0_COLOR_32_32
;
498 /* 96-bit buffers. */
499 case PIPE_FORMAT_R32G32B32_FLOAT
:
500 return V_0280A0_COLOR_32_32_32_FLOAT
;
502 /* 128-bit buffers. */
503 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
504 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
505 case PIPE_FORMAT_R32G32B32A32_SNORM
:
506 case PIPE_FORMAT_R32G32B32A32_UNORM
:
507 case PIPE_FORMAT_R32G32B32A32_SINT
:
508 case PIPE_FORMAT_R32G32B32A32_UINT
:
509 return V_0280A0_COLOR_32_32_32_32
;
512 case PIPE_FORMAT_UYVY
:
513 case PIPE_FORMAT_YUYV
:
515 return ~0U; /* Unsupported. */
519 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
521 if (R600_BIG_ENDIAN
) {
522 switch(colorformat
) {
523 case V_0280A0_COLOR_4_4
:
527 case V_0280A0_COLOR_8
:
530 /* 16-bit buffers. */
531 case V_0280A0_COLOR_5_6_5
:
532 case V_0280A0_COLOR_1_5_5_5
:
533 case V_0280A0_COLOR_4_4_4_4
:
534 case V_0280A0_COLOR_16
:
535 case V_0280A0_COLOR_8_8
:
538 /* 32-bit buffers. */
539 case V_0280A0_COLOR_8_8_8_8
:
540 case V_0280A0_COLOR_2_10_10_10
:
541 case V_0280A0_COLOR_8_24
:
542 case V_0280A0_COLOR_24_8
:
543 case V_0280A0_COLOR_32_FLOAT
:
544 case V_0280A0_COLOR_16_16_FLOAT
:
545 case V_0280A0_COLOR_16_16
:
548 /* 64-bit buffers. */
549 case V_0280A0_COLOR_16_16_16_16
:
550 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
553 case V_0280A0_COLOR_32_32_FLOAT
:
554 case V_0280A0_COLOR_32_32
:
555 case V_0280A0_COLOR_X24_8_32_FLOAT
:
558 /* 128-bit buffers. */
559 case V_0280A0_COLOR_32_32_32_FLOAT
:
560 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
561 case V_0280A0_COLOR_32_32_32_32
:
564 return ENDIAN_NONE
; /* Unsupported. */
571 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
573 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
576 static bool r600_is_colorbuffer_format_supported(enum pipe_format format
)
578 return r600_translate_colorformat(format
) != ~0U &&
579 r600_translate_colorswap(format
) != ~0U;
582 static bool r600_is_zs_format_supported(enum pipe_format format
)
584 return r600_translate_dbformat(format
) != ~0U;
587 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
588 enum pipe_format format
,
589 enum pipe_texture_target target
,
590 unsigned sample_count
,
595 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
596 R600_ERR("r600: unsupported texture type %d\n", target
);
600 if (!util_format_is_supported(format
, usage
))
604 if (sample_count
> 1)
607 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
608 r600_is_sampler_format_supported(screen
, format
)) {
609 retval
|= PIPE_BIND_SAMPLER_VIEW
;
612 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
613 PIPE_BIND_DISPLAY_TARGET
|
615 PIPE_BIND_SHARED
)) &&
616 r600_is_colorbuffer_format_supported(format
)) {
618 (PIPE_BIND_RENDER_TARGET
|
619 PIPE_BIND_DISPLAY_TARGET
|
624 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
625 r600_is_zs_format_supported(format
)) {
626 retval
|= PIPE_BIND_DEPTH_STENCIL
;
629 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
630 r600_is_vertex_format_supported(format
)) {
631 retval
|= PIPE_BIND_VERTEX_BUFFER
;
634 if (usage
& PIPE_BIND_TRANSFER_READ
)
635 retval
|= PIPE_BIND_TRANSFER_READ
;
636 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
637 retval
|= PIPE_BIND_TRANSFER_WRITE
;
639 return retval
== usage
;
642 void r600_polygon_offset_update(struct r600_context
*rctx
)
644 struct r600_pipe_state state
;
646 state
.id
= R600_PIPE_STATE_POLYGON_OFFSET
;
648 if (rctx
->rasterizer
&& rctx
->framebuffer
.zsbuf
) {
649 float offset_units
= rctx
->rasterizer
->offset_units
;
650 unsigned offset_db_fmt_cntl
= 0, depth
;
652 switch (rctx
->framebuffer
.zsbuf
->texture
->format
) {
653 case PIPE_FORMAT_Z24X8_UNORM
:
654 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
656 offset_units
*= 2.0f
;
658 case PIPE_FORMAT_Z32_FLOAT
:
659 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
661 offset_units
*= 1.0f
;
662 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
664 case PIPE_FORMAT_Z16_UNORM
:
666 offset_units
*= 4.0f
;
671 /* XXX some of those reg can be computed with cso */
672 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
673 r600_pipe_state_add_reg(&state
,
674 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE
,
675 fui(rctx
->rasterizer
->offset_scale
), NULL
, 0);
676 r600_pipe_state_add_reg(&state
,
677 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
678 fui(offset_units
), NULL
, 0);
679 r600_pipe_state_add_reg(&state
,
680 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE
,
681 fui(rctx
->rasterizer
->offset_scale
), NULL
, 0);
682 r600_pipe_state_add_reg(&state
,
683 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
684 fui(offset_units
), NULL
, 0);
685 r600_pipe_state_add_reg(&state
,
686 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
687 offset_db_fmt_cntl
, NULL
, 0);
688 r600_context_pipe_state_set(rctx
, &state
);
692 static void *r600_create_blend_state(struct pipe_context
*ctx
,
693 const struct pipe_blend_state
*state
)
695 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
696 struct r600_pipe_blend
*blend
= CALLOC_STRUCT(r600_pipe_blend
);
697 struct r600_pipe_state
*rstate
;
698 uint32_t color_control
= 0, target_mask
;
703 rstate
= &blend
->rstate
;
705 rstate
->id
= R600_PIPE_STATE_BLEND
;
709 /* R600 does not support per-MRT blends */
710 if (rctx
->family
> CHIP_R600
)
711 color_control
|= S_028808_PER_MRT_BLEND(1);
712 if (state
->logicop_enable
) {
713 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
715 color_control
|= (0xcc << 16);
717 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
718 if (state
->independent_blend_enable
) {
719 for (int i
= 0; i
< 8; i
++) {
720 if (state
->rt
[i
].blend_enable
) {
721 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
723 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
726 for (int i
= 0; i
< 8; i
++) {
727 if (state
->rt
[0].blend_enable
) {
728 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
730 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
733 blend
->cb_target_mask
= target_mask
;
734 blend
->cb_color_control
= color_control
;
736 for (int i
= 0; i
< 8; i
++) {
737 /* state->rt entries > 0 only written if independent blending */
738 const int j
= state
->independent_blend_enable
? i
: 0;
740 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
741 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
742 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
744 unsigned eqA
= state
->rt
[j
].alpha_func
;
745 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
746 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
749 if (!state
->rt
[j
].blend_enable
)
752 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
753 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
754 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
756 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
757 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
758 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
759 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
760 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
763 /* R600 does not support per-MRT blends */
764 if (rctx
->family
> CHIP_R600
)
765 r600_pipe_state_add_reg(rstate
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, bc
, NULL
, 0);
767 r600_pipe_state_add_reg(rstate
, R_028804_CB_BLEND_CONTROL
, bc
, NULL
, 0);
772 static void *r600_create_dsa_state(struct pipe_context
*ctx
,
773 const struct pipe_depth_stencil_alpha_state
*state
)
775 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
776 struct r600_pipe_dsa
*dsa
= CALLOC_STRUCT(r600_pipe_dsa
);
777 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
778 struct r600_pipe_state
*rstate
;
784 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
785 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
786 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
787 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
789 rstate
= &dsa
->rstate
;
791 rstate
->id
= R600_PIPE_STATE_DSA
;
792 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
793 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
794 S_028800_ZFUNC(state
->depth
.func
);
797 if (state
->stencil
[0].enabled
) {
798 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
799 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
800 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
801 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
802 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
804 if (state
->stencil
[1].enabled
) {
805 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
806 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
807 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
808 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
809 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
814 alpha_test_control
= 0;
816 if (state
->alpha
.enabled
) {
817 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
818 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
819 alpha_ref
= fui(state
->alpha
.ref_value
);
821 dsa
->alpha_ref
= alpha_ref
;
823 r600_pipe_state_add_reg(rstate
, R_028410_SX_ALPHA_TEST_CONTROL
, alpha_test_control
, NULL
, 0);
824 r600_pipe_state_add_reg(rstate
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
, NULL
, 0);
828 static void *r600_create_rs_state(struct pipe_context
*ctx
,
829 const struct pipe_rasterizer_state
*state
)
831 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
832 struct r600_pipe_rasterizer
*rs
= CALLOC_STRUCT(r600_pipe_rasterizer
);
833 struct r600_pipe_state
*rstate
;
835 unsigned prov_vtx
= 1, polygon_dual_mode
;
836 unsigned sc_mode_cntl
;
837 float psize_min
, psize_max
;
843 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
844 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
846 if (state
->flatshade_first
)
849 rstate
= &rs
->rstate
;
850 rs
->flatshade
= state
->flatshade
;
851 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
852 rs
->two_side
= state
->light_twoside
;
853 rs
->clip_plane_enable
= state
->clip_plane_enable
;
854 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
855 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
856 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
857 rs
->pa_cl_clip_cntl
=
858 S_028810_PS_UCP_MODE(3) |
859 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
860 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
861 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
864 rs
->offset_units
= state
->offset_units
;
865 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
867 rstate
->id
= R600_PIPE_STATE_RASTERIZER
;
868 tmp
= S_0286D4_FLAT_SHADE_ENA(1);
869 if (state
->sprite_coord_enable
) {
870 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
871 S_0286D4_PNT_SPRITE_OVRD_X(2) |
872 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
873 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
874 S_0286D4_PNT_SPRITE_OVRD_W(1);
875 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
876 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
879 r600_pipe_state_add_reg(rstate
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
, NULL
, 0);
881 /* point size 12.4 fixed point */
882 /* For rasterizer discard, disable point rendering by forcing the point size to be 0. */
883 tmp
= state
->rasterizer_discard
? 0 : r600_pack_float_12p4(state
->point_size
/2);
884 r600_pipe_state_add_reg(rstate
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
), NULL
, 0);
886 if (state
->rasterizer_discard
) {
887 /* For rasterizer discard, disable point rendering by forcing the point size to be 0. */
890 } else if (state
->point_size_per_vertex
) {
891 psize_min
= util_get_min_point_size(state
);
894 /* Force the point size to be as if the vertex output was disabled. */
895 psize_min
= state
->point_size
;
896 psize_max
= state
->point_size
;
898 /* Divide by two, because 0.5 = 1 pixel. */
899 r600_pipe_state_add_reg(rstate
, R_028A04_PA_SU_POINT_MINMAX
,
900 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
901 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)),
904 /* For rasterizer discard, disable line rendering by forcing the line width to be 0. */
905 tmp
= state
->rasterizer_discard
? 0 : r600_pack_float_12p4(state
->line_width
/2);
906 r600_pipe_state_add_reg(rstate
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
), NULL
, 0);
908 if (rctx
->chip_class
>= R700
) {
910 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
911 S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
912 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
913 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state
->scissor
);
916 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
917 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
918 rs
->scissor_enable
= state
->scissor
;
920 sc_mode_cntl
|= S_028A4C_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
);
922 r600_pipe_state_add_reg(rstate
, R_028A4C_PA_SC_MODE_CNTL
, sc_mode_cntl
,
925 r600_pipe_state_add_reg(rstate
, R_028C08_PA_SU_VTX_CNTL
,
926 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
),
929 r600_pipe_state_add_reg(rstate
, R_028DFC_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
), NULL
, 0);
930 r600_pipe_state_add_reg(rstate
, R_028814_PA_SU_SC_MODE_CNTL
,
931 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
932 S_028814_CULL_FRONT(state
->rasterizer_discard
|| (state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
933 S_028814_CULL_BACK(state
->rasterizer_discard
|| (state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
934 S_028814_FACE(!state
->front_ccw
) |
935 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
936 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
937 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
938 S_028814_POLY_MODE(polygon_dual_mode
) |
939 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
940 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)),
943 r600_pipe_state_add_reg(rstate
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
944 state
->rasterizer_discard
? 0 : (S_028034_BR_X(8192) | S_028034_BR_Y(8192)),
949 static void *r600_create_sampler_state(struct pipe_context
*ctx
,
950 const struct pipe_sampler_state
*state
)
952 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
953 struct r600_pipe_state
*rstate
;
955 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 4 : 0;
961 ss
->seamless_cube_map
= state
->seamless_cube_map
;
962 rstate
= &ss
->rstate
;
963 rstate
->id
= R600_PIPE_STATE_SAMPLER
;
964 util_pack_color(state
->border_color
.f
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
965 r600_pipe_state_add_reg_noblock(rstate
, R_03C000_SQ_TEX_SAMPLER_WORD0_0
,
966 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
967 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
968 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
969 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
970 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
971 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
972 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
973 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
974 S_03C000_BORDER_COLOR_TYPE(uc
.ui
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0), NULL
, 0);
975 r600_pipe_state_add_reg_noblock(rstate
, R_03C004_SQ_TEX_SAMPLER_WORD1_0
,
976 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
977 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
978 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6)), NULL
, 0);
979 r600_pipe_state_add_reg_noblock(rstate
, R_03C008_SQ_TEX_SAMPLER_WORD2_0
, S_03C008_TYPE(1), NULL
, 0);
981 r600_pipe_state_add_reg_noblock(rstate
, R_00A400_TD_PS_SAMPLER0_BORDER_RED
, fui(state
->border_color
.f
[0]), NULL
, 0);
982 r600_pipe_state_add_reg_noblock(rstate
, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN
, fui(state
->border_color
.f
[1]), NULL
, 0);
983 r600_pipe_state_add_reg_noblock(rstate
, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE
, fui(state
->border_color
.f
[2]), NULL
, 0);
984 r600_pipe_state_add_reg_noblock(rstate
, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA
, fui(state
->border_color
.f
[3]), NULL
, 0);
989 static struct pipe_sampler_view
*r600_create_sampler_view(struct pipe_context
*ctx
,
990 struct pipe_resource
*texture
,
991 const struct pipe_sampler_view
*state
)
993 struct r600_screen
*rscreen
= (struct r600_screen
*)ctx
->screen
;
994 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
995 struct r600_pipe_resource_state
*rstate
;
996 struct r600_resource_texture
*tmp
= (struct r600_resource_texture
*)texture
;
997 unsigned format
, endian
;
998 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
999 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
1000 unsigned width
, height
, depth
, offset_level
, last_level
;
1004 rstate
= &view
->state
;
1006 /* initialize base object */
1007 view
->base
= *state
;
1008 view
->base
.texture
= NULL
;
1009 pipe_reference(NULL
, &texture
->reference
);
1010 view
->base
.texture
= texture
;
1011 view
->base
.reference
.count
= 1;
1012 view
->base
.context
= ctx
;
1014 swizzle
[0] = state
->swizzle_r
;
1015 swizzle
[1] = state
->swizzle_g
;
1016 swizzle
[2] = state
->swizzle_b
;
1017 swizzle
[3] = state
->swizzle_a
;
1019 format
= r600_translate_texformat(ctx
->screen
, state
->format
,
1021 &word4
, &yuv_format
);
1026 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
1027 r600_texture_depth_flush(ctx
, texture
, TRUE
);
1028 tmp
= tmp
->flushed_depth_texture
;
1031 endian
= r600_colorformat_endian_swap(format
);
1033 offset_level
= state
->u
.tex
.first_level
;
1034 last_level
= state
->u
.tex
.last_level
- offset_level
;
1035 if (!rscreen
->use_surface_alloc
) {
1036 width
= u_minify(texture
->width0
, offset_level
);
1037 height
= u_minify(texture
->height0
, offset_level
);
1038 depth
= u_minify(texture
->depth0
, offset_level
);
1040 pitch
= align(tmp
->pitch_in_blocks
[offset_level
] *
1041 util_format_get_blockwidth(state
->format
), 8);
1042 array_mode
= tmp
->array_mode
[offset_level
];
1043 tile_type
= tmp
->tile_type
;
1045 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
1047 depth
= texture
->array_size
;
1048 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
1049 depth
= texture
->array_size
;
1052 rstate
->bo
[0] = &tmp
->resource
;
1053 rstate
->bo
[1] = &tmp
->resource
;
1054 rstate
->bo_usage
[0] = RADEON_USAGE_READ
;
1055 rstate
->bo_usage
[1] = RADEON_USAGE_READ
;
1057 rstate
->val
[0] = (S_038000_DIM(r600_tex_dim(texture
->target
)) |
1058 S_038000_TILE_MODE(array_mode
) |
1059 S_038000_TILE_TYPE(tile_type
) |
1060 S_038000_PITCH((pitch
/ 8) - 1) |
1061 S_038000_TEX_WIDTH(width
- 1));
1062 rstate
->val
[1] = (S_038004_TEX_HEIGHT(height
- 1) |
1063 S_038004_TEX_DEPTH(depth
- 1) |
1064 S_038004_DATA_FORMAT(format
));
1065 rstate
->val
[2] = tmp
->offset
[offset_level
] >> 8;
1066 rstate
->val
[3] = tmp
->offset
[offset_level
+1] >> 8;
1067 rstate
->val
[4] = (word4
|
1068 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
1069 S_038010_REQUEST_SIZE(1) |
1070 S_038010_ENDIAN_SWAP(endian
) |
1071 S_038010_BASE_LEVEL(0));
1072 rstate
->val
[5] = (S_038014_LAST_LEVEL(last_level
) |
1073 S_038014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
1074 S_038014_LAST_ARRAY(state
->u
.tex
.last_layer
));
1075 rstate
->val
[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
) |
1076 S_038018_MAX_ANISO(4 /* max 16 samples */));
1078 width
= tmp
->surface
.level
[offset_level
].npix_x
;
1079 height
= tmp
->surface
.level
[offset_level
].npix_y
;
1080 depth
= tmp
->surface
.level
[offset_level
].npix_z
;
1081 pitch
= tmp
->surface
.level
[offset_level
].nblk_x
* util_format_get_blockwidth(state
->format
);
1082 tile_type
= tmp
->tile_type
;
1084 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
1086 depth
= texture
->array_size
;
1087 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
1088 depth
= texture
->array_size
;
1090 switch (tmp
->surface
.level
[offset_level
].mode
) {
1091 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1092 array_mode
= V_038000_ARRAY_LINEAR_ALIGNED
;
1094 case RADEON_SURF_MODE_1D
:
1095 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
1097 case RADEON_SURF_MODE_2D
:
1098 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
1100 case RADEON_SURF_MODE_LINEAR
:
1102 array_mode
= V_038000_ARRAY_LINEAR_GENERAL
;
1106 rstate
->bo
[0] = &tmp
->resource
;
1107 rstate
->bo
[1] = &tmp
->resource
;
1108 rstate
->bo_usage
[0] = RADEON_USAGE_READ
;
1109 rstate
->bo_usage
[1] = RADEON_USAGE_READ
;
1111 rstate
->val
[0] = (S_038000_DIM(r600_tex_dim(texture
->target
)) |
1112 S_038000_TILE_MODE(array_mode
) |
1113 S_038000_TILE_TYPE(tile_type
) |
1114 S_038000_PITCH((pitch
/ 8) - 1) |
1115 S_038000_TEX_WIDTH(width
- 1));
1116 rstate
->val
[1] = (S_038004_TEX_HEIGHT(height
- 1) |
1117 S_038004_TEX_DEPTH(depth
- 1) |
1118 S_038004_DATA_FORMAT(format
));
1119 rstate
->val
[2] = tmp
->surface
.level
[offset_level
].offset
>> 8;
1120 if (offset_level
>= tmp
->surface
.last_level
) {
1121 rstate
->val
[3] = tmp
->surface
.level
[offset_level
].offset
>> 8;
1123 rstate
->val
[3] = tmp
->surface
.level
[offset_level
+ 1].offset
>> 8;
1125 rstate
->val
[4] = (word4
|
1126 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
1127 S_038010_REQUEST_SIZE(1) |
1128 S_038010_ENDIAN_SWAP(endian
) |
1129 S_038010_BASE_LEVEL(0));
1130 rstate
->val
[5] = (S_038014_LAST_LEVEL(last_level
) |
1131 S_038014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
1132 S_038014_LAST_ARRAY(state
->u
.tex
.last_layer
));
1133 rstate
->val
[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
) |
1134 S_038018_MAX_ANISO(4 /* max 16 samples */));
1139 static void r600_set_sampler_views(struct r600_context
*rctx
,
1140 struct r600_textures_info
*dst
,
1142 struct pipe_sampler_view
**views
,
1143 void (*set_resource
)(struct r600_context
*, struct r600_pipe_resource_state
*, unsigned))
1145 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
1149 r600_inval_texture_cache(rctx
);
1151 for (i
= 0; i
< count
; i
++) {
1153 if (((struct r600_resource_texture
*)rviews
[i
]->base
.texture
)->is_depth
)
1154 rctx
->have_depth_texture
= true;
1156 /* Changing from array to non-arrays textures and vice versa requires updating TEX_ARRAY_OVERRIDE. */
1157 if ((rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
1158 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
])
1159 dst
->samplers_dirty
= true;
1161 set_resource(rctx
, &rviews
[i
]->state
, i
+ R600_MAX_CONST_BUFFERS
);
1163 set_resource(rctx
, NULL
, i
+ R600_MAX_CONST_BUFFERS
);
1166 pipe_sampler_view_reference(
1167 (struct pipe_sampler_view
**)&dst
->views
[i
],
1171 for (i
= count
; i
< dst
->n_views
; i
++) {
1172 if (dst
->views
[i
]) {
1173 set_resource(rctx
, NULL
, i
+ R600_MAX_CONST_BUFFERS
);
1174 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
[i
], NULL
);
1178 dst
->n_views
= count
;
1181 static void r600_set_vs_sampler_views(struct pipe_context
*ctx
, unsigned count
,
1182 struct pipe_sampler_view
**views
)
1184 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1185 r600_set_sampler_views(rctx
, &rctx
->vs_samplers
, count
, views
,
1186 r600_context_pipe_state_set_vs_resource
);
1189 static void r600_set_ps_sampler_views(struct pipe_context
*ctx
, unsigned count
,
1190 struct pipe_sampler_view
**views
)
1192 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1193 r600_set_sampler_views(rctx
, &rctx
->ps_samplers
, count
, views
,
1194 r600_context_pipe_state_set_ps_resource
);
1197 static void r600_set_seamless_cubemap(struct r600_context
*rctx
, boolean enable
)
1199 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1203 rstate
->id
= R600_PIPE_STATE_SEAMLESS_CUBEMAP
;
1204 r600_pipe_state_add_reg(rstate
, R_009508_TA_CNTL_AUX
,
1205 (enable
? 0 : S_009508_DISABLE_CUBE_WRAP(1)) |
1206 S_009508_DISABLE_CUBE_ANISO(1) |
1207 S_009508_SYNC_GRADIENT(1) |
1208 S_009508_SYNC_WALKER(1) |
1209 S_009508_SYNC_ALIGNER(1),
1212 free(rctx
->states
[R600_PIPE_STATE_SEAMLESS_CUBEMAP
]);
1213 rctx
->states
[R600_PIPE_STATE_SEAMLESS_CUBEMAP
] = rstate
;
1214 r600_context_pipe_state_set(rctx
, rstate
);
1217 static void r600_bind_samplers(struct r600_context
*rctx
,
1218 struct r600_textures_info
*dst
,
1219 unsigned count
, void **states
)
1221 memcpy(dst
->samplers
, states
, sizeof(void*) * count
);
1222 dst
->n_samplers
= count
;
1223 dst
->samplers_dirty
= true;
1226 static void r600_bind_vs_samplers(struct pipe_context
*ctx
, unsigned count
, void **states
)
1228 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1229 r600_bind_samplers(rctx
, &rctx
->vs_samplers
, count
, states
);
1232 static void r600_bind_ps_samplers(struct pipe_context
*ctx
, unsigned count
, void **states
)
1234 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1235 r600_bind_samplers(rctx
, &rctx
->ps_samplers
, count
, states
);
1238 static void r600_update_samplers(struct r600_context
*rctx
,
1239 struct r600_textures_info
*tex
,
1240 void (*set_sampler
)(struct r600_context
*, struct r600_pipe_state
*, unsigned))
1244 if (tex
->samplers_dirty
) {
1246 for (i
= 0; i
< tex
->n_samplers
; i
++) {
1247 if (!tex
->samplers
[i
])
1250 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1251 * filtering between layers.
1252 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */
1253 if (tex
->views
[i
]) {
1254 if (tex
->views
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
1255 tex
->views
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
1256 tex
->samplers
[i
]->rstate
.regs
[0].value
|= S_03C000_TEX_ARRAY_OVERRIDE(1);
1257 tex
->is_array_sampler
[i
] = true;
1259 tex
->samplers
[i
]->rstate
.regs
[0].value
&= C_03C000_TEX_ARRAY_OVERRIDE
;
1260 tex
->is_array_sampler
[i
] = false;
1264 set_sampler(rctx
, &tex
->samplers
[i
]->rstate
, i
);
1266 if (tex
->samplers
[i
])
1267 seamless
= tex
->samplers
[i
]->seamless_cube_map
;
1271 r600_set_seamless_cubemap(rctx
, seamless
);
1273 tex
->samplers_dirty
= false;
1277 void r600_update_sampler_states(struct r600_context
*rctx
)
1279 r600_update_samplers(rctx
, &rctx
->vs_samplers
,
1280 r600_context_pipe_state_set_vs_sampler
);
1281 r600_update_samplers(rctx
, &rctx
->ps_samplers
,
1282 r600_context_pipe_state_set_ps_sampler
);
1285 static void r600_set_clip_state(struct pipe_context
*ctx
,
1286 const struct pipe_clip_state
*state
)
1288 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1289 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1290 struct pipe_resource
* cbuf
;
1295 rctx
->clip
= *state
;
1296 rstate
->id
= R600_PIPE_STATE_CLIP
;
1297 for (int i
= 0; i
< 6; i
++) {
1298 r600_pipe_state_add_reg(rstate
,
1299 R_028E20_PA_CL_UCP0_X
+ i
* 16,
1300 fui(state
->ucp
[i
][0]), NULL
, 0);
1301 r600_pipe_state_add_reg(rstate
,
1302 R_028E24_PA_CL_UCP0_Y
+ i
* 16,
1303 fui(state
->ucp
[i
][1]) , NULL
, 0);
1304 r600_pipe_state_add_reg(rstate
,
1305 R_028E28_PA_CL_UCP0_Z
+ i
* 16,
1306 fui(state
->ucp
[i
][2]), NULL
, 0);
1307 r600_pipe_state_add_reg(rstate
,
1308 R_028E2C_PA_CL_UCP0_W
+ i
* 16,
1309 fui(state
->ucp
[i
][3]), NULL
, 0);
1312 free(rctx
->states
[R600_PIPE_STATE_CLIP
]);
1313 rctx
->states
[R600_PIPE_STATE_CLIP
] = rstate
;
1314 r600_context_pipe_state_set(rctx
, rstate
);
1316 cbuf
= pipe_user_buffer_create(ctx
->screen
,
1318 4*4*8, /* 8*4 floats */
1319 PIPE_BIND_CONSTANT_BUFFER
);
1320 r600_set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, 1, cbuf
);
1321 pipe_resource_reference(&cbuf
, NULL
);
1324 static void r600_set_polygon_stipple(struct pipe_context
*ctx
,
1325 const struct pipe_poly_stipple
*state
)
1329 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1333 void r600_set_scissor_state(struct r600_context
*rctx
,
1334 const struct pipe_scissor_state
*state
)
1336 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1342 rstate
->id
= R600_PIPE_STATE_SCISSOR
;
1343 tl
= S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
) | S_028240_WINDOW_OFFSET_DISABLE(1);
1344 br
= S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
);
1345 r600_pipe_state_add_reg(rstate
,
1346 R_028250_PA_SC_VPORT_SCISSOR_0_TL
, tl
,
1348 r600_pipe_state_add_reg(rstate
,
1349 R_028254_PA_SC_VPORT_SCISSOR_0_BR
, br
,
1352 free(rctx
->states
[R600_PIPE_STATE_SCISSOR
]);
1353 rctx
->states
[R600_PIPE_STATE_SCISSOR
] = rstate
;
1354 r600_context_pipe_state_set(rctx
, rstate
);
1357 static void r600_pipe_set_scissor_state(struct pipe_context
*ctx
,
1358 const struct pipe_scissor_state
*state
)
1360 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1362 if (rctx
->chip_class
== R600
) {
1363 rctx
->scissor_state
= *state
;
1365 if (!rctx
->scissor_enable
)
1369 r600_set_scissor_state(rctx
, state
);
1372 static void r600_set_viewport_state(struct pipe_context
*ctx
,
1373 const struct pipe_viewport_state
*state
)
1375 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1376 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1381 rctx
->viewport
= *state
;
1382 rstate
->id
= R600_PIPE_STATE_VIEWPORT
;
1383 r600_pipe_state_add_reg(rstate
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]), NULL
, 0);
1384 r600_pipe_state_add_reg(rstate
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]), NULL
, 0);
1385 r600_pipe_state_add_reg(rstate
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]), NULL
, 0);
1386 r600_pipe_state_add_reg(rstate
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]), NULL
, 0);
1387 r600_pipe_state_add_reg(rstate
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]), NULL
, 0);
1388 r600_pipe_state_add_reg(rstate
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]), NULL
, 0);
1390 free(rctx
->states
[R600_PIPE_STATE_VIEWPORT
]);
1391 rctx
->states
[R600_PIPE_STATE_VIEWPORT
] = rstate
;
1392 r600_context_pipe_state_set(rctx
, rstate
);
1395 static void r600_cb(struct r600_context
*rctx
, struct r600_pipe_state
*rstate
,
1396 const struct pipe_framebuffer_state
*state
, int cb
)
1398 struct r600_screen
*rscreen
= rctx
->screen
;
1399 struct r600_resource_texture
*rtex
;
1400 struct r600_surface
*surf
;
1401 unsigned level
= state
->cbufs
[cb
]->u
.tex
.level
;
1402 unsigned pitch
, slice
;
1403 unsigned color_info
;
1404 unsigned format
, swap
, ntype
, endian
;
1406 const struct util_format_description
*desc
;
1408 unsigned blend_bypass
= 0, blend_clamp
= 1;
1410 surf
= (struct r600_surface
*)state
->cbufs
[cb
];
1411 rtex
= (struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
;
1414 rctx
->have_depth_fb
= TRUE
;
1416 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
1417 rtex
= rtex
->flushed_depth_texture
;
1420 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1421 if (!rscreen
->use_surface_alloc
) {
1422 offset
= r600_texture_get_offset(rtex
,
1423 level
, state
->cbufs
[cb
]->u
.tex
.first_layer
);
1424 pitch
= rtex
->pitch_in_blocks
[level
] / 8 - 1;
1425 slice
= rtex
->pitch_in_blocks
[level
] * surf
->aligned_height
/ 64;
1429 color_info
= S_0280A0_ARRAY_MODE(rtex
->array_mode
[level
]);
1431 offset
= rtex
->surface
.level
[level
].offset
;
1432 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1433 offset
+= rtex
->surface
.level
[level
].slice_size
*
1434 state
->cbufs
[cb
]->u
.tex
.first_layer
;
1436 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
1437 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1442 switch (rtex
->surface
.level
[level
].mode
) {
1443 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1444 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED
);
1446 case RADEON_SURF_MODE_1D
:
1447 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1
);
1449 case RADEON_SURF_MODE_2D
:
1450 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1
);
1452 case RADEON_SURF_MODE_LINEAR
:
1454 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL
);
1458 desc
= util_format_description(surf
->base
.format
);
1460 for (i
= 0; i
< 4; i
++) {
1461 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1466 ntype
= V_0280A0_NUMBER_UNORM
;
1467 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1468 ntype
= V_0280A0_NUMBER_SRGB
;
1469 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1470 if (desc
->channel
[i
].normalized
)
1471 ntype
= V_0280A0_NUMBER_SNORM
;
1472 else if (desc
->channel
[i
].pure_integer
)
1473 ntype
= V_0280A0_NUMBER_SINT
;
1474 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1475 if (desc
->channel
[i
].normalized
)
1476 ntype
= V_0280A0_NUMBER_UNORM
;
1477 else if (desc
->channel
[i
].pure_integer
)
1478 ntype
= V_0280A0_NUMBER_UINT
;
1481 format
= r600_translate_colorformat(surf
->base
.format
);
1482 swap
= r600_translate_colorswap(surf
->base
.format
);
1483 if(rtex
->resource
.b
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1484 endian
= ENDIAN_NONE
;
1486 endian
= r600_colorformat_endian_swap(format
);
1489 /* set blend bypass according to docs if SINT/UINT or
1490 8/24 COLOR variants */
1491 if (ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
||
1492 format
== V_0280A0_COLOR_8_24
|| format
== V_0280A0_COLOR_24_8
||
1493 format
== V_0280A0_COLOR_X24_8_32_FLOAT
) {
1498 color_info
|= S_0280A0_FORMAT(format
) |
1499 S_0280A0_COMP_SWAP(swap
) |
1500 S_0280A0_BLEND_BYPASS(blend_bypass
) |
1501 S_0280A0_BLEND_CLAMP(blend_clamp
) |
1502 S_0280A0_NUMBER_TYPE(ntype
) |
1503 S_0280A0_ENDIAN(endian
);
1505 /* EXPORT_NORM is an optimzation that can be enabled for better
1506 * performance in certain cases
1508 if (rctx
->chip_class
== R600
) {
1509 /* EXPORT_NORM can be enabled if:
1510 * - 11-bit or smaller UNORM/SNORM/SRGB
1511 * - BLEND_CLAMP is enabled
1512 * - BLEND_FLOAT32 is disabled
1514 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1515 (desc
->channel
[i
].size
< 12 &&
1516 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1517 ntype
!= V_0280A0_NUMBER_UINT
&&
1518 ntype
!= V_0280A0_NUMBER_SINT
) &&
1519 G_0280A0_BLEND_CLAMP(color_info
) &&
1520 !G_0280A0_BLEND_FLOAT32(color_info
))
1521 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
1523 /* EXPORT_NORM can be enabled if:
1524 * - 11-bit or smaller UNORM/SNORM/SRGB
1525 * - 16-bit or smaller FLOAT
1527 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1528 ((desc
->channel
[i
].size
< 12 &&
1529 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1530 ntype
!= V_0280A0_NUMBER_UINT
&& ntype
!= V_0280A0_NUMBER_SINT
) ||
1531 (desc
->channel
[i
].size
< 17 &&
1532 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)))
1533 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
1536 r600_pipe_state_add_reg(rstate
,
1537 R_028040_CB_COLOR0_BASE
+ cb
* 4,
1538 offset
>> 8, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1539 r600_pipe_state_add_reg(rstate
,
1540 R_0280A0_CB_COLOR0_INFO
+ cb
* 4,
1541 color_info
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1542 r600_pipe_state_add_reg(rstate
,
1543 R_028060_CB_COLOR0_SIZE
+ cb
* 4,
1544 S_028060_PITCH_TILE_MAX(pitch
) |
1545 S_028060_SLICE_TILE_MAX(slice
),
1547 if (!rscreen
->use_surface_alloc
) {
1548 r600_pipe_state_add_reg(rstate
,
1549 R_028080_CB_COLOR0_VIEW
+ cb
* 4,
1550 0x00000000, NULL
, 0);
1552 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1553 r600_pipe_state_add_reg(rstate
,
1554 R_028080_CB_COLOR0_VIEW
+ cb
* 4,
1555 0x00000000, NULL
, 0);
1557 r600_pipe_state_add_reg(rstate
,
1558 R_028080_CB_COLOR0_VIEW
+ cb
* 4,
1559 S_028080_SLICE_START(state
->cbufs
[cb
]->u
.tex
.first_layer
) |
1560 S_028080_SLICE_MAX(state
->cbufs
[cb
]->u
.tex
.last_layer
),
1564 r600_pipe_state_add_reg(rstate
,
1565 R_0280E0_CB_COLOR0_FRAG
+ cb
* 4,
1566 0, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1567 r600_pipe_state_add_reg(rstate
,
1568 R_0280C0_CB_COLOR0_TILE
+ cb
* 4,
1569 0, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1572 static void r600_db(struct r600_context
*rctx
, struct r600_pipe_state
*rstate
,
1573 const struct pipe_framebuffer_state
*state
)
1575 struct r600_screen
*rscreen
= rctx
->screen
;
1576 struct r600_resource_texture
*rtex
;
1577 struct r600_surface
*surf
;
1578 unsigned level
, pitch
, slice
, format
, offset
, array_mode
;
1580 if (state
->zsbuf
== NULL
)
1583 level
= state
->zsbuf
->u
.tex
.level
;
1585 surf
= (struct r600_surface
*)state
->zsbuf
;
1586 rtex
= (struct r600_resource_texture
*)state
->zsbuf
->texture
;
1588 if (!rscreen
->use_surface_alloc
) {
1589 /* XXX remove this once tiling is properly supported */
1590 array_mode
= rtex
->array_mode
[level
] ? rtex
->array_mode
[level
] :
1591 V_0280A0_ARRAY_1D_TILED_THIN1
;
1593 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1594 offset
= r600_texture_get_offset((struct r600_resource_texture
*)state
->zsbuf
->texture
,
1595 level
, state
->zsbuf
->u
.tex
.first_layer
);
1596 pitch
= rtex
->pitch_in_blocks
[level
] / 8 - 1;
1597 slice
= rtex
->pitch_in_blocks
[level
] * surf
->aligned_height
/ 64;
1602 offset
= rtex
->surface
.level
[level
].offset
;
1603 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
1604 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1608 switch (rtex
->surface
.level
[level
].mode
) {
1609 case RADEON_SURF_MODE_2D
:
1610 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
1612 case RADEON_SURF_MODE_1D
:
1613 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1614 case RADEON_SURF_MODE_LINEAR
:
1616 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
1621 format
= r600_translate_dbformat(state
->zsbuf
->texture
->format
);
1623 r600_pipe_state_add_reg(rstate
, R_02800C_DB_DEPTH_BASE
,
1624 offset
>> 8, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1625 r600_pipe_state_add_reg(rstate
, R_028000_DB_DEPTH_SIZE
,
1626 S_028000_PITCH_TILE_MAX(pitch
) | S_028000_SLICE_TILE_MAX(slice
),
1628 if (!rscreen
->use_surface_alloc
) {
1629 r600_pipe_state_add_reg(rstate
, R_028004_DB_DEPTH_VIEW
, 0x00000000, NULL
, 0);
1631 r600_pipe_state_add_reg(rstate
, R_028004_DB_DEPTH_VIEW
,
1632 S_028004_SLICE_START(state
->zsbuf
->u
.tex
.first_layer
) |
1633 S_028004_SLICE_MAX(state
->zsbuf
->u
.tex
.last_layer
),
1636 r600_pipe_state_add_reg(rstate
, R_028010_DB_DEPTH_INFO
,
1637 S_028010_ARRAY_MODE(array_mode
) | S_028010_FORMAT(format
),
1638 &rtex
->resource
, RADEON_USAGE_READWRITE
);
1639 r600_pipe_state_add_reg(rstate
, R_028D34_DB_PREFETCH_LIMIT
,
1640 (surf
->aligned_height
/ 8) - 1, NULL
, 0);
1643 static void r600_set_framebuffer_state(struct pipe_context
*ctx
,
1644 const struct pipe_framebuffer_state
*state
)
1646 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1647 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1648 uint32_t shader_mask
, tl
, br
, shader_control
;
1653 r600_flush_framebuffer(rctx
, false);
1655 /* unreference old buffer and reference new one */
1656 rstate
->id
= R600_PIPE_STATE_FRAMEBUFFER
;
1658 util_copy_framebuffer_state(&rctx
->framebuffer
, state
);
1661 rctx
->have_depth_fb
= 0;
1662 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
1663 r600_cb(rctx
, rstate
, state
, i
);
1666 r600_db(rctx
, rstate
, state
);
1671 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
1672 shader_mask
|= 0xf << (i
* 4);
1673 shader_control
|= 1 << i
;
1675 tl
= S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1676 br
= S_028244_BR_X(state
->width
) | S_028244_BR_Y(state
->height
);
1678 r600_pipe_state_add_reg(rstate
,
1679 R_028204_PA_SC_WINDOW_SCISSOR_TL
, tl
,
1681 r600_pipe_state_add_reg(rstate
,
1682 R_028208_PA_SC_WINDOW_SCISSOR_BR
, br
,
1685 r600_pipe_state_add_reg(rstate
, R_0287A0_CB_SHADER_CONTROL
,
1686 shader_control
, NULL
, 0);
1687 r600_pipe_state_add_reg(rstate
, R_02823C_CB_SHADER_MASK
,
1688 shader_mask
, NULL
, 0);
1690 free(rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
]);
1691 rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
] = rstate
;
1692 r600_context_pipe_state_set(rctx
, rstate
);
1695 r600_polygon_offset_update(rctx
);
1699 static void r600_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1701 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1702 struct r600_atom_db_misc_state
*a
= (struct r600_atom_db_misc_state
*)atom
;
1703 unsigned db_render_control
= 0;
1704 unsigned db_render_override
=
1705 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
) |
1706 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE
) |
1707 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE
);
1709 if (a
->occlusion_query_enabled
) {
1710 if (rctx
->chip_class
>= R700
) {
1711 db_render_control
|= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1713 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
1715 if (a
->flush_depthstencil_enabled
) {
1716 db_render_control
|= S_028D0C_DEPTH_COPY_ENABLE(1) |
1717 S_028D0C_STENCIL_COPY_ENABLE(1) |
1718 S_028D0C_COPY_CENTROID(1);
1721 r600_write_context_reg_seq(cs
, R_028D0C_DB_RENDER_CONTROL
, 2);
1722 r600_write_value(cs
, db_render_control
); /* R_028D0C_DB_RENDER_CONTROL */
1723 r600_write_value(cs
, db_render_override
); /* R_028D10_DB_RENDER_OVERRIDE */
1726 void r600_init_state_functions(struct r600_context
*rctx
)
1728 r600_init_atom(&rctx
->atom_db_misc_state
.atom
, r600_emit_db_misc_state
, 4, 0);
1729 r600_atom_dirty(rctx
, &rctx
->atom_db_misc_state
.atom
);
1731 rctx
->context
.create_blend_state
= r600_create_blend_state
;
1732 rctx
->context
.create_depth_stencil_alpha_state
= r600_create_dsa_state
;
1733 rctx
->context
.create_fs_state
= r600_create_shader_state
;
1734 rctx
->context
.create_rasterizer_state
= r600_create_rs_state
;
1735 rctx
->context
.create_sampler_state
= r600_create_sampler_state
;
1736 rctx
->context
.create_sampler_view
= r600_create_sampler_view
;
1737 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
1738 rctx
->context
.create_vs_state
= r600_create_shader_state
;
1739 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
1740 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
1741 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_samplers
;
1742 rctx
->context
.bind_fs_state
= r600_bind_ps_shader
;
1743 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
1744 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
1745 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_samplers
;
1746 rctx
->context
.bind_vs_state
= r600_bind_vs_shader
;
1747 rctx
->context
.delete_blend_state
= r600_delete_state
;
1748 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
1749 rctx
->context
.delete_fs_state
= r600_delete_ps_shader
;
1750 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
1751 rctx
->context
.delete_sampler_state
= r600_delete_state
;
1752 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_element
;
1753 rctx
->context
.delete_vs_state
= r600_delete_vs_shader
;
1754 rctx
->context
.set_blend_color
= r600_set_blend_color
;
1755 rctx
->context
.set_clip_state
= r600_set_clip_state
;
1756 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1757 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_views
;
1758 rctx
->context
.set_framebuffer_state
= r600_set_framebuffer_state
;
1759 rctx
->context
.set_polygon_stipple
= r600_set_polygon_stipple
;
1760 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
1761 rctx
->context
.set_scissor_state
= r600_pipe_set_scissor_state
;
1762 rctx
->context
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
1763 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1764 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1765 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_views
;
1766 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
1767 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1768 rctx
->context
.redefine_user_buffer
= u_default_redefine_user_buffer
;
1769 rctx
->context
.texture_barrier
= r600_texture_barrier
;
1770 rctx
->context
.create_stream_output_target
= r600_create_so_target
;
1771 rctx
->context
.stream_output_target_destroy
= r600_so_target_destroy
;
1772 rctx
->context
.set_stream_output_targets
= r600_set_so_targets
;
1775 void r600_adjust_gprs(struct r600_context
*rctx
)
1777 struct r600_pipe_state rstate
;
1778 unsigned num_ps_gprs
= rctx
->default_ps_gprs
;
1779 unsigned num_vs_gprs
= rctx
->default_vs_gprs
;
1783 if (rctx
->chip_class
>= EVERGREEN
)
1786 if (!rctx
->ps_shader
|| !rctx
->vs_shader
)
1789 if (rctx
->ps_shader
->shader
.bc
.ngpr
> rctx
->default_ps_gprs
)
1791 diff
= rctx
->ps_shader
->shader
.bc
.ngpr
- rctx
->default_ps_gprs
;
1792 num_vs_gprs
-= diff
;
1793 num_ps_gprs
+= diff
;
1796 if (rctx
->vs_shader
->shader
.bc
.ngpr
> rctx
->default_vs_gprs
)
1798 diff
= rctx
->vs_shader
->shader
.bc
.ngpr
- rctx
->default_vs_gprs
;
1799 num_ps_gprs
-= diff
;
1800 num_vs_gprs
+= diff
;
1804 tmp
|= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
1805 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
1806 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx
->r6xx_num_clause_temp_gprs
);
1808 r600_pipe_state_add_reg(&rstate
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, tmp
, NULL
, 0);
1810 r600_context_pipe_state_set(rctx
, &rstate
);
1813 void r600_init_atom_start_cs(struct r600_context
*rctx
)
1828 int num_ps_stack_entries
;
1829 int num_vs_stack_entries
;
1830 int num_gs_stack_entries
;
1831 int num_es_stack_entries
;
1832 enum radeon_family family
;
1833 struct r600_command_buffer
*cb
= &rctx
->atom_start_cs
;
1837 r600_init_command_buffer(cb
, 256, EMIT_EARLY
);
1839 /* R6xx requires this packet at the start of each command buffer */
1840 if (rctx
->chip_class
== R600
) {
1841 r600_store_value(cb
, PKT3(PKT3_START_3D_CMDBUF
, 0, 0));
1842 r600_store_value(cb
, 0);
1844 /* All asics require this one */
1845 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1846 r600_store_value(cb
, 0x80000000);
1847 r600_store_value(cb
, 0x80000000);
1849 family
= rctx
->family
;
1861 num_ps_threads
= 136;
1862 num_vs_threads
= 48;
1865 num_ps_stack_entries
= 128;
1866 num_vs_stack_entries
= 128;
1867 num_gs_stack_entries
= 0;
1868 num_es_stack_entries
= 0;
1877 num_ps_threads
= 144;
1878 num_vs_threads
= 40;
1881 num_ps_stack_entries
= 40;
1882 num_vs_stack_entries
= 40;
1883 num_gs_stack_entries
= 32;
1884 num_es_stack_entries
= 16;
1896 num_ps_threads
= 136;
1897 num_vs_threads
= 48;
1900 num_ps_stack_entries
= 40;
1901 num_vs_stack_entries
= 40;
1902 num_gs_stack_entries
= 32;
1903 num_es_stack_entries
= 16;
1911 num_ps_threads
= 136;
1912 num_vs_threads
= 48;
1915 num_ps_stack_entries
= 40;
1916 num_vs_stack_entries
= 40;
1917 num_gs_stack_entries
= 32;
1918 num_es_stack_entries
= 16;
1926 num_ps_threads
= 188;
1927 num_vs_threads
= 60;
1930 num_ps_stack_entries
= 256;
1931 num_vs_stack_entries
= 256;
1932 num_gs_stack_entries
= 0;
1933 num_es_stack_entries
= 0;
1942 num_ps_threads
= 188;
1943 num_vs_threads
= 60;
1946 num_ps_stack_entries
= 128;
1947 num_vs_stack_entries
= 128;
1948 num_gs_stack_entries
= 0;
1949 num_es_stack_entries
= 0;
1957 num_ps_threads
= 144;
1958 num_vs_threads
= 48;
1961 num_ps_stack_entries
= 128;
1962 num_vs_stack_entries
= 128;
1963 num_gs_stack_entries
= 0;
1964 num_es_stack_entries
= 0;
1968 rctx
->default_ps_gprs
= num_ps_gprs
;
1969 rctx
->default_vs_gprs
= num_vs_gprs
;
1970 rctx
->r6xx_num_clause_temp_gprs
= num_temp_gprs
;
1982 tmp
|= S_008C00_VC_ENABLE(1);
1985 tmp
|= S_008C00_DX9_CONSTS(0);
1986 tmp
|= S_008C00_ALU_INST_PREFER_VECTOR(1);
1987 tmp
|= S_008C00_PS_PRIO(ps_prio
);
1988 tmp
|= S_008C00_VS_PRIO(vs_prio
);
1989 tmp
|= S_008C00_GS_PRIO(gs_prio
);
1990 tmp
|= S_008C00_ES_PRIO(es_prio
);
1991 r600_store_config_reg(cb
, R_008C00_SQ_CONFIG
, tmp
);
1993 /* SQ_GPR_RESOURCE_MGMT_2 */
1994 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
1995 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
1996 r600_store_config_reg_seq(cb
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, 4);
1997 r600_store_value(cb
, tmp
);
1999 /* SQ_THREAD_RESOURCE_MGMT */
2000 tmp
= S_008C0C_NUM_PS_THREADS(num_ps_threads
);
2001 tmp
|= S_008C0C_NUM_VS_THREADS(num_vs_threads
);
2002 tmp
|= S_008C0C_NUM_GS_THREADS(num_gs_threads
);
2003 tmp
|= S_008C0C_NUM_ES_THREADS(num_es_threads
);
2004 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2006 /* SQ_STACK_RESOURCE_MGMT_1 */
2007 tmp
= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2008 tmp
|= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2009 r600_store_value(cb
, tmp
); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2011 /* SQ_STACK_RESOURCE_MGMT_2 */
2012 tmp
= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2013 tmp
|= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2014 r600_store_value(cb
, tmp
); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2016 r600_store_config_reg(cb
, R_009714_VC_ENHANCE
, 0);
2018 r600_store_context_reg(cb
, R_028350_SX_MISC
, 0);
2020 if (rctx
->chip_class
>= R700
) {
2021 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x00004000);
2022 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0);
2023 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x00420204);
2024 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2026 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0);
2027 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0x82000000);
2028 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x01020204);
2029 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 1);
2031 r600_store_context_reg_seq(cb
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
, 9);
2032 r600_store_value(cb
, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2033 r600_store_value(cb
, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2034 r600_store_value(cb
, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2035 r600_store_value(cb
, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2036 r600_store_value(cb
, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2037 r600_store_value(cb
, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2038 r600_store_value(cb
, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2039 r600_store_value(cb
, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2040 r600_store_value(cb
, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2042 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2043 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2044 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2045 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2046 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2047 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2048 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2049 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2050 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2051 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2052 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2053 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2054 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2055 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE, 0); */
2057 r600_store_context_reg(cb
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
2058 r600_store_context_reg(cb
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 0);
2059 r600_store_context_reg(cb
, R_028AA4_VGT_INSTANCE_STEP_RATE_1
, 0);
2061 r600_store_context_reg_seq(cb
, R_028AB0_VGT_STRMOUT_EN
, 3);
2062 r600_store_value(cb
, 0); /* R_028AB0_VGT_STRMOUT_EN */
2063 r600_store_value(cb
, 1); /* R_028AB4_VGT_REUSE_OFF */
2064 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2066 r600_store_context_reg(cb
, R_028B20_VGT_STRMOUT_BUFFER_EN
, 0);
2068 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2069 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2070 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2072 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2074 r600_store_context_reg_seq(cb
, R_028028_DB_STENCIL_CLEAR
, 2);
2075 r600_store_value(cb
, 0); /* R_028028_DB_STENCIL_CLEAR */
2076 r600_store_value(cb
, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2078 r600_store_context_reg_seq(cb
, R_0286DC_SPI_FOG_CNTL
, 3);
2079 r600_store_value(cb
, 0); /* R_0286DC_SPI_FOG_CNTL */
2080 r600_store_value(cb
, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2081 r600_store_value(cb
, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2083 r600_store_context_reg_seq(cb
, R_028D2C_DB_SRESULTS_COMPARE_STATE1
, 2);
2084 r600_store_value(cb
, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2085 r600_store_value(cb
, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2087 r600_store_context_reg(cb
, R_028D44_DB_ALPHA_TO_MASK
, 0xAA00);
2089 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2090 r600_store_context_reg(cb
, R_028A48_PA_SC_MPASS_PS_CNTL
, 0);
2092 r600_store_context_reg_seq(cb
, R_028C00_PA_SC_LINE_CNTL
, 2);
2093 r600_store_value(cb
, 0x400); /* R_028C00_PA_SC_LINE_CNTL */
2094 r600_store_value(cb
, 0); /* R_028C04_PA_SC_AA_CONFIG */
2096 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 6);
2097 r600_store_value(cb
, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2098 r600_store_value(cb
, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2099 r600_store_value(cb
, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2100 r600_store_value(cb
, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2101 r600_store_value(cb
, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
2102 r600_store_value(cb
, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX */
2104 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
2105 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2106 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2108 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x43F);
2110 r600_store_context_reg_seq(cb
, R_028100_CB_COLOR0_MASK
, 8);
2111 for (i
= 0; i
< 8; i
++) {
2112 r600_store_value(cb
, 0);
2115 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2116 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2118 if (rctx
->chip_class
>= R700
) {
2119 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2122 r600_store_context_reg_seq(cb
, R_028C30_CB_CLRCMP_CONTROL
, 4);
2123 r600_store_value(cb
, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2124 r600_store_value(cb
, 0); /* R_028C34_CB_CLRCMP_SRC */
2125 r600_store_value(cb
, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2126 r600_store_value(cb
, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2128 r600_store_context_reg(cb
, R_028C48_PA_SC_AA_MASK
, 0xFFFFFFFF);
2130 r600_store_context_reg(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
2132 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2133 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2134 r600_store_value(cb
, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2136 r600_store_context_reg_seq(cb
, R_0288CC_SQ_PGM_CF_OFFSET_PS
, 2);
2137 r600_store_value(cb
, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2138 r600_store_value(cb
, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2140 r600_store_context_reg(cb
, R_0288A4_SQ_PGM_RESOURCES_FS
, 0);
2141 r600_store_context_reg(cb
, R_0288DC_SQ_PGM_CF_OFFSET_FS
, 0);
2143 if (rctx
->chip_class
== R700
)
2144 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2145 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2147 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
, 0x1000FFF);
2148 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
+ (32 * 4), 0x1000FFF);
2151 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2153 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2154 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2155 struct r600_shader
*rshader
= &shader
->shader
;
2156 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
2157 int pos_index
= -1, face_index
= -1;
2158 unsigned tmp
, sid
, ufi
= 0;
2159 int need_linear
= 0;
2163 for (i
= 0; i
< rshader
->ninput
; i
++) {
2164 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2166 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
2169 sid
= rshader
->input
[i
].spi_sid
;
2171 tmp
= S_028644_SEMANTIC(sid
);
2173 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
2174 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2175 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
2176 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
))
2177 tmp
|= S_028644_FLAT_SHADE(1);
2179 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
2180 rctx
->sprite_coord_enable
& (1 << rshader
->input
[i
].sid
)) {
2181 tmp
|= S_028644_PT_SPRITE_TEX(1);
2184 if (rshader
->input
[i
].centroid
)
2185 tmp
|= S_028644_SEL_CENTROID(1);
2187 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
) {
2189 tmp
|= S_028644_SEL_LINEAR(1);
2192 r600_pipe_state_add_reg(rstate
, R_028644_SPI_PS_INPUT_CNTL_0
+ i
* 4,
2196 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2197 for (i
= 0; i
< rshader
->noutput
; i
++) {
2198 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2199 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(1);
2200 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2201 db_shader_control
|= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
2203 if (rshader
->uses_kill
)
2204 db_shader_control
|= S_02880C_KILL_ENABLE(1);
2208 for (i
= 0; i
< rshader
->noutput
; i
++) {
2209 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
2210 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2212 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
2216 exports_ps
|= S_028854_EXPORT_COLORS(num_cout
);
2218 /* always at least export 1 component per pixel */
2222 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(rshader
->ninput
) |
2223 S_0286CC_PERSP_GRADIENT_ENA(1)|
2224 S_0286CC_LINEAR_GRADIENT_ENA(need_linear
);
2226 if (pos_index
!= -1) {
2227 spi_ps_in_control_0
|= (S_0286CC_POSITION_ENA(1) |
2228 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
2229 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
) |
2230 S_0286CC_BARYC_SAMPLE_CNTL(1));
2234 spi_ps_in_control_1
= 0;
2235 if (face_index
!= -1) {
2236 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
2237 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
2240 /* HW bug in original R600 */
2241 if (rctx
->family
== CHIP_R600
)
2244 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
, spi_ps_in_control_0
, NULL
, 0);
2245 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
, spi_ps_in_control_1
, NULL
, 0);
2246 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
, NULL
, 0);
2247 r600_pipe_state_add_reg(rstate
,
2248 R_028840_SQ_PGM_START_PS
,
2249 0, shader
->bo
, RADEON_USAGE_READ
);
2250 r600_pipe_state_add_reg(rstate
,
2251 R_028850_SQ_PGM_RESOURCES_PS
,
2252 S_028850_NUM_GPRS(rshader
->bc
.ngpr
) |
2253 S_028850_STACK_SIZE(rshader
->bc
.nstack
) |
2254 S_028850_UNCACHED_FIRST_INST(ufi
),
2256 r600_pipe_state_add_reg(rstate
,
2257 R_028854_SQ_PGM_EXPORTS_PS
,
2258 exports_ps
, NULL
, 0);
2259 /* only set some bits here, the other bits are set in the dsa state */
2260 r600_pipe_state_add_reg(rstate
, R_02880C_DB_SHADER_CONTROL
,
2264 shader
->sprite_coord_enable
= rctx
->sprite_coord_enable
;
2265 if (rctx
->rasterizer
)
2266 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
2269 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2271 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2272 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2273 struct r600_shader
*rshader
= &shader
->shader
;
2274 unsigned spi_vs_out_id
[10] = {};
2275 unsigned i
, tmp
, nparams
= 0;
2277 /* clear previous register */
2280 for (i
= 0; i
< rshader
->noutput
; i
++) {
2281 if (rshader
->output
[i
].spi_sid
) {
2282 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
2283 spi_vs_out_id
[nparams
/ 4] |= tmp
;
2288 for (i
= 0; i
< 10; i
++) {
2289 r600_pipe_state_add_reg(rstate
,
2290 R_028614_SPI_VS_OUT_ID_0
+ i
* 4,
2291 spi_vs_out_id
[i
], NULL
, 0);
2294 /* Certain attributes (position, psize, etc.) don't count as params.
2295 * VS is required to export at least one param and r600_shader_from_tgsi()
2296 * takes care of adding a dummy export.
2301 r600_pipe_state_add_reg(rstate
,
2302 R_0286C4_SPI_VS_OUT_CONFIG
,
2303 S_0286C4_VS_EXPORT_COUNT(nparams
- 1),
2305 r600_pipe_state_add_reg(rstate
,
2306 R_028868_SQ_PGM_RESOURCES_VS
,
2307 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
2308 S_028868_STACK_SIZE(rshader
->bc
.nstack
),
2310 r600_pipe_state_add_reg(rstate
,
2311 R_028858_SQ_PGM_START_VS
,
2312 0, shader
->bo
, RADEON_USAGE_READ
);
2314 shader
->pa_cl_vs_out_cntl
=
2315 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
2316 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
2317 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
2318 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
);
2321 void r600_fetch_shader(struct pipe_context
*ctx
,
2322 struct r600_vertex_element
*ve
)
2324 struct r600_pipe_state
*rstate
;
2325 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2327 rstate
= &ve
->rstate
;
2328 rstate
->id
= R600_PIPE_STATE_FETCH_SHADER
;
2330 r600_pipe_state_add_reg(rstate
, R_028894_SQ_PGM_START_FS
,
2332 ve
->fetch_shader
, RADEON_USAGE_READ
);
2335 void *r600_create_db_flush_dsa(struct r600_context
*rctx
)
2337 struct pipe_depth_stencil_alpha_state dsa
;
2338 struct r600_pipe_state
*rstate
;
2339 struct r600_pipe_dsa
*dsa_state
;
2340 boolean quirk
= false;
2342 if (rctx
->family
== CHIP_RV610
|| rctx
->family
== CHIP_RV630
||
2343 rctx
->family
== CHIP_RV620
|| rctx
->family
== CHIP_RV635
)
2346 memset(&dsa
, 0, sizeof(dsa
));
2349 dsa
.depth
.enabled
= 1;
2350 dsa
.depth
.func
= PIPE_FUNC_LEQUAL
;
2351 dsa
.stencil
[0].enabled
= 1;
2352 dsa
.stencil
[0].func
= PIPE_FUNC_ALWAYS
;
2353 dsa
.stencil
[0].zpass_op
= PIPE_STENCIL_OP_KEEP
;
2354 dsa
.stencil
[0].zfail_op
= PIPE_STENCIL_OP_INCR
;
2355 dsa
.stencil
[0].writemask
= 0xff;
2358 rstate
= rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
2359 dsa_state
= (struct r600_pipe_dsa
*)rstate
;
2360 dsa_state
->is_flush
= true;
2364 void r600_pipe_init_buffer_resource(struct r600_context
*rctx
,
2365 struct r600_pipe_resource_state
*rstate
)
2367 rstate
->id
= R600_PIPE_STATE_RESOURCE
;
2369 rstate
->bo
[0] = NULL
;
2376 rstate
->val
[6] = 0xc0000000;
2379 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state
*rstate
,
2380 struct r600_resource
*rbuffer
,
2381 unsigned offset
, unsigned stride
,
2382 enum radeon_bo_usage usage
)
2384 rstate
->val
[0] = offset
;
2385 rstate
->bo
[0] = rbuffer
;
2386 rstate
->bo_usage
[0] = usage
;
2387 rstate
->val
[1] = rbuffer
->buf
->size
- offset
- 1;
2388 rstate
->val
[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2389 S_038008_STRIDE(stride
);