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r600g: atomize stencil ref state
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600d.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31
32 static uint32_t r600_translate_blend_function(int blend_func)
33 {
34 switch (blend_func) {
35 case PIPE_BLEND_ADD:
36 return V_028804_COMB_DST_PLUS_SRC;
37 case PIPE_BLEND_SUBTRACT:
38 return V_028804_COMB_SRC_MINUS_DST;
39 case PIPE_BLEND_REVERSE_SUBTRACT:
40 return V_028804_COMB_DST_MINUS_SRC;
41 case PIPE_BLEND_MIN:
42 return V_028804_COMB_MIN_DST_SRC;
43 case PIPE_BLEND_MAX:
44 return V_028804_COMB_MAX_DST_SRC;
45 default:
46 R600_ERR("Unknown blend function %d\n", blend_func);
47 assert(0);
48 break;
49 }
50 return 0;
51 }
52
53 static uint32_t r600_translate_blend_factor(int blend_fact)
54 {
55 switch (blend_fact) {
56 case PIPE_BLENDFACTOR_ONE:
57 return V_028804_BLEND_ONE;
58 case PIPE_BLENDFACTOR_SRC_COLOR:
59 return V_028804_BLEND_SRC_COLOR;
60 case PIPE_BLENDFACTOR_SRC_ALPHA:
61 return V_028804_BLEND_SRC_ALPHA;
62 case PIPE_BLENDFACTOR_DST_ALPHA:
63 return V_028804_BLEND_DST_ALPHA;
64 case PIPE_BLENDFACTOR_DST_COLOR:
65 return V_028804_BLEND_DST_COLOR;
66 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
67 return V_028804_BLEND_SRC_ALPHA_SATURATE;
68 case PIPE_BLENDFACTOR_CONST_COLOR:
69 return V_028804_BLEND_CONST_COLOR;
70 case PIPE_BLENDFACTOR_CONST_ALPHA:
71 return V_028804_BLEND_CONST_ALPHA;
72 case PIPE_BLENDFACTOR_ZERO:
73 return V_028804_BLEND_ZERO;
74 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
75 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
76 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
77 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
78 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
79 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
80 case PIPE_BLENDFACTOR_INV_DST_COLOR:
81 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
82 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
83 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
84 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
85 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
86 case PIPE_BLENDFACTOR_SRC1_COLOR:
87 return V_028804_BLEND_SRC1_COLOR;
88 case PIPE_BLENDFACTOR_SRC1_ALPHA:
89 return V_028804_BLEND_SRC1_ALPHA;
90 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
91 return V_028804_BLEND_INV_SRC1_COLOR;
92 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
93 return V_028804_BLEND_INV_SRC1_ALPHA;
94 default:
95 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
96 assert(0);
97 break;
98 }
99 return 0;
100 }
101
102 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
103 {
104 switch (dim) {
105 default:
106 case PIPE_TEXTURE_1D:
107 return V_038000_SQ_TEX_DIM_1D;
108 case PIPE_TEXTURE_1D_ARRAY:
109 return V_038000_SQ_TEX_DIM_1D_ARRAY;
110 case PIPE_TEXTURE_2D:
111 case PIPE_TEXTURE_RECT:
112 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
113 V_038000_SQ_TEX_DIM_2D;
114 case PIPE_TEXTURE_2D_ARRAY:
115 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
116 V_038000_SQ_TEX_DIM_2D_ARRAY;
117 case PIPE_TEXTURE_3D:
118 return V_038000_SQ_TEX_DIM_3D;
119 case PIPE_TEXTURE_CUBE:
120 return V_038000_SQ_TEX_DIM_CUBEMAP;
121 }
122 }
123
124 static uint32_t r600_translate_dbformat(enum pipe_format format)
125 {
126 switch (format) {
127 case PIPE_FORMAT_Z16_UNORM:
128 return V_028010_DEPTH_16;
129 case PIPE_FORMAT_Z24X8_UNORM:
130 return V_028010_DEPTH_X8_24;
131 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
132 return V_028010_DEPTH_8_24;
133 case PIPE_FORMAT_Z32_FLOAT:
134 return V_028010_DEPTH_32_FLOAT;
135 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
136 return V_028010_DEPTH_X24_8_32_FLOAT;
137 default:
138 return ~0U;
139 }
140 }
141
142 static uint32_t r600_translate_colorswap(enum pipe_format format)
143 {
144 switch (format) {
145 /* 8-bit buffers. */
146 case PIPE_FORMAT_A8_UNORM:
147 case PIPE_FORMAT_A8_SNORM:
148 case PIPE_FORMAT_A8_UINT:
149 case PIPE_FORMAT_A8_SINT:
150 case PIPE_FORMAT_A16_UNORM:
151 case PIPE_FORMAT_A16_SNORM:
152 case PIPE_FORMAT_A16_UINT:
153 case PIPE_FORMAT_A16_SINT:
154 case PIPE_FORMAT_A16_FLOAT:
155 case PIPE_FORMAT_A32_UINT:
156 case PIPE_FORMAT_A32_SINT:
157 case PIPE_FORMAT_A32_FLOAT:
158 case PIPE_FORMAT_R4A4_UNORM:
159 return V_0280A0_SWAP_ALT_REV;
160 case PIPE_FORMAT_I8_UNORM:
161 case PIPE_FORMAT_I8_SNORM:
162 case PIPE_FORMAT_I8_UINT:
163 case PIPE_FORMAT_I8_SINT:
164 case PIPE_FORMAT_L8_UNORM:
165 case PIPE_FORMAT_L8_SNORM:
166 case PIPE_FORMAT_L8_UINT:
167 case PIPE_FORMAT_L8_SINT:
168 case PIPE_FORMAT_L8_SRGB:
169 case PIPE_FORMAT_L16_UNORM:
170 case PIPE_FORMAT_L16_SNORM:
171 case PIPE_FORMAT_L16_UINT:
172 case PIPE_FORMAT_L16_SINT:
173 case PIPE_FORMAT_L16_FLOAT:
174 case PIPE_FORMAT_L32_UINT:
175 case PIPE_FORMAT_L32_SINT:
176 case PIPE_FORMAT_L32_FLOAT:
177 case PIPE_FORMAT_I16_UNORM:
178 case PIPE_FORMAT_I16_SNORM:
179 case PIPE_FORMAT_I16_UINT:
180 case PIPE_FORMAT_I16_SINT:
181 case PIPE_FORMAT_I16_FLOAT:
182 case PIPE_FORMAT_I32_UINT:
183 case PIPE_FORMAT_I32_SINT:
184 case PIPE_FORMAT_I32_FLOAT:
185 case PIPE_FORMAT_R8_UNORM:
186 case PIPE_FORMAT_R8_SNORM:
187 case PIPE_FORMAT_R8_UINT:
188 case PIPE_FORMAT_R8_SINT:
189 return V_0280A0_SWAP_STD;
190
191 case PIPE_FORMAT_L4A4_UNORM:
192 case PIPE_FORMAT_A4R4_UNORM:
193 return V_0280A0_SWAP_ALT;
194
195 /* 16-bit buffers. */
196 case PIPE_FORMAT_B5G6R5_UNORM:
197 return V_0280A0_SWAP_STD_REV;
198
199 case PIPE_FORMAT_B5G5R5A1_UNORM:
200 case PIPE_FORMAT_B5G5R5X1_UNORM:
201 return V_0280A0_SWAP_ALT;
202
203 case PIPE_FORMAT_B4G4R4A4_UNORM:
204 case PIPE_FORMAT_B4G4R4X4_UNORM:
205 return V_0280A0_SWAP_ALT;
206
207 case PIPE_FORMAT_Z16_UNORM:
208 return V_0280A0_SWAP_STD;
209
210 case PIPE_FORMAT_L8A8_UNORM:
211 case PIPE_FORMAT_L8A8_SNORM:
212 case PIPE_FORMAT_L8A8_UINT:
213 case PIPE_FORMAT_L8A8_SINT:
214 case PIPE_FORMAT_L8A8_SRGB:
215 case PIPE_FORMAT_L16A16_UNORM:
216 case PIPE_FORMAT_L16A16_SNORM:
217 case PIPE_FORMAT_L16A16_UINT:
218 case PIPE_FORMAT_L16A16_SINT:
219 case PIPE_FORMAT_L16A16_FLOAT:
220 case PIPE_FORMAT_L32A32_UINT:
221 case PIPE_FORMAT_L32A32_SINT:
222 case PIPE_FORMAT_L32A32_FLOAT:
223 return V_0280A0_SWAP_ALT;
224 case PIPE_FORMAT_R8G8_UNORM:
225 case PIPE_FORMAT_R8G8_SNORM:
226 case PIPE_FORMAT_R8G8_UINT:
227 case PIPE_FORMAT_R8G8_SINT:
228 return V_0280A0_SWAP_STD;
229
230 case PIPE_FORMAT_R16_UNORM:
231 case PIPE_FORMAT_R16_SNORM:
232 case PIPE_FORMAT_R16_UINT:
233 case PIPE_FORMAT_R16_SINT:
234 case PIPE_FORMAT_R16_FLOAT:
235 return V_0280A0_SWAP_STD;
236
237 /* 32-bit buffers. */
238
239 case PIPE_FORMAT_A8B8G8R8_SRGB:
240 return V_0280A0_SWAP_STD_REV;
241 case PIPE_FORMAT_B8G8R8A8_SRGB:
242 return V_0280A0_SWAP_ALT;
243
244 case PIPE_FORMAT_B8G8R8A8_UNORM:
245 case PIPE_FORMAT_B8G8R8X8_UNORM:
246 return V_0280A0_SWAP_ALT;
247
248 case PIPE_FORMAT_A8R8G8B8_UNORM:
249 case PIPE_FORMAT_X8R8G8B8_UNORM:
250 return V_0280A0_SWAP_ALT_REV;
251 case PIPE_FORMAT_R8G8B8A8_SNORM:
252 case PIPE_FORMAT_R8G8B8A8_UNORM:
253 case PIPE_FORMAT_R8G8B8X8_UNORM:
254 case PIPE_FORMAT_R8G8B8A8_SINT:
255 case PIPE_FORMAT_R8G8B8A8_UINT:
256 return V_0280A0_SWAP_STD;
257
258 case PIPE_FORMAT_A8B8G8R8_UNORM:
259 case PIPE_FORMAT_X8B8G8R8_UNORM:
260 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
261 return V_0280A0_SWAP_STD_REV;
262
263 case PIPE_FORMAT_Z24X8_UNORM:
264 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
265 return V_0280A0_SWAP_STD;
266
267 case PIPE_FORMAT_X8Z24_UNORM:
268 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
269 return V_0280A0_SWAP_STD;
270
271 case PIPE_FORMAT_R10G10B10A2_UNORM:
272 case PIPE_FORMAT_R10G10B10X2_SNORM:
273 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
274 return V_0280A0_SWAP_STD;
275
276 case PIPE_FORMAT_B10G10R10A2_UNORM:
277 case PIPE_FORMAT_B10G10R10A2_UINT:
278 return V_0280A0_SWAP_ALT;
279
280 case PIPE_FORMAT_R11G11B10_FLOAT:
281 case PIPE_FORMAT_R16G16_UNORM:
282 case PIPE_FORMAT_R16G16_SNORM:
283 case PIPE_FORMAT_R16G16_FLOAT:
284 case PIPE_FORMAT_R16G16_UINT:
285 case PIPE_FORMAT_R16G16_SINT:
286 case PIPE_FORMAT_R32_UINT:
287 case PIPE_FORMAT_R32_SINT:
288 case PIPE_FORMAT_R32_FLOAT:
289 case PIPE_FORMAT_Z32_FLOAT:
290 return V_0280A0_SWAP_STD;
291
292 /* 64-bit buffers. */
293 case PIPE_FORMAT_R32G32_FLOAT:
294 case PIPE_FORMAT_R32G32_UINT:
295 case PIPE_FORMAT_R32G32_SINT:
296 case PIPE_FORMAT_R16G16B16A16_UNORM:
297 case PIPE_FORMAT_R16G16B16A16_SNORM:
298 case PIPE_FORMAT_R16G16B16A16_UINT:
299 case PIPE_FORMAT_R16G16B16A16_SINT:
300 case PIPE_FORMAT_R16G16B16A16_FLOAT:
301 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
302
303 /* 128-bit buffers. */
304 case PIPE_FORMAT_R32G32B32A32_FLOAT:
305 case PIPE_FORMAT_R32G32B32A32_SNORM:
306 case PIPE_FORMAT_R32G32B32A32_UNORM:
307 case PIPE_FORMAT_R32G32B32A32_SINT:
308 case PIPE_FORMAT_R32G32B32A32_UINT:
309 return V_0280A0_SWAP_STD;
310 default:
311 R600_ERR("unsupported colorswap format %d\n", format);
312 return ~0U;
313 }
314 return ~0U;
315 }
316
317 static uint32_t r600_translate_colorformat(enum pipe_format format)
318 {
319 switch (format) {
320 case PIPE_FORMAT_L4A4_UNORM:
321 case PIPE_FORMAT_R4A4_UNORM:
322 case PIPE_FORMAT_A4R4_UNORM:
323 return V_0280A0_COLOR_4_4;
324
325 /* 8-bit buffers. */
326 case PIPE_FORMAT_A8_UNORM:
327 case PIPE_FORMAT_A8_SNORM:
328 case PIPE_FORMAT_A8_UINT:
329 case PIPE_FORMAT_A8_SINT:
330 case PIPE_FORMAT_I8_UNORM:
331 case PIPE_FORMAT_I8_SNORM:
332 case PIPE_FORMAT_I8_UINT:
333 case PIPE_FORMAT_I8_SINT:
334 case PIPE_FORMAT_L8_UNORM:
335 case PIPE_FORMAT_L8_SNORM:
336 case PIPE_FORMAT_L8_UINT:
337 case PIPE_FORMAT_L8_SINT:
338 case PIPE_FORMAT_L8_SRGB:
339 case PIPE_FORMAT_R8_UNORM:
340 case PIPE_FORMAT_R8_SNORM:
341 case PIPE_FORMAT_R8_UINT:
342 case PIPE_FORMAT_R8_SINT:
343 return V_0280A0_COLOR_8;
344
345 /* 16-bit buffers. */
346 case PIPE_FORMAT_B5G6R5_UNORM:
347 return V_0280A0_COLOR_5_6_5;
348
349 case PIPE_FORMAT_B5G5R5A1_UNORM:
350 case PIPE_FORMAT_B5G5R5X1_UNORM:
351 return V_0280A0_COLOR_1_5_5_5;
352
353 case PIPE_FORMAT_B4G4R4A4_UNORM:
354 case PIPE_FORMAT_B4G4R4X4_UNORM:
355 return V_0280A0_COLOR_4_4_4_4;
356
357 case PIPE_FORMAT_Z16_UNORM:
358 return V_0280A0_COLOR_16;
359
360 case PIPE_FORMAT_L8A8_UNORM:
361 case PIPE_FORMAT_L8A8_SNORM:
362 case PIPE_FORMAT_L8A8_UINT:
363 case PIPE_FORMAT_L8A8_SINT:
364 case PIPE_FORMAT_L8A8_SRGB:
365 case PIPE_FORMAT_R8G8_UNORM:
366 case PIPE_FORMAT_R8G8_SNORM:
367 case PIPE_FORMAT_R8G8_UINT:
368 case PIPE_FORMAT_R8G8_SINT:
369 return V_0280A0_COLOR_8_8;
370
371 case PIPE_FORMAT_R16_UNORM:
372 case PIPE_FORMAT_R16_SNORM:
373 case PIPE_FORMAT_R16_UINT:
374 case PIPE_FORMAT_R16_SINT:
375 case PIPE_FORMAT_A16_UNORM:
376 case PIPE_FORMAT_A16_SNORM:
377 case PIPE_FORMAT_A16_UINT:
378 case PIPE_FORMAT_A16_SINT:
379 case PIPE_FORMAT_L16_UNORM:
380 case PIPE_FORMAT_L16_SNORM:
381 case PIPE_FORMAT_L16_UINT:
382 case PIPE_FORMAT_L16_SINT:
383 case PIPE_FORMAT_I16_UNORM:
384 case PIPE_FORMAT_I16_SNORM:
385 case PIPE_FORMAT_I16_UINT:
386 case PIPE_FORMAT_I16_SINT:
387 return V_0280A0_COLOR_16;
388
389 case PIPE_FORMAT_R16_FLOAT:
390 case PIPE_FORMAT_A16_FLOAT:
391 case PIPE_FORMAT_L16_FLOAT:
392 case PIPE_FORMAT_I16_FLOAT:
393 return V_0280A0_COLOR_16_FLOAT;
394
395 /* 32-bit buffers. */
396 case PIPE_FORMAT_A8B8G8R8_SRGB:
397 case PIPE_FORMAT_A8B8G8R8_UNORM:
398 case PIPE_FORMAT_A8R8G8B8_UNORM:
399 case PIPE_FORMAT_B8G8R8A8_SRGB:
400 case PIPE_FORMAT_B8G8R8A8_UNORM:
401 case PIPE_FORMAT_B8G8R8X8_UNORM:
402 case PIPE_FORMAT_R8G8B8A8_SNORM:
403 case PIPE_FORMAT_R8G8B8A8_UNORM:
404 case PIPE_FORMAT_R8G8B8X8_UNORM:
405 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
406 case PIPE_FORMAT_X8B8G8R8_UNORM:
407 case PIPE_FORMAT_X8R8G8B8_UNORM:
408 case PIPE_FORMAT_R8G8B8A8_SINT:
409 case PIPE_FORMAT_R8G8B8A8_UINT:
410 return V_0280A0_COLOR_8_8_8_8;
411
412 case PIPE_FORMAT_R10G10B10A2_UNORM:
413 case PIPE_FORMAT_R10G10B10X2_SNORM:
414 case PIPE_FORMAT_B10G10R10A2_UNORM:
415 case PIPE_FORMAT_B10G10R10A2_UINT:
416 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
417 return V_0280A0_COLOR_2_10_10_10;
418
419 case PIPE_FORMAT_Z24X8_UNORM:
420 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
421 return V_0280A0_COLOR_8_24;
422
423 case PIPE_FORMAT_X8Z24_UNORM:
424 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
425 return V_0280A0_COLOR_24_8;
426
427 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
428 return V_0280A0_COLOR_X24_8_32_FLOAT;
429
430 case PIPE_FORMAT_R32_UINT:
431 case PIPE_FORMAT_R32_SINT:
432 case PIPE_FORMAT_A32_UINT:
433 case PIPE_FORMAT_A32_SINT:
434 case PIPE_FORMAT_L32_UINT:
435 case PIPE_FORMAT_L32_SINT:
436 case PIPE_FORMAT_I32_UINT:
437 case PIPE_FORMAT_I32_SINT:
438 return V_0280A0_COLOR_32;
439
440 case PIPE_FORMAT_R32_FLOAT:
441 case PIPE_FORMAT_A32_FLOAT:
442 case PIPE_FORMAT_L32_FLOAT:
443 case PIPE_FORMAT_I32_FLOAT:
444 case PIPE_FORMAT_Z32_FLOAT:
445 return V_0280A0_COLOR_32_FLOAT;
446
447 case PIPE_FORMAT_R16G16_FLOAT:
448 case PIPE_FORMAT_L16A16_FLOAT:
449 return V_0280A0_COLOR_16_16_FLOAT;
450
451 case PIPE_FORMAT_R16G16_UNORM:
452 case PIPE_FORMAT_R16G16_SNORM:
453 case PIPE_FORMAT_R16G16_UINT:
454 case PIPE_FORMAT_R16G16_SINT:
455 case PIPE_FORMAT_L16A16_UNORM:
456 case PIPE_FORMAT_L16A16_SNORM:
457 case PIPE_FORMAT_L16A16_UINT:
458 case PIPE_FORMAT_L16A16_SINT:
459 return V_0280A0_COLOR_16_16;
460
461 case PIPE_FORMAT_R11G11B10_FLOAT:
462 return V_0280A0_COLOR_10_11_11_FLOAT;
463
464 /* 64-bit buffers. */
465 case PIPE_FORMAT_R16G16B16A16_UINT:
466 case PIPE_FORMAT_R16G16B16A16_SINT:
467 case PIPE_FORMAT_R16G16B16A16_UNORM:
468 case PIPE_FORMAT_R16G16B16A16_SNORM:
469 return V_0280A0_COLOR_16_16_16_16;
470
471 case PIPE_FORMAT_R16G16B16A16_FLOAT:
472 return V_0280A0_COLOR_16_16_16_16_FLOAT;
473
474 case PIPE_FORMAT_R32G32_FLOAT:
475 case PIPE_FORMAT_L32A32_FLOAT:
476 return V_0280A0_COLOR_32_32_FLOAT;
477
478 case PIPE_FORMAT_R32G32_SINT:
479 case PIPE_FORMAT_R32G32_UINT:
480 case PIPE_FORMAT_L32A32_UINT:
481 case PIPE_FORMAT_L32A32_SINT:
482 return V_0280A0_COLOR_32_32;
483
484 /* 128-bit buffers. */
485 case PIPE_FORMAT_R32G32B32A32_FLOAT:
486 return V_0280A0_COLOR_32_32_32_32_FLOAT;
487 case PIPE_FORMAT_R32G32B32A32_SNORM:
488 case PIPE_FORMAT_R32G32B32A32_UNORM:
489 case PIPE_FORMAT_R32G32B32A32_SINT:
490 case PIPE_FORMAT_R32G32B32A32_UINT:
491 return V_0280A0_COLOR_32_32_32_32;
492
493 /* YUV buffers. */
494 case PIPE_FORMAT_UYVY:
495 case PIPE_FORMAT_YUYV:
496 default:
497 return ~0U; /* Unsupported. */
498 }
499 }
500
501 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
502 {
503 if (R600_BIG_ENDIAN) {
504 switch(colorformat) {
505 case V_0280A0_COLOR_4_4:
506 return ENDIAN_NONE;
507
508 /* 8-bit buffers. */
509 case V_0280A0_COLOR_8:
510 return ENDIAN_NONE;
511
512 /* 16-bit buffers. */
513 case V_0280A0_COLOR_5_6_5:
514 case V_0280A0_COLOR_1_5_5_5:
515 case V_0280A0_COLOR_4_4_4_4:
516 case V_0280A0_COLOR_16:
517 case V_0280A0_COLOR_8_8:
518 return ENDIAN_8IN16;
519
520 /* 32-bit buffers. */
521 case V_0280A0_COLOR_8_8_8_8:
522 case V_0280A0_COLOR_2_10_10_10:
523 case V_0280A0_COLOR_8_24:
524 case V_0280A0_COLOR_24_8:
525 case V_0280A0_COLOR_32_FLOAT:
526 case V_0280A0_COLOR_16_16_FLOAT:
527 case V_0280A0_COLOR_16_16:
528 return ENDIAN_8IN32;
529
530 /* 64-bit buffers. */
531 case V_0280A0_COLOR_16_16_16_16:
532 case V_0280A0_COLOR_16_16_16_16_FLOAT:
533 return ENDIAN_8IN16;
534
535 case V_0280A0_COLOR_32_32_FLOAT:
536 case V_0280A0_COLOR_32_32:
537 case V_0280A0_COLOR_X24_8_32_FLOAT:
538 return ENDIAN_8IN32;
539
540 /* 128-bit buffers. */
541 case V_0280A0_COLOR_32_32_32_FLOAT:
542 case V_0280A0_COLOR_32_32_32_32_FLOAT:
543 case V_0280A0_COLOR_32_32_32_32:
544 return ENDIAN_8IN32;
545 default:
546 return ENDIAN_NONE; /* Unsupported. */
547 }
548 } else {
549 return ENDIAN_NONE;
550 }
551 }
552
553 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
554 {
555 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
556 }
557
558 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
559 {
560 return r600_translate_colorformat(format) != ~0U &&
561 r600_translate_colorswap(format) != ~0U;
562 }
563
564 static bool r600_is_zs_format_supported(enum pipe_format format)
565 {
566 return r600_translate_dbformat(format) != ~0U;
567 }
568
569 boolean r600_is_format_supported(struct pipe_screen *screen,
570 enum pipe_format format,
571 enum pipe_texture_target target,
572 unsigned sample_count,
573 unsigned usage)
574 {
575 struct r600_screen *rscreen = (struct r600_screen*)screen;
576 unsigned retval = 0;
577
578 if (target >= PIPE_MAX_TEXTURE_TYPES) {
579 R600_ERR("r600: unsupported texture type %d\n", target);
580 return FALSE;
581 }
582
583 if (!util_format_is_supported(format, usage))
584 return FALSE;
585
586 if (sample_count > 1) {
587 if (rscreen->info.drm_minor < 22)
588 return FALSE;
589
590 /* R11G11B10 is broken on R6xx. */
591 if (rscreen->chip_class == R600 &&
592 format == PIPE_FORMAT_R11G11B10_FLOAT)
593 return FALSE;
594
595 switch (sample_count) {
596 case 2:
597 case 4:
598 case 8:
599 break;
600 default:
601 return FALSE;
602 }
603
604 /* require render-target support for multisample resources */
605 if (util_format_is_depth_or_stencil(format)) {
606 usage |= PIPE_BIND_DEPTH_STENCIL;
607 } else if (util_format_is_pure_integer(format)) {
608 return FALSE; /* no integer textures */
609 } else {
610 usage |= PIPE_BIND_RENDER_TARGET;
611 }
612 }
613
614 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
615 r600_is_sampler_format_supported(screen, format)) {
616 retval |= PIPE_BIND_SAMPLER_VIEW;
617 }
618
619 if ((usage & (PIPE_BIND_RENDER_TARGET |
620 PIPE_BIND_DISPLAY_TARGET |
621 PIPE_BIND_SCANOUT |
622 PIPE_BIND_SHARED)) &&
623 r600_is_colorbuffer_format_supported(format)) {
624 retval |= usage &
625 (PIPE_BIND_RENDER_TARGET |
626 PIPE_BIND_DISPLAY_TARGET |
627 PIPE_BIND_SCANOUT |
628 PIPE_BIND_SHARED);
629 }
630
631 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
632 r600_is_zs_format_supported(format)) {
633 retval |= PIPE_BIND_DEPTH_STENCIL;
634 }
635
636 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
637 r600_is_vertex_format_supported(format)) {
638 retval |= PIPE_BIND_VERTEX_BUFFER;
639 }
640
641 if (usage & PIPE_BIND_TRANSFER_READ)
642 retval |= PIPE_BIND_TRANSFER_READ;
643 if (usage & PIPE_BIND_TRANSFER_WRITE)
644 retval |= PIPE_BIND_TRANSFER_WRITE;
645
646 return retval == usage;
647 }
648
649 void r600_polygon_offset_update(struct r600_context *rctx)
650 {
651 struct r600_pipe_state state;
652
653 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
654 state.nregs = 0;
655 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
656 float offset_units = rctx->rasterizer->offset_units;
657 unsigned offset_db_fmt_cntl = 0, depth;
658
659 switch (rctx->framebuffer.zsbuf->format) {
660 case PIPE_FORMAT_Z24X8_UNORM:
661 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
662 depth = -24;
663 offset_units *= 2.0f;
664 break;
665 case PIPE_FORMAT_Z32_FLOAT:
666 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
667 depth = -23;
668 offset_units *= 1.0f;
669 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
670 break;
671 case PIPE_FORMAT_Z16_UNORM:
672 depth = -16;
673 offset_units *= 4.0f;
674 break;
675 default:
676 return;
677 }
678 /* XXX some of those reg can be computed with cso */
679 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
680 r600_pipe_state_add_reg(&state,
681 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
682 fui(rctx->rasterizer->offset_scale));
683 r600_pipe_state_add_reg(&state,
684 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
685 fui(offset_units));
686 r600_pipe_state_add_reg(&state,
687 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
688 fui(rctx->rasterizer->offset_scale));
689 r600_pipe_state_add_reg(&state,
690 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
691 fui(offset_units));
692 r600_pipe_state_add_reg(&state,
693 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
694 offset_db_fmt_cntl);
695 r600_context_pipe_state_set(rctx, &state);
696 }
697 }
698
699 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
700 const struct pipe_blend_state *state,
701 int mode)
702 {
703 struct r600_context *rctx = (struct r600_context *)ctx;
704 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
705 struct r600_pipe_state *rstate;
706 uint32_t color_control = 0, target_mask = 0;
707
708 if (blend == NULL) {
709 return NULL;
710 }
711 rstate = &blend->rstate;
712
713 rstate->id = R600_PIPE_STATE_BLEND;
714
715 /* R600 does not support per-MRT blends */
716 if (rctx->family > CHIP_R600)
717 color_control |= S_028808_PER_MRT_BLEND(1);
718
719 if (state->logicop_enable) {
720 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
721 } else {
722 color_control |= (0xcc << 16);
723 }
724 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
725 if (state->independent_blend_enable) {
726 for (int i = 0; i < 8; i++) {
727 if (state->rt[i].blend_enable) {
728 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
729 }
730 target_mask |= (state->rt[i].colormask << (4 * i));
731 }
732 } else {
733 for (int i = 0; i < 8; i++) {
734 if (state->rt[0].blend_enable) {
735 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
736 }
737 target_mask |= (state->rt[0].colormask << (4 * i));
738 }
739 }
740
741 if (target_mask)
742 color_control |= S_028808_SPECIAL_OP(mode);
743 else
744 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
745
746 blend->cb_target_mask = target_mask;
747 blend->cb_color_control = color_control;
748 /* only MRT0 has dual src blend */
749 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
750 for (int i = 0; i < 8; i++) {
751 /* state->rt entries > 0 only written if independent blending */
752 const int j = state->independent_blend_enable ? i : 0;
753
754 unsigned eqRGB = state->rt[j].rgb_func;
755 unsigned srcRGB = state->rt[j].rgb_src_factor;
756 unsigned dstRGB = state->rt[j].rgb_dst_factor;
757
758 unsigned eqA = state->rt[j].alpha_func;
759 unsigned srcA = state->rt[j].alpha_src_factor;
760 unsigned dstA = state->rt[j].alpha_dst_factor;
761 uint32_t bc = 0;
762
763 if (!state->rt[j].blend_enable)
764 continue;
765
766 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
767 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
768 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
769
770 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
771 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
772 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
773 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
774 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
775 }
776
777 /* R600 does not support per-MRT blends */
778 if (rctx->family > CHIP_R600)
779 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc);
780 if (i == 0)
781 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
782 }
783
784 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK,
785 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
786 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
787 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
788 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
789 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
790
791 blend->alpha_to_one = state->alpha_to_one;
792 return rstate;
793 }
794
795
796 static void *r600_create_blend_state(struct pipe_context *ctx,
797 const struct pipe_blend_state *state)
798 {
799 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
800 }
801
802 static void *r600_create_dsa_state(struct pipe_context *ctx,
803 const struct pipe_depth_stencil_alpha_state *state)
804 {
805 struct r600_context *rctx = (struct r600_context *)ctx;
806 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
807 unsigned db_depth_control, alpha_test_control, alpha_ref;
808 struct r600_pipe_state *rstate;
809
810 if (dsa == NULL) {
811 return NULL;
812 }
813
814 dsa->valuemask[0] = state->stencil[0].valuemask;
815 dsa->valuemask[1] = state->stencil[1].valuemask;
816 dsa->writemask[0] = state->stencil[0].writemask;
817 dsa->writemask[1] = state->stencil[1].writemask;
818
819 rstate = &dsa->rstate;
820
821 rstate->id = R600_PIPE_STATE_DSA;
822 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
823 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
824 S_028800_ZFUNC(state->depth.func);
825
826 /* stencil */
827 if (state->stencil[0].enabled) {
828 db_depth_control |= S_028800_STENCIL_ENABLE(1);
829 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
830 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
831 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
832 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
833
834 if (state->stencil[1].enabled) {
835 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
836 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
837 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
838 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
839 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
840 }
841 }
842
843 /* alpha */
844 alpha_test_control = 0;
845 alpha_ref = 0;
846 if (state->alpha.enabled) {
847 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
848 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
849 alpha_ref = fui(state->alpha.ref_value);
850 }
851 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
852 dsa->alpha_ref = alpha_ref;
853
854 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
855 return rstate;
856 }
857
858 static void *r600_create_rs_state(struct pipe_context *ctx,
859 const struct pipe_rasterizer_state *state)
860 {
861 struct r600_context *rctx = (struct r600_context *)ctx;
862 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
863 struct r600_pipe_state *rstate;
864 unsigned tmp;
865 unsigned prov_vtx = 1, polygon_dual_mode;
866 unsigned sc_mode_cntl;
867 float psize_min, psize_max;
868
869 if (rs == NULL) {
870 return NULL;
871 }
872
873 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
874 state->fill_back != PIPE_POLYGON_MODE_FILL);
875
876 if (state->flatshade_first)
877 prov_vtx = 0;
878
879 rstate = &rs->rstate;
880 rs->flatshade = state->flatshade;
881 rs->sprite_coord_enable = state->sprite_coord_enable;
882 rs->two_side = state->light_twoside;
883 rs->clip_plane_enable = state->clip_plane_enable;
884 rs->pa_sc_line_stipple = state->line_stipple_enable ?
885 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
886 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
887 rs->pa_cl_clip_cntl =
888 S_028810_PS_UCP_MODE(3) |
889 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
890 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
891 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
892 rs->multisample_enable = state->multisample;
893
894 /* offset */
895 rs->offset_units = state->offset_units;
896 rs->offset_scale = state->offset_scale * 12.0f;
897
898 rstate->id = R600_PIPE_STATE_RASTERIZER;
899 tmp = S_0286D4_FLAT_SHADE_ENA(1);
900 if (state->sprite_coord_enable) {
901 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
902 S_0286D4_PNT_SPRITE_OVRD_X(2) |
903 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
904 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
905 S_0286D4_PNT_SPRITE_OVRD_W(1);
906 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
907 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
908 }
909 }
910 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
911
912 /* point size 12.4 fixed point */
913 tmp = r600_pack_float_12p4(state->point_size/2);
914 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
915
916 if (state->point_size_per_vertex) {
917 psize_min = util_get_min_point_size(state);
918 psize_max = 8192;
919 } else {
920 /* Force the point size to be as if the vertex output was disabled. */
921 psize_min = state->point_size;
922 psize_max = state->point_size;
923 }
924 /* Divide by two, because 0.5 = 1 pixel. */
925 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
926 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
927 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
928
929 tmp = r600_pack_float_12p4(state->line_width/2);
930 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
931
932 if (rctx->chip_class >= R700) {
933 sc_mode_cntl =
934 S_028A4C_MSAA_ENABLE(state->multisample) |
935 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
936 S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
937 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
938 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
939 } else {
940 sc_mode_cntl =
941 S_028A4C_MSAA_ENABLE(state->multisample) |
942 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
943 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
944 rs->scissor_enable = state->scissor;
945 }
946 sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
947
948 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
949
950 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
951 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
952 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
953
954 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
955 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
956 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
957 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
958 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
959 S_028814_FACE(!state->front_ccw) |
960 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
961 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
962 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
963 S_028814_POLY_MODE(polygon_dual_mode) |
964 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
965 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
966 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
967 return rstate;
968 }
969
970 static void *r600_create_sampler_state(struct pipe_context *ctx,
971 const struct pipe_sampler_state *state)
972 {
973 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
974 union util_color uc;
975 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
976
977 if (ss == NULL) {
978 return NULL;
979 }
980
981 ss->seamless_cube_map = state->seamless_cube_map;
982 ss->border_color_use = false;
983 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
984 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
985 ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
986 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
987 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
988 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
989 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
990 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
991 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
992 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
993 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
994 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
995 ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
996 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
997 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
998 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
999 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
1000 if (uc.ui) {
1001 ss->border_color_use = true;
1002 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
1003 ss->border_color[0] = fui(state->border_color.f[0]);
1004 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
1005 ss->border_color[1] = fui(state->border_color.f[1]);
1006 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
1007 ss->border_color[2] = fui(state->border_color.f[2]);
1008 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
1009 ss->border_color[3] = fui(state->border_color.f[3]);
1010 }
1011 return ss;
1012 }
1013
1014 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1015 struct pipe_resource *texture,
1016 const struct pipe_sampler_view *state)
1017 {
1018 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1019 struct r600_texture *tmp = (struct r600_texture*)texture;
1020 unsigned format, endian;
1021 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1022 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1023 unsigned width, height, depth, offset_level, last_level;
1024
1025 if (view == NULL)
1026 return NULL;
1027
1028 /* initialize base object */
1029 view->base = *state;
1030 view->base.texture = NULL;
1031 pipe_reference(NULL, &texture->reference);
1032 view->base.texture = texture;
1033 view->base.reference.count = 1;
1034 view->base.context = ctx;
1035
1036 swizzle[0] = state->swizzle_r;
1037 swizzle[1] = state->swizzle_g;
1038 swizzle[2] = state->swizzle_b;
1039 swizzle[3] = state->swizzle_a;
1040
1041 format = r600_translate_texformat(ctx->screen, state->format,
1042 swizzle,
1043 &word4, &yuv_format);
1044 assert(format != ~0);
1045 if (format == ~0) {
1046 FREE(view);
1047 return NULL;
1048 }
1049
1050 if (tmp->is_depth && !tmp->is_flushing_texture) {
1051 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1052 FREE(view);
1053 return NULL;
1054 }
1055 tmp = tmp->flushed_depth_texture;
1056 }
1057
1058 endian = r600_colorformat_endian_swap(format);
1059
1060 offset_level = state->u.tex.first_level;
1061 last_level = state->u.tex.last_level - offset_level;
1062 width = tmp->surface.level[offset_level].npix_x;
1063 height = tmp->surface.level[offset_level].npix_y;
1064 depth = tmp->surface.level[offset_level].npix_z;
1065 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1066 tile_type = tmp->tile_type;
1067
1068 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1069 height = 1;
1070 depth = texture->array_size;
1071 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1072 depth = texture->array_size;
1073 }
1074 switch (tmp->surface.level[offset_level].mode) {
1075 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1076 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1077 break;
1078 case RADEON_SURF_MODE_1D:
1079 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1080 break;
1081 case RADEON_SURF_MODE_2D:
1082 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1083 break;
1084 case RADEON_SURF_MODE_LINEAR:
1085 default:
1086 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1087 break;
1088 }
1089
1090 view->tex_resource = &tmp->resource;
1091 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1092 S_038000_TILE_MODE(array_mode) |
1093 S_038000_TILE_TYPE(tile_type) |
1094 S_038000_PITCH((pitch / 8) - 1) |
1095 S_038000_TEX_WIDTH(width - 1));
1096 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1097 S_038004_TEX_DEPTH(depth - 1) |
1098 S_038004_DATA_FORMAT(format));
1099 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1100 if (offset_level >= tmp->surface.last_level) {
1101 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1102 } else {
1103 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1104 }
1105 view->tex_resource_words[4] = (word4 |
1106 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1107 S_038010_REQUEST_SIZE(1) |
1108 S_038010_ENDIAN_SWAP(endian) |
1109 S_038010_BASE_LEVEL(0));
1110 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1111 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1112 if (texture->nr_samples > 1) {
1113 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1114 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1115 } else {
1116 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
1117 }
1118 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1119 S_038018_MAX_ANISO(4 /* max 16 samples */));
1120 return &view->base;
1121 }
1122
1123 static void r600_set_clip_state(struct pipe_context *ctx,
1124 const struct pipe_clip_state *state)
1125 {
1126 struct r600_context *rctx = (struct r600_context *)ctx;
1127 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1128 struct pipe_constant_buffer cb;
1129
1130 if (rstate == NULL)
1131 return;
1132
1133 rctx->clip = *state;
1134 rstate->id = R600_PIPE_STATE_CLIP;
1135 for (int i = 0; i < 6; i++) {
1136 r600_pipe_state_add_reg(rstate,
1137 R_028E20_PA_CL_UCP0_X + i * 16,
1138 fui(state->ucp[i][0]));
1139 r600_pipe_state_add_reg(rstate,
1140 R_028E24_PA_CL_UCP0_Y + i * 16,
1141 fui(state->ucp[i][1]) );
1142 r600_pipe_state_add_reg(rstate,
1143 R_028E28_PA_CL_UCP0_Z + i * 16,
1144 fui(state->ucp[i][2]));
1145 r600_pipe_state_add_reg(rstate,
1146 R_028E2C_PA_CL_UCP0_W + i * 16,
1147 fui(state->ucp[i][3]));
1148 }
1149
1150 free(rctx->states[R600_PIPE_STATE_CLIP]);
1151 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1152 r600_context_pipe_state_set(rctx, rstate);
1153
1154 cb.buffer = NULL;
1155 cb.user_buffer = state->ucp;
1156 cb.buffer_offset = 0;
1157 cb.buffer_size = 4*4*8;
1158 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1159 pipe_resource_reference(&cb.buffer, NULL);
1160 }
1161
1162 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1163 const struct pipe_poly_stipple *state)
1164 {
1165 }
1166
1167 void r600_set_scissor_state(struct r600_context *rctx,
1168 const struct pipe_scissor_state *state)
1169 {
1170 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1171 uint32_t tl, br;
1172
1173 if (rstate == NULL)
1174 return;
1175
1176 rstate->id = R600_PIPE_STATE_SCISSOR;
1177 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1178 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1179 r600_pipe_state_add_reg(rstate,
1180 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1181 r600_pipe_state_add_reg(rstate,
1182 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1183
1184 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1185 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1186 r600_context_pipe_state_set(rctx, rstate);
1187 }
1188
1189 static void r600_pipe_set_scissor_state(struct pipe_context *ctx,
1190 const struct pipe_scissor_state *state)
1191 {
1192 struct r600_context *rctx = (struct r600_context *)ctx;
1193
1194 if (rctx->chip_class == R600) {
1195 rctx->scissor_state = *state;
1196
1197 if (!rctx->scissor_enable)
1198 return;
1199 }
1200
1201 r600_set_scissor_state(rctx, state);
1202 }
1203
1204 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
1205 unsigned size, unsigned alignment)
1206 {
1207 struct pipe_resource buffer;
1208
1209 memset(&buffer, 0, sizeof buffer);
1210 buffer.target = PIPE_BUFFER;
1211 buffer.format = PIPE_FORMAT_R8_UNORM;
1212 buffer.bind = PIPE_BIND_CUSTOM;
1213 buffer.usage = PIPE_USAGE_STATIC;
1214 buffer.flags = 0;
1215 buffer.width0 = size;
1216 buffer.height0 = 1;
1217 buffer.depth0 = 1;
1218 buffer.array_size = 1;
1219
1220 return (struct r600_resource*)
1221 r600_buffer_create(&rscreen->screen, &buffer, alignment);
1222 }
1223
1224 static void r600_init_color_surface(struct r600_context *rctx,
1225 struct r600_surface *surf,
1226 bool force_cmask_fmask)
1227 {
1228 struct r600_screen *rscreen = rctx->screen;
1229 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1230 unsigned level = surf->base.u.tex.level;
1231 unsigned pitch, slice;
1232 unsigned color_info;
1233 unsigned format, swap, ntype, endian;
1234 unsigned offset;
1235 const struct util_format_description *desc;
1236 int i;
1237 bool blend_bypass = 0, blend_clamp = 1;
1238
1239 if (rtex->is_depth && !rtex->is_flushing_texture) {
1240 r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL);
1241 rtex = rtex->flushed_depth_texture;
1242 assert(rtex);
1243 }
1244
1245 offset = rtex->surface.level[level].offset;
1246 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1247 offset += rtex->surface.level[level].slice_size *
1248 surf->base.u.tex.first_layer;
1249 }
1250 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1251 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1252 if (slice) {
1253 slice = slice - 1;
1254 }
1255 color_info = 0;
1256 switch (rtex->surface.level[level].mode) {
1257 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1258 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1259 break;
1260 case RADEON_SURF_MODE_1D:
1261 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1262 break;
1263 case RADEON_SURF_MODE_2D:
1264 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1265 break;
1266 case RADEON_SURF_MODE_LINEAR:
1267 default:
1268 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1269 break;
1270 }
1271
1272 desc = util_format_description(surf->base.format);
1273
1274 for (i = 0; i < 4; i++) {
1275 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1276 break;
1277 }
1278 }
1279
1280 ntype = V_0280A0_NUMBER_UNORM;
1281 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1282 ntype = V_0280A0_NUMBER_SRGB;
1283 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1284 if (desc->channel[i].normalized)
1285 ntype = V_0280A0_NUMBER_SNORM;
1286 else if (desc->channel[i].pure_integer)
1287 ntype = V_0280A0_NUMBER_SINT;
1288 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1289 if (desc->channel[i].normalized)
1290 ntype = V_0280A0_NUMBER_UNORM;
1291 else if (desc->channel[i].pure_integer)
1292 ntype = V_0280A0_NUMBER_UINT;
1293 }
1294
1295 format = r600_translate_colorformat(surf->base.format);
1296 assert(format != ~0);
1297
1298 swap = r600_translate_colorswap(surf->base.format);
1299 assert(swap != ~0);
1300
1301 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1302 endian = ENDIAN_NONE;
1303 } else {
1304 endian = r600_colorformat_endian_swap(format);
1305 }
1306
1307 /* set blend bypass according to docs if SINT/UINT or
1308 8/24 COLOR variants */
1309 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1310 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1311 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1312 blend_clamp = 0;
1313 blend_bypass = 1;
1314 }
1315
1316 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1317
1318 color_info |= S_0280A0_FORMAT(format) |
1319 S_0280A0_COMP_SWAP(swap) |
1320 S_0280A0_BLEND_BYPASS(blend_bypass) |
1321 S_0280A0_BLEND_CLAMP(blend_clamp) |
1322 S_0280A0_NUMBER_TYPE(ntype) |
1323 S_0280A0_ENDIAN(endian);
1324
1325 /* EXPORT_NORM is an optimzation that can be enabled for better
1326 * performance in certain cases
1327 */
1328 if (rctx->chip_class == R600) {
1329 /* EXPORT_NORM can be enabled if:
1330 * - 11-bit or smaller UNORM/SNORM/SRGB
1331 * - BLEND_CLAMP is enabled
1332 * - BLEND_FLOAT32 is disabled
1333 */
1334 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1335 (desc->channel[i].size < 12 &&
1336 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1337 ntype != V_0280A0_NUMBER_UINT &&
1338 ntype != V_0280A0_NUMBER_SINT) &&
1339 G_0280A0_BLEND_CLAMP(color_info) &&
1340 !G_0280A0_BLEND_FLOAT32(color_info)) {
1341 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1342 surf->export_16bpc = true;
1343 }
1344 } else {
1345 /* EXPORT_NORM can be enabled if:
1346 * - 11-bit or smaller UNORM/SNORM/SRGB
1347 * - 16-bit or smaller FLOAT
1348 */
1349 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1350 ((desc->channel[i].size < 12 &&
1351 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1352 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1353 (desc->channel[i].size < 17 &&
1354 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1355 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1356 surf->export_16bpc = true;
1357 }
1358 }
1359
1360 /* These might not always be initialized to zero. */
1361 surf->cb_color_base = offset >> 8;
1362 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1363 S_028060_SLICE_TILE_MAX(slice);
1364 surf->cb_color_fmask = surf->cb_color_base;
1365 surf->cb_color_cmask = surf->cb_color_base;
1366 surf->cb_color_mask = 0;
1367
1368 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1369 &rtex->resource.b.b);
1370 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1371 &rtex->resource.b.b);
1372
1373 if (rtex->cmask_size) {
1374 surf->cb_color_cmask = rtex->cmask_offset >> 8;
1375 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask_slice_tile_max);
1376
1377 if (rtex->fmask_size) {
1378 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1379 surf->cb_color_fmask = rtex->fmask_offset >> 8;
1380 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(slice);
1381 } else { /* cmask only */
1382 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1383 }
1384 } else if (force_cmask_fmask) {
1385 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1386 *
1387 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1388 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1389 * because it's not an MSAA buffer.
1390 */
1391 struct r600_cmask_info cmask;
1392 struct r600_fmask_info fmask;
1393
1394 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
1395 r600_texture_get_fmask_info(rscreen, rtex, 8, &fmask);
1396
1397 /* CMASK. */
1398 if (!rctx->dummy_cmask ||
1399 rctx->dummy_cmask->buf->size < cmask.size ||
1400 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1401 struct pipe_transfer *transfer;
1402 void *ptr;
1403
1404 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1405 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1406
1407 /* Set the contents to 0xCC. */
1408 ptr = pipe_buffer_map(&rctx->context, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1409 memset(ptr, 0xCC, cmask.size);
1410 pipe_buffer_unmap(&rctx->context, transfer);
1411 }
1412 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1413 &rctx->dummy_cmask->b.b);
1414
1415 /* FMASK. */
1416 if (!rctx->dummy_fmask ||
1417 rctx->dummy_fmask->buf->size < fmask.size ||
1418 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1419 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1420 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1421
1422 }
1423 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1424 &rctx->dummy_fmask->b.b);
1425
1426 /* Init the registers. */
1427 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1428 surf->cb_color_cmask = 0;
1429 surf->cb_color_fmask = 0;
1430 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1431 S_028100_FMASK_TILE_MAX(slice);
1432 }
1433
1434 surf->cb_color_info = color_info;
1435
1436 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1437 surf->cb_color_view = 0;
1438 } else {
1439 surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1440 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1441 }
1442
1443 surf->color_initialized = true;
1444 }
1445
1446 static void r600_init_depth_surface(struct r600_context *rctx,
1447 struct r600_surface *surf)
1448 {
1449 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1450 unsigned level, pitch, slice, format, offset, array_mode;
1451
1452 level = surf->base.u.tex.level;
1453 offset = rtex->surface.level[level].offset;
1454 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1455 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1456 if (slice) {
1457 slice = slice - 1;
1458 }
1459 switch (rtex->surface.level[level].mode) {
1460 case RADEON_SURF_MODE_2D:
1461 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1462 break;
1463 case RADEON_SURF_MODE_1D:
1464 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1465 case RADEON_SURF_MODE_LINEAR:
1466 default:
1467 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1468 break;
1469 }
1470
1471 format = r600_translate_dbformat(surf->base.format);
1472 assert(format != ~0);
1473
1474 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1475 surf->db_depth_base = offset >> 8;
1476 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1477 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1478 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1479 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1480
1481 surf->depth_initialized = true;
1482 }
1483
1484 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1485 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1486 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1487 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1488 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1489
1490 static uint32_t r600_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1491 {
1492 static uint32_t sample_locs_2x[] = {
1493 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1494 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1495 };
1496 static unsigned max_dist_2x = 4;
1497 static uint32_t sample_locs_4x[] = {
1498 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1499 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1500 };
1501 static unsigned max_dist_4x = 6;
1502 static uint32_t sample_locs_8x[] = {
1503 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1504 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1505 };
1506 static unsigned max_dist_8x = 8;
1507 struct r600_context *rctx = (struct r600_context *)ctx;
1508
1509 if (rctx->family == CHIP_R600) {
1510 switch (nsample) {
1511 case 0:
1512 case 1:
1513 return 0;
1514 case 2:
1515 r600_pipe_state_add_reg(rstate, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1516 return max_dist_2x;
1517 case 4:
1518 r600_pipe_state_add_reg(rstate, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1519 return max_dist_4x;
1520 case 8:
1521 r600_pipe_state_add_reg(rstate, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, sample_locs_8x[0]);
1522 r600_pipe_state_add_reg(rstate, R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1, sample_locs_8x[1]);
1523 return max_dist_8x;
1524 }
1525 } else {
1526 switch (nsample) {
1527 case 0:
1528 case 1:
1529 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0);
1530 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, 0);
1531 return 0;
1532 case 2:
1533 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_2x[0]);
1534 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_2x[1]);
1535 return max_dist_2x;
1536 case 4:
1537 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_4x[0]);
1538 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_4x[1]);
1539 return max_dist_4x;
1540 case 8:
1541 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_8x[0]);
1542 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_8x[1]);
1543 return max_dist_8x;
1544 }
1545 }
1546 R600_ERR("Invalid nr_samples %i\n", nsample);
1547 return 0;
1548 }
1549
1550 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1551 const struct pipe_framebuffer_state *state)
1552 {
1553 struct r600_context *rctx = (struct r600_context *)ctx;
1554 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1555 struct r600_surface *surf;
1556 struct r600_resource *res;
1557 struct r600_texture *rtex;
1558 uint32_t tl, br, i, nr_samples, max_dist;
1559 bool is_resolve = state->nr_cbufs == 2 &&
1560 state->cbufs[0]->texture->nr_samples > 1 &&
1561 state->cbufs[1]->texture->nr_samples <= 1;
1562 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1563 bool cb1_force_cmask_fmask = rctx->chip_class == R600 && is_resolve;
1564
1565 if (rstate == NULL)
1566 return;
1567
1568 if (rctx->framebuffer.nr_cbufs) {
1569 rctx->flags |= R600_CONTEXT_CB_FLUSH;
1570 }
1571 if (rctx->framebuffer.zsbuf) {
1572 rctx->flags |= R600_CONTEXT_DB_FLUSH;
1573 }
1574 /* R6xx errata */
1575 if (rctx->chip_class == R600) {
1576 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
1577 }
1578
1579 /* unreference old buffer and reference new one */
1580 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1581
1582 util_copy_framebuffer_state(&rctx->framebuffer, state);
1583
1584
1585 /* Colorbuffers. */
1586 rctx->export_16bpc = true;
1587 rctx->nr_cbufs = state->nr_cbufs;
1588 rctx->cb0_is_integer = state->nr_cbufs &&
1589 util_format_is_pure_integer(state->cbufs[0]->format);
1590 rctx->compressed_cb_mask = 0;
1591
1592 for (i = 0; i < state->nr_cbufs; i++) {
1593 bool force_cmask_fmask = cb1_force_cmask_fmask && i == 1;
1594 surf = (struct r600_surface*)state->cbufs[i];
1595 res = (struct r600_resource*)surf->base.texture;
1596 rtex = (struct r600_texture*)res;
1597
1598 if (!surf->color_initialized || force_cmask_fmask) {
1599 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1600 if (force_cmask_fmask) {
1601 /* re-initialize later without compression */
1602 surf->color_initialized = false;
1603 }
1604 }
1605
1606 if (!surf->export_16bpc) {
1607 rctx->export_16bpc = false;
1608 }
1609
1610 r600_pipe_state_add_reg_bo(rstate, R_028040_CB_COLOR0_BASE + i * 4,
1611 surf->cb_color_base, res, RADEON_USAGE_READWRITE);
1612 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + i * 4,
1613 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1614 r600_pipe_state_add_reg(rstate, R_028060_CB_COLOR0_SIZE + i * 4,
1615 surf->cb_color_size);
1616 r600_pipe_state_add_reg(rstate, R_028080_CB_COLOR0_VIEW + i * 4,
1617 surf->cb_color_view);
1618 r600_pipe_state_add_reg_bo(rstate, R_0280E0_CB_COLOR0_FRAG + i * 4,
1619 surf->cb_color_fmask, surf->cb_buffer_fmask,
1620 RADEON_USAGE_READWRITE);
1621 r600_pipe_state_add_reg_bo(rstate, R_0280C0_CB_COLOR0_TILE + i * 4,
1622 surf->cb_color_cmask, surf->cb_buffer_cmask,
1623 RADEON_USAGE_READWRITE);
1624 r600_pipe_state_add_reg(rstate, R_028100_CB_COLOR0_MASK + i * 4,
1625 surf->cb_color_mask);
1626
1627 if (rtex->fmask_size && rtex->cmask_size) {
1628 rctx->compressed_cb_mask |= 1 << i;
1629 }
1630 }
1631 /* set CB_COLOR1_INFO for possible dual-src blending */
1632 if (i == 1) {
1633 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + 1 * 4,
1634 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1635 i++;
1636 }
1637 for (; i < 8 ; i++) {
1638 r600_pipe_state_add_reg(rstate, R_0280A0_CB_COLOR0_INFO + i * 4, 0);
1639 }
1640
1641 /* Update alpha-test state dependencies.
1642 * Alpha-test is done on the first colorbuffer only. */
1643 if (state->nr_cbufs) {
1644 surf = (struct r600_surface*)state->cbufs[0];
1645 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1646 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1647 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1648 }
1649 }
1650
1651 /* ZS buffer. */
1652 if (state->zsbuf) {
1653 surf = (struct r600_surface*)state->zsbuf;
1654 res = (struct r600_resource*)surf->base.texture;
1655
1656 if (!surf->depth_initialized) {
1657 r600_init_depth_surface(rctx, surf);
1658 }
1659
1660 r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE, surf->db_depth_base,
1661 res, RADEON_USAGE_READWRITE);
1662 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, surf->db_depth_size);
1663 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, surf->db_depth_view);
1664 r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO, surf->db_depth_info,
1665 res, RADEON_USAGE_READWRITE);
1666 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1667 }
1668
1669 /* Framebuffer dimensions. */
1670 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1671 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1672
1673 r600_pipe_state_add_reg(rstate,
1674 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1675 r600_pipe_state_add_reg(rstate,
1676 R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1677
1678 /* If we're doing MSAA resolve... */
1679 if (is_resolve) {
1680 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL, 1);
1681 } else {
1682 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1683 * will assure that the alpha-test will work even if there is
1684 * no colorbuffer bound. */
1685 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1686 (1ull << MAX2(state->nr_cbufs, 1)) - 1);
1687 }
1688
1689 /* Multisampling */
1690 if (state->nr_cbufs)
1691 nr_samples = state->cbufs[0]->texture->nr_samples;
1692 else if (state->zsbuf)
1693 nr_samples = state->zsbuf->texture->nr_samples;
1694 else
1695 nr_samples = 0;
1696
1697 max_dist = r600_set_ms_pos(ctx, rstate, nr_samples);
1698
1699 if (nr_samples > 1) {
1700 unsigned log_samples = util_logbase2(nr_samples);
1701
1702 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL,
1703 S_028C00_LAST_PIXEL(1) |
1704 S_028C00_EXPAND_LINE_WIDTH(1));
1705 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1706 S_028C04_MSAA_NUM_SAMPLES(log_samples) |
1707 S_028C04_MAX_SAMPLE_DIST(max_dist));
1708 } else {
1709 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1710 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 0);
1711 }
1712
1713 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1714 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1715 r600_context_pipe_state_set(rctx, rstate);
1716
1717 if (state->zsbuf) {
1718 r600_polygon_offset_update(rctx);
1719 }
1720
1721 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1722 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1723 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1724 }
1725
1726 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1727 rctx->alphatest_state.bypass = false;
1728 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1729 }
1730 }
1731
1732 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1733 {
1734 struct radeon_winsys_cs *cs = rctx->cs;
1735 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1736
1737 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1738 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1739 if (rctx->chip_class == R600) {
1740 r600_write_value(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1741 r600_write_value(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1742 } else {
1743 r600_write_value(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1744 r600_write_value(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1745 }
1746 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1747 } else {
1748 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1749 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1750 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1751
1752 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1753 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1754 /* Always enable the first color output to make sure alpha-test works even without one. */
1755 r600_write_value(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1756 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1757 a->cb_color_control |
1758 S_028808_MULTIWRITE_ENABLE(multiwrite));
1759 }
1760 }
1761
1762 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1763 {
1764 struct radeon_winsys_cs *cs = rctx->cs;
1765 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1766 unsigned db_render_control = 0;
1767 unsigned db_render_override =
1768 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1769 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1770 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1771
1772 if (a->occlusion_query_enabled) {
1773 if (rctx->chip_class >= R700) {
1774 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1775 }
1776 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1777 }
1778 if (a->flush_depthstencil_through_cb) {
1779 assert(a->copy_depth || a->copy_stencil);
1780
1781 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1782 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1783 S_028D0C_COPY_CENTROID(1) |
1784 S_028D0C_COPY_SAMPLE(a->copy_sample);
1785 }
1786
1787 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1788 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1789 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1790 }
1791
1792 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1793 {
1794 struct radeon_winsys_cs *cs = rctx->cs;
1795 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1796
1797 while (dirty_mask) {
1798 struct pipe_vertex_buffer *vb;
1799 struct r600_resource *rbuffer;
1800 unsigned offset;
1801 unsigned buffer_index = u_bit_scan(&dirty_mask);
1802
1803 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1804 rbuffer = (struct r600_resource*)vb->buffer;
1805 assert(rbuffer);
1806
1807 offset = vb->buffer_offset;
1808
1809 /* fetch resources start at index 320 */
1810 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1811 r600_write_value(cs, (320 + buffer_index) * 7);
1812 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1813 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1814 r600_write_value(cs, /* RESOURCEi_WORD2 */
1815 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1816 S_038008_STRIDE(vb->stride));
1817 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1818 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1819 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1820 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1821
1822 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1823 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1824 }
1825 }
1826
1827 static void r600_emit_constant_buffers(struct r600_context *rctx,
1828 struct r600_constbuf_state *state,
1829 unsigned buffer_id_base,
1830 unsigned reg_alu_constbuf_size,
1831 unsigned reg_alu_const_cache)
1832 {
1833 struct radeon_winsys_cs *cs = rctx->cs;
1834 uint32_t dirty_mask = state->dirty_mask;
1835
1836 while (dirty_mask) {
1837 struct pipe_constant_buffer *cb;
1838 struct r600_resource *rbuffer;
1839 unsigned offset;
1840 unsigned buffer_index = ffs(dirty_mask) - 1;
1841
1842 cb = &state->cb[buffer_index];
1843 rbuffer = (struct r600_resource*)cb->buffer;
1844 assert(rbuffer);
1845
1846 offset = cb->buffer_offset;
1847
1848 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1849 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1850 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1851
1852 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1853 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1854
1855 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1856 r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1857 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1858 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1859 r600_write_value(cs, /* RESOURCEi_WORD2 */
1860 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1861 S_038008_STRIDE(16));
1862 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1863 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1864 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1865 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1866
1867 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1868 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1869
1870 dirty_mask &= ~(1 << buffer_index);
1871 }
1872 state->dirty_mask = 0;
1873 }
1874
1875 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1876 {
1877 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
1878 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1879 R_028980_ALU_CONST_CACHE_VS_0);
1880 }
1881
1882 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1883 {
1884 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
1885 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1886 R_0289C0_ALU_CONST_CACHE_GS_0);
1887 }
1888
1889 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1890 {
1891 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
1892 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1893 R_028940_ALU_CONST_CACHE_PS_0);
1894 }
1895
1896 static void r600_emit_sampler_views(struct r600_context *rctx,
1897 struct r600_samplerview_state *state,
1898 unsigned resource_id_base)
1899 {
1900 struct radeon_winsys_cs *cs = rctx->cs;
1901 uint32_t dirty_mask = state->dirty_mask;
1902
1903 while (dirty_mask) {
1904 struct r600_pipe_sampler_view *rview;
1905 unsigned resource_index = u_bit_scan(&dirty_mask);
1906 unsigned reloc;
1907
1908 rview = state->views[resource_index];
1909 assert(rview);
1910
1911 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1912 r600_write_value(cs, (resource_id_base + resource_index) * 7);
1913 r600_write_array(cs, 7, rview->tex_resource_words);
1914
1915 /* XXX The kernel needs two relocations. This is stupid. */
1916 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1917 RADEON_USAGE_READ);
1918 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1919 r600_write_value(cs, reloc);
1920 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1921 r600_write_value(cs, reloc);
1922 }
1923 state->dirty_mask = 0;
1924 }
1925
1926 /* Resource IDs:
1927 * PS: 0 .. +160
1928 * VS: 160 .. +160
1929 * FS: 320 .. +16
1930 * GS: 336 .. +160
1931 */
1932
1933 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1934 {
1935 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
1936 }
1937
1938 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1939 {
1940 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
1941 }
1942
1943 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1944 {
1945 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
1946 }
1947
1948 static void r600_emit_sampler_states(struct r600_context *rctx,
1949 struct r600_textures_info *texinfo,
1950 unsigned resource_id_base,
1951 unsigned border_color_reg)
1952 {
1953 struct radeon_winsys_cs *cs = rctx->cs;
1954 uint32_t dirty_mask = texinfo->states.dirty_mask;
1955
1956 while (dirty_mask) {
1957 struct r600_pipe_sampler_state *rstate;
1958 struct r600_pipe_sampler_view *rview;
1959 unsigned i = u_bit_scan(&dirty_mask);
1960
1961 rstate = texinfo->states.states[i];
1962 assert(rstate);
1963 rview = texinfo->views.views[i];
1964
1965 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1966 * filtering between layers.
1967 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1968 */
1969 if (rview) {
1970 enum pipe_texture_target target = rview->base.texture->target;
1971 if (target == PIPE_TEXTURE_1D_ARRAY ||
1972 target == PIPE_TEXTURE_2D_ARRAY) {
1973 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1974 texinfo->is_array_sampler[i] = true;
1975 } else {
1976 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1977 texinfo->is_array_sampler[i] = false;
1978 }
1979 }
1980
1981 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1982 r600_write_value(cs, (resource_id_base + i) * 3);
1983 r600_write_array(cs, 3, rstate->tex_sampler_words);
1984
1985 if (rstate->border_color_use) {
1986 unsigned offset;
1987
1988 offset = border_color_reg;
1989 offset += i * 16;
1990 r600_write_config_reg_seq(cs, offset, 4);
1991 r600_write_array(cs, 4, rstate->border_color);
1992 }
1993 }
1994 texinfo->states.dirty_mask = 0;
1995 }
1996
1997 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1998 {
1999 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
2000 }
2001
2002 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2003 {
2004 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
2005 }
2006
2007 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2008 {
2009 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
2010 }
2011
2012 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
2013 {
2014 struct radeon_winsys_cs *cs = rctx->cs;
2015 unsigned tmp;
2016
2017 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
2018 S_009508_SYNC_GRADIENT(1) |
2019 S_009508_SYNC_WALKER(1) |
2020 S_009508_SYNC_ALIGNER(1);
2021 if (!rctx->seamless_cube_map.enabled) {
2022 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
2023 }
2024 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
2025 }
2026
2027 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2028 {
2029 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2030 uint8_t mask = s->sample_mask;
2031
2032 r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
2033 mask | (mask << 8) | (mask << 16) | (mask << 24));
2034 }
2035
2036 void r600_init_state_functions(struct r600_context *rctx)
2037 {
2038 unsigned id = 4;
2039
2040 /* !!!
2041 * To avoid GPU lockup registers must be emited in a specific order
2042 * (no kidding ...). The order below is important and have been
2043 * partialy infered from analyzing fglrx command stream.
2044 *
2045 * Don't reorder atom without carefully checking the effect (GPU lockup
2046 * or piglit regression).
2047 * !!!
2048 */
2049
2050 /* shader const */
2051 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
2052 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
2053 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
2054
2055 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2056 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2057 */
2058 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
2059 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
2060 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
2061 /* resource */
2062 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
2063 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
2064 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
2065 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
2066
2067 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
2068 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
2069 rctx->sample_mask.sample_mask = ~0;
2070
2071 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 0);
2072 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2073 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 4);
2074 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
2075
2076 rctx->context.create_blend_state = r600_create_blend_state;
2077 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
2078 rctx->context.create_rasterizer_state = r600_create_rs_state;
2079 rctx->context.create_sampler_state = r600_create_sampler_state;
2080 rctx->context.create_sampler_view = r600_create_sampler_view;
2081 rctx->context.set_clip_state = r600_set_clip_state;
2082 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
2083 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
2084 rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
2085 }
2086
2087 /* Adjust GPR allocation on R6xx/R7xx */
2088 void r600_adjust_gprs(struct r600_context *rctx)
2089 {
2090 struct r600_pipe_state rstate;
2091 unsigned num_ps_gprs = rctx->default_ps_gprs;
2092 unsigned num_vs_gprs = rctx->default_vs_gprs;
2093 unsigned tmp;
2094 int diff;
2095
2096 if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs) {
2097 diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
2098 num_vs_gprs -= diff;
2099 num_ps_gprs += diff;
2100 }
2101
2102 if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
2103 {
2104 diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
2105 num_ps_gprs -= diff;
2106 num_vs_gprs += diff;
2107 }
2108
2109 tmp = 0;
2110 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2111 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2112 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
2113 rstate.nregs = 0;
2114 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
2115
2116 r600_context_pipe_state_set(rctx, &rstate);
2117 }
2118
2119 void r600_init_atom_start_cs(struct r600_context *rctx)
2120 {
2121 int ps_prio;
2122 int vs_prio;
2123 int gs_prio;
2124 int es_prio;
2125 int num_ps_gprs;
2126 int num_vs_gprs;
2127 int num_gs_gprs;
2128 int num_es_gprs;
2129 int num_temp_gprs;
2130 int num_ps_threads;
2131 int num_vs_threads;
2132 int num_gs_threads;
2133 int num_es_threads;
2134 int num_ps_stack_entries;
2135 int num_vs_stack_entries;
2136 int num_gs_stack_entries;
2137 int num_es_stack_entries;
2138 enum radeon_family family;
2139 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2140 uint32_t tmp;
2141
2142 r600_init_command_buffer(rctx, cb, 0, 256);
2143
2144 /* R6xx requires this packet at the start of each command buffer */
2145 if (rctx->chip_class == R600) {
2146 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2147 r600_store_value(cb, 0);
2148 }
2149 /* All asics require this one */
2150 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2151 r600_store_value(cb, 0x80000000);
2152 r600_store_value(cb, 0x80000000);
2153
2154 family = rctx->family;
2155 ps_prio = 0;
2156 vs_prio = 1;
2157 gs_prio = 2;
2158 es_prio = 3;
2159 switch (family) {
2160 case CHIP_R600:
2161 num_ps_gprs = 192;
2162 num_vs_gprs = 56;
2163 num_temp_gprs = 4;
2164 num_gs_gprs = 0;
2165 num_es_gprs = 0;
2166 num_ps_threads = 136;
2167 num_vs_threads = 48;
2168 num_gs_threads = 4;
2169 num_es_threads = 4;
2170 num_ps_stack_entries = 128;
2171 num_vs_stack_entries = 128;
2172 num_gs_stack_entries = 0;
2173 num_es_stack_entries = 0;
2174 break;
2175 case CHIP_RV630:
2176 case CHIP_RV635:
2177 num_ps_gprs = 84;
2178 num_vs_gprs = 36;
2179 num_temp_gprs = 4;
2180 num_gs_gprs = 0;
2181 num_es_gprs = 0;
2182 num_ps_threads = 144;
2183 num_vs_threads = 40;
2184 num_gs_threads = 4;
2185 num_es_threads = 4;
2186 num_ps_stack_entries = 40;
2187 num_vs_stack_entries = 40;
2188 num_gs_stack_entries = 32;
2189 num_es_stack_entries = 16;
2190 break;
2191 case CHIP_RV610:
2192 case CHIP_RV620:
2193 case CHIP_RS780:
2194 case CHIP_RS880:
2195 default:
2196 num_ps_gprs = 84;
2197 num_vs_gprs = 36;
2198 num_temp_gprs = 4;
2199 num_gs_gprs = 0;
2200 num_es_gprs = 0;
2201 num_ps_threads = 136;
2202 num_vs_threads = 48;
2203 num_gs_threads = 4;
2204 num_es_threads = 4;
2205 num_ps_stack_entries = 40;
2206 num_vs_stack_entries = 40;
2207 num_gs_stack_entries = 32;
2208 num_es_stack_entries = 16;
2209 break;
2210 case CHIP_RV670:
2211 num_ps_gprs = 144;
2212 num_vs_gprs = 40;
2213 num_temp_gprs = 4;
2214 num_gs_gprs = 0;
2215 num_es_gprs = 0;
2216 num_ps_threads = 136;
2217 num_vs_threads = 48;
2218 num_gs_threads = 4;
2219 num_es_threads = 4;
2220 num_ps_stack_entries = 40;
2221 num_vs_stack_entries = 40;
2222 num_gs_stack_entries = 32;
2223 num_es_stack_entries = 16;
2224 break;
2225 case CHIP_RV770:
2226 num_ps_gprs = 192;
2227 num_vs_gprs = 56;
2228 num_temp_gprs = 4;
2229 num_gs_gprs = 0;
2230 num_es_gprs = 0;
2231 num_ps_threads = 188;
2232 num_vs_threads = 60;
2233 num_gs_threads = 0;
2234 num_es_threads = 0;
2235 num_ps_stack_entries = 256;
2236 num_vs_stack_entries = 256;
2237 num_gs_stack_entries = 0;
2238 num_es_stack_entries = 0;
2239 break;
2240 case CHIP_RV730:
2241 case CHIP_RV740:
2242 num_ps_gprs = 84;
2243 num_vs_gprs = 36;
2244 num_temp_gprs = 4;
2245 num_gs_gprs = 0;
2246 num_es_gprs = 0;
2247 num_ps_threads = 188;
2248 num_vs_threads = 60;
2249 num_gs_threads = 0;
2250 num_es_threads = 0;
2251 num_ps_stack_entries = 128;
2252 num_vs_stack_entries = 128;
2253 num_gs_stack_entries = 0;
2254 num_es_stack_entries = 0;
2255 break;
2256 case CHIP_RV710:
2257 num_ps_gprs = 192;
2258 num_vs_gprs = 56;
2259 num_temp_gprs = 4;
2260 num_gs_gprs = 0;
2261 num_es_gprs = 0;
2262 num_ps_threads = 144;
2263 num_vs_threads = 48;
2264 num_gs_threads = 0;
2265 num_es_threads = 0;
2266 num_ps_stack_entries = 128;
2267 num_vs_stack_entries = 128;
2268 num_gs_stack_entries = 0;
2269 num_es_stack_entries = 0;
2270 break;
2271 }
2272
2273 rctx->default_ps_gprs = num_ps_gprs;
2274 rctx->default_vs_gprs = num_vs_gprs;
2275 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2276
2277 /* SQ_CONFIG */
2278 tmp = 0;
2279 switch (family) {
2280 case CHIP_RV610:
2281 case CHIP_RV620:
2282 case CHIP_RS780:
2283 case CHIP_RS880:
2284 case CHIP_RV710:
2285 break;
2286 default:
2287 tmp |= S_008C00_VC_ENABLE(1);
2288 break;
2289 }
2290 tmp |= S_008C00_DX9_CONSTS(0);
2291 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2292 tmp |= S_008C00_PS_PRIO(ps_prio);
2293 tmp |= S_008C00_VS_PRIO(vs_prio);
2294 tmp |= S_008C00_GS_PRIO(gs_prio);
2295 tmp |= S_008C00_ES_PRIO(es_prio);
2296 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2297
2298 /* SQ_GPR_RESOURCE_MGMT_2 */
2299 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2300 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2301 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2302 r600_store_value(cb, tmp);
2303
2304 /* SQ_THREAD_RESOURCE_MGMT */
2305 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2306 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2307 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2308 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2309 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2310
2311 /* SQ_STACK_RESOURCE_MGMT_1 */
2312 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2313 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2314 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2315
2316 /* SQ_STACK_RESOURCE_MGMT_2 */
2317 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2318 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2319 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2320
2321 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2322
2323 if (rctx->chip_class >= R700) {
2324 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2325 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2326 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2327 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2328 } else {
2329 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2330 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2331 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2332 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2333 }
2334 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2335 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2336 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2337 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2338 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2339 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2340 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2341 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2342 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2343 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2344
2345 /* to avoid GPU doing any preloading of constant from random address */
2346 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2347 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2348 r600_store_value(cb, 0);
2349 r600_store_value(cb, 0);
2350 r600_store_value(cb, 0);
2351 r600_store_value(cb, 0);
2352 r600_store_value(cb, 0);
2353 r600_store_value(cb, 0);
2354 r600_store_value(cb, 0);
2355 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2356 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2357 r600_store_value(cb, 0);
2358 r600_store_value(cb, 0);
2359 r600_store_value(cb, 0);
2360 r600_store_value(cb, 0);
2361 r600_store_value(cb, 0);
2362 r600_store_value(cb, 0);
2363 r600_store_value(cb, 0);
2364
2365 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2366 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2367 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2368 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2369 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2370 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2371 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2372 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2373 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2374 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2375 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2376 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2377 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2378 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2379
2380 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2381 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2382 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2383
2384 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2385 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2386 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2387 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2388
2389 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2390
2391 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2392 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2393 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2394
2395 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2396
2397 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2398 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2399 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2400
2401 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2402 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2403 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2404 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2405
2406 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2407 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2408 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2409
2410 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2411 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2412
2413 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2414 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2415 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2416 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2417 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2418
2419 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2420 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2421 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2422
2423 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2424
2425 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2426 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2427
2428 if (rctx->chip_class >= R700) {
2429 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2430 }
2431
2432 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2433 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2434 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2435 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2436 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2437
2438 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2439 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2440 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2441
2442 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2443 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2444 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2445
2446 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2447 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2448 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2449
2450 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2451 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2452
2453 if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2454 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2455 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2456 if (rctx->screen->has_streamout) {
2457 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2458 }
2459
2460 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2461 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2462 }
2463
2464 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2465 {
2466 struct r600_context *rctx = (struct r600_context *)ctx;
2467 struct r600_pipe_state *rstate = &shader->rstate;
2468 struct r600_shader *rshader = &shader->shader;
2469 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2470 int pos_index = -1, face_index = -1;
2471 unsigned tmp, sid, ufi = 0;
2472 int need_linear = 0;
2473 unsigned z_export = 0, stencil_export = 0;
2474
2475 rstate->nregs = 0;
2476
2477 for (i = 0; i < rshader->ninput; i++) {
2478 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2479 pos_index = i;
2480 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2481 face_index = i;
2482
2483 sid = rshader->input[i].spi_sid;
2484
2485 tmp = S_028644_SEMANTIC(sid);
2486
2487 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2488 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2489 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2490 rctx->rasterizer && rctx->rasterizer->flatshade))
2491 tmp |= S_028644_FLAT_SHADE(1);
2492
2493 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2494 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2495 tmp |= S_028644_PT_SPRITE_TEX(1);
2496 }
2497
2498 if (rshader->input[i].centroid)
2499 tmp |= S_028644_SEL_CENTROID(1);
2500
2501 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2502 need_linear = 1;
2503 tmp |= S_028644_SEL_LINEAR(1);
2504 }
2505
2506 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2507 tmp);
2508 }
2509
2510 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2511 for (i = 0; i < rshader->noutput; i++) {
2512 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2513 z_export = 1;
2514 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2515 stencil_export = 1;
2516 }
2517 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2518 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2519 if (rshader->uses_kill)
2520 db_shader_control |= S_02880C_KILL_ENABLE(1);
2521
2522 exports_ps = 0;
2523 for (i = 0; i < rshader->noutput; i++) {
2524 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2525 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2526 exports_ps |= 1;
2527 }
2528 }
2529 num_cout = rshader->nr_ps_color_exports;
2530 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2531 if (!exports_ps) {
2532 /* always at least export 1 component per pixel */
2533 exports_ps = 2;
2534 }
2535
2536 shader->nr_ps_color_outputs = num_cout;
2537
2538 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2539 S_0286CC_PERSP_GRADIENT_ENA(1)|
2540 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2541 spi_input_z = 0;
2542 if (pos_index != -1) {
2543 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2544 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2545 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2546 S_0286CC_BARYC_SAMPLE_CNTL(1));
2547 spi_input_z |= 1;
2548 }
2549
2550 spi_ps_in_control_1 = 0;
2551 if (face_index != -1) {
2552 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2553 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2554 }
2555
2556 /* HW bug in original R600 */
2557 if (rctx->family == CHIP_R600)
2558 ufi = 1;
2559
2560 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2561 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2562 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2563 r600_pipe_state_add_reg_bo(rstate,
2564 R_028840_SQ_PGM_START_PS,
2565 0, shader->bo, RADEON_USAGE_READ);
2566 r600_pipe_state_add_reg(rstate,
2567 R_028850_SQ_PGM_RESOURCES_PS,
2568 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2569 S_028850_STACK_SIZE(rshader->bc.nstack) |
2570 S_028850_UNCACHED_FIRST_INST(ufi));
2571 r600_pipe_state_add_reg(rstate,
2572 R_028854_SQ_PGM_EXPORTS_PS,
2573 exports_ps);
2574 /* only set some bits here, the other bits are set in the dsa state */
2575 shader->db_shader_control = db_shader_control;
2576 shader->ps_depth_export = z_export | stencil_export;
2577
2578 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2579 if (rctx->rasterizer)
2580 shader->flatshade = rctx->rasterizer->flatshade;
2581 }
2582
2583 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2584 {
2585 struct r600_context *rctx = (struct r600_context *)ctx;
2586 struct r600_pipe_state *rstate = &shader->rstate;
2587 struct r600_shader *rshader = &shader->shader;
2588 unsigned spi_vs_out_id[10] = {};
2589 unsigned i, tmp, nparams = 0;
2590
2591 /* clear previous register */
2592 rstate->nregs = 0;
2593
2594 for (i = 0; i < rshader->noutput; i++) {
2595 if (rshader->output[i].spi_sid) {
2596 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2597 spi_vs_out_id[nparams / 4] |= tmp;
2598 nparams++;
2599 }
2600 }
2601
2602 for (i = 0; i < 10; i++) {
2603 r600_pipe_state_add_reg(rstate,
2604 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2605 spi_vs_out_id[i]);
2606 }
2607
2608 /* Certain attributes (position, psize, etc.) don't count as params.
2609 * VS is required to export at least one param and r600_shader_from_tgsi()
2610 * takes care of adding a dummy export.
2611 */
2612 if (nparams < 1)
2613 nparams = 1;
2614
2615 r600_pipe_state_add_reg(rstate,
2616 R_0286C4_SPI_VS_OUT_CONFIG,
2617 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2618 r600_pipe_state_add_reg(rstate,
2619 R_028868_SQ_PGM_RESOURCES_VS,
2620 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2621 S_028868_STACK_SIZE(rshader->bc.nstack));
2622 r600_pipe_state_add_reg_bo(rstate,
2623 R_028858_SQ_PGM_START_VS,
2624 0, shader->bo, RADEON_USAGE_READ);
2625
2626 shader->pa_cl_vs_out_cntl =
2627 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2628 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2629 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2630 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2631 }
2632
2633 void r600_fetch_shader(struct pipe_context *ctx,
2634 struct r600_vertex_element *ve)
2635 {
2636 struct r600_pipe_state *rstate;
2637 struct r600_context *rctx = (struct r600_context *)ctx;
2638
2639 rstate = &ve->rstate;
2640 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2641 rstate->nregs = 0;
2642 r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS,
2643 0,
2644 ve->fetch_shader, RADEON_USAGE_READ);
2645 }
2646
2647 void *r600_create_resolve_blend(struct r600_context *rctx)
2648 {
2649 struct pipe_blend_state blend;
2650 struct r600_pipe_state *rstate;
2651 unsigned i;
2652
2653 memset(&blend, 0, sizeof(blend));
2654 blend.independent_blend_enable = true;
2655 for (i = 0; i < 2; i++) {
2656 blend.rt[i].colormask = 0xf;
2657 blend.rt[i].blend_enable = 1;
2658 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2659 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2660 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2661 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2662 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2663 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2664 }
2665 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2666 return rstate;
2667 }
2668
2669 void *r700_create_resolve_blend(struct r600_context *rctx)
2670 {
2671 struct pipe_blend_state blend;
2672 struct r600_pipe_state *rstate;
2673
2674 memset(&blend, 0, sizeof(blend));
2675 blend.independent_blend_enable = true;
2676 blend.rt[0].colormask = 0xf;
2677 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2678 return rstate;
2679 }
2680
2681 void *r600_create_decompress_blend(struct r600_context *rctx)
2682 {
2683 struct pipe_blend_state blend;
2684 struct r600_pipe_state *rstate;
2685
2686 memset(&blend, 0, sizeof(blend));
2687 blend.independent_blend_enable = true;
2688 blend.rt[0].colormask = 0xf;
2689 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2690 return rstate;
2691 }
2692
2693 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2694 {
2695 struct pipe_depth_stencil_alpha_state dsa;
2696 boolean quirk = false;
2697
2698 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2699 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2700 quirk = true;
2701
2702 memset(&dsa, 0, sizeof(dsa));
2703
2704 if (quirk) {
2705 dsa.depth.enabled = 1;
2706 dsa.depth.func = PIPE_FUNC_LEQUAL;
2707 dsa.stencil[0].enabled = 1;
2708 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2709 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2710 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2711 dsa.stencil[0].writemask = 0xff;
2712 }
2713
2714 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2715 }
2716
2717 void r600_update_dual_export_state(struct r600_context * rctx)
2718 {
2719 unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2720 !rctx->ps_shader->current->ps_depth_export;
2721 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2722 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2723
2724 if (db_shader_control != rctx->db_shader_control) {
2725 struct r600_pipe_state rstate;
2726
2727 rctx->db_shader_control = db_shader_control;
2728 rstate.nregs = 0;
2729 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2730 r600_context_pipe_state_set(rctx, &rstate);
2731 }
2732 }