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[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
145 {
146 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
147 FALSE) != ~0U;
148 }
149
150 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
151 {
152 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
153 r600_translate_colorswap(format, FALSE) != ~0U;
154 }
155
156 static bool r600_is_zs_format_supported(enum pipe_format format)
157 {
158 return r600_translate_dbformat(format) != ~0U;
159 }
160
161 boolean r600_is_format_supported(struct pipe_screen *screen,
162 enum pipe_format format,
163 enum pipe_texture_target target,
164 unsigned sample_count,
165 unsigned usage)
166 {
167 struct r600_screen *rscreen = (struct r600_screen*)screen;
168 unsigned retval = 0;
169
170 if (target >= PIPE_MAX_TEXTURE_TYPES) {
171 R600_ERR("r600: unsupported texture type %d\n", target);
172 return FALSE;
173 }
174
175 if (sample_count > 1) {
176 if (!rscreen->has_msaa)
177 return FALSE;
178
179 /* R11G11B10 is broken on R6xx. */
180 if (rscreen->b.chip_class == R600 &&
181 format == PIPE_FORMAT_R11G11B10_FLOAT)
182 return FALSE;
183
184 /* MSAA integer colorbuffers hang. */
185 if (util_format_is_pure_integer(format) &&
186 !util_format_is_depth_or_stencil(format))
187 return FALSE;
188
189 switch (sample_count) {
190 case 2:
191 case 4:
192 case 8:
193 break;
194 default:
195 return FALSE;
196 }
197 }
198
199 if (usage & PIPE_BIND_SAMPLER_VIEW) {
200 if (target == PIPE_BUFFER) {
201 if (r600_is_vertex_format_supported(format))
202 retval |= PIPE_BIND_SAMPLER_VIEW;
203 } else {
204 if (r600_is_sampler_format_supported(screen, format))
205 retval |= PIPE_BIND_SAMPLER_VIEW;
206 }
207 }
208
209 if ((usage & (PIPE_BIND_RENDER_TARGET |
210 PIPE_BIND_DISPLAY_TARGET |
211 PIPE_BIND_SCANOUT |
212 PIPE_BIND_SHARED |
213 PIPE_BIND_BLENDABLE)) &&
214 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
215 retval |= usage &
216 (PIPE_BIND_RENDER_TARGET |
217 PIPE_BIND_DISPLAY_TARGET |
218 PIPE_BIND_SCANOUT |
219 PIPE_BIND_SHARED);
220 if (!util_format_is_pure_integer(format) &&
221 !util_format_is_depth_or_stencil(format))
222 retval |= usage & PIPE_BIND_BLENDABLE;
223 }
224
225 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
226 r600_is_zs_format_supported(format)) {
227 retval |= PIPE_BIND_DEPTH_STENCIL;
228 }
229
230 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
231 r600_is_vertex_format_supported(format)) {
232 retval |= PIPE_BIND_VERTEX_BUFFER;
233 }
234
235 if ((usage & PIPE_BIND_LINEAR) &&
236 !util_format_is_compressed(format) &&
237 !(usage & PIPE_BIND_DEPTH_STENCIL))
238 retval |= PIPE_BIND_LINEAR;
239
240 return retval == usage;
241 }
242
243 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
244 {
245 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
246 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
247 float offset_units = state->offset_units;
248 float offset_scale = state->offset_scale;
249 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
250
251 if (!state->offset_units_unscaled) {
252 switch (state->zs_format) {
253 case PIPE_FORMAT_Z24X8_UNORM:
254 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
255 offset_units *= 2.0f;
256 pa_su_poly_offset_db_fmt_cntl =
257 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
258 break;
259 case PIPE_FORMAT_Z16_UNORM:
260 offset_units *= 4.0f;
261 pa_su_poly_offset_db_fmt_cntl =
262 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
263 break;
264 default:
265 pa_su_poly_offset_db_fmt_cntl =
266 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
267 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
268 }
269 }
270
271 radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
272 radeon_emit(cs, fui(offset_scale));
273 radeon_emit(cs, fui(offset_units));
274 radeon_emit(cs, fui(offset_scale));
275 radeon_emit(cs, fui(offset_units));
276
277 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
278 pa_su_poly_offset_db_fmt_cntl);
279 }
280
281 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
282 {
283 int j = state->independent_blend_enable ? i : 0;
284
285 unsigned eqRGB = state->rt[j].rgb_func;
286 unsigned srcRGB = state->rt[j].rgb_src_factor;
287 unsigned dstRGB = state->rt[j].rgb_dst_factor;
288
289 unsigned eqA = state->rt[j].alpha_func;
290 unsigned srcA = state->rt[j].alpha_src_factor;
291 unsigned dstA = state->rt[j].alpha_dst_factor;
292 uint32_t bc = 0;
293
294 if (!state->rt[j].blend_enable)
295 return 0;
296
297 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
298 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
299 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
300
301 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
302 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
303 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
304 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
305 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
306 }
307 return bc;
308 }
309
310 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
311 const struct pipe_blend_state *state,
312 int mode)
313 {
314 struct r600_context *rctx = (struct r600_context *)ctx;
315 uint32_t color_control = 0, target_mask = 0;
316 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
317
318 if (!blend) {
319 return NULL;
320 }
321
322 r600_init_command_buffer(&blend->buffer, 20);
323 r600_init_command_buffer(&blend->buffer_no_blend, 20);
324
325 /* R600 does not support per-MRT blends */
326 if (rctx->b.family > CHIP_R600)
327 color_control |= S_028808_PER_MRT_BLEND(1);
328
329 if (state->logicop_enable) {
330 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
331 } else {
332 color_control |= (0xcc << 16);
333 }
334 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
335 if (state->independent_blend_enable) {
336 for (int i = 0; i < 8; i++) {
337 if (state->rt[i].blend_enable) {
338 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
339 }
340 target_mask |= (state->rt[i].colormask << (4 * i));
341 }
342 } else {
343 for (int i = 0; i < 8; i++) {
344 if (state->rt[0].blend_enable) {
345 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
346 }
347 target_mask |= (state->rt[0].colormask << (4 * i));
348 }
349 }
350
351 if (target_mask)
352 color_control |= S_028808_SPECIAL_OP(mode);
353 else
354 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
355
356 /* only MRT0 has dual src blend */
357 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
358 blend->cb_target_mask = target_mask;
359 blend->cb_color_control = color_control;
360 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
361 blend->alpha_to_one = state->alpha_to_one;
362
363 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
364 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
365 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
366 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
367 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
368 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
369
370 /* Copy over the registers set so far into buffer_no_blend. */
371 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
372 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
373
374 /* Only add blend registers if blending is enabled. */
375 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
376 return blend;
377 }
378
379 /* The first R600 does not support per-MRT blends */
380 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
381 r600_get_blend_control(state, 0));
382
383 if (rctx->b.family > CHIP_R600) {
384 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
385 for (int i = 0; i < 8; i++) {
386 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
387 }
388 }
389 return blend;
390 }
391
392 static void *r600_create_blend_state(struct pipe_context *ctx,
393 const struct pipe_blend_state *state)
394 {
395 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
396 }
397
398 static void *r600_create_dsa_state(struct pipe_context *ctx,
399 const struct pipe_depth_stencil_alpha_state *state)
400 {
401 unsigned db_depth_control, alpha_test_control, alpha_ref;
402 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
403
404 if (!dsa) {
405 return NULL;
406 }
407
408 r600_init_command_buffer(&dsa->buffer, 3);
409
410 dsa->valuemask[0] = state->stencil[0].valuemask;
411 dsa->valuemask[1] = state->stencil[1].valuemask;
412 dsa->writemask[0] = state->stencil[0].writemask;
413 dsa->writemask[1] = state->stencil[1].writemask;
414 dsa->zwritemask = state->depth.writemask;
415
416 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
417 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
418 S_028800_ZFUNC(state->depth.func);
419
420 /* stencil */
421 if (state->stencil[0].enabled) {
422 db_depth_control |= S_028800_STENCIL_ENABLE(1);
423 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
424 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
425 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
426 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
427
428 if (state->stencil[1].enabled) {
429 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
430 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
431 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
432 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
433 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
434 }
435 }
436
437 /* alpha */
438 alpha_test_control = 0;
439 alpha_ref = 0;
440 if (state->alpha.enabled) {
441 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
442 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
443 alpha_ref = fui(state->alpha.ref_value);
444 }
445 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
446 dsa->alpha_ref = alpha_ref;
447
448 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
449 return dsa;
450 }
451
452 static void *r600_create_rs_state(struct pipe_context *ctx,
453 const struct pipe_rasterizer_state *state)
454 {
455 struct r600_context *rctx = (struct r600_context *)ctx;
456 unsigned tmp, sc_mode_cntl, spi_interp;
457 float psize_min, psize_max;
458 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
459
460 if (!rs) {
461 return NULL;
462 }
463
464 r600_init_command_buffer(&rs->buffer, 30);
465
466 rs->scissor_enable = state->scissor;
467 rs->clip_halfz = state->clip_halfz;
468 rs->flatshade = state->flatshade;
469 rs->sprite_coord_enable = state->sprite_coord_enable;
470 rs->rasterizer_discard = state->rasterizer_discard;
471 rs->two_side = state->light_twoside;
472 rs->clip_plane_enable = state->clip_plane_enable;
473 rs->pa_sc_line_stipple = state->line_stipple_enable ?
474 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
475 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
476 rs->pa_cl_clip_cntl =
477 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
478 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
479 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
480 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
481 if (rctx->b.chip_class == R700) {
482 rs->pa_cl_clip_cntl |=
483 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
484 }
485 rs->multisample_enable = state->multisample;
486
487 /* offset */
488 rs->offset_units = state->offset_units;
489 rs->offset_scale = state->offset_scale * 16.0f;
490 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
491 rs->offset_units_unscaled = state->offset_units_unscaled;
492
493 if (state->point_size_per_vertex) {
494 psize_min = util_get_min_point_size(state);
495 psize_max = 8192;
496 } else {
497 /* Force the point size to be as if the vertex output was disabled. */
498 psize_min = state->point_size;
499 psize_max = state->point_size;
500 }
501
502 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
503 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
504 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
505 S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1);
506 if (rctx->b.family == CHIP_RV770) {
507 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */
508 sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1);
509 }
510 if (rctx->b.chip_class >= R700) {
511 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
512 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
513 S_028A4C_R700_VPORT_SCISSOR_ENABLE(1);
514 } else {
515 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
516 }
517
518 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
519 if (state->sprite_coord_enable) {
520 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
521 S_0286D4_PNT_SPRITE_OVRD_X(2) |
522 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
523 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
524 S_0286D4_PNT_SPRITE_OVRD_W(1);
525 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
526 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
527 }
528 }
529
530 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
531 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
532 tmp = r600_pack_float_12p4(state->point_size/2);
533 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
534 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
535 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
536 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
537 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
538 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
539 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
540
541 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
542 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
543 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
544 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
545 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
546 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
547
548 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
549 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
550 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
551 S_028814_FACE(!state->front_ccw) |
552 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
553 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
554 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
555 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
556 state->fill_back != PIPE_POLYGON_MODE_FILL) |
557 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
558 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
559 if (rctx->b.chip_class == R700) {
560 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
561 }
562 if (rctx->b.chip_class == R600) {
563 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
564 S_028350_MULTIPASS(state->rasterizer_discard));
565 }
566 return rs;
567 }
568
569 static unsigned r600_tex_filter(unsigned filter, unsigned max_aniso)
570 {
571 if (filter == PIPE_TEX_FILTER_LINEAR)
572 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_BILINEAR
573 : V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
574 else
575 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_POINT
576 : V_03C000_SQ_TEX_XY_FILTER_POINT;
577 }
578
579 static void *r600_create_sampler_state(struct pipe_context *ctx,
580 const struct pipe_sampler_state *state)
581 {
582 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
583 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
584 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
585 : state->max_anisotropy;
586 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
587
588 if (!ss) {
589 return NULL;
590 }
591
592 ss->seamless_cube_map = state->seamless_cube_map;
593 ss->border_color_use = sampler_state_needs_border_color(state);
594
595 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
596 ss->tex_sampler_words[0] =
597 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
598 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
599 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
600 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter, max_aniso)) |
601 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter, max_aniso)) |
602 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
603 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
604 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
605 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
606 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
607 ss->tex_sampler_words[1] =
608 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
609 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
610 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
611 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
612 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
613
614 if (ss->border_color_use) {
615 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
616 }
617 return ss;
618 }
619
620 static struct pipe_sampler_view *
621 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
622 unsigned width0, unsigned height0)
623
624 {
625 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
626 int stride = util_format_get_blocksize(view->base.format);
627 unsigned format, num_format, format_comp, endian;
628 uint64_t offset = view->base.u.buf.offset;
629 unsigned size = view->base.u.buf.size;
630
631 r600_vertex_data_type(view->base.format,
632 &format, &num_format, &format_comp,
633 &endian);
634
635 view->tex_resource = &tmp->resource;
636 view->skip_mip_address_reloc = true;
637
638 view->tex_resource_words[0] = offset;
639 view->tex_resource_words[1] = size - 1;
640 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) |
641 S_038008_STRIDE(stride) |
642 S_038008_DATA_FORMAT(format) |
643 S_038008_NUM_FORMAT_ALL(num_format) |
644 S_038008_FORMAT_COMP_ALL(format_comp) |
645 S_038008_ENDIAN_SWAP(endian);
646 view->tex_resource_words[3] = 0;
647 /*
648 * in theory dword 4 is for number of elements, for use with resinfo,
649 * but it seems to utterly fail to work, the amd gpu shader analyser
650 * uses a const buffer to store the element sizes for buffer txq
651 */
652 view->tex_resource_words[4] = 0;
653 view->tex_resource_words[5] = 0;
654 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
655 return &view->base;
656 }
657
658 struct pipe_sampler_view *
659 r600_create_sampler_view_custom(struct pipe_context *ctx,
660 struct pipe_resource *texture,
661 const struct pipe_sampler_view *state,
662 unsigned width_first_level, unsigned height_first_level)
663 {
664 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
665 struct r600_texture *tmp = (struct r600_texture*)texture;
666 unsigned format, endian;
667 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
668 unsigned char swizzle[4], array_mode = 0;
669 unsigned width, height, depth, offset_level, last_level;
670 bool do_endian_swap = FALSE;
671
672 if (!view)
673 return NULL;
674
675 /* initialize base object */
676 view->base = *state;
677 view->base.texture = NULL;
678 pipe_reference(NULL, &texture->reference);
679 view->base.texture = texture;
680 view->base.reference.count = 1;
681 view->base.context = ctx;
682
683 if (texture->target == PIPE_BUFFER)
684 return texture_buffer_sampler_view(view, texture->width0, 1);
685
686 swizzle[0] = state->swizzle_r;
687 swizzle[1] = state->swizzle_g;
688 swizzle[2] = state->swizzle_b;
689 swizzle[3] = state->swizzle_a;
690
691 if (R600_BIG_ENDIAN)
692 do_endian_swap = !tmp->db_compatible;
693
694 format = r600_translate_texformat(ctx->screen, state->format,
695 swizzle,
696 &word4, &yuv_format, do_endian_swap);
697 assert(format != ~0);
698 if (format == ~0) {
699 FREE(view);
700 return NULL;
701 }
702
703 if (state->format == PIPE_FORMAT_X24S8_UINT ||
704 state->format == PIPE_FORMAT_S8X24_UINT ||
705 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
706 state->format == PIPE_FORMAT_S8_UINT)
707 view->is_stencil_sampler = true;
708
709 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
710 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
711 FREE(view);
712 return NULL;
713 }
714 tmp = tmp->flushed_depth_texture;
715 }
716
717 endian = r600_colorformat_endian_swap(format, do_endian_swap);
718
719 offset_level = state->u.tex.first_level;
720 last_level = state->u.tex.last_level - offset_level;
721 width = width_first_level;
722 height = height_first_level;
723 depth = u_minify(texture->depth0, offset_level);
724 pitch = tmp->surface.u.legacy.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
725
726 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
727 height = 1;
728 depth = texture->array_size;
729 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
730 depth = texture->array_size;
731 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
732 depth = texture->array_size / 6;
733
734 switch (tmp->surface.u.legacy.level[offset_level].mode) {
735 default:
736 case RADEON_SURF_MODE_LINEAR_ALIGNED:
737 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
738 break;
739 case RADEON_SURF_MODE_1D:
740 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
741 break;
742 case RADEON_SURF_MODE_2D:
743 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
744 break;
745 }
746
747 view->tex_resource = &tmp->resource;
748 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
749 S_038000_TILE_MODE(array_mode) |
750 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
751 S_038000_PITCH((pitch / 8) - 1) |
752 S_038000_TEX_WIDTH(width - 1));
753 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
754 S_038004_TEX_DEPTH(depth - 1) |
755 S_038004_DATA_FORMAT(format));
756 view->tex_resource_words[2] = tmp->surface.u.legacy.level[offset_level].offset >> 8;
757 if (offset_level >= tmp->resource.b.b.last_level) {
758 view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level].offset >> 8;
759 } else {
760 view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level + 1].offset >> 8;
761 }
762 view->tex_resource_words[4] = (word4 |
763 S_038010_REQUEST_SIZE(1) |
764 S_038010_ENDIAN_SWAP(endian) |
765 S_038010_BASE_LEVEL(0));
766 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
767 S_038014_LAST_ARRAY(state->u.tex.last_layer));
768 if (texture->nr_samples > 1) {
769 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
770 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
771 } else {
772 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
773 }
774 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
775 S_038018_MAX_ANISO(4 /* max 16 samples */));
776 return &view->base;
777 }
778
779 static struct pipe_sampler_view *
780 r600_create_sampler_view(struct pipe_context *ctx,
781 struct pipe_resource *tex,
782 const struct pipe_sampler_view *state)
783 {
784 return r600_create_sampler_view_custom(ctx, tex, state,
785 u_minify(tex->width0, state->u.tex.first_level),
786 u_minify(tex->height0, state->u.tex.first_level));
787 }
788
789 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
790 {
791 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
792 struct pipe_clip_state *state = &rctx->clip_state.state;
793
794 radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
795 radeon_emit_array(cs, (unsigned*)state, 6*4);
796 }
797
798 static void r600_set_polygon_stipple(struct pipe_context *ctx,
799 const struct pipe_poly_stipple *state)
800 {
801 }
802
803 static void r600_init_color_surface(struct r600_context *rctx,
804 struct r600_surface *surf,
805 bool force_cmask_fmask)
806 {
807 struct r600_screen *rscreen = rctx->screen;
808 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
809 unsigned level = surf->base.u.tex.level;
810 unsigned pitch, slice;
811 unsigned color_info;
812 unsigned color_view;
813 unsigned format, swap, ntype, endian;
814 unsigned offset;
815 const struct util_format_description *desc;
816 int i;
817 bool blend_bypass = 0, blend_clamp = 0, do_endian_swap = FALSE;
818
819 if (rtex->db_compatible && !r600_can_sample_zs(rtex, false)) {
820 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
821 rtex = rtex->flushed_depth_texture;
822 assert(rtex);
823 }
824
825 offset = rtex->surface.u.legacy.level[level].offset;
826 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
827 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
828
829 pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1;
830 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
831 if (slice) {
832 slice = slice - 1;
833 }
834 color_info = 0;
835 switch (rtex->surface.u.legacy.level[level].mode) {
836 default:
837 case RADEON_SURF_MODE_LINEAR_ALIGNED:
838 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
839 break;
840 case RADEON_SURF_MODE_1D:
841 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
842 break;
843 case RADEON_SURF_MODE_2D:
844 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
845 break;
846 }
847
848 desc = util_format_description(surf->base.format);
849
850 for (i = 0; i < 4; i++) {
851 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
852 break;
853 }
854 }
855
856 ntype = V_0280A0_NUMBER_UNORM;
857 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
858 ntype = V_0280A0_NUMBER_SRGB;
859 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
860 if (desc->channel[i].normalized)
861 ntype = V_0280A0_NUMBER_SNORM;
862 else if (desc->channel[i].pure_integer)
863 ntype = V_0280A0_NUMBER_SINT;
864 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
865 if (desc->channel[i].normalized)
866 ntype = V_0280A0_NUMBER_UNORM;
867 else if (desc->channel[i].pure_integer)
868 ntype = V_0280A0_NUMBER_UINT;
869 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
870 ntype = V_0280A0_NUMBER_FLOAT;
871 }
872
873 if (R600_BIG_ENDIAN)
874 do_endian_swap = !rtex->db_compatible;
875
876 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format,
877 do_endian_swap);
878 assert(format != ~0);
879
880 swap = r600_translate_colorswap(surf->base.format, do_endian_swap);
881 assert(swap != ~0);
882
883 endian = r600_colorformat_endian_swap(format, do_endian_swap);
884
885 /* blend clamp should be set for all NORM/SRGB types */
886 if (ntype == V_0280A0_NUMBER_UNORM || ntype == V_0280A0_NUMBER_SNORM ||
887 ntype == V_0280A0_NUMBER_SRGB)
888 blend_clamp = 1;
889
890 /* set blend bypass according to docs if SINT/UINT or
891 8/24 COLOR variants */
892 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
893 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
894 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
895 blend_clamp = 0;
896 blend_bypass = 1;
897 }
898
899 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
900
901 color_info |= S_0280A0_FORMAT(format) |
902 S_0280A0_COMP_SWAP(swap) |
903 S_0280A0_BLEND_BYPASS(blend_bypass) |
904 S_0280A0_BLEND_CLAMP(blend_clamp) |
905 S_0280A0_SIMPLE_FLOAT(1) |
906 S_0280A0_NUMBER_TYPE(ntype) |
907 S_0280A0_ENDIAN(endian);
908
909 /* EXPORT_NORM is an optimzation that can be enabled for better
910 * performance in certain cases
911 */
912 if (rctx->b.chip_class == R600) {
913 /* EXPORT_NORM can be enabled if:
914 * - 11-bit or smaller UNORM/SNORM/SRGB
915 * - BLEND_CLAMP is enabled
916 * - BLEND_FLOAT32 is disabled
917 */
918 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
919 (desc->channel[i].size < 12 &&
920 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
921 ntype != V_0280A0_NUMBER_UINT &&
922 ntype != V_0280A0_NUMBER_SINT) &&
923 G_0280A0_BLEND_CLAMP(color_info) &&
924 /* XXX this condition is always true since BLEND_FLOAT32 is never set (bug?). */
925 !G_0280A0_BLEND_FLOAT32(color_info)) {
926 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
927 surf->export_16bpc = true;
928 }
929 } else {
930 /* EXPORT_NORM can be enabled if:
931 * - 11-bit or smaller UNORM/SNORM/SRGB
932 * - 16-bit or smaller FLOAT
933 */
934 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
935 ((desc->channel[i].size < 12 &&
936 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
937 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
938 (desc->channel[i].size < 17 &&
939 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
940 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
941 surf->export_16bpc = true;
942 }
943 }
944
945 /* These might not always be initialized to zero. */
946 surf->cb_color_base = offset >> 8;
947 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
948 S_028060_SLICE_TILE_MAX(slice);
949 surf->cb_color_fmask = surf->cb_color_base;
950 surf->cb_color_cmask = surf->cb_color_base;
951 surf->cb_color_mask = 0;
952
953 r600_resource_reference(&surf->cb_buffer_cmask, &rtex->resource);
954 r600_resource_reference(&surf->cb_buffer_fmask, &rtex->resource);
955
956 if (rtex->cmask.size) {
957 surf->cb_color_cmask = rtex->cmask.offset >> 8;
958 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
959
960 if (rtex->fmask.size) {
961 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
962 surf->cb_color_fmask = rtex->fmask.offset >> 8;
963 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
964 } else { /* cmask only */
965 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
966 }
967 } else if (force_cmask_fmask) {
968 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
969 *
970 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
971 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
972 * because it's not an MSAA buffer.
973 */
974 struct r600_cmask_info cmask;
975 struct r600_fmask_info fmask;
976
977 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
978 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
979
980 /* CMASK. */
981 if (!rctx->dummy_cmask ||
982 rctx->dummy_cmask->b.b.width0 < cmask.size ||
983 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
984 struct pipe_transfer *transfer;
985 void *ptr;
986
987 r600_resource_reference(&rctx->dummy_cmask, NULL);
988 rctx->dummy_cmask = (struct r600_resource*)
989 r600_aligned_buffer_create(&rscreen->b.b, 0,
990 PIPE_USAGE_DEFAULT,
991 cmask.size, cmask.alignment);
992
993 if (unlikely(!rctx->dummy_cmask)) {
994 surf->color_initialized = false;
995 return;
996 }
997
998 /* Set the contents to 0xCC. */
999 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1000 memset(ptr, 0xCC, cmask.size);
1001 pipe_buffer_unmap(&rctx->b.b, transfer);
1002 }
1003 r600_resource_reference(&surf->cb_buffer_cmask, rctx->dummy_cmask);
1004
1005 /* FMASK. */
1006 if (!rctx->dummy_fmask ||
1007 rctx->dummy_fmask->b.b.width0 < fmask.size ||
1008 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1009 r600_resource_reference(&rctx->dummy_fmask, NULL);
1010 rctx->dummy_fmask = (struct r600_resource*)
1011 r600_aligned_buffer_create(&rscreen->b.b, 0,
1012 PIPE_USAGE_DEFAULT,
1013 fmask.size, fmask.alignment);
1014
1015 if (unlikely(!rctx->dummy_fmask)) {
1016 surf->color_initialized = false;
1017 return;
1018 }
1019 }
1020 r600_resource_reference(&surf->cb_buffer_fmask, rctx->dummy_fmask);
1021
1022 /* Init the registers. */
1023 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1024 surf->cb_color_cmask = 0;
1025 surf->cb_color_fmask = 0;
1026 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1027 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1028 }
1029
1030 surf->cb_color_info = color_info;
1031 surf->cb_color_view = color_view;
1032 surf->color_initialized = true;
1033 }
1034
1035 static void r600_init_depth_surface(struct r600_context *rctx,
1036 struct r600_surface *surf)
1037 {
1038 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1039 unsigned level, pitch, slice, format, offset, array_mode;
1040
1041 level = surf->base.u.tex.level;
1042 offset = rtex->surface.u.legacy.level[level].offset;
1043 pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1;
1044 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
1045 if (slice) {
1046 slice = slice - 1;
1047 }
1048 switch (rtex->surface.u.legacy.level[level].mode) {
1049 case RADEON_SURF_MODE_2D:
1050 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1051 break;
1052 case RADEON_SURF_MODE_1D:
1053 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1054 default:
1055 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1056 break;
1057 }
1058
1059 format = r600_translate_dbformat(surf->base.format);
1060 assert(format != ~0);
1061
1062 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1063 surf->db_depth_base = offset >> 8;
1064 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1065 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1066 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1067 surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1;
1068
1069 if (r600_htile_enabled(rtex, level)) {
1070 surf->db_htile_data_base = rtex->htile_offset >> 8;
1071 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1072 S_028D24_HTILE_HEIGHT(1) |
1073 S_028D24_FULL_CACHE(1);
1074 /* preload is not working properly on r6xx/r7xx */
1075 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1076 }
1077
1078 surf->depth_initialized = true;
1079 }
1080
1081 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1082 const struct pipe_framebuffer_state *state)
1083 {
1084 struct r600_context *rctx = (struct r600_context *)ctx;
1085 struct r600_surface *surf;
1086 struct r600_texture *rtex;
1087 unsigned i;
1088 uint32_t target_mask = 0;
1089
1090 /* Flush TC when changing the framebuffer state, because the only
1091 * client not using TC that can change textures is the framebuffer.
1092 * Other places don't typically have to flush TC.
1093 */
1094 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1095 R600_CONTEXT_FLUSH_AND_INV |
1096 R600_CONTEXT_FLUSH_AND_INV_CB |
1097 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1098 R600_CONTEXT_FLUSH_AND_INV_DB |
1099 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1100 R600_CONTEXT_INV_TEX_CACHE;
1101
1102 /* Set the new state. */
1103 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1104
1105 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1106 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1107 util_format_is_pure_integer(state->cbufs[0]->format);
1108 rctx->framebuffer.compressed_cb_mask = 0;
1109 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1110 state->cbufs[0] && state->cbufs[1] &&
1111 state->cbufs[0]->texture->nr_samples > 1 &&
1112 state->cbufs[1]->texture->nr_samples <= 1;
1113 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1114
1115 /* Colorbuffers. */
1116 for (i = 0; i < state->nr_cbufs; i++) {
1117 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1118 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1119 rctx->framebuffer.is_msaa_resolve &&
1120 i == 1;
1121
1122 surf = (struct r600_surface*)state->cbufs[i];
1123 if (!surf)
1124 continue;
1125
1126 rtex = (struct r600_texture*)surf->base.texture;
1127 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1128
1129 target_mask |= (0xf << (i * 4));
1130
1131 if (!surf->color_initialized || force_cmask_fmask) {
1132 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1133 if (force_cmask_fmask) {
1134 /* re-initialize later without compression */
1135 surf->color_initialized = false;
1136 }
1137 }
1138
1139 if (!surf->export_16bpc) {
1140 rctx->framebuffer.export_16bpc = false;
1141 }
1142
1143 if (rtex->fmask.size) {
1144 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1145 }
1146 }
1147
1148 /* Update alpha-test state dependencies.
1149 * Alpha-test is done on the first colorbuffer only. */
1150 if (state->nr_cbufs) {
1151 bool alphatest_bypass = false;
1152
1153 surf = (struct r600_surface*)state->cbufs[0];
1154 if (surf) {
1155 alphatest_bypass = surf->alphatest_bypass;
1156 }
1157
1158 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1159 rctx->alphatest_state.bypass = alphatest_bypass;
1160 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1161 }
1162 }
1163
1164 /* ZS buffer. */
1165 if (state->zsbuf) {
1166 surf = (struct r600_surface*)state->zsbuf;
1167
1168 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1169
1170 if (!surf->depth_initialized) {
1171 r600_init_depth_surface(rctx, surf);
1172 }
1173
1174 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1175 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1176 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1177 }
1178
1179 if (rctx->db_state.rsurf != surf) {
1180 rctx->db_state.rsurf = surf;
1181 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1182 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1183 }
1184 } else if (rctx->db_state.rsurf) {
1185 rctx->db_state.rsurf = NULL;
1186 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1187 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1188 }
1189
1190 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs ||
1191 rctx->cb_misc_state.bound_cbufs_target_mask != target_mask) {
1192 rctx->cb_misc_state.bound_cbufs_target_mask = target_mask;
1193 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1194 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1195 }
1196
1197 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1198 rctx->alphatest_state.bypass = false;
1199 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1200 }
1201
1202 /* Calculate the CS size. */
1203 rctx->framebuffer.atom.num_dw =
1204 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1205
1206 if (rctx->framebuffer.state.nr_cbufs) {
1207 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1208 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1209 }
1210 if (rctx->framebuffer.state.zsbuf) {
1211 rctx->framebuffer.atom.num_dw += 16;
1212 } else if (rctx->screen->b.info.drm_minor >= 18) {
1213 rctx->framebuffer.atom.num_dw += 3;
1214 }
1215 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1216 rctx->framebuffer.atom.num_dw += 2;
1217 }
1218
1219 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1220
1221 r600_set_sample_locations_constant_buffer(rctx);
1222 rctx->framebuffer.do_update_surf_dirtiness = true;
1223 }
1224
1225 static uint32_t sample_locs_2x[] = {
1226 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1227 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1228 };
1229 static unsigned max_dist_2x = 4;
1230
1231 static uint32_t sample_locs_4x[] = {
1232 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1233 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1234 };
1235 static unsigned max_dist_4x = 6;
1236 static uint32_t sample_locs_8x[] = {
1237 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1238 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1239 };
1240 static unsigned max_dist_8x = 7;
1241
1242 static void r600_get_sample_position(struct pipe_context *ctx,
1243 unsigned sample_count,
1244 unsigned sample_index,
1245 float *out_value)
1246 {
1247 int offset, index;
1248 struct {
1249 int idx:4;
1250 } val;
1251 switch (sample_count) {
1252 case 1:
1253 default:
1254 out_value[0] = out_value[1] = 0.5;
1255 break;
1256 case 2:
1257 offset = 4 * (sample_index * 2);
1258 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1259 out_value[0] = (float)(val.idx + 8) / 16.0f;
1260 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1261 out_value[1] = (float)(val.idx + 8) / 16.0f;
1262 break;
1263 case 4:
1264 offset = 4 * (sample_index * 2);
1265 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1266 out_value[0] = (float)(val.idx + 8) / 16.0f;
1267 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1268 out_value[1] = (float)(val.idx + 8) / 16.0f;
1269 break;
1270 case 8:
1271 offset = 4 * (sample_index % 4 * 2);
1272 index = (sample_index / 4);
1273 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1274 out_value[0] = (float)(val.idx + 8) / 16.0f;
1275 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1276 out_value[1] = (float)(val.idx + 8) / 16.0f;
1277 break;
1278 }
1279 }
1280
1281 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1282 {
1283 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1284 unsigned max_dist = 0;
1285
1286 if (rctx->b.family == CHIP_R600) {
1287 switch (nr_samples) {
1288 default:
1289 nr_samples = 0;
1290 break;
1291 case 2:
1292 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1293 max_dist = max_dist_2x;
1294 break;
1295 case 4:
1296 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1297 max_dist = max_dist_4x;
1298 break;
1299 case 8:
1300 radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1301 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1302 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1303 max_dist = max_dist_8x;
1304 break;
1305 }
1306 } else {
1307 switch (nr_samples) {
1308 default:
1309 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1310 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1311 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1312 nr_samples = 0;
1313 break;
1314 case 2:
1315 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1316 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1317 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1318 max_dist = max_dist_2x;
1319 break;
1320 case 4:
1321 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1322 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1323 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1324 max_dist = max_dist_4x;
1325 break;
1326 case 8:
1327 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1328 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1329 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1330 max_dist = max_dist_8x;
1331 break;
1332 }
1333 }
1334
1335 if (nr_samples > 1) {
1336 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1337 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1338 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1339 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1340 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1341 } else {
1342 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1343 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1344 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1345 }
1346 }
1347
1348 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1349 {
1350 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1351 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1352 unsigned nr_cbufs = state->nr_cbufs;
1353 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1354 unsigned i, sbu = 0;
1355
1356 /* Colorbuffers. */
1357 radeon_set_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1358 for (i = 0; i < nr_cbufs; i++) {
1359 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1360 }
1361 /* set CB_COLOR1_INFO for possible dual-src blending */
1362 if (rctx->framebuffer.dual_src_blend && i == 1 && cb[0]) {
1363 radeon_emit(cs, cb[0]->cb_color_info);
1364 i++;
1365 }
1366 for (; i < 8; i++) {
1367 radeon_emit(cs, 0);
1368 }
1369
1370 if (nr_cbufs) {
1371 for (i = 0; i < nr_cbufs; i++) {
1372 unsigned reloc;
1373
1374 if (!cb[i])
1375 continue;
1376
1377 /* COLOR_BASE */
1378 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1379
1380 reloc = radeon_add_to_buffer_list(&rctx->b,
1381 &rctx->b.gfx,
1382 (struct r600_resource*)cb[i]->base.texture,
1383 RADEON_USAGE_READWRITE,
1384 cb[i]->base.texture->nr_samples > 1 ?
1385 RADEON_PRIO_COLOR_BUFFER_MSAA :
1386 RADEON_PRIO_COLOR_BUFFER);
1387 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1388 radeon_emit(cs, reloc);
1389
1390 /* FMASK */
1391 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1392
1393 reloc = radeon_add_to_buffer_list(&rctx->b,
1394 &rctx->b.gfx,
1395 cb[i]->cb_buffer_fmask,
1396 RADEON_USAGE_READWRITE,
1397 cb[i]->base.texture->nr_samples > 1 ?
1398 RADEON_PRIO_COLOR_BUFFER_MSAA :
1399 RADEON_PRIO_COLOR_BUFFER);
1400 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1401 radeon_emit(cs, reloc);
1402
1403 /* CMASK */
1404 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1405
1406 reloc = radeon_add_to_buffer_list(&rctx->b,
1407 &rctx->b.gfx,
1408 cb[i]->cb_buffer_cmask,
1409 RADEON_USAGE_READWRITE,
1410 cb[i]->base.texture->nr_samples > 1 ?
1411 RADEON_PRIO_COLOR_BUFFER_MSAA :
1412 RADEON_PRIO_COLOR_BUFFER);
1413 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1414 radeon_emit(cs, reloc);
1415 }
1416
1417 radeon_set_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1418 for (i = 0; i < nr_cbufs; i++) {
1419 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1420 }
1421
1422 radeon_set_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1423 for (i = 0; i < nr_cbufs; i++) {
1424 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1425 }
1426
1427 radeon_set_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1428 for (i = 0; i < nr_cbufs; i++) {
1429 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1430 }
1431
1432 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1433 }
1434
1435 /* SURFACE_BASE_UPDATE */
1436 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1437 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1438 radeon_emit(cs, sbu);
1439 sbu = 0;
1440 }
1441
1442 /* Zbuffer. */
1443 if (state->zsbuf) {
1444 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1445 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1446 &rctx->b.gfx,
1447 (struct r600_resource*)state->zsbuf->texture,
1448 RADEON_USAGE_READWRITE,
1449 surf->base.texture->nr_samples > 1 ?
1450 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1451 RADEON_PRIO_DEPTH_BUFFER);
1452
1453 radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1454 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1455 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1456 radeon_set_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1457 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1458 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1459
1460 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1461 radeon_emit(cs, reloc);
1462
1463 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1464
1465 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1466 } else if (rctx->screen->b.info.drm_minor >= 18) {
1467 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1468 * Older kernels are out of luck. */
1469 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1470 }
1471
1472 /* SURFACE_BASE_UPDATE */
1473 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1474 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1475 radeon_emit(cs, sbu);
1476 sbu = 0;
1477 }
1478
1479 /* Framebuffer dimensions. */
1480 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1481 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1482 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1483 radeon_emit(cs, S_028244_BR_X(state->width) |
1484 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1485
1486 if (rctx->framebuffer.is_msaa_resolve) {
1487 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1488 } else {
1489 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1490 * will assure that the alpha-test will work even if there is
1491 * no colorbuffer bound. */
1492 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1493 (1ull << MAX2(nr_cbufs, 1)) - 1);
1494 }
1495
1496 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1497 }
1498
1499 static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1500 {
1501 struct r600_context *rctx = (struct r600_context *)ctx;
1502
1503 if (rctx->ps_iter_samples == min_samples)
1504 return;
1505
1506 rctx->ps_iter_samples = min_samples;
1507 if (rctx->framebuffer.nr_samples > 1) {
1508 r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom);
1509 if (rctx->b.chip_class == R600)
1510 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1511 }
1512 }
1513
1514 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1515 {
1516 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1517 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1518
1519 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1520 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1521 if (rctx->b.chip_class == R600) {
1522 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1523 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1524 } else {
1525 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1526 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1527 }
1528 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1529 } else {
1530 unsigned fb_colormask = a->bound_cbufs_target_mask;
1531 unsigned ps_colormask = a->ps_color_export_mask;
1532 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1533
1534 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1535 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1536 /* Always enable the first color output to make sure alpha-test works even without one. */
1537 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1538 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1539 a->cb_color_control |
1540 S_028808_MULTIWRITE_ENABLE(multiwrite));
1541 }
1542 }
1543
1544 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1545 {
1546 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1547 struct r600_db_state *a = (struct r600_db_state*)atom;
1548
1549 if (a->rsurf && a->rsurf->db_htile_surface) {
1550 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1551 unsigned reloc_idx;
1552
1553 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1554 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1555 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1556 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
1557 RADEON_USAGE_READWRITE, RADEON_PRIO_SEPARATE_META);
1558 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1559 radeon_emit(cs, reloc_idx);
1560 } else {
1561 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1562 }
1563 }
1564
1565 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1566 {
1567 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1568 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1569 unsigned db_render_control = 0;
1570 unsigned db_render_override =
1571 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1572 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1573
1574 if (rctx->b.chip_class >= R700) {
1575 switch (a->ps_conservative_z) {
1576 default: /* fall through */
1577 case TGSI_FS_DEPTH_LAYOUT_ANY:
1578 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_ANY_Z);
1579 break;
1580 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1581 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_GREATER_THAN_Z);
1582 break;
1583 case TGSI_FS_DEPTH_LAYOUT_LESS:
1584 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_LESS_THAN_Z);
1585 break;
1586 }
1587 }
1588
1589 if (rctx->b.num_occlusion_queries > 0 &&
1590 !a->occlusion_queries_disabled) {
1591 if (rctx->b.chip_class >= R700) {
1592 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1593 }
1594 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1595 } else {
1596 db_render_control |= S_028D0C_ZPASS_INCREMENT_DISABLE(1);
1597 }
1598
1599 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1600 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1601 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1602 /* This is to fix a lockup when hyperz and alpha test are enabled at
1603 * the same time somehow GPU get confuse on which order to pick for
1604 * z test
1605 */
1606 if (rctx->alphatest_state.sx_alpha_test_control) {
1607 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1608 }
1609 } else {
1610 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1611 }
1612 if (rctx->b.chip_class == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) {
1613 /* sample shading and hyperz causes lockups on R6xx chips */
1614 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1615 }
1616 if (a->flush_depthstencil_through_cb) {
1617 assert(a->copy_depth || a->copy_stencil);
1618
1619 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1620 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1621 S_028D0C_COPY_CENTROID(1) |
1622 S_028D0C_COPY_SAMPLE(a->copy_sample);
1623
1624 if (rctx->b.chip_class == R600)
1625 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1626
1627 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
1628 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
1629 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1630 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1631 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1632 S_028D0C_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1633 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1634 }
1635 if (a->htile_clear) {
1636 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1637 }
1638
1639 /* RV770 workaround for a hang with 8x MSAA. */
1640 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1641 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
1642 }
1643
1644 radeon_set_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1645 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1646 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1647 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1648 }
1649
1650 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1651 {
1652 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1653 struct r600_config_state *a = (struct r600_config_state*)atom;
1654
1655 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1656 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1657 }
1658
1659 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1660 {
1661 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1662 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1663
1664 while (dirty_mask) {
1665 struct pipe_vertex_buffer *vb;
1666 struct r600_resource *rbuffer;
1667 unsigned offset;
1668 unsigned buffer_index = u_bit_scan(&dirty_mask);
1669
1670 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1671 rbuffer = (struct r600_resource*)vb->buffer.resource;
1672 assert(rbuffer);
1673
1674 offset = vb->buffer_offset;
1675
1676 /* fetch resources start at index 320 (OFFSET_FS) */
1677 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1678 radeon_emit(cs, (R600_FETCH_CONSTANTS_OFFSET_FS + buffer_index) * 7);
1679 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1680 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1681 radeon_emit(cs, /* RESOURCEi_WORD2 */
1682 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1683 S_038008_STRIDE(vb->stride));
1684 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1685 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1686 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1687 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1688
1689 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1690 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1691 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1692 }
1693 }
1694
1695 static void r600_emit_constant_buffers(struct r600_context *rctx,
1696 struct r600_constbuf_state *state,
1697 unsigned buffer_id_base,
1698 unsigned reg_alu_constbuf_size,
1699 unsigned reg_alu_const_cache)
1700 {
1701 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1702 uint32_t dirty_mask = state->dirty_mask;
1703
1704 while (dirty_mask) {
1705 struct pipe_constant_buffer *cb;
1706 struct r600_resource *rbuffer;
1707 unsigned offset;
1708 unsigned buffer_index = ffs(dirty_mask) - 1;
1709 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1710 cb = &state->cb[buffer_index];
1711 rbuffer = (struct r600_resource*)cb->buffer;
1712 assert(rbuffer);
1713
1714 offset = cb->buffer_offset;
1715
1716 if (!gs_ring_buffer) {
1717 assert(buffer_index < R600_MAX_HW_CONST_BUFFERS);
1718 radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1719 DIV_ROUND_UP(cb->buffer_size, 256));
1720 radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1721 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1722 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1723 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1724 }
1725
1726 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1727 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1728 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1729 radeon_emit(cs, cb->buffer_size - 1); /* RESOURCEi_WORD1 */
1730 radeon_emit(cs, /* RESOURCEi_WORD2 */
1731 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1732 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1733 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1734 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1735 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1736 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1737
1738 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1739 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1740 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1741
1742 dirty_mask &= ~(1 << buffer_index);
1743 }
1744 state->dirty_mask = 0;
1745 }
1746
1747 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1748 {
1749 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1750 R600_FETCH_CONSTANTS_OFFSET_VS,
1751 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1752 R_028980_ALU_CONST_CACHE_VS_0);
1753 }
1754
1755 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1756 {
1757 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1758 R600_FETCH_CONSTANTS_OFFSET_GS,
1759 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1760 R_0289C0_ALU_CONST_CACHE_GS_0);
1761 }
1762
1763 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1764 {
1765 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1766 R600_FETCH_CONSTANTS_OFFSET_PS,
1767 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1768 R_028940_ALU_CONST_CACHE_PS_0);
1769 }
1770
1771 static void r600_emit_sampler_views(struct r600_context *rctx,
1772 struct r600_samplerview_state *state,
1773 unsigned resource_id_base)
1774 {
1775 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1776 uint32_t dirty_mask = state->dirty_mask;
1777
1778 while (dirty_mask) {
1779 struct r600_pipe_sampler_view *rview;
1780 unsigned resource_index = u_bit_scan(&dirty_mask);
1781 unsigned reloc;
1782
1783 rview = state->views[resource_index];
1784 assert(rview);
1785
1786 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1787 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1788 radeon_emit_array(cs, rview->tex_resource_words, 7);
1789
1790 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
1791 RADEON_USAGE_READ,
1792 r600_get_sampler_view_priority(rview->tex_resource));
1793 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1794 radeon_emit(cs, reloc);
1795 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1796 radeon_emit(cs, reloc);
1797 }
1798 state->dirty_mask = 0;
1799 }
1800
1801
1802 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1803 {
1804 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, R600_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS);
1805 }
1806
1807 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1808 {
1809 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, R600_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS);
1810 }
1811
1812 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1813 {
1814 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS);
1815 }
1816
1817 static void r600_emit_sampler_states(struct r600_context *rctx,
1818 struct r600_textures_info *texinfo,
1819 unsigned resource_id_base,
1820 unsigned border_color_reg)
1821 {
1822 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1823 uint32_t dirty_mask = texinfo->states.dirty_mask;
1824
1825 while (dirty_mask) {
1826 struct r600_pipe_sampler_state *rstate;
1827 struct r600_pipe_sampler_view *rview;
1828 unsigned i = u_bit_scan(&dirty_mask);
1829
1830 rstate = texinfo->states.states[i];
1831 assert(rstate);
1832 rview = texinfo->views.views[i];
1833
1834 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1835 * filtering between layers.
1836 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1837 */
1838 if (rview) {
1839 enum pipe_texture_target target = rview->base.texture->target;
1840 if (target == PIPE_TEXTURE_1D_ARRAY ||
1841 target == PIPE_TEXTURE_2D_ARRAY) {
1842 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1843 texinfo->is_array_sampler[i] = true;
1844 } else {
1845 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1846 texinfo->is_array_sampler[i] = false;
1847 }
1848 }
1849
1850 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1851 radeon_emit(cs, (resource_id_base + i) * 3);
1852 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1853
1854 if (rstate->border_color_use) {
1855 unsigned offset;
1856
1857 offset = border_color_reg;
1858 offset += i * 16;
1859 radeon_set_config_reg_seq(cs, offset, 4);
1860 radeon_emit_array(cs, rstate->border_color.ui, 4);
1861 }
1862 }
1863 texinfo->states.dirty_mask = 0;
1864 }
1865
1866 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1867 {
1868 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1869 }
1870
1871 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1872 {
1873 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1874 }
1875
1876 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1877 {
1878 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1879 }
1880
1881 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1882 {
1883 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1884 unsigned tmp;
1885
1886 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1887 S_009508_SYNC_GRADIENT(1) |
1888 S_009508_SYNC_WALKER(1) |
1889 S_009508_SYNC_ALIGNER(1);
1890 if (!rctx->seamless_cube_map.enabled) {
1891 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1892 }
1893 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1894 }
1895
1896 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1897 {
1898 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1899 uint8_t mask = s->sample_mask;
1900
1901 radeon_set_context_reg(rctx->b.gfx.cs, R_028C48_PA_SC_AA_MASK,
1902 mask | (mask << 8) | (mask << 16) | (mask << 24));
1903 }
1904
1905 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1906 {
1907 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1908 struct r600_cso_state *state = (struct r600_cso_state*)a;
1909 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1910
1911 if (!shader)
1912 return;
1913
1914 radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1915 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1916 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
1917 RADEON_USAGE_READ,
1918 RADEON_PRIO_SHADER_BINARY));
1919 }
1920
1921 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1922 {
1923 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1924 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1925
1926 uint32_t v2 = 0, primid = 0;
1927
1928 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
1929 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1930 primid = 1;
1931 }
1932
1933 if (state->geom_enable) {
1934 uint32_t cut_val;
1935
1936 if (rctx->gs_shader->gs_max_out_vertices <= 128)
1937 cut_val = V_028A40_GS_CUT_128;
1938 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
1939 cut_val = V_028A40_GS_CUT_256;
1940 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
1941 cut_val = V_028A40_GS_CUT_512;
1942 else
1943 cut_val = V_028A40_GS_CUT_1024;
1944
1945 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1946 S_028A40_CUT_MODE(cut_val);
1947
1948 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1949 primid = 1;
1950 }
1951
1952 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1953 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
1954 }
1955
1956 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1957 {
1958 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1959 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
1960 struct r600_resource *rbuffer;
1961
1962 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1963 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1964 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1965
1966 if (state->enable) {
1967 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
1968 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
1969 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1970 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1971 RADEON_USAGE_READWRITE,
1972 RADEON_PRIO_SHADER_RINGS));
1973 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1974 state->esgs_ring.buffer_size >> 8);
1975
1976 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
1977 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
1978 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1979 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1980 RADEON_USAGE_READWRITE,
1981 RADEON_PRIO_SHADER_RINGS));
1982 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
1983 state->gsvs_ring.buffer_size >> 8);
1984 } else {
1985 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
1986 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
1987 }
1988
1989 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1990 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1991 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1992 }
1993
1994 /* Adjust GPR allocation on R6xx/R7xx */
1995 bool r600_adjust_gprs(struct r600_context *rctx)
1996 {
1997 unsigned num_gprs[R600_NUM_HW_STAGES];
1998 unsigned new_gprs[R600_NUM_HW_STAGES];
1999 unsigned cur_gprs[R600_NUM_HW_STAGES];
2000 unsigned def_gprs[R600_NUM_HW_STAGES];
2001 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2002 unsigned max_gprs;
2003 unsigned tmp, tmp2;
2004 unsigned i;
2005 bool need_recalc = false, use_default = true;
2006
2007 /* hardware will reserve twice num_clause_temp_gprs */
2008 max_gprs = def_num_clause_temp_gprs * 2;
2009 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2010 def_gprs[i] = rctx->default_gprs[i];
2011 max_gprs += def_gprs[i];
2012 }
2013
2014 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2015 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2016 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2017 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2018
2019 num_gprs[R600_HW_STAGE_PS] = rctx->ps_shader->current->shader.bc.ngpr;
2020 if (rctx->gs_shader) {
2021 num_gprs[R600_HW_STAGE_ES] = rctx->vs_shader->current->shader.bc.ngpr;
2022 num_gprs[R600_HW_STAGE_GS] = rctx->gs_shader->current->shader.bc.ngpr;
2023 num_gprs[R600_HW_STAGE_VS] = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2024 } else {
2025 num_gprs[R600_HW_STAGE_ES] = 0;
2026 num_gprs[R600_HW_STAGE_GS] = 0;
2027 num_gprs[R600_HW_STAGE_VS] = rctx->vs_shader->current->shader.bc.ngpr;
2028 }
2029
2030 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2031 new_gprs[i] = num_gprs[i];
2032 if (new_gprs[i] > cur_gprs[i])
2033 need_recalc = true;
2034 if (new_gprs[i] > def_gprs[i])
2035 use_default = false;
2036 }
2037
2038 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2039 if (!need_recalc)
2040 return true;
2041
2042 /* try to use switch back to default */
2043 if (!use_default) {
2044 /* always privilege vs stage so that at worst we have the
2045 * pixel stage producing wrong output (not the vertex
2046 * stage) */
2047 new_gprs[R600_HW_STAGE_PS] = max_gprs - def_num_clause_temp_gprs * 2;
2048 for (i = R600_HW_STAGE_VS; i < R600_NUM_HW_STAGES; i++)
2049 new_gprs[R600_HW_STAGE_PS] -= new_gprs[i];
2050 } else {
2051 for (i = 0; i < R600_NUM_HW_STAGES; i++)
2052 new_gprs[i] = def_gprs[i];
2053 }
2054
2055 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2056 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2057 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2058 * it will lockup. So in this case just discard the draw command
2059 * and don't change the current gprs repartitions.
2060 */
2061 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2062 if (num_gprs[i] > new_gprs[i]) {
2063 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2064 "for a combined maximum of %d\n",
2065 num_gprs[R600_HW_STAGE_PS], num_gprs[R600_HW_STAGE_VS], num_gprs[R600_HW_STAGE_ES], num_gprs[R600_HW_STAGE_GS], max_gprs);
2066 return false;
2067 }
2068 }
2069
2070 /* in some case we endup recomputing the current value */
2071 tmp = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
2072 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
2073 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2074
2075 tmp2 = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
2076 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
2077 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2078 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2079 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2080 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
2081 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2082 }
2083 return true;
2084 }
2085
2086 void r600_init_atom_start_cs(struct r600_context *rctx)
2087 {
2088 int ps_prio;
2089 int vs_prio;
2090 int gs_prio;
2091 int es_prio;
2092 int num_ps_gprs;
2093 int num_vs_gprs;
2094 int num_gs_gprs;
2095 int num_es_gprs;
2096 int num_temp_gprs;
2097 int num_ps_threads;
2098 int num_vs_threads;
2099 int num_gs_threads;
2100 int num_es_threads;
2101 int num_ps_stack_entries;
2102 int num_vs_stack_entries;
2103 int num_gs_stack_entries;
2104 int num_es_stack_entries;
2105 enum radeon_family family;
2106 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2107 uint32_t tmp, i;
2108
2109 r600_init_command_buffer(cb, 256);
2110
2111 /* R6xx requires this packet at the start of each command buffer */
2112 if (rctx->b.chip_class == R600) {
2113 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2114 r600_store_value(cb, 0);
2115 }
2116 /* All asics require this one */
2117 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2118 r600_store_value(cb, 0x80000000);
2119 r600_store_value(cb, 0x80000000);
2120
2121 /* We're setting config registers here. */
2122 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2123 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2124
2125 /* This enables pipeline stat & streamout queries.
2126 * They are only disabled by blits.
2127 */
2128 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2129 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2130
2131 family = rctx->b.family;
2132 ps_prio = 0;
2133 vs_prio = 1;
2134 gs_prio = 2;
2135 es_prio = 3;
2136 switch (family) {
2137 case CHIP_R600:
2138 num_ps_gprs = 192;
2139 num_vs_gprs = 56;
2140 num_temp_gprs = 4;
2141 num_gs_gprs = 0;
2142 num_es_gprs = 0;
2143 num_ps_threads = 136;
2144 num_vs_threads = 48;
2145 num_gs_threads = 4;
2146 num_es_threads = 4;
2147 num_ps_stack_entries = 128;
2148 num_vs_stack_entries = 128;
2149 num_gs_stack_entries = 0;
2150 num_es_stack_entries = 0;
2151 break;
2152 case CHIP_RV630:
2153 case CHIP_RV635:
2154 num_ps_gprs = 84;
2155 num_vs_gprs = 36;
2156 num_temp_gprs = 4;
2157 num_gs_gprs = 0;
2158 num_es_gprs = 0;
2159 num_ps_threads = 144;
2160 num_vs_threads = 40;
2161 num_gs_threads = 4;
2162 num_es_threads = 4;
2163 num_ps_stack_entries = 40;
2164 num_vs_stack_entries = 40;
2165 num_gs_stack_entries = 32;
2166 num_es_stack_entries = 16;
2167 break;
2168 case CHIP_RV610:
2169 case CHIP_RV620:
2170 case CHIP_RS780:
2171 case CHIP_RS880:
2172 default:
2173 num_ps_gprs = 84;
2174 num_vs_gprs = 36;
2175 num_temp_gprs = 4;
2176 num_gs_gprs = 0;
2177 num_es_gprs = 0;
2178 /* use limits 40 VS and at least 16 ES/GS */
2179 num_ps_threads = 120;
2180 num_vs_threads = 40;
2181 num_gs_threads = 16;
2182 num_es_threads = 16;
2183 num_ps_stack_entries = 40;
2184 num_vs_stack_entries = 40;
2185 num_gs_stack_entries = 32;
2186 num_es_stack_entries = 16;
2187 break;
2188 case CHIP_RV670:
2189 num_ps_gprs = 144;
2190 num_vs_gprs = 40;
2191 num_temp_gprs = 4;
2192 num_gs_gprs = 0;
2193 num_es_gprs = 0;
2194 num_ps_threads = 136;
2195 num_vs_threads = 48;
2196 num_gs_threads = 4;
2197 num_es_threads = 4;
2198 num_ps_stack_entries = 40;
2199 num_vs_stack_entries = 40;
2200 num_gs_stack_entries = 32;
2201 num_es_stack_entries = 16;
2202 break;
2203 case CHIP_RV770:
2204 num_ps_gprs = 130;
2205 num_vs_gprs = 56;
2206 num_temp_gprs = 4;
2207 num_gs_gprs = 31;
2208 num_es_gprs = 31;
2209 num_ps_threads = 180;
2210 num_vs_threads = 60;
2211 num_gs_threads = 4;
2212 num_es_threads = 4;
2213 num_ps_stack_entries = 128;
2214 num_vs_stack_entries = 128;
2215 num_gs_stack_entries = 128;
2216 num_es_stack_entries = 128;
2217 break;
2218 case CHIP_RV730:
2219 case CHIP_RV740:
2220 num_ps_gprs = 84;
2221 num_vs_gprs = 36;
2222 num_temp_gprs = 4;
2223 num_gs_gprs = 0;
2224 num_es_gprs = 0;
2225 num_ps_threads = 180;
2226 num_vs_threads = 60;
2227 num_gs_threads = 4;
2228 num_es_threads = 4;
2229 num_ps_stack_entries = 128;
2230 num_vs_stack_entries = 128;
2231 num_gs_stack_entries = 0;
2232 num_es_stack_entries = 0;
2233 break;
2234 case CHIP_RV710:
2235 num_ps_gprs = 192;
2236 num_vs_gprs = 56;
2237 num_temp_gprs = 4;
2238 num_gs_gprs = 0;
2239 num_es_gprs = 0;
2240 num_ps_threads = 136;
2241 num_vs_threads = 48;
2242 num_gs_threads = 4;
2243 num_es_threads = 4;
2244 num_ps_stack_entries = 128;
2245 num_vs_stack_entries = 128;
2246 num_gs_stack_entries = 0;
2247 num_es_stack_entries = 0;
2248 break;
2249 }
2250
2251 rctx->default_gprs[R600_HW_STAGE_PS] = num_ps_gprs;
2252 rctx->default_gprs[R600_HW_STAGE_VS] = num_vs_gprs;
2253 rctx->default_gprs[R600_HW_STAGE_GS] = 0;
2254 rctx->default_gprs[R600_HW_STAGE_ES] = 0;
2255
2256 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2257
2258 /* SQ_CONFIG */
2259 tmp = 0;
2260 switch (family) {
2261 case CHIP_RV610:
2262 case CHIP_RV620:
2263 case CHIP_RS780:
2264 case CHIP_RS880:
2265 case CHIP_RV710:
2266 break;
2267 default:
2268 tmp |= S_008C00_VC_ENABLE(1);
2269 break;
2270 }
2271 tmp |= S_008C00_DX9_CONSTS(0);
2272 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2273 tmp |= S_008C00_PS_PRIO(ps_prio);
2274 tmp |= S_008C00_VS_PRIO(vs_prio);
2275 tmp |= S_008C00_GS_PRIO(gs_prio);
2276 tmp |= S_008C00_ES_PRIO(es_prio);
2277 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2278
2279 /* SQ_GPR_RESOURCE_MGMT_2 */
2280 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2281 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2282 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2283 r600_store_value(cb, tmp);
2284
2285 /* SQ_THREAD_RESOURCE_MGMT */
2286 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2287 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2288 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2289 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2290 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2291
2292 /* SQ_STACK_RESOURCE_MGMT_1 */
2293 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2294 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2295 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2296
2297 /* SQ_STACK_RESOURCE_MGMT_2 */
2298 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2299 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2300 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2301
2302 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2303
2304 if (rctx->b.chip_class >= R700) {
2305 r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4);
2306 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2307 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2308 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2309 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2310 } else {
2311 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2312 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2313 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2314 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2315 }
2316 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2317 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2318 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2319 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2320 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2321 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2322 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2323 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2324 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2325 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2326
2327 /* to avoid GPU doing any preloading of constant from random address */
2328 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2329 for (i = 0; i < 16; i++)
2330 r600_store_value(cb, 0);
2331
2332 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2333 for (i = 0; i < 16; i++)
2334 r600_store_value(cb, 0);
2335
2336 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2337 for (i = 0; i < 16; i++)
2338 r600_store_value(cb, 0);
2339
2340 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2341 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2342 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2343 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2344 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2345 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2346 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2347 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2348 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2349 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2350 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2351 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2352 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2353 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2354
2355 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2356 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2357 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2358
2359 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2360 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2361 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2362
2363 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2364
2365 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2366
2367 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2368
2369 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2370 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2371 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2372 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2373
2374 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2375 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2376 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2377 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2378
2379 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2380 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2381
2382 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2383 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2384
2385 if (rctx->b.chip_class >= R700) {
2386 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2387 }
2388
2389 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2390 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2391 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2392 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2393 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2394
2395 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2396 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2397 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2398
2399 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2400 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2401 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2402
2403 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2404 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2405 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2406 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2407 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2408 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2409
2410 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2411
2412 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2413 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2414 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2415
2416 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2417
2418 if (rctx->b.chip_class == R700)
2419 r600_store_context_reg(cb, R_028350_SX_MISC, 0);
2420 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2421 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2422
2423 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2424 if (rctx->screen->b.has_streamout) {
2425 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2426 }
2427
2428 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2429 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2430 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2431 }
2432
2433 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2434 {
2435 struct r600_context *rctx = (struct r600_context *)ctx;
2436 struct r600_command_buffer *cb = &shader->command_buffer;
2437 struct r600_shader *rshader = &shader->shader;
2438 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2439 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2440 unsigned tmp, sid, ufi = 0;
2441 int need_linear = 0;
2442 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2443 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2444
2445 if (!cb->buf) {
2446 r600_init_command_buffer(cb, 64);
2447 } else {
2448 cb->num_dw = 0;
2449 }
2450
2451 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2452 for (i = 0; i < rshader->ninput; i++) {
2453 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2454 pos_index = i;
2455 if (rshader->input[i].name == TGSI_SEMANTIC_FACE && face_index == -1)
2456 face_index = i;
2457 if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID)
2458 fixed_pt_position_index = i;
2459
2460 sid = rshader->input[i].spi_sid;
2461
2462 tmp = S_028644_SEMANTIC(sid);
2463
2464 /* D3D 9 behaviour. GL is undefined */
2465 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
2466 tmp |= S_028644_DEFAULT_VAL(3);
2467
2468 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2469 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2470 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2471 rctx->rasterizer && rctx->rasterizer->flatshade))
2472 tmp |= S_028644_FLAT_SHADE(1);
2473
2474 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2475 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2476 tmp |= S_028644_PT_SPRITE_TEX(1);
2477 }
2478
2479 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID)
2480 tmp |= S_028644_SEL_CENTROID(1);
2481
2482 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE)
2483 tmp |= S_028644_SEL_SAMPLE(1);
2484
2485 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2486 need_linear = 1;
2487 tmp |= S_028644_SEL_LINEAR(1);
2488 }
2489
2490 r600_store_value(cb, tmp);
2491 }
2492
2493 db_shader_control = 0;
2494 for (i = 0; i < rshader->noutput; i++) {
2495 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2496 z_export = 1;
2497 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2498 stencil_export = 1;
2499 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
2500 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
2501 mask_export = 1;
2502 }
2503 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2504 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2505 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
2506 if (rshader->uses_kill)
2507 db_shader_control |= S_02880C_KILL_ENABLE(1);
2508
2509 exports_ps = 0;
2510 for (i = 0; i < rshader->noutput; i++) {
2511 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2512 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
2513 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2514 exports_ps |= 1;
2515 }
2516 }
2517 num_cout = rshader->nr_ps_color_exports;
2518 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2519 if (!exports_ps) {
2520 /* always at least export 1 component per pixel */
2521 exports_ps = 2;
2522 }
2523
2524 shader->nr_ps_color_outputs = num_cout;
2525 shader->ps_color_export_mask = rshader->ps_color_export_mask;
2526
2527 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2528 S_0286CC_PERSP_GRADIENT_ENA(1)|
2529 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2530 spi_input_z = 0;
2531 if (pos_index != -1) {
2532 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2533 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
2534 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2535 S_0286CC_BARYC_SAMPLE_CNTL(1)) |
2536 S_0286CC_POSITION_SAMPLE(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE);
2537 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2538 }
2539
2540 spi_ps_in_control_1 = 0;
2541 if (face_index != -1) {
2542 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2543 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2544 }
2545 if (fixed_pt_position_index != -1) {
2546 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2547 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
2548 }
2549
2550 /* HW bug in original R600 */
2551 if (rctx->b.family == CHIP_R600)
2552 ufi = 1;
2553
2554 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2555 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2556 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2557
2558 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2559
2560 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2561 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2562 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2563 /*
2564 * docs are misleading about the dx10_clamp bit. This only affects
2565 * instructions using CLAMP dst modifier, in which case they will
2566 * return 0 with this set for a NaN (otherwise NaN).
2567 */
2568 S_028850_DX10_CLAMP(1) |
2569 S_028850_STACK_SIZE(rshader->bc.nstack) |
2570 S_028850_UNCACHED_FIRST_INST(ufi));
2571 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2572
2573 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2574 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2575
2576 /* only set some bits here, the other bits are set in the dsa state */
2577 shader->db_shader_control = db_shader_control;
2578 shader->ps_depth_export = z_export | stencil_export | mask_export;
2579
2580 shader->sprite_coord_enable = sprite_coord_enable;
2581 if (rctx->rasterizer)
2582 shader->flatshade = rctx->rasterizer->flatshade;
2583 }
2584
2585 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2586 {
2587 struct r600_command_buffer *cb = &shader->command_buffer;
2588 struct r600_shader *rshader = &shader->shader;
2589 unsigned spi_vs_out_id[10] = {};
2590 unsigned i, tmp, nparams = 0;
2591
2592 for (i = 0; i < rshader->noutput; i++) {
2593 if (rshader->output[i].spi_sid) {
2594 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2595 spi_vs_out_id[nparams / 4] |= tmp;
2596 nparams++;
2597 }
2598 }
2599
2600 r600_init_command_buffer(cb, 32);
2601
2602 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2603 for (i = 0; i < 10; i++) {
2604 r600_store_value(cb, spi_vs_out_id[i]);
2605 }
2606
2607 /* Certain attributes (position, psize, etc.) don't count as params.
2608 * VS is required to export at least one param and r600_shader_from_tgsi()
2609 * takes care of adding a dummy export.
2610 */
2611 if (nparams < 1)
2612 nparams = 1;
2613
2614 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2615 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2616 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2617 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2618 S_028868_DX10_CLAMP(1) |
2619 S_028868_STACK_SIZE(rshader->bc.nstack));
2620 if (rshader->vs_position_window_space) {
2621 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2622 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2623 } else {
2624 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2625 S_028818_VTX_W0_FMT(1) |
2626 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2627 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2628 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2629
2630 }
2631 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2632 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2633
2634 shader->pa_cl_vs_out_cntl =
2635 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2636 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2637 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2638 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2639 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2640 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2641 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2642 }
2643
2644 #define RV610_GSVS_ALIGN 32
2645 #define R600_GSVS_ALIGN 16
2646
2647 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2648 {
2649 struct r600_context *rctx = (struct r600_context *)ctx;
2650 struct r600_command_buffer *cb = &shader->command_buffer;
2651 struct r600_shader *rshader = &shader->shader;
2652 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2653 unsigned gsvs_itemsize =
2654 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2;
2655
2656 /* some r600s needs gsvs itemsize aligned to cacheline size
2657 this was fixed in rs780 and above. */
2658 switch (rctx->b.family) {
2659 case CHIP_RV610:
2660 gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN);
2661 break;
2662 case CHIP_R600:
2663 case CHIP_RV630:
2664 case CHIP_RV670:
2665 case CHIP_RV620:
2666 case CHIP_RV635:
2667 gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN);
2668 break;
2669 default:
2670 break;
2671 }
2672
2673 r600_init_command_buffer(cb, 64);
2674
2675 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2676 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2677
2678 if (rctx->b.chip_class >= R700) {
2679 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2680 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
2681 }
2682 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2683 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
2684
2685 r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE,
2686 cp_shader->ring_item_sizes[0] >> 2);
2687
2688 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2689 (rshader->ring_item_sizes[0]) >> 2);
2690
2691 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2692 gsvs_itemsize);
2693
2694 /* FIXME calculate these values somehow ??? */
2695 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2696 r600_store_value(cb, 0x80); /* GS_PER_ES */
2697 r600_store_value(cb, 0x100); /* ES_PER_GS */
2698 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2699 r600_store_value(cb, 0x2); /* GS_PER_VS */
2700
2701 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2702 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2703 S_02887C_DX10_CLAMP(1) |
2704 S_02887C_STACK_SIZE(rshader->bc.nstack));
2705 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0);
2706 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2707 }
2708
2709 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2710 {
2711 struct r600_command_buffer *cb = &shader->command_buffer;
2712 struct r600_shader *rshader = &shader->shader;
2713
2714 r600_init_command_buffer(cb, 32);
2715
2716 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2717 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2718 S_028890_DX10_CLAMP(1) |
2719 S_028890_STACK_SIZE(rshader->bc.nstack));
2720 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0);
2721 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2722 }
2723
2724
2725 void *r600_create_resolve_blend(struct r600_context *rctx)
2726 {
2727 struct pipe_blend_state blend;
2728 unsigned i;
2729
2730 memset(&blend, 0, sizeof(blend));
2731 blend.independent_blend_enable = true;
2732 for (i = 0; i < 2; i++) {
2733 blend.rt[i].colormask = 0xf;
2734 blend.rt[i].blend_enable = 1;
2735 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2736 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2737 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2738 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2739 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2740 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2741 }
2742 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2743 }
2744
2745 void *r700_create_resolve_blend(struct r600_context *rctx)
2746 {
2747 struct pipe_blend_state blend;
2748
2749 memset(&blend, 0, sizeof(blend));
2750 blend.independent_blend_enable = true;
2751 blend.rt[0].colormask = 0xf;
2752 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2753 }
2754
2755 void *r600_create_decompress_blend(struct r600_context *rctx)
2756 {
2757 struct pipe_blend_state blend;
2758
2759 memset(&blend, 0, sizeof(blend));
2760 blend.independent_blend_enable = true;
2761 blend.rt[0].colormask = 0xf;
2762 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2763 }
2764
2765 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2766 {
2767 struct pipe_depth_stencil_alpha_state dsa;
2768 boolean quirk = false;
2769
2770 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2771 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2772 quirk = true;
2773
2774 memset(&dsa, 0, sizeof(dsa));
2775
2776 if (quirk) {
2777 dsa.depth.enabled = 1;
2778 dsa.depth.func = PIPE_FUNC_LEQUAL;
2779 dsa.stencil[0].enabled = 1;
2780 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2781 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2782 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2783 dsa.stencil[0].writemask = 0xff;
2784 }
2785
2786 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2787 }
2788
2789 void r600_update_db_shader_control(struct r600_context * rctx)
2790 {
2791 bool dual_export;
2792 unsigned db_shader_control;
2793 uint8_t ps_conservative_z;
2794
2795 if (!rctx->ps_shader) {
2796 return;
2797 }
2798
2799 dual_export = rctx->framebuffer.export_16bpc &&
2800 !rctx->ps_shader->current->ps_depth_export;
2801
2802 db_shader_control = rctx->ps_shader->current->db_shader_control |
2803 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2804
2805 ps_conservative_z = rctx->ps_shader->current->shader.ps_conservative_z;
2806
2807 /* When alpha test is enabled we can't trust the hw to make the proper
2808 * decision on the order in which ztest should be run related to fragment
2809 * shader execution.
2810 *
2811 * If alpha test is enabled perform z test after fragment. RE_Z (early
2812 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2813 */
2814 if (rctx->alphatest_state.sx_alpha_test_control) {
2815 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2816 } else {
2817 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2818 }
2819
2820 if (db_shader_control != rctx->db_misc_state.db_shader_control ||
2821 ps_conservative_z != rctx->db_misc_state.ps_conservative_z) {
2822 rctx->db_misc_state.db_shader_control = db_shader_control;
2823 rctx->db_misc_state.ps_conservative_z = ps_conservative_z;
2824 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2825 }
2826 }
2827
2828 static inline unsigned r600_array_mode(unsigned mode)
2829 {
2830 switch (mode) {
2831 default:
2832 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2833 break;
2834 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2835 break;
2836 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2837 }
2838 }
2839
2840 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2841 struct pipe_resource *dst,
2842 unsigned dst_level,
2843 unsigned dst_x,
2844 unsigned dst_y,
2845 unsigned dst_z,
2846 struct pipe_resource *src,
2847 unsigned src_level,
2848 unsigned src_x,
2849 unsigned src_y,
2850 unsigned src_z,
2851 unsigned copy_height,
2852 unsigned pitch,
2853 unsigned bpp)
2854 {
2855 struct radeon_cmdbuf *cs = rctx->b.dma.cs;
2856 struct r600_texture *rsrc = (struct r600_texture*)src;
2857 struct r600_texture *rdst = (struct r600_texture*)dst;
2858 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2859 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2860 uint64_t base, addr;
2861
2862 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
2863 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
2864 assert(dst_mode != src_mode);
2865
2866 y = 0;
2867 lbpp = util_logbase2(bpp);
2868 pitch_tile_max = ((pitch / bpp) / 8) - 1;
2869
2870 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
2871 /* T2L */
2872 array_mode = r600_array_mode(src_mode);
2873 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
2874 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2875 /* linear height must be the same as the slice tile max height, it's ok even
2876 * if the linear destination/source have smaller heigh as the size of the
2877 * dma packet will be using the copy_height which is always smaller or equal
2878 * to the linear height
2879 */
2880 height = u_minify(rsrc->resource.b.b.height0, src_level);
2881 detile = 1;
2882 x = src_x;
2883 y = src_y;
2884 z = src_z;
2885 base = rsrc->surface.u.legacy.level[src_level].offset;
2886 addr = rdst->surface.u.legacy.level[dst_level].offset;
2887 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
2888 addr += dst_y * pitch + dst_x * bpp;
2889 } else {
2890 /* L2T */
2891 array_mode = r600_array_mode(dst_mode);
2892 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
2893 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2894 /* linear height must be the same as the slice tile max height, it's ok even
2895 * if the linear destination/source have smaller heigh as the size of the
2896 * dma packet will be using the copy_height which is always smaller or equal
2897 * to the linear height
2898 */
2899 height = u_minify(rdst->resource.b.b.height0, dst_level);
2900 detile = 0;
2901 x = dst_x;
2902 y = dst_y;
2903 z = dst_z;
2904 base = rdst->surface.u.legacy.level[dst_level].offset;
2905 addr = rsrc->surface.u.legacy.level[src_level].offset;
2906 addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z;
2907 addr += src_y * pitch + src_x * bpp;
2908 }
2909 /* check that we are in dw/base alignment constraint */
2910 if (addr % 4 || base % 256) {
2911 return FALSE;
2912 }
2913
2914 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2915 * line in the blit. Compute max 8 line we can copy in the size limit
2916 */
2917 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2918 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2919 r600_need_dma_space(&rctx->b, ncopy * 7, &rdst->resource, &rsrc->resource);
2920
2921 for (i = 0; i < ncopy; i++) {
2922 cheight = cheight > copy_height ? copy_height : cheight;
2923 size = (cheight * pitch) / 4;
2924 /* emit reloc before writing cs so that cs is always in consistent state */
2925 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ,
2926 RADEON_PRIO_SDMA_TEXTURE);
2927 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE,
2928 RADEON_PRIO_SDMA_TEXTURE);
2929 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, 1, 0, size));
2930 radeon_emit(cs, base >> 8);
2931 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
2932 (lbpp << 24) | ((height - 1) << 10) |
2933 pitch_tile_max);
2934 radeon_emit(cs, (slice_tile_max << 12) | (z << 0));
2935 radeon_emit(cs, (x << 3) | (y << 17));
2936 radeon_emit(cs, addr & 0xfffffffc);
2937 radeon_emit(cs, (addr >> 32UL) & 0xff);
2938 copy_height -= cheight;
2939 addr += cheight * pitch;
2940 y += cheight;
2941 }
2942 return TRUE;
2943 }
2944
2945 static void r600_dma_copy(struct pipe_context *ctx,
2946 struct pipe_resource *dst,
2947 unsigned dst_level,
2948 unsigned dstx, unsigned dsty, unsigned dstz,
2949 struct pipe_resource *src,
2950 unsigned src_level,
2951 const struct pipe_box *src_box)
2952 {
2953 struct r600_context *rctx = (struct r600_context *)ctx;
2954 struct r600_texture *rsrc = (struct r600_texture*)src;
2955 struct r600_texture *rdst = (struct r600_texture*)dst;
2956 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2957 unsigned src_w, dst_w;
2958 unsigned src_x, src_y;
2959 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
2960
2961 if (rctx->b.dma.cs == NULL) {
2962 goto fallback;
2963 }
2964
2965 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
2966 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
2967 goto fallback;
2968
2969 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
2970 return;
2971 }
2972
2973 if (src_box->depth > 1 ||
2974 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
2975 dstz, rsrc, src_level, src_box))
2976 goto fallback;
2977
2978 src_x = util_format_get_nblocksx(src->format, src_box->x);
2979 dst_x = util_format_get_nblocksx(src->format, dst_x);
2980 src_y = util_format_get_nblocksy(src->format, src_box->y);
2981 dst_y = util_format_get_nblocksy(src->format, dst_y);
2982
2983 bpp = rdst->surface.bpe;
2984 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
2985 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
2986 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
2987 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
2988 copy_height = src_box->height / rsrc->surface.blk_h;
2989
2990 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
2991 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
2992
2993 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
2994 /* strict requirement on r6xx/r7xx */
2995 goto fallback;
2996 }
2997 /* lot of constraint on alignment this should capture them all */
2998 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
2999 goto fallback;
3000 }
3001
3002 if (src_mode == dst_mode) {
3003 uint64_t dst_offset, src_offset, size;
3004
3005 /* simple dma blit would do NOTE code here assume :
3006 * src_box.x/y == 0
3007 * dst_x/y == 0
3008 * dst_pitch == src_pitch
3009 */
3010 src_offset= rsrc->surface.u.legacy.level[src_level].offset;
3011 src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
3012 src_offset += src_y * src_pitch + src_x * bpp;
3013 dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
3014 dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3015 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3016 size = src_box->height * src_pitch;
3017 /* must be dw aligned */
3018 if (dst_offset % 4 || src_offset % 4 || size % 4) {
3019 goto fallback;
3020 }
3021 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
3022 } else {
3023 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3024 src, src_level, src_x, src_y, src_box->z,
3025 copy_height, dst_pitch, bpp)) {
3026 goto fallback;
3027 }
3028 }
3029 return;
3030
3031 fallback:
3032 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3033 src, src_level, src_box);
3034 }
3035
3036 void r600_init_state_functions(struct r600_context *rctx)
3037 {
3038 unsigned id = 1;
3039 unsigned i;
3040 /* !!!
3041 * To avoid GPU lockup registers must be emited in a specific order
3042 * (no kidding ...). The order below is important and have been
3043 * partialy infered from analyzing fglrx command stream.
3044 *
3045 * Don't reorder atom without carefully checking the effect (GPU lockup
3046 * or piglit regression).
3047 * !!!
3048 */
3049
3050 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3051
3052 /* shader const */
3053 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3054 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3055 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3056
3057 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3058 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3059 */
3060 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3061 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3062 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3063 /* resource */
3064 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3065 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3066 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3067 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3068
3069 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3070
3071 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3072 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3073 rctx->sample_mask.sample_mask = ~0;
3074
3075 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3076 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3077 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3078 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3079 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3080 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3081 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3082 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3083 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3084 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 9);
3085 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3086 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3087 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3088 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3089 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3090 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3091 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3092 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3093 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3094 for (i = 0; i < R600_NUM_HW_STAGES; i++)
3095 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3096 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3097 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3098
3099 rctx->b.b.create_blend_state = r600_create_blend_state;
3100 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3101 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3102 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3103 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3104 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3105 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3106 rctx->b.b.set_min_samples = r600_set_min_samples;
3107 rctx->b.b.get_sample_position = r600_get_sample_position;
3108 rctx->b.dma_copy = r600_dma_copy;
3109 }
3110 /* this function must be last */