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gallium/radeon: don't do (fmask.size && cmask.size)
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
145 {
146 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
147 FALSE) != ~0U;
148 }
149
150 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
151 {
152 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
153 r600_translate_colorswap(format, FALSE) != ~0U;
154 }
155
156 static bool r600_is_zs_format_supported(enum pipe_format format)
157 {
158 return r600_translate_dbformat(format) != ~0U;
159 }
160
161 boolean r600_is_format_supported(struct pipe_screen *screen,
162 enum pipe_format format,
163 enum pipe_texture_target target,
164 unsigned sample_count,
165 unsigned usage)
166 {
167 struct r600_screen *rscreen = (struct r600_screen*)screen;
168 unsigned retval = 0;
169
170 if (target >= PIPE_MAX_TEXTURE_TYPES) {
171 R600_ERR("r600: unsupported texture type %d\n", target);
172 return FALSE;
173 }
174
175 if (!util_format_is_supported(format, usage))
176 return FALSE;
177
178 if (sample_count > 1) {
179 if (!rscreen->has_msaa)
180 return FALSE;
181
182 /* R11G11B10 is broken on R6xx. */
183 if (rscreen->b.chip_class == R600 &&
184 format == PIPE_FORMAT_R11G11B10_FLOAT)
185 return FALSE;
186
187 /* MSAA integer colorbuffers hang. */
188 if (util_format_is_pure_integer(format) &&
189 !util_format_is_depth_or_stencil(format))
190 return FALSE;
191
192 switch (sample_count) {
193 case 2:
194 case 4:
195 case 8:
196 break;
197 default:
198 return FALSE;
199 }
200 }
201
202 if (usage & PIPE_BIND_SAMPLER_VIEW) {
203 if (target == PIPE_BUFFER) {
204 if (r600_is_vertex_format_supported(format))
205 retval |= PIPE_BIND_SAMPLER_VIEW;
206 } else {
207 if (r600_is_sampler_format_supported(screen, format))
208 retval |= PIPE_BIND_SAMPLER_VIEW;
209 }
210 }
211
212 if ((usage & (PIPE_BIND_RENDER_TARGET |
213 PIPE_BIND_DISPLAY_TARGET |
214 PIPE_BIND_SCANOUT |
215 PIPE_BIND_SHARED |
216 PIPE_BIND_BLENDABLE)) &&
217 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
218 retval |= usage &
219 (PIPE_BIND_RENDER_TARGET |
220 PIPE_BIND_DISPLAY_TARGET |
221 PIPE_BIND_SCANOUT |
222 PIPE_BIND_SHARED);
223 if (!util_format_is_pure_integer(format) &&
224 !util_format_is_depth_or_stencil(format))
225 retval |= usage & PIPE_BIND_BLENDABLE;
226 }
227
228 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
229 r600_is_zs_format_supported(format)) {
230 retval |= PIPE_BIND_DEPTH_STENCIL;
231 }
232
233 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
234 r600_is_vertex_format_supported(format)) {
235 retval |= PIPE_BIND_VERTEX_BUFFER;
236 }
237
238 if ((usage & PIPE_BIND_LINEAR) &&
239 !util_format_is_compressed(format) &&
240 !(usage & PIPE_BIND_DEPTH_STENCIL))
241 retval |= PIPE_BIND_LINEAR;
242
243 return retval == usage;
244 }
245
246 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
247 {
248 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
249 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
250 float offset_units = state->offset_units;
251 float offset_scale = state->offset_scale;
252 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
253
254 if (!state->offset_units_unscaled) {
255 switch (state->zs_format) {
256 case PIPE_FORMAT_Z24X8_UNORM:
257 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
258 offset_units *= 2.0f;
259 pa_su_poly_offset_db_fmt_cntl =
260 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
261 break;
262 case PIPE_FORMAT_Z16_UNORM:
263 offset_units *= 4.0f;
264 pa_su_poly_offset_db_fmt_cntl =
265 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
266 break;
267 default:
268 pa_su_poly_offset_db_fmt_cntl =
269 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
270 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
271 }
272 }
273
274 radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
275 radeon_emit(cs, fui(offset_scale));
276 radeon_emit(cs, fui(offset_units));
277 radeon_emit(cs, fui(offset_scale));
278 radeon_emit(cs, fui(offset_units));
279
280 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
281 pa_su_poly_offset_db_fmt_cntl);
282 }
283
284 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
285 {
286 int j = state->independent_blend_enable ? i : 0;
287
288 unsigned eqRGB = state->rt[j].rgb_func;
289 unsigned srcRGB = state->rt[j].rgb_src_factor;
290 unsigned dstRGB = state->rt[j].rgb_dst_factor;
291
292 unsigned eqA = state->rt[j].alpha_func;
293 unsigned srcA = state->rt[j].alpha_src_factor;
294 unsigned dstA = state->rt[j].alpha_dst_factor;
295 uint32_t bc = 0;
296
297 if (!state->rt[j].blend_enable)
298 return 0;
299
300 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
301 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
302 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
303
304 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
305 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
306 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
307 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
308 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
309 }
310 return bc;
311 }
312
313 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
314 const struct pipe_blend_state *state,
315 int mode)
316 {
317 struct r600_context *rctx = (struct r600_context *)ctx;
318 uint32_t color_control = 0, target_mask = 0;
319 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
320
321 if (!blend) {
322 return NULL;
323 }
324
325 r600_init_command_buffer(&blend->buffer, 20);
326 r600_init_command_buffer(&blend->buffer_no_blend, 20);
327
328 /* R600 does not support per-MRT blends */
329 if (rctx->b.family > CHIP_R600)
330 color_control |= S_028808_PER_MRT_BLEND(1);
331
332 if (state->logicop_enable) {
333 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
334 } else {
335 color_control |= (0xcc << 16);
336 }
337 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
338 if (state->independent_blend_enable) {
339 for (int i = 0; i < 8; i++) {
340 if (state->rt[i].blend_enable) {
341 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
342 }
343 target_mask |= (state->rt[i].colormask << (4 * i));
344 }
345 } else {
346 for (int i = 0; i < 8; i++) {
347 if (state->rt[0].blend_enable) {
348 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
349 }
350 target_mask |= (state->rt[0].colormask << (4 * i));
351 }
352 }
353
354 if (target_mask)
355 color_control |= S_028808_SPECIAL_OP(mode);
356 else
357 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
358
359 /* only MRT0 has dual src blend */
360 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
361 blend->cb_target_mask = target_mask;
362 blend->cb_color_control = color_control;
363 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
364 blend->alpha_to_one = state->alpha_to_one;
365
366 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
367 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
368 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
369 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
370 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
371 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
372
373 /* Copy over the registers set so far into buffer_no_blend. */
374 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
375 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
376
377 /* Only add blend registers if blending is enabled. */
378 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
379 return blend;
380 }
381
382 /* The first R600 does not support per-MRT blends */
383 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
384 r600_get_blend_control(state, 0));
385
386 if (rctx->b.family > CHIP_R600) {
387 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
388 for (int i = 0; i < 8; i++) {
389 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
390 }
391 }
392 return blend;
393 }
394
395 static void *r600_create_blend_state(struct pipe_context *ctx,
396 const struct pipe_blend_state *state)
397 {
398 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
399 }
400
401 static void *r600_create_dsa_state(struct pipe_context *ctx,
402 const struct pipe_depth_stencil_alpha_state *state)
403 {
404 unsigned db_depth_control, alpha_test_control, alpha_ref;
405 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
406
407 if (!dsa) {
408 return NULL;
409 }
410
411 r600_init_command_buffer(&dsa->buffer, 3);
412
413 dsa->valuemask[0] = state->stencil[0].valuemask;
414 dsa->valuemask[1] = state->stencil[1].valuemask;
415 dsa->writemask[0] = state->stencil[0].writemask;
416 dsa->writemask[1] = state->stencil[1].writemask;
417 dsa->zwritemask = state->depth.writemask;
418
419 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
420 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
421 S_028800_ZFUNC(state->depth.func);
422
423 /* stencil */
424 if (state->stencil[0].enabled) {
425 db_depth_control |= S_028800_STENCIL_ENABLE(1);
426 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
427 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
428 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
429 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
430
431 if (state->stencil[1].enabled) {
432 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
433 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
434 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
435 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
436 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
437 }
438 }
439
440 /* alpha */
441 alpha_test_control = 0;
442 alpha_ref = 0;
443 if (state->alpha.enabled) {
444 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
445 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
446 alpha_ref = fui(state->alpha.ref_value);
447 }
448 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
449 dsa->alpha_ref = alpha_ref;
450
451 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
452 return dsa;
453 }
454
455 static void *r600_create_rs_state(struct pipe_context *ctx,
456 const struct pipe_rasterizer_state *state)
457 {
458 struct r600_context *rctx = (struct r600_context *)ctx;
459 unsigned tmp, sc_mode_cntl, spi_interp;
460 float psize_min, psize_max;
461 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
462
463 if (!rs) {
464 return NULL;
465 }
466
467 r600_init_command_buffer(&rs->buffer, 30);
468
469 rs->scissor_enable = state->scissor;
470 rs->clip_halfz = state->clip_halfz;
471 rs->flatshade = state->flatshade;
472 rs->sprite_coord_enable = state->sprite_coord_enable;
473 rs->two_side = state->light_twoside;
474 rs->clip_plane_enable = state->clip_plane_enable;
475 rs->pa_sc_line_stipple = state->line_stipple_enable ?
476 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
477 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
478 rs->pa_cl_clip_cntl =
479 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
480 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
481 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
482 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
483 if (rctx->b.chip_class == R700) {
484 rs->pa_cl_clip_cntl |=
485 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
486 }
487 rs->multisample_enable = state->multisample;
488
489 /* offset */
490 rs->offset_units = state->offset_units;
491 rs->offset_scale = state->offset_scale * 16.0f;
492 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
493 rs->offset_units_unscaled = state->offset_units_unscaled;
494
495 if (state->point_size_per_vertex) {
496 psize_min = util_get_min_point_size(state);
497 psize_max = 8192;
498 } else {
499 /* Force the point size to be as if the vertex output was disabled. */
500 psize_min = state->point_size;
501 psize_max = state->point_size;
502 }
503
504 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
505 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
506 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
507 S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1);
508 if (rctx->b.family == CHIP_RV770) {
509 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */
510 sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1);
511 }
512 if (rctx->b.chip_class >= R700) {
513 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
514 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
515 S_028A4C_R700_VPORT_SCISSOR_ENABLE(1);
516 } else {
517 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
518 }
519
520 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
521 if (state->sprite_coord_enable) {
522 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
523 S_0286D4_PNT_SPRITE_OVRD_X(2) |
524 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
525 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
526 S_0286D4_PNT_SPRITE_OVRD_W(1);
527 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
528 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
529 }
530 }
531
532 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
533 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
534 tmp = r600_pack_float_12p4(state->point_size/2);
535 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
536 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
537 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
538 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
539 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
540 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
541 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
542
543 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
544 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
545 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
546 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
547 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
548 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
549
550 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
551 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
552 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
553 S_028814_FACE(!state->front_ccw) |
554 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
555 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
556 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
557 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
558 state->fill_back != PIPE_POLYGON_MODE_FILL) |
559 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
560 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
561 if (rctx->b.chip_class == R700) {
562 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
563 }
564 if (rctx->b.chip_class == R600) {
565 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
566 S_028350_MULTIPASS(state->rasterizer_discard));
567 }
568 return rs;
569 }
570
571 static unsigned r600_tex_filter(unsigned filter, unsigned max_aniso)
572 {
573 if (filter == PIPE_TEX_FILTER_LINEAR)
574 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_BILINEAR
575 : V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
576 else
577 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_POINT
578 : V_03C000_SQ_TEX_XY_FILTER_POINT;
579 }
580
581 static void *r600_create_sampler_state(struct pipe_context *ctx,
582 const struct pipe_sampler_state *state)
583 {
584 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
585 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
586 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
587 : state->max_anisotropy;
588 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
589
590 if (!ss) {
591 return NULL;
592 }
593
594 ss->seamless_cube_map = state->seamless_cube_map;
595 ss->border_color_use = sampler_state_needs_border_color(state);
596
597 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
598 ss->tex_sampler_words[0] =
599 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
600 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
601 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
602 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter, max_aniso)) |
603 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter, max_aniso)) |
604 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
605 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
606 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
607 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
608 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
609 ss->tex_sampler_words[1] =
610 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
611 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
612 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
613 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
614 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
615
616 if (ss->border_color_use) {
617 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
618 }
619 return ss;
620 }
621
622 static struct pipe_sampler_view *
623 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
624 unsigned width0, unsigned height0)
625
626 {
627 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
628 int stride = util_format_get_blocksize(view->base.format);
629 unsigned format, num_format, format_comp, endian;
630 uint64_t offset = view->base.u.buf.offset;
631 unsigned size = view->base.u.buf.size;
632
633 r600_vertex_data_type(view->base.format,
634 &format, &num_format, &format_comp,
635 &endian);
636
637 view->tex_resource = &tmp->resource;
638 view->skip_mip_address_reloc = true;
639
640 view->tex_resource_words[0] = offset;
641 view->tex_resource_words[1] = size - 1;
642 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) |
643 S_038008_STRIDE(stride) |
644 S_038008_DATA_FORMAT(format) |
645 S_038008_NUM_FORMAT_ALL(num_format) |
646 S_038008_FORMAT_COMP_ALL(format_comp) |
647 S_038008_ENDIAN_SWAP(endian);
648 view->tex_resource_words[3] = 0;
649 /*
650 * in theory dword 4 is for number of elements, for use with resinfo,
651 * but it seems to utterly fail to work, the amd gpu shader analyser
652 * uses a const buffer to store the element sizes for buffer txq
653 */
654 view->tex_resource_words[4] = 0;
655 view->tex_resource_words[5] = 0;
656 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
657 return &view->base;
658 }
659
660 struct pipe_sampler_view *
661 r600_create_sampler_view_custom(struct pipe_context *ctx,
662 struct pipe_resource *texture,
663 const struct pipe_sampler_view *state,
664 unsigned width_first_level, unsigned height_first_level)
665 {
666 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
667 struct r600_texture *tmp = (struct r600_texture*)texture;
668 unsigned format, endian;
669 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
670 unsigned char swizzle[4], array_mode = 0;
671 unsigned width, height, depth, offset_level, last_level;
672 bool do_endian_swap = FALSE;
673
674 if (!view)
675 return NULL;
676
677 /* initialize base object */
678 view->base = *state;
679 view->base.texture = NULL;
680 pipe_reference(NULL, &texture->reference);
681 view->base.texture = texture;
682 view->base.reference.count = 1;
683 view->base.context = ctx;
684
685 if (texture->target == PIPE_BUFFER)
686 return texture_buffer_sampler_view(view, texture->width0, 1);
687
688 swizzle[0] = state->swizzle_r;
689 swizzle[1] = state->swizzle_g;
690 swizzle[2] = state->swizzle_b;
691 swizzle[3] = state->swizzle_a;
692
693 if (R600_BIG_ENDIAN)
694 do_endian_swap = !tmp->db_compatible;
695
696 format = r600_translate_texformat(ctx->screen, state->format,
697 swizzle,
698 &word4, &yuv_format, do_endian_swap);
699 assert(format != ~0);
700 if (format == ~0) {
701 FREE(view);
702 return NULL;
703 }
704
705 if (state->format == PIPE_FORMAT_X24S8_UINT ||
706 state->format == PIPE_FORMAT_S8X24_UINT ||
707 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
708 state->format == PIPE_FORMAT_S8_UINT)
709 view->is_stencil_sampler = true;
710
711 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
712 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
713 FREE(view);
714 return NULL;
715 }
716 tmp = tmp->flushed_depth_texture;
717 }
718
719 endian = r600_colorformat_endian_swap(format, do_endian_swap);
720
721 offset_level = state->u.tex.first_level;
722 last_level = state->u.tex.last_level - offset_level;
723 width = width_first_level;
724 height = height_first_level;
725 depth = u_minify(texture->depth0, offset_level);
726 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
727
728 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
729 height = 1;
730 depth = texture->array_size;
731 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
732 depth = texture->array_size;
733 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
734 depth = texture->array_size / 6;
735
736 switch (tmp->surface.level[offset_level].mode) {
737 default:
738 case RADEON_SURF_MODE_LINEAR_ALIGNED:
739 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
740 break;
741 case RADEON_SURF_MODE_1D:
742 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
743 break;
744 case RADEON_SURF_MODE_2D:
745 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
746 break;
747 }
748
749 view->tex_resource = &tmp->resource;
750 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
751 S_038000_TILE_MODE(array_mode) |
752 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
753 S_038000_PITCH((pitch / 8) - 1) |
754 S_038000_TEX_WIDTH(width - 1));
755 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
756 S_038004_TEX_DEPTH(depth - 1) |
757 S_038004_DATA_FORMAT(format));
758 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
759 if (offset_level >= tmp->resource.b.b.last_level) {
760 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
761 } else {
762 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
763 }
764 view->tex_resource_words[4] = (word4 |
765 S_038010_REQUEST_SIZE(1) |
766 S_038010_ENDIAN_SWAP(endian) |
767 S_038010_BASE_LEVEL(0));
768 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
769 S_038014_LAST_ARRAY(state->u.tex.last_layer));
770 if (texture->nr_samples > 1) {
771 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
772 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
773 } else {
774 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
775 }
776 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
777 S_038018_MAX_ANISO(4 /* max 16 samples */));
778 return &view->base;
779 }
780
781 static struct pipe_sampler_view *
782 r600_create_sampler_view(struct pipe_context *ctx,
783 struct pipe_resource *tex,
784 const struct pipe_sampler_view *state)
785 {
786 return r600_create_sampler_view_custom(ctx, tex, state,
787 u_minify(tex->width0, state->u.tex.first_level),
788 u_minify(tex->height0, state->u.tex.first_level));
789 }
790
791 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
792 {
793 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
794 struct pipe_clip_state *state = &rctx->clip_state.state;
795
796 radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
797 radeon_emit_array(cs, (unsigned*)state, 6*4);
798 }
799
800 static void r600_set_polygon_stipple(struct pipe_context *ctx,
801 const struct pipe_poly_stipple *state)
802 {
803 }
804
805 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
806 unsigned size, unsigned alignment)
807 {
808 struct pipe_resource buffer;
809
810 memset(&buffer, 0, sizeof buffer);
811 buffer.target = PIPE_BUFFER;
812 buffer.format = PIPE_FORMAT_R8_UNORM;
813 buffer.bind = PIPE_BIND_CUSTOM;
814 buffer.usage = PIPE_USAGE_DEFAULT;
815 buffer.flags = 0;
816 buffer.width0 = size;
817 buffer.height0 = 1;
818 buffer.depth0 = 1;
819 buffer.array_size = 1;
820
821 return (struct r600_resource*)
822 r600_buffer_create(&rscreen->b.b, &buffer, alignment);
823 }
824
825 static void r600_init_color_surface(struct r600_context *rctx,
826 struct r600_surface *surf,
827 bool force_cmask_fmask)
828 {
829 struct r600_screen *rscreen = rctx->screen;
830 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
831 unsigned level = surf->base.u.tex.level;
832 unsigned pitch, slice;
833 unsigned color_info;
834 unsigned color_view;
835 unsigned format, swap, ntype, endian;
836 unsigned offset;
837 const struct util_format_description *desc;
838 int i;
839 bool blend_bypass = 0, blend_clamp = 1, do_endian_swap = FALSE;
840
841 if (rtex->db_compatible && !r600_can_sample_zs(rtex, false)) {
842 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
843 rtex = rtex->flushed_depth_texture;
844 assert(rtex);
845 }
846
847 offset = rtex->surface.level[level].offset;
848 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
849 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
850
851 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
852 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
853 if (slice) {
854 slice = slice - 1;
855 }
856 color_info = 0;
857 switch (rtex->surface.level[level].mode) {
858 default:
859 case RADEON_SURF_MODE_LINEAR_ALIGNED:
860 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
861 break;
862 case RADEON_SURF_MODE_1D:
863 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
864 break;
865 case RADEON_SURF_MODE_2D:
866 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
867 break;
868 }
869
870 desc = util_format_description(surf->base.format);
871
872 for (i = 0; i < 4; i++) {
873 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
874 break;
875 }
876 }
877
878 ntype = V_0280A0_NUMBER_UNORM;
879 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
880 ntype = V_0280A0_NUMBER_SRGB;
881 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
882 if (desc->channel[i].normalized)
883 ntype = V_0280A0_NUMBER_SNORM;
884 else if (desc->channel[i].pure_integer)
885 ntype = V_0280A0_NUMBER_SINT;
886 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
887 if (desc->channel[i].normalized)
888 ntype = V_0280A0_NUMBER_UNORM;
889 else if (desc->channel[i].pure_integer)
890 ntype = V_0280A0_NUMBER_UINT;
891 }
892
893 if (R600_BIG_ENDIAN)
894 do_endian_swap = !rtex->db_compatible;
895
896 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format,
897 do_endian_swap);
898 assert(format != ~0);
899
900 swap = r600_translate_colorswap(surf->base.format, do_endian_swap);
901 assert(swap != ~0);
902
903 endian = r600_colorformat_endian_swap(format, do_endian_swap);
904
905 /* set blend bypass according to docs if SINT/UINT or
906 8/24 COLOR variants */
907 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
908 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
909 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
910 blend_clamp = 0;
911 blend_bypass = 1;
912 }
913
914 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
915
916 color_info |= S_0280A0_FORMAT(format) |
917 S_0280A0_COMP_SWAP(swap) |
918 S_0280A0_BLEND_BYPASS(blend_bypass) |
919 S_0280A0_BLEND_CLAMP(blend_clamp) |
920 S_0280A0_NUMBER_TYPE(ntype) |
921 S_0280A0_ENDIAN(endian);
922
923 /* EXPORT_NORM is an optimzation that can be enabled for better
924 * performance in certain cases
925 */
926 if (rctx->b.chip_class == R600) {
927 /* EXPORT_NORM can be enabled if:
928 * - 11-bit or smaller UNORM/SNORM/SRGB
929 * - BLEND_CLAMP is enabled
930 * - BLEND_FLOAT32 is disabled
931 */
932 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
933 (desc->channel[i].size < 12 &&
934 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
935 ntype != V_0280A0_NUMBER_UINT &&
936 ntype != V_0280A0_NUMBER_SINT) &&
937 G_0280A0_BLEND_CLAMP(color_info) &&
938 !G_0280A0_BLEND_FLOAT32(color_info)) {
939 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
940 surf->export_16bpc = true;
941 }
942 } else {
943 /* EXPORT_NORM can be enabled if:
944 * - 11-bit or smaller UNORM/SNORM/SRGB
945 * - 16-bit or smaller FLOAT
946 */
947 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
948 ((desc->channel[i].size < 12 &&
949 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
950 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
951 (desc->channel[i].size < 17 &&
952 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
953 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
954 surf->export_16bpc = true;
955 }
956 }
957
958 /* These might not always be initialized to zero. */
959 surf->cb_color_base = offset >> 8;
960 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
961 S_028060_SLICE_TILE_MAX(slice);
962 surf->cb_color_fmask = surf->cb_color_base;
963 surf->cb_color_cmask = surf->cb_color_base;
964 surf->cb_color_mask = 0;
965
966 r600_resource_reference(&surf->cb_buffer_cmask, &rtex->resource);
967 r600_resource_reference(&surf->cb_buffer_fmask, &rtex->resource);
968
969 if (rtex->cmask.size) {
970 surf->cb_color_cmask = rtex->cmask.offset >> 8;
971 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
972
973 if (rtex->fmask.size) {
974 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
975 surf->cb_color_fmask = rtex->fmask.offset >> 8;
976 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
977 } else { /* cmask only */
978 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
979 }
980 } else if (force_cmask_fmask) {
981 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
982 *
983 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
984 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
985 * because it's not an MSAA buffer.
986 */
987 struct r600_cmask_info cmask;
988 struct r600_fmask_info fmask;
989
990 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
991 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
992
993 /* CMASK. */
994 if (!rctx->dummy_cmask ||
995 rctx->dummy_cmask->b.b.width0 < cmask.size ||
996 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
997 struct pipe_transfer *transfer;
998 void *ptr;
999
1000 r600_resource_reference(&rctx->dummy_cmask, NULL);
1001 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1002
1003 /* Set the contents to 0xCC. */
1004 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1005 memset(ptr, 0xCC, cmask.size);
1006 pipe_buffer_unmap(&rctx->b.b, transfer);
1007 }
1008 r600_resource_reference(&surf->cb_buffer_cmask, rctx->dummy_cmask);
1009
1010 /* FMASK. */
1011 if (!rctx->dummy_fmask ||
1012 rctx->dummy_fmask->b.b.width0 < fmask.size ||
1013 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1014 r600_resource_reference(&rctx->dummy_fmask, NULL);
1015 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1016
1017 }
1018 r600_resource_reference(&surf->cb_buffer_fmask, rctx->dummy_fmask);
1019
1020 /* Init the registers. */
1021 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1022 surf->cb_color_cmask = 0;
1023 surf->cb_color_fmask = 0;
1024 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1025 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1026 }
1027
1028 surf->cb_color_info = color_info;
1029 surf->cb_color_view = color_view;
1030 surf->color_initialized = true;
1031 }
1032
1033 static void r600_init_depth_surface(struct r600_context *rctx,
1034 struct r600_surface *surf)
1035 {
1036 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1037 unsigned level, pitch, slice, format, offset, array_mode;
1038
1039 level = surf->base.u.tex.level;
1040 offset = rtex->surface.level[level].offset;
1041 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1042 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1043 if (slice) {
1044 slice = slice - 1;
1045 }
1046 switch (rtex->surface.level[level].mode) {
1047 case RADEON_SURF_MODE_2D:
1048 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1049 break;
1050 case RADEON_SURF_MODE_1D:
1051 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1052 default:
1053 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1054 break;
1055 }
1056
1057 format = r600_translate_dbformat(surf->base.format);
1058 assert(format != ~0);
1059
1060 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1061 surf->db_depth_base = offset >> 8;
1062 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1063 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1064 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1065 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1066
1067 /* use htile only for first level */
1068 if (rtex->htile_buffer && !level) {
1069 surf->db_htile_data_base = 0;
1070 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1071 S_028D24_HTILE_HEIGHT(1) |
1072 S_028D24_FULL_CACHE(1);
1073 /* preload is not working properly on r6xx/r7xx */
1074 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1075 }
1076
1077 surf->depth_initialized = true;
1078 }
1079
1080 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1081 const struct pipe_framebuffer_state *state)
1082 {
1083 struct r600_context *rctx = (struct r600_context *)ctx;
1084 struct r600_surface *surf;
1085 struct r600_texture *rtex;
1086 unsigned i;
1087
1088 /* Flush TC when changing the framebuffer state, because the only
1089 * client not using TC that can change textures is the framebuffer.
1090 * Other places don't typically have to flush TC.
1091 */
1092 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1093 R600_CONTEXT_FLUSH_AND_INV |
1094 R600_CONTEXT_FLUSH_AND_INV_CB |
1095 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1096 R600_CONTEXT_FLUSH_AND_INV_DB |
1097 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1098 R600_CONTEXT_INV_TEX_CACHE;
1099
1100 /* Set the new state. */
1101 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1102
1103 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1104 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1105 util_format_is_pure_integer(state->cbufs[0]->format);
1106 rctx->framebuffer.compressed_cb_mask = 0;
1107 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1108 state->cbufs[0] && state->cbufs[1] &&
1109 state->cbufs[0]->texture->nr_samples > 1 &&
1110 state->cbufs[1]->texture->nr_samples <= 1;
1111 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1112
1113 /* Colorbuffers. */
1114 for (i = 0; i < state->nr_cbufs; i++) {
1115 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1116 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1117 rctx->framebuffer.is_msaa_resolve &&
1118 i == 1;
1119
1120 surf = (struct r600_surface*)state->cbufs[i];
1121 if (!surf)
1122 continue;
1123
1124 rtex = (struct r600_texture*)surf->base.texture;
1125 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1126
1127 if (!surf->color_initialized || force_cmask_fmask) {
1128 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1129 if (force_cmask_fmask) {
1130 /* re-initialize later without compression */
1131 surf->color_initialized = false;
1132 }
1133 }
1134
1135 if (!surf->export_16bpc) {
1136 rctx->framebuffer.export_16bpc = false;
1137 }
1138
1139 if (rtex->fmask.size) {
1140 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1141 }
1142 }
1143
1144 /* Update alpha-test state dependencies.
1145 * Alpha-test is done on the first colorbuffer only. */
1146 if (state->nr_cbufs) {
1147 bool alphatest_bypass = false;
1148
1149 surf = (struct r600_surface*)state->cbufs[0];
1150 if (surf) {
1151 alphatest_bypass = surf->alphatest_bypass;
1152 }
1153
1154 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1155 rctx->alphatest_state.bypass = alphatest_bypass;
1156 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1157 }
1158 }
1159
1160 /* ZS buffer. */
1161 if (state->zsbuf) {
1162 surf = (struct r600_surface*)state->zsbuf;
1163
1164 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1165
1166 if (!surf->depth_initialized) {
1167 r600_init_depth_surface(rctx, surf);
1168 }
1169
1170 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1171 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1172 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1173 }
1174
1175 if (rctx->db_state.rsurf != surf) {
1176 rctx->db_state.rsurf = surf;
1177 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1178 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1179 }
1180 } else if (rctx->db_state.rsurf) {
1181 rctx->db_state.rsurf = NULL;
1182 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1183 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1184 }
1185
1186 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1187 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1188 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1189 }
1190
1191 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1192 rctx->alphatest_state.bypass = false;
1193 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1194 }
1195
1196 /* Calculate the CS size. */
1197 rctx->framebuffer.atom.num_dw =
1198 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1199
1200 if (rctx->framebuffer.state.nr_cbufs) {
1201 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1202 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1203 }
1204 if (rctx->framebuffer.state.zsbuf) {
1205 rctx->framebuffer.atom.num_dw += 16;
1206 } else if (rctx->screen->b.info.drm_minor >= 18) {
1207 rctx->framebuffer.atom.num_dw += 3;
1208 }
1209 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1210 rctx->framebuffer.atom.num_dw += 2;
1211 }
1212
1213 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1214
1215 r600_set_sample_locations_constant_buffer(rctx);
1216 }
1217
1218 static uint32_t sample_locs_2x[] = {
1219 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1220 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1221 };
1222 static unsigned max_dist_2x = 4;
1223
1224 static uint32_t sample_locs_4x[] = {
1225 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1226 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1227 };
1228 static unsigned max_dist_4x = 6;
1229 static uint32_t sample_locs_8x[] = {
1230 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1231 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1232 };
1233 static unsigned max_dist_8x = 7;
1234
1235 static void r600_get_sample_position(struct pipe_context *ctx,
1236 unsigned sample_count,
1237 unsigned sample_index,
1238 float *out_value)
1239 {
1240 int offset, index;
1241 struct {
1242 int idx:4;
1243 } val;
1244 switch (sample_count) {
1245 case 1:
1246 default:
1247 out_value[0] = out_value[1] = 0.5;
1248 break;
1249 case 2:
1250 offset = 4 * (sample_index * 2);
1251 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1252 out_value[0] = (float)(val.idx + 8) / 16.0f;
1253 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1254 out_value[1] = (float)(val.idx + 8) / 16.0f;
1255 break;
1256 case 4:
1257 offset = 4 * (sample_index * 2);
1258 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1259 out_value[0] = (float)(val.idx + 8) / 16.0f;
1260 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1261 out_value[1] = (float)(val.idx + 8) / 16.0f;
1262 break;
1263 case 8:
1264 offset = 4 * (sample_index % 4 * 2);
1265 index = (sample_index / 4);
1266 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1267 out_value[0] = (float)(val.idx + 8) / 16.0f;
1268 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1269 out_value[1] = (float)(val.idx + 8) / 16.0f;
1270 break;
1271 }
1272 }
1273
1274 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1275 {
1276 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1277 unsigned max_dist = 0;
1278
1279 if (rctx->b.family == CHIP_R600) {
1280 switch (nr_samples) {
1281 default:
1282 nr_samples = 0;
1283 break;
1284 case 2:
1285 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1286 max_dist = max_dist_2x;
1287 break;
1288 case 4:
1289 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1290 max_dist = max_dist_4x;
1291 break;
1292 case 8:
1293 radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1294 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1295 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1296 max_dist = max_dist_8x;
1297 break;
1298 }
1299 } else {
1300 switch (nr_samples) {
1301 default:
1302 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1303 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1304 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1305 nr_samples = 0;
1306 break;
1307 case 2:
1308 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1309 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1310 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1311 max_dist = max_dist_2x;
1312 break;
1313 case 4:
1314 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1315 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1316 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1317 max_dist = max_dist_4x;
1318 break;
1319 case 8:
1320 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1321 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1322 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1323 max_dist = max_dist_8x;
1324 break;
1325 }
1326 }
1327
1328 if (nr_samples > 1) {
1329 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1330 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1331 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1332 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1333 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1334 } else {
1335 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1336 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1337 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1338 }
1339 }
1340
1341 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1342 {
1343 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1344 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1345 unsigned nr_cbufs = state->nr_cbufs;
1346 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1347 unsigned i, sbu = 0;
1348
1349 /* Colorbuffers. */
1350 radeon_set_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1351 for (i = 0; i < nr_cbufs; i++) {
1352 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1353 }
1354 /* set CB_COLOR1_INFO for possible dual-src blending */
1355 if (i == 1 && cb[0]) {
1356 radeon_emit(cs, cb[0]->cb_color_info);
1357 i++;
1358 }
1359 for (; i < 8; i++) {
1360 radeon_emit(cs, 0);
1361 }
1362
1363 if (nr_cbufs) {
1364 for (i = 0; i < nr_cbufs; i++) {
1365 unsigned reloc;
1366
1367 if (!cb[i])
1368 continue;
1369
1370 /* COLOR_BASE */
1371 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1372
1373 reloc = radeon_add_to_buffer_list(&rctx->b,
1374 &rctx->b.gfx,
1375 (struct r600_resource*)cb[i]->base.texture,
1376 RADEON_USAGE_READWRITE,
1377 cb[i]->base.texture->nr_samples > 1 ?
1378 RADEON_PRIO_COLOR_BUFFER_MSAA :
1379 RADEON_PRIO_COLOR_BUFFER);
1380 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1381 radeon_emit(cs, reloc);
1382
1383 /* FMASK */
1384 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1385
1386 reloc = radeon_add_to_buffer_list(&rctx->b,
1387 &rctx->b.gfx,
1388 cb[i]->cb_buffer_fmask,
1389 RADEON_USAGE_READWRITE,
1390 cb[i]->base.texture->nr_samples > 1 ?
1391 RADEON_PRIO_COLOR_BUFFER_MSAA :
1392 RADEON_PRIO_COLOR_BUFFER);
1393 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1394 radeon_emit(cs, reloc);
1395
1396 /* CMASK */
1397 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1398
1399 reloc = radeon_add_to_buffer_list(&rctx->b,
1400 &rctx->b.gfx,
1401 cb[i]->cb_buffer_cmask,
1402 RADEON_USAGE_READWRITE,
1403 cb[i]->base.texture->nr_samples > 1 ?
1404 RADEON_PRIO_COLOR_BUFFER_MSAA :
1405 RADEON_PRIO_COLOR_BUFFER);
1406 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1407 radeon_emit(cs, reloc);
1408 }
1409
1410 radeon_set_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1411 for (i = 0; i < nr_cbufs; i++) {
1412 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1413 }
1414
1415 radeon_set_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1416 for (i = 0; i < nr_cbufs; i++) {
1417 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1418 }
1419
1420 radeon_set_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1421 for (i = 0; i < nr_cbufs; i++) {
1422 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1423 }
1424
1425 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1426 }
1427
1428 /* SURFACE_BASE_UPDATE */
1429 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1430 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1431 radeon_emit(cs, sbu);
1432 sbu = 0;
1433 }
1434
1435 /* Zbuffer. */
1436 if (state->zsbuf) {
1437 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1438 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1439 &rctx->b.gfx,
1440 (struct r600_resource*)state->zsbuf->texture,
1441 RADEON_USAGE_READWRITE,
1442 surf->base.texture->nr_samples > 1 ?
1443 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1444 RADEON_PRIO_DEPTH_BUFFER);
1445
1446 radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1447 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1448 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1449 radeon_set_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1450 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1451 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1452
1453 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1454 radeon_emit(cs, reloc);
1455
1456 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1457
1458 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1459 } else if (rctx->screen->b.info.drm_minor >= 18) {
1460 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1461 * Older kernels are out of luck. */
1462 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1463 }
1464
1465 /* SURFACE_BASE_UPDATE */
1466 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1467 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1468 radeon_emit(cs, sbu);
1469 sbu = 0;
1470 }
1471
1472 /* Framebuffer dimensions. */
1473 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1474 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1475 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1476 radeon_emit(cs, S_028244_BR_X(state->width) |
1477 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1478
1479 if (rctx->framebuffer.is_msaa_resolve) {
1480 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1481 } else {
1482 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1483 * will assure that the alpha-test will work even if there is
1484 * no colorbuffer bound. */
1485 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1486 (1ull << MAX2(nr_cbufs, 1)) - 1);
1487 }
1488
1489 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1490 }
1491
1492 static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1493 {
1494 struct r600_context *rctx = (struct r600_context *)ctx;
1495
1496 if (rctx->ps_iter_samples == min_samples)
1497 return;
1498
1499 rctx->ps_iter_samples = min_samples;
1500 if (rctx->framebuffer.nr_samples > 1) {
1501 r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom);
1502 if (rctx->b.chip_class == R600)
1503 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1504 }
1505 }
1506
1507 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1508 {
1509 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1510 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1511
1512 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1513 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1514 if (rctx->b.chip_class == R600) {
1515 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1516 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1517 } else {
1518 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1519 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1520 }
1521 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1522 } else {
1523 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1524 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1525 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1526
1527 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1528 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1529 /* Always enable the first color output to make sure alpha-test works even without one. */
1530 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1531 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1532 a->cb_color_control |
1533 S_028808_MULTIWRITE_ENABLE(multiwrite));
1534 }
1535 }
1536
1537 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1538 {
1539 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1540 struct r600_db_state *a = (struct r600_db_state*)atom;
1541
1542 if (a->rsurf && a->rsurf->db_htile_surface) {
1543 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1544 unsigned reloc_idx;
1545
1546 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1547 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1548 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1549 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1550 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1551 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1552 radeon_emit(cs, reloc_idx);
1553 } else {
1554 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1555 }
1556 }
1557
1558 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1559 {
1560 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1561 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1562 unsigned db_render_control = 0;
1563 unsigned db_render_override =
1564 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1565 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1566
1567 if (rctx->b.chip_class >= R700) {
1568 switch (a->ps_conservative_z) {
1569 default: /* fall through */
1570 case TGSI_FS_DEPTH_LAYOUT_ANY:
1571 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_ANY_Z);
1572 break;
1573 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1574 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_GREATER_THAN_Z);
1575 break;
1576 case TGSI_FS_DEPTH_LAYOUT_LESS:
1577 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_LESS_THAN_Z);
1578 break;
1579 }
1580 }
1581
1582 if (rctx->b.num_occlusion_queries > 0 &&
1583 !a->occlusion_queries_disabled) {
1584 if (rctx->b.chip_class >= R700) {
1585 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1586 }
1587 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1588 } else {
1589 db_render_control |= S_028D0C_ZPASS_INCREMENT_DISABLE(1);
1590 }
1591
1592 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1593 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1594 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1595 /* This is to fix a lockup when hyperz and alpha test are enabled at
1596 * the same time somehow GPU get confuse on which order to pick for
1597 * z test
1598 */
1599 if (rctx->alphatest_state.sx_alpha_test_control) {
1600 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1601 }
1602 } else {
1603 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1604 }
1605 if (rctx->b.chip_class == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) {
1606 /* sample shading and hyperz causes lockups on R6xx chips */
1607 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1608 }
1609 if (a->flush_depthstencil_through_cb) {
1610 assert(a->copy_depth || a->copy_stencil);
1611
1612 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1613 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1614 S_028D0C_COPY_CENTROID(1) |
1615 S_028D0C_COPY_SAMPLE(a->copy_sample);
1616
1617 if (rctx->b.chip_class == R600)
1618 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1619
1620 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
1621 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
1622 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1623 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1624 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1625 S_028D0C_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1626 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1627 }
1628 if (a->htile_clear) {
1629 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1630 }
1631
1632 /* RV770 workaround for a hang with 8x MSAA. */
1633 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1634 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
1635 }
1636
1637 radeon_set_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1638 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1639 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1640 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1641 }
1642
1643 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1644 {
1645 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1646 struct r600_config_state *a = (struct r600_config_state*)atom;
1647
1648 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1649 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1650 }
1651
1652 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1653 {
1654 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1655 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1656
1657 while (dirty_mask) {
1658 struct pipe_vertex_buffer *vb;
1659 struct r600_resource *rbuffer;
1660 unsigned offset;
1661 unsigned buffer_index = u_bit_scan(&dirty_mask);
1662
1663 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1664 rbuffer = (struct r600_resource*)vb->buffer;
1665 assert(rbuffer);
1666
1667 offset = vb->buffer_offset;
1668
1669 /* fetch resources start at index 320 (OFFSET_FS) */
1670 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1671 radeon_emit(cs, (R600_FETCH_CONSTANTS_OFFSET_FS + buffer_index) * 7);
1672 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1673 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1674 radeon_emit(cs, /* RESOURCEi_WORD2 */
1675 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1676 S_038008_STRIDE(vb->stride));
1677 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1678 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1679 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1680 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1681
1682 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1683 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1684 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1685 }
1686 }
1687
1688 static void r600_emit_constant_buffers(struct r600_context *rctx,
1689 struct r600_constbuf_state *state,
1690 unsigned buffer_id_base,
1691 unsigned reg_alu_constbuf_size,
1692 unsigned reg_alu_const_cache)
1693 {
1694 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1695 uint32_t dirty_mask = state->dirty_mask;
1696
1697 while (dirty_mask) {
1698 struct pipe_constant_buffer *cb;
1699 struct r600_resource *rbuffer;
1700 unsigned offset;
1701 unsigned buffer_index = ffs(dirty_mask) - 1;
1702 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1703 cb = &state->cb[buffer_index];
1704 rbuffer = (struct r600_resource*)cb->buffer;
1705 assert(rbuffer);
1706
1707 offset = cb->buffer_offset;
1708
1709 if (!gs_ring_buffer) {
1710 radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1711 DIV_ROUND_UP(cb->buffer_size, 256));
1712 radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1713 }
1714
1715 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1716 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1717 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1718
1719 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1720 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1721 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1722 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1723 radeon_emit(cs, /* RESOURCEi_WORD2 */
1724 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1725 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1726 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1727 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1728 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1729 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1730
1731 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1732 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1733 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1734
1735 dirty_mask &= ~(1 << buffer_index);
1736 }
1737 state->dirty_mask = 0;
1738 }
1739
1740 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1741 {
1742 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1743 R600_FETCH_CONSTANTS_OFFSET_VS,
1744 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1745 R_028980_ALU_CONST_CACHE_VS_0);
1746 }
1747
1748 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1749 {
1750 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1751 R600_FETCH_CONSTANTS_OFFSET_GS,
1752 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1753 R_0289C0_ALU_CONST_CACHE_GS_0);
1754 }
1755
1756 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1757 {
1758 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1759 R600_FETCH_CONSTANTS_OFFSET_PS,
1760 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1761 R_028940_ALU_CONST_CACHE_PS_0);
1762 }
1763
1764 static void r600_emit_sampler_views(struct r600_context *rctx,
1765 struct r600_samplerview_state *state,
1766 unsigned resource_id_base)
1767 {
1768 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1769 uint32_t dirty_mask = state->dirty_mask;
1770
1771 while (dirty_mask) {
1772 struct r600_pipe_sampler_view *rview;
1773 unsigned resource_index = u_bit_scan(&dirty_mask);
1774 unsigned reloc;
1775
1776 rview = state->views[resource_index];
1777 assert(rview);
1778
1779 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1780 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1781 radeon_emit_array(cs, rview->tex_resource_words, 7);
1782
1783 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
1784 RADEON_USAGE_READ,
1785 r600_get_sampler_view_priority(rview->tex_resource));
1786 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1787 radeon_emit(cs, reloc);
1788 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1789 radeon_emit(cs, reloc);
1790 }
1791 state->dirty_mask = 0;
1792 }
1793
1794
1795 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1796 {
1797 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, R600_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS);
1798 }
1799
1800 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1801 {
1802 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, R600_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS);
1803 }
1804
1805 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1806 {
1807 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS);
1808 }
1809
1810 static void r600_emit_sampler_states(struct r600_context *rctx,
1811 struct r600_textures_info *texinfo,
1812 unsigned resource_id_base,
1813 unsigned border_color_reg)
1814 {
1815 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1816 uint32_t dirty_mask = texinfo->states.dirty_mask;
1817
1818 while (dirty_mask) {
1819 struct r600_pipe_sampler_state *rstate;
1820 struct r600_pipe_sampler_view *rview;
1821 unsigned i = u_bit_scan(&dirty_mask);
1822
1823 rstate = texinfo->states.states[i];
1824 assert(rstate);
1825 rview = texinfo->views.views[i];
1826
1827 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1828 * filtering between layers.
1829 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1830 */
1831 if (rview) {
1832 enum pipe_texture_target target = rview->base.texture->target;
1833 if (target == PIPE_TEXTURE_1D_ARRAY ||
1834 target == PIPE_TEXTURE_2D_ARRAY) {
1835 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1836 texinfo->is_array_sampler[i] = true;
1837 } else {
1838 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1839 texinfo->is_array_sampler[i] = false;
1840 }
1841 }
1842
1843 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1844 radeon_emit(cs, (resource_id_base + i) * 3);
1845 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1846
1847 if (rstate->border_color_use) {
1848 unsigned offset;
1849
1850 offset = border_color_reg;
1851 offset += i * 16;
1852 radeon_set_config_reg_seq(cs, offset, 4);
1853 radeon_emit_array(cs, rstate->border_color.ui, 4);
1854 }
1855 }
1856 texinfo->states.dirty_mask = 0;
1857 }
1858
1859 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1860 {
1861 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1862 }
1863
1864 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1865 {
1866 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1867 }
1868
1869 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1870 {
1871 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1872 }
1873
1874 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1875 {
1876 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1877 unsigned tmp;
1878
1879 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1880 S_009508_SYNC_GRADIENT(1) |
1881 S_009508_SYNC_WALKER(1) |
1882 S_009508_SYNC_ALIGNER(1);
1883 if (!rctx->seamless_cube_map.enabled) {
1884 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1885 }
1886 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1887 }
1888
1889 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1890 {
1891 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1892 uint8_t mask = s->sample_mask;
1893
1894 radeon_set_context_reg(rctx->b.gfx.cs, R_028C48_PA_SC_AA_MASK,
1895 mask | (mask << 8) | (mask << 16) | (mask << 24));
1896 }
1897
1898 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1899 {
1900 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1901 struct r600_cso_state *state = (struct r600_cso_state*)a;
1902 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1903
1904 radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1905 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1906 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
1907 RADEON_USAGE_READ,
1908 RADEON_PRIO_SHADER_BINARY));
1909 }
1910
1911 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1912 {
1913 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1914 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1915
1916 uint32_t v2 = 0, primid = 0;
1917
1918 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
1919 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1920 primid = 1;
1921 }
1922
1923 if (state->geom_enable) {
1924 uint32_t cut_val;
1925
1926 if (rctx->gs_shader->gs_max_out_vertices <= 128)
1927 cut_val = V_028A40_GS_CUT_128;
1928 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
1929 cut_val = V_028A40_GS_CUT_256;
1930 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
1931 cut_val = V_028A40_GS_CUT_512;
1932 else
1933 cut_val = V_028A40_GS_CUT_1024;
1934
1935 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1936 S_028A40_CUT_MODE(cut_val);
1937
1938 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1939 primid = 1;
1940 }
1941
1942 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1943 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
1944 }
1945
1946 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1947 {
1948 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1949 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
1950 struct r600_resource *rbuffer;
1951
1952 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1953 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1954 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1955
1956 if (state->enable) {
1957 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
1958 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
1959 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1960 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1961 RADEON_USAGE_READWRITE,
1962 RADEON_PRIO_SHADER_RINGS));
1963 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1964 state->esgs_ring.buffer_size >> 8);
1965
1966 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
1967 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
1968 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1969 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1970 RADEON_USAGE_READWRITE,
1971 RADEON_PRIO_SHADER_RINGS));
1972 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
1973 state->gsvs_ring.buffer_size >> 8);
1974 } else {
1975 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
1976 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
1977 }
1978
1979 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1980 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1981 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1982 }
1983
1984 /* Adjust GPR allocation on R6xx/R7xx */
1985 bool r600_adjust_gprs(struct r600_context *rctx)
1986 {
1987 unsigned num_gprs[R600_NUM_HW_STAGES];
1988 unsigned new_gprs[R600_NUM_HW_STAGES];
1989 unsigned cur_gprs[R600_NUM_HW_STAGES];
1990 unsigned def_gprs[R600_NUM_HW_STAGES];
1991 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
1992 unsigned max_gprs;
1993 unsigned tmp, tmp2;
1994 unsigned i;
1995 bool need_recalc = false, use_default = true;
1996
1997 /* hardware will reserve twice num_clause_temp_gprs */
1998 max_gprs = def_num_clause_temp_gprs * 2;
1999 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2000 def_gprs[i] = rctx->default_gprs[i];
2001 max_gprs += def_gprs[i];
2002 }
2003
2004 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2005 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2006 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2007 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2008
2009 num_gprs[R600_HW_STAGE_PS] = rctx->ps_shader->current->shader.bc.ngpr;
2010 if (rctx->gs_shader) {
2011 num_gprs[R600_HW_STAGE_ES] = rctx->vs_shader->current->shader.bc.ngpr;
2012 num_gprs[R600_HW_STAGE_GS] = rctx->gs_shader->current->shader.bc.ngpr;
2013 num_gprs[R600_HW_STAGE_VS] = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2014 } else {
2015 num_gprs[R600_HW_STAGE_ES] = 0;
2016 num_gprs[R600_HW_STAGE_GS] = 0;
2017 num_gprs[R600_HW_STAGE_VS] = rctx->vs_shader->current->shader.bc.ngpr;
2018 }
2019
2020 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2021 new_gprs[i] = num_gprs[i];
2022 if (new_gprs[i] > cur_gprs[i])
2023 need_recalc = true;
2024 if (new_gprs[i] > def_gprs[i])
2025 use_default = false;
2026 }
2027
2028 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2029 if (!need_recalc)
2030 return true;
2031
2032 /* try to use switch back to default */
2033 if (!use_default) {
2034 /* always privilege vs stage so that at worst we have the
2035 * pixel stage producing wrong output (not the vertex
2036 * stage) */
2037 new_gprs[R600_HW_STAGE_PS] = max_gprs - def_num_clause_temp_gprs * 2;
2038 for (i = R600_HW_STAGE_VS; i < R600_NUM_HW_STAGES; i++)
2039 new_gprs[R600_HW_STAGE_PS] -= new_gprs[i];
2040 } else {
2041 for (i = 0; i < R600_NUM_HW_STAGES; i++)
2042 new_gprs[i] = def_gprs[i];
2043 }
2044
2045 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2046 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2047 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2048 * it will lockup. So in this case just discard the draw command
2049 * and don't change the current gprs repartitions.
2050 */
2051 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2052 if (num_gprs[i] > new_gprs[i]) {
2053 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2054 "for a combined maximum of %d\n",
2055 num_gprs[R600_HW_STAGE_PS], num_gprs[R600_HW_STAGE_VS], num_gprs[R600_HW_STAGE_ES], num_gprs[R600_HW_STAGE_GS], max_gprs);
2056 return false;
2057 }
2058 }
2059
2060 /* in some case we endup recomputing the current value */
2061 tmp = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
2062 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
2063 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2064
2065 tmp2 = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
2066 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
2067 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2068 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2069 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2070 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
2071 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2072 }
2073 return true;
2074 }
2075
2076 void r600_init_atom_start_cs(struct r600_context *rctx)
2077 {
2078 int ps_prio;
2079 int vs_prio;
2080 int gs_prio;
2081 int es_prio;
2082 int num_ps_gprs;
2083 int num_vs_gprs;
2084 int num_gs_gprs;
2085 int num_es_gprs;
2086 int num_temp_gprs;
2087 int num_ps_threads;
2088 int num_vs_threads;
2089 int num_gs_threads;
2090 int num_es_threads;
2091 int num_ps_stack_entries;
2092 int num_vs_stack_entries;
2093 int num_gs_stack_entries;
2094 int num_es_stack_entries;
2095 enum radeon_family family;
2096 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2097 uint32_t tmp, i;
2098
2099 r600_init_command_buffer(cb, 256);
2100
2101 /* R6xx requires this packet at the start of each command buffer */
2102 if (rctx->b.chip_class == R600) {
2103 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2104 r600_store_value(cb, 0);
2105 }
2106 /* All asics require this one */
2107 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2108 r600_store_value(cb, 0x80000000);
2109 r600_store_value(cb, 0x80000000);
2110
2111 /* We're setting config registers here. */
2112 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2113 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2114
2115 /* This enables pipeline stat & streamout queries.
2116 * They are only disabled by blits.
2117 */
2118 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2119 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2120
2121 family = rctx->b.family;
2122 ps_prio = 0;
2123 vs_prio = 1;
2124 gs_prio = 2;
2125 es_prio = 3;
2126 switch (family) {
2127 case CHIP_R600:
2128 num_ps_gprs = 192;
2129 num_vs_gprs = 56;
2130 num_temp_gprs = 4;
2131 num_gs_gprs = 0;
2132 num_es_gprs = 0;
2133 num_ps_threads = 136;
2134 num_vs_threads = 48;
2135 num_gs_threads = 4;
2136 num_es_threads = 4;
2137 num_ps_stack_entries = 128;
2138 num_vs_stack_entries = 128;
2139 num_gs_stack_entries = 0;
2140 num_es_stack_entries = 0;
2141 break;
2142 case CHIP_RV630:
2143 case CHIP_RV635:
2144 num_ps_gprs = 84;
2145 num_vs_gprs = 36;
2146 num_temp_gprs = 4;
2147 num_gs_gprs = 0;
2148 num_es_gprs = 0;
2149 num_ps_threads = 144;
2150 num_vs_threads = 40;
2151 num_gs_threads = 4;
2152 num_es_threads = 4;
2153 num_ps_stack_entries = 40;
2154 num_vs_stack_entries = 40;
2155 num_gs_stack_entries = 32;
2156 num_es_stack_entries = 16;
2157 break;
2158 case CHIP_RV610:
2159 case CHIP_RV620:
2160 case CHIP_RS780:
2161 case CHIP_RS880:
2162 default:
2163 num_ps_gprs = 84;
2164 num_vs_gprs = 36;
2165 num_temp_gprs = 4;
2166 num_gs_gprs = 0;
2167 num_es_gprs = 0;
2168 /* use limits 40 VS and at least 16 ES/GS */
2169 num_ps_threads = 120;
2170 num_vs_threads = 40;
2171 num_gs_threads = 16;
2172 num_es_threads = 16;
2173 num_ps_stack_entries = 40;
2174 num_vs_stack_entries = 40;
2175 num_gs_stack_entries = 32;
2176 num_es_stack_entries = 16;
2177 break;
2178 case CHIP_RV670:
2179 num_ps_gprs = 144;
2180 num_vs_gprs = 40;
2181 num_temp_gprs = 4;
2182 num_gs_gprs = 0;
2183 num_es_gprs = 0;
2184 num_ps_threads = 136;
2185 num_vs_threads = 48;
2186 num_gs_threads = 4;
2187 num_es_threads = 4;
2188 num_ps_stack_entries = 40;
2189 num_vs_stack_entries = 40;
2190 num_gs_stack_entries = 32;
2191 num_es_stack_entries = 16;
2192 break;
2193 case CHIP_RV770:
2194 num_ps_gprs = 130;
2195 num_vs_gprs = 56;
2196 num_temp_gprs = 4;
2197 num_gs_gprs = 31;
2198 num_es_gprs = 31;
2199 num_ps_threads = 180;
2200 num_vs_threads = 60;
2201 num_gs_threads = 4;
2202 num_es_threads = 4;
2203 num_ps_stack_entries = 128;
2204 num_vs_stack_entries = 128;
2205 num_gs_stack_entries = 128;
2206 num_es_stack_entries = 128;
2207 break;
2208 case CHIP_RV730:
2209 case CHIP_RV740:
2210 num_ps_gprs = 84;
2211 num_vs_gprs = 36;
2212 num_temp_gprs = 4;
2213 num_gs_gprs = 0;
2214 num_es_gprs = 0;
2215 num_ps_threads = 180;
2216 num_vs_threads = 60;
2217 num_gs_threads = 4;
2218 num_es_threads = 4;
2219 num_ps_stack_entries = 128;
2220 num_vs_stack_entries = 128;
2221 num_gs_stack_entries = 0;
2222 num_es_stack_entries = 0;
2223 break;
2224 case CHIP_RV710:
2225 num_ps_gprs = 192;
2226 num_vs_gprs = 56;
2227 num_temp_gprs = 4;
2228 num_gs_gprs = 0;
2229 num_es_gprs = 0;
2230 num_ps_threads = 136;
2231 num_vs_threads = 48;
2232 num_gs_threads = 4;
2233 num_es_threads = 4;
2234 num_ps_stack_entries = 128;
2235 num_vs_stack_entries = 128;
2236 num_gs_stack_entries = 0;
2237 num_es_stack_entries = 0;
2238 break;
2239 }
2240
2241 rctx->default_gprs[R600_HW_STAGE_PS] = num_ps_gprs;
2242 rctx->default_gprs[R600_HW_STAGE_VS] = num_vs_gprs;
2243 rctx->default_gprs[R600_HW_STAGE_GS] = 0;
2244 rctx->default_gprs[R600_HW_STAGE_ES] = 0;
2245
2246 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2247
2248 /* SQ_CONFIG */
2249 tmp = 0;
2250 switch (family) {
2251 case CHIP_RV610:
2252 case CHIP_RV620:
2253 case CHIP_RS780:
2254 case CHIP_RS880:
2255 case CHIP_RV710:
2256 break;
2257 default:
2258 tmp |= S_008C00_VC_ENABLE(1);
2259 break;
2260 }
2261 tmp |= S_008C00_DX9_CONSTS(0);
2262 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2263 tmp |= S_008C00_PS_PRIO(ps_prio);
2264 tmp |= S_008C00_VS_PRIO(vs_prio);
2265 tmp |= S_008C00_GS_PRIO(gs_prio);
2266 tmp |= S_008C00_ES_PRIO(es_prio);
2267 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2268
2269 /* SQ_GPR_RESOURCE_MGMT_2 */
2270 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2271 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2272 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2273 r600_store_value(cb, tmp);
2274
2275 /* SQ_THREAD_RESOURCE_MGMT */
2276 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2277 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2278 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2279 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2280 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2281
2282 /* SQ_STACK_RESOURCE_MGMT_1 */
2283 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2284 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2285 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2286
2287 /* SQ_STACK_RESOURCE_MGMT_2 */
2288 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2289 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2290 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2291
2292 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2293
2294 if (rctx->b.chip_class >= R700) {
2295 r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4);
2296 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2297 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2298 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2299 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2300 } else {
2301 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2302 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2303 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2304 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2305 }
2306 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2307 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2308 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2309 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2310 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2311 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2312 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2313 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2314 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2315 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2316
2317 /* to avoid GPU doing any preloading of constant from random address */
2318 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2319 for (i = 0; i < 16; i++)
2320 r600_store_value(cb, 0);
2321
2322 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2323 for (i = 0; i < 16; i++)
2324 r600_store_value(cb, 0);
2325
2326 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2327 for (i = 0; i < 16; i++)
2328 r600_store_value(cb, 0);
2329
2330 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2331 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2332 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2333 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2334 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2335 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2336 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2337 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2338 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2339 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2340 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2341 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2342 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2343 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2344
2345 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2346 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2347 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2348
2349 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2350 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2351 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2352
2353 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2354
2355 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2356
2357 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2358
2359 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2360 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2361 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2362 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2363
2364 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2365 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2366 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2367 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2368
2369 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2370 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2371
2372 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2373 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2374
2375 if (rctx->b.chip_class >= R700) {
2376 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2377 }
2378
2379 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2380 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2381 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2382 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2383 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2384
2385 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2386 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2387 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2388
2389 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2390 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2391 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2392
2393 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2394 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2395 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2396 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2397 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2398 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2399
2400 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2401
2402 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2403 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2404 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2405
2406 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2407
2408 if (rctx->b.chip_class == R700)
2409 r600_store_context_reg(cb, R_028350_SX_MISC, 0);
2410 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2411 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2412
2413 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2414 if (rctx->screen->b.has_streamout) {
2415 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2416 }
2417
2418 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2419 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2420 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2421 }
2422
2423 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2424 {
2425 struct r600_context *rctx = (struct r600_context *)ctx;
2426 struct r600_command_buffer *cb = &shader->command_buffer;
2427 struct r600_shader *rshader = &shader->shader;
2428 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2429 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2430 unsigned tmp, sid, ufi = 0;
2431 int need_linear = 0;
2432 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2433 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2434
2435 if (!cb->buf) {
2436 r600_init_command_buffer(cb, 64);
2437 } else {
2438 cb->num_dw = 0;
2439 }
2440
2441 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2442 for (i = 0; i < rshader->ninput; i++) {
2443 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2444 pos_index = i;
2445 if (rshader->input[i].name == TGSI_SEMANTIC_FACE && face_index == -1)
2446 face_index = i;
2447 if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID)
2448 fixed_pt_position_index = i;
2449
2450 sid = rshader->input[i].spi_sid;
2451
2452 tmp = S_028644_SEMANTIC(sid);
2453
2454 /* D3D 9 behaviour. GL is undefined */
2455 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
2456 tmp |= S_028644_DEFAULT_VAL(3);
2457
2458 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2459 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2460 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2461 rctx->rasterizer && rctx->rasterizer->flatshade))
2462 tmp |= S_028644_FLAT_SHADE(1);
2463
2464 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2465 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2466 tmp |= S_028644_PT_SPRITE_TEX(1);
2467 }
2468
2469 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID)
2470 tmp |= S_028644_SEL_CENTROID(1);
2471
2472 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE)
2473 tmp |= S_028644_SEL_SAMPLE(1);
2474
2475 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2476 need_linear = 1;
2477 tmp |= S_028644_SEL_LINEAR(1);
2478 }
2479
2480 r600_store_value(cb, tmp);
2481 }
2482
2483 db_shader_control = 0;
2484 for (i = 0; i < rshader->noutput; i++) {
2485 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2486 z_export = 1;
2487 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2488 stencil_export = 1;
2489 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
2490 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
2491 mask_export = 1;
2492 }
2493 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2494 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2495 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
2496 if (rshader->uses_kill)
2497 db_shader_control |= S_02880C_KILL_ENABLE(1);
2498
2499 exports_ps = 0;
2500 for (i = 0; i < rshader->noutput; i++) {
2501 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2502 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
2503 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2504 exports_ps |= 1;
2505 }
2506 }
2507 num_cout = rshader->nr_ps_color_exports;
2508 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2509 if (!exports_ps) {
2510 /* always at least export 1 component per pixel */
2511 exports_ps = 2;
2512 }
2513
2514 shader->nr_ps_color_outputs = num_cout;
2515
2516 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2517 S_0286CC_PERSP_GRADIENT_ENA(1)|
2518 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2519 spi_input_z = 0;
2520 if (pos_index != -1) {
2521 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2522 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
2523 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2524 S_0286CC_BARYC_SAMPLE_CNTL(1)) |
2525 S_0286CC_POSITION_SAMPLE(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE);
2526 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2527 }
2528
2529 spi_ps_in_control_1 = 0;
2530 if (face_index != -1) {
2531 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2532 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2533 }
2534 if (fixed_pt_position_index != -1) {
2535 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2536 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
2537 }
2538
2539 /* HW bug in original R600 */
2540 if (rctx->b.family == CHIP_R600)
2541 ufi = 1;
2542
2543 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2544 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2545 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2546
2547 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2548
2549 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2550 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2551 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2552 S_028850_STACK_SIZE(rshader->bc.nstack) |
2553 S_028850_UNCACHED_FIRST_INST(ufi));
2554 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2555
2556 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2557 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2558
2559 /* only set some bits here, the other bits are set in the dsa state */
2560 shader->db_shader_control = db_shader_control;
2561 shader->ps_depth_export = z_export | stencil_export | mask_export;
2562
2563 shader->sprite_coord_enable = sprite_coord_enable;
2564 if (rctx->rasterizer)
2565 shader->flatshade = rctx->rasterizer->flatshade;
2566 }
2567
2568 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2569 {
2570 struct r600_command_buffer *cb = &shader->command_buffer;
2571 struct r600_shader *rshader = &shader->shader;
2572 unsigned spi_vs_out_id[10] = {};
2573 unsigned i, tmp, nparams = 0;
2574
2575 for (i = 0; i < rshader->noutput; i++) {
2576 if (rshader->output[i].spi_sid) {
2577 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2578 spi_vs_out_id[nparams / 4] |= tmp;
2579 nparams++;
2580 }
2581 }
2582
2583 r600_init_command_buffer(cb, 32);
2584
2585 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2586 for (i = 0; i < 10; i++) {
2587 r600_store_value(cb, spi_vs_out_id[i]);
2588 }
2589
2590 /* Certain attributes (position, psize, etc.) don't count as params.
2591 * VS is required to export at least one param and r600_shader_from_tgsi()
2592 * takes care of adding a dummy export.
2593 */
2594 if (nparams < 1)
2595 nparams = 1;
2596
2597 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2598 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2599 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2600 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2601 S_028868_STACK_SIZE(rshader->bc.nstack));
2602 if (rshader->vs_position_window_space) {
2603 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2604 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2605 } else {
2606 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2607 S_028818_VTX_W0_FMT(1) |
2608 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2609 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2610 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2611
2612 }
2613 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2614 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2615
2616 shader->pa_cl_vs_out_cntl =
2617 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2618 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2619 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2620 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2621 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2622 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2623 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2624 }
2625
2626 #define RV610_GSVS_ALIGN 32
2627 #define R600_GSVS_ALIGN 16
2628
2629 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2630 {
2631 struct r600_context *rctx = (struct r600_context *)ctx;
2632 struct r600_command_buffer *cb = &shader->command_buffer;
2633 struct r600_shader *rshader = &shader->shader;
2634 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2635 unsigned gsvs_itemsize =
2636 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2;
2637
2638 /* some r600s needs gsvs itemsize aligned to cacheline size
2639 this was fixed in rs780 and above. */
2640 switch (rctx->b.family) {
2641 case CHIP_RV610:
2642 gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN);
2643 break;
2644 case CHIP_R600:
2645 case CHIP_RV630:
2646 case CHIP_RV670:
2647 case CHIP_RV620:
2648 case CHIP_RV635:
2649 gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN);
2650 break;
2651 default:
2652 break;
2653 }
2654
2655 r600_init_command_buffer(cb, 64);
2656
2657 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2658 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2659
2660 if (rctx->b.chip_class >= R700) {
2661 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2662 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
2663 }
2664 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2665 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
2666
2667 r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE,
2668 cp_shader->ring_item_sizes[0] >> 2);
2669
2670 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2671 (rshader->ring_item_sizes[0]) >> 2);
2672
2673 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2674 gsvs_itemsize);
2675
2676 /* FIXME calculate these values somehow ??? */
2677 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2678 r600_store_value(cb, 0x80); /* GS_PER_ES */
2679 r600_store_value(cb, 0x100); /* ES_PER_GS */
2680 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2681 r600_store_value(cb, 0x2); /* GS_PER_VS */
2682
2683 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2684 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2685 S_02887C_STACK_SIZE(rshader->bc.nstack));
2686 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0);
2687 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2688 }
2689
2690 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2691 {
2692 struct r600_command_buffer *cb = &shader->command_buffer;
2693 struct r600_shader *rshader = &shader->shader;
2694
2695 r600_init_command_buffer(cb, 32);
2696
2697 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2698 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2699 S_028890_STACK_SIZE(rshader->bc.nstack));
2700 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0);
2701 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2702 }
2703
2704
2705 void *r600_create_resolve_blend(struct r600_context *rctx)
2706 {
2707 struct pipe_blend_state blend;
2708 unsigned i;
2709
2710 memset(&blend, 0, sizeof(blend));
2711 blend.independent_blend_enable = true;
2712 for (i = 0; i < 2; i++) {
2713 blend.rt[i].colormask = 0xf;
2714 blend.rt[i].blend_enable = 1;
2715 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2716 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2717 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2718 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2719 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2720 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2721 }
2722 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2723 }
2724
2725 void *r700_create_resolve_blend(struct r600_context *rctx)
2726 {
2727 struct pipe_blend_state blend;
2728
2729 memset(&blend, 0, sizeof(blend));
2730 blend.independent_blend_enable = true;
2731 blend.rt[0].colormask = 0xf;
2732 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2733 }
2734
2735 void *r600_create_decompress_blend(struct r600_context *rctx)
2736 {
2737 struct pipe_blend_state blend;
2738
2739 memset(&blend, 0, sizeof(blend));
2740 blend.independent_blend_enable = true;
2741 blend.rt[0].colormask = 0xf;
2742 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2743 }
2744
2745 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2746 {
2747 struct pipe_depth_stencil_alpha_state dsa;
2748 boolean quirk = false;
2749
2750 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2751 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2752 quirk = true;
2753
2754 memset(&dsa, 0, sizeof(dsa));
2755
2756 if (quirk) {
2757 dsa.depth.enabled = 1;
2758 dsa.depth.func = PIPE_FUNC_LEQUAL;
2759 dsa.stencil[0].enabled = 1;
2760 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2761 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2762 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2763 dsa.stencil[0].writemask = 0xff;
2764 }
2765
2766 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2767 }
2768
2769 void r600_update_db_shader_control(struct r600_context * rctx)
2770 {
2771 bool dual_export;
2772 unsigned db_shader_control;
2773 uint8_t ps_conservative_z;
2774
2775 if (!rctx->ps_shader) {
2776 return;
2777 }
2778
2779 dual_export = rctx->framebuffer.export_16bpc &&
2780 !rctx->ps_shader->current->ps_depth_export;
2781
2782 db_shader_control = rctx->ps_shader->current->db_shader_control |
2783 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2784
2785 ps_conservative_z = rctx->ps_shader->current->shader.ps_conservative_z;
2786
2787 /* When alpha test is enabled we can't trust the hw to make the proper
2788 * decision on the order in which ztest should be run related to fragment
2789 * shader execution.
2790 *
2791 * If alpha test is enabled perform z test after fragment. RE_Z (early
2792 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2793 */
2794 if (rctx->alphatest_state.sx_alpha_test_control) {
2795 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2796 } else {
2797 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2798 }
2799
2800 if (db_shader_control != rctx->db_misc_state.db_shader_control ||
2801 ps_conservative_z != rctx->db_misc_state.ps_conservative_z) {
2802 rctx->db_misc_state.db_shader_control = db_shader_control;
2803 rctx->db_misc_state.ps_conservative_z = ps_conservative_z;
2804 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2805 }
2806 }
2807
2808 static inline unsigned r600_array_mode(unsigned mode)
2809 {
2810 switch (mode) {
2811 default:
2812 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2813 break;
2814 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2815 break;
2816 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2817 }
2818 }
2819
2820 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2821 struct pipe_resource *dst,
2822 unsigned dst_level,
2823 unsigned dst_x,
2824 unsigned dst_y,
2825 unsigned dst_z,
2826 struct pipe_resource *src,
2827 unsigned src_level,
2828 unsigned src_x,
2829 unsigned src_y,
2830 unsigned src_z,
2831 unsigned copy_height,
2832 unsigned pitch,
2833 unsigned bpp)
2834 {
2835 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
2836 struct r600_texture *rsrc = (struct r600_texture*)src;
2837 struct r600_texture *rdst = (struct r600_texture*)dst;
2838 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2839 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2840 uint64_t base, addr;
2841
2842 dst_mode = rdst->surface.level[dst_level].mode;
2843 src_mode = rsrc->surface.level[src_level].mode;
2844 assert(dst_mode != src_mode);
2845
2846 y = 0;
2847 lbpp = util_logbase2(bpp);
2848 pitch_tile_max = ((pitch / bpp) / 8) - 1;
2849
2850 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
2851 /* T2L */
2852 array_mode = r600_array_mode(src_mode);
2853 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
2854 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2855 /* linear height must be the same as the slice tile max height, it's ok even
2856 * if the linear destination/source have smaller heigh as the size of the
2857 * dma packet will be using the copy_height which is always smaller or equal
2858 * to the linear height
2859 */
2860 height = u_minify(rsrc->resource.b.b.height0, src_level);
2861 detile = 1;
2862 x = src_x;
2863 y = src_y;
2864 z = src_z;
2865 base = rsrc->surface.level[src_level].offset;
2866 addr = rdst->surface.level[dst_level].offset;
2867 addr += rdst->surface.level[dst_level].slice_size * dst_z;
2868 addr += dst_y * pitch + dst_x * bpp;
2869 } else {
2870 /* L2T */
2871 array_mode = r600_array_mode(dst_mode);
2872 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
2873 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2874 /* linear height must be the same as the slice tile max height, it's ok even
2875 * if the linear destination/source have smaller heigh as the size of the
2876 * dma packet will be using the copy_height which is always smaller or equal
2877 * to the linear height
2878 */
2879 height = u_minify(rdst->resource.b.b.height0, dst_level);
2880 detile = 0;
2881 x = dst_x;
2882 y = dst_y;
2883 z = dst_z;
2884 base = rdst->surface.level[dst_level].offset;
2885 addr = rsrc->surface.level[src_level].offset;
2886 addr += rsrc->surface.level[src_level].slice_size * src_z;
2887 addr += src_y * pitch + src_x * bpp;
2888 }
2889 /* check that we are in dw/base alignment constraint */
2890 if (addr % 4 || base % 256) {
2891 return FALSE;
2892 }
2893
2894 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2895 * line in the blit. Compute max 8 line we can copy in the size limit
2896 */
2897 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2898 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2899 r600_need_dma_space(&rctx->b, ncopy * 7, &rdst->resource, &rsrc->resource);
2900
2901 for (i = 0; i < ncopy; i++) {
2902 cheight = cheight > copy_height ? copy_height : cheight;
2903 size = (cheight * pitch) / 4;
2904 /* emit reloc before writing cs so that cs is always in consistent state */
2905 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ,
2906 RADEON_PRIO_SDMA_TEXTURE);
2907 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE,
2908 RADEON_PRIO_SDMA_TEXTURE);
2909 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, 1, 0, size));
2910 radeon_emit(cs, base >> 8);
2911 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
2912 (lbpp << 24) | ((height - 1) << 10) |
2913 pitch_tile_max);
2914 radeon_emit(cs, (slice_tile_max << 12) | (z << 0));
2915 radeon_emit(cs, (x << 3) | (y << 17));
2916 radeon_emit(cs, addr & 0xfffffffc);
2917 radeon_emit(cs, (addr >> 32UL) & 0xff);
2918 copy_height -= cheight;
2919 addr += cheight * pitch;
2920 y += cheight;
2921 }
2922 r600_dma_emit_wait_idle(&rctx->b);
2923 return TRUE;
2924 }
2925
2926 static void r600_dma_copy(struct pipe_context *ctx,
2927 struct pipe_resource *dst,
2928 unsigned dst_level,
2929 unsigned dstx, unsigned dsty, unsigned dstz,
2930 struct pipe_resource *src,
2931 unsigned src_level,
2932 const struct pipe_box *src_box)
2933 {
2934 struct r600_context *rctx = (struct r600_context *)ctx;
2935 struct r600_texture *rsrc = (struct r600_texture*)src;
2936 struct r600_texture *rdst = (struct r600_texture*)dst;
2937 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2938 unsigned src_w, dst_w;
2939 unsigned src_x, src_y;
2940 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
2941
2942 if (rctx->b.dma.cs == NULL) {
2943 goto fallback;
2944 }
2945
2946 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
2947 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
2948 goto fallback;
2949
2950 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
2951 return;
2952 }
2953
2954 if (src_box->depth > 1 ||
2955 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
2956 dstz, rsrc, src_level, src_box))
2957 goto fallback;
2958
2959 src_x = util_format_get_nblocksx(src->format, src_box->x);
2960 dst_x = util_format_get_nblocksx(src->format, dst_x);
2961 src_y = util_format_get_nblocksy(src->format, src_box->y);
2962 dst_y = util_format_get_nblocksy(src->format, dst_y);
2963
2964 bpp = rdst->surface.bpe;
2965 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
2966 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
2967 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
2968 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
2969 copy_height = src_box->height / rsrc->surface.blk_h;
2970
2971 dst_mode = rdst->surface.level[dst_level].mode;
2972 src_mode = rsrc->surface.level[src_level].mode;
2973
2974 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
2975 /* strict requirement on r6xx/r7xx */
2976 goto fallback;
2977 }
2978 /* lot of constraint on alignment this should capture them all */
2979 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
2980 goto fallback;
2981 }
2982
2983 if (src_mode == dst_mode) {
2984 uint64_t dst_offset, src_offset, size;
2985
2986 /* simple dma blit would do NOTE code here assume :
2987 * src_box.x/y == 0
2988 * dst_x/y == 0
2989 * dst_pitch == src_pitch
2990 */
2991 src_offset= rsrc->surface.level[src_level].offset;
2992 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
2993 src_offset += src_y * src_pitch + src_x * bpp;
2994 dst_offset = rdst->surface.level[dst_level].offset;
2995 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
2996 dst_offset += dst_y * dst_pitch + dst_x * bpp;
2997 size = src_box->height * src_pitch;
2998 /* must be dw aligned */
2999 if (dst_offset % 4 || src_offset % 4 || size % 4) {
3000 goto fallback;
3001 }
3002 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
3003 } else {
3004 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3005 src, src_level, src_x, src_y, src_box->z,
3006 copy_height, dst_pitch, bpp)) {
3007 goto fallback;
3008 }
3009 }
3010 return;
3011
3012 fallback:
3013 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3014 src, src_level, src_box);
3015 }
3016
3017 void r600_init_state_functions(struct r600_context *rctx)
3018 {
3019 unsigned id = 1;
3020 unsigned i;
3021 /* !!!
3022 * To avoid GPU lockup registers must be emited in a specific order
3023 * (no kidding ...). The order below is important and have been
3024 * partialy infered from analyzing fglrx command stream.
3025 *
3026 * Don't reorder atom without carefully checking the effect (GPU lockup
3027 * or piglit regression).
3028 * !!!
3029 */
3030
3031 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3032
3033 /* shader const */
3034 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3035 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3036 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3037
3038 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3039 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3040 */
3041 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3042 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3043 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3044 /* resource */
3045 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3046 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3047 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3048 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3049
3050 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3051
3052 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3053 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3054 rctx->sample_mask.sample_mask = ~0;
3055
3056 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3057 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3058 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3059 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3060 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3061 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3062 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3063 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3064 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3065 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 9);
3066 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3067 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3068 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3069 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3070 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3071 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3072 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3073 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3074 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3075 for (i = 0; i < R600_NUM_HW_STAGES; i++)
3076 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3077 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3078 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3079
3080 rctx->b.b.create_blend_state = r600_create_blend_state;
3081 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3082 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3083 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3084 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3085 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3086 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3087 rctx->b.b.set_min_samples = r600_set_min_samples;
3088 rctx->b.b.get_sample_position = r600_get_sample_position;
3089 rctx->b.dma_copy = r600_dma_copy;
3090 }
3091 /* this function must be last */