2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * - fix mask for depth control & cull for query
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_upload_mgr.h>
40 #include <util/u_framebuffer.h>
41 #include <pipebuffer/pb_buffer.h>
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_state_inlines.h"
49 static void r600_draw_common(struct r600_drawl
*draw
)
51 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)draw
->ctx
;
52 struct r600_pipe_state
*rstate
;
53 struct r600_resource
*rbuffer
;
54 unsigned i
, j
, offset
, prim
;
55 u32 vgt_dma_index_type
, vgt_draw_initiator
, mask
;
56 struct pipe_vertex_buffer
*vertex_buffer
;
57 struct r600_draw rdraw
;
58 struct r600_pipe_state vgt
;
60 switch (draw
->index_size
) {
62 vgt_draw_initiator
= 0;
63 vgt_dma_index_type
= 0;
66 vgt_draw_initiator
= 0;
67 vgt_dma_index_type
= 1;
70 vgt_draw_initiator
= 2;
71 vgt_dma_index_type
= 0;
74 R600_ERR("unsupported index size %d\n", draw
->index_size
);
77 if (r600_conv_pipe_prim(draw
->mode
, &prim
))
81 /* rebuild vertex shader if input format changed */
82 if (r600_pipe_shader_update(&rctx
->context
, rctx
->vs_shader
))
84 if (r600_pipe_shader_update(&rctx
->context
, rctx
->ps_shader
))
87 for (i
= 0 ; i
< rctx
->vertex_elements
->count
; i
++) {
88 uint32_t word2
, format
;
90 rstate
= &rctx
->vs_resource
[i
];
91 rstate
->id
= R600_PIPE_STATE_RESOURCE
;
94 j
= rctx
->vertex_elements
->elements
[i
].vertex_buffer_index
;
95 vertex_buffer
= &rctx
->vertex_buffer
[j
];
96 rbuffer
= (struct r600_resource
*)vertex_buffer
->buffer
;
97 offset
= rctx
->vertex_elements
->elements
[i
].src_offset
+
98 vertex_buffer
->buffer_offset
+
99 r600_bo_offset(rbuffer
->bo
);
101 format
= r600_translate_vertex_data_type(rctx
->vertex_elements
->hw_format
[i
]);
103 word2
= format
| S_038008_STRIDE(vertex_buffer
->stride
);
105 r600_pipe_state_add_reg(rstate
, R_038000_RESOURCE0_WORD0
, offset
, 0xFFFFFFFF, rbuffer
->bo
);
106 r600_pipe_state_add_reg(rstate
, R_038004_RESOURCE0_WORD1
, rbuffer
->size
- offset
- 1, 0xFFFFFFFF, NULL
);
107 r600_pipe_state_add_reg(rstate
, R_038008_RESOURCE0_WORD2
, word2
, 0xFFFFFFFF, NULL
);
108 r600_pipe_state_add_reg(rstate
, R_03800C_RESOURCE0_WORD3
, 0x00000000, 0xFFFFFFFF, NULL
);
109 r600_pipe_state_add_reg(rstate
, R_038010_RESOURCE0_WORD4
, 0x00000000, 0xFFFFFFFF, NULL
);
110 r600_pipe_state_add_reg(rstate
, R_038014_RESOURCE0_WORD5
, 0x00000000, 0xFFFFFFFF, NULL
);
111 r600_pipe_state_add_reg(rstate
, R_038018_RESOURCE0_WORD6
, 0xC0000000, 0xFFFFFFFF, NULL
);
112 r600_context_pipe_state_set_vs_resource(&rctx
->ctx
, rstate
, i
);
116 for (int i
= 0; i
< rctx
->framebuffer
.nr_cbufs
; i
++) {
117 mask
|= (0xF << (i
* 4));
120 vgt
.id
= R600_PIPE_STATE_VGT
;
122 r600_pipe_state_add_reg(&vgt
, R_008958_VGT_PRIMITIVE_TYPE
, prim
, 0xFFFFFFFF, NULL
);
123 r600_pipe_state_add_reg(&vgt
, R_028408_VGT_INDX_OFFSET
, draw
->index_bias
, 0xFFFFFFFF, NULL
);
124 r600_pipe_state_add_reg(&vgt
, R_028400_VGT_MAX_VTX_INDX
, draw
->max_index
, 0xFFFFFFFF, NULL
);
125 r600_pipe_state_add_reg(&vgt
, R_028404_VGT_MIN_VTX_INDX
, draw
->min_index
, 0xFFFFFFFF, NULL
);
126 r600_pipe_state_add_reg(&vgt
, R_028238_CB_TARGET_MASK
, rctx
->cb_target_mask
& mask
, 0xFFFFFFFF, NULL
);
127 r600_pipe_state_add_reg(&vgt
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0, 0xFFFFFFFF, NULL
);
128 r600_pipe_state_add_reg(&vgt
, R_03CFF4_SQ_VTX_START_INST_LOC
, 0, 0xFFFFFFFF, NULL
);
129 /* build late state */
130 if (rctx
->rasterizer
&& rctx
->framebuffer
.zsbuf
) {
131 float offset_units
= rctx
->rasterizer
->offset_units
;
132 unsigned offset_db_fmt_cntl
= 0, depth
;
134 switch (rctx
->framebuffer
.zsbuf
->texture
->format
) {
135 case PIPE_FORMAT_Z24X8_UNORM
:
136 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
138 offset_units
*= 2.0f
;
140 case PIPE_FORMAT_Z32_FLOAT
:
142 offset_units
*= 1.0f
;
143 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
145 case PIPE_FORMAT_Z16_UNORM
:
147 offset_units
*= 4.0f
;
152 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
153 r600_pipe_state_add_reg(&vgt
,
154 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE
,
155 fui(rctx
->rasterizer
->offset_scale
), 0xFFFFFFFF, NULL
);
156 r600_pipe_state_add_reg(&vgt
,
157 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
158 fui(offset_units
), 0xFFFFFFFF, NULL
);
159 r600_pipe_state_add_reg(&vgt
,
160 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE
,
161 fui(rctx
->rasterizer
->offset_scale
), 0xFFFFFFFF, NULL
);
162 r600_pipe_state_add_reg(&vgt
,
163 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
164 fui(offset_units
), 0xFFFFFFFF, NULL
);
165 r600_pipe_state_add_reg(&vgt
,
166 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
167 offset_db_fmt_cntl
, 0xFFFFFFFF, NULL
);
169 r600_context_pipe_state_set(&rctx
->ctx
, &vgt
);
171 rdraw
.vgt_num_indices
= draw
->count
;
172 rdraw
.vgt_num_instances
= 1;
173 rdraw
.vgt_index_type
= vgt_dma_index_type
;
174 rdraw
.vgt_draw_initiator
= vgt_draw_initiator
;
175 rdraw
.indices
= NULL
;
176 if (draw
->index_buffer
) {
177 rbuffer
= (struct r600_resource
*)draw
->index_buffer
;
178 rdraw
.indices
= rbuffer
->bo
;
179 rdraw
.indices_bo_offset
= draw
->index_buffer_offset
;
181 r600_context_draw(&rctx
->ctx
, &rdraw
);
184 void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
186 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
187 struct r600_drawl draw
;
188 boolean translate
= FALSE
;
190 if (rctx
->vertex_elements
->incompatible_layout
) {
191 r600_begin_vertex_translate(rctx
);
195 if (rctx
->any_user_vbs
) {
196 r600_upload_user_buffers(rctx
);
197 rctx
->any_user_vbs
= FALSE
;
199 memset(&draw
, 0, sizeof(struct r600_drawl
));
201 draw
.mode
= info
->mode
;
202 draw
.start
= info
->start
;
203 draw
.count
= info
->count
;
204 if (info
->indexed
&& rctx
->index_buffer
.buffer
) {
205 draw
.start
+= rctx
->index_buffer
.offset
/ rctx
->index_buffer
.index_size
;
206 draw
.min_index
= info
->min_index
;
207 draw
.max_index
= info
->max_index
;
208 draw
.index_bias
= info
->index_bias
;
210 r600_translate_index_buffer(rctx
, &rctx
->index_buffer
.buffer
,
211 &rctx
->index_buffer
.index_size
,
215 draw
.index_size
= rctx
->index_buffer
.index_size
;
216 pipe_resource_reference(&draw
.index_buffer
, rctx
->index_buffer
.buffer
);
217 draw
.index_buffer_offset
= draw
.start
* draw
.index_size
;
219 r600_upload_index_buffer(rctx
, &draw
);
222 draw
.index_buffer
= NULL
;
223 draw
.min_index
= info
->min_index
;
224 draw
.max_index
= info
->max_index
;
225 draw
.index_bias
= info
->start
;
227 r600_draw_common(&draw
);
230 r600_end_vertex_translate(rctx
);
232 pipe_resource_reference(&draw
.index_buffer
, NULL
);
235 static void r600_set_blend_color(struct pipe_context
*ctx
,
236 const struct pipe_blend_color
*state
)
238 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
239 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
244 rstate
->id
= R600_PIPE_STATE_BLEND_COLOR
;
245 r600_pipe_state_add_reg(rstate
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]), 0xFFFFFFFF, NULL
);
246 r600_pipe_state_add_reg(rstate
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]), 0xFFFFFFFF, NULL
);
247 r600_pipe_state_add_reg(rstate
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]), 0xFFFFFFFF, NULL
);
248 r600_pipe_state_add_reg(rstate
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]), 0xFFFFFFFF, NULL
);
249 free(rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
]);
250 rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
] = rstate
;
251 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
254 static void *r600_create_blend_state(struct pipe_context
*ctx
,
255 const struct pipe_blend_state
*state
)
257 struct r600_pipe_blend
*blend
= CALLOC_STRUCT(r600_pipe_blend
);
258 struct r600_pipe_state
*rstate
;
259 u32 color_control
, target_mask
;
264 rstate
= &blend
->rstate
;
266 rstate
->id
= R600_PIPE_STATE_BLEND
;
269 color_control
= S_028808_PER_MRT_BLEND(1);
270 if (state
->logicop_enable
) {
271 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
273 color_control
|= (0xcc << 16);
275 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
276 if (state
->independent_blend_enable
) {
277 for (int i
= 0; i
< 8; i
++) {
278 if (state
->rt
[i
].blend_enable
) {
279 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
281 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
284 for (int i
= 0; i
< 8; i
++) {
285 if (state
->rt
[0].blend_enable
) {
286 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
288 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
291 blend
->cb_target_mask
= target_mask
;
292 r600_pipe_state_add_reg(rstate
, R_028808_CB_COLOR_CONTROL
,
293 color_control
, 0xFFFFFFFF, NULL
);
295 for (int i
= 0; i
< 8; i
++) {
296 unsigned eqRGB
= state
->rt
[i
].rgb_func
;
297 unsigned srcRGB
= state
->rt
[i
].rgb_src_factor
;
298 unsigned dstRGB
= state
->rt
[i
].rgb_dst_factor
;
300 unsigned eqA
= state
->rt
[i
].alpha_func
;
301 unsigned srcA
= state
->rt
[i
].alpha_src_factor
;
302 unsigned dstA
= state
->rt
[i
].alpha_dst_factor
;
305 if (!state
->rt
[i
].blend_enable
)
308 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
309 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
310 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
312 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
313 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
314 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
315 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
316 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
319 r600_pipe_state_add_reg(rstate
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, bc
, 0xFFFFFFFF, NULL
);
321 r600_pipe_state_add_reg(rstate
, R_028804_CB_BLEND_CONTROL
, bc
, 0xFFFFFFFF, NULL
);
327 static void *r600_create_dsa_state(struct pipe_context
*ctx
,
328 const struct pipe_depth_stencil_alpha_state
*state
)
330 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
331 unsigned db_depth_control
, alpha_test_control
, alpha_ref
, db_shader_control
;
332 unsigned stencil_ref_mask
, stencil_ref_mask_bf
, db_render_override
, db_render_control
;
334 if (rstate
== NULL
) {
338 rstate
->id
= R600_PIPE_STATE_DSA
;
339 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
340 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
341 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
342 * be set if shader use texkill instruction
344 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
345 stencil_ref_mask
= 0;
346 stencil_ref_mask_bf
= 0;
347 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
348 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
349 S_028800_ZFUNC(state
->depth
.func
);
352 if (state
->stencil
[0].enabled
) {
353 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
354 db_depth_control
|= S_028800_STENCILFUNC(r600_translate_ds_func(state
->stencil
[0].func
));
355 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
356 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
357 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
360 stencil_ref_mask
= S_028430_STENCILMASK(state
->stencil
[0].valuemask
) |
361 S_028430_STENCILWRITEMASK(state
->stencil
[0].writemask
);
362 if (state
->stencil
[1].enabled
) {
363 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
364 db_depth_control
|= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state
->stencil
[1].func
));
365 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
366 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
367 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
368 stencil_ref_mask_bf
= S_028434_STENCILMASK_BF(state
->stencil
[1].valuemask
) |
369 S_028434_STENCILWRITEMASK_BF(state
->stencil
[1].writemask
);
374 alpha_test_control
= 0;
376 if (state
->alpha
.enabled
) {
377 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
378 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
379 alpha_ref
= fui(state
->alpha
.ref_value
);
383 db_render_control
= 0;
384 db_render_override
= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
) |
385 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE
) |
386 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE
);
387 /* TODO db_render_override depends on query */
388 r600_pipe_state_add_reg(rstate
, R_028028_DB_STENCIL_CLEAR
, 0x00000000, 0xFFFFFFFF, NULL
);
389 r600_pipe_state_add_reg(rstate
, R_02802C_DB_DEPTH_CLEAR
, 0x3F800000, 0xFFFFFFFF, NULL
);
390 r600_pipe_state_add_reg(rstate
, R_028410_SX_ALPHA_TEST_CONTROL
, alpha_test_control
, 0xFFFFFFFF, NULL
);
391 r600_pipe_state_add_reg(rstate
,
392 R_028430_DB_STENCILREFMASK
, stencil_ref_mask
,
393 0xFFFFFFFF & C_028430_STENCILREF
, NULL
);
394 r600_pipe_state_add_reg(rstate
,
395 R_028434_DB_STENCILREFMASK_BF
, stencil_ref_mask_bf
,
396 0xFFFFFFFF & C_028434_STENCILREF_BF
, NULL
);
397 r600_pipe_state_add_reg(rstate
, R_028438_SX_ALPHA_REF
, alpha_ref
, 0xFFFFFFFF, NULL
);
398 r600_pipe_state_add_reg(rstate
, R_0286E0_SPI_FOG_FUNC_SCALE
, 0x00000000, 0xFFFFFFFF, NULL
);
399 r600_pipe_state_add_reg(rstate
, R_0286E4_SPI_FOG_FUNC_BIAS
, 0x00000000, 0xFFFFFFFF, NULL
);
400 r600_pipe_state_add_reg(rstate
, R_0286DC_SPI_FOG_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
401 r600_pipe_state_add_reg(rstate
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
, 0xFFFFFFFF, NULL
);
402 r600_pipe_state_add_reg(rstate
, R_02880C_DB_SHADER_CONTROL
, db_shader_control
, 0xFFFFFFBE, NULL
);
403 r600_pipe_state_add_reg(rstate
, R_028D0C_DB_RENDER_CONTROL
, db_render_control
, 0xFFFFFFFF, NULL
);
404 r600_pipe_state_add_reg(rstate
, R_028D10_DB_RENDER_OVERRIDE
, db_render_override
, 0xFFFFFFFF, NULL
);
405 r600_pipe_state_add_reg(rstate
, R_028D2C_DB_SRESULTS_COMPARE_STATE1
, 0x00000000, 0xFFFFFFFF, NULL
);
406 r600_pipe_state_add_reg(rstate
, R_028D30_DB_PRELOAD_CONTROL
, 0x00000000, 0xFFFFFFFF, NULL
);
407 r600_pipe_state_add_reg(rstate
, R_028D44_DB_ALPHA_TO_MASK
, 0x0000AA00, 0xFFFFFFFF, NULL
);
412 static void *r600_create_rs_state(struct pipe_context
*ctx
,
413 const struct pipe_rasterizer_state
*state
)
415 struct r600_pipe_rasterizer
*rs
= CALLOC_STRUCT(r600_pipe_rasterizer
);
416 struct r600_pipe_state
*rstate
;
418 unsigned prov_vtx
= 1, polygon_dual_mode
;
425 rstate
= &rs
->rstate
;
426 rs
->flatshade
= state
->flatshade
;
427 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
429 clip_rule
= state
->scissor
? 0xAAAA : 0xFFFF;
431 rs
->offset_units
= state
->offset_units
;
432 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
434 rstate
->id
= R600_PIPE_STATE_RASTERIZER
;
435 if (state
->flatshade_first
)
437 tmp
= S_0286D4_FLAT_SHADE_ENA(1);
438 if (state
->sprite_coord_enable
) {
439 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
440 S_0286D4_PNT_SPRITE_OVRD_X(2) |
441 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
442 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
443 S_0286D4_PNT_SPRITE_OVRD_W(1);
444 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
445 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
448 r600_pipe_state_add_reg(rstate
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
, 0xFFFFFFFF, NULL
);
450 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
451 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
452 r600_pipe_state_add_reg(rstate
, R_028814_PA_SU_SC_MODE_CNTL
,
453 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
454 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
455 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
456 S_028814_FACE(!state
->front_ccw
) |
457 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
458 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
459 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
460 S_028814_POLY_MODE(polygon_dual_mode
) |
461 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
462 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)), 0xFFFFFFFF, NULL
);
463 r600_pipe_state_add_reg(rstate
, R_02881C_PA_CL_VS_OUT_CNTL
,
464 S_02881C_USE_VTX_POINT_SIZE(state
->point_size_per_vertex
) |
465 S_02881C_VS_OUT_MISC_VEC_ENA(state
->point_size_per_vertex
), 0xFFFFFFFF, NULL
);
466 r600_pipe_state_add_reg(rstate
, R_028820_PA_CL_NANINF_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
467 /* point size 12.4 fixed point */
468 tmp
= (unsigned)(state
->point_size
* 8.0);
469 r600_pipe_state_add_reg(rstate
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
), 0xFFFFFFFF, NULL
);
470 r600_pipe_state_add_reg(rstate
, R_028A04_PA_SU_POINT_MINMAX
, 0x80000000, 0xFFFFFFFF, NULL
);
472 tmp
= (unsigned)(state
->line_width
* 8.0);
473 r600_pipe_state_add_reg(rstate
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
), 0xFFFFFFFF, NULL
);
475 r600_pipe_state_add_reg(rstate
, R_028A0C_PA_SC_LINE_STIPPLE
, 0x00000005, 0xFFFFFFFF, NULL
);
476 r600_pipe_state_add_reg(rstate
, R_028A48_PA_SC_MPASS_PS_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
477 r600_pipe_state_add_reg(rstate
, R_028C00_PA_SC_LINE_CNTL
, 0x00000400, 0xFFFFFFFF, NULL
);
478 r600_pipe_state_add_reg(rstate
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
479 r600_pipe_state_add_reg(rstate
, R_028C10_PA_CL_GB_VERT_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
480 r600_pipe_state_add_reg(rstate
, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
481 r600_pipe_state_add_reg(rstate
, R_028C18_PA_CL_GB_HORZ_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
482 r600_pipe_state_add_reg(rstate
, R_028DFC_PA_SU_POLY_OFFSET_CLAMP
, 0x00000000, 0xFFFFFFFF, NULL
);
483 r600_pipe_state_add_reg(rstate
, R_02820C_PA_SC_CLIPRECT_RULE
, clip_rule
, 0xFFFFFFFF, NULL
);
488 static void *r600_create_sampler_state(struct pipe_context
*ctx
,
489 const struct pipe_sampler_state
*state
)
491 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
494 if (rstate
== NULL
) {
498 rstate
->id
= R600_PIPE_STATE_SAMPLER
;
499 util_pack_color(state
->border_color
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
500 r600_pipe_state_add_reg(rstate
, R_03C000_SQ_TEX_SAMPLER_WORD0_0
,
501 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
502 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
503 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
504 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
)) |
505 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
)) |
506 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
507 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
508 S_03C000_BORDER_COLOR_TYPE(uc
.ui
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0), 0xFFFFFFFF, NULL
);
509 /* FIXME LOD it depends on texture base level ... */
510 r600_pipe_state_add_reg(rstate
, R_03C004_SQ_TEX_SAMPLER_WORD1_0
,
511 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
512 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
513 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6)), 0xFFFFFFFF, NULL
);
514 r600_pipe_state_add_reg(rstate
, R_03C008_SQ_TEX_SAMPLER_WORD2_0
, S_03C008_TYPE(1), 0xFFFFFFFF, NULL
);
516 r600_pipe_state_add_reg(rstate
, R_00A400_TD_PS_SAMPLER0_BORDER_RED
, fui(state
->border_color
[0]), 0xFFFFFFFF, NULL
);
517 r600_pipe_state_add_reg(rstate
, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN
, fui(state
->border_color
[1]), 0xFFFFFFFF, NULL
);
518 r600_pipe_state_add_reg(rstate
, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE
, fui(state
->border_color
[2]), 0xFFFFFFFF, NULL
);
519 r600_pipe_state_add_reg(rstate
, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA
, fui(state
->border_color
[3]), 0xFFFFFFFF, NULL
);
524 static struct pipe_sampler_view
*r600_create_sampler_view(struct pipe_context
*ctx
,
525 struct pipe_resource
*texture
,
526 const struct pipe_sampler_view
*state
)
528 struct r600_pipe_sampler_view
*resource
= CALLOC_STRUCT(r600_pipe_sampler_view
);
529 struct r600_pipe_state
*rstate
;
530 const struct util_format_description
*desc
;
531 struct r600_resource_texture
*tmp
;
532 struct r600_resource
*rbuffer
;
534 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
535 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
536 struct r600_bo
*bo
[2];
538 if (resource
== NULL
)
540 rstate
= &resource
->state
;
542 /* initialize base object */
543 resource
->base
= *state
;
544 resource
->base
.texture
= NULL
;
545 pipe_reference(NULL
, &texture
->reference
);
546 resource
->base
.texture
= texture
;
547 resource
->base
.reference
.count
= 1;
548 resource
->base
.context
= ctx
;
550 swizzle
[0] = state
->swizzle_r
;
551 swizzle
[1] = state
->swizzle_g
;
552 swizzle
[2] = state
->swizzle_b
;
553 swizzle
[3] = state
->swizzle_a
;
554 format
= r600_translate_texformat(state
->format
,
556 &word4
, &yuv_format
);
560 desc
= util_format_description(state
->format
);
562 R600_ERR("unknow format %d\n", state
->format
);
564 tmp
= (struct r600_resource_texture
*)texture
;
565 rbuffer
= &tmp
->resource
;
568 /* FIXME depth texture decompression */
570 r600_texture_depth_flush(ctx
, texture
);
571 tmp
= (struct r600_resource_texture
*)texture
;
572 rbuffer
= &tmp
->flushed_depth_texture
->resource
;
576 pitch
= align(tmp
->pitch_in_pixels
[0], 8);
578 array_mode
= tmp
->array_mode
[0];
579 tile_type
= tmp
->tile_type
;
582 /* FIXME properly handle first level != 0 */
583 r600_pipe_state_add_reg(rstate
, R_038000_RESOURCE0_WORD0
,
584 S_038000_DIM(r600_tex_dim(texture
->target
)) |
585 S_038000_TILE_MODE(array_mode
) |
586 S_038000_TILE_TYPE(tile_type
) |
587 S_038000_PITCH((pitch
/ 8) - 1) |
588 S_038000_TEX_WIDTH(texture
->width0
- 1), 0xFFFFFFFF, NULL
);
589 r600_pipe_state_add_reg(rstate
, R_038004_RESOURCE0_WORD1
,
590 S_038004_TEX_HEIGHT(texture
->height0
- 1) |
591 S_038004_TEX_DEPTH(texture
->depth0
- 1) |
592 S_038004_DATA_FORMAT(format
), 0xFFFFFFFF, NULL
);
593 r600_pipe_state_add_reg(rstate
, R_038008_RESOURCE0_WORD2
,
594 (tmp
->offset
[0] + r600_bo_offset(bo
[0])) >> 8, 0xFFFFFFFF, bo
[0]);
595 r600_pipe_state_add_reg(rstate
, R_03800C_RESOURCE0_WORD3
,
596 (tmp
->offset
[1] + r600_bo_offset(bo
[1])) >> 8, 0xFFFFFFFF, bo
[1]);
597 r600_pipe_state_add_reg(rstate
, R_038010_RESOURCE0_WORD4
,
598 word4
| S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM
) |
599 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO
) |
600 S_038010_REQUEST_SIZE(1) |
601 S_038010_BASE_LEVEL(state
->first_level
), 0xFFFFFFFF, NULL
);
602 r600_pipe_state_add_reg(rstate
, R_038014_RESOURCE0_WORD5
,
603 S_038014_LAST_LEVEL(state
->last_level
) |
604 S_038014_BASE_ARRAY(0) |
605 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL
);
606 r600_pipe_state_add_reg(rstate
, R_038018_RESOURCE0_WORD6
,
607 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
), 0xFFFFFFFF, NULL
);
609 return &resource
->base
;
612 static void r600_set_vs_sampler_view(struct pipe_context
*ctx
, unsigned count
,
613 struct pipe_sampler_view
**views
)
615 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
616 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
618 for (int i
= 0; i
< count
; i
++) {
620 r600_context_pipe_state_set_vs_resource(&rctx
->ctx
, &resource
[i
]->state
, i
+ PIPE_MAX_ATTRIBS
);
625 static void r600_set_ps_sampler_view(struct pipe_context
*ctx
, unsigned count
,
626 struct pipe_sampler_view
**views
)
628 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
629 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
632 for (i
= 0; i
< count
; i
++) {
633 if (&rctx
->ps_samplers
.views
[i
]->base
!= views
[i
]) {
635 r600_context_pipe_state_set_ps_resource(&rctx
->ctx
, &resource
[i
]->state
, i
);
637 r600_context_pipe_state_set_ps_resource(&rctx
->ctx
, NULL
, i
);
639 pipe_sampler_view_reference(
640 (struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
],
645 for (i
= count
; i
< NUM_TEX_UNITS
; i
++) {
646 if (rctx
->ps_samplers
.views
[i
]) {
647 r600_context_pipe_state_set_ps_resource(&rctx
->ctx
, NULL
, i
);
648 pipe_sampler_view_reference((struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
], NULL
);
651 rctx
->ps_samplers
.n_views
= count
;
654 static void r600_bind_ps_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
656 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
657 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
659 memcpy(rctx
->ps_samplers
.samplers
, states
, sizeof(void*) * count
);
660 rctx
->ps_samplers
.n_samplers
= count
;
662 for (int i
= 0; i
< count
; i
++) {
663 r600_context_pipe_state_set_ps_sampler(&rctx
->ctx
, rstates
[i
], i
);
667 static void r600_bind_vs_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
669 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
670 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
672 for (int i
= 0; i
< count
; i
++) {
673 r600_context_pipe_state_set_vs_sampler(&rctx
->ctx
, rstates
[i
], i
);
677 static void r600_set_clip_state(struct pipe_context
*ctx
,
678 const struct pipe_clip_state
*state
)
680 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
681 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
687 rstate
->id
= R600_PIPE_STATE_CLIP
;
688 for (int i
= 0; i
< state
->nr
; i
++) {
689 r600_pipe_state_add_reg(rstate
,
690 R_028E20_PA_CL_UCP0_X
+ i
* 4,
691 fui(state
->ucp
[i
][0]), 0xFFFFFFFF, NULL
);
692 r600_pipe_state_add_reg(rstate
,
693 R_028E24_PA_CL_UCP0_Y
+ i
* 4,
694 fui(state
->ucp
[i
][1]) , 0xFFFFFFFF, NULL
);
695 r600_pipe_state_add_reg(rstate
,
696 R_028E28_PA_CL_UCP0_Z
+ i
* 4,
697 fui(state
->ucp
[i
][2]), 0xFFFFFFFF, NULL
);
698 r600_pipe_state_add_reg(rstate
,
699 R_028E2C_PA_CL_UCP0_W
+ i
* 4,
700 fui(state
->ucp
[i
][3]), 0xFFFFFFFF, NULL
);
702 r600_pipe_state_add_reg(rstate
, R_028810_PA_CL_CLIP_CNTL
,
703 S_028810_PS_UCP_MODE(3) | ((1 << state
->nr
) - 1) |
704 S_028810_ZCLIP_NEAR_DISABLE(state
->depth_clamp
) |
705 S_028810_ZCLIP_FAR_DISABLE(state
->depth_clamp
), 0xFFFFFFFF, NULL
);
707 free(rctx
->states
[R600_PIPE_STATE_CLIP
]);
708 rctx
->states
[R600_PIPE_STATE_CLIP
] = rstate
;
709 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
712 static void r600_set_polygon_stipple(struct pipe_context
*ctx
,
713 const struct pipe_poly_stipple
*state
)
717 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
721 static void r600_set_scissor_state(struct pipe_context
*ctx
,
722 const struct pipe_scissor_state
*state
)
724 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
725 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
731 rstate
->id
= R600_PIPE_STATE_SCISSOR
;
732 tl
= S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
) | S_028240_WINDOW_OFFSET_DISABLE(1);
733 br
= S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
);
734 r600_pipe_state_add_reg(rstate
,
735 R_028210_PA_SC_CLIPRECT_0_TL
, tl
,
737 r600_pipe_state_add_reg(rstate
,
738 R_028214_PA_SC_CLIPRECT_0_BR
, br
,
740 r600_pipe_state_add_reg(rstate
,
741 R_028218_PA_SC_CLIPRECT_1_TL
, tl
,
743 r600_pipe_state_add_reg(rstate
,
744 R_02821C_PA_SC_CLIPRECT_1_BR
, br
,
746 r600_pipe_state_add_reg(rstate
,
747 R_028220_PA_SC_CLIPRECT_2_TL
, tl
,
749 r600_pipe_state_add_reg(rstate
,
750 R_028224_PA_SC_CLIPRECT_2_BR
, br
,
752 r600_pipe_state_add_reg(rstate
,
753 R_028228_PA_SC_CLIPRECT_3_TL
, tl
,
755 r600_pipe_state_add_reg(rstate
,
756 R_02822C_PA_SC_CLIPRECT_3_BR
, br
,
759 free(rctx
->states
[R600_PIPE_STATE_SCISSOR
]);
760 rctx
->states
[R600_PIPE_STATE_SCISSOR
] = rstate
;
761 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
764 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
765 const struct pipe_stencil_ref
*state
)
767 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
768 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
774 rctx
->stencil_ref
= *state
;
775 rstate
->id
= R600_PIPE_STATE_STENCIL_REF
;
776 tmp
= S_028430_STENCILREF(state
->ref_value
[0]);
777 r600_pipe_state_add_reg(rstate
,
778 R_028430_DB_STENCILREFMASK
, tmp
,
779 ~C_028430_STENCILREF
, NULL
);
780 tmp
= S_028434_STENCILREF_BF(state
->ref_value
[1]);
781 r600_pipe_state_add_reg(rstate
,
782 R_028434_DB_STENCILREFMASK_BF
, tmp
,
783 ~C_028434_STENCILREF_BF
, NULL
);
785 free(rctx
->states
[R600_PIPE_STATE_STENCIL_REF
]);
786 rctx
->states
[R600_PIPE_STATE_STENCIL_REF
] = rstate
;
787 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
790 static void r600_set_viewport_state(struct pipe_context
*ctx
,
791 const struct pipe_viewport_state
*state
)
793 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
794 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
799 rctx
->viewport
= *state
;
800 rstate
->id
= R600_PIPE_STATE_VIEWPORT
;
801 r600_pipe_state_add_reg(rstate
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 0x00000000, 0xFFFFFFFF, NULL
);
802 r600_pipe_state_add_reg(rstate
, R_0282D4_PA_SC_VPORT_ZMAX_0
, 0x3F800000, 0xFFFFFFFF, NULL
);
803 r600_pipe_state_add_reg(rstate
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]), 0xFFFFFFFF, NULL
);
804 r600_pipe_state_add_reg(rstate
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]), 0xFFFFFFFF, NULL
);
805 r600_pipe_state_add_reg(rstate
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]), 0xFFFFFFFF, NULL
);
806 r600_pipe_state_add_reg(rstate
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]), 0xFFFFFFFF, NULL
);
807 r600_pipe_state_add_reg(rstate
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]), 0xFFFFFFFF, NULL
);
808 r600_pipe_state_add_reg(rstate
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]), 0xFFFFFFFF, NULL
);
809 r600_pipe_state_add_reg(rstate
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F, 0xFFFFFFFF, NULL
);
811 free(rctx
->states
[R600_PIPE_STATE_VIEWPORT
]);
812 rctx
->states
[R600_PIPE_STATE_VIEWPORT
] = rstate
;
813 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
816 static void r600_cb(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
,
817 const struct pipe_framebuffer_state
*state
, int cb
)
819 struct r600_resource_texture
*rtex
;
820 struct r600_resource
*rbuffer
;
821 struct r600_surface
*surf
;
822 unsigned level
= state
->cbufs
[cb
]->level
;
823 unsigned pitch
, slice
;
825 unsigned format
, swap
, ntype
;
826 const struct util_format_description
*desc
;
827 struct r600_bo
*bo
[3];
829 surf
= (struct r600_surface
*)state
->cbufs
[cb
];
830 rtex
= (struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
;
831 rbuffer
= &rtex
->resource
;
836 pitch
= rtex
->pitch_in_pixels
[level
] / 8 - 1;
837 slice
= rtex
->pitch_in_pixels
[level
] * surf
->aligned_height
/ 64 - 1;
839 desc
= util_format_description(rtex
->resource
.base
.b
.format
);
840 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
841 ntype
= V_0280A0_NUMBER_SRGB
;
843 format
= r600_translate_colorformat(rtex
->resource
.base
.b
.format
);
844 swap
= r600_translate_colorswap(rtex
->resource
.base
.b
.format
);
845 color_info
= S_0280A0_FORMAT(format
) |
846 S_0280A0_COMP_SWAP(swap
) |
847 S_0280A0_ARRAY_MODE(rtex
->array_mode
[level
]) |
848 S_0280A0_BLEND_CLAMP(1) |
849 S_0280A0_NUMBER_TYPE(ntype
);
850 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
851 color_info
|= S_0280A0_SOURCE_FORMAT(1);
853 r600_pipe_state_add_reg(rstate
,
854 R_028040_CB_COLOR0_BASE
+ cb
* 4,
855 (state
->cbufs
[cb
]->offset
+ r600_bo_offset(bo
[0])) >> 8, 0xFFFFFFFF, bo
[0]);
856 r600_pipe_state_add_reg(rstate
,
857 R_0280A0_CB_COLOR0_INFO
+ cb
* 4,
858 color_info
, 0xFFFFFFFF, bo
[0]);
859 r600_pipe_state_add_reg(rstate
,
860 R_028060_CB_COLOR0_SIZE
+ cb
* 4,
861 S_028060_PITCH_TILE_MAX(pitch
) |
862 S_028060_SLICE_TILE_MAX(slice
),
864 r600_pipe_state_add_reg(rstate
,
865 R_028080_CB_COLOR0_VIEW
+ cb
* 4,
866 0x00000000, 0xFFFFFFFF, NULL
);
867 r600_pipe_state_add_reg(rstate
,
868 R_0280E0_CB_COLOR0_FRAG
+ cb
* 4,
869 r600_bo_offset(bo
[1]) >> 8, 0xFFFFFFFF, bo
[1]);
870 r600_pipe_state_add_reg(rstate
,
871 R_0280C0_CB_COLOR0_TILE
+ cb
* 4,
872 r600_bo_offset(bo
[2]) >> 8, 0xFFFFFFFF, bo
[2]);
873 r600_pipe_state_add_reg(rstate
,
874 R_028100_CB_COLOR0_MASK
+ cb
* 4,
875 0x00000000, 0xFFFFFFFF, NULL
);
878 static void r600_db(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
,
879 const struct pipe_framebuffer_state
*state
)
881 struct r600_resource_texture
*rtex
;
882 struct r600_resource
*rbuffer
;
883 struct r600_surface
*surf
;
885 unsigned pitch
, slice
, format
;
887 if (state
->zsbuf
== NULL
)
890 level
= state
->zsbuf
->level
;
892 surf
= (struct r600_surface
*)state
->zsbuf
;
893 rtex
= (struct r600_resource_texture
*)state
->zsbuf
->texture
;
895 rtex
->array_mode
[level
] = 2;
898 rbuffer
= &rtex
->resource
;
900 pitch
= rtex
->pitch_in_pixels
[level
] / 8 - 1;
901 slice
= rtex
->pitch_in_pixels
[level
] * surf
->aligned_height
/ 64 - 1;
902 format
= r600_translate_dbformat(state
->zsbuf
->texture
->format
);
904 r600_pipe_state_add_reg(rstate
, R_02800C_DB_DEPTH_BASE
,
905 (state
->zsbuf
->offset
+ r600_bo_offset(rbuffer
->bo
)) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
906 r600_pipe_state_add_reg(rstate
, R_028000_DB_DEPTH_SIZE
,
907 S_028000_PITCH_TILE_MAX(pitch
) | S_028000_SLICE_TILE_MAX(slice
),
909 r600_pipe_state_add_reg(rstate
, R_028004_DB_DEPTH_VIEW
, 0x00000000, 0xFFFFFFFF, NULL
);
910 r600_pipe_state_add_reg(rstate
, R_028010_DB_DEPTH_INFO
,
911 S_028010_ARRAY_MODE(rtex
->array_mode
[level
]) | S_028010_FORMAT(format
),
912 0xFFFFFFFF, rbuffer
->bo
);
913 r600_pipe_state_add_reg(rstate
, R_028D34_DB_PREFETCH_LIMIT
,
914 (surf
->aligned_height
/ 8) - 1, 0xFFFFFFFF, NULL
);
917 static void r600_set_framebuffer_state(struct pipe_context
*ctx
,
918 const struct pipe_framebuffer_state
*state
)
920 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
921 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
922 u32 shader_mask
, tl
, br
, shader_control
, target_mask
;
927 /* unreference old buffer and reference new one */
928 rstate
->id
= R600_PIPE_STATE_FRAMEBUFFER
;
930 util_copy_framebuffer_state(&rctx
->framebuffer
, state
);
932 rctx
->pframebuffer
= &rctx
->framebuffer
;
935 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
936 r600_cb(rctx
, rstate
, state
, i
);
939 r600_db(rctx
, rstate
, state
);
942 target_mask
= 0x00000000;
943 target_mask
= 0xFFFFFFFF;
946 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
947 target_mask
^= 0xf << (i
* 4);
948 shader_mask
|= 0xf << (i
* 4);
949 shader_control
|= 1 << i
;
951 tl
= S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
952 br
= S_028244_BR_X(state
->width
) | S_028244_BR_Y(state
->height
);
954 r600_pipe_state_add_reg(rstate
,
955 R_028030_PA_SC_SCREEN_SCISSOR_TL
, tl
,
957 r600_pipe_state_add_reg(rstate
,
958 R_028034_PA_SC_SCREEN_SCISSOR_BR
, br
,
960 r600_pipe_state_add_reg(rstate
,
961 R_028204_PA_SC_WINDOW_SCISSOR_TL
, tl
,
963 r600_pipe_state_add_reg(rstate
,
964 R_028208_PA_SC_WINDOW_SCISSOR_BR
, br
,
966 r600_pipe_state_add_reg(rstate
,
967 R_028240_PA_SC_GENERIC_SCISSOR_TL
, tl
,
969 r600_pipe_state_add_reg(rstate
,
970 R_028244_PA_SC_GENERIC_SCISSOR_BR
, br
,
972 r600_pipe_state_add_reg(rstate
,
973 R_028250_PA_SC_VPORT_SCISSOR_0_TL
, tl
,
975 r600_pipe_state_add_reg(rstate
,
976 R_028254_PA_SC_VPORT_SCISSOR_0_BR
, br
,
978 r600_pipe_state_add_reg(rstate
,
979 R_028200_PA_SC_WINDOW_OFFSET
, 0x00000000,
981 if (rctx
->family
>= CHIP_RV770
) {
982 r600_pipe_state_add_reg(rstate
,
983 R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA,
987 r600_pipe_state_add_reg(rstate
, R_0287A0_CB_SHADER_CONTROL
,
988 shader_control
, 0xFFFFFFFF, NULL
);
989 r600_pipe_state_add_reg(rstate
, R_028238_CB_TARGET_MASK
,
990 0x00000000, target_mask
, NULL
);
991 r600_pipe_state_add_reg(rstate
, R_02823C_CB_SHADER_MASK
,
992 shader_mask
, 0xFFFFFFFF, NULL
);
993 r600_pipe_state_add_reg(rstate
, R_028C04_PA_SC_AA_CONFIG
,
994 0x00000000, 0xFFFFFFFF, NULL
);
995 r600_pipe_state_add_reg(rstate
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
,
996 0x00000000, 0xFFFFFFFF, NULL
);
997 r600_pipe_state_add_reg(rstate
, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX
,
998 0x00000000, 0xFFFFFFFF, NULL
);
999 r600_pipe_state_add_reg(rstate
, R_028C30_CB_CLRCMP_CONTROL
,
1000 0x01000000, 0xFFFFFFFF, NULL
);
1001 r600_pipe_state_add_reg(rstate
, R_028C34_CB_CLRCMP_SRC
,
1002 0x00000000, 0xFFFFFFFF, NULL
);
1003 r600_pipe_state_add_reg(rstate
, R_028C38_CB_CLRCMP_DST
,
1004 0x000000FF, 0xFFFFFFFF, NULL
);
1005 r600_pipe_state_add_reg(rstate
, R_028C3C_CB_CLRCMP_MSK
,
1006 0xFFFFFFFF, 0xFFFFFFFF, NULL
);
1007 r600_pipe_state_add_reg(rstate
, R_028C48_PA_SC_AA_MASK
,
1008 0xFFFFFFFF, 0xFFFFFFFF, NULL
);
1010 free(rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
]);
1011 rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
] = rstate
;
1012 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1015 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
1016 struct pipe_resource
*buffer
)
1018 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1019 struct r600_resource
*rbuffer
= (struct r600_resource
*)buffer
;
1022 case PIPE_SHADER_VERTEX
:
1023 rctx
->vs_const_buffer
.nregs
= 0;
1024 r600_pipe_state_add_reg(&rctx
->vs_const_buffer
,
1025 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
1026 ALIGN_DIVUP(buffer
->width0
>> 4, 16),
1028 r600_pipe_state_add_reg(&rctx
->vs_const_buffer
,
1029 R_028980_ALU_CONST_CACHE_VS_0
,
1030 r600_bo_offset(rbuffer
->bo
) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
1031 r600_context_pipe_state_set(&rctx
->ctx
, &rctx
->vs_const_buffer
);
1033 case PIPE_SHADER_FRAGMENT
:
1034 rctx
->ps_const_buffer
.nregs
= 0;
1035 r600_pipe_state_add_reg(&rctx
->ps_const_buffer
,
1036 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
1037 ALIGN_DIVUP(buffer
->width0
>> 4, 16),
1039 r600_pipe_state_add_reg(&rctx
->ps_const_buffer
,
1040 R_028940_ALU_CONST_CACHE_PS_0
,
1041 r600_bo_offset(rbuffer
->bo
) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
1042 r600_context_pipe_state_set(&rctx
->ctx
, &rctx
->ps_const_buffer
);
1045 R600_ERR("unsupported %d\n", shader
);
1050 void r600_init_state_functions(struct r600_pipe_context
*rctx
)
1052 rctx
->context
.create_blend_state
= r600_create_blend_state
;
1053 rctx
->context
.create_depth_stencil_alpha_state
= r600_create_dsa_state
;
1054 rctx
->context
.create_fs_state
= r600_create_shader_state
;
1055 rctx
->context
.create_rasterizer_state
= r600_create_rs_state
;
1056 rctx
->context
.create_sampler_state
= r600_create_sampler_state
;
1057 rctx
->context
.create_sampler_view
= r600_create_sampler_view
;
1058 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
1059 rctx
->context
.create_vs_state
= r600_create_shader_state
;
1060 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
1061 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_state
;
1062 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_sampler
;
1063 rctx
->context
.bind_fs_state
= r600_bind_ps_shader
;
1064 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
1065 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
1066 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_sampler
;
1067 rctx
->context
.bind_vs_state
= r600_bind_vs_shader
;
1068 rctx
->context
.delete_blend_state
= r600_delete_state
;
1069 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
1070 rctx
->context
.delete_fs_state
= r600_delete_ps_shader
;
1071 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
1072 rctx
->context
.delete_sampler_state
= r600_delete_state
;
1073 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_element
;
1074 rctx
->context
.delete_vs_state
= r600_delete_vs_shader
;
1075 rctx
->context
.set_blend_color
= r600_set_blend_color
;
1076 rctx
->context
.set_clip_state
= r600_set_clip_state
;
1077 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1078 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_view
;
1079 rctx
->context
.set_framebuffer_state
= r600_set_framebuffer_state
;
1080 rctx
->context
.set_polygon_stipple
= r600_set_polygon_stipple
;
1081 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
1082 rctx
->context
.set_scissor_state
= r600_set_scissor_state
;
1083 rctx
->context
.set_stencil_ref
= r600_set_stencil_ref
;
1084 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1085 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1086 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_view
;
1087 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
1088 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1091 void r600_init_config(struct r600_pipe_context
*rctx
)
1106 int num_ps_stack_entries
;
1107 int num_vs_stack_entries
;
1108 int num_gs_stack_entries
;
1109 int num_es_stack_entries
;
1110 enum radeon_family family
;
1111 struct r600_pipe_state
*rstate
= &rctx
->config
;
1114 family
= r600_get_family(rctx
->radeon
);
1126 num_ps_threads
= 136;
1127 num_vs_threads
= 48;
1130 num_ps_stack_entries
= 128;
1131 num_vs_stack_entries
= 128;
1132 num_gs_stack_entries
= 0;
1133 num_es_stack_entries
= 0;
1142 num_ps_threads
= 144;
1143 num_vs_threads
= 40;
1146 num_ps_stack_entries
= 40;
1147 num_vs_stack_entries
= 40;
1148 num_gs_stack_entries
= 32;
1149 num_es_stack_entries
= 16;
1161 num_ps_threads
= 136;
1162 num_vs_threads
= 48;
1165 num_ps_stack_entries
= 40;
1166 num_vs_stack_entries
= 40;
1167 num_gs_stack_entries
= 32;
1168 num_es_stack_entries
= 16;
1176 num_ps_threads
= 136;
1177 num_vs_threads
= 48;
1180 num_ps_stack_entries
= 40;
1181 num_vs_stack_entries
= 40;
1182 num_gs_stack_entries
= 32;
1183 num_es_stack_entries
= 16;
1191 num_ps_threads
= 188;
1192 num_vs_threads
= 60;
1195 num_ps_stack_entries
= 256;
1196 num_vs_stack_entries
= 256;
1197 num_gs_stack_entries
= 0;
1198 num_es_stack_entries
= 0;
1207 num_ps_threads
= 188;
1208 num_vs_threads
= 60;
1211 num_ps_stack_entries
= 128;
1212 num_vs_stack_entries
= 128;
1213 num_gs_stack_entries
= 0;
1214 num_es_stack_entries
= 0;
1222 num_ps_threads
= 144;
1223 num_vs_threads
= 48;
1226 num_ps_stack_entries
= 128;
1227 num_vs_stack_entries
= 128;
1228 num_gs_stack_entries
= 0;
1229 num_es_stack_entries
= 0;
1233 rstate
->id
= R600_PIPE_STATE_CONFIG
;
1245 tmp
|= S_008C00_VC_ENABLE(1);
1248 tmp
|= S_008C00_DX9_CONSTS(0);
1249 tmp
|= S_008C00_ALU_INST_PREFER_VECTOR(1);
1250 tmp
|= S_008C00_PS_PRIO(ps_prio
);
1251 tmp
|= S_008C00_VS_PRIO(vs_prio
);
1252 tmp
|= S_008C00_GS_PRIO(gs_prio
);
1253 tmp
|= S_008C00_ES_PRIO(es_prio
);
1254 r600_pipe_state_add_reg(rstate
, R_008C00_SQ_CONFIG
, tmp
, 0xFFFFFFFF, NULL
);
1256 /* SQ_GPR_RESOURCE_MGMT_1 */
1258 tmp
|= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
1259 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
1260 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
1261 r600_pipe_state_add_reg(rstate
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
);
1263 /* SQ_GPR_RESOURCE_MGMT_2 */
1265 tmp
|= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
1266 tmp
|= S_008C08_NUM_GS_GPRS(num_es_gprs
);
1267 r600_pipe_state_add_reg(rstate
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
);
1269 /* SQ_THREAD_RESOURCE_MGMT */
1271 tmp
|= S_008C0C_NUM_PS_THREADS(num_ps_threads
);
1272 tmp
|= S_008C0C_NUM_VS_THREADS(num_vs_threads
);
1273 tmp
|= S_008C0C_NUM_GS_THREADS(num_gs_threads
);
1274 tmp
|= S_008C0C_NUM_ES_THREADS(num_es_threads
);
1275 r600_pipe_state_add_reg(rstate
, R_008C0C_SQ_THREAD_RESOURCE_MGMT
, tmp
, 0xFFFFFFFF, NULL
);
1277 /* SQ_STACK_RESOURCE_MGMT_1 */
1279 tmp
|= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
1280 tmp
|= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
1281 r600_pipe_state_add_reg(rstate
, R_008C10_SQ_STACK_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
);
1283 /* SQ_STACK_RESOURCE_MGMT_2 */
1285 tmp
|= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
1286 tmp
|= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
1287 r600_pipe_state_add_reg(rstate
, R_008C14_SQ_STACK_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
);
1289 r600_pipe_state_add_reg(rstate
, R_009714_VC_ENHANCE
, 0x00000000, 0xFFFFFFFF, NULL
);
1290 r600_pipe_state_add_reg(rstate
, R_028350_SX_MISC
, 0x00000000, 0xFFFFFFFF, NULL
);
1292 if (family
>= CHIP_RV770
) {
1293 r600_pipe_state_add_reg(rstate
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x00004000, 0xFFFFFFFF, NULL
);
1294 r600_pipe_state_add_reg(rstate
, R_009508_TA_CNTL_AUX
, 0x07000002, 0xFFFFFFFF, NULL
);
1295 r600_pipe_state_add_reg(rstate
, R_009830_DB_DEBUG
, 0x00000000, 0xFFFFFFFF, NULL
);
1296 r600_pipe_state_add_reg(rstate
, R_009838_DB_WATERMARKS
, 0x00420204, 0xFFFFFFFF, NULL
);
1297 r600_pipe_state_add_reg(rstate
, R_0286C8_SPI_THREAD_GROUPING
, 0x00000000, 0xFFFFFFFF, NULL
);
1298 r600_pipe_state_add_reg(rstate
, R_028A4C_PA_SC_MODE_CNTL
, 0x00514002, 0xFFFFFFFF, NULL
);
1300 r600_pipe_state_add_reg(rstate
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x00000000, 0xFFFFFFFF, NULL
);
1301 r600_pipe_state_add_reg(rstate
, R_009508_TA_CNTL_AUX
, 0x07000003, 0xFFFFFFFF, NULL
);
1302 r600_pipe_state_add_reg(rstate
, R_009830_DB_DEBUG
, 0x82000000, 0xFFFFFFFF, NULL
);
1303 r600_pipe_state_add_reg(rstate
, R_009838_DB_WATERMARKS
, 0x01020204, 0xFFFFFFFF, NULL
);
1304 r600_pipe_state_add_reg(rstate
, R_0286C8_SPI_THREAD_GROUPING
, 0x00000001, 0xFFFFFFFF, NULL
);
1305 r600_pipe_state_add_reg(rstate
, R_028A4C_PA_SC_MODE_CNTL
, 0x00004012, 0xFFFFFFFF, NULL
);
1307 r600_pipe_state_add_reg(rstate
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1308 r600_pipe_state_add_reg(rstate
, R_0288AC_SQ_GSVS_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1309 r600_pipe_state_add_reg(rstate
, R_0288B0_SQ_ESTMP_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1310 r600_pipe_state_add_reg(rstate
, R_0288B4_SQ_GSTMP_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1311 r600_pipe_state_add_reg(rstate
, R_0288B8_SQ_VSTMP_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1312 r600_pipe_state_add_reg(rstate
, R_0288BC_SQ_PSTMP_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1313 r600_pipe_state_add_reg(rstate
, R_0288C0_SQ_FBUF_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1314 r600_pipe_state_add_reg(rstate
, R_0288C4_SQ_REDUC_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1315 r600_pipe_state_add_reg(rstate
, R_0288C8_SQ_GS_VERT_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1316 r600_pipe_state_add_reg(rstate
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1317 r600_pipe_state_add_reg(rstate
, R_028A14_VGT_HOS_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1318 r600_pipe_state_add_reg(rstate
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0x00000000, 0xFFFFFFFF, NULL
);
1319 r600_pipe_state_add_reg(rstate
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0x00000000, 0xFFFFFFFF, NULL
);
1320 r600_pipe_state_add_reg(rstate
, R_028A20_VGT_HOS_REUSE_DEPTH
, 0x00000000, 0xFFFFFFFF, NULL
);
1321 r600_pipe_state_add_reg(rstate
, R_028A24_VGT_GROUP_PRIM_TYPE
, 0x00000000, 0xFFFFFFFF, NULL
);
1322 r600_pipe_state_add_reg(rstate
, R_028A28_VGT_GROUP_FIRST_DECR
, 0x00000000, 0xFFFFFFFF, NULL
);
1323 r600_pipe_state_add_reg(rstate
, R_028A2C_VGT_GROUP_DECR
, 0x00000000, 0xFFFFFFFF, NULL
);
1324 r600_pipe_state_add_reg(rstate
, R_028A30_VGT_GROUP_VECT_0_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1325 r600_pipe_state_add_reg(rstate
, R_028A34_VGT_GROUP_VECT_1_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1326 r600_pipe_state_add_reg(rstate
, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1327 r600_pipe_state_add_reg(rstate
, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1328 r600_pipe_state_add_reg(rstate
, R_028A40_VGT_GS_MODE
, 0x00000000, 0xFFFFFFFF, NULL
);
1329 r600_pipe_state_add_reg(rstate
, R_028AB0_VGT_STRMOUT_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
1330 r600_pipe_state_add_reg(rstate
, R_028AB4_VGT_REUSE_OFF
, 0x00000001, 0xFFFFFFFF, NULL
);
1331 r600_pipe_state_add_reg(rstate
, R_028AB8_VGT_VTX_CNT_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
1332 r600_pipe_state_add_reg(rstate
, R_028B20_VGT_STRMOUT_BUFFER_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
1334 r600_pipe_state_add_reg(rstate
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, 0x00000000, 0xFFFFFFFF, NULL
);
1335 r600_pipe_state_add_reg(rstate
, R_028A84_VGT_PRIMITIVEID_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
1336 r600_pipe_state_add_reg(rstate
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
1337 r600_pipe_state_add_reg(rstate
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 0x00000000, 0xFFFFFFFF, NULL
);
1338 r600_pipe_state_add_reg(rstate
, R_028AA4_VGT_INSTANCE_STEP_RATE_1
, 0x00000000, 0xFFFFFFFF, NULL
);
1339 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1342 void *r600_create_db_flush_dsa(struct r600_pipe_context
*rctx
)
1344 struct pipe_depth_stencil_alpha_state dsa
;
1345 struct r600_pipe_state
*rstate
;
1346 boolean quirk
= false;
1348 if (rctx
->family
== CHIP_RV610
|| rctx
->family
== CHIP_RV630
||
1349 rctx
->family
== CHIP_RV620
|| rctx
->family
== CHIP_RV635
)
1352 memset(&dsa
, 0, sizeof(dsa
));
1355 dsa
.depth
.enabled
= 1;
1356 dsa
.depth
.func
= PIPE_FUNC_LEQUAL
;
1357 dsa
.stencil
[0].enabled
= 1;
1358 dsa
.stencil
[0].func
= PIPE_FUNC_ALWAYS
;
1359 dsa
.stencil
[0].zpass_op
= PIPE_STENCIL_OP_KEEP
;
1360 dsa
.stencil
[0].zfail_op
= PIPE_STENCIL_OP_INCR
;
1361 dsa
.stencil
[0].writemask
= 0xff;
1364 rstate
= rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
1365 r600_pipe_state_add_reg(rstate
,
1366 R_02880C_DB_SHADER_CONTROL
,
1368 S_02880C_DUAL_EXPORT_ENABLE(1), NULL
);
1369 r600_pipe_state_add_reg(rstate
,
1370 R_028D0C_DB_RENDER_CONTROL
,
1371 S_028D0C_DEPTH_COPY_ENABLE(1) |
1372 S_028D0C_STENCIL_COPY_ENABLE(1) |
1373 S_028D0C_COPY_CENTROID(1),
1374 S_028D0C_DEPTH_COPY_ENABLE(1) |
1375 S_028D0C_STENCIL_COPY_ENABLE(1) |
1376 S_028D0C_COPY_CENTROID(1), NULL
);