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r600g: update polygon offset only when rasterizer or zbuffer change
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_upload_mgr.h>
40 #include <util/u_framebuffer.h>
41 #include <pipebuffer/pb_buffer.h>
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_state_inlines.h"
48
49 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
50 {
51 struct r600_pipe_state state;
52
53 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
54 state.nregs = 0;
55 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
56 float offset_units = rctx->rasterizer->offset_units;
57 unsigned offset_db_fmt_cntl = 0, depth;
58
59 switch (rctx->framebuffer.zsbuf->texture->format) {
60 case PIPE_FORMAT_Z24X8_UNORM:
61 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
62 depth = -24;
63 offset_units *= 2.0f;
64 break;
65 case PIPE_FORMAT_Z32_FLOAT:
66 depth = -23;
67 offset_units *= 1.0f;
68 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
69 break;
70 case PIPE_FORMAT_Z16_UNORM:
71 depth = -16;
72 offset_units *= 4.0f;
73 break;
74 default:
75 return;
76 }
77 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
78 r600_pipe_state_add_reg(&state,
79 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
80 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
81 r600_pipe_state_add_reg(&state,
82 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
83 fui(offset_units), 0xFFFFFFFF, NULL);
84 r600_pipe_state_add_reg(&state,
85 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
86 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
87 r600_pipe_state_add_reg(&state,
88 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
89 fui(offset_units), 0xFFFFFFFF, NULL);
90 r600_pipe_state_add_reg(&state,
91 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
92 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
93 r600_context_pipe_state_set(&rctx->ctx, &state);
94 }
95 }
96
97 static void r600_draw_common(struct r600_drawl *draw)
98 {
99 struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
100 struct r600_pipe_state *rstate;
101 struct r600_resource *rbuffer;
102 unsigned i, j, offset, prim;
103 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
104 struct pipe_vertex_buffer *vertex_buffer;
105 struct r600_draw rdraw;
106 struct r600_pipe_state vgt;
107
108 switch (draw->index_size) {
109 case 2:
110 vgt_draw_initiator = 0;
111 vgt_dma_index_type = 0;
112 break;
113 case 4:
114 vgt_draw_initiator = 0;
115 vgt_dma_index_type = 1;
116 break;
117 case 0:
118 vgt_draw_initiator = 2;
119 vgt_dma_index_type = 0;
120 break;
121 default:
122 R600_ERR("unsupported index size %d\n", draw->index_size);
123 return;
124 }
125 if (r600_conv_pipe_prim(draw->mode, &prim))
126 return;
127
128
129 /* rebuild vertex shader if input format changed */
130 if (r600_pipe_shader_update(&rctx->context, rctx->vs_shader))
131 return;
132 if (r600_pipe_shader_update(&rctx->context, rctx->ps_shader))
133 return;
134
135 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
136 uint32_t word2, format;
137
138 rstate = &rctx->vs_resource[i];
139 rstate->id = R600_PIPE_STATE_RESOURCE;
140 rstate->nregs = 0;
141
142 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
143 vertex_buffer = &rctx->vertex_buffer[j];
144 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
145 offset = rctx->vertex_elements->elements[i].src_offset +
146 vertex_buffer->buffer_offset +
147 r600_bo_offset(rbuffer->bo);
148
149 format = r600_translate_vertex_data_type(rctx->vertex_elements->hw_format[i]);
150
151 word2 = format | S_038008_STRIDE(vertex_buffer->stride);
152
153 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
154 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
155 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2, word2, 0xFFFFFFFF, NULL);
156 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3, 0x00000000, 0xFFFFFFFF, NULL);
157 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
158 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
159 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6, 0xC0000000, 0xFFFFFFFF, NULL);
160 r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
161 }
162
163 mask = 0;
164 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
165 mask |= (0xF << (i * 4));
166 }
167
168 vgt.id = R600_PIPE_STATE_VGT;
169 vgt.nregs = 0;
170 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
171 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw->index_bias, 0xFFFFFFFF, NULL);
172 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw->max_index, 0xFFFFFFFF, NULL);
173 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw->min_index, 0xFFFFFFFF, NULL);
174 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
175 r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
176 r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
177 r600_context_pipe_state_set(&rctx->ctx, &vgt);
178
179 rdraw.vgt_num_indices = draw->count;
180 rdraw.vgt_num_instances = 1;
181 rdraw.vgt_index_type = vgt_dma_index_type;
182 rdraw.vgt_draw_initiator = vgt_draw_initiator;
183 rdraw.indices = NULL;
184 if (draw->index_buffer) {
185 rbuffer = (struct r600_resource*)draw->index_buffer;
186 rdraw.indices = rbuffer->bo;
187 rdraw.indices_bo_offset = draw->index_buffer_offset;
188 }
189 r600_context_draw(&rctx->ctx, &rdraw);
190 }
191
192 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
193 {
194 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
195 struct r600_drawl draw;
196 boolean translate = FALSE;
197
198 if (rctx->vertex_elements->incompatible_layout) {
199 r600_begin_vertex_translate(rctx);
200 translate = TRUE;
201 }
202
203 if (rctx->any_user_vbs) {
204 r600_upload_user_buffers(rctx);
205 rctx->any_user_vbs = FALSE;
206 }
207 memset(&draw, 0, sizeof(struct r600_drawl));
208 draw.ctx = ctx;
209 draw.mode = info->mode;
210 draw.start = info->start;
211 draw.count = info->count;
212 if (info->indexed && rctx->index_buffer.buffer) {
213 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
214 draw.min_index = info->min_index;
215 draw.max_index = info->max_index;
216 draw.index_bias = info->index_bias;
217
218 r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
219 &rctx->index_buffer.index_size,
220 &draw.start,
221 info->count);
222
223 draw.index_size = rctx->index_buffer.index_size;
224 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
225 draw.index_buffer_offset = draw.start * draw.index_size;
226 draw.start = 0;
227 r600_upload_index_buffer(rctx, &draw);
228 } else {
229 draw.index_size = 0;
230 draw.index_buffer = NULL;
231 draw.min_index = info->min_index;
232 draw.max_index = info->max_index;
233 draw.index_bias = info->start;
234 }
235 r600_draw_common(&draw);
236
237 if (translate)
238 r600_end_vertex_translate(rctx);
239
240 pipe_resource_reference(&draw.index_buffer, NULL);
241 }
242
243 static void r600_set_blend_color(struct pipe_context *ctx,
244 const struct pipe_blend_color *state)
245 {
246 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
247 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
248
249 if (rstate == NULL)
250 return;
251
252 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
253 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
254 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
255 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
256 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
257 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
258 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
259 r600_context_pipe_state_set(&rctx->ctx, rstate);
260 }
261
262 static void *r600_create_blend_state(struct pipe_context *ctx,
263 const struct pipe_blend_state *state)
264 {
265 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
266 struct r600_pipe_state *rstate;
267 u32 color_control, target_mask;
268
269 if (blend == NULL) {
270 return NULL;
271 }
272 rstate = &blend->rstate;
273
274 rstate->id = R600_PIPE_STATE_BLEND;
275
276 target_mask = 0;
277 color_control = S_028808_PER_MRT_BLEND(1);
278 if (state->logicop_enable) {
279 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
280 } else {
281 color_control |= (0xcc << 16);
282 }
283 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
284 if (state->independent_blend_enable) {
285 for (int i = 0; i < 8; i++) {
286 if (state->rt[i].blend_enable) {
287 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
288 }
289 target_mask |= (state->rt[i].colormask << (4 * i));
290 }
291 } else {
292 for (int i = 0; i < 8; i++) {
293 if (state->rt[0].blend_enable) {
294 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
295 }
296 target_mask |= (state->rt[0].colormask << (4 * i));
297 }
298 }
299 blend->cb_target_mask = target_mask;
300 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
301 color_control, 0xFFFFFFFF, NULL);
302
303 for (int i = 0; i < 8; i++) {
304 unsigned eqRGB = state->rt[i].rgb_func;
305 unsigned srcRGB = state->rt[i].rgb_src_factor;
306 unsigned dstRGB = state->rt[i].rgb_dst_factor;
307
308 unsigned eqA = state->rt[i].alpha_func;
309 unsigned srcA = state->rt[i].alpha_src_factor;
310 unsigned dstA = state->rt[i].alpha_dst_factor;
311 uint32_t bc = 0;
312
313 if (!state->rt[i].blend_enable)
314 continue;
315
316 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
317 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
318 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
319
320 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
321 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
322 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
323 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
324 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
325 }
326
327 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
328 if (i == 0) {
329 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
330 }
331 }
332 return rstate;
333 }
334
335 static void *r600_create_dsa_state(struct pipe_context *ctx,
336 const struct pipe_depth_stencil_alpha_state *state)
337 {
338 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
339 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
340 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
341
342 if (rstate == NULL) {
343 return NULL;
344 }
345
346 rstate->id = R600_PIPE_STATE_DSA;
347 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
348 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
349 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
350 * be set if shader use texkill instruction
351 */
352 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
353 stencil_ref_mask = 0;
354 stencil_ref_mask_bf = 0;
355 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
356 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
357 S_028800_ZFUNC(state->depth.func);
358
359 /* stencil */
360 if (state->stencil[0].enabled) {
361 db_depth_control |= S_028800_STENCIL_ENABLE(1);
362 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
363 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
364 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
365 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
366
367
368 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
369 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
370 if (state->stencil[1].enabled) {
371 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
372 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
373 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
374 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
375 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
376 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
377 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
378 }
379 }
380
381 /* alpha */
382 alpha_test_control = 0;
383 alpha_ref = 0;
384 if (state->alpha.enabled) {
385 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
386 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
387 alpha_ref = fui(state->alpha.ref_value);
388 }
389
390 /* misc */
391 db_render_control = 0;
392 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
393 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
394 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
395 /* TODO db_render_override depends on query */
396 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
397 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
398 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
399 r600_pipe_state_add_reg(rstate,
400 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
401 0xFFFFFFFF & C_028430_STENCILREF, NULL);
402 r600_pipe_state_add_reg(rstate,
403 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
404 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
405 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
406 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
407 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
408 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
409 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
410 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
411 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
412 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
413 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
414 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
415 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
416
417 return rstate;
418 }
419
420 static void *r600_create_rs_state(struct pipe_context *ctx,
421 const struct pipe_rasterizer_state *state)
422 {
423 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
424 struct r600_pipe_state *rstate;
425 unsigned tmp;
426 unsigned prov_vtx = 1, polygon_dual_mode;
427 unsigned clip_rule;
428
429 if (rs == NULL) {
430 return NULL;
431 }
432
433 rstate = &rs->rstate;
434 rs->flatshade = state->flatshade;
435 rs->sprite_coord_enable = state->sprite_coord_enable;
436
437 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
438 /* offset */
439 rs->offset_units = state->offset_units;
440 rs->offset_scale = state->offset_scale * 12.0f;
441
442 rstate->id = R600_PIPE_STATE_RASTERIZER;
443 if (state->flatshade_first)
444 prov_vtx = 0;
445 tmp = S_0286D4_FLAT_SHADE_ENA(1);
446 if (state->sprite_coord_enable) {
447 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
448 S_0286D4_PNT_SPRITE_OVRD_X(2) |
449 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
450 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
451 S_0286D4_PNT_SPRITE_OVRD_W(1);
452 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
453 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
454 }
455 }
456 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
457
458 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
459 state->fill_back != PIPE_POLYGON_MODE_FILL);
460 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
461 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
462 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
463 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
464 S_028814_FACE(!state->front_ccw) |
465 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
466 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
467 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
468 S_028814_POLY_MODE(polygon_dual_mode) |
469 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
470 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
471 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
472 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
473 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
474 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
475 /* point size 12.4 fixed point */
476 tmp = (unsigned)(state->point_size * 8.0);
477 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
478 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
479
480 tmp = (unsigned)state->line_width * 8;
481 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
482
483 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
484 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
485 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
486
487 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
488 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
489 0xFFFFFFFF, NULL);
490
491 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
492 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
493 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
494 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
495 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
496 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
497
498 return rstate;
499 }
500
501 static void *r600_create_sampler_state(struct pipe_context *ctx,
502 const struct pipe_sampler_state *state)
503 {
504 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
505 union util_color uc;
506
507 if (rstate == NULL) {
508 return NULL;
509 }
510
511 rstate->id = R600_PIPE_STATE_SAMPLER;
512 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
513 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
514 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
515 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
516 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
517 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
518 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
519 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
520 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
521 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
522 /* FIXME LOD it depends on texture base level ... */
523 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
524 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
525 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
526 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
527 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
528 if (uc.ui) {
529 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
530 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
531 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
532 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
533 }
534 return rstate;
535 }
536
537 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
538 struct pipe_resource *texture,
539 const struct pipe_sampler_view *state)
540 {
541 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
542 struct r600_pipe_state *rstate;
543 const struct util_format_description *desc;
544 struct r600_resource_texture *tmp;
545 struct r600_resource *rbuffer;
546 unsigned format;
547 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
548 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
549 struct r600_bo *bo[2];
550
551 if (resource == NULL)
552 return NULL;
553 rstate = &resource->state;
554
555 /* initialize base object */
556 resource->base = *state;
557 resource->base.texture = NULL;
558 pipe_reference(NULL, &texture->reference);
559 resource->base.texture = texture;
560 resource->base.reference.count = 1;
561 resource->base.context = ctx;
562
563 swizzle[0] = state->swizzle_r;
564 swizzle[1] = state->swizzle_g;
565 swizzle[2] = state->swizzle_b;
566 swizzle[3] = state->swizzle_a;
567 format = r600_translate_texformat(state->format,
568 swizzle,
569 &word4, &yuv_format);
570 if (format == ~0) {
571 format = 0;
572 }
573 desc = util_format_description(state->format);
574 if (desc == NULL) {
575 R600_ERR("unknow format %d\n", state->format);
576 }
577 tmp = (struct r600_resource_texture*)texture;
578 rbuffer = &tmp->resource;
579 bo[0] = rbuffer->bo;
580 bo[1] = rbuffer->bo;
581 /* FIXME depth texture decompression */
582 if (tmp->depth) {
583 r600_texture_depth_flush(ctx, texture);
584 tmp = (struct r600_resource_texture*)texture;
585 rbuffer = &tmp->flushed_depth_texture->resource;
586 bo[0] = rbuffer->bo;
587 bo[1] = rbuffer->bo;
588 }
589 pitch = align(tmp->pitch_in_pixels[0], 8);
590 if (tmp->tiled) {
591 array_mode = tmp->array_mode[0];
592 tile_type = tmp->tile_type;
593 }
594
595 /* FIXME properly handle first level != 0 */
596 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
597 S_038000_DIM(r600_tex_dim(texture->target)) |
598 S_038000_TILE_MODE(array_mode) |
599 S_038000_TILE_TYPE(tile_type) |
600 S_038000_PITCH((pitch / 8) - 1) |
601 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
602 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
603 S_038004_TEX_HEIGHT(texture->height0 - 1) |
604 S_038004_TEX_DEPTH(texture->depth0 - 1) |
605 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
606 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
607 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
608 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
609 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
610 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
611 word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
612 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
613 S_038010_REQUEST_SIZE(1) |
614 S_038010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
615 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
616 S_038014_LAST_LEVEL(state->u.tex.last_level) |
617 S_038014_BASE_ARRAY(0) |
618 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
619 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
620 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
621
622 return &resource->base;
623 }
624
625 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
626 struct pipe_sampler_view **views)
627 {
628 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
629 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
630
631 for (int i = 0; i < count; i++) {
632 if (resource[i]) {
633 r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i);
634 }
635 }
636 }
637
638 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
639 struct pipe_sampler_view **views)
640 {
641 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
642 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
643 int i;
644
645 for (i = 0; i < count; i++) {
646 if (&rctx->ps_samplers.views[i]->base != views[i]) {
647 if (resource[i])
648 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
649 else
650 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
651
652 pipe_sampler_view_reference(
653 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
654 views[i]);
655
656 }
657 }
658 for (i = count; i < NUM_TEX_UNITS; i++) {
659 if (rctx->ps_samplers.views[i]) {
660 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
661 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
662 }
663 }
664 rctx->ps_samplers.n_views = count;
665 }
666
667 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
668 {
669 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
670 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
671
672 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
673 rctx->ps_samplers.n_samplers = count;
674
675 for (int i = 0; i < count; i++) {
676 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
677 }
678 }
679
680 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
681 {
682 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
683 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
684
685 for (int i = 0; i < count; i++) {
686 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
687 }
688 }
689
690 static void r600_set_clip_state(struct pipe_context *ctx,
691 const struct pipe_clip_state *state)
692 {
693 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
694 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
695
696 if (rstate == NULL)
697 return;
698
699 rctx->clip = *state;
700 rstate->id = R600_PIPE_STATE_CLIP;
701 for (int i = 0; i < state->nr; i++) {
702 r600_pipe_state_add_reg(rstate,
703 R_028E20_PA_CL_UCP0_X + i * 16,
704 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
705 r600_pipe_state_add_reg(rstate,
706 R_028E24_PA_CL_UCP0_Y + i * 16,
707 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
708 r600_pipe_state_add_reg(rstate,
709 R_028E28_PA_CL_UCP0_Z + i * 16,
710 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
711 r600_pipe_state_add_reg(rstate,
712 R_028E2C_PA_CL_UCP0_W + i * 16,
713 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
714 }
715 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
716 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
717 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
718 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
719
720 free(rctx->states[R600_PIPE_STATE_CLIP]);
721 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
722 r600_context_pipe_state_set(&rctx->ctx, rstate);
723 }
724
725 static void r600_set_polygon_stipple(struct pipe_context *ctx,
726 const struct pipe_poly_stipple *state)
727 {
728 }
729
730 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
731 {
732 }
733
734 static void r600_set_scissor_state(struct pipe_context *ctx,
735 const struct pipe_scissor_state *state)
736 {
737 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
738 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
739 u32 tl, br;
740
741 if (rstate == NULL)
742 return;
743
744 rstate->id = R600_PIPE_STATE_SCISSOR;
745 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
746 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
747 r600_pipe_state_add_reg(rstate,
748 R_028210_PA_SC_CLIPRECT_0_TL, tl,
749 0xFFFFFFFF, NULL);
750 r600_pipe_state_add_reg(rstate,
751 R_028214_PA_SC_CLIPRECT_0_BR, br,
752 0xFFFFFFFF, NULL);
753 r600_pipe_state_add_reg(rstate,
754 R_028218_PA_SC_CLIPRECT_1_TL, tl,
755 0xFFFFFFFF, NULL);
756 r600_pipe_state_add_reg(rstate,
757 R_02821C_PA_SC_CLIPRECT_1_BR, br,
758 0xFFFFFFFF, NULL);
759 r600_pipe_state_add_reg(rstate,
760 R_028220_PA_SC_CLIPRECT_2_TL, tl,
761 0xFFFFFFFF, NULL);
762 r600_pipe_state_add_reg(rstate,
763 R_028224_PA_SC_CLIPRECT_2_BR, br,
764 0xFFFFFFFF, NULL);
765 r600_pipe_state_add_reg(rstate,
766 R_028228_PA_SC_CLIPRECT_3_TL, tl,
767 0xFFFFFFFF, NULL);
768 r600_pipe_state_add_reg(rstate,
769 R_02822C_PA_SC_CLIPRECT_3_BR, br,
770 0xFFFFFFFF, NULL);
771
772 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
773 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
774 r600_context_pipe_state_set(&rctx->ctx, rstate);
775 }
776
777 static void r600_set_stencil_ref(struct pipe_context *ctx,
778 const struct pipe_stencil_ref *state)
779 {
780 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
781 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
782 u32 tmp;
783
784 if (rstate == NULL)
785 return;
786
787 rctx->stencil_ref = *state;
788 rstate->id = R600_PIPE_STATE_STENCIL_REF;
789 tmp = S_028430_STENCILREF(state->ref_value[0]);
790 r600_pipe_state_add_reg(rstate,
791 R_028430_DB_STENCILREFMASK, tmp,
792 ~C_028430_STENCILREF, NULL);
793 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
794 r600_pipe_state_add_reg(rstate,
795 R_028434_DB_STENCILREFMASK_BF, tmp,
796 ~C_028434_STENCILREF_BF, NULL);
797
798 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
799 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
800 r600_context_pipe_state_set(&rctx->ctx, rstate);
801 }
802
803 static void r600_set_viewport_state(struct pipe_context *ctx,
804 const struct pipe_viewport_state *state)
805 {
806 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
807 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
808
809 if (rstate == NULL)
810 return;
811
812 rctx->viewport = *state;
813 rstate->id = R600_PIPE_STATE_VIEWPORT;
814 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
815 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
816 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
817 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
818 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
819 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
820 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
821 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
822 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
823
824 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
825 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
826 r600_context_pipe_state_set(&rctx->ctx, rstate);
827 }
828
829 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
830 const struct pipe_framebuffer_state *state, int cb)
831 {
832 struct r600_resource_texture *rtex;
833 struct r600_resource *rbuffer;
834 struct r600_surface *surf;
835 unsigned level = state->cbufs[cb]->u.tex.level;
836 unsigned pitch, slice;
837 unsigned color_info;
838 unsigned format, swap, ntype;
839 unsigned offset;
840 const struct util_format_description *desc;
841 struct r600_bo *bo[3];
842
843 surf = (struct r600_surface *)state->cbufs[cb];
844 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
845 rbuffer = &rtex->resource;
846 bo[0] = rbuffer->bo;
847 bo[1] = rbuffer->bo;
848 bo[2] = rbuffer->bo;
849
850 /* XXX quite sure for dx10+ hw don't need any offset hacks */
851 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
852 level, state->cbufs[cb]->u.tex.first_layer);
853 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
854 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
855 ntype = 0;
856 desc = util_format_description(rtex->resource.base.b.format);
857 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
858 ntype = V_0280A0_NUMBER_SRGB;
859
860 format = r600_translate_colorformat(rtex->resource.base.b.format);
861 swap = r600_translate_colorswap(rtex->resource.base.b.format);
862 color_info = S_0280A0_FORMAT(format) |
863 S_0280A0_COMP_SWAP(swap) |
864 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
865 S_0280A0_BLEND_CLAMP(1) |
866 S_0280A0_NUMBER_TYPE(ntype);
867 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
868 color_info |= S_0280A0_SOURCE_FORMAT(1);
869
870 r600_pipe_state_add_reg(rstate,
871 R_028040_CB_COLOR0_BASE + cb * 4,
872 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
873 r600_pipe_state_add_reg(rstate,
874 R_0280A0_CB_COLOR0_INFO + cb * 4,
875 color_info, 0xFFFFFFFF, bo[0]);
876 r600_pipe_state_add_reg(rstate,
877 R_028060_CB_COLOR0_SIZE + cb * 4,
878 S_028060_PITCH_TILE_MAX(pitch) |
879 S_028060_SLICE_TILE_MAX(slice),
880 0xFFFFFFFF, NULL);
881 r600_pipe_state_add_reg(rstate,
882 R_028080_CB_COLOR0_VIEW + cb * 4,
883 0x00000000, 0xFFFFFFFF, NULL);
884 r600_pipe_state_add_reg(rstate,
885 R_0280E0_CB_COLOR0_FRAG + cb * 4,
886 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
887 r600_pipe_state_add_reg(rstate,
888 R_0280C0_CB_COLOR0_TILE + cb * 4,
889 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
890 r600_pipe_state_add_reg(rstate,
891 R_028100_CB_COLOR0_MASK + cb * 4,
892 0x00000000, 0xFFFFFFFF, NULL);
893 }
894
895 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
896 const struct pipe_framebuffer_state *state)
897 {
898 struct r600_resource_texture *rtex;
899 struct r600_resource *rbuffer;
900 struct r600_surface *surf;
901 unsigned level;
902 unsigned pitch, slice, format;
903 unsigned offset;
904
905 if (state->zsbuf == NULL)
906 return;
907
908 level = state->zsbuf->u.tex.level;
909
910 surf = (struct r600_surface *)state->zsbuf;
911 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
912 rtex->tiled = 1;
913 rtex->array_mode[level] = 2;
914 rtex->tile_type = 1;
915 rtex->depth = 1;
916 rbuffer = &rtex->resource;
917
918 /* XXX quite sure for dx10+ hw don't need any offset hacks */
919 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
920 level, state->zsbuf->u.tex.first_layer);
921 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
922 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
923 format = r600_translate_dbformat(state->zsbuf->texture->format);
924
925 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
926 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
927 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
928 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
929 0xFFFFFFFF, NULL);
930 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
931 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
932 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
933 0xFFFFFFFF, rbuffer->bo);
934 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
935 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL);
936 }
937
938 static void r600_set_framebuffer_state(struct pipe_context *ctx,
939 const struct pipe_framebuffer_state *state)
940 {
941 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
942 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
943 u32 shader_mask, tl, br, shader_control, target_mask;
944
945 if (rstate == NULL)
946 return;
947
948 /* unreference old buffer and reference new one */
949 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
950
951 util_copy_framebuffer_state(&rctx->framebuffer, state);
952
953 rctx->pframebuffer = &rctx->framebuffer;
954
955 /* build states */
956 for (int i = 0; i < state->nr_cbufs; i++) {
957 r600_cb(rctx, rstate, state, i);
958 }
959 if (state->zsbuf) {
960 r600_db(rctx, rstate, state);
961 }
962
963 target_mask = 0x00000000;
964 target_mask = 0xFFFFFFFF;
965 shader_mask = 0;
966 shader_control = 0;
967 for (int i = 0; i < state->nr_cbufs; i++) {
968 target_mask ^= 0xf << (i * 4);
969 shader_mask |= 0xf << (i * 4);
970 shader_control |= 1 << i;
971 }
972 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
973 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
974
975 r600_pipe_state_add_reg(rstate,
976 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
977 0xFFFFFFFF, NULL);
978 r600_pipe_state_add_reg(rstate,
979 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
980 0xFFFFFFFF, NULL);
981 r600_pipe_state_add_reg(rstate,
982 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
983 0xFFFFFFFF, NULL);
984 r600_pipe_state_add_reg(rstate,
985 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
986 0xFFFFFFFF, NULL);
987 r600_pipe_state_add_reg(rstate,
988 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
989 0xFFFFFFFF, NULL);
990 r600_pipe_state_add_reg(rstate,
991 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
992 0xFFFFFFFF, NULL);
993 r600_pipe_state_add_reg(rstate,
994 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
995 0xFFFFFFFF, NULL);
996 r600_pipe_state_add_reg(rstate,
997 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
998 0xFFFFFFFF, NULL);
999 r600_pipe_state_add_reg(rstate,
1000 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1001 0xFFFFFFFF, NULL);
1002 if (rctx->family >= CHIP_RV770) {
1003 r600_pipe_state_add_reg(rstate,
1004 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1005 0xFFFFFFFF, NULL);
1006 }
1007
1008 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1009 shader_control, 0xFFFFFFFF, NULL);
1010 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1011 0x00000000, target_mask, NULL);
1012 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1013 shader_mask, 0xFFFFFFFF, NULL);
1014 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1015 0x00000000, 0xFFFFFFFF, NULL);
1016 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1017 0x00000000, 0xFFFFFFFF, NULL);
1018 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1019 0x00000000, 0xFFFFFFFF, NULL);
1020 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1021 0x01000000, 0xFFFFFFFF, NULL);
1022 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1023 0x00000000, 0xFFFFFFFF, NULL);
1024 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1025 0x000000FF, 0xFFFFFFFF, NULL);
1026 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1027 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1028 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1029 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1030
1031 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1032 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1033 r600_context_pipe_state_set(&rctx->ctx, rstate);
1034
1035 if (state->zsbuf) {
1036 r600_polygon_offset_update(rctx);
1037 }
1038 }
1039
1040 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
1041 struct pipe_resource *buffer)
1042 {
1043 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1044 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
1045
1046 /* Note that the state tracker can unbind constant buffers by
1047 * passing NULL here.
1048 */
1049 if (buffer == NULL) {
1050 return;
1051 }
1052
1053 switch (shader) {
1054 case PIPE_SHADER_VERTEX:
1055 rctx->vs_const_buffer.nregs = 0;
1056 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1057 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1058 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1059 0xFFFFFFFF, NULL);
1060 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1061 R_028980_ALU_CONST_CACHE_VS_0,
1062 r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
1063 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
1064 break;
1065 case PIPE_SHADER_FRAGMENT:
1066 rctx->ps_const_buffer.nregs = 0;
1067 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1068 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1069 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1070 0xFFFFFFFF, NULL);
1071 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1072 R_028940_ALU_CONST_CACHE_PS_0,
1073 r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
1074 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
1075 break;
1076 default:
1077 R600_ERR("unsupported %d\n", shader);
1078 return;
1079 }
1080 }
1081
1082 void r600_init_state_functions(struct r600_pipe_context *rctx)
1083 {
1084 rctx->context.create_blend_state = r600_create_blend_state;
1085 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1086 rctx->context.create_fs_state = r600_create_shader_state;
1087 rctx->context.create_rasterizer_state = r600_create_rs_state;
1088 rctx->context.create_sampler_state = r600_create_sampler_state;
1089 rctx->context.create_sampler_view = r600_create_sampler_view;
1090 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1091 rctx->context.create_vs_state = r600_create_shader_state;
1092 rctx->context.bind_blend_state = r600_bind_blend_state;
1093 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
1094 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
1095 rctx->context.bind_fs_state = r600_bind_ps_shader;
1096 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1097 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1098 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
1099 rctx->context.bind_vs_state = r600_bind_vs_shader;
1100 rctx->context.delete_blend_state = r600_delete_state;
1101 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1102 rctx->context.delete_fs_state = r600_delete_ps_shader;
1103 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1104 rctx->context.delete_sampler_state = r600_delete_state;
1105 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1106 rctx->context.delete_vs_state = r600_delete_vs_shader;
1107 rctx->context.set_blend_color = r600_set_blend_color;
1108 rctx->context.set_clip_state = r600_set_clip_state;
1109 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1110 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1111 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1112 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1113 rctx->context.set_sample_mask = r600_set_sample_mask;
1114 rctx->context.set_scissor_state = r600_set_scissor_state;
1115 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1116 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1117 rctx->context.set_index_buffer = r600_set_index_buffer;
1118 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1119 rctx->context.set_viewport_state = r600_set_viewport_state;
1120 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1121 }
1122
1123 void r600_init_config(struct r600_pipe_context *rctx)
1124 {
1125 int ps_prio;
1126 int vs_prio;
1127 int gs_prio;
1128 int es_prio;
1129 int num_ps_gprs;
1130 int num_vs_gprs;
1131 int num_gs_gprs;
1132 int num_es_gprs;
1133 int num_temp_gprs;
1134 int num_ps_threads;
1135 int num_vs_threads;
1136 int num_gs_threads;
1137 int num_es_threads;
1138 int num_ps_stack_entries;
1139 int num_vs_stack_entries;
1140 int num_gs_stack_entries;
1141 int num_es_stack_entries;
1142 enum radeon_family family;
1143 struct r600_pipe_state *rstate = &rctx->config;
1144 u32 tmp;
1145
1146 family = r600_get_family(rctx->radeon);
1147 ps_prio = 0;
1148 vs_prio = 1;
1149 gs_prio = 2;
1150 es_prio = 3;
1151 switch (family) {
1152 case CHIP_R600:
1153 num_ps_gprs = 192;
1154 num_vs_gprs = 56;
1155 num_temp_gprs = 4;
1156 num_gs_gprs = 0;
1157 num_es_gprs = 0;
1158 num_ps_threads = 136;
1159 num_vs_threads = 48;
1160 num_gs_threads = 4;
1161 num_es_threads = 4;
1162 num_ps_stack_entries = 128;
1163 num_vs_stack_entries = 128;
1164 num_gs_stack_entries = 0;
1165 num_es_stack_entries = 0;
1166 break;
1167 case CHIP_RV630:
1168 case CHIP_RV635:
1169 num_ps_gprs = 84;
1170 num_vs_gprs = 36;
1171 num_temp_gprs = 4;
1172 num_gs_gprs = 0;
1173 num_es_gprs = 0;
1174 num_ps_threads = 144;
1175 num_vs_threads = 40;
1176 num_gs_threads = 4;
1177 num_es_threads = 4;
1178 num_ps_stack_entries = 40;
1179 num_vs_stack_entries = 40;
1180 num_gs_stack_entries = 32;
1181 num_es_stack_entries = 16;
1182 break;
1183 case CHIP_RV610:
1184 case CHIP_RV620:
1185 case CHIP_RS780:
1186 case CHIP_RS880:
1187 default:
1188 num_ps_gprs = 84;
1189 num_vs_gprs = 36;
1190 num_temp_gprs = 4;
1191 num_gs_gprs = 0;
1192 num_es_gprs = 0;
1193 num_ps_threads = 136;
1194 num_vs_threads = 48;
1195 num_gs_threads = 4;
1196 num_es_threads = 4;
1197 num_ps_stack_entries = 40;
1198 num_vs_stack_entries = 40;
1199 num_gs_stack_entries = 32;
1200 num_es_stack_entries = 16;
1201 break;
1202 case CHIP_RV670:
1203 num_ps_gprs = 144;
1204 num_vs_gprs = 40;
1205 num_temp_gprs = 4;
1206 num_gs_gprs = 0;
1207 num_es_gprs = 0;
1208 num_ps_threads = 136;
1209 num_vs_threads = 48;
1210 num_gs_threads = 4;
1211 num_es_threads = 4;
1212 num_ps_stack_entries = 40;
1213 num_vs_stack_entries = 40;
1214 num_gs_stack_entries = 32;
1215 num_es_stack_entries = 16;
1216 break;
1217 case CHIP_RV770:
1218 num_ps_gprs = 192;
1219 num_vs_gprs = 56;
1220 num_temp_gprs = 4;
1221 num_gs_gprs = 0;
1222 num_es_gprs = 0;
1223 num_ps_threads = 188;
1224 num_vs_threads = 60;
1225 num_gs_threads = 0;
1226 num_es_threads = 0;
1227 num_ps_stack_entries = 256;
1228 num_vs_stack_entries = 256;
1229 num_gs_stack_entries = 0;
1230 num_es_stack_entries = 0;
1231 break;
1232 case CHIP_RV730:
1233 case CHIP_RV740:
1234 num_ps_gprs = 84;
1235 num_vs_gprs = 36;
1236 num_temp_gprs = 4;
1237 num_gs_gprs = 0;
1238 num_es_gprs = 0;
1239 num_ps_threads = 188;
1240 num_vs_threads = 60;
1241 num_gs_threads = 0;
1242 num_es_threads = 0;
1243 num_ps_stack_entries = 128;
1244 num_vs_stack_entries = 128;
1245 num_gs_stack_entries = 0;
1246 num_es_stack_entries = 0;
1247 break;
1248 case CHIP_RV710:
1249 num_ps_gprs = 192;
1250 num_vs_gprs = 56;
1251 num_temp_gprs = 4;
1252 num_gs_gprs = 0;
1253 num_es_gprs = 0;
1254 num_ps_threads = 144;
1255 num_vs_threads = 48;
1256 num_gs_threads = 0;
1257 num_es_threads = 0;
1258 num_ps_stack_entries = 128;
1259 num_vs_stack_entries = 128;
1260 num_gs_stack_entries = 0;
1261 num_es_stack_entries = 0;
1262 break;
1263 }
1264
1265 rstate->id = R600_PIPE_STATE_CONFIG;
1266
1267 /* SQ_CONFIG */
1268 tmp = 0;
1269 switch (family) {
1270 case CHIP_RV610:
1271 case CHIP_RV620:
1272 case CHIP_RS780:
1273 case CHIP_RS880:
1274 case CHIP_RV710:
1275 break;
1276 default:
1277 tmp |= S_008C00_VC_ENABLE(1);
1278 break;
1279 }
1280 tmp |= S_008C00_DX9_CONSTS(0);
1281 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1282 tmp |= S_008C00_PS_PRIO(ps_prio);
1283 tmp |= S_008C00_VS_PRIO(vs_prio);
1284 tmp |= S_008C00_GS_PRIO(gs_prio);
1285 tmp |= S_008C00_ES_PRIO(es_prio);
1286 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1287
1288 /* SQ_GPR_RESOURCE_MGMT_1 */
1289 tmp = 0;
1290 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1291 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1292 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1293 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1294
1295 /* SQ_GPR_RESOURCE_MGMT_2 */
1296 tmp = 0;
1297 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1298 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1299 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1300
1301 /* SQ_THREAD_RESOURCE_MGMT */
1302 tmp = 0;
1303 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1304 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1305 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1306 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1307 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1308
1309 /* SQ_STACK_RESOURCE_MGMT_1 */
1310 tmp = 0;
1311 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1312 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1313 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1314
1315 /* SQ_STACK_RESOURCE_MGMT_2 */
1316 tmp = 0;
1317 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1318 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1319 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1320
1321 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1322 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1323
1324 if (family >= CHIP_RV770) {
1325 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1326 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1327 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1328 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1329 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1330 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
1331 } else {
1332 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1333 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1334 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1335 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1336 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1337 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
1338 }
1339 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1340 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1341 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1342 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1343 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1344 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1345 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1346 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1347 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1348 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1349 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1350 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1351 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1352 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1353 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1354 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1355 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1356 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1357 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1358 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1359 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1360 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1361 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1362 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1363 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1364 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1365
1366 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1367 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1368 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1369 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1370 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1371 r600_context_pipe_state_set(&rctx->ctx, rstate);
1372 }
1373
1374 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1375 {
1376 struct pipe_depth_stencil_alpha_state dsa;
1377 struct r600_pipe_state *rstate;
1378 boolean quirk = false;
1379
1380 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1381 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1382 quirk = true;
1383
1384 memset(&dsa, 0, sizeof(dsa));
1385
1386 if (quirk) {
1387 dsa.depth.enabled = 1;
1388 dsa.depth.func = PIPE_FUNC_LEQUAL;
1389 dsa.stencil[0].enabled = 1;
1390 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1391 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1392 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1393 dsa.stencil[0].writemask = 0xff;
1394 }
1395
1396 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1397 r600_pipe_state_add_reg(rstate,
1398 R_02880C_DB_SHADER_CONTROL,
1399 0x0,
1400 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1401 r600_pipe_state_add_reg(rstate,
1402 R_028D0C_DB_RENDER_CONTROL,
1403 S_028D0C_DEPTH_COPY_ENABLE(1) |
1404 S_028D0C_STENCIL_COPY_ENABLE(1) |
1405 S_028D0C_COPY_CENTROID(1),
1406 S_028D0C_DEPTH_COPY_ENABLE(1) |
1407 S_028D0C_STENCIL_COPY_ENABLE(1) |
1408 S_028D0C_COPY_CENTROID(1), NULL);
1409 return rstate;
1410 }