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[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <stdio.h>
27 #include <errno.h>
28 #include "util/u_inlines.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "r600_screen.h"
32 #include "r600_context.h"
33 #include "r600_resource.h"
34 #include "r600d.h"
35 #include "r600_state_inlines.h"
36
37 static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state);
38 static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state);
39 static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_clip_state *state);
40 static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_sampler_state *state, unsigned id);
41 static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate, const struct pipe_sampler_view *view, unsigned id);
42
43
44 static void *r600_create_blend_state(struct pipe_context *ctx,
45 const struct pipe_blend_state *state)
46 {
47 struct r600_context *rctx = r600_context(ctx);
48
49 return r600_context_state(rctx, pipe_blend_type, state);
50 }
51
52 static void *r600_create_dsa_state(struct pipe_context *ctx,
53 const struct pipe_depth_stencil_alpha_state *state)
54 {
55 struct r600_context *rctx = r600_context(ctx);
56
57 return r600_context_state(rctx, pipe_dsa_type, state);
58 }
59
60 static void *r600_create_rs_state(struct pipe_context *ctx,
61 const struct pipe_rasterizer_state *state)
62 {
63 struct r600_context *rctx = r600_context(ctx);
64
65 return r600_context_state(rctx, pipe_rasterizer_type, state);
66 }
67
68 static void *r600_create_sampler_state(struct pipe_context *ctx,
69 const struct pipe_sampler_state *state)
70 {
71 struct r600_context *rctx = r600_context(ctx);
72
73 return r600_context_state(rctx, pipe_sampler_type, state);
74 }
75
76 static void r600_sampler_view_destroy(struct pipe_context *ctx,
77 struct pipe_sampler_view *state)
78 {
79 struct r600_context_state *rstate = (struct r600_context_state *)state;
80
81 r600_context_state_decref(rstate);
82 }
83
84 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
85 struct pipe_resource *texture,
86 const struct pipe_sampler_view *state)
87 {
88 struct r600_context *rctx = r600_context(ctx);
89 struct r600_context_state *rstate;
90
91 rstate = r600_context_state(rctx, pipe_sampler_type, state);
92 pipe_reference(NULL, &texture->reference);
93 rstate->state.sampler_view.texture = texture;
94 rstate->state.sampler_view.reference.count = 1;
95 rstate->state.sampler_view.context = ctx;
96 r600_resource(ctx, &rstate->rstate, &rstate->state.sampler_view, 0);
97 return &rstate->state.sampler_view;
98 }
99
100 static void *r600_create_shader_state(struct pipe_context *ctx,
101 const struct pipe_shader_state *state)
102 {
103 struct r600_context *rctx = r600_context(ctx);
104
105 return r600_context_state(rctx, pipe_shader_type, state);
106 }
107
108 static void *r600_create_vertex_elements(struct pipe_context *ctx,
109 unsigned count,
110 const struct pipe_vertex_element *elements)
111 {
112 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
113
114 assert(count < 32);
115 v->count = count;
116 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
117 v->refcount = 1;
118 return v;
119 }
120
121 static void r600_bind_state(struct pipe_context *ctx, void *state)
122 {
123 struct r600_context *rctx = r600_context(ctx);
124 struct r600_context_state *rstate = (struct r600_context_state *)state;
125
126 if (state == NULL)
127 return;
128 switch (rstate->type) {
129 case pipe_rasterizer_type:
130 rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
131 rctx->rasterizer = r600_context_state_incref(rstate);
132 break;
133 case pipe_poly_stipple_type:
134 rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
135 rctx->poly_stipple = r600_context_state_incref(rstate);
136 break;
137 case pipe_scissor_type:
138 rctx->scissor = r600_context_state_decref(rctx->scissor);
139 rctx->scissor = r600_context_state_incref(rstate);
140 break;
141 case pipe_clip_type:
142 rctx->clip = r600_context_state_decref(rctx->clip);
143 rctx->clip = r600_context_state_incref(rstate);
144 break;
145 case pipe_depth_type:
146 rctx->depth = r600_context_state_decref(rctx->depth);
147 rctx->depth = r600_context_state_incref(rstate);
148 break;
149 case pipe_stencil_type:
150 rctx->stencil = r600_context_state_decref(rctx->stencil);
151 rctx->stencil = r600_context_state_incref(rstate);
152 break;
153 case pipe_alpha_type:
154 rctx->alpha = r600_context_state_decref(rctx->alpha);
155 rctx->alpha = r600_context_state_incref(rstate);
156 break;
157 case pipe_dsa_type:
158 rctx->dsa = r600_context_state_decref(rctx->dsa);
159 rctx->dsa = r600_context_state_incref(rstate);
160 break;
161 case pipe_blend_type:
162 rctx->blend = r600_context_state_decref(rctx->blend);
163 rctx->blend = r600_context_state_incref(rstate);
164 break;
165 case pipe_framebuffer_type:
166 rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
167 rctx->framebuffer = r600_context_state_incref(rstate);
168 break;
169 case pipe_stencil_ref_type:
170 rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
171 rctx->stencil_ref = r600_context_state_incref(rstate);
172 break;
173 case pipe_viewport_type:
174 rctx->viewport = r600_context_state_decref(rctx->viewport);
175 rctx->viewport = r600_context_state_incref(rstate);
176 break;
177 case pipe_shader_type:
178 case pipe_sampler_type:
179 case pipe_sampler_view_type:
180 default:
181 R600_ERR("invalid type %d\n", rstate->type);
182 return;
183 }
184 }
185
186 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
187 {
188 struct r600_context *rctx = r600_context(ctx);
189 struct r600_context_state *rstate = (struct r600_context_state *)state;
190
191 rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
192 rctx->ps_shader = r600_context_state_incref(rstate);
193 }
194
195 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
196 {
197 struct r600_context *rctx = r600_context(ctx);
198 struct r600_context_state *rstate = (struct r600_context_state *)state;
199
200 rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
201 rctx->vs_shader = r600_context_state_incref(rstate);
202 }
203
204 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
205 {
206 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
207
208 if (v == NULL)
209 return;
210 if (--v->refcount)
211 return;
212 free(v);
213 }
214
215 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
216 {
217 struct r600_context *rctx = r600_context(ctx);
218 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
219
220 r600_delete_vertex_element(ctx, rctx->vertex_elements);
221 rctx->vertex_elements = v;
222 if (v) {
223 v->refcount++;
224 }
225 }
226
227 static void r600_bind_ps_sampler(struct pipe_context *ctx,
228 unsigned count, void **states)
229 {
230 struct r600_context *rctx = r600_context(ctx);
231 struct r600_context_state *rstate;
232 unsigned i;
233
234 for (i = 0; i < rctx->ps_nsampler; i++) {
235 rctx->ps_sampler[i] = r600_context_state_decref(rctx->ps_sampler[i]);
236 }
237 for (i = 0; i < count; i++) {
238 rstate = (struct r600_context_state *)states[i];
239 rctx->ps_sampler[i] = r600_context_state_incref(rstate);
240 if (rstate) {
241 radeon_state_convert(&rstate->rstate, R600_STATE_SAMPLER, i, R600_SHADER_PS);
242 }
243 }
244 rctx->ps_nsampler = count;
245 }
246
247 static void r600_bind_vs_sampler(struct pipe_context *ctx,
248 unsigned count, void **states)
249 {
250 struct r600_context *rctx = r600_context(ctx);
251 struct r600_context_state *rstate;
252 unsigned i;
253
254 for (i = 0; i < rctx->vs_nsampler; i++) {
255 rctx->vs_sampler[i] = r600_context_state_decref(rctx->vs_sampler[i]);
256 }
257 for (i = 0; i < count; i++) {
258 rstate = (struct r600_context_state *)states[i];
259 rctx->vs_sampler[i] = r600_context_state_incref(rstate);
260 if (rstate) {
261 radeon_state_convert(&rstate->rstate, R600_STATE_SAMPLER, i, R600_SHADER_VS);
262 }
263 }
264 rctx->vs_nsampler = count;
265 }
266
267 static void r600_delete_state(struct pipe_context *ctx, void *state)
268 {
269 struct r600_context_state *rstate = (struct r600_context_state *)state;
270
271 r600_context_state_decref(rstate);
272 }
273
274 static void r600_set_blend_color(struct pipe_context *ctx,
275 const struct pipe_blend_color *color)
276 {
277 struct r600_context *rctx = r600_context(ctx);
278
279 rctx->blend_color = *color;
280 }
281
282 static void r600_set_clip_state(struct pipe_context *ctx,
283 const struct pipe_clip_state *state)
284 {
285 struct r600_context *rctx = r600_context(ctx);
286 struct r600_context_state *rstate;
287
288 rstate = r600_context_state(rctx, pipe_clip_type, state);
289 r600_bind_state(ctx, rstate);
290 /* refcount is taken care of this */
291 r600_delete_state(ctx, rstate);
292 }
293
294 static void r600_set_constant_buffer(struct pipe_context *ctx,
295 uint shader, uint index,
296 struct pipe_resource *buffer)
297 {
298 struct r600_screen *rscreen = r600_screen(ctx->screen);
299 struct r600_context *rctx = r600_context(ctx);
300 unsigned nconstant = 0, i, type, shader_class;
301 struct radeon_state *rstate, *rstates;
302 struct pipe_transfer *transfer;
303 u32 *ptr;
304
305 type = R600_STATE_CONSTANT;
306
307 switch (shader) {
308 case PIPE_SHADER_VERTEX:
309 shader_class = R600_SHADER_VS;
310 rstates = rctx->vs_constant;
311 break;
312 case PIPE_SHADER_FRAGMENT:
313 shader_class = R600_SHADER_PS;
314 rstates = rctx->ps_constant;
315 break;
316 default:
317 R600_ERR("unsupported %d\n", shader);
318 return;
319 }
320 if (buffer && buffer->width0 > 0) {
321 nconstant = buffer->width0 / 16;
322 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
323 if (ptr == NULL)
324 return;
325 for (i = 0; i < nconstant; i++) {
326 rstate = &rstates[i];
327 radeon_state_init(rstate, rscreen->rw, type, i, shader_class);
328 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
329 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
330 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
331 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
332 if (radeon_state_pm4(rstate))
333 return;
334 radeon_draw_bind(&rctx->draw, rstate);
335 }
336 pipe_buffer_unmap(ctx, buffer, transfer);
337 }
338 }
339
340 static void r600_set_ps_sampler_view(struct pipe_context *ctx,
341 unsigned count,
342 struct pipe_sampler_view **views)
343 {
344 struct r600_context *rctx = r600_context(ctx);
345 struct r600_context_state *rstate;
346 unsigned i;
347
348 for (i = 0; i < rctx->ps_nsampler_view; i++) {
349 rctx->ps_sampler_view[i] = r600_context_state_decref(rctx->ps_sampler_view[i]);
350 }
351 for (i = 0; i < count; i++) {
352 rstate = (struct r600_context_state *)views[i];
353 rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
354 if (rstate) {
355 radeon_state_convert(&rstate->rstate, R600_STATE_RESOURCE, i, R600_SHADER_PS);
356 }
357 }
358 rctx->ps_nsampler_view = count;
359 }
360
361 static void r600_set_vs_sampler_view(struct pipe_context *ctx,
362 unsigned count,
363 struct pipe_sampler_view **views)
364 {
365 struct r600_context *rctx = r600_context(ctx);
366 struct r600_context_state *rstate;
367 unsigned i;
368
369 for (i = 0; i < rctx->vs_nsampler_view; i++) {
370 rctx->vs_sampler_view[i] = r600_context_state_decref(rctx->vs_sampler_view[i]);
371 }
372 for (i = 0; i < count; i++) {
373 rstate = (struct r600_context_state *)views[i];
374 rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
375 if (rstate) {
376 radeon_state_convert(&rstate->rstate, R600_STATE_RESOURCE, i, R600_SHADER_VS);
377 }
378 }
379 rctx->vs_nsampler_view = count;
380 }
381
382 static void r600_set_framebuffer_state(struct pipe_context *ctx,
383 const struct pipe_framebuffer_state *state)
384 {
385 struct r600_context *rctx = r600_context(ctx);
386 struct r600_resource_texture *rtexture;
387 struct r600_context_state *rstate;
388
389 rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
390 r600_bind_state(ctx, rstate);
391 for (int i = 0; i < state->nr_cbufs; i++) {
392 rtexture = (struct r600_resource_texture*)state->cbufs[i]->texture;
393 r600_texture_cb(ctx, rtexture, i, state->cbufs[i]->level);
394 }
395 if (state->zsbuf) {
396 rtexture = (struct r600_resource_texture*)state->zsbuf->texture;
397 r600_texture_db(ctx, rtexture, state->zsbuf->level);
398 }
399 }
400
401 static void r600_set_polygon_stipple(struct pipe_context *ctx,
402 const struct pipe_poly_stipple *state)
403 {
404 }
405
406 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
407 {
408 }
409
410 static void r600_set_scissor_state(struct pipe_context *ctx,
411 const struct pipe_scissor_state *state)
412 {
413 struct r600_context *rctx = r600_context(ctx);
414 struct r600_context_state *rstate;
415
416 rstate = r600_context_state(rctx, pipe_scissor_type, state);
417 r600_bind_state(ctx, rstate);
418 /* refcount is taken care of this */
419 r600_delete_state(ctx, rstate);
420 }
421
422 static void r600_set_stencil_ref(struct pipe_context *ctx,
423 const struct pipe_stencil_ref *state)
424 {
425 struct r600_context *rctx = r600_context(ctx);
426 struct r600_context_state *rstate;
427
428 rstate = r600_context_state(rctx, pipe_stencil_ref_type, state);
429 r600_bind_state(ctx, rstate);
430 /* refcount is taken care of this */
431 r600_delete_state(ctx, rstate);
432 }
433
434 static void r600_set_vertex_buffers(struct pipe_context *ctx,
435 unsigned count,
436 const struct pipe_vertex_buffer *buffers)
437 {
438 struct r600_context *rctx = r600_context(ctx);
439 unsigned i;
440
441 for (i = 0; i < rctx->nvertex_buffer; i++) {
442 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
443 }
444 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
445 for (i = 0; i < count; i++) {
446 rctx->vertex_buffer[i].buffer = NULL;
447 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
448 }
449 rctx->nvertex_buffer = count;
450 }
451
452 static void r600_set_index_buffer(struct pipe_context *ctx,
453 const struct pipe_index_buffer *ib)
454 {
455 struct r600_context *rctx = r600_context(ctx);
456
457 if (ib) {
458 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
459 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
460 } else {
461 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
462 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
463 }
464
465 /* TODO make this more like a state */
466 }
467
468 static void r600_set_viewport_state(struct pipe_context *ctx,
469 const struct pipe_viewport_state *state)
470 {
471 struct r600_context *rctx = r600_context(ctx);
472 struct r600_context_state *rstate;
473
474 rstate = r600_context_state(rctx, pipe_viewport_type, state);
475 r600_bind_state(ctx, rstate);
476 r600_delete_state(ctx, rstate);
477 }
478
479 void r600_init_state_functions(struct r600_context *rctx)
480 {
481 rctx->context.create_blend_state = r600_create_blend_state;
482 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
483 rctx->context.create_fs_state = r600_create_shader_state;
484 rctx->context.create_rasterizer_state = r600_create_rs_state;
485 rctx->context.create_sampler_state = r600_create_sampler_state;
486 rctx->context.create_sampler_view = r600_create_sampler_view;
487 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
488 rctx->context.create_vs_state = r600_create_shader_state;
489 rctx->context.bind_blend_state = r600_bind_state;
490 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
491 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
492 rctx->context.bind_fs_state = r600_bind_ps_shader;
493 rctx->context.bind_rasterizer_state = r600_bind_state;
494 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
495 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
496 rctx->context.bind_vs_state = r600_bind_vs_shader;
497 rctx->context.delete_blend_state = r600_delete_state;
498 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
499 rctx->context.delete_fs_state = r600_delete_state;
500 rctx->context.delete_rasterizer_state = r600_delete_state;
501 rctx->context.delete_sampler_state = r600_delete_state;
502 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
503 rctx->context.delete_vs_state = r600_delete_state;
504 rctx->context.set_blend_color = r600_set_blend_color;
505 rctx->context.set_clip_state = r600_set_clip_state;
506 rctx->context.set_constant_buffer = r600_set_constant_buffer;
507 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
508 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
509 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
510 rctx->context.set_sample_mask = r600_set_sample_mask;
511 rctx->context.set_scissor_state = r600_set_scissor_state;
512 rctx->context.set_stencil_ref = r600_set_stencil_ref;
513 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
514 rctx->context.set_index_buffer = r600_set_index_buffer;
515 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
516 rctx->context.set_viewport_state = r600_set_viewport_state;
517 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
518 }
519
520 struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate)
521 {
522 if (rstate == NULL)
523 return NULL;
524 rstate->refcount++;
525 return rstate;
526 }
527
528 struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate)
529 {
530 unsigned i;
531
532 if (rstate == NULL)
533 return NULL;
534 if (--rstate->refcount)
535 return NULL;
536 switch (rstate->type) {
537 case pipe_sampler_view_type:
538 pipe_resource_reference(&rstate->state.sampler_view.texture, NULL);
539 break;
540 case pipe_framebuffer_type:
541 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
542 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
543 }
544 pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
545 break;
546 case pipe_viewport_type:
547 case pipe_depth_type:
548 case pipe_rasterizer_type:
549 case pipe_poly_stipple_type:
550 case pipe_scissor_type:
551 case pipe_clip_type:
552 case pipe_stencil_type:
553 case pipe_alpha_type:
554 case pipe_dsa_type:
555 case pipe_blend_type:
556 case pipe_stencil_ref_type:
557 case pipe_shader_type:
558 case pipe_sampler_type:
559 break;
560 default:
561 R600_ERR("invalid type %d\n", rstate->type);
562 return NULL;
563 }
564 radeon_state_fini(&rstate->rstate);
565 FREE(rstate);
566 return NULL;
567 }
568
569 struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state)
570 {
571 struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
572 const union pipe_states *states = state;
573 unsigned i;
574 int r;
575
576 if (rstate == NULL)
577 return NULL;
578 rstate->type = type;
579 rstate->refcount = 1;
580
581 switch (rstate->type) {
582 case pipe_sampler_view_type:
583 rstate->state.sampler_view = (*states).sampler_view;
584 rstate->state.sampler_view.texture = NULL;
585 break;
586 case pipe_framebuffer_type:
587 rstate->state.framebuffer = (*states).framebuffer;
588 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
589 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i],
590 (*states).framebuffer.cbufs[i]);
591 }
592 pipe_surface_reference(&rstate->state.framebuffer.zsbuf,
593 (*states).framebuffer.zsbuf);
594 break;
595 case pipe_viewport_type:
596 rstate->state.viewport = (*states).viewport;
597 r600_viewport(rctx, &rstate->rstate, &rstate->state.viewport);
598 break;
599 case pipe_depth_type:
600 rstate->state.depth = (*states).depth;
601 break;
602 case pipe_rasterizer_type:
603 rstate->state.rasterizer = (*states).rasterizer;
604 break;
605 case pipe_poly_stipple_type:
606 rstate->state.poly_stipple = (*states).poly_stipple;
607 break;
608 case pipe_scissor_type:
609 rstate->state.scissor = (*states).scissor;
610 break;
611 case pipe_clip_type:
612 rstate->state.clip = (*states).clip;
613 r600_ucp(rctx, &rstate->rstate, &rstate->state.clip);
614 break;
615 case pipe_stencil_type:
616 rstate->state.stencil = (*states).stencil;
617 break;
618 case pipe_alpha_type:
619 rstate->state.alpha = (*states).alpha;
620 break;
621 case pipe_dsa_type:
622 rstate->state.dsa = (*states).dsa;
623 break;
624 case pipe_blend_type:
625 rstate->state.blend = (*states).blend;
626 r600_blend(rctx, &rstate->rstate, &rstate->state.blend);
627 break;
628 case pipe_stencil_ref_type:
629 rstate->state.stencil_ref = (*states).stencil_ref;
630 break;
631 case pipe_shader_type:
632 rstate->state.shader = (*states).shader;
633 r = r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
634 if (r) {
635 r600_context_state_decref(rstate);
636 return NULL;
637 }
638 break;
639 case pipe_sampler_type:
640 rstate->state.sampler = (*states).sampler;
641 r600_sampler(rctx, &rstate->rstate, &rstate->state.sampler, 0);
642 break;
643 default:
644 R600_ERR("invalid type %d\n", rstate->type);
645 FREE(rstate);
646 return NULL;
647 }
648 return rstate;
649 }
650
651 static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
652 {
653 struct r600_screen *rscreen = rctx->screen;
654 int i;
655
656 radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
657 rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
658 rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
659 rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
660 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
661 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
662 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
663 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
664 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
665 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
666 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
667 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
668 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
669 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
670
671 for (i = 0; i < 8; i++) {
672 unsigned eqRGB = state->rt[i].rgb_func;
673 unsigned srcRGB = state->rt[i].rgb_src_factor;
674 unsigned dstRGB = state->rt[i].rgb_dst_factor;
675
676 unsigned eqA = state->rt[i].alpha_func;
677 unsigned srcA = state->rt[i].alpha_src_factor;
678 unsigned dstA = state->rt[i].alpha_dst_factor;
679 uint32_t bc = 0;
680
681 if (!state->rt[i].blend_enable)
682 continue;
683
684 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
685 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
686 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
687
688 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
689 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
690 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
691 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
692 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
693 }
694
695 rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
696 if (i == 0)
697 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
698 }
699
700 radeon_state_pm4(rstate);
701 }
702
703 static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate,
704 const struct pipe_clip_state *state)
705 {
706 struct r600_screen *rscreen = rctx->screen;
707
708 radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
709
710 for (int i = 0; i < state->nr; i++) {
711 rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
712 rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
713 rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
714 rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
715 }
716 radeon_state_pm4(rstate);
717 }
718
719 static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
720 {
721 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
722 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
723 const struct pipe_clip_state *clip = NULL;
724 struct r600_screen *rscreen = rctx->screen;
725 float offset_units = 0, offset_scale = 0;
726 char depth = 0;
727 unsigned offset_db_fmt_cntl = 0;
728 unsigned tmp;
729 unsigned prov_vtx = 1;
730
731 if (rctx->clip)
732 clip = &rctx->clip->state.clip;
733 if (fb->zsbuf) {
734 offset_units = state->offset_units;
735 offset_scale = state->offset_scale * 12.0f;
736 switch (fb->zsbuf->texture->format) {
737 case PIPE_FORMAT_Z24X8_UNORM:
738 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
739 depth = -24;
740 offset_units *= 2.0f;
741 break;
742 case PIPE_FORMAT_Z32_FLOAT:
743 depth = -23;
744 offset_units *= 1.0f;
745 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
746 break;
747 case PIPE_FORMAT_Z16_UNORM:
748 depth = -16;
749 offset_units *= 4.0f;
750 break;
751 default:
752 R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
753 return;
754 }
755 }
756 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
757
758 if (state->flatshade_first)
759 prov_vtx = 0;
760
761 rctx->flat_shade = state->flatshade;
762 radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
763 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
764 if (state->sprite_coord_enable) {
765 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
766 S_0286D4_PNT_SPRITE_ENA(1) |
767 S_0286D4_PNT_SPRITE_OVRD_X(2) |
768 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
769 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
770 S_0286D4_PNT_SPRITE_OVRD_W(1);
771 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
772 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
773 S_0286D4_PNT_SPRITE_TOP_1(1);
774 }
775 }
776 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
777 if (clip) {
778 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
779 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
780 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
781 }
782 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] =
783 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
784 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
785 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
786 S_028814_FACE(!state->front_ccw) |
787 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
788 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
789 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
790 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] =
791 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
792 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
793 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
794 /* point size 12.4 fixed point */
795 tmp = (unsigned)(state->point_size * 8.0);
796 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
797 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
798 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
799 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
800 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
801 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
802 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
803 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
804 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
805 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
806 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
807 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
808 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
809 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
810 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
811 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
812 radeon_state_pm4(rstate);
813 }
814
815 static void r600_scissor(struct r600_context *rctx, struct radeon_state *rstate)
816 {
817 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
818 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
819 struct r600_screen *rscreen = rctx->screen;
820 unsigned minx, maxx, miny, maxy;
821 u32 tl, br;
822
823 if (state == NULL) {
824 minx = 0;
825 miny = 0;
826 maxx = fb->cbufs[0]->width;
827 maxy = fb->cbufs[0]->height;
828 } else {
829 minx = state->minx;
830 miny = state->miny;
831 maxx = state->maxx;
832 maxy = state->maxy;
833 }
834 tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
835 br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
836 radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
837 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
838 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
839 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
840 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
841 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
842 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
843 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
844 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
845 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
846 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
847 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
848 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
849 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
850 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
851 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
852 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
853 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
854 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
855 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
856 radeon_state_pm4(rstate);
857 }
858
859 static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
860 {
861 struct r600_screen *rscreen = rctx->screen;
862
863 radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
864 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
865 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
866 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
867 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
868 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
869 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
870 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
871 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
872 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
873 radeon_state_pm4(rstate);
874 }
875
876 static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
877 {
878 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
879 const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
880 struct r600_screen *rscreen = rctx->screen;
881 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
882 unsigned stencil_ref_mask, stencil_ref_mask_bf;
883 struct r600_shader *rshader;
884 int i;
885
886 if (rctx->ps_shader == NULL) {
887 return;
888 }
889 radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
890
891 db_shader_control = 0x210;
892 rshader = &rctx->ps_shader->shader;
893 if (rshader->uses_kill)
894 db_shader_control |= (1 << 6);
895 for (i = 0; i < rshader->noutput; i++) {
896 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
897 db_shader_control |= 1;
898 }
899 stencil_ref_mask = 0;
900 stencil_ref_mask_bf = 0;
901 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
902 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
903 S_028800_ZFUNC(state->depth.func);
904 /* set stencil enable */
905
906 if (state->stencil[0].enabled) {
907 db_depth_control |= S_028800_STENCIL_ENABLE(1);
908 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
909 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
910 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
911 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
912
913 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
914 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
915 stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
916 if (state->stencil[1].enabled) {
917 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
918 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
919 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
920 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
921 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
922 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
923 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
924 stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
925 }
926 }
927
928 alpha_test_control = 0;
929 alpha_ref = 0;
930 if (state->alpha.enabled) {
931 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
932 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
933 alpha_ref = fui(state->alpha.ref_value);
934 }
935
936 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
937 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
938 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
939 rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
940 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
941 rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
942 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
943 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
944 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
945 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
946 rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control;
947 rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
948 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
949 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
950 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
951 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
952 radeon_state_pm4(rstate);
953 }
954
955 static inline unsigned r600_tex_wrap(unsigned wrap)
956 {
957 switch (wrap) {
958 default:
959 case PIPE_TEX_WRAP_REPEAT:
960 return V_03C000_SQ_TEX_WRAP;
961 case PIPE_TEX_WRAP_CLAMP:
962 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
963 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
964 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
965 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
966 return V_03C000_SQ_TEX_CLAMP_BORDER;
967 case PIPE_TEX_WRAP_MIRROR_REPEAT:
968 return V_03C000_SQ_TEX_MIRROR;
969 case PIPE_TEX_WRAP_MIRROR_CLAMP:
970 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
971 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
972 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
973 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
974 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
975 }
976 }
977
978 static inline unsigned r600_tex_filter(unsigned filter)
979 {
980 switch (filter) {
981 default:
982 case PIPE_TEX_FILTER_NEAREST:
983 return V_03C000_SQ_TEX_XY_FILTER_POINT;
984 case PIPE_TEX_FILTER_LINEAR:
985 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
986 }
987 }
988
989 static inline unsigned r600_tex_mipfilter(unsigned filter)
990 {
991 switch (filter) {
992 case PIPE_TEX_MIPFILTER_NEAREST:
993 return V_03C000_SQ_TEX_Z_FILTER_POINT;
994 case PIPE_TEX_MIPFILTER_LINEAR:
995 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
996 default:
997 case PIPE_TEX_MIPFILTER_NONE:
998 return V_03C000_SQ_TEX_Z_FILTER_NONE;
999 }
1000 }
1001
1002 static inline unsigned r600_tex_compare(unsigned compare)
1003 {
1004 switch (compare) {
1005 default:
1006 case PIPE_FUNC_NEVER:
1007 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1008 case PIPE_FUNC_LESS:
1009 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1010 case PIPE_FUNC_EQUAL:
1011 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1012 case PIPE_FUNC_LEQUAL:
1013 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1014 case PIPE_FUNC_GREATER:
1015 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1016 case PIPE_FUNC_NOTEQUAL:
1017 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1018 case PIPE_FUNC_GEQUAL:
1019 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1020 case PIPE_FUNC_ALWAYS:
1021 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1022 }
1023 }
1024
1025 static INLINE u32 S_FIXED(float value, u32 frac_bits)
1026 {
1027 return value * (1 << frac_bits);
1028 }
1029
1030 static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate,
1031 const struct pipe_sampler_state *state, unsigned id)
1032 {
1033 struct r600_screen *rscreen = rctx->screen;
1034
1035 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
1036 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
1037 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1038 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1039 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1040 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
1041 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
1042 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1043 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func));
1044 /* FIXME LOD it depends on texture base level ... */
1045 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
1046 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1047 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1048 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
1049 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
1050 radeon_state_pm4(rstate);
1051 }
1052
1053 static inline unsigned r600_tex_swizzle(unsigned swizzle)
1054 {
1055 switch (swizzle) {
1056 case PIPE_SWIZZLE_RED:
1057 return V_038010_SQ_SEL_X;
1058 case PIPE_SWIZZLE_GREEN:
1059 return V_038010_SQ_SEL_Y;
1060 case PIPE_SWIZZLE_BLUE:
1061 return V_038010_SQ_SEL_Z;
1062 case PIPE_SWIZZLE_ALPHA:
1063 return V_038010_SQ_SEL_W;
1064 case PIPE_SWIZZLE_ZERO:
1065 return V_038010_SQ_SEL_0;
1066 default:
1067 case PIPE_SWIZZLE_ONE:
1068 return V_038010_SQ_SEL_1;
1069 }
1070 }
1071
1072 static inline unsigned r600_format_type(unsigned format_type)
1073 {
1074 switch (format_type) {
1075 default:
1076 case UTIL_FORMAT_TYPE_UNSIGNED:
1077 return V_038010_SQ_FORMAT_COMP_UNSIGNED;
1078 case UTIL_FORMAT_TYPE_SIGNED:
1079 return V_038010_SQ_FORMAT_COMP_SIGNED;
1080 case UTIL_FORMAT_TYPE_FIXED:
1081 return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
1082 }
1083 }
1084
1085 static inline unsigned r600_tex_dim(unsigned dim)
1086 {
1087 switch (dim) {
1088 default:
1089 case PIPE_TEXTURE_1D:
1090 return V_038000_SQ_TEX_DIM_1D;
1091 case PIPE_TEXTURE_2D:
1092 case PIPE_TEXTURE_RECT:
1093 return V_038000_SQ_TEX_DIM_2D;
1094 case PIPE_TEXTURE_3D:
1095 return V_038000_SQ_TEX_DIM_3D;
1096 case PIPE_TEXTURE_CUBE:
1097 return V_038000_SQ_TEX_DIM_CUBEMAP;
1098 }
1099 }
1100
1101 static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate,
1102 const struct pipe_sampler_view *view, unsigned id)
1103 {
1104 struct r600_context *rctx = r600_context(ctx);
1105 struct r600_screen *rscreen = rctx->screen;
1106 const struct util_format_description *desc;
1107 struct r600_resource_texture *tmp;
1108 struct r600_resource *rbuffer;
1109 unsigned format;
1110 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1111 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1112 int r;
1113
1114 rstate->cpm4 = 0;
1115 swizzle[0] = view->swizzle_r;
1116 swizzle[1] = view->swizzle_g;
1117 swizzle[2] = view->swizzle_b;
1118 swizzle[3] = view->swizzle_a;
1119 format = r600_translate_texformat(view->texture->format,
1120 swizzle,
1121 &word4, &yuv_format);
1122 if (format == ~0) {
1123 return;
1124 }
1125 desc = util_format_description(view->texture->format);
1126 if (desc == NULL) {
1127 R600_ERR("unknow format %d\n", view->texture->format);
1128 return;
1129 }
1130 radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
1131 tmp = (struct r600_resource_texture*)view->texture;
1132 rbuffer = &tmp->resource;
1133 if (tmp->depth) {
1134 r = r600_texture_from_depth(ctx, tmp, view->first_level);
1135 if (r) {
1136 return;
1137 }
1138 rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
1139 rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
1140 } else {
1141 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1142 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1143 }
1144 rstate->nbo = 2;
1145 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
1146 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
1147 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
1148 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
1149
1150 pitch = (tmp->pitch[0] / tmp->bpt);
1151 pitch = (pitch + 0x7) & ~0x7;
1152
1153 /* FIXME properly handle first level != 0 */
1154 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
1155 S_038000_DIM(r600_tex_dim(view->texture->target)) |
1156 S_038000_TILE_MODE(array_mode) |
1157 S_038000_TILE_TYPE(tile_type) |
1158 S_038000_PITCH((pitch / 8) - 1) |
1159 S_038000_TEX_WIDTH(view->texture->width0 - 1);
1160 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
1161 S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
1162 S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
1163 S_038004_DATA_FORMAT(format);
1164 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
1165 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
1166 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
1167 word4 |
1168 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
1169 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
1170 S_038010_REQUEST_SIZE(1) |
1171 S_038010_BASE_LEVEL(view->first_level);
1172 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
1173 S_038014_LAST_LEVEL(view->last_level) |
1174 S_038014_BASE_ARRAY(0) |
1175 S_038014_LAST_ARRAY(0);
1176 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
1177 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
1178 radeon_state_pm4(rstate);
1179 }
1180
1181 static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
1182 {
1183 struct r600_screen *rscreen = rctx->screen;
1184 const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
1185 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
1186 uint32_t color_control, target_mask, shader_mask;
1187 int i;
1188
1189 target_mask = 0;
1190 shader_mask = 0;
1191 color_control = S_028808_PER_MRT_BLEND(1);
1192
1193 for (i = 0; i < nr_cbufs; i++) {
1194 shader_mask |= 0xf << (i * 4);
1195 }
1196
1197 if (pbs->logicop_enable) {
1198 color_control |= (pbs->logicop_func) << 16;
1199 } else {
1200 color_control |= (0xcc << 16);
1201 }
1202
1203 if (pbs->independent_blend_enable) {
1204 for (i = 0; i < nr_cbufs; i++) {
1205 if (pbs->rt[i].blend_enable) {
1206 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1207 }
1208 target_mask |= (pbs->rt[i].colormask << (4 * i));
1209 }
1210 } else {
1211 for (i = 0; i < nr_cbufs; i++) {
1212 if (pbs->rt[0].blend_enable) {
1213 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1214 }
1215 target_mask |= (pbs->rt[0].colormask << (4 * i));
1216 }
1217 }
1218 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
1219 rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
1220 rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
1221 rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
1222 rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
1223 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
1224 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
1225 rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
1226 rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
1227 rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
1228 rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
1229 rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
1230 radeon_state_pm4(rstate);
1231 }
1232
1233 int r600_context_hw_states(struct pipe_context *ctx)
1234 {
1235 struct r600_context *rctx = r600_context(ctx);
1236 struct r600_resource_texture *rtexture;
1237 unsigned i;
1238
1239 /* build new states */
1240 r600_rasterizer(rctx, &rctx->hw_states.rasterizer);
1241 r600_scissor(rctx, &rctx->hw_states.scissor);
1242 r600_dsa(rctx, &rctx->hw_states.dsa);
1243 r600_cb_cntl(rctx, &rctx->hw_states.cb_cntl);
1244
1245 /* bind states */
1246 radeon_draw_bind(&rctx->draw, &rctx->hw_states.rasterizer);
1247 radeon_draw_bind(&rctx->draw, &rctx->hw_states.scissor);
1248 radeon_draw_bind(&rctx->draw, &rctx->hw_states.dsa);
1249 radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_cntl);
1250
1251 radeon_draw_bind(&rctx->draw, &rctx->config);
1252
1253 if (rctx->viewport) {
1254 radeon_draw_bind(&rctx->draw, &rctx->viewport->rstate);
1255 }
1256 if (rctx->blend) {
1257 radeon_draw_bind(&rctx->draw, &rctx->blend->rstate);
1258 }
1259 if (rctx->clip) {
1260 radeon_draw_bind(&rctx->draw, &rctx->clip->rstate);
1261 }
1262 for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
1263 rtexture = (struct r600_resource_texture*)rctx->framebuffer->state.framebuffer.cbufs[i]->texture;
1264 radeon_draw_bind(&rctx->draw, &rtexture->cb[i][rctx->framebuffer->state.framebuffer.cbufs[i]->level]);
1265 }
1266 if (rctx->framebuffer->state.framebuffer.zsbuf) {
1267 rtexture = (struct r600_resource_texture*)rctx->framebuffer->state.framebuffer.zsbuf->texture;
1268 radeon_draw_bind(&rctx->draw, &rtexture->db[rctx->framebuffer->state.framebuffer.zsbuf->level]);
1269 }
1270 for (i = 0; i < rctx->ps_nsampler; i++) {
1271 if (rctx->ps_sampler[i]) {
1272 radeon_draw_bind(&rctx->draw, &rctx->ps_sampler[i]->rstate);
1273 }
1274 }
1275 for (i = 0; i < rctx->ps_nsampler_view; i++) {
1276 if (rctx->ps_sampler_view[i]) {
1277 radeon_draw_bind(&rctx->draw, &rctx->ps_sampler_view[i]->rstate);
1278 }
1279 }
1280 return 0;
1281 }