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ce65da668df0d2aeb5909c5991e0c3d8eb822acc
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include "pipe/p_defines.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_util.h"
35 #include "util/u_double_list.h"
36 #include "util/u_pack_color.h"
37 #include "util/u_memory.h"
38 #include "util/u_inlines.h"
39 #include "util/u_framebuffer.h"
40 #include "util/u_transfer.h"
41 #include "pipebuffer/pb_buffer.h"
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_formats.h"
48
49 static uint32_t r600_translate_blend_function(int blend_func)
50 {
51 switch (blend_func) {
52 case PIPE_BLEND_ADD:
53 return V_028804_COMB_DST_PLUS_SRC;
54 case PIPE_BLEND_SUBTRACT:
55 return V_028804_COMB_SRC_MINUS_DST;
56 case PIPE_BLEND_REVERSE_SUBTRACT:
57 return V_028804_COMB_DST_MINUS_SRC;
58 case PIPE_BLEND_MIN:
59 return V_028804_COMB_MIN_DST_SRC;
60 case PIPE_BLEND_MAX:
61 return V_028804_COMB_MAX_DST_SRC;
62 default:
63 R600_ERR("Unknown blend function %d\n", blend_func);
64 assert(0);
65 break;
66 }
67 return 0;
68 }
69
70 static uint32_t r600_translate_blend_factor(int blend_fact)
71 {
72 switch (blend_fact) {
73 case PIPE_BLENDFACTOR_ONE:
74 return V_028804_BLEND_ONE;
75 case PIPE_BLENDFACTOR_SRC_COLOR:
76 return V_028804_BLEND_SRC_COLOR;
77 case PIPE_BLENDFACTOR_SRC_ALPHA:
78 return V_028804_BLEND_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_DST_ALPHA:
80 return V_028804_BLEND_DST_ALPHA;
81 case PIPE_BLENDFACTOR_DST_COLOR:
82 return V_028804_BLEND_DST_COLOR;
83 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
84 return V_028804_BLEND_SRC_ALPHA_SATURATE;
85 case PIPE_BLENDFACTOR_CONST_COLOR:
86 return V_028804_BLEND_CONST_COLOR;
87 case PIPE_BLENDFACTOR_CONST_ALPHA:
88 return V_028804_BLEND_CONST_ALPHA;
89 case PIPE_BLENDFACTOR_ZERO:
90 return V_028804_BLEND_ZERO;
91 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
92 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
94 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
95 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
96 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
97 case PIPE_BLENDFACTOR_INV_DST_COLOR:
98 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
99 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
100 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
101 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
102 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
103 case PIPE_BLENDFACTOR_SRC1_COLOR:
104 return V_028804_BLEND_SRC1_COLOR;
105 case PIPE_BLENDFACTOR_SRC1_ALPHA:
106 return V_028804_BLEND_SRC1_ALPHA;
107 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
108 return V_028804_BLEND_INV_SRC1_COLOR;
109 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
110 return V_028804_BLEND_INV_SRC1_ALPHA;
111 default:
112 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
113 assert(0);
114 break;
115 }
116 return 0;
117 }
118
119 static uint32_t r600_translate_stencil_op(int s_op)
120 {
121 switch (s_op) {
122 case PIPE_STENCIL_OP_KEEP:
123 return V_028800_STENCIL_KEEP;
124 case PIPE_STENCIL_OP_ZERO:
125 return V_028800_STENCIL_ZERO;
126 case PIPE_STENCIL_OP_REPLACE:
127 return V_028800_STENCIL_REPLACE;
128 case PIPE_STENCIL_OP_INCR:
129 return V_028800_STENCIL_INCR;
130 case PIPE_STENCIL_OP_DECR:
131 return V_028800_STENCIL_DECR;
132 case PIPE_STENCIL_OP_INCR_WRAP:
133 return V_028800_STENCIL_INCR_WRAP;
134 case PIPE_STENCIL_OP_DECR_WRAP:
135 return V_028800_STENCIL_DECR_WRAP;
136 case PIPE_STENCIL_OP_INVERT:
137 return V_028800_STENCIL_INVERT;
138 default:
139 R600_ERR("Unknown stencil op %d", s_op);
140 assert(0);
141 break;
142 }
143 return 0;
144 }
145
146 static uint32_t r600_translate_fill(uint32_t func)
147 {
148 switch(func) {
149 case PIPE_POLYGON_MODE_FILL:
150 return 2;
151 case PIPE_POLYGON_MODE_LINE:
152 return 1;
153 case PIPE_POLYGON_MODE_POINT:
154 return 0;
155 default:
156 assert(0);
157 return 0;
158 }
159 }
160
161 /* translates straight */
162 static uint32_t r600_translate_ds_func(int func)
163 {
164 return func;
165 }
166
167 static unsigned r600_tex_wrap(unsigned wrap)
168 {
169 switch (wrap) {
170 default:
171 case PIPE_TEX_WRAP_REPEAT:
172 return V_03C000_SQ_TEX_WRAP;
173 case PIPE_TEX_WRAP_CLAMP:
174 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
175 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
176 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
177 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
178 return V_03C000_SQ_TEX_CLAMP_BORDER;
179 case PIPE_TEX_WRAP_MIRROR_REPEAT:
180 return V_03C000_SQ_TEX_MIRROR;
181 case PIPE_TEX_WRAP_MIRROR_CLAMP:
182 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
183 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
184 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
185 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
186 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
187 }
188 }
189
190 static unsigned r600_tex_filter(unsigned filter)
191 {
192 switch (filter) {
193 default:
194 case PIPE_TEX_FILTER_NEAREST:
195 return V_03C000_SQ_TEX_XY_FILTER_POINT;
196 case PIPE_TEX_FILTER_LINEAR:
197 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
198 }
199 }
200
201 static unsigned r600_tex_mipfilter(unsigned filter)
202 {
203 switch (filter) {
204 case PIPE_TEX_MIPFILTER_NEAREST:
205 return V_03C000_SQ_TEX_Z_FILTER_POINT;
206 case PIPE_TEX_MIPFILTER_LINEAR:
207 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
208 default:
209 case PIPE_TEX_MIPFILTER_NONE:
210 return V_03C000_SQ_TEX_Z_FILTER_NONE;
211 }
212 }
213
214 static unsigned r600_tex_compare(unsigned compare)
215 {
216 switch (compare) {
217 default:
218 case PIPE_FUNC_NEVER:
219 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
220 case PIPE_FUNC_LESS:
221 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
222 case PIPE_FUNC_EQUAL:
223 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
224 case PIPE_FUNC_LEQUAL:
225 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
226 case PIPE_FUNC_GREATER:
227 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
228 case PIPE_FUNC_NOTEQUAL:
229 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
230 case PIPE_FUNC_GEQUAL:
231 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
232 case PIPE_FUNC_ALWAYS:
233 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
234 }
235 }
236
237 static unsigned r600_tex_dim(unsigned dim)
238 {
239 switch (dim) {
240 default:
241 case PIPE_TEXTURE_1D:
242 return V_038000_SQ_TEX_DIM_1D;
243 case PIPE_TEXTURE_1D_ARRAY:
244 return V_038000_SQ_TEX_DIM_1D_ARRAY;
245 case PIPE_TEXTURE_2D:
246 case PIPE_TEXTURE_RECT:
247 return V_038000_SQ_TEX_DIM_2D;
248 case PIPE_TEXTURE_2D_ARRAY:
249 return V_038000_SQ_TEX_DIM_2D_ARRAY;
250 case PIPE_TEXTURE_3D:
251 return V_038000_SQ_TEX_DIM_3D;
252 case PIPE_TEXTURE_CUBE:
253 return V_038000_SQ_TEX_DIM_CUBEMAP;
254 }
255 }
256
257 static uint32_t r600_translate_dbformat(enum pipe_format format)
258 {
259 switch (format) {
260 case PIPE_FORMAT_Z16_UNORM:
261 return V_028010_DEPTH_16;
262 case PIPE_FORMAT_Z24X8_UNORM:
263 return V_028010_DEPTH_X8_24;
264 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
265 return V_028010_DEPTH_8_24;
266 case PIPE_FORMAT_Z32_FLOAT:
267 return V_028010_DEPTH_32_FLOAT;
268 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
269 return V_028010_DEPTH_X24_8_32_FLOAT;
270 default:
271 return ~0U;
272 }
273 }
274
275 static uint32_t r600_translate_colorswap(enum pipe_format format)
276 {
277 switch (format) {
278 /* 8-bit buffers. */
279 case PIPE_FORMAT_A8_UNORM:
280 case PIPE_FORMAT_A8_UINT:
281 case PIPE_FORMAT_A8_SINT:
282 case PIPE_FORMAT_R4A4_UNORM:
283 return V_0280A0_SWAP_ALT_REV;
284 case PIPE_FORMAT_I8_UNORM:
285 case PIPE_FORMAT_L8_UNORM:
286 case PIPE_FORMAT_I8_UINT:
287 case PIPE_FORMAT_I8_SINT:
288 case PIPE_FORMAT_L8_UINT:
289 case PIPE_FORMAT_L8_SINT:
290 case PIPE_FORMAT_L8_SRGB:
291 case PIPE_FORMAT_R8_UNORM:
292 case PIPE_FORMAT_R8_SNORM:
293 return V_0280A0_SWAP_STD;
294
295 case PIPE_FORMAT_L4A4_UNORM:
296 case PIPE_FORMAT_A4R4_UNORM:
297 return V_0280A0_SWAP_ALT;
298
299 /* 16-bit buffers. */
300 case PIPE_FORMAT_B5G6R5_UNORM:
301 return V_0280A0_SWAP_STD_REV;
302
303 case PIPE_FORMAT_B5G5R5A1_UNORM:
304 case PIPE_FORMAT_B5G5R5X1_UNORM:
305 return V_0280A0_SWAP_ALT;
306
307 case PIPE_FORMAT_B4G4R4A4_UNORM:
308 case PIPE_FORMAT_B4G4R4X4_UNORM:
309 return V_0280A0_SWAP_ALT;
310
311 case PIPE_FORMAT_Z16_UNORM:
312 return V_0280A0_SWAP_STD;
313
314 case PIPE_FORMAT_L8A8_UNORM:
315 case PIPE_FORMAT_L8A8_UINT:
316 case PIPE_FORMAT_L8A8_SINT:
317 case PIPE_FORMAT_L8A8_SRGB:
318 return V_0280A0_SWAP_ALT;
319 case PIPE_FORMAT_R8G8_UNORM:
320 case PIPE_FORMAT_R8G8_UINT:
321 case PIPE_FORMAT_R8G8_SINT:
322 return V_0280A0_SWAP_STD;
323
324 case PIPE_FORMAT_R16_UNORM:
325 case PIPE_FORMAT_R16_UINT:
326 case PIPE_FORMAT_R16_SINT:
327 case PIPE_FORMAT_R16_FLOAT:
328 return V_0280A0_SWAP_STD;
329
330 /* 32-bit buffers. */
331
332 case PIPE_FORMAT_A8B8G8R8_SRGB:
333 return V_0280A0_SWAP_STD_REV;
334 case PIPE_FORMAT_B8G8R8A8_SRGB:
335 return V_0280A0_SWAP_ALT;
336
337 case PIPE_FORMAT_B8G8R8A8_UNORM:
338 case PIPE_FORMAT_B8G8R8X8_UNORM:
339 return V_0280A0_SWAP_ALT;
340
341 case PIPE_FORMAT_A8R8G8B8_UNORM:
342 case PIPE_FORMAT_X8R8G8B8_UNORM:
343 return V_0280A0_SWAP_ALT_REV;
344 case PIPE_FORMAT_R8G8B8A8_SNORM:
345 case PIPE_FORMAT_R8G8B8A8_UNORM:
346 case PIPE_FORMAT_R8G8B8X8_UNORM:
347 case PIPE_FORMAT_R8G8B8A8_SSCALED:
348 case PIPE_FORMAT_R8G8B8A8_USCALED:
349 case PIPE_FORMAT_R8G8B8A8_SINT:
350 case PIPE_FORMAT_R8G8B8A8_UINT:
351 return V_0280A0_SWAP_STD;
352
353 case PIPE_FORMAT_A8B8G8R8_UNORM:
354 case PIPE_FORMAT_X8B8G8R8_UNORM:
355 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
356 return V_0280A0_SWAP_STD_REV;
357
358 case PIPE_FORMAT_Z24X8_UNORM:
359 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
360 return V_0280A0_SWAP_STD;
361
362 case PIPE_FORMAT_X8Z24_UNORM:
363 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
364 return V_0280A0_SWAP_STD;
365
366 case PIPE_FORMAT_R10G10B10A2_UNORM:
367 case PIPE_FORMAT_R10G10B10X2_SNORM:
368 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
369 return V_0280A0_SWAP_STD;
370
371 case PIPE_FORMAT_B10G10R10A2_UNORM:
372 return V_0280A0_SWAP_ALT;
373
374 case PIPE_FORMAT_R11G11B10_FLOAT:
375 case PIPE_FORMAT_R16G16_UNORM:
376 case PIPE_FORMAT_R16G16_FLOAT:
377 case PIPE_FORMAT_R16G16_UINT:
378 case PIPE_FORMAT_R16G16_SINT:
379 case PIPE_FORMAT_R32_UINT:
380 case PIPE_FORMAT_R32_SINT:
381 case PIPE_FORMAT_R32_FLOAT:
382 case PIPE_FORMAT_Z32_FLOAT:
383 return V_0280A0_SWAP_STD;
384
385 /* 64-bit buffers. */
386 case PIPE_FORMAT_R32G32_FLOAT:
387 case PIPE_FORMAT_R32G32_UINT:
388 case PIPE_FORMAT_R32G32_SINT:
389 case PIPE_FORMAT_R16G16B16A16_UNORM:
390 case PIPE_FORMAT_R16G16B16A16_SNORM:
391 case PIPE_FORMAT_R16G16B16A16_USCALED:
392 case PIPE_FORMAT_R16G16B16A16_SSCALED:
393 case PIPE_FORMAT_R16G16B16A16_UINT:
394 case PIPE_FORMAT_R16G16B16A16_SINT:
395 case PIPE_FORMAT_R16G16B16A16_FLOAT:
396 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
397
398 /* 128-bit buffers. */
399 case PIPE_FORMAT_R32G32B32A32_FLOAT:
400 case PIPE_FORMAT_R32G32B32A32_SNORM:
401 case PIPE_FORMAT_R32G32B32A32_UNORM:
402 case PIPE_FORMAT_R32G32B32A32_USCALED:
403 case PIPE_FORMAT_R32G32B32A32_SSCALED:
404 case PIPE_FORMAT_R32G32B32A32_SINT:
405 case PIPE_FORMAT_R32G32B32A32_UINT:
406 return V_0280A0_SWAP_STD;
407 default:
408 R600_ERR("unsupported colorswap format %d\n", format);
409 return ~0U;
410 }
411 return ~0U;
412 }
413
414 static uint32_t r600_translate_colorformat(enum pipe_format format)
415 {
416 switch (format) {
417 case PIPE_FORMAT_L4A4_UNORM:
418 case PIPE_FORMAT_R4A4_UNORM:
419 case PIPE_FORMAT_A4R4_UNORM:
420 return V_0280A0_COLOR_4_4;
421
422 /* 8-bit buffers. */
423 case PIPE_FORMAT_A8_UNORM:
424 case PIPE_FORMAT_A8_UINT:
425 case PIPE_FORMAT_A8_SINT:
426 case PIPE_FORMAT_I8_UNORM:
427 case PIPE_FORMAT_I8_UINT:
428 case PIPE_FORMAT_I8_SINT:
429 case PIPE_FORMAT_L8_UNORM:
430 case PIPE_FORMAT_L8_UINT:
431 case PIPE_FORMAT_L8_SINT:
432 case PIPE_FORMAT_L8_SRGB:
433 case PIPE_FORMAT_R8_UNORM:
434 case PIPE_FORMAT_R8_SNORM:
435 case PIPE_FORMAT_R8_UINT:
436 case PIPE_FORMAT_R8_SINT:
437 return V_0280A0_COLOR_8;
438
439 /* 16-bit buffers. */
440 case PIPE_FORMAT_B5G6R5_UNORM:
441 return V_0280A0_COLOR_5_6_5;
442
443 case PIPE_FORMAT_B5G5R5A1_UNORM:
444 case PIPE_FORMAT_B5G5R5X1_UNORM:
445 return V_0280A0_COLOR_1_5_5_5;
446
447 case PIPE_FORMAT_B4G4R4A4_UNORM:
448 case PIPE_FORMAT_B4G4R4X4_UNORM:
449 return V_0280A0_COLOR_4_4_4_4;
450
451 case PIPE_FORMAT_Z16_UNORM:
452 return V_0280A0_COLOR_16;
453
454 case PIPE_FORMAT_L8A8_UNORM:
455 case PIPE_FORMAT_L8A8_UINT:
456 case PIPE_FORMAT_L8A8_SINT:
457 case PIPE_FORMAT_L8A8_SRGB:
458 case PIPE_FORMAT_R8G8_UNORM:
459 case PIPE_FORMAT_R8G8_UINT:
460 case PIPE_FORMAT_R8G8_SINT:
461 return V_0280A0_COLOR_8_8;
462
463 case PIPE_FORMAT_R16_UNORM:
464 case PIPE_FORMAT_R16_UINT:
465 case PIPE_FORMAT_R16_SINT:
466 return V_0280A0_COLOR_16;
467
468 case PIPE_FORMAT_R16_FLOAT:
469 return V_0280A0_COLOR_16_FLOAT;
470
471 /* 32-bit buffers. */
472 case PIPE_FORMAT_A8B8G8R8_SRGB:
473 case PIPE_FORMAT_A8B8G8R8_UNORM:
474 case PIPE_FORMAT_A8R8G8B8_UNORM:
475 case PIPE_FORMAT_B8G8R8A8_SRGB:
476 case PIPE_FORMAT_B8G8R8A8_UNORM:
477 case PIPE_FORMAT_B8G8R8X8_UNORM:
478 case PIPE_FORMAT_R8G8B8A8_SNORM:
479 case PIPE_FORMAT_R8G8B8A8_UNORM:
480 case PIPE_FORMAT_R8G8B8A8_SSCALED:
481 case PIPE_FORMAT_R8G8B8A8_USCALED:
482 case PIPE_FORMAT_R8G8B8X8_UNORM:
483 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
484 case PIPE_FORMAT_X8B8G8R8_UNORM:
485 case PIPE_FORMAT_X8R8G8B8_UNORM:
486 case PIPE_FORMAT_R8G8B8_UNORM:
487 case PIPE_FORMAT_R8G8B8A8_SINT:
488 case PIPE_FORMAT_R8G8B8A8_UINT:
489 return V_0280A0_COLOR_8_8_8_8;
490
491 case PIPE_FORMAT_R10G10B10A2_UNORM:
492 case PIPE_FORMAT_R10G10B10X2_SNORM:
493 case PIPE_FORMAT_B10G10R10A2_UNORM:
494 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
495 return V_0280A0_COLOR_2_10_10_10;
496
497 case PIPE_FORMAT_Z24X8_UNORM:
498 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
499 return V_0280A0_COLOR_8_24;
500
501 case PIPE_FORMAT_X8Z24_UNORM:
502 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
503 return V_0280A0_COLOR_24_8;
504
505 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
506 return V_0280A0_COLOR_X24_8_32_FLOAT;
507
508 case PIPE_FORMAT_R32_FLOAT:
509 case PIPE_FORMAT_Z32_FLOAT:
510 return V_0280A0_COLOR_32_FLOAT;
511
512 case PIPE_FORMAT_R16G16_FLOAT:
513 return V_0280A0_COLOR_16_16_FLOAT;
514
515 case PIPE_FORMAT_R16G16_SSCALED:
516 case PIPE_FORMAT_R16G16_UNORM:
517 case PIPE_FORMAT_R16G16_UINT:
518 case PIPE_FORMAT_R16G16_SINT:
519 return V_0280A0_COLOR_16_16;
520
521 case PIPE_FORMAT_R11G11B10_FLOAT:
522 return V_0280A0_COLOR_10_11_11_FLOAT;
523
524 /* 64-bit buffers. */
525 case PIPE_FORMAT_R16G16B16_USCALED:
526 case PIPE_FORMAT_R16G16B16A16_USCALED:
527 case PIPE_FORMAT_R16G16B16_SSCALED:
528 case PIPE_FORMAT_R16G16B16A16_UINT:
529 case PIPE_FORMAT_R16G16B16A16_SINT:
530 case PIPE_FORMAT_R16G16B16A16_SSCALED:
531 case PIPE_FORMAT_R16G16B16A16_UNORM:
532 case PIPE_FORMAT_R16G16B16A16_SNORM:
533 return V_0280A0_COLOR_16_16_16_16;
534
535 case PIPE_FORMAT_R16G16B16_FLOAT:
536 case PIPE_FORMAT_R16G16B16A16_FLOAT:
537 return V_0280A0_COLOR_16_16_16_16_FLOAT;
538
539 case PIPE_FORMAT_R32G32_FLOAT:
540 return V_0280A0_COLOR_32_32_FLOAT;
541
542 case PIPE_FORMAT_R32G32_USCALED:
543 case PIPE_FORMAT_R32G32_SSCALED:
544 case PIPE_FORMAT_R32G32_SINT:
545 case PIPE_FORMAT_R32G32_UINT:
546 return V_0280A0_COLOR_32_32;
547
548 /* 96-bit buffers. */
549 case PIPE_FORMAT_R32G32B32_FLOAT:
550 return V_0280A0_COLOR_32_32_32_FLOAT;
551
552 /* 128-bit buffers. */
553 case PIPE_FORMAT_R32G32B32A32_FLOAT:
554 return V_0280A0_COLOR_32_32_32_32_FLOAT;
555 case PIPE_FORMAT_R32G32B32A32_SNORM:
556 case PIPE_FORMAT_R32G32B32A32_UNORM:
557 case PIPE_FORMAT_R32G32B32A32_SSCALED:
558 case PIPE_FORMAT_R32G32B32A32_USCALED:
559 case PIPE_FORMAT_R32G32B32A32_SINT:
560 case PIPE_FORMAT_R32G32B32A32_UINT:
561 return V_0280A0_COLOR_32_32_32_32;
562
563 /* YUV buffers. */
564 case PIPE_FORMAT_UYVY:
565 case PIPE_FORMAT_YUYV:
566 default:
567 return ~0U; /* Unsupported. */
568 }
569 }
570
571 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
572 {
573 if (R600_BIG_ENDIAN) {
574 switch(colorformat) {
575 case V_0280A0_COLOR_4_4:
576 return ENDIAN_NONE;
577
578 /* 8-bit buffers. */
579 case V_0280A0_COLOR_8:
580 return ENDIAN_NONE;
581
582 /* 16-bit buffers. */
583 case V_0280A0_COLOR_5_6_5:
584 case V_0280A0_COLOR_1_5_5_5:
585 case V_0280A0_COLOR_4_4_4_4:
586 case V_0280A0_COLOR_16:
587 case V_0280A0_COLOR_8_8:
588 return ENDIAN_8IN16;
589
590 /* 32-bit buffers. */
591 case V_0280A0_COLOR_8_8_8_8:
592 case V_0280A0_COLOR_2_10_10_10:
593 case V_0280A0_COLOR_8_24:
594 case V_0280A0_COLOR_24_8:
595 case V_0280A0_COLOR_32_FLOAT:
596 case V_0280A0_COLOR_16_16_FLOAT:
597 case V_0280A0_COLOR_16_16:
598 return ENDIAN_8IN32;
599
600 /* 64-bit buffers. */
601 case V_0280A0_COLOR_16_16_16_16:
602 case V_0280A0_COLOR_16_16_16_16_FLOAT:
603 return ENDIAN_8IN16;
604
605 case V_0280A0_COLOR_32_32_FLOAT:
606 case V_0280A0_COLOR_32_32:
607 case V_0280A0_COLOR_X24_8_32_FLOAT:
608 return ENDIAN_8IN32;
609
610 /* 128-bit buffers. */
611 case V_0280A0_COLOR_32_32_32_FLOAT:
612 case V_0280A0_COLOR_32_32_32_32_FLOAT:
613 case V_0280A0_COLOR_32_32_32_32:
614 return ENDIAN_8IN32;
615 default:
616 return ENDIAN_NONE; /* Unsupported. */
617 }
618 } else {
619 return ENDIAN_NONE;
620 }
621 }
622
623 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
624 {
625 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
626 }
627
628 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
629 {
630 return r600_translate_colorformat(format) != ~0U &&
631 r600_translate_colorswap(format) != ~0U;
632 }
633
634 static bool r600_is_zs_format_supported(enum pipe_format format)
635 {
636 return r600_translate_dbformat(format) != ~0U;
637 }
638
639 boolean r600_is_format_supported(struct pipe_screen *screen,
640 enum pipe_format format,
641 enum pipe_texture_target target,
642 unsigned sample_count,
643 unsigned usage)
644 {
645 unsigned retval = 0;
646
647 if (target >= PIPE_MAX_TEXTURE_TYPES) {
648 R600_ERR("r600: unsupported texture type %d\n", target);
649 return FALSE;
650 }
651
652 if (!util_format_is_supported(format, usage))
653 return FALSE;
654
655 /* Multisample */
656 if (sample_count > 1)
657 return FALSE;
658
659 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
660 r600_is_sampler_format_supported(screen, format)) {
661 retval |= PIPE_BIND_SAMPLER_VIEW;
662 }
663
664 if ((usage & (PIPE_BIND_RENDER_TARGET |
665 PIPE_BIND_DISPLAY_TARGET |
666 PIPE_BIND_SCANOUT |
667 PIPE_BIND_SHARED)) &&
668 r600_is_colorbuffer_format_supported(format)) {
669 retval |= usage &
670 (PIPE_BIND_RENDER_TARGET |
671 PIPE_BIND_DISPLAY_TARGET |
672 PIPE_BIND_SCANOUT |
673 PIPE_BIND_SHARED);
674 }
675
676 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
677 r600_is_zs_format_supported(format)) {
678 retval |= PIPE_BIND_DEPTH_STENCIL;
679 }
680
681 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
682 r600_is_vertex_format_supported(format)) {
683 retval |= PIPE_BIND_VERTEX_BUFFER;
684 }
685
686 if (usage & PIPE_BIND_TRANSFER_READ)
687 retval |= PIPE_BIND_TRANSFER_READ;
688 if (usage & PIPE_BIND_TRANSFER_WRITE)
689 retval |= PIPE_BIND_TRANSFER_WRITE;
690
691 return retval == usage;
692 }
693
694 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
695 {
696 struct r600_pipe_state state;
697
698 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
699 state.nregs = 0;
700 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
701 float offset_units = rctx->rasterizer->offset_units;
702 unsigned offset_db_fmt_cntl = 0, depth;
703
704 switch (rctx->framebuffer.zsbuf->texture->format) {
705 case PIPE_FORMAT_Z24X8_UNORM:
706 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
707 depth = -24;
708 offset_units *= 2.0f;
709 break;
710 case PIPE_FORMAT_Z32_FLOAT:
711 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
712 depth = -23;
713 offset_units *= 1.0f;
714 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
715 break;
716 case PIPE_FORMAT_Z16_UNORM:
717 depth = -16;
718 offset_units *= 4.0f;
719 break;
720 default:
721 return;
722 }
723 /* FIXME some of those reg can be computed with cso */
724 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
725 r600_pipe_state_add_reg(&state,
726 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
727 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
728 r600_pipe_state_add_reg(&state,
729 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
730 fui(offset_units), 0xFFFFFFFF, NULL, 0);
731 r600_pipe_state_add_reg(&state,
732 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
733 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
734 r600_pipe_state_add_reg(&state,
735 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
736 fui(offset_units), 0xFFFFFFFF, NULL, 0);
737 r600_pipe_state_add_reg(&state,
738 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
739 offset_db_fmt_cntl, 0xFFFFFFFF, NULL, 0);
740 r600_context_pipe_state_set(&rctx->ctx, &state);
741 }
742 }
743
744 static void r600_set_blend_color(struct pipe_context *ctx,
745 const struct pipe_blend_color *state)
746 {
747 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
748 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
749
750 if (rstate == NULL)
751 return;
752
753 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
754 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL, 0);
755 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL, 0);
756 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL, 0);
757 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL, 0);
758 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
759 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
760 r600_context_pipe_state_set(&rctx->ctx, rstate);
761 }
762
763 static void *r600_create_blend_state(struct pipe_context *ctx,
764 const struct pipe_blend_state *state)
765 {
766 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
767 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
768 struct r600_pipe_state *rstate;
769 u32 color_control = 0, target_mask;
770
771 if (blend == NULL) {
772 return NULL;
773 }
774 rstate = &blend->rstate;
775
776 rstate->id = R600_PIPE_STATE_BLEND;
777
778 target_mask = 0;
779
780 /* R600 does not support per-MRT blends */
781 if (rctx->family > CHIP_R600)
782 color_control |= S_028808_PER_MRT_BLEND(1);
783 if (state->logicop_enable) {
784 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
785 } else {
786 color_control |= (0xcc << 16);
787 }
788 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
789 if (state->independent_blend_enable) {
790 for (int i = 0; i < 8; i++) {
791 if (state->rt[i].blend_enable) {
792 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
793 }
794 target_mask |= (state->rt[i].colormask << (4 * i));
795 }
796 } else {
797 for (int i = 0; i < 8; i++) {
798 if (state->rt[0].blend_enable) {
799 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
800 }
801 target_mask |= (state->rt[0].colormask << (4 * i));
802 }
803 }
804 blend->cb_target_mask = target_mask;
805 /* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */
806 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
807 color_control, 0xFFFFFFFD, NULL, 0);
808
809 for (int i = 0; i < 8; i++) {
810 /* state->rt entries > 0 only written if independent blending */
811 const int j = state->independent_blend_enable ? i : 0;
812
813 unsigned eqRGB = state->rt[j].rgb_func;
814 unsigned srcRGB = state->rt[j].rgb_src_factor;
815 unsigned dstRGB = state->rt[j].rgb_dst_factor;
816
817 unsigned eqA = state->rt[j].alpha_func;
818 unsigned srcA = state->rt[j].alpha_src_factor;
819 unsigned dstA = state->rt[j].alpha_dst_factor;
820 uint32_t bc = 0;
821
822 if (!state->rt[j].blend_enable)
823 continue;
824
825 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
826 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
827 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
828
829 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
830 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
831 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
832 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
833 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
834 }
835
836 /* R600 does not support per-MRT blends */
837 if (rctx->family > CHIP_R600)
838 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL, 0);
839 if (i == 0)
840 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL, 0);
841 }
842 return rstate;
843 }
844
845 static void *r600_create_dsa_state(struct pipe_context *ctx,
846 const struct pipe_depth_stencil_alpha_state *state)
847 {
848 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
849 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
850 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
851 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
852 struct r600_pipe_state *rstate;
853
854 if (dsa == NULL) {
855 return NULL;
856 }
857
858 rstate = &dsa->rstate;
859
860 rstate->id = R600_PIPE_STATE_DSA;
861 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
862 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
863 stencil_ref_mask = 0;
864 stencil_ref_mask_bf = 0;
865 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
866 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
867 S_028800_ZFUNC(state->depth.func);
868
869 /* stencil */
870 if (state->stencil[0].enabled) {
871 db_depth_control |= S_028800_STENCIL_ENABLE(1);
872 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
873 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
874 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
875 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
876
877
878 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
879 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
880 if (state->stencil[1].enabled) {
881 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
882 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
883 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
884 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
885 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
886 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
887 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
888 }
889 }
890
891 /* alpha */
892 alpha_test_control = 0;
893 alpha_ref = 0;
894 if (state->alpha.enabled) {
895 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
896 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
897 alpha_ref = fui(state->alpha.ref_value);
898 }
899 dsa->alpha_ref = alpha_ref;
900
901 /* misc */
902 db_render_control = 0;
903 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
904 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
905 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
906 /* TODO db_render_override depends on query */
907 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL, 0);
908 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL, 0);
909 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL, 0);
910 r600_pipe_state_add_reg(rstate,
911 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
912 0xFFFFFFFF & C_028430_STENCILREF, NULL, 0);
913 r600_pipe_state_add_reg(rstate,
914 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
915 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL, 0);
916 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL, 0);
917 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL, 0);
918 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
919 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL, 0);
920 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
921 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
922 * r600_pipe_shader_ps().*/
923 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL, 0);
924 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL, 0);
925 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL, 0);
926 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL, 0);
927 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL, 0);
928 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL, 0);
929
930 return rstate;
931 }
932
933 static void *r600_create_rs_state(struct pipe_context *ctx,
934 const struct pipe_rasterizer_state *state)
935 {
936 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
937 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
938 struct r600_pipe_state *rstate;
939 unsigned tmp;
940 unsigned prov_vtx = 1, polygon_dual_mode;
941 unsigned clip_rule;
942
943 if (rs == NULL) {
944 return NULL;
945 }
946
947 rstate = &rs->rstate;
948 rs->clamp_vertex_color = state->clamp_vertex_color;
949 rs->clamp_fragment_color = state->clamp_fragment_color;
950 rs->flatshade = state->flatshade;
951 rs->sprite_coord_enable = state->sprite_coord_enable;
952
953 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
954 /* offset */
955 rs->offset_units = state->offset_units;
956 rs->offset_scale = state->offset_scale * 12.0f;
957
958 rstate->id = R600_PIPE_STATE_RASTERIZER;
959 if (state->flatshade_first)
960 prov_vtx = 0;
961 tmp = S_0286D4_FLAT_SHADE_ENA(1);
962 if (state->sprite_coord_enable) {
963 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
964 S_0286D4_PNT_SPRITE_OVRD_X(2) |
965 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
966 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
967 S_0286D4_PNT_SPRITE_OVRD_W(1);
968 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
969 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
970 }
971 }
972 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL, 0);
973
974 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
975 state->fill_back != PIPE_POLYGON_MODE_FILL);
976 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
977 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
978 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
979 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
980 S_028814_FACE(!state->front_ccw) |
981 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
982 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
983 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
984 S_028814_POLY_MODE(polygon_dual_mode) |
985 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
986 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL, 0);
987 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
988 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
989 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL, 0);
990 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
991 /* point size 12.4 fixed point */
992 tmp = (unsigned)(state->point_size * 8.0);
993 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
994 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL, 0);
995
996 tmp = (unsigned)state->line_width * 8;
997 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
998
999 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL, 0);
1000 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1001 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
1002
1003 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
1004 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
1005 0xFFFFFFFF, NULL, 0);
1006
1007 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1008 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1009 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1010 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1011 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), 0xFFFFFFFF, NULL, 0);
1012 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL, 0);
1013
1014 return rstate;
1015 }
1016
1017 static void *r600_create_sampler_state(struct pipe_context *ctx,
1018 const struct pipe_sampler_state *state)
1019 {
1020 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
1021 struct r600_pipe_state *rstate;
1022 union util_color uc;
1023 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
1024
1025 if (ss == NULL) {
1026 return NULL;
1027 }
1028
1029 ss->seamless_cube_map = state->seamless_cube_map;
1030 rstate = &ss->rstate;
1031 rstate->id = R600_PIPE_STATE_SAMPLER;
1032 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1033 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
1034 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1035 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1036 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1037 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1038 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1039 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1040 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1041 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1042 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL, 0);
1043 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
1044 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1045 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1046 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL, 0);
1047 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL, 0);
1048 if (uc.ui) {
1049 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), 0xFFFFFFFF, NULL, 0);
1050 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), 0xFFFFFFFF, NULL, 0);
1051 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), 0xFFFFFFFF, NULL, 0);
1052 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), 0xFFFFFFFF, NULL, 0);
1053 }
1054 return rstate;
1055 }
1056
1057 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1058 struct pipe_resource *texture,
1059 const struct pipe_sampler_view *state)
1060 {
1061 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1062 struct r600_pipe_resource_state *rstate;
1063 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1064 unsigned format, endian;
1065 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1066 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1067 unsigned width, height, depth, offset_level, last_level;
1068
1069 if (view == NULL)
1070 return NULL;
1071 rstate = &view->state;
1072
1073 /* initialize base object */
1074 view->base = *state;
1075 view->base.texture = NULL;
1076 pipe_reference(NULL, &texture->reference);
1077 view->base.texture = texture;
1078 view->base.reference.count = 1;
1079 view->base.context = ctx;
1080
1081 swizzle[0] = state->swizzle_r;
1082 swizzle[1] = state->swizzle_g;
1083 swizzle[2] = state->swizzle_b;
1084 swizzle[3] = state->swizzle_a;
1085
1086 format = r600_translate_texformat(ctx->screen, state->format,
1087 swizzle,
1088 &word4, &yuv_format);
1089 if (format == ~0) {
1090 format = 0;
1091 }
1092
1093 if (tmp->depth && !tmp->is_flushing_texture) {
1094 r600_texture_depth_flush(ctx, texture, TRUE);
1095 tmp = tmp->flushed_depth_texture;
1096 }
1097
1098 endian = r600_colorformat_endian_swap(format);
1099
1100 offset_level = state->u.tex.first_level;
1101 last_level = state->u.tex.last_level - offset_level;
1102 width = u_minify(texture->width0, offset_level);
1103 height = u_minify(texture->height0, offset_level);
1104 depth = u_minify(texture->depth0, offset_level);
1105
1106 pitch = align(tmp->pitch_in_blocks[offset_level] *
1107 util_format_get_blockwidth(state->format), 8);
1108 array_mode = tmp->array_mode[offset_level];
1109 tile_type = tmp->tile_type;
1110
1111 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1112 height = 1;
1113 depth = texture->array_size;
1114 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1115 depth = texture->array_size;
1116 }
1117
1118 rstate->bo[0] = &tmp->resource;
1119 rstate->bo[1] = &tmp->resource;
1120 rstate->bo_usage[0] = RADEON_USAGE_READ;
1121 rstate->bo_usage[1] = RADEON_USAGE_READ;
1122
1123 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1124 S_038000_TILE_MODE(array_mode) |
1125 S_038000_TILE_TYPE(tile_type) |
1126 S_038000_PITCH((pitch / 8) - 1) |
1127 S_038000_TEX_WIDTH(width - 1));
1128 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1129 S_038004_TEX_DEPTH(depth - 1) |
1130 S_038004_DATA_FORMAT(format));
1131 rstate->val[2] = tmp->offset[offset_level] >> 8;
1132 rstate->val[3] = tmp->offset[offset_level+1] >> 8;
1133 rstate->val[4] = (word4 |
1134 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1135 S_038010_REQUEST_SIZE(1) |
1136 S_038010_ENDIAN_SWAP(endian) |
1137 S_038010_BASE_LEVEL(0));
1138 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1139 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1140 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1141 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1142 S_038018_MAX_ANISO(4 /* max 16 samples */));
1143
1144 return &view->base;
1145 }
1146
1147 static void r600_set_sampler_views(struct r600_pipe_context *rctx,
1148 struct r600_textures_info *dst,
1149 unsigned count,
1150 struct pipe_sampler_view **views,
1151 void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned))
1152 {
1153 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
1154 unsigned i;
1155
1156 for (i = 0; i < count; i++) {
1157 if (rviews[i]) {
1158 if (((struct r600_resource_texture *)rviews[i]->base.texture)->depth)
1159 rctx->have_depth_texture = true;
1160
1161 /* Changing from array to non-arrays textures and vice versa requires updating TEX_ARRAY_OVERRIDE. */
1162 if ((rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1163 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i])
1164 dst->samplers_dirty = true;
1165
1166 set_resource(&rctx->ctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS);
1167 } else {
1168 set_resource(&rctx->ctx, NULL, i + R600_MAX_CONST_BUFFERS);
1169 }
1170
1171 pipe_sampler_view_reference(
1172 (struct pipe_sampler_view **)&dst->views[i],
1173 views[i]);
1174 }
1175
1176 for (i = count; i < dst->n_views; i++) {
1177 if (dst->views[i]) {
1178 set_resource(&rctx->ctx, NULL, i + R600_MAX_CONST_BUFFERS);
1179 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL);
1180 }
1181 }
1182
1183 dst->n_views = count;
1184 }
1185
1186 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1187 struct pipe_sampler_view **views)
1188 {
1189 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1190 r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views,
1191 r600_context_pipe_state_set_vs_resource);
1192 }
1193
1194 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1195 struct pipe_sampler_view **views)
1196 {
1197 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1198 r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views,
1199 r600_context_pipe_state_set_ps_resource);
1200 }
1201
1202 static void r600_set_seamless_cubemap(struct r600_pipe_context *rctx, boolean enable)
1203 {
1204 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1205 if (rstate == NULL)
1206 return;
1207
1208 rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP;
1209 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1210 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)),
1211 1, NULL, 0);
1212
1213 free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]);
1214 rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate;
1215 r600_context_pipe_state_set(&rctx->ctx, rstate);
1216 }
1217
1218 static void r600_bind_samplers(struct r600_pipe_context *rctx,
1219 struct r600_textures_info *dst,
1220 unsigned count, void **states)
1221 {
1222 memcpy(dst->samplers, states, sizeof(void*) * count);
1223 dst->n_samplers = count;
1224 dst->samplers_dirty = true;
1225 }
1226
1227 static void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
1228 {
1229 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1230 r600_bind_samplers(rctx, &rctx->vs_samplers, count, states);
1231 }
1232
1233 static void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
1234 {
1235 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1236 r600_bind_samplers(rctx, &rctx->ps_samplers, count, states);
1237 }
1238
1239 static void r600_update_samplers(struct r600_pipe_context *rctx,
1240 struct r600_textures_info *tex,
1241 void (*set_sampler)(struct r600_context*, struct r600_pipe_state*, unsigned))
1242 {
1243 unsigned i;
1244
1245 if (tex->samplers_dirty) {
1246 int seamless = -1;
1247 for (i = 0; i < tex->n_samplers; i++) {
1248 if (!tex->samplers[i])
1249 continue;
1250
1251 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1252 * filtering between layers.
1253 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */
1254 if (tex->views[i]) {
1255 if (tex->views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1256 tex->views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1257 tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1258 tex->is_array_sampler[i] = true;
1259 } else {
1260 tex->samplers[i]->rstate.regs[0].value &= C_03C000_TEX_ARRAY_OVERRIDE;
1261 tex->is_array_sampler[i] = false;
1262 }
1263 }
1264
1265 set_sampler(&rctx->ctx, &tex->samplers[i]->rstate, i);
1266
1267 if (tex->samplers[i])
1268 seamless = tex->samplers[i]->seamless_cube_map;
1269 }
1270
1271 if (seamless != -1)
1272 r600_set_seamless_cubemap(rctx, seamless);
1273
1274 tex->samplers_dirty = false;
1275 }
1276 }
1277
1278 void r600_update_sampler_states(struct r600_pipe_context *rctx)
1279 {
1280 r600_update_samplers(rctx, &rctx->vs_samplers,
1281 r600_context_pipe_state_set_vs_sampler);
1282 r600_update_samplers(rctx, &rctx->ps_samplers,
1283 r600_context_pipe_state_set_ps_sampler);
1284 }
1285
1286 static void r600_set_clip_state(struct pipe_context *ctx,
1287 const struct pipe_clip_state *state)
1288 {
1289 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1290 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1291
1292 if (rstate == NULL)
1293 return;
1294
1295 rctx->clip = *state;
1296 rstate->id = R600_PIPE_STATE_CLIP;
1297 for (int i = 0; i < state->nr; i++) {
1298 r600_pipe_state_add_reg(rstate,
1299 R_028E20_PA_CL_UCP0_X + i * 16,
1300 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL, 0);
1301 r600_pipe_state_add_reg(rstate,
1302 R_028E24_PA_CL_UCP0_Y + i * 16,
1303 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL, 0);
1304 r600_pipe_state_add_reg(rstate,
1305 R_028E28_PA_CL_UCP0_Z + i * 16,
1306 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL, 0);
1307 r600_pipe_state_add_reg(rstate,
1308 R_028E2C_PA_CL_UCP0_W + i * 16,
1309 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL, 0);
1310 }
1311 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1312 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
1313 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
1314 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL, 0);
1315
1316 free(rctx->states[R600_PIPE_STATE_CLIP]);
1317 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1318 r600_context_pipe_state_set(&rctx->ctx, rstate);
1319 }
1320
1321 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1322 const struct pipe_poly_stipple *state)
1323 {
1324 }
1325
1326 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1327 {
1328 }
1329
1330 static void r600_set_scissor_state(struct pipe_context *ctx,
1331 const struct pipe_scissor_state *state)
1332 {
1333 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1334 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1335 u32 tl, br;
1336
1337 if (rstate == NULL)
1338 return;
1339
1340 rstate->id = R600_PIPE_STATE_SCISSOR;
1341 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1342 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1343 r600_pipe_state_add_reg(rstate,
1344 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1345 0xFFFFFFFF, NULL, 0);
1346 r600_pipe_state_add_reg(rstate,
1347 R_028214_PA_SC_CLIPRECT_0_BR, br,
1348 0xFFFFFFFF, NULL, 0);
1349 r600_pipe_state_add_reg(rstate,
1350 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1351 0xFFFFFFFF, NULL, 0);
1352 r600_pipe_state_add_reg(rstate,
1353 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1354 0xFFFFFFFF, NULL, 0);
1355 r600_pipe_state_add_reg(rstate,
1356 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1357 0xFFFFFFFF, NULL, 0);
1358 r600_pipe_state_add_reg(rstate,
1359 R_028224_PA_SC_CLIPRECT_2_BR, br,
1360 0xFFFFFFFF, NULL, 0);
1361 r600_pipe_state_add_reg(rstate,
1362 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1363 0xFFFFFFFF, NULL, 0);
1364 r600_pipe_state_add_reg(rstate,
1365 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1366 0xFFFFFFFF, NULL, 0);
1367
1368 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1369 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1370 r600_context_pipe_state_set(&rctx->ctx, rstate);
1371 }
1372
1373 static void r600_set_stencil_ref(struct pipe_context *ctx,
1374 const struct pipe_stencil_ref *state)
1375 {
1376 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1377 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1378 u32 tmp;
1379
1380 if (rstate == NULL)
1381 return;
1382
1383 rctx->stencil_ref = *state;
1384 rstate->id = R600_PIPE_STATE_STENCIL_REF;
1385 tmp = S_028430_STENCILREF(state->ref_value[0]);
1386 r600_pipe_state_add_reg(rstate,
1387 R_028430_DB_STENCILREFMASK, tmp,
1388 ~C_028430_STENCILREF, NULL, 0);
1389 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
1390 r600_pipe_state_add_reg(rstate,
1391 R_028434_DB_STENCILREFMASK_BF, tmp,
1392 ~C_028434_STENCILREF_BF, NULL, 0);
1393
1394 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
1395 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
1396 r600_context_pipe_state_set(&rctx->ctx, rstate);
1397 }
1398
1399 static void r600_set_viewport_state(struct pipe_context *ctx,
1400 const struct pipe_viewport_state *state)
1401 {
1402 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1403 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1404
1405 if (rstate == NULL)
1406 return;
1407
1408 rctx->viewport = *state;
1409 rstate->id = R600_PIPE_STATE_VIEWPORT;
1410 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
1411 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1412 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL, 0);
1413 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL, 0);
1414 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL, 0);
1415 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL, 0);
1416 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL, 0);
1417 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL, 0);
1418 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL, 0);
1419
1420 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1421 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1422 r600_context_pipe_state_set(&rctx->ctx, rstate);
1423 }
1424
1425 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1426 const struct pipe_framebuffer_state *state, int cb)
1427 {
1428 struct r600_resource_texture *rtex;
1429 struct r600_surface *surf;
1430 unsigned level = state->cbufs[cb]->u.tex.level;
1431 unsigned pitch, slice;
1432 unsigned color_info;
1433 unsigned format, swap, ntype, endian;
1434 unsigned offset;
1435 const struct util_format_description *desc;
1436 int i;
1437
1438 surf = (struct r600_surface *)state->cbufs[cb];
1439 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1440
1441 if (rtex->depth)
1442 rctx->have_depth_fb = TRUE;
1443
1444 if (rtex->depth && !rtex->is_flushing_texture) {
1445 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1446 rtex = rtex->flushed_depth_texture;
1447 }
1448
1449 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1450 offset = r600_texture_get_offset(rtex,
1451 level, state->cbufs[cb]->u.tex.first_layer);
1452 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1453 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1454 desc = util_format_description(surf->base.format);
1455
1456 for (i = 0; i < 4; i++) {
1457 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1458 break;
1459 }
1460 }
1461
1462 ntype = V_0280A0_NUMBER_UNORM;
1463 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1464 ntype = V_0280A0_NUMBER_SRGB;
1465 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1466 if (desc->channel[i].normalized)
1467 ntype = V_0280A0_NUMBER_SNORM;
1468 else if (desc->channel[i].pure_integer)
1469 ntype = V_0280A0_NUMBER_SINT;
1470 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1471 if (desc->channel[i].normalized)
1472 ntype = V_0280A0_NUMBER_UNORM;
1473 else if (desc->channel[i].pure_integer)
1474 ntype = V_0280A0_NUMBER_UINT;
1475 }
1476
1477 format = r600_translate_colorformat(surf->base.format);
1478 swap = r600_translate_colorswap(surf->base.format);
1479 if(rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1480 endian = ENDIAN_NONE;
1481 } else {
1482 endian = r600_colorformat_endian_swap(format);
1483 }
1484
1485 color_info = S_0280A0_FORMAT(format) |
1486 S_0280A0_COMP_SWAP(swap) |
1487 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
1488 S_0280A0_BLEND_CLAMP(1) |
1489 S_0280A0_NUMBER_TYPE(ntype) |
1490 S_0280A0_ENDIAN(endian);
1491
1492 /* EXPORT_NORM is an optimzation that can be enabled for better
1493 * performance in certain cases
1494 */
1495 if (rctx->chip_class == R600) {
1496 /* EXPORT_NORM can be enabled if:
1497 * - 11-bit or smaller UNORM/SNORM/SRGB
1498 * - BLEND_CLAMP is enabled
1499 * - BLEND_FLOAT32 is disabled
1500 */
1501 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1502 (desc->channel[i].size < 12 &&
1503 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1504 ntype != V_0280A0_NUMBER_UINT &&
1505 ntype != V_0280A0_NUMBER_SINT) &&
1506 G_0280A0_BLEND_CLAMP(color_info) &&
1507 !G_0280A0_BLEND_FLOAT32(color_info))
1508 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1509 } else {
1510 /* EXPORT_NORM can be enabled if:
1511 * - 11-bit or smaller UNORM/SNORM/SRGB
1512 * - 16-bit or smaller FLOAT
1513 */
1514 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1515 ((desc->channel[i].size < 12 &&
1516 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1517 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1518 (desc->channel[i].size < 17 &&
1519 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)))
1520 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1521 }
1522
1523 r600_pipe_state_add_reg(rstate,
1524 R_028040_CB_COLOR0_BASE + cb * 4,
1525 offset >> 8, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1526 r600_pipe_state_add_reg(rstate,
1527 R_0280A0_CB_COLOR0_INFO + cb * 4,
1528 color_info, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1529 r600_pipe_state_add_reg(rstate,
1530 R_028060_CB_COLOR0_SIZE + cb * 4,
1531 S_028060_PITCH_TILE_MAX(pitch) |
1532 S_028060_SLICE_TILE_MAX(slice),
1533 0xFFFFFFFF, NULL, 0);
1534 r600_pipe_state_add_reg(rstate,
1535 R_028080_CB_COLOR0_VIEW + cb * 4,
1536 0x00000000, 0xFFFFFFFF, NULL, 0);
1537 r600_pipe_state_add_reg(rstate,
1538 R_0280E0_CB_COLOR0_FRAG + cb * 4,
1539 0, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1540 r600_pipe_state_add_reg(rstate,
1541 R_0280C0_CB_COLOR0_TILE + cb * 4,
1542 0, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1543 r600_pipe_state_add_reg(rstate,
1544 R_028100_CB_COLOR0_MASK + cb * 4,
1545 0x00000000, 0xFFFFFFFF, NULL, 0);
1546 }
1547
1548 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1549 const struct pipe_framebuffer_state *state)
1550 {
1551 struct r600_resource_texture *rtex;
1552 struct r600_surface *surf;
1553 unsigned level, pitch, slice, format, offset, array_mode;
1554
1555 if (state->zsbuf == NULL)
1556 return;
1557
1558 level = state->zsbuf->u.tex.level;
1559
1560 surf = (struct r600_surface *)state->zsbuf;
1561 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1562
1563 /* XXX remove this once tiling is properly supported */
1564 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1565 V_0280A0_ARRAY_1D_TILED_THIN1;
1566
1567 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1568 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1569 level, state->zsbuf->u.tex.first_layer);
1570 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1571 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1572 format = r600_translate_dbformat(state->zsbuf->texture->format);
1573
1574 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1575 offset >> 8, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1576 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1577 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1578 0xFFFFFFFF, NULL, 0);
1579 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL, 0);
1580 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1581 S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format),
1582 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
1583 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1584 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL, 0);
1585 }
1586
1587 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1588 const struct pipe_framebuffer_state *state)
1589 {
1590 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1591 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1592 u32 shader_mask, tl, br, shader_control, target_mask;
1593
1594 if (rstate == NULL)
1595 return;
1596
1597 r600_context_flush_dest_caches(&rctx->ctx);
1598 rctx->ctx.num_dest_buffers = state->nr_cbufs;
1599
1600 /* unreference old buffer and reference new one */
1601 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1602
1603 util_copy_framebuffer_state(&rctx->framebuffer, state);
1604
1605 /* build states */
1606 rctx->have_depth_fb = 0;
1607 for (int i = 0; i < state->nr_cbufs; i++) {
1608 r600_cb(rctx, rstate, state, i);
1609 }
1610 if (state->zsbuf) {
1611 r600_db(rctx, rstate, state);
1612 rctx->ctx.num_dest_buffers++;
1613 }
1614
1615 target_mask = 0x00000000;
1616 target_mask = 0xFFFFFFFF;
1617 shader_mask = 0;
1618 shader_control = 0;
1619 for (int i = 0; i < state->nr_cbufs; i++) {
1620 target_mask ^= 0xf << (i * 4);
1621 shader_mask |= 0xf << (i * 4);
1622 shader_control |= 1 << i;
1623 }
1624 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1625 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1626
1627 r600_pipe_state_add_reg(rstate,
1628 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1629 0xFFFFFFFF, NULL, 0);
1630 r600_pipe_state_add_reg(rstate,
1631 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1632 0xFFFFFFFF, NULL, 0);
1633 r600_pipe_state_add_reg(rstate,
1634 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1635 0xFFFFFFFF, NULL, 0);
1636 r600_pipe_state_add_reg(rstate,
1637 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1638 0xFFFFFFFF, NULL, 0);
1639 r600_pipe_state_add_reg(rstate,
1640 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1641 0xFFFFFFFF, NULL, 0);
1642 r600_pipe_state_add_reg(rstate,
1643 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1644 0xFFFFFFFF, NULL, 0);
1645 r600_pipe_state_add_reg(rstate,
1646 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1647 0xFFFFFFFF, NULL, 0);
1648 r600_pipe_state_add_reg(rstate,
1649 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1650 0xFFFFFFFF, NULL, 0);
1651 r600_pipe_state_add_reg(rstate,
1652 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1653 0xFFFFFFFF, NULL, 0);
1654 if (rctx->chip_class >= R700) {
1655 r600_pipe_state_add_reg(rstate,
1656 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1657 0xFFFFFFFF, NULL, 0);
1658 }
1659
1660 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1661 shader_control, 0xFFFFFFFF, NULL, 0);
1662 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1663 0x00000000, target_mask, NULL, 0);
1664 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1665 shader_mask, 0xFFFFFFFF, NULL, 0);
1666 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1667 0x00000000, 0xFFFFFFFF, NULL, 0);
1668 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1669 0x00000000, 0xFFFFFFFF, NULL, 0);
1670 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1671 0x00000000, 0xFFFFFFFF, NULL, 0);
1672 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1673 0x01000000, 0xFFFFFFFF, NULL, 0);
1674 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1675 0x00000000, 0xFFFFFFFF, NULL, 0);
1676 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1677 0x000000FF, 0xFFFFFFFF, NULL, 0);
1678 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1679 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
1680 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1681 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
1682
1683 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1684 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1685 r600_context_pipe_state_set(&rctx->ctx, rstate);
1686
1687 if (state->zsbuf) {
1688 r600_polygon_offset_update(rctx);
1689 }
1690 }
1691
1692 static void r600_texture_barrier(struct pipe_context *ctx)
1693 {
1694 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1695
1696 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1697 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1698 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1699 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1700 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1));
1701 }
1702
1703 void r600_init_state_functions(struct r600_pipe_context *rctx)
1704 {
1705 rctx->context.create_blend_state = r600_create_blend_state;
1706 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1707 rctx->context.create_fs_state = r600_create_shader_state;
1708 rctx->context.create_rasterizer_state = r600_create_rs_state;
1709 rctx->context.create_sampler_state = r600_create_sampler_state;
1710 rctx->context.create_sampler_view = r600_create_sampler_view;
1711 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1712 rctx->context.create_vs_state = r600_create_shader_state;
1713 rctx->context.bind_blend_state = r600_bind_blend_state;
1714 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1715 rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1716 rctx->context.bind_fs_state = r600_bind_ps_shader;
1717 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1718 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1719 rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1720 rctx->context.bind_vs_state = r600_bind_vs_shader;
1721 rctx->context.delete_blend_state = r600_delete_state;
1722 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1723 rctx->context.delete_fs_state = r600_delete_ps_shader;
1724 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1725 rctx->context.delete_sampler_state = r600_delete_state;
1726 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1727 rctx->context.delete_vs_state = r600_delete_vs_shader;
1728 rctx->context.set_blend_color = r600_set_blend_color;
1729 rctx->context.set_clip_state = r600_set_clip_state;
1730 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1731 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1732 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1733 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1734 rctx->context.set_sample_mask = r600_set_sample_mask;
1735 rctx->context.set_scissor_state = r600_set_scissor_state;
1736 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1737 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1738 rctx->context.set_index_buffer = r600_set_index_buffer;
1739 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1740 rctx->context.set_viewport_state = r600_set_viewport_state;
1741 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1742 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1743 rctx->context.texture_barrier = r600_texture_barrier;
1744 }
1745
1746 void r600_adjust_gprs(struct r600_pipe_context *rctx)
1747 {
1748 struct r600_pipe_state rstate;
1749 unsigned num_ps_gprs = rctx->default_ps_gprs;
1750 unsigned num_vs_gprs = rctx->default_vs_gprs;
1751 unsigned tmp;
1752 int diff;
1753
1754 if (rctx->chip_class >= EVERGREEN)
1755 return;
1756
1757 if (!rctx->ps_shader || !rctx->vs_shader)
1758 return;
1759
1760 if (rctx->ps_shader->shader.bc.ngpr > rctx->default_ps_gprs)
1761 {
1762 diff = rctx->ps_shader->shader.bc.ngpr - rctx->default_ps_gprs;
1763 num_vs_gprs -= diff;
1764 num_ps_gprs += diff;
1765 }
1766
1767 if (rctx->vs_shader->shader.bc.ngpr > rctx->default_vs_gprs)
1768 {
1769 diff = rctx->vs_shader->shader.bc.ngpr - rctx->default_vs_gprs;
1770 num_ps_gprs -= diff;
1771 num_vs_gprs += diff;
1772 }
1773
1774 tmp = 0;
1775 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1776 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1777 rstate.nregs = 0;
1778 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0x0FFFFFFF, NULL, 0);
1779
1780 r600_context_pipe_state_set(&rctx->ctx, &rstate);
1781 }
1782
1783 void r600_init_config(struct r600_pipe_context *rctx)
1784 {
1785 int ps_prio;
1786 int vs_prio;
1787 int gs_prio;
1788 int es_prio;
1789 int num_ps_gprs;
1790 int num_vs_gprs;
1791 int num_gs_gprs;
1792 int num_es_gprs;
1793 int num_temp_gprs;
1794 int num_ps_threads;
1795 int num_vs_threads;
1796 int num_gs_threads;
1797 int num_es_threads;
1798 int num_ps_stack_entries;
1799 int num_vs_stack_entries;
1800 int num_gs_stack_entries;
1801 int num_es_stack_entries;
1802 enum radeon_family family;
1803 struct r600_pipe_state *rstate = &rctx->config;
1804 u32 tmp;
1805
1806 family = rctx->family;
1807 ps_prio = 0;
1808 vs_prio = 1;
1809 gs_prio = 2;
1810 es_prio = 3;
1811 switch (family) {
1812 case CHIP_R600:
1813 num_ps_gprs = 192;
1814 num_vs_gprs = 56;
1815 num_temp_gprs = 4;
1816 num_gs_gprs = 0;
1817 num_es_gprs = 0;
1818 num_ps_threads = 136;
1819 num_vs_threads = 48;
1820 num_gs_threads = 4;
1821 num_es_threads = 4;
1822 num_ps_stack_entries = 128;
1823 num_vs_stack_entries = 128;
1824 num_gs_stack_entries = 0;
1825 num_es_stack_entries = 0;
1826 break;
1827 case CHIP_RV630:
1828 case CHIP_RV635:
1829 num_ps_gprs = 84;
1830 num_vs_gprs = 36;
1831 num_temp_gprs = 4;
1832 num_gs_gprs = 0;
1833 num_es_gprs = 0;
1834 num_ps_threads = 144;
1835 num_vs_threads = 40;
1836 num_gs_threads = 4;
1837 num_es_threads = 4;
1838 num_ps_stack_entries = 40;
1839 num_vs_stack_entries = 40;
1840 num_gs_stack_entries = 32;
1841 num_es_stack_entries = 16;
1842 break;
1843 case CHIP_RV610:
1844 case CHIP_RV620:
1845 case CHIP_RS780:
1846 case CHIP_RS880:
1847 default:
1848 num_ps_gprs = 84;
1849 num_vs_gprs = 36;
1850 num_temp_gprs = 4;
1851 num_gs_gprs = 0;
1852 num_es_gprs = 0;
1853 num_ps_threads = 136;
1854 num_vs_threads = 48;
1855 num_gs_threads = 4;
1856 num_es_threads = 4;
1857 num_ps_stack_entries = 40;
1858 num_vs_stack_entries = 40;
1859 num_gs_stack_entries = 32;
1860 num_es_stack_entries = 16;
1861 break;
1862 case CHIP_RV670:
1863 num_ps_gprs = 144;
1864 num_vs_gprs = 40;
1865 num_temp_gprs = 4;
1866 num_gs_gprs = 0;
1867 num_es_gprs = 0;
1868 num_ps_threads = 136;
1869 num_vs_threads = 48;
1870 num_gs_threads = 4;
1871 num_es_threads = 4;
1872 num_ps_stack_entries = 40;
1873 num_vs_stack_entries = 40;
1874 num_gs_stack_entries = 32;
1875 num_es_stack_entries = 16;
1876 break;
1877 case CHIP_RV770:
1878 num_ps_gprs = 192;
1879 num_vs_gprs = 56;
1880 num_temp_gprs = 4;
1881 num_gs_gprs = 0;
1882 num_es_gprs = 0;
1883 num_ps_threads = 188;
1884 num_vs_threads = 60;
1885 num_gs_threads = 0;
1886 num_es_threads = 0;
1887 num_ps_stack_entries = 256;
1888 num_vs_stack_entries = 256;
1889 num_gs_stack_entries = 0;
1890 num_es_stack_entries = 0;
1891 break;
1892 case CHIP_RV730:
1893 case CHIP_RV740:
1894 num_ps_gprs = 84;
1895 num_vs_gprs = 36;
1896 num_temp_gprs = 4;
1897 num_gs_gprs = 0;
1898 num_es_gprs = 0;
1899 num_ps_threads = 188;
1900 num_vs_threads = 60;
1901 num_gs_threads = 0;
1902 num_es_threads = 0;
1903 num_ps_stack_entries = 128;
1904 num_vs_stack_entries = 128;
1905 num_gs_stack_entries = 0;
1906 num_es_stack_entries = 0;
1907 break;
1908 case CHIP_RV710:
1909 num_ps_gprs = 192;
1910 num_vs_gprs = 56;
1911 num_temp_gprs = 4;
1912 num_gs_gprs = 0;
1913 num_es_gprs = 0;
1914 num_ps_threads = 144;
1915 num_vs_threads = 48;
1916 num_gs_threads = 0;
1917 num_es_threads = 0;
1918 num_ps_stack_entries = 128;
1919 num_vs_stack_entries = 128;
1920 num_gs_stack_entries = 0;
1921 num_es_stack_entries = 0;
1922 break;
1923 }
1924
1925 rctx->default_ps_gprs = num_ps_gprs;
1926 rctx->default_vs_gprs = num_vs_gprs;
1927
1928 rstate->id = R600_PIPE_STATE_CONFIG;
1929
1930 /* SQ_CONFIG */
1931 tmp = 0;
1932 switch (family) {
1933 case CHIP_RV610:
1934 case CHIP_RV620:
1935 case CHIP_RS780:
1936 case CHIP_RS880:
1937 case CHIP_RV710:
1938 break;
1939 default:
1940 tmp |= S_008C00_VC_ENABLE(1);
1941 break;
1942 }
1943 tmp |= S_008C00_DX9_CONSTS(0);
1944 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1945 tmp |= S_008C00_PS_PRIO(ps_prio);
1946 tmp |= S_008C00_VS_PRIO(vs_prio);
1947 tmp |= S_008C00_GS_PRIO(gs_prio);
1948 tmp |= S_008C00_ES_PRIO(es_prio);
1949 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
1950
1951 /* SQ_GPR_RESOURCE_MGMT_1 */
1952 tmp = 0;
1953 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1954 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1955 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1956 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
1957
1958 /* SQ_GPR_RESOURCE_MGMT_2 */
1959 tmp = 0;
1960 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1961 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1962 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
1963
1964 /* SQ_THREAD_RESOURCE_MGMT */
1965 tmp = 0;
1966 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1967 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1968 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1969 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1970 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL, 0);
1971
1972 /* SQ_STACK_RESOURCE_MGMT_1 */
1973 tmp = 0;
1974 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1975 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1976 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
1977
1978 /* SQ_STACK_RESOURCE_MGMT_2 */
1979 tmp = 0;
1980 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1981 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1982 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
1983
1984 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1985 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL, 0);
1986
1987 if (rctx->chip_class >= R700) {
1988 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL, 0);
1989 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1990 S_009508_DISABLE_CUBE_ANISO(1) |
1991 S_009508_SYNC_GRADIENT(1) |
1992 S_009508_SYNC_WALKER(1) |
1993 S_009508_SYNC_ALIGNER(1), 0xFFFFFFFF, NULL, 0);
1994 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL, 0);
1995 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL, 0);
1996 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL, 0);
1997 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL, 0);
1998 } else {
1999 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL, 0);
2000 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
2001 S_009508_DISABLE_CUBE_ANISO(1) |
2002 S_009508_SYNC_GRADIENT(1) |
2003 S_009508_SYNC_WALKER(1) |
2004 S_009508_SYNC_ALIGNER(1), 0xFFFFFFFF, NULL, 0);
2005 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL, 0);
2006 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL, 0);
2007 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL, 0);
2008 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL, 0);
2009 }
2010 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2011 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2012 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2013 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2014 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2015 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2016 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2017 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2018 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2019 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2020 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2021 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2022 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2023 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL, 0);
2024 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2025 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL, 0);
2026 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL, 0);
2027 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2028 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2029 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2030 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
2031 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL, 0);
2032 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2033 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL, 0);
2034 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2035 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2036
2037 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL, 0);
2038 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2039 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2040 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
2041 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL, 0);
2042 r600_context_pipe_state_set(&rctx->ctx, rstate);
2043 }
2044
2045 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2046 {
2047 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2048 struct r600_pipe_state *rstate = &shader->rstate;
2049 struct r600_shader *rshader = &shader->shader;
2050 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2051 int pos_index = -1, face_index = -1;
2052
2053 rstate->nregs = 0;
2054
2055 for (i = 0; i < rshader->ninput; i++) {
2056 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2057 pos_index = i;
2058 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2059 face_index = i;
2060 }
2061
2062 db_shader_control = 0;
2063 for (i = 0; i < rshader->noutput; i++) {
2064 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2065 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2066 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2067 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
2068 }
2069 if (rshader->uses_kill)
2070 db_shader_control |= S_02880C_KILL_ENABLE(1);
2071
2072 exports_ps = 0;
2073 num_cout = 0;
2074 for (i = 0; i < rshader->noutput; i++) {
2075 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2076 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2077 exports_ps |= 1;
2078 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2079 num_cout++;
2080 }
2081 }
2082 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2083 if (!exports_ps) {
2084 /* always at least export 1 component per pixel */
2085 exports_ps = 2;
2086 }
2087
2088 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2089 S_0286CC_PERSP_GRADIENT_ENA(1);
2090 spi_input_z = 0;
2091 if (pos_index != -1) {
2092 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2093 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2094 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2095 S_0286CC_BARYC_SAMPLE_CNTL(1));
2096 spi_input_z |= 1;
2097 }
2098
2099 spi_ps_in_control_1 = 0;
2100 if (face_index != -1) {
2101 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2102 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2103 }
2104
2105 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL, 0);
2106 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL, 0);
2107 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL, 0);
2108 r600_pipe_state_add_reg(rstate,
2109 R_028840_SQ_PGM_START_PS,
2110 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2111 r600_pipe_state_add_reg(rstate,
2112 R_028850_SQ_PGM_RESOURCES_PS,
2113 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2114 S_028850_STACK_SIZE(rshader->bc.nstack),
2115 0xFFFFFFFF, NULL, 0);
2116 r600_pipe_state_add_reg(rstate,
2117 R_028854_SQ_PGM_EXPORTS_PS,
2118 exports_ps, 0xFFFFFFFF, NULL, 0);
2119 r600_pipe_state_add_reg(rstate,
2120 R_0288CC_SQ_PGM_CF_OFFSET_PS,
2121 0x00000000, 0xFFFFFFFF, NULL, 0);
2122 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
2123 S_028808_MULTIWRITE_ENABLE(!!rshader->fs_write_all),
2124 S_028808_MULTIWRITE_ENABLE(1),
2125 NULL, 0);
2126 /* only set some bits here, the other bits are set in the dsa state */
2127 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2128 db_shader_control,
2129 S_02880C_Z_EXPORT_ENABLE(1) |
2130 S_02880C_STENCIL_REF_EXPORT_ENABLE(1) |
2131 S_02880C_KILL_ENABLE(1),
2132 NULL, 0);
2133
2134 r600_pipe_state_add_reg(rstate,
2135 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
2136 0xFFFFFFFF, NULL, 0);
2137 }
2138
2139 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2140 {
2141 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2142 struct r600_pipe_state *rstate = &shader->rstate;
2143 struct r600_shader *rshader = &shader->shader;
2144 unsigned spi_vs_out_id[10];
2145 unsigned i, tmp, nparams = 0;
2146
2147 /* clear previous register */
2148 rstate->nregs = 0;
2149
2150 for (i = 0; i < rshader->noutput; i++) {
2151 if (rshader->output[i].spi_sid) {
2152 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2153 spi_vs_out_id[nparams / 4] |= tmp;
2154 nparams++;
2155 }
2156 }
2157
2158 for (i = 0; i < 10; i++) {
2159 r600_pipe_state_add_reg(rstate,
2160 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2161 spi_vs_out_id[i], 0xFFFFFFFF, NULL, 0);
2162 }
2163
2164 /* Certain attributes (position, psize, etc.) don't count as params.
2165 * VS is required to export at least one param and r600_shader_from_tgsi()
2166 * takes care of adding a dummy export.
2167 */
2168 if (nparams < 1)
2169 nparams = 1;
2170
2171 r600_pipe_state_add_reg(rstate,
2172 R_0286C4_SPI_VS_OUT_CONFIG,
2173 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2174 0xFFFFFFFF, NULL, 0);
2175 r600_pipe_state_add_reg(rstate,
2176 R_028868_SQ_PGM_RESOURCES_VS,
2177 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2178 S_028868_STACK_SIZE(rshader->bc.nstack),
2179 0xFFFFFFFF, NULL, 0);
2180 r600_pipe_state_add_reg(rstate,
2181 R_0288D0_SQ_PGM_CF_OFFSET_VS,
2182 0x00000000, 0xFFFFFFFF, NULL, 0);
2183 r600_pipe_state_add_reg(rstate,
2184 R_028858_SQ_PGM_START_VS,
2185 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2186
2187 r600_pipe_state_add_reg(rstate,
2188 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2189 0xFFFFFFFF, NULL, 0);
2190 }
2191
2192 void r600_fetch_shader(struct pipe_context *ctx,
2193 struct r600_vertex_element *ve)
2194 {
2195 struct r600_pipe_state *rstate;
2196 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2197
2198 rstate = &ve->rstate;
2199 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2200 rstate->nregs = 0;
2201 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
2202 0x00000000, 0xFFFFFFFF, NULL, 0);
2203 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
2204 0x00000000, 0xFFFFFFFF, NULL, 0);
2205 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
2206 0,
2207 0xFFFFFFFF, ve->fetch_shader, RADEON_USAGE_READ);
2208 }
2209
2210 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
2211 {
2212 struct pipe_depth_stencil_alpha_state dsa;
2213 struct r600_pipe_state *rstate;
2214 boolean quirk = false;
2215
2216 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2217 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2218 quirk = true;
2219
2220 memset(&dsa, 0, sizeof(dsa));
2221
2222 if (quirk) {
2223 dsa.depth.enabled = 1;
2224 dsa.depth.func = PIPE_FUNC_LEQUAL;
2225 dsa.stencil[0].enabled = 1;
2226 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2227 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2228 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2229 dsa.stencil[0].writemask = 0xff;
2230 }
2231
2232 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2233 r600_pipe_state_add_reg(rstate,
2234 R_02880C_DB_SHADER_CONTROL,
2235 0x0,
2236 S_02880C_DUAL_EXPORT_ENABLE(1), NULL, 0);
2237 r600_pipe_state_add_reg(rstate,
2238 R_028D0C_DB_RENDER_CONTROL,
2239 S_028D0C_DEPTH_COPY_ENABLE(1) |
2240 S_028D0C_STENCIL_COPY_ENABLE(1) |
2241 S_028D0C_COPY_CENTROID(1),
2242 S_028D0C_DEPTH_COPY_ENABLE(1) |
2243 S_028D0C_STENCIL_COPY_ENABLE(1) |
2244 S_028D0C_COPY_CENTROID(1), NULL, 0);
2245 return rstate;
2246 }
2247
2248 void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
2249 struct r600_pipe_resource_state *rstate)
2250 {
2251 rstate->id = R600_PIPE_STATE_RESOURCE;
2252
2253 rstate->bo[0] = NULL;
2254 rstate->val[0] = 0;
2255 rstate->val[1] = 0;
2256 rstate->val[2] = 0;
2257 rstate->val[3] = 0;
2258 rstate->val[4] = 0;
2259 rstate->val[5] = 0;
2260 rstate->val[6] = 0xc0000000;
2261 }
2262
2263 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
2264 struct r600_resource *rbuffer,
2265 unsigned offset, unsigned stride,
2266 enum radeon_bo_usage usage)
2267 {
2268 rstate->val[0] = offset;
2269 rstate->bo[0] = rbuffer;
2270 rstate->bo_usage[0] = usage;
2271 rstate->val[1] = rbuffer->buf->size - offset - 1;
2272 rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2273 S_038008_STRIDE(stride);
2274 }