2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "util/u_inlines.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "r600_screen.h"
32 #include "r600_context.h"
33 #include "r600_resource.h"
35 #include "r600_state_inlines.h"
37 static void r600_blend(struct r600_context
*rctx
, struct radeon_state
*rstate
, const struct pipe_blend_state
*state
);
38 static void r600_viewport(struct r600_context
*rctx
, struct radeon_state
*rstate
, const struct pipe_viewport_state
*state
);
39 static void r600_ucp(struct r600_context
*rctx
, struct radeon_state
*rstate
, const struct pipe_clip_state
*state
);
40 static void r600_sampler(struct r600_context
*rctx
, struct radeon_state
*rstate
, const struct pipe_sampler_state
*state
, unsigned id
);
41 static void r600_resource(struct pipe_context
*ctx
, struct radeon_state
*rstate
, const struct pipe_sampler_view
*view
, unsigned id
);
42 static void r600_cb(struct r600_context
*rctx
, struct radeon_state
*rstate
,
43 const struct pipe_framebuffer_state
*state
, int cb
);
44 static void r600_db(struct r600_context
*rctx
, struct radeon_state
*rstate
,
45 const struct pipe_framebuffer_state
*state
);
48 static void *r600_create_blend_state(struct pipe_context
*ctx
,
49 const struct pipe_blend_state
*state
)
51 struct r600_context
*rctx
= r600_context(ctx
);
53 return r600_context_state(rctx
, pipe_blend_type
, state
);
56 static void *r600_create_dsa_state(struct pipe_context
*ctx
,
57 const struct pipe_depth_stencil_alpha_state
*state
)
59 struct r600_context
*rctx
= r600_context(ctx
);
61 return r600_context_state(rctx
, pipe_dsa_type
, state
);
64 static void *r600_create_rs_state(struct pipe_context
*ctx
,
65 const struct pipe_rasterizer_state
*state
)
67 struct r600_context
*rctx
= r600_context(ctx
);
69 return r600_context_state(rctx
, pipe_rasterizer_type
, state
);
72 static void *r600_create_sampler_state(struct pipe_context
*ctx
,
73 const struct pipe_sampler_state
*state
)
75 struct r600_context
*rctx
= r600_context(ctx
);
77 return r600_context_state(rctx
, pipe_sampler_type
, state
);
80 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
81 struct pipe_sampler_view
*state
)
83 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
85 r600_context_state_decref(rstate
);
88 static struct pipe_sampler_view
*r600_create_sampler_view(struct pipe_context
*ctx
,
89 struct pipe_resource
*texture
,
90 const struct pipe_sampler_view
*state
)
92 struct r600_context
*rctx
= r600_context(ctx
);
93 struct r600_context_state
*rstate
;
95 rstate
= r600_context_state(rctx
, pipe_sampler_view_type
, state
);
96 pipe_reference(NULL
, &texture
->reference
);
97 rstate
->state
.sampler_view
.texture
= texture
;
98 rstate
->state
.sampler_view
.reference
.count
= 1;
99 rstate
->state
.sampler_view
.context
= ctx
;
100 r600_resource(ctx
, &rstate
->rstate
[0], &rstate
->state
.sampler_view
, 0);
101 return &rstate
->state
.sampler_view
;
104 static void r600_set_ps_sampler_view(struct pipe_context
*ctx
,
106 struct pipe_sampler_view
**views
)
108 struct r600_context
*rctx
= r600_context(ctx
);
109 struct r600_context_state
*rstate
;
112 for (i
= 0; i
< rctx
->ps_nsampler_view
; i
++) {
113 radeon_draw_unbind(&rctx
->draw
, rctx
->ps_sampler_view
[i
]);
115 for (i
= 0; i
< count
; i
++) {
116 rstate
= (struct r600_context_state
*)views
[i
];
121 for (i
= 0; i
< count
; i
++) {
122 rstate
= (struct r600_context_state
*)views
[i
];
124 if (rstate
->nrstate
>= R600_MAX_RSTATE
)
126 if (rstate
->nrstate
) {
127 memcpy(&rstate
->rstate
[rstate
->nrstate
], &rstate
->rstate
[0], sizeof(struct radeon_state
));
129 radeon_state_convert(&rstate
->rstate
[rstate
->nrstate
], R600_STATE_RESOURCE
, i
, R600_SHADER_PS
);
130 rctx
->ps_sampler_view
[i
] = &rstate
->rstate
[rstate
->nrstate
];
134 rctx
->ps_nsampler_view
= count
;
137 static void r600_set_vs_sampler_view(struct pipe_context
*ctx
,
139 struct pipe_sampler_view
**views
)
141 struct r600_context
*rctx
= r600_context(ctx
);
142 struct r600_context_state
*rstate
;
145 for (i
= 0; i
< rctx
->vs_nsampler_view
; i
++) {
146 radeon_draw_unbind(&rctx
->draw
, rctx
->vs_sampler_view
[i
]);
148 for (i
= 0; i
< count
; i
++) {
149 rstate
= (struct r600_context_state
*)views
[i
];
154 for (i
= 0; i
< count
; i
++) {
155 rstate
= (struct r600_context_state
*)views
[i
];
157 if (rstate
->nrstate
>= R600_MAX_RSTATE
)
159 if (rstate
->nrstate
) {
160 memcpy(&rstate
->rstate
[rstate
->nrstate
], &rstate
->rstate
[0], sizeof(struct radeon_state
));
162 radeon_state_convert(&rstate
->rstate
[rstate
->nrstate
], R600_STATE_RESOURCE
, i
, R600_SHADER_VS
);
163 rctx
->vs_sampler_view
[i
] = &rstate
->rstate
[rstate
->nrstate
];
167 rctx
->vs_nsampler_view
= count
;
170 static void *r600_create_shader_state(struct pipe_context
*ctx
,
171 const struct pipe_shader_state
*state
)
173 struct r600_context
*rctx
= r600_context(ctx
);
175 return r600_context_state(rctx
, pipe_shader_type
, state
);
178 static void *r600_create_vertex_elements(struct pipe_context
*ctx
,
180 const struct pipe_vertex_element
*elements
)
182 struct r600_vertex_element
*v
= CALLOC_STRUCT(r600_vertex_element
);
186 memcpy(v
->elements
, elements
, count
* sizeof(struct pipe_vertex_element
));
191 static void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
193 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
202 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
204 struct r600_context
*rctx
= r600_context(ctx
);
205 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
207 r600_delete_vertex_element(ctx
, rctx
->vertex_elements
);
208 rctx
->vertex_elements
= v
;
214 static void r600_bind_state(struct pipe_context
*ctx
, void *state
)
216 struct r600_context
*rctx
= r600_context(ctx
);
217 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
221 switch (rstate
->type
) {
222 case pipe_rasterizer_type
:
223 rctx
->rasterizer
= r600_context_state_decref(rctx
->rasterizer
);
224 rctx
->rasterizer
= r600_context_state_incref(rstate
);
226 case pipe_poly_stipple_type
:
227 rctx
->poly_stipple
= r600_context_state_decref(rctx
->poly_stipple
);
228 rctx
->poly_stipple
= r600_context_state_incref(rstate
);
230 case pipe_scissor_type
:
231 rctx
->scissor
= r600_context_state_decref(rctx
->scissor
);
232 rctx
->scissor
= r600_context_state_incref(rstate
);
235 rctx
->clip
= r600_context_state_decref(rctx
->clip
);
236 rctx
->clip
= r600_context_state_incref(rstate
);
238 case pipe_depth_type
:
239 rctx
->depth
= r600_context_state_decref(rctx
->depth
);
240 rctx
->depth
= r600_context_state_incref(rstate
);
242 case pipe_stencil_type
:
243 rctx
->stencil
= r600_context_state_decref(rctx
->stencil
);
244 rctx
->stencil
= r600_context_state_incref(rstate
);
246 case pipe_alpha_type
:
247 rctx
->alpha
= r600_context_state_decref(rctx
->alpha
);
248 rctx
->alpha
= r600_context_state_incref(rstate
);
251 rctx
->dsa
= r600_context_state_decref(rctx
->dsa
);
252 rctx
->dsa
= r600_context_state_incref(rstate
);
254 case pipe_blend_type
:
255 rctx
->blend
= r600_context_state_decref(rctx
->blend
);
256 rctx
->blend
= r600_context_state_incref(rstate
);
258 case pipe_framebuffer_type
:
259 rctx
->framebuffer
= r600_context_state_decref(rctx
->framebuffer
);
260 rctx
->framebuffer
= r600_context_state_incref(rstate
);
262 case pipe_stencil_ref_type
:
263 rctx
->stencil_ref
= r600_context_state_decref(rctx
->stencil_ref
);
264 rctx
->stencil_ref
= r600_context_state_incref(rstate
);
266 case pipe_viewport_type
:
267 rctx
->viewport
= r600_context_state_decref(rctx
->viewport
);
268 rctx
->viewport
= r600_context_state_incref(rstate
);
270 case pipe_shader_type
:
271 case pipe_sampler_type
:
272 case pipe_sampler_view_type
:
274 R600_ERR("invalid type %d\n", rstate
->type
);
279 static void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
281 struct r600_context
*rctx
= r600_context(ctx
);
282 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
284 rctx
->ps_shader
= r600_context_state_decref(rctx
->ps_shader
);
285 rctx
->ps_shader
= r600_context_state_incref(rstate
);
288 static void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
290 struct r600_context
*rctx
= r600_context(ctx
);
291 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
293 rctx
->vs_shader
= r600_context_state_decref(rctx
->vs_shader
);
294 rctx
->vs_shader
= r600_context_state_incref(rstate
);
297 static void r600_bind_ps_sampler(struct pipe_context
*ctx
,
298 unsigned count
, void **states
)
300 struct r600_context
*rctx
= r600_context(ctx
);
301 struct r600_context_state
*rstate
;
304 for (i
= 0; i
< rctx
->ps_nsampler
; i
++) {
305 radeon_draw_unbind(&rctx
->draw
, rctx
->ps_sampler
[i
]);
307 for (i
= 0; i
< count
; i
++) {
308 rstate
= (struct r600_context_state
*)states
[i
];
313 for (i
= 0; i
< count
; i
++) {
314 rstate
= (struct r600_context_state
*)states
[i
];
316 if (rstate
->nrstate
>= R600_MAX_RSTATE
)
318 if (rstate
->nrstate
) {
319 memcpy(&rstate
->rstate
[rstate
->nrstate
], &rstate
->rstate
[0], sizeof(struct radeon_state
));
321 radeon_state_convert(&rstate
->rstate
[rstate
->nrstate
], R600_STATE_SAMPLER
, i
, R600_SHADER_PS
);
322 rctx
->ps_sampler
[i
] = &rstate
->rstate
[rstate
->nrstate
];
326 rctx
->ps_nsampler
= count
;
329 static void r600_bind_vs_sampler(struct pipe_context
*ctx
,
330 unsigned count
, void **states
)
332 struct r600_context
*rctx
= r600_context(ctx
);
333 struct r600_context_state
*rstate
;
336 for (i
= 0; i
< rctx
->vs_nsampler
; i
++) {
337 radeon_draw_unbind(&rctx
->draw
, rctx
->vs_sampler
[i
]);
339 for (i
= 0; i
< count
; i
++) {
340 rstate
= (struct r600_context_state
*)states
[i
];
345 for (i
= 0; i
< count
; i
++) {
346 rstate
= (struct r600_context_state
*)states
[i
];
348 if (rstate
->nrstate
>= R600_MAX_RSTATE
)
350 if (rstate
->nrstate
) {
351 memcpy(&rstate
->rstate
[rstate
->nrstate
], &rstate
->rstate
[0], sizeof(struct radeon_state
));
353 radeon_state_convert(&rstate
->rstate
[rstate
->nrstate
], R600_STATE_SAMPLER
, i
, R600_SHADER_VS
);
354 rctx
->vs_sampler
[i
] = &rstate
->rstate
[rstate
->nrstate
];
358 rctx
->vs_nsampler
= count
;
361 static void r600_delete_state(struct pipe_context
*ctx
, void *state
)
363 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
365 r600_context_state_decref(rstate
);
368 static void r600_set_blend_color(struct pipe_context
*ctx
,
369 const struct pipe_blend_color
*color
)
371 struct r600_context
*rctx
= r600_context(ctx
);
373 rctx
->blend_color
= *color
;
376 static void r600_set_clip_state(struct pipe_context
*ctx
,
377 const struct pipe_clip_state
*state
)
379 struct r600_context
*rctx
= r600_context(ctx
);
380 struct r600_context_state
*rstate
;
382 rstate
= r600_context_state(rctx
, pipe_clip_type
, state
);
383 r600_bind_state(ctx
, rstate
);
384 /* refcount is taken care of this */
385 r600_delete_state(ctx
, rstate
);
388 static void r600_set_constant_buffer(struct pipe_context
*ctx
,
389 uint shader
, uint index
,
390 struct pipe_resource
*buffer
)
392 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
393 struct r600_context
*rctx
= r600_context(ctx
);
394 unsigned nconstant
= 0, i
, type
, shader_class
;
395 struct radeon_state
*rstate
, *rstates
;
396 struct pipe_transfer
*transfer
;
399 type
= R600_STATE_CONSTANT
;
402 case PIPE_SHADER_VERTEX
:
403 shader_class
= R600_SHADER_VS
;
404 rstates
= rctx
->vs_constant
;
406 case PIPE_SHADER_FRAGMENT
:
407 shader_class
= R600_SHADER_PS
;
408 rstates
= rctx
->ps_constant
;
411 R600_ERR("unsupported %d\n", shader
);
414 if (buffer
&& buffer
->width0
> 0) {
415 nconstant
= buffer
->width0
/ 16;
416 ptr
= pipe_buffer_map(ctx
, buffer
, PIPE_TRANSFER_READ
, &transfer
);
419 for (i
= 0; i
< nconstant
; i
++) {
420 rstate
= &rstates
[i
];
421 radeon_state_init(rstate
, rscreen
->rw
, type
, i
, shader_class
);
422 rstate
->states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0
] = ptr
[i
* 4 + 0];
423 rstate
->states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0
] = ptr
[i
* 4 + 1];
424 rstate
->states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0
] = ptr
[i
* 4 + 2];
425 rstate
->states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0
] = ptr
[i
* 4 + 3];
426 if (radeon_state_pm4(rstate
))
428 radeon_draw_bind(&rctx
->draw
, rstate
);
430 pipe_buffer_unmap(ctx
, buffer
, transfer
);
434 static void r600_set_framebuffer_state(struct pipe_context
*ctx
,
435 const struct pipe_framebuffer_state
*state
)
437 struct r600_context
*rctx
= r600_context(ctx
);
438 struct r600_context_state
*rstate
;
440 rstate
= r600_context_state(rctx
, pipe_framebuffer_type
, state
);
441 r600_bind_state(ctx
, rstate
);
442 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
443 r600_cb(rctx
, &rstate
->rstate
[i
+1], state
, i
);
446 r600_db(rctx
, &rstate
->rstate
[0], state
);
450 static void r600_set_polygon_stipple(struct pipe_context
*ctx
,
451 const struct pipe_poly_stipple
*state
)
455 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
459 static void r600_set_scissor_state(struct pipe_context
*ctx
,
460 const struct pipe_scissor_state
*state
)
462 struct r600_context
*rctx
= r600_context(ctx
);
463 struct r600_context_state
*rstate
;
465 rstate
= r600_context_state(rctx
, pipe_scissor_type
, state
);
466 r600_bind_state(ctx
, rstate
);
467 /* refcount is taken care of this */
468 r600_delete_state(ctx
, rstate
);
471 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
472 const struct pipe_stencil_ref
*state
)
474 struct r600_context
*rctx
= r600_context(ctx
);
475 struct r600_context_state
*rstate
;
477 rstate
= r600_context_state(rctx
, pipe_stencil_ref_type
, state
);
478 r600_bind_state(ctx
, rstate
);
479 /* refcount is taken care of this */
480 r600_delete_state(ctx
, rstate
);
483 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
485 const struct pipe_vertex_buffer
*buffers
)
487 struct r600_context
*rctx
= r600_context(ctx
);
490 for (i
= 0; i
< rctx
->nvertex_buffer
; i
++) {
491 pipe_resource_reference(&rctx
->vertex_buffer
[i
].buffer
, NULL
);
493 memcpy(rctx
->vertex_buffer
, buffers
, sizeof(struct pipe_vertex_buffer
) * count
);
494 for (i
= 0; i
< count
; i
++) {
495 rctx
->vertex_buffer
[i
].buffer
= NULL
;
496 pipe_resource_reference(&rctx
->vertex_buffer
[i
].buffer
, buffers
[i
].buffer
);
498 rctx
->nvertex_buffer
= count
;
501 static void r600_set_index_buffer(struct pipe_context
*ctx
,
502 const struct pipe_index_buffer
*ib
)
504 struct r600_context
*rctx
= r600_context(ctx
);
507 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
508 memcpy(&rctx
->index_buffer
, ib
, sizeof(rctx
->index_buffer
));
510 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
511 memset(&rctx
->index_buffer
, 0, sizeof(rctx
->index_buffer
));
514 /* TODO make this more like a state */
517 static void r600_set_viewport_state(struct pipe_context
*ctx
,
518 const struct pipe_viewport_state
*state
)
520 struct r600_context
*rctx
= r600_context(ctx
);
521 struct r600_context_state
*rstate
;
523 rstate
= r600_context_state(rctx
, pipe_viewport_type
, state
);
524 r600_bind_state(ctx
, rstate
);
525 r600_delete_state(ctx
, rstate
);
528 void r600_init_state_functions(struct r600_context
*rctx
)
530 rctx
->context
.create_blend_state
= r600_create_blend_state
;
531 rctx
->context
.create_depth_stencil_alpha_state
= r600_create_dsa_state
;
532 rctx
->context
.create_fs_state
= r600_create_shader_state
;
533 rctx
->context
.create_rasterizer_state
= r600_create_rs_state
;
534 rctx
->context
.create_sampler_state
= r600_create_sampler_state
;
535 rctx
->context
.create_sampler_view
= r600_create_sampler_view
;
536 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
537 rctx
->context
.create_vs_state
= r600_create_shader_state
;
538 rctx
->context
.bind_blend_state
= r600_bind_state
;
539 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_state
;
540 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_sampler
;
541 rctx
->context
.bind_fs_state
= r600_bind_ps_shader
;
542 rctx
->context
.bind_rasterizer_state
= r600_bind_state
;
543 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
544 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_sampler
;
545 rctx
->context
.bind_vs_state
= r600_bind_vs_shader
;
546 rctx
->context
.delete_blend_state
= r600_delete_state
;
547 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
548 rctx
->context
.delete_fs_state
= r600_delete_state
;
549 rctx
->context
.delete_rasterizer_state
= r600_delete_state
;
550 rctx
->context
.delete_sampler_state
= r600_delete_state
;
551 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_element
;
552 rctx
->context
.delete_vs_state
= r600_delete_state
;
553 rctx
->context
.set_blend_color
= r600_set_blend_color
;
554 rctx
->context
.set_clip_state
= r600_set_clip_state
;
555 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
556 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_view
;
557 rctx
->context
.set_framebuffer_state
= r600_set_framebuffer_state
;
558 rctx
->context
.set_polygon_stipple
= r600_set_polygon_stipple
;
559 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
560 rctx
->context
.set_scissor_state
= r600_set_scissor_state
;
561 rctx
->context
.set_stencil_ref
= r600_set_stencil_ref
;
562 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
563 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
564 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_view
;
565 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
566 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
569 struct r600_context_state
*r600_context_state_incref(struct r600_context_state
*rstate
)
577 struct r600_context_state
*r600_context_state_decref(struct r600_context_state
*rstate
)
583 if (--rstate
->refcount
)
585 switch (rstate
->type
) {
586 case pipe_sampler_view_type
:
587 pipe_resource_reference(&rstate
->state
.sampler_view
.texture
, NULL
);
589 case pipe_framebuffer_type
:
590 for (i
= 0; i
< rstate
->state
.framebuffer
.nr_cbufs
; i
++) {
591 pipe_surface_reference(&rstate
->state
.framebuffer
.cbufs
[i
], NULL
);
593 pipe_surface_reference(&rstate
->state
.framebuffer
.zsbuf
, NULL
);
595 case pipe_viewport_type
:
596 case pipe_depth_type
:
597 case pipe_rasterizer_type
:
598 case pipe_poly_stipple_type
:
599 case pipe_scissor_type
:
601 case pipe_stencil_type
:
602 case pipe_alpha_type
:
604 case pipe_blend_type
:
605 case pipe_stencil_ref_type
:
606 case pipe_shader_type
:
607 case pipe_sampler_type
:
610 R600_ERR("invalid type %d\n", rstate
->type
);
613 radeon_state_fini(&rstate
->rstate
[0]);
618 struct r600_context_state
*r600_context_state(struct r600_context
*rctx
, unsigned type
, const void *state
)
620 struct r600_context_state
*rstate
= CALLOC_STRUCT(r600_context_state
);
621 const union pipe_states
*states
= state
;
628 rstate
->refcount
= 1;
630 switch (rstate
->type
) {
631 case pipe_sampler_view_type
:
632 rstate
->state
.sampler_view
= (*states
).sampler_view
;
633 rstate
->state
.sampler_view
.texture
= NULL
;
635 case pipe_framebuffer_type
:
636 rstate
->state
.framebuffer
= (*states
).framebuffer
;
637 for (i
= 0; i
< rstate
->state
.framebuffer
.nr_cbufs
; i
++) {
638 pipe_surface_reference(&rstate
->state
.framebuffer
.cbufs
[i
],
639 (*states
).framebuffer
.cbufs
[i
]);
641 pipe_surface_reference(&rstate
->state
.framebuffer
.zsbuf
,
642 (*states
).framebuffer
.zsbuf
);
644 case pipe_viewport_type
:
645 rstate
->state
.viewport
= (*states
).viewport
;
646 r600_viewport(rctx
, &rstate
->rstate
[0], &rstate
->state
.viewport
);
648 case pipe_depth_type
:
649 rstate
->state
.depth
= (*states
).depth
;
651 case pipe_rasterizer_type
:
652 rstate
->state
.rasterizer
= (*states
).rasterizer
;
654 case pipe_poly_stipple_type
:
655 rstate
->state
.poly_stipple
= (*states
).poly_stipple
;
657 case pipe_scissor_type
:
658 rstate
->state
.scissor
= (*states
).scissor
;
661 rstate
->state
.clip
= (*states
).clip
;
662 r600_ucp(rctx
, &rstate
->rstate
[0], &rstate
->state
.clip
);
664 case pipe_stencil_type
:
665 rstate
->state
.stencil
= (*states
).stencil
;
667 case pipe_alpha_type
:
668 rstate
->state
.alpha
= (*states
).alpha
;
671 rstate
->state
.dsa
= (*states
).dsa
;
673 case pipe_blend_type
:
674 rstate
->state
.blend
= (*states
).blend
;
675 r600_blend(rctx
, &rstate
->rstate
[0], &rstate
->state
.blend
);
677 case pipe_stencil_ref_type
:
678 rstate
->state
.stencil_ref
= (*states
).stencil_ref
;
680 case pipe_shader_type
:
681 rstate
->state
.shader
= (*states
).shader
;
682 r
= r600_pipe_shader_create(&rctx
->context
, rstate
, rstate
->state
.shader
.tokens
);
684 r600_context_state_decref(rstate
);
688 case pipe_sampler_type
:
689 rstate
->state
.sampler
= (*states
).sampler
;
690 r600_sampler(rctx
, &rstate
->rstate
[0], &rstate
->state
.sampler
, 0);
693 R600_ERR("invalid type %d\n", rstate
->type
);
700 static void r600_blend(struct r600_context
*rctx
, struct radeon_state
*rstate
, const struct pipe_blend_state
*state
)
702 struct r600_screen
*rscreen
= rctx
->screen
;
705 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_BLEND
, 0, 0);
706 rstate
->states
[R600_BLEND__CB_BLEND_RED
] = fui(rctx
->blend_color
.color
[0]);
707 rstate
->states
[R600_BLEND__CB_BLEND_GREEN
] = fui(rctx
->blend_color
.color
[1]);
708 rstate
->states
[R600_BLEND__CB_BLEND_BLUE
] = fui(rctx
->blend_color
.color
[2]);
709 rstate
->states
[R600_BLEND__CB_BLEND_ALPHA
] = fui(rctx
->blend_color
.color
[3]);
710 rstate
->states
[R600_BLEND__CB_BLEND0_CONTROL
] = 0x00000000;
711 rstate
->states
[R600_BLEND__CB_BLEND1_CONTROL
] = 0x00000000;
712 rstate
->states
[R600_BLEND__CB_BLEND2_CONTROL
] = 0x00000000;
713 rstate
->states
[R600_BLEND__CB_BLEND3_CONTROL
] = 0x00000000;
714 rstate
->states
[R600_BLEND__CB_BLEND4_CONTROL
] = 0x00000000;
715 rstate
->states
[R600_BLEND__CB_BLEND5_CONTROL
] = 0x00000000;
716 rstate
->states
[R600_BLEND__CB_BLEND6_CONTROL
] = 0x00000000;
717 rstate
->states
[R600_BLEND__CB_BLEND7_CONTROL
] = 0x00000000;
718 rstate
->states
[R600_BLEND__CB_BLEND_CONTROL
] = 0x00000000;
720 for (i
= 0; i
< 8; i
++) {
721 unsigned eqRGB
= state
->rt
[i
].rgb_func
;
722 unsigned srcRGB
= state
->rt
[i
].rgb_src_factor
;
723 unsigned dstRGB
= state
->rt
[i
].rgb_dst_factor
;
725 unsigned eqA
= state
->rt
[i
].alpha_func
;
726 unsigned srcA
= state
->rt
[i
].alpha_src_factor
;
727 unsigned dstA
= state
->rt
[i
].alpha_dst_factor
;
730 if (!state
->rt
[i
].blend_enable
)
733 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
734 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
735 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
737 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
738 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
739 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
740 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
741 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
744 rstate
->states
[R600_BLEND__CB_BLEND0_CONTROL
+ i
] = bc
;
746 rstate
->states
[R600_BLEND__CB_BLEND_CONTROL
] = bc
;
749 radeon_state_pm4(rstate
);
752 static void r600_ucp(struct r600_context
*rctx
, struct radeon_state
*rstate
,
753 const struct pipe_clip_state
*state
)
755 struct r600_screen
*rscreen
= rctx
->screen
;
757 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_UCP
, 0, 0);
759 for (int i
= 0; i
< state
->nr
; i
++) {
760 rstate
->states
[i
* 4 + 0] = fui(state
->ucp
[i
][0]);
761 rstate
->states
[i
* 4 + 1] = fui(state
->ucp
[i
][1]);
762 rstate
->states
[i
* 4 + 2] = fui(state
->ucp
[i
][2]);
763 rstate
->states
[i
* 4 + 3] = fui(state
->ucp
[i
][3]);
765 radeon_state_pm4(rstate
);
768 static void r600_cb(struct r600_context
*rctx
, struct radeon_state
*rstate
,
769 const struct pipe_framebuffer_state
*state
, int cb
)
771 struct r600_screen
*rscreen
= rctx
->screen
;
772 struct r600_resource_texture
*rtex
;
773 struct r600_resource
*rbuffer
;
774 unsigned level
= state
->cbufs
[cb
]->level
;
775 unsigned pitch
, slice
;
777 unsigned format
, swap
, ntype
;
778 const struct util_format_description
*desc
;
780 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_CB0
+ cb
, 0, 0);
781 rtex
= (struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
;
782 rbuffer
= &rtex
->resource
;
783 rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
784 rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
785 rstate
->bo
[2] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
786 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
787 rstate
->placement
[2] = RADEON_GEM_DOMAIN_GTT
;
788 rstate
->placement
[4] = RADEON_GEM_DOMAIN_GTT
;
790 pitch
= (rtex
->pitch
[level
] / rtex
->bpt
) / 8 - 1;
791 slice
= (rtex
->pitch
[level
] / rtex
->bpt
) * state
->cbufs
[cb
]->height
/ 64 - 1;
794 desc
= util_format_description(rtex
->resource
.base
.b
.format
);
795 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
796 ntype
= V_0280A0_NUMBER_SRGB
;
798 format
= r600_translate_colorformat(rtex
->resource
.base
.b
.format
);
799 swap
= r600_translate_colorswap(rtex
->resource
.base
.b
.format
);
801 color_info
= S_0280A0_FORMAT(format
) |
802 S_0280A0_COMP_SWAP(swap
) |
803 S_0280A0_BLEND_CLAMP(1) |
804 S_0280A0_SOURCE_FORMAT(1) |
805 S_0280A0_NUMBER_TYPE(ntype
);
807 rstate
->states
[R600_CB0__CB_COLOR0_BASE
] = state
->cbufs
[cb
]->offset
>> 8;
808 rstate
->states
[R600_CB0__CB_COLOR0_INFO
] = color_info
;
809 rstate
->states
[R600_CB0__CB_COLOR0_SIZE
] = S_028060_PITCH_TILE_MAX(pitch
) |
810 S_028060_SLICE_TILE_MAX(slice
);
811 rstate
->states
[R600_CB0__CB_COLOR0_VIEW
] = 0x00000000;
812 rstate
->states
[R600_CB0__CB_COLOR0_FRAG
] = 0x00000000;
813 rstate
->states
[R600_CB0__CB_COLOR0_TILE
] = 0x00000000;
814 rstate
->states
[R600_CB0__CB_COLOR0_MASK
] = 0x00000000;
815 radeon_state_pm4(rstate
);
818 static void r600_db(struct r600_context
*rctx
, struct radeon_state
*rstate
,
819 const struct pipe_framebuffer_state
*state
)
821 struct r600_screen
*rscreen
= rctx
->screen
;
822 struct r600_resource_texture
*rtex
;
823 struct r600_resource
*rbuffer
;
825 unsigned pitch
, slice
, format
;
827 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_DB
, 0, 0);
828 if (state
->zsbuf
== NULL
)
831 rtex
= (struct r600_resource_texture
*)state
->zsbuf
->texture
;
833 rtex
->array_mode
= 2;
836 rbuffer
= &rtex
->resource
;
838 rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
840 rstate
->placement
[0] = RADEON_GEM_DOMAIN_VRAM
;
841 level
= state
->zsbuf
->level
;
842 pitch
= (rtex
->pitch
[level
] / rtex
->bpt
) / 8 - 1;
843 slice
= (rtex
->pitch
[level
] / rtex
->bpt
) * state
->zsbuf
->height
/ 64 - 1;
844 format
= r600_translate_dbformat(state
->zsbuf
->texture
->format
);
845 rstate
->states
[R600_DB__DB_DEPTH_BASE
] = state
->zsbuf
->offset
>> 8;
846 rstate
->states
[R600_DB__DB_DEPTH_INFO
] = S_028010_ARRAY_MODE(rtex
->array_mode
) |
847 S_028010_FORMAT(format
);
848 rstate
->states
[R600_DB__DB_DEPTH_VIEW
] = 0x00000000;
849 rstate
->states
[R600_DB__DB_PREFETCH_LIMIT
] = (state
->zsbuf
->height
/ 8) -1;
850 rstate
->states
[R600_DB__DB_DEPTH_SIZE
] = S_028000_PITCH_TILE_MAX(pitch
) |
851 S_028000_SLICE_TILE_MAX(slice
);
852 radeon_state_pm4(rstate
);
855 static void r600_rasterizer(struct r600_context
*rctx
, struct radeon_state
*rstate
)
857 const struct pipe_rasterizer_state
*state
= &rctx
->rasterizer
->state
.rasterizer
;
858 const struct pipe_framebuffer_state
*fb
= &rctx
->framebuffer
->state
.framebuffer
;
859 const struct pipe_clip_state
*clip
= NULL
;
860 struct r600_screen
*rscreen
= rctx
->screen
;
861 float offset_units
= 0, offset_scale
= 0;
863 unsigned offset_db_fmt_cntl
= 0;
865 unsigned prov_vtx
= 1;
868 clip
= &rctx
->clip
->state
.clip
;
870 offset_units
= state
->offset_units
;
871 offset_scale
= state
->offset_scale
* 12.0f
;
872 switch (fb
->zsbuf
->texture
->format
) {
873 case PIPE_FORMAT_Z24X8_UNORM
:
874 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
876 offset_units
*= 2.0f
;
878 case PIPE_FORMAT_Z32_FLOAT
:
880 offset_units
*= 1.0f
;
881 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
883 case PIPE_FORMAT_Z16_UNORM
:
885 offset_units
*= 4.0f
;
888 R600_ERR("unsupported %d\n", fb
->zsbuf
->texture
->format
);
892 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
894 if (state
->flatshade_first
)
897 rctx
->flat_shade
= state
->flatshade
;
898 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_RASTERIZER
, 0, 0);
899 rstate
->states
[R600_RASTERIZER__SPI_INTERP_CONTROL_0
] = 0x00000001;
900 if (state
->sprite_coord_enable
) {
901 rstate
->states
[R600_RASTERIZER__SPI_INTERP_CONTROL_0
] |=
902 S_0286D4_PNT_SPRITE_ENA(1) |
903 S_0286D4_PNT_SPRITE_OVRD_X(2) |
904 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
905 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
906 S_0286D4_PNT_SPRITE_OVRD_W(1);
907 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
908 rstate
->states
[R600_RASTERIZER__SPI_INTERP_CONTROL_0
] |=
909 S_0286D4_PNT_SPRITE_TOP_1(1);
912 rstate
->states
[R600_RASTERIZER__PA_CL_CLIP_CNTL
] = 0;
914 rstate
->states
[R600_RASTERIZER__PA_CL_CLIP_CNTL
] = S_028810_PS_UCP_MODE(3) | ((1 << clip
->nr
) - 1);
915 rstate
->states
[R600_RASTERIZER__PA_CL_CLIP_CNTL
] |= S_028810_ZCLIP_NEAR_DISABLE(clip
->depth_clamp
);
916 rstate
->states
[R600_RASTERIZER__PA_CL_CLIP_CNTL
] |= S_028810_ZCLIP_FAR_DISABLE(clip
->depth_clamp
);
918 rstate
->states
[R600_RASTERIZER__PA_SU_SC_MODE_CNTL
] =
919 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
920 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
921 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
922 S_028814_FACE(!state
->front_ccw
) |
923 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
924 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
925 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
);
926 rstate
->states
[R600_RASTERIZER__PA_CL_VS_OUT_CNTL
] =
927 S_02881C_USE_VTX_POINT_SIZE(state
->point_size_per_vertex
) |
928 S_02881C_VS_OUT_MISC_VEC_ENA(state
->point_size_per_vertex
);
929 rstate
->states
[R600_RASTERIZER__PA_CL_NANINF_CNTL
] = 0x00000000;
930 /* point size 12.4 fixed point */
931 tmp
= (unsigned)(state
->point_size
* 8.0);
932 rstate
->states
[R600_RASTERIZER__PA_SU_POINT_SIZE
] = S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
);
933 rstate
->states
[R600_RASTERIZER__PA_SU_POINT_MINMAX
] = 0x80000000;
934 rstate
->states
[R600_RASTERIZER__PA_SU_LINE_CNTL
] = 0x00000008;
935 rstate
->states
[R600_RASTERIZER__PA_SC_LINE_STIPPLE
] = 0x00000005;
936 rstate
->states
[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL
] = 0x00000000;
937 rstate
->states
[R600_RASTERIZER__PA_SC_LINE_CNTL
] = 0x00000400;
938 rstate
->states
[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ
] = 0x3F800000;
939 rstate
->states
[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ
] = 0x3F800000;
940 rstate
->states
[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ
] = 0x3F800000;
941 rstate
->states
[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ
] = 0x3F800000;
942 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL
] = offset_db_fmt_cntl
;
943 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP
] = 0x00000000;
944 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE
] = fui(offset_scale
);
945 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET
] = fui(offset_units
);
946 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE
] = fui(offset_scale
);
947 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET
] = fui(offset_units
);
948 radeon_state_pm4(rstate
);
951 static void r600_scissor(struct r600_context
*rctx
, struct radeon_state
*rstate
)
953 const struct pipe_scissor_state
*state
= &rctx
->scissor
->state
.scissor
;
954 const struct pipe_framebuffer_state
*fb
= &rctx
->framebuffer
->state
.framebuffer
;
955 struct r600_screen
*rscreen
= rctx
->screen
;
956 unsigned minx
, maxx
, miny
, maxy
;
962 maxx
= fb
->cbufs
[0]->width
;
963 maxy
= fb
->cbufs
[0]->height
;
970 tl
= S_028240_TL_X(minx
) | S_028240_TL_Y(miny
) | S_028240_WINDOW_OFFSET_DISABLE(1);
971 br
= S_028244_BR_X(maxx
) | S_028244_BR_Y(maxy
);
972 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_SCISSOR
, 0, 0);
973 rstate
->states
[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL
] = tl
;
974 rstate
->states
[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR
] = br
;
975 rstate
->states
[R600_SCISSOR__PA_SC_WINDOW_OFFSET
] = 0x00000000;
976 rstate
->states
[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL
] = tl
;
977 rstate
->states
[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR
] = br
;
978 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_RULE
] = 0x0000FFFF;
979 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_0_TL
] = tl
;
980 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_0_BR
] = br
;
981 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_1_TL
] = tl
;
982 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_1_BR
] = br
;
983 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_2_TL
] = tl
;
984 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_2_BR
] = br
;
985 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_3_TL
] = tl
;
986 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_3_BR
] = br
;
987 rstate
->states
[R600_SCISSOR__PA_SC_EDGERULE
] = 0xAAAAAAAA;
988 rstate
->states
[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL
] = tl
;
989 rstate
->states
[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR
] = br
;
990 rstate
->states
[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL
] = tl
;
991 rstate
->states
[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR
] = br
;
992 radeon_state_pm4(rstate
);
995 static void r600_viewport(struct r600_context
*rctx
, struct radeon_state
*rstate
, const struct pipe_viewport_state
*state
)
997 struct r600_screen
*rscreen
= rctx
->screen
;
999 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_VIEWPORT
, 0, 0);
1000 rstate
->states
[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0
] = 0x00000000;
1001 rstate
->states
[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0
] = 0x3F800000;
1002 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0
] = fui(state
->scale
[0]);
1003 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0
] = fui(state
->scale
[1]);
1004 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0
] = fui(state
->scale
[2]);
1005 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0
] = fui(state
->translate
[0]);
1006 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0
] = fui(state
->translate
[1]);
1007 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0
] = fui(state
->translate
[2]);
1008 rstate
->states
[R600_VIEWPORT__PA_CL_VTE_CNTL
] = 0x0000043F;
1009 radeon_state_pm4(rstate
);
1012 static void r600_dsa(struct r600_context
*rctx
, struct radeon_state
*rstate
)
1014 const struct pipe_depth_stencil_alpha_state
*state
= &rctx
->dsa
->state
.dsa
;
1015 const struct pipe_stencil_ref
*stencil_ref
= &rctx
->stencil_ref
->state
.stencil_ref
;
1016 struct r600_screen
*rscreen
= rctx
->screen
;
1017 unsigned db_depth_control
, alpha_test_control
, alpha_ref
, db_shader_control
;
1018 unsigned stencil_ref_mask
, stencil_ref_mask_bf
, db_render_override
, db_render_control
;
1019 struct r600_shader
*rshader
;
1020 struct r600_query
*rquery
;
1021 boolean query_running
;
1024 if (rctx
->ps_shader
== NULL
) {
1027 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_DSA
, 0, 0);
1029 db_shader_control
= 0x210;
1030 rshader
= &rctx
->ps_shader
->shader
;
1031 if (rshader
->uses_kill
)
1032 db_shader_control
|= (1 << 6);
1033 for (i
= 0; i
< rshader
->noutput
; i
++) {
1034 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
1035 db_shader_control
|= 1;
1037 stencil_ref_mask
= 0;
1038 stencil_ref_mask_bf
= 0;
1039 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1040 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1041 S_028800_ZFUNC(state
->depth
.func
);
1042 /* set stencil enable */
1044 if (state
->stencil
[0].enabled
) {
1045 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1046 db_depth_control
|= S_028800_STENCILFUNC(r600_translate_ds_func(state
->stencil
[0].func
));
1047 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
1048 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
1049 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
1051 stencil_ref_mask
= S_028430_STENCILMASK(state
->stencil
[0].valuemask
) |
1052 S_028430_STENCILWRITEMASK(state
->stencil
[0].writemask
);
1053 stencil_ref_mask
|= S_028430_STENCILREF(stencil_ref
->ref_value
[0]);
1054 if (state
->stencil
[1].enabled
) {
1055 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1056 db_depth_control
|= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state
->stencil
[1].func
));
1057 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
1058 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
1059 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
1060 stencil_ref_mask_bf
= S_028434_STENCILMASK_BF(state
->stencil
[1].valuemask
) |
1061 S_028434_STENCILWRITEMASK_BF(state
->stencil
[1].writemask
);
1062 stencil_ref_mask_bf
|= S_028430_STENCILREF(stencil_ref
->ref_value
[1]);
1066 alpha_test_control
= 0;
1068 if (state
->alpha
.enabled
) {
1069 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
1070 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
1071 alpha_ref
= fui(state
->alpha
.ref_value
);
1074 db_render_control
= S_028D0C_STENCIL_COMPRESS_DISABLE(1) |
1075 S_028D0C_DEPTH_COMPRESS_DISABLE(1);
1076 db_render_override
= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
) |
1077 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE
) |
1078 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE
);
1080 query_running
= false;
1082 LIST_FOR_EACH_ENTRY(rquery
, &rctx
->query_list
, list
) {
1083 if (rquery
->state
& R600_QUERY_STATE_STARTED
) {
1084 query_running
= true;
1088 if (query_running
) {
1089 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
1090 if (rscreen
->chip_class
== R700
)
1091 db_render_control
|= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1094 rstate
->states
[R600_DSA__DB_STENCIL_CLEAR
] = 0x00000000;
1095 rstate
->states
[R600_DSA__DB_DEPTH_CLEAR
] = 0x3F800000;
1096 rstate
->states
[R600_DSA__SX_ALPHA_TEST_CONTROL
] = alpha_test_control
;
1097 rstate
->states
[R600_DSA__DB_STENCILREFMASK
] = stencil_ref_mask
;
1098 rstate
->states
[R600_DSA__DB_STENCILREFMASK_BF
] = stencil_ref_mask_bf
;
1099 rstate
->states
[R600_DSA__SX_ALPHA_REF
] = alpha_ref
;
1100 rstate
->states
[R600_DSA__SPI_FOG_FUNC_SCALE
] = 0x00000000;
1101 rstate
->states
[R600_DSA__SPI_FOG_FUNC_BIAS
] = 0x00000000;
1102 rstate
->states
[R600_DSA__SPI_FOG_CNTL
] = 0x00000000;
1103 rstate
->states
[R600_DSA__DB_DEPTH_CONTROL
] = db_depth_control
;
1104 rstate
->states
[R600_DSA__DB_SHADER_CONTROL
] = db_shader_control
;
1105 rstate
->states
[R600_DSA__DB_RENDER_CONTROL
] = db_render_control
;
1106 rstate
->states
[R600_DSA__DB_RENDER_OVERRIDE
] = db_render_override
;
1108 rstate
->states
[R600_DSA__DB_SRESULTS_COMPARE_STATE1
] = 0x00000000;
1109 rstate
->states
[R600_DSA__DB_PRELOAD_CONTROL
] = 0x00000000;
1110 rstate
->states
[R600_DSA__DB_ALPHA_TO_MASK
] = 0x0000AA00;
1111 radeon_state_pm4(rstate
);
1115 static INLINE u32
S_FIXED(float value
, u32 frac_bits
)
1117 return value
* (1 << frac_bits
);
1120 static void r600_sampler(struct r600_context
*rctx
, struct radeon_state
*rstate
,
1121 const struct pipe_sampler_state
*state
, unsigned id
)
1123 struct r600_screen
*rscreen
= rctx
->screen
;
1125 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_SAMPLER
, id
, R600_SHADER_PS
);
1126 rstate
->states
[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0
] =
1127 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
1128 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
1129 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
1130 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
)) |
1131 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
)) |
1132 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
1133 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
));
1134 /* FIXME LOD it depends on texture base level ... */
1135 rstate
->states
[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0
] =
1136 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
1137 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
1138 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6));
1139 rstate
->states
[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0
] = S_03C008_TYPE(1);
1140 radeon_state_pm4(rstate
);
1145 static void r600_resource(struct pipe_context
*ctx
, struct radeon_state
*rstate
,
1146 const struct pipe_sampler_view
*view
, unsigned id
)
1148 struct r600_context
*rctx
= r600_context(ctx
);
1149 struct r600_screen
*rscreen
= rctx
->screen
;
1150 const struct util_format_description
*desc
;
1151 struct r600_resource_texture
*tmp
;
1152 struct r600_resource
*rbuffer
;
1154 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
1155 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
1159 swizzle
[0] = view
->swizzle_r
;
1160 swizzle
[1] = view
->swizzle_g
;
1161 swizzle
[2] = view
->swizzle_b
;
1162 swizzle
[3] = view
->swizzle_a
;
1163 format
= r600_translate_texformat(view
->texture
->format
,
1165 &word4
, &yuv_format
);
1169 desc
= util_format_description(view
->texture
->format
);
1171 R600_ERR("unknow format %d\n", view
->texture
->format
);
1174 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_RESOURCE
, id
, R600_SHADER_PS
);
1175 tmp
= (struct r600_resource_texture
*)view
->texture
;
1176 rbuffer
= &tmp
->resource
;
1178 r
= r600_texture_from_depth(ctx
, tmp
, view
->first_level
);
1182 rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, tmp
->uncompressed
);
1183 rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, tmp
->uncompressed
);
1185 rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
1186 rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
1189 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
1190 rstate
->placement
[1] = RADEON_GEM_DOMAIN_GTT
;
1191 rstate
->placement
[2] = RADEON_GEM_DOMAIN_GTT
;
1192 rstate
->placement
[3] = RADEON_GEM_DOMAIN_GTT
;
1194 pitch
= (tmp
->pitch
[0] / tmp
->bpt
);
1195 pitch
= (pitch
+ 0x7) & ~0x7;
1197 /* FIXME properly handle first level != 0 */
1198 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD0
] =
1199 S_038000_DIM(r600_tex_dim(view
->texture
->target
)) |
1200 S_038000_TILE_MODE(array_mode
) |
1201 S_038000_TILE_TYPE(tile_type
) |
1202 S_038000_PITCH((pitch
/ 8) - 1) |
1203 S_038000_TEX_WIDTH(view
->texture
->width0
- 1);
1204 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD1
] =
1205 S_038004_TEX_HEIGHT(view
->texture
->height0
- 1) |
1206 S_038004_TEX_DEPTH(view
->texture
->depth0
- 1) |
1207 S_038004_DATA_FORMAT(format
);
1208 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD2
] = tmp
->offset
[0] >> 8;
1209 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD3
] = tmp
->offset
[1] >> 8;
1210 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD4
] =
1212 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM
) |
1213 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO
) |
1214 S_038010_REQUEST_SIZE(1) |
1215 S_038010_BASE_LEVEL(view
->first_level
);
1216 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD5
] =
1217 S_038014_LAST_LEVEL(view
->last_level
) |
1218 S_038014_BASE_ARRAY(0) |
1219 S_038014_LAST_ARRAY(0);
1220 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD6
] =
1221 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
);
1222 radeon_state_pm4(rstate
);
1225 static void r600_cb_cntl(struct r600_context
*rctx
, struct radeon_state
*rstate
)
1227 struct r600_screen
*rscreen
= rctx
->screen
;
1228 const struct pipe_blend_state
*pbs
= &rctx
->blend
->state
.blend
;
1229 int nr_cbufs
= rctx
->framebuffer
->state
.framebuffer
.nr_cbufs
;
1230 uint32_t color_control
, target_mask
, shader_mask
;
1235 color_control
= S_028808_PER_MRT_BLEND(1);
1237 for (i
= 0; i
< nr_cbufs
; i
++) {
1238 shader_mask
|= 0xf << (i
* 4);
1241 if (pbs
->logicop_enable
) {
1242 color_control
|= (pbs
->logicop_func
<< 16) | (pbs
->logicop_func
<< 20);
1244 color_control
|= (0xcc << 16);
1247 if (pbs
->independent_blend_enable
) {
1248 for (i
= 0; i
< nr_cbufs
; i
++) {
1249 if (pbs
->rt
[i
].blend_enable
) {
1250 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
1252 target_mask
|= (pbs
->rt
[i
].colormask
<< (4 * i
));
1255 for (i
= 0; i
< nr_cbufs
; i
++) {
1256 if (pbs
->rt
[0].blend_enable
) {
1257 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
1259 target_mask
|= (pbs
->rt
[0].colormask
<< (4 * i
));
1262 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_CB_CNTL
, 0, 0);
1263 rstate
->states
[R600_CB_CNTL__CB_SHADER_MASK
] = shader_mask
;
1264 rstate
->states
[R600_CB_CNTL__CB_TARGET_MASK
] = target_mask
;
1265 rstate
->states
[R600_CB_CNTL__CB_COLOR_CONTROL
] = color_control
;
1266 rstate
->states
[R600_CB_CNTL__PA_SC_AA_CONFIG
] = 0x00000000;
1267 rstate
->states
[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX
] = 0x00000000;
1268 rstate
->states
[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX
] = 0x00000000;
1269 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_CONTROL
] = 0x01000000;
1270 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_SRC
] = 0x00000000;
1271 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_DST
] = 0x000000FF;
1272 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_MSK
] = 0xFFFFFFFF;
1273 rstate
->states
[R600_CB_CNTL__PA_SC_AA_MASK
] = 0xFFFFFFFF;
1274 radeon_state_pm4(rstate
);
1277 int r600_context_hw_states(struct pipe_context
*ctx
)
1279 struct r600_context
*rctx
= r600_context(ctx
);
1282 /* build new states */
1283 r600_rasterizer(rctx
, &rctx
->hw_states
.rasterizer
);
1284 r600_scissor(rctx
, &rctx
->hw_states
.scissor
);
1285 r600_dsa(rctx
, &rctx
->hw_states
.dsa
);
1286 r600_cb_cntl(rctx
, &rctx
->hw_states
.cb_cntl
);
1289 radeon_draw_bind(&rctx
->draw
, &rctx
->hw_states
.rasterizer
);
1290 radeon_draw_bind(&rctx
->draw
, &rctx
->hw_states
.scissor
);
1291 radeon_draw_bind(&rctx
->draw
, &rctx
->hw_states
.dsa
);
1292 radeon_draw_bind(&rctx
->draw
, &rctx
->hw_states
.cb_cntl
);
1294 radeon_draw_bind(&rctx
->draw
, &rctx
->config
);
1296 if (rctx
->viewport
) {
1297 radeon_draw_bind(&rctx
->draw
, &rctx
->viewport
->rstate
[0]);
1300 radeon_draw_bind(&rctx
->draw
, &rctx
->blend
->rstate
[0]);
1303 radeon_draw_bind(&rctx
->draw
, &rctx
->clip
->rstate
[0]);
1305 for (i
= 0; i
< rctx
->framebuffer
->state
.framebuffer
.nr_cbufs
; i
++) {
1306 radeon_draw_bind(&rctx
->draw
, &rctx
->framebuffer
->rstate
[i
+1]);
1308 if (rctx
->framebuffer
->state
.framebuffer
.zsbuf
) {
1309 radeon_draw_bind(&rctx
->draw
, &rctx
->framebuffer
->rstate
[0]);
1311 for (i
= 0; i
< rctx
->ps_nsampler
; i
++) {
1312 if (rctx
->ps_sampler
[i
]) {
1313 radeon_draw_bind(&rctx
->draw
, rctx
->ps_sampler
[i
]);
1316 for (i
= 0; i
< rctx
->ps_nsampler_view
; i
++) {
1317 if (rctx
->ps_sampler_view
[i
]) {
1318 radeon_draw_bind(&rctx
->draw
, rctx
->ps_sampler_view
[i
]);