projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: don't set per-MRT blend bits on R600
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_framebuffer.h>
40 #include "util/u_transfer.h"
41 #include <pipebuffer/pb_buffer.h>
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_state_inlines.h"
48
49 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
50 {
51 struct r600_pipe_state state;
52
53 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
54 state.nregs = 0;
55 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
56 float offset_units = rctx->rasterizer->offset_units;
57 unsigned offset_db_fmt_cntl = 0, depth;
58
59 switch (rctx->framebuffer.zsbuf->texture->format) {
60 case PIPE_FORMAT_Z24X8_UNORM:
61 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
62 depth = -24;
63 offset_units *= 2.0f;
64 break;
65 case PIPE_FORMAT_Z32_FLOAT:
66 depth = -23;
67 offset_units *= 1.0f;
68 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
69 break;
70 case PIPE_FORMAT_Z16_UNORM:
71 depth = -16;
72 offset_units *= 4.0f;
73 break;
74 default:
75 return;
76 }
77 /* FIXME some of those reg can be computed with cso */
78 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
79 r600_pipe_state_add_reg(&state,
80 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
81 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
82 r600_pipe_state_add_reg(&state,
83 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
84 fui(offset_units), 0xFFFFFFFF, NULL);
85 r600_pipe_state_add_reg(&state,
86 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
87 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
88 r600_pipe_state_add_reg(&state,
89 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
90 fui(offset_units), 0xFFFFFFFF, NULL);
91 r600_pipe_state_add_reg(&state,
92 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
93 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
94 r600_context_pipe_state_set(&rctx->ctx, &state);
95 }
96 }
97
98 static void r600_set_blend_color(struct pipe_context *ctx,
99 const struct pipe_blend_color *state)
100 {
101 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
102 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
103
104 if (rstate == NULL)
105 return;
106
107 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
108 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
109 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
110 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
111 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
112 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
113 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
114 r600_context_pipe_state_set(&rctx->ctx, rstate);
115 }
116
117 static void *r600_create_blend_state(struct pipe_context *ctx,
118 const struct pipe_blend_state *state)
119 {
120 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
121 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
122 struct r600_pipe_state *rstate;
123 u32 color_control = 0, target_mask;
124
125 if (blend == NULL) {
126 return NULL;
127 }
128 rstate = &blend->rstate;
129
130 rstate->id = R600_PIPE_STATE_BLEND;
131
132 target_mask = 0;
133
134 /* R600 does not support per-MRT blends */
135 if (rctx->family > CHIP_R600)
136 color_control |= S_028808_PER_MRT_BLEND(1);
137 if (state->logicop_enable) {
138 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
139 } else {
140 color_control |= (0xcc << 16);
141 }
142 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
143 if (state->independent_blend_enable) {
144 for (int i = 0; i < 8; i++) {
145 if (state->rt[i].blend_enable) {
146 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
147 }
148 target_mask |= (state->rt[i].colormask << (4 * i));
149 }
150 } else {
151 for (int i = 0; i < 8; i++) {
152 if (state->rt[0].blend_enable) {
153 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
154 }
155 target_mask |= (state->rt[0].colormask << (4 * i));
156 }
157 }
158 blend->cb_target_mask = target_mask;
159 /* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */
160 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
161 color_control, 0xFFFFFFFD, NULL);
162
163 for (int i = 0; i < 8; i++) {
164 unsigned eqRGB = state->rt[i].rgb_func;
165 unsigned srcRGB = state->rt[i].rgb_src_factor;
166 unsigned dstRGB = state->rt[i].rgb_dst_factor;
167
168 unsigned eqA = state->rt[i].alpha_func;
169 unsigned srcA = state->rt[i].alpha_src_factor;
170 unsigned dstA = state->rt[i].alpha_dst_factor;
171 uint32_t bc = 0;
172
173 if (!state->rt[i].blend_enable)
174 continue;
175
176 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
177 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
178 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
179
180 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
181 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
182 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
183 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
184 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
185 }
186
187 /* R600 does not support per-MRT blends */
188 if (rctx->family > CHIP_R600)
189 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
190 if (i == 0)
191 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
192 }
193 return rstate;
194 }
195
196 static void *r600_create_dsa_state(struct pipe_context *ctx,
197 const struct pipe_depth_stencil_alpha_state *state)
198 {
199 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
200 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
201 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
202
203 if (rstate == NULL) {
204 return NULL;
205 }
206
207 rstate->id = R600_PIPE_STATE_DSA;
208 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
209 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
210 stencil_ref_mask = 0;
211 stencil_ref_mask_bf = 0;
212 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
213 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
214 S_028800_ZFUNC(state->depth.func);
215
216 /* stencil */
217 if (state->stencil[0].enabled) {
218 db_depth_control |= S_028800_STENCIL_ENABLE(1);
219 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
220 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
221 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
222 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
223
224
225 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
226 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
227 if (state->stencil[1].enabled) {
228 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
229 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
230 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
231 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
232 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
233 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
234 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
235 }
236 }
237
238 /* alpha */
239 alpha_test_control = 0;
240 alpha_ref = 0;
241 if (state->alpha.enabled) {
242 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
243 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
244 alpha_ref = fui(state->alpha.ref_value);
245 }
246
247 /* misc */
248 db_render_control = 0;
249 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
250 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
251 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
252 /* TODO db_render_override depends on query */
253 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
254 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
255 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
256 r600_pipe_state_add_reg(rstate,
257 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
258 0xFFFFFFFF & C_028430_STENCILREF, NULL);
259 r600_pipe_state_add_reg(rstate,
260 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
261 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
262 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
263 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
264 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
265 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
266 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
267 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
268 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
269 * r600_pipe_shader_ps().*/
270 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL);
271 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
272 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
273 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
274 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
275 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
276
277 return rstate;
278 }
279
280 static void *r600_create_rs_state(struct pipe_context *ctx,
281 const struct pipe_rasterizer_state *state)
282 {
283 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
284 struct r600_pipe_state *rstate;
285 unsigned tmp;
286 unsigned prov_vtx = 1, polygon_dual_mode;
287 unsigned clip_rule;
288
289 if (rs == NULL) {
290 return NULL;
291 }
292
293 rstate = &rs->rstate;
294 rs->flatshade = state->flatshade;
295 rs->sprite_coord_enable = state->sprite_coord_enable;
296
297 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
298 /* offset */
299 rs->offset_units = state->offset_units;
300 rs->offset_scale = state->offset_scale * 12.0f;
301
302 rstate->id = R600_PIPE_STATE_RASTERIZER;
303 if (state->flatshade_first)
304 prov_vtx = 0;
305 tmp = S_0286D4_FLAT_SHADE_ENA(1);
306 if (state->sprite_coord_enable) {
307 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
308 S_0286D4_PNT_SPRITE_OVRD_X(2) |
309 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
310 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
311 S_0286D4_PNT_SPRITE_OVRD_W(1);
312 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
313 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
314 }
315 }
316 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
317
318 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
319 state->fill_back != PIPE_POLYGON_MODE_FILL);
320 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
321 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
322 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
323 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
324 S_028814_FACE(!state->front_ccw) |
325 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
326 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
327 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
328 S_028814_POLY_MODE(polygon_dual_mode) |
329 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
330 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
331 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
332 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
333 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
334 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
335 /* point size 12.4 fixed point */
336 tmp = (unsigned)(state->point_size * 8.0);
337 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
338 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
339
340 tmp = (unsigned)state->line_width * 8;
341 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
342
343 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
344 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
345 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
346
347 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
348 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
349 0xFFFFFFFF, NULL);
350
351 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
352 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
353 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
354 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
355 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
356 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
357
358 return rstate;
359 }
360
361 static void *r600_create_sampler_state(struct pipe_context *ctx,
362 const struct pipe_sampler_state *state)
363 {
364 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
365 union util_color uc;
366 uint32_t coord_trunc = 0;
367
368 if (rstate == NULL) {
369 return NULL;
370 }
371
372 if ((state->mag_img_filter == PIPE_TEX_FILTER_NEAREST) ||
373 (state->min_img_filter == PIPE_TEX_FILTER_NEAREST))
374 coord_trunc = 1;
375
376 rstate->id = R600_PIPE_STATE_SAMPLER;
377 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
378 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
379 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
380 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
381 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
382 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
383 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
384 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
385 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
386 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
387 /* FIXME LOD it depends on texture base level ... */
388 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
389 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
390 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
391 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
392 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
393 S_03C008_MC_COORD_TRUNCATE(coord_trunc) |
394 S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
395 if (uc.ui) {
396 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
397 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
398 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
399 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
400 }
401 return rstate;
402 }
403
404 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
405 struct pipe_resource *texture,
406 const struct pipe_sampler_view *state)
407 {
408 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
409 struct r600_pipe_state *rstate;
410 const struct util_format_description *desc;
411 struct r600_resource_texture *tmp;
412 struct r600_resource *rbuffer;
413 unsigned format;
414 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
415 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
416 struct r600_bo *bo[2];
417 unsigned height, depth;
418
419 if (resource == NULL)
420 return NULL;
421 rstate = &resource->state;
422
423 /* initialize base object */
424 resource->base = *state;
425 resource->base.texture = NULL;
426 pipe_reference(NULL, &texture->reference);
427 resource->base.texture = texture;
428 resource->base.reference.count = 1;
429 resource->base.context = ctx;
430
431 swizzle[0] = state->swizzle_r;
432 swizzle[1] = state->swizzle_g;
433 swizzle[2] = state->swizzle_b;
434 swizzle[3] = state->swizzle_a;
435 format = r600_translate_texformat(ctx->screen, state->format,
436 swizzle,
437 &word4, &yuv_format);
438 if (format == ~0) {
439 format = 0;
440 }
441 desc = util_format_description(state->format);
442 if (desc == NULL) {
443 R600_ERR("unknow format %d\n", state->format);
444 }
445 tmp = (struct r600_resource_texture *)texture;
446 if (tmp->depth && !tmp->is_flushing_texture) {
447 r600_texture_depth_flush(ctx, texture, TRUE);
448 tmp = tmp->flushed_depth_texture;
449 }
450
451 if (tmp->force_int_type) {
452 word4 &= C_038010_NUM_FORMAT_ALL;
453 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
454 }
455 rbuffer = &tmp->resource;
456 bo[0] = rbuffer->bo;
457 bo[1] = rbuffer->bo;
458 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8);
459 array_mode = tmp->array_mode[0];
460 tile_type = tmp->tile_type;
461
462 height = texture->height0;
463 depth = texture->depth0;
464 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
465 height = 1;
466 depth = texture->array_size;
467 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
468 depth = texture->array_size;
469 }
470
471 /* FIXME properly handle first level != 0 */
472 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
473 S_038000_DIM(r600_tex_dim(texture->target)) |
474 S_038000_TILE_MODE(array_mode) |
475 S_038000_TILE_TYPE(tile_type) |
476 S_038000_PITCH((pitch / 8) - 1) |
477 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
478 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
479 S_038004_TEX_HEIGHT(height - 1) |
480 S_038004_TEX_DEPTH(depth - 1) |
481 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
482 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
483 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
484 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
485 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
486 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
487 word4 |
488 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_NO_ZERO) |
489 S_038010_REQUEST_SIZE(1) |
490 S_038010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
491 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
492 S_038014_LAST_LEVEL(state->u.tex.last_level) |
493 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
494 S_038014_LAST_ARRAY(state->u.tex.last_layer), 0xFFFFFFFF, NULL);
495 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
496 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
497
498 return &resource->base;
499 }
500
501 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
502 struct pipe_sampler_view **views)
503 {
504 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
505 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
506
507 for (int i = 0; i < count; i++) {
508 if (resource[i]) {
509 r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
510 i + R600_MAX_CONST_BUFFERS);
511 }
512 }
513 }
514
515 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
516 struct pipe_sampler_view **views)
517 {
518 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
519 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
520 int i;
521
522 for (i = 0; i < count; i++) {
523 if (&rctx->ps_samplers.views[i]->base != views[i]) {
524 if (resource[i])
525 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
526 i + R600_MAX_CONST_BUFFERS);
527 else
528 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
529 i + R600_MAX_CONST_BUFFERS);
530
531 pipe_sampler_view_reference(
532 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
533 views[i]);
534
535 }
536 }
537 for (i = count; i < NUM_TEX_UNITS; i++) {
538 if (rctx->ps_samplers.views[i]) {
539 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
540 i + R600_MAX_CONST_BUFFERS);
541 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
542 }
543 }
544 rctx->ps_samplers.n_views = count;
545 }
546
547 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
548 {
549 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
550 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
551
552 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
553 rctx->ps_samplers.n_samplers = count;
554
555 for (int i = 0; i < count; i++) {
556 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
557 }
558 }
559
560 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
561 {
562 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
563 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
564
565 for (int i = 0; i < count; i++) {
566 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
567 }
568 }
569
570 static void r600_set_clip_state(struct pipe_context *ctx,
571 const struct pipe_clip_state *state)
572 {
573 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
574 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
575
576 if (rstate == NULL)
577 return;
578
579 rctx->clip = *state;
580 rstate->id = R600_PIPE_STATE_CLIP;
581 for (int i = 0; i < state->nr; i++) {
582 r600_pipe_state_add_reg(rstate,
583 R_028E20_PA_CL_UCP0_X + i * 16,
584 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
585 r600_pipe_state_add_reg(rstate,
586 R_028E24_PA_CL_UCP0_Y + i * 16,
587 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
588 r600_pipe_state_add_reg(rstate,
589 R_028E28_PA_CL_UCP0_Z + i * 16,
590 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
591 r600_pipe_state_add_reg(rstate,
592 R_028E2C_PA_CL_UCP0_W + i * 16,
593 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
594 }
595 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
596 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
597 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
598 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
599
600 free(rctx->states[R600_PIPE_STATE_CLIP]);
601 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
602 r600_context_pipe_state_set(&rctx->ctx, rstate);
603 }
604
605 static void r600_set_polygon_stipple(struct pipe_context *ctx,
606 const struct pipe_poly_stipple *state)
607 {
608 }
609
610 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
611 {
612 }
613
614 static void r600_set_scissor_state(struct pipe_context *ctx,
615 const struct pipe_scissor_state *state)
616 {
617 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
618 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
619 u32 tl, br;
620
621 if (rstate == NULL)
622 return;
623
624 rstate->id = R600_PIPE_STATE_SCISSOR;
625 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
626 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
627 r600_pipe_state_add_reg(rstate,
628 R_028210_PA_SC_CLIPRECT_0_TL, tl,
629 0xFFFFFFFF, NULL);
630 r600_pipe_state_add_reg(rstate,
631 R_028214_PA_SC_CLIPRECT_0_BR, br,
632 0xFFFFFFFF, NULL);
633 r600_pipe_state_add_reg(rstate,
634 R_028218_PA_SC_CLIPRECT_1_TL, tl,
635 0xFFFFFFFF, NULL);
636 r600_pipe_state_add_reg(rstate,
637 R_02821C_PA_SC_CLIPRECT_1_BR, br,
638 0xFFFFFFFF, NULL);
639 r600_pipe_state_add_reg(rstate,
640 R_028220_PA_SC_CLIPRECT_2_TL, tl,
641 0xFFFFFFFF, NULL);
642 r600_pipe_state_add_reg(rstate,
643 R_028224_PA_SC_CLIPRECT_2_BR, br,
644 0xFFFFFFFF, NULL);
645 r600_pipe_state_add_reg(rstate,
646 R_028228_PA_SC_CLIPRECT_3_TL, tl,
647 0xFFFFFFFF, NULL);
648 r600_pipe_state_add_reg(rstate,
649 R_02822C_PA_SC_CLIPRECT_3_BR, br,
650 0xFFFFFFFF, NULL);
651
652 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
653 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
654 r600_context_pipe_state_set(&rctx->ctx, rstate);
655 }
656
657 static void r600_set_stencil_ref(struct pipe_context *ctx,
658 const struct pipe_stencil_ref *state)
659 {
660 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
661 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
662 u32 tmp;
663
664 if (rstate == NULL)
665 return;
666
667 rctx->stencil_ref = *state;
668 rstate->id = R600_PIPE_STATE_STENCIL_REF;
669 tmp = S_028430_STENCILREF(state->ref_value[0]);
670 r600_pipe_state_add_reg(rstate,
671 R_028430_DB_STENCILREFMASK, tmp,
672 ~C_028430_STENCILREF, NULL);
673 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
674 r600_pipe_state_add_reg(rstate,
675 R_028434_DB_STENCILREFMASK_BF, tmp,
676 ~C_028434_STENCILREF_BF, NULL);
677
678 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
679 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
680 r600_context_pipe_state_set(&rctx->ctx, rstate);
681 }
682
683 static void r600_set_viewport_state(struct pipe_context *ctx,
684 const struct pipe_viewport_state *state)
685 {
686 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
687 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
688
689 if (rstate == NULL)
690 return;
691
692 rctx->viewport = *state;
693 rstate->id = R600_PIPE_STATE_VIEWPORT;
694 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
695 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
696 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
697 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
698 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
699 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
700 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
701 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
702 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
703
704 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
705 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
706 r600_context_pipe_state_set(&rctx->ctx, rstate);
707 }
708
709 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
710 const struct pipe_framebuffer_state *state, int cb)
711 {
712 struct r600_resource_texture *rtex;
713 struct r600_resource *rbuffer;
714 struct r600_surface *surf;
715 unsigned level = state->cbufs[cb]->u.tex.level;
716 unsigned pitch, slice;
717 unsigned color_info;
718 unsigned format, swap, ntype;
719 unsigned offset;
720 const struct util_format_description *desc;
721 struct r600_bo *bo[3];
722 int i;
723
724 surf = (struct r600_surface *)state->cbufs[cb];
725 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
726
727 if (rtex->depth && !rtex->is_flushing_texture) {
728 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
729 rtex = rtex->flushed_depth_texture;
730 }
731
732 rbuffer = &rtex->resource;
733 bo[0] = rbuffer->bo;
734 bo[1] = rbuffer->bo;
735 bo[2] = rbuffer->bo;
736
737 /* XXX quite sure for dx10+ hw don't need any offset hacks */
738 offset = r600_texture_get_offset(rtex,
739 level, state->cbufs[cb]->u.tex.first_layer);
740 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
741 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
742 ntype = 0;
743 desc = util_format_description(surf->base.format);
744 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
745 ntype = V_0280A0_NUMBER_SRGB;
746
747 for (i = 0; i < 4; i++) {
748 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
749 break;
750 }
751 }
752
753 format = r600_translate_colorformat(surf->base.format);
754 swap = r600_translate_colorswap(surf->base.format);
755
756 /* disable when gallium grows int textures */
757 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
758 ntype = 4;
759
760 color_info = S_0280A0_FORMAT(format) |
761 S_0280A0_COMP_SWAP(swap) |
762 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
763 S_0280A0_BLEND_CLAMP(1) |
764 S_0280A0_NUMBER_TYPE(ntype);
765
766 /* on R600 this can't be set if BLEND_CLAMP isn't set,
767 if BLEND_FLOAT32 is set of > 11 bits in a UNORM or SNORM */
768 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
769 desc->channel[i].size < 12)
770 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
771
772 r600_pipe_state_add_reg(rstate,
773 R_028040_CB_COLOR0_BASE + cb * 4,
774 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
775 r600_pipe_state_add_reg(rstate,
776 R_0280A0_CB_COLOR0_INFO + cb * 4,
777 color_info, 0xFFFFFFFF, bo[0]);
778 r600_pipe_state_add_reg(rstate,
779 R_028060_CB_COLOR0_SIZE + cb * 4,
780 S_028060_PITCH_TILE_MAX(pitch) |
781 S_028060_SLICE_TILE_MAX(slice),
782 0xFFFFFFFF, NULL);
783 r600_pipe_state_add_reg(rstate,
784 R_028080_CB_COLOR0_VIEW + cb * 4,
785 0x00000000, 0xFFFFFFFF, NULL);
786 r600_pipe_state_add_reg(rstate,
787 R_0280E0_CB_COLOR0_FRAG + cb * 4,
788 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
789 r600_pipe_state_add_reg(rstate,
790 R_0280C0_CB_COLOR0_TILE + cb * 4,
791 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
792 r600_pipe_state_add_reg(rstate,
793 R_028100_CB_COLOR0_MASK + cb * 4,
794 0x00000000, 0xFFFFFFFF, NULL);
795 }
796
797 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
798 const struct pipe_framebuffer_state *state)
799 {
800 struct r600_resource_texture *rtex;
801 struct r600_resource *rbuffer;
802 struct r600_surface *surf;
803 unsigned level;
804 unsigned pitch, slice, format;
805 unsigned offset;
806
807 if (state->zsbuf == NULL)
808 return;
809
810 level = state->zsbuf->u.tex.level;
811
812 surf = (struct r600_surface *)state->zsbuf;
813 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
814
815 rbuffer = &rtex->resource;
816
817 /* XXX quite sure for dx10+ hw don't need any offset hacks */
818 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
819 level, state->zsbuf->u.tex.first_layer);
820 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
821 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
822 format = r600_translate_dbformat(state->zsbuf->texture->format);
823
824 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
825 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
826 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
827 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
828 0xFFFFFFFF, NULL);
829 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
830 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
831 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
832 0xFFFFFFFF, rbuffer->bo);
833 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
834 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL);
835 }
836
837 static void r600_set_framebuffer_state(struct pipe_context *ctx,
838 const struct pipe_framebuffer_state *state)
839 {
840 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
841 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
842 u32 shader_mask, tl, br, shader_control, target_mask;
843
844 if (rstate == NULL)
845 return;
846
847 /* unreference old buffer and reference new one */
848 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
849
850 util_copy_framebuffer_state(&rctx->framebuffer, state);
851
852 /* build states */
853 for (int i = 0; i < state->nr_cbufs; i++) {
854 r600_cb(rctx, rstate, state, i);
855 }
856 if (state->zsbuf) {
857 r600_db(rctx, rstate, state);
858 }
859
860 target_mask = 0x00000000;
861 target_mask = 0xFFFFFFFF;
862 shader_mask = 0;
863 shader_control = 0;
864 for (int i = 0; i < state->nr_cbufs; i++) {
865 target_mask ^= 0xf << (i * 4);
866 shader_mask |= 0xf << (i * 4);
867 shader_control |= 1 << i;
868 }
869 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
870 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
871
872 r600_pipe_state_add_reg(rstate,
873 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
874 0xFFFFFFFF, NULL);
875 r600_pipe_state_add_reg(rstate,
876 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
877 0xFFFFFFFF, NULL);
878 r600_pipe_state_add_reg(rstate,
879 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
880 0xFFFFFFFF, NULL);
881 r600_pipe_state_add_reg(rstate,
882 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
883 0xFFFFFFFF, NULL);
884 r600_pipe_state_add_reg(rstate,
885 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
886 0xFFFFFFFF, NULL);
887 r600_pipe_state_add_reg(rstate,
888 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
889 0xFFFFFFFF, NULL);
890 r600_pipe_state_add_reg(rstate,
891 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
892 0xFFFFFFFF, NULL);
893 r600_pipe_state_add_reg(rstate,
894 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
895 0xFFFFFFFF, NULL);
896 r600_pipe_state_add_reg(rstate,
897 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
898 0xFFFFFFFF, NULL);
899 if (rctx->family >= CHIP_RV770) {
900 r600_pipe_state_add_reg(rstate,
901 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
902 0xFFFFFFFF, NULL);
903 }
904
905 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
906 shader_control, 0xFFFFFFFF, NULL);
907 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
908 0x00000000, target_mask, NULL);
909 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
910 shader_mask, 0xFFFFFFFF, NULL);
911 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
912 0x00000000, 0xFFFFFFFF, NULL);
913 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
914 0x00000000, 0xFFFFFFFF, NULL);
915 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
916 0x00000000, 0xFFFFFFFF, NULL);
917 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
918 0x01000000, 0xFFFFFFFF, NULL);
919 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
920 0x00000000, 0xFFFFFFFF, NULL);
921 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
922 0x000000FF, 0xFFFFFFFF, NULL);
923 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
924 0xFFFFFFFF, 0xFFFFFFFF, NULL);
925 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
926 0xFFFFFFFF, 0xFFFFFFFF, NULL);
927
928 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
929 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
930 r600_context_pipe_state_set(&rctx->ctx, rstate);
931
932 if (state->zsbuf) {
933 r600_polygon_offset_update(rctx);
934 }
935 }
936
937 void r600_init_state_functions(struct r600_pipe_context *rctx)
938 {
939 rctx->context.create_blend_state = r600_create_blend_state;
940 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
941 rctx->context.create_fs_state = r600_create_shader_state;
942 rctx->context.create_rasterizer_state = r600_create_rs_state;
943 rctx->context.create_sampler_state = r600_create_sampler_state;
944 rctx->context.create_sampler_view = r600_create_sampler_view;
945 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
946 rctx->context.create_vs_state = r600_create_shader_state;
947 rctx->context.bind_blend_state = r600_bind_blend_state;
948 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
949 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
950 rctx->context.bind_fs_state = r600_bind_ps_shader;
951 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
952 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
953 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
954 rctx->context.bind_vs_state = r600_bind_vs_shader;
955 rctx->context.delete_blend_state = r600_delete_state;
956 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
957 rctx->context.delete_fs_state = r600_delete_ps_shader;
958 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
959 rctx->context.delete_sampler_state = r600_delete_state;
960 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
961 rctx->context.delete_vs_state = r600_delete_vs_shader;
962 rctx->context.set_blend_color = r600_set_blend_color;
963 rctx->context.set_clip_state = r600_set_clip_state;
964 rctx->context.set_constant_buffer = r600_set_constant_buffer;
965 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
966 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
967 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
968 rctx->context.set_sample_mask = r600_set_sample_mask;
969 rctx->context.set_scissor_state = r600_set_scissor_state;
970 rctx->context.set_stencil_ref = r600_set_stencil_ref;
971 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
972 rctx->context.set_index_buffer = r600_set_index_buffer;
973 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
974 rctx->context.set_viewport_state = r600_set_viewport_state;
975 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
976 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
977 }
978
979 void r600_init_config(struct r600_pipe_context *rctx)
980 {
981 int ps_prio;
982 int vs_prio;
983 int gs_prio;
984 int es_prio;
985 int num_ps_gprs;
986 int num_vs_gprs;
987 int num_gs_gprs;
988 int num_es_gprs;
989 int num_temp_gprs;
990 int num_ps_threads;
991 int num_vs_threads;
992 int num_gs_threads;
993 int num_es_threads;
994 int num_ps_stack_entries;
995 int num_vs_stack_entries;
996 int num_gs_stack_entries;
997 int num_es_stack_entries;
998 enum radeon_family family;
999 struct r600_pipe_state *rstate = &rctx->config;
1000 u32 tmp;
1001
1002 family = r600_get_family(rctx->radeon);
1003 ps_prio = 0;
1004 vs_prio = 1;
1005 gs_prio = 2;
1006 es_prio = 3;
1007 switch (family) {
1008 case CHIP_R600:
1009 num_ps_gprs = 192;
1010 num_vs_gprs = 56;
1011 num_temp_gprs = 4;
1012 num_gs_gprs = 0;
1013 num_es_gprs = 0;
1014 num_ps_threads = 136;
1015 num_vs_threads = 48;
1016 num_gs_threads = 4;
1017 num_es_threads = 4;
1018 num_ps_stack_entries = 128;
1019 num_vs_stack_entries = 128;
1020 num_gs_stack_entries = 0;
1021 num_es_stack_entries = 0;
1022 break;
1023 case CHIP_RV630:
1024 case CHIP_RV635:
1025 num_ps_gprs = 84;
1026 num_vs_gprs = 36;
1027 num_temp_gprs = 4;
1028 num_gs_gprs = 0;
1029 num_es_gprs = 0;
1030 num_ps_threads = 144;
1031 num_vs_threads = 40;
1032 num_gs_threads = 4;
1033 num_es_threads = 4;
1034 num_ps_stack_entries = 40;
1035 num_vs_stack_entries = 40;
1036 num_gs_stack_entries = 32;
1037 num_es_stack_entries = 16;
1038 break;
1039 case CHIP_RV610:
1040 case CHIP_RV620:
1041 case CHIP_RS780:
1042 case CHIP_RS880:
1043 default:
1044 num_ps_gprs = 84;
1045 num_vs_gprs = 36;
1046 num_temp_gprs = 4;
1047 num_gs_gprs = 0;
1048 num_es_gprs = 0;
1049 num_ps_threads = 136;
1050 num_vs_threads = 48;
1051 num_gs_threads = 4;
1052 num_es_threads = 4;
1053 num_ps_stack_entries = 40;
1054 num_vs_stack_entries = 40;
1055 num_gs_stack_entries = 32;
1056 num_es_stack_entries = 16;
1057 break;
1058 case CHIP_RV670:
1059 num_ps_gprs = 144;
1060 num_vs_gprs = 40;
1061 num_temp_gprs = 4;
1062 num_gs_gprs = 0;
1063 num_es_gprs = 0;
1064 num_ps_threads = 136;
1065 num_vs_threads = 48;
1066 num_gs_threads = 4;
1067 num_es_threads = 4;
1068 num_ps_stack_entries = 40;
1069 num_vs_stack_entries = 40;
1070 num_gs_stack_entries = 32;
1071 num_es_stack_entries = 16;
1072 break;
1073 case CHIP_RV770:
1074 num_ps_gprs = 192;
1075 num_vs_gprs = 56;
1076 num_temp_gprs = 4;
1077 num_gs_gprs = 0;
1078 num_es_gprs = 0;
1079 num_ps_threads = 188;
1080 num_vs_threads = 60;
1081 num_gs_threads = 0;
1082 num_es_threads = 0;
1083 num_ps_stack_entries = 256;
1084 num_vs_stack_entries = 256;
1085 num_gs_stack_entries = 0;
1086 num_es_stack_entries = 0;
1087 break;
1088 case CHIP_RV730:
1089 case CHIP_RV740:
1090 num_ps_gprs = 84;
1091 num_vs_gprs = 36;
1092 num_temp_gprs = 4;
1093 num_gs_gprs = 0;
1094 num_es_gprs = 0;
1095 num_ps_threads = 188;
1096 num_vs_threads = 60;
1097 num_gs_threads = 0;
1098 num_es_threads = 0;
1099 num_ps_stack_entries = 128;
1100 num_vs_stack_entries = 128;
1101 num_gs_stack_entries = 0;
1102 num_es_stack_entries = 0;
1103 break;
1104 case CHIP_RV710:
1105 num_ps_gprs = 192;
1106 num_vs_gprs = 56;
1107 num_temp_gprs = 4;
1108 num_gs_gprs = 0;
1109 num_es_gprs = 0;
1110 num_ps_threads = 144;
1111 num_vs_threads = 48;
1112 num_gs_threads = 0;
1113 num_es_threads = 0;
1114 num_ps_stack_entries = 128;
1115 num_vs_stack_entries = 128;
1116 num_gs_stack_entries = 0;
1117 num_es_stack_entries = 0;
1118 break;
1119 }
1120
1121 rstate->id = R600_PIPE_STATE_CONFIG;
1122
1123 /* SQ_CONFIG */
1124 tmp = 0;
1125 switch (family) {
1126 case CHIP_RV610:
1127 case CHIP_RV620:
1128 case CHIP_RS780:
1129 case CHIP_RS880:
1130 case CHIP_RV710:
1131 break;
1132 default:
1133 tmp |= S_008C00_VC_ENABLE(1);
1134 break;
1135 }
1136 tmp |= S_008C00_DX9_CONSTS(0);
1137 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1138 tmp |= S_008C00_PS_PRIO(ps_prio);
1139 tmp |= S_008C00_VS_PRIO(vs_prio);
1140 tmp |= S_008C00_GS_PRIO(gs_prio);
1141 tmp |= S_008C00_ES_PRIO(es_prio);
1142 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1143
1144 /* SQ_GPR_RESOURCE_MGMT_1 */
1145 tmp = 0;
1146 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1147 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1148 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1149 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1150
1151 /* SQ_GPR_RESOURCE_MGMT_2 */
1152 tmp = 0;
1153 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1154 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1155 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1156
1157 /* SQ_THREAD_RESOURCE_MGMT */
1158 tmp = 0;
1159 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1160 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1161 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1162 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1163 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1164
1165 /* SQ_STACK_RESOURCE_MGMT_1 */
1166 tmp = 0;
1167 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1168 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1169 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1170
1171 /* SQ_STACK_RESOURCE_MGMT_2 */
1172 tmp = 0;
1173 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1174 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1175 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1176
1177 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1178 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1179
1180 if (family >= CHIP_RV770) {
1181 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1182 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1183 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1184 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1185 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1186 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
1187 } else {
1188 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1189 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1190 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1191 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1192 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1193 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
1194 }
1195 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1196 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1197 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1198 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1199 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1200 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1201 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1202 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1203 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1204 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1205 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1206 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1207 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1208 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1209 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1210 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1211 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1212 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1213 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1214 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1215 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1216 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1217 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1218 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1219 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1220 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1221
1222 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1223 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1224 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1225 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1226 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1227 r600_context_pipe_state_set(&rctx->ctx, rstate);
1228 }
1229
1230 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1231 {
1232 struct r600_pipe_state *rstate = &shader->rstate;
1233 struct r600_shader *rshader = &shader->shader;
1234 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
1235 int pos_index = -1, face_index = -1;
1236
1237 rstate->nregs = 0;
1238
1239 for (i = 0; i < rshader->ninput; i++) {
1240 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1241 pos_index = i;
1242 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1243 face_index = i;
1244 }
1245
1246 db_shader_control = 0;
1247 for (i = 0; i < rshader->noutput; i++) {
1248 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1249 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1250 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1251 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
1252 }
1253 if (rshader->uses_kill)
1254 db_shader_control |= S_02880C_KILL_ENABLE(1);
1255
1256 exports_ps = 0;
1257 num_cout = 0;
1258 for (i = 0; i < rshader->noutput; i++) {
1259 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1260 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1261 exports_ps |= 1;
1262 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1263 num_cout++;
1264 }
1265 }
1266 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
1267 if (!exports_ps) {
1268 /* always at least export 1 component per pixel */
1269 exports_ps = 2;
1270 }
1271
1272 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
1273 S_0286CC_PERSP_GRADIENT_ENA(1);
1274 spi_input_z = 0;
1275 if (pos_index != -1) {
1276 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
1277 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1278 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
1279 S_0286CC_BARYC_SAMPLE_CNTL(1));
1280 spi_input_z |= 1;
1281 }
1282
1283 spi_ps_in_control_1 = 0;
1284 if (face_index != -1) {
1285 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1286 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1287 }
1288
1289 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1290 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1291 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1292 r600_pipe_state_add_reg(rstate,
1293 R_028840_SQ_PGM_START_PS,
1294 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
1295 r600_pipe_state_add_reg(rstate,
1296 R_028850_SQ_PGM_RESOURCES_PS,
1297 S_028868_NUM_GPRS(rshader->bc.ngpr) |
1298 S_028868_STACK_SIZE(rshader->bc.nstack),
1299 0xFFFFFFFF, NULL);
1300 r600_pipe_state_add_reg(rstate,
1301 R_028854_SQ_PGM_EXPORTS_PS,
1302 exports_ps, 0xFFFFFFFF, NULL);
1303 r600_pipe_state_add_reg(rstate,
1304 R_0288CC_SQ_PGM_CF_OFFSET_PS,
1305 0x00000000, 0xFFFFFFFF, NULL);
1306 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
1307 S_028808_MULTIWRITE_ENABLE(!!rshader->fs_write_all),
1308 S_028808_MULTIWRITE_ENABLE(1),
1309 NULL);
1310 /* only set some bits here, the other bits are set in the dsa state */
1311 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
1312 db_shader_control,
1313 S_02880C_Z_EXPORT_ENABLE(1) |
1314 S_02880C_STENCIL_REF_EXPORT_ENABLE(1) |
1315 S_02880C_KILL_ENABLE(1),
1316 NULL);
1317
1318 r600_pipe_state_add_reg(rstate,
1319 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
1320 0xFFFFFFFF, NULL);
1321 }
1322
1323 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1324 {
1325 struct r600_pipe_state *rstate = &shader->rstate;
1326 struct r600_shader *rshader = &shader->shader;
1327 unsigned spi_vs_out_id[10];
1328 unsigned i, tmp;
1329
1330 /* clear previous register */
1331 rstate->nregs = 0;
1332
1333 /* so far never got proper semantic id from tgsi */
1334 /* FIXME better to move this in config things so they get emited
1335 * only one time per cs
1336 */
1337 for (i = 0; i < 10; i++) {
1338 spi_vs_out_id[i] = 0;
1339 }
1340 for (i = 0; i < 32; i++) {
1341 tmp = i << ((i & 3) * 8);
1342 spi_vs_out_id[i / 4] |= tmp;
1343 }
1344 for (i = 0; i < 10; i++) {
1345 r600_pipe_state_add_reg(rstate,
1346 R_028614_SPI_VS_OUT_ID_0 + i * 4,
1347 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1348 }
1349
1350 r600_pipe_state_add_reg(rstate,
1351 R_0286C4_SPI_VS_OUT_CONFIG,
1352 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1353 0xFFFFFFFF, NULL);
1354 r600_pipe_state_add_reg(rstate,
1355 R_028868_SQ_PGM_RESOURCES_VS,
1356 S_028868_NUM_GPRS(rshader->bc.ngpr) |
1357 S_028868_STACK_SIZE(rshader->bc.nstack),
1358 0xFFFFFFFF, NULL);
1359 r600_pipe_state_add_reg(rstate,
1360 R_0288D0_SQ_PGM_CF_OFFSET_VS,
1361 0x00000000, 0xFFFFFFFF, NULL);
1362 r600_pipe_state_add_reg(rstate,
1363 R_028858_SQ_PGM_START_VS,
1364 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
1365
1366 r600_pipe_state_add_reg(rstate,
1367 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1368 0xFFFFFFFF, NULL);
1369 }
1370
1371 void r600_fetch_shader(struct r600_vertex_element *ve)
1372 {
1373 struct r600_pipe_state *rstate;
1374
1375 rstate = &ve->rstate;
1376 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1377 rstate->nregs = 0;
1378 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1379 0x00000000, 0xFFFFFFFF, NULL);
1380 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1381 0x00000000, 0xFFFFFFFF, NULL);
1382 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1383 r600_bo_offset(ve->fetch_shader) >> 8,
1384 0xFFFFFFFF, ve->fetch_shader);
1385 }
1386
1387 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1388 {
1389 struct pipe_depth_stencil_alpha_state dsa;
1390 struct r600_pipe_state *rstate;
1391 boolean quirk = false;
1392
1393 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1394 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1395 quirk = true;
1396
1397 memset(&dsa, 0, sizeof(dsa));
1398
1399 if (quirk) {
1400 dsa.depth.enabled = 1;
1401 dsa.depth.func = PIPE_FUNC_LEQUAL;
1402 dsa.stencil[0].enabled = 1;
1403 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1404 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1405 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1406 dsa.stencil[0].writemask = 0xff;
1407 }
1408
1409 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1410 r600_pipe_state_add_reg(rstate,
1411 R_02880C_DB_SHADER_CONTROL,
1412 0x0,
1413 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1414 r600_pipe_state_add_reg(rstate,
1415 R_028D0C_DB_RENDER_CONTROL,
1416 S_028D0C_DEPTH_COPY_ENABLE(1) |
1417 S_028D0C_STENCIL_COPY_ENABLE(1) |
1418 S_028D0C_COPY_CENTROID(1),
1419 S_028D0C_DEPTH_COPY_ENABLE(1) |
1420 S_028D0C_STENCIL_COPY_ENABLE(1) |
1421 S_028D0C_COPY_CENTROID(1), NULL);
1422 return rstate;
1423 }
1424
1425 void r600_pipe_set_buffer_resource(struct r600_pipe_context *rctx,
1426 struct r600_pipe_state *rstate,
1427 struct r600_resource *rbuffer,
1428 unsigned offset, unsigned stride)
1429 {
1430 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
1431 offset, 0xFFFFFFFF, rbuffer->bo);
1432 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
1433 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
1434 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
1435 S_038008_STRIDE(stride),
1436 0xFFFFFFFF, NULL);
1437 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
1438 0x00000000, 0xFFFFFFFF, NULL);
1439 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
1440 0x00000000, 0xFFFFFFFF, NULL);
1441 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
1442 0x00000000, 0xFFFFFFFF, NULL);
1443 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
1444 0xC0000000, 0xFFFFFFFF, NULL);
1445 }