2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * - fix mask for depth control & cull for query
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_framebuffer.h>
40 #include "util/u_transfer.h"
41 #include <pipebuffer/pb_buffer.h>
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_state_inlines.h"
49 void r600_polygon_offset_update(struct r600_pipe_context
*rctx
)
51 struct r600_pipe_state state
;
53 state
.id
= R600_PIPE_STATE_POLYGON_OFFSET
;
55 if (rctx
->rasterizer
&& rctx
->framebuffer
.zsbuf
) {
56 float offset_units
= rctx
->rasterizer
->offset_units
;
57 unsigned offset_db_fmt_cntl
= 0, depth
;
59 switch (rctx
->framebuffer
.zsbuf
->texture
->format
) {
60 case PIPE_FORMAT_Z24X8_UNORM
:
61 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
65 case PIPE_FORMAT_Z32_FLOAT
:
68 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
70 case PIPE_FORMAT_Z16_UNORM
:
77 /* FIXME some of those reg can be computed with cso */
78 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
79 r600_pipe_state_add_reg(&state
,
80 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE
,
81 fui(rctx
->rasterizer
->offset_scale
), 0xFFFFFFFF, NULL
);
82 r600_pipe_state_add_reg(&state
,
83 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
84 fui(offset_units
), 0xFFFFFFFF, NULL
);
85 r600_pipe_state_add_reg(&state
,
86 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE
,
87 fui(rctx
->rasterizer
->offset_scale
), 0xFFFFFFFF, NULL
);
88 r600_pipe_state_add_reg(&state
,
89 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
90 fui(offset_units
), 0xFFFFFFFF, NULL
);
91 r600_pipe_state_add_reg(&state
,
92 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
93 offset_db_fmt_cntl
, 0xFFFFFFFF, NULL
);
94 r600_context_pipe_state_set(&rctx
->ctx
, &state
);
98 static void r600_set_blend_color(struct pipe_context
*ctx
,
99 const struct pipe_blend_color
*state
)
101 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
102 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
107 rstate
->id
= R600_PIPE_STATE_BLEND_COLOR
;
108 r600_pipe_state_add_reg(rstate
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]), 0xFFFFFFFF, NULL
);
109 r600_pipe_state_add_reg(rstate
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]), 0xFFFFFFFF, NULL
);
110 r600_pipe_state_add_reg(rstate
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]), 0xFFFFFFFF, NULL
);
111 r600_pipe_state_add_reg(rstate
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]), 0xFFFFFFFF, NULL
);
112 free(rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
]);
113 rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
] = rstate
;
114 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
117 static void *r600_create_blend_state(struct pipe_context
*ctx
,
118 const struct pipe_blend_state
*state
)
120 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
121 struct r600_pipe_blend
*blend
= CALLOC_STRUCT(r600_pipe_blend
);
122 struct r600_pipe_state
*rstate
;
123 u32 color_control
= 0, target_mask
;
128 rstate
= &blend
->rstate
;
130 rstate
->id
= R600_PIPE_STATE_BLEND
;
134 /* R600 does not support per-MRT blends */
135 if (rctx
->family
> CHIP_R600
)
136 color_control
|= S_028808_PER_MRT_BLEND(1);
137 if (state
->logicop_enable
) {
138 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
140 color_control
|= (0xcc << 16);
142 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
143 if (state
->independent_blend_enable
) {
144 for (int i
= 0; i
< 8; i
++) {
145 if (state
->rt
[i
].blend_enable
) {
146 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
148 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
151 for (int i
= 0; i
< 8; i
++) {
152 if (state
->rt
[0].blend_enable
) {
153 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
155 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
158 blend
->cb_target_mask
= target_mask
;
159 /* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */
160 r600_pipe_state_add_reg(rstate
, R_028808_CB_COLOR_CONTROL
,
161 color_control
, 0xFFFFFFFD, NULL
);
163 for (int i
= 0; i
< 8; i
++) {
164 /* state->rt entries > 0 only written if independent blending */
165 const int j
= state
->independent_blend_enable
? i
: 0;
167 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
168 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
169 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
171 unsigned eqA
= state
->rt
[j
].alpha_func
;
172 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
173 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
176 if (!state
->rt
[j
].blend_enable
)
179 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
180 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
181 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
183 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
184 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
185 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
186 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
187 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
190 /* R600 does not support per-MRT blends */
191 if (rctx
->family
> CHIP_R600
)
192 r600_pipe_state_add_reg(rstate
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, bc
, 0xFFFFFFFF, NULL
);
194 r600_pipe_state_add_reg(rstate
, R_028804_CB_BLEND_CONTROL
, bc
, 0xFFFFFFFF, NULL
);
199 static void *r600_create_dsa_state(struct pipe_context
*ctx
,
200 const struct pipe_depth_stencil_alpha_state
*state
)
202 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
203 struct r600_pipe_dsa
*dsa
= CALLOC_STRUCT(r600_pipe_dsa
);
204 unsigned db_depth_control
, alpha_test_control
, alpha_ref
, db_shader_control
;
205 unsigned stencil_ref_mask
, stencil_ref_mask_bf
, db_render_override
, db_render_control
;
206 struct r600_pipe_state
*rstate
;
212 rstate
= &dsa
->rstate
;
214 rstate
->id
= R600_PIPE_STATE_DSA
;
215 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
216 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
217 stencil_ref_mask
= 0;
218 stencil_ref_mask_bf
= 0;
219 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
220 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
221 S_028800_ZFUNC(state
->depth
.func
);
224 if (state
->stencil
[0].enabled
) {
225 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
226 db_depth_control
|= S_028800_STENCILFUNC(r600_translate_ds_func(state
->stencil
[0].func
));
227 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
228 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
229 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
232 stencil_ref_mask
= S_028430_STENCILMASK(state
->stencil
[0].valuemask
) |
233 S_028430_STENCILWRITEMASK(state
->stencil
[0].writemask
);
234 if (state
->stencil
[1].enabled
) {
235 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
236 db_depth_control
|= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state
->stencil
[1].func
));
237 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
238 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
239 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
240 stencil_ref_mask_bf
= S_028434_STENCILMASK_BF(state
->stencil
[1].valuemask
) |
241 S_028434_STENCILWRITEMASK_BF(state
->stencil
[1].writemask
);
246 alpha_test_control
= 0;
248 if (state
->alpha
.enabled
) {
249 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
250 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
251 alpha_ref
= fui(state
->alpha
.ref_value
);
253 dsa
->alpha_ref
= alpha_ref
;
256 db_render_control
= 0;
257 db_render_override
= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
) |
258 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE
) |
259 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE
);
260 /* TODO db_render_override depends on query */
261 r600_pipe_state_add_reg(rstate
, R_028028_DB_STENCIL_CLEAR
, 0x00000000, 0xFFFFFFFF, NULL
);
262 r600_pipe_state_add_reg(rstate
, R_02802C_DB_DEPTH_CLEAR
, 0x3F800000, 0xFFFFFFFF, NULL
);
263 r600_pipe_state_add_reg(rstate
, R_028410_SX_ALPHA_TEST_CONTROL
, alpha_test_control
, 0xFFFFFFFF, NULL
);
264 r600_pipe_state_add_reg(rstate
,
265 R_028430_DB_STENCILREFMASK
, stencil_ref_mask
,
266 0xFFFFFFFF & C_028430_STENCILREF
, NULL
);
267 r600_pipe_state_add_reg(rstate
,
268 R_028434_DB_STENCILREFMASK_BF
, stencil_ref_mask_bf
,
269 0xFFFFFFFF & C_028434_STENCILREF_BF
, NULL
);
270 r600_pipe_state_add_reg(rstate
, R_0286E0_SPI_FOG_FUNC_SCALE
, 0x00000000, 0xFFFFFFFF, NULL
);
271 r600_pipe_state_add_reg(rstate
, R_0286E4_SPI_FOG_FUNC_BIAS
, 0x00000000, 0xFFFFFFFF, NULL
);
272 r600_pipe_state_add_reg(rstate
, R_0286DC_SPI_FOG_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
273 r600_pipe_state_add_reg(rstate
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
, 0xFFFFFFFF, NULL
);
274 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
275 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
276 * r600_pipe_shader_ps().*/
277 r600_pipe_state_add_reg(rstate
, R_02880C_DB_SHADER_CONTROL
, db_shader_control
, 0xFFFFFFBC, NULL
);
278 r600_pipe_state_add_reg(rstate
, R_028D0C_DB_RENDER_CONTROL
, db_render_control
, 0xFFFFFFFF, NULL
);
279 r600_pipe_state_add_reg(rstate
, R_028D10_DB_RENDER_OVERRIDE
, db_render_override
, 0xFFFFFFFF, NULL
);
280 r600_pipe_state_add_reg(rstate
, R_028D2C_DB_SRESULTS_COMPARE_STATE1
, 0x00000000, 0xFFFFFFFF, NULL
);
281 r600_pipe_state_add_reg(rstate
, R_028D30_DB_PRELOAD_CONTROL
, 0x00000000, 0xFFFFFFFF, NULL
);
282 r600_pipe_state_add_reg(rstate
, R_028D44_DB_ALPHA_TO_MASK
, 0x0000AA00, 0xFFFFFFFF, NULL
);
287 static void *r600_create_rs_state(struct pipe_context
*ctx
,
288 const struct pipe_rasterizer_state
*state
)
290 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
291 struct r600_pipe_rasterizer
*rs
= CALLOC_STRUCT(r600_pipe_rasterizer
);
292 struct r600_pipe_state
*rstate
;
294 unsigned prov_vtx
= 1, polygon_dual_mode
;
301 rstate
= &rs
->rstate
;
302 rs
->flatshade
= state
->flatshade
;
303 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
305 clip_rule
= state
->scissor
? 0xAAAA : 0xFFFF;
307 rs
->offset_units
= state
->offset_units
;
308 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
310 rstate
->id
= R600_PIPE_STATE_RASTERIZER
;
311 if (state
->flatshade_first
)
313 tmp
= S_0286D4_FLAT_SHADE_ENA(1);
314 if (state
->sprite_coord_enable
) {
315 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
316 S_0286D4_PNT_SPRITE_OVRD_X(2) |
317 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
318 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
319 S_0286D4_PNT_SPRITE_OVRD_W(1);
320 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
321 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
324 r600_pipe_state_add_reg(rstate
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
, 0xFFFFFFFF, NULL
);
326 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
327 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
328 r600_pipe_state_add_reg(rstate
, R_028814_PA_SU_SC_MODE_CNTL
,
329 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
330 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
331 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
332 S_028814_FACE(!state
->front_ccw
) |
333 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
334 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
335 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
336 S_028814_POLY_MODE(polygon_dual_mode
) |
337 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
338 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)), 0xFFFFFFFF, NULL
);
339 r600_pipe_state_add_reg(rstate
, R_02881C_PA_CL_VS_OUT_CNTL
,
340 S_02881C_USE_VTX_POINT_SIZE(state
->point_size_per_vertex
) |
341 S_02881C_VS_OUT_MISC_VEC_ENA(state
->point_size_per_vertex
), 0xFFFFFFFF, NULL
);
342 r600_pipe_state_add_reg(rstate
, R_028820_PA_CL_NANINF_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
343 /* point size 12.4 fixed point */
344 tmp
= (unsigned)(state
->point_size
* 8.0);
345 r600_pipe_state_add_reg(rstate
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
), 0xFFFFFFFF, NULL
);
346 r600_pipe_state_add_reg(rstate
, R_028A04_PA_SU_POINT_MINMAX
, 0x80000000, 0xFFFFFFFF, NULL
);
348 tmp
= (unsigned)state
->line_width
* 8;
349 r600_pipe_state_add_reg(rstate
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
), 0xFFFFFFFF, NULL
);
351 r600_pipe_state_add_reg(rstate
, R_028A0C_PA_SC_LINE_STIPPLE
, 0x00000005, 0xFFFFFFFF, NULL
);
352 r600_pipe_state_add_reg(rstate
, R_028A48_PA_SC_MPASS_PS_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
353 r600_pipe_state_add_reg(rstate
, R_028C00_PA_SC_LINE_CNTL
, 0x00000400, 0xFFFFFFFF, NULL
);
355 r600_pipe_state_add_reg(rstate
, R_028C08_PA_SU_VTX_CNTL
,
356 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
),
359 r600_pipe_state_add_reg(rstate
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
360 r600_pipe_state_add_reg(rstate
, R_028C10_PA_CL_GB_VERT_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
361 r600_pipe_state_add_reg(rstate
, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
362 r600_pipe_state_add_reg(rstate
, R_028C18_PA_CL_GB_HORZ_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
363 r600_pipe_state_add_reg(rstate
, R_028DFC_PA_SU_POLY_OFFSET_CLAMP
, 0x00000000, 0xFFFFFFFF, NULL
);
364 r600_pipe_state_add_reg(rstate
, R_02820C_PA_SC_CLIPRECT_RULE
, clip_rule
, 0xFFFFFFFF, NULL
);
369 static void *r600_create_sampler_state(struct pipe_context
*ctx
,
370 const struct pipe_sampler_state
*state
)
372 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
374 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 4 : 0;
376 if (rstate
== NULL
) {
380 rstate
->id
= R600_PIPE_STATE_SAMPLER
;
381 util_pack_color(state
->border_color
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
382 r600_pipe_state_add_reg_noblock(rstate
, R_03C000_SQ_TEX_SAMPLER_WORD0_0
,
383 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
384 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
385 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
386 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
387 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
388 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
389 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
390 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
391 S_03C000_BORDER_COLOR_TYPE(uc
.ui
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0), 0xFFFFFFFF, NULL
);
392 r600_pipe_state_add_reg_noblock(rstate
, R_03C004_SQ_TEX_SAMPLER_WORD1_0
,
393 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
394 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
395 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6)), 0xFFFFFFFF, NULL
);
396 r600_pipe_state_add_reg_noblock(rstate
, R_03C008_SQ_TEX_SAMPLER_WORD2_0
, S_03C008_TYPE(1), 0xFFFFFFFF, NULL
);
398 r600_pipe_state_add_reg_noblock(rstate
, R_00A400_TD_PS_SAMPLER0_BORDER_RED
, fui(state
->border_color
[0]), 0xFFFFFFFF, NULL
);
399 r600_pipe_state_add_reg_noblock(rstate
, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN
, fui(state
->border_color
[1]), 0xFFFFFFFF, NULL
);
400 r600_pipe_state_add_reg_noblock(rstate
, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE
, fui(state
->border_color
[2]), 0xFFFFFFFF, NULL
);
401 r600_pipe_state_add_reg_noblock(rstate
, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA
, fui(state
->border_color
[3]), 0xFFFFFFFF, NULL
);
406 static struct pipe_sampler_view
*r600_create_sampler_view(struct pipe_context
*ctx
,
407 struct pipe_resource
*texture
,
408 const struct pipe_sampler_view
*state
)
410 struct r600_pipe_sampler_view
*resource
= CALLOC_STRUCT(r600_pipe_sampler_view
);
411 struct r600_pipe_resource_state
*rstate
;
412 const struct util_format_description
*desc
;
413 struct r600_resource_texture
*tmp
;
414 struct r600_resource
*rbuffer
;
415 unsigned format
, endian
;
416 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
417 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
418 struct r600_bo
*bo
[2];
419 unsigned width
, height
, depth
, offset_level
, last_level
;
421 if (resource
== NULL
)
423 rstate
= &resource
->state
;
425 /* initialize base object */
426 resource
->base
= *state
;
427 resource
->base
.texture
= NULL
;
428 pipe_reference(NULL
, &texture
->reference
);
429 resource
->base
.texture
= texture
;
430 resource
->base
.reference
.count
= 1;
431 resource
->base
.context
= ctx
;
433 swizzle
[0] = state
->swizzle_r
;
434 swizzle
[1] = state
->swizzle_g
;
435 swizzle
[2] = state
->swizzle_b
;
436 swizzle
[3] = state
->swizzle_a
;
437 format
= r600_translate_texformat(ctx
->screen
, state
->format
,
439 &word4
, &yuv_format
);
443 desc
= util_format_description(state
->format
);
445 R600_ERR("unknown format %d\n", state
->format
);
447 tmp
= (struct r600_resource_texture
*)texture
;
448 if (tmp
->depth
&& !tmp
->is_flushing_texture
) {
449 r600_texture_depth_flush(ctx
, texture
, TRUE
);
450 tmp
= tmp
->flushed_depth_texture
;
452 endian
= r600_colorformat_endian_swap(format
);
454 if (tmp
->force_int_type
) {
455 word4
&= C_038010_NUM_FORMAT_ALL
;
456 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
458 rbuffer
= &tmp
->resource
;
462 offset_level
= state
->u
.tex
.first_level
;
463 last_level
= state
->u
.tex
.last_level
- offset_level
;
464 width
= u_minify(texture
->width0
, offset_level
);
465 height
= u_minify(texture
->height0
, offset_level
);
466 depth
= u_minify(texture
->depth0
, offset_level
);
468 pitch
= align(tmp
->pitch_in_blocks
[offset_level
] *
469 util_format_get_blockwidth(state
->format
), 8);
470 array_mode
= tmp
->array_mode
[offset_level
];
471 tile_type
= tmp
->tile_type
;
473 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
475 depth
= texture
->array_size
;
476 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
477 depth
= texture
->array_size
;
480 rstate
->bo
[0] = bo
[0];
481 rstate
->bo
[1] = bo
[1];
483 rstate
->val
[0] = (S_038000_DIM(r600_tex_dim(texture
->target
)) |
484 S_038000_TILE_MODE(array_mode
) |
485 S_038000_TILE_TYPE(tile_type
) |
486 S_038000_PITCH((pitch
/ 8) - 1) |
487 S_038000_TEX_WIDTH(width
- 1));
488 rstate
->val
[1] = (S_038004_TEX_HEIGHT(height
- 1) |
489 S_038004_TEX_DEPTH(depth
- 1) |
490 S_038004_DATA_FORMAT(format
));
491 rstate
->val
[2] = (tmp
->offset
[offset_level
] + r600_bo_offset(bo
[0])) >> 8;
492 rstate
->val
[3] = (tmp
->offset
[offset_level
+1] + r600_bo_offset(bo
[1])) >> 8;
493 rstate
->val
[4] = (word4
|
494 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
495 S_038010_REQUEST_SIZE(1) |
496 S_038010_ENDIAN_SWAP(endian
) |
497 S_038010_BASE_LEVEL(0));
498 rstate
->val
[5] = (S_038014_LAST_LEVEL(last_level
) |
499 S_038014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
500 S_038014_LAST_ARRAY(state
->u
.tex
.last_layer
));
501 rstate
->val
[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
) |
502 S_038018_MAX_ANISO(4 /* max 16 samples */));
504 return &resource
->base
;
507 static void r600_set_vs_sampler_view(struct pipe_context
*ctx
, unsigned count
,
508 struct pipe_sampler_view
**views
)
510 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
511 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
513 for (int i
= 0; i
< count
; i
++) {
515 r600_context_pipe_state_set_vs_resource(&rctx
->ctx
, &resource
[i
]->state
,
516 i
+ R600_MAX_CONST_BUFFERS
);
521 static void r600_set_ps_sampler_view(struct pipe_context
*ctx
, unsigned count
,
522 struct pipe_sampler_view
**views
)
524 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
525 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
529 for (i
= 0; i
< count
; i
++) {
530 if (&rctx
->ps_samplers
.views
[i
]->base
!= views
[i
]) {
532 if (((struct r600_resource_texture
*)resource
[i
]->base
.texture
)->depth
)
534 r600_context_pipe_state_set_ps_resource(&rctx
->ctx
, &resource
[i
]->state
,
535 i
+ R600_MAX_CONST_BUFFERS
);
537 r600_context_pipe_state_set_ps_resource(&rctx
->ctx
, NULL
,
538 i
+ R600_MAX_CONST_BUFFERS
);
540 pipe_sampler_view_reference(
541 (struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
],
546 if (((struct r600_resource_texture
*)resource
[i
]->base
.texture
)->depth
)
551 for (i
= count
; i
< NUM_TEX_UNITS
; i
++) {
552 if (rctx
->ps_samplers
.views
[i
]) {
553 r600_context_pipe_state_set_ps_resource(&rctx
->ctx
, NULL
,
554 i
+ R600_MAX_CONST_BUFFERS
);
555 pipe_sampler_view_reference((struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
], NULL
);
558 rctx
->have_depth_texture
= has_depth
;
559 rctx
->ps_samplers
.n_views
= count
;
562 static void r600_bind_ps_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
564 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
565 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
567 memcpy(rctx
->ps_samplers
.samplers
, states
, sizeof(void*) * count
);
568 rctx
->ps_samplers
.n_samplers
= count
;
570 for (int i
= 0; i
< count
; i
++) {
571 r600_context_pipe_state_set_ps_sampler(&rctx
->ctx
, rstates
[i
], i
);
575 static void r600_bind_vs_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
577 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
578 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
580 for (int i
= 0; i
< count
; i
++) {
581 r600_context_pipe_state_set_vs_sampler(&rctx
->ctx
, rstates
[i
], i
);
585 static void r600_set_clip_state(struct pipe_context
*ctx
,
586 const struct pipe_clip_state
*state
)
588 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
589 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
595 rstate
->id
= R600_PIPE_STATE_CLIP
;
596 for (int i
= 0; i
< state
->nr
; i
++) {
597 r600_pipe_state_add_reg(rstate
,
598 R_028E20_PA_CL_UCP0_X
+ i
* 16,
599 fui(state
->ucp
[i
][0]), 0xFFFFFFFF, NULL
);
600 r600_pipe_state_add_reg(rstate
,
601 R_028E24_PA_CL_UCP0_Y
+ i
* 16,
602 fui(state
->ucp
[i
][1]) , 0xFFFFFFFF, NULL
);
603 r600_pipe_state_add_reg(rstate
,
604 R_028E28_PA_CL_UCP0_Z
+ i
* 16,
605 fui(state
->ucp
[i
][2]), 0xFFFFFFFF, NULL
);
606 r600_pipe_state_add_reg(rstate
,
607 R_028E2C_PA_CL_UCP0_W
+ i
* 16,
608 fui(state
->ucp
[i
][3]), 0xFFFFFFFF, NULL
);
610 r600_pipe_state_add_reg(rstate
, R_028810_PA_CL_CLIP_CNTL
,
611 S_028810_PS_UCP_MODE(3) | ((1 << state
->nr
) - 1) |
612 S_028810_ZCLIP_NEAR_DISABLE(state
->depth_clamp
) |
613 S_028810_ZCLIP_FAR_DISABLE(state
->depth_clamp
), 0xFFFFFFFF, NULL
);
615 free(rctx
->states
[R600_PIPE_STATE_CLIP
]);
616 rctx
->states
[R600_PIPE_STATE_CLIP
] = rstate
;
617 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
620 static void r600_set_polygon_stipple(struct pipe_context
*ctx
,
621 const struct pipe_poly_stipple
*state
)
625 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
629 static void r600_set_scissor_state(struct pipe_context
*ctx
,
630 const struct pipe_scissor_state
*state
)
632 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
633 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
639 rstate
->id
= R600_PIPE_STATE_SCISSOR
;
640 tl
= S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
) | S_028240_WINDOW_OFFSET_DISABLE(1);
641 br
= S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
);
642 r600_pipe_state_add_reg(rstate
,
643 R_028210_PA_SC_CLIPRECT_0_TL
, tl
,
645 r600_pipe_state_add_reg(rstate
,
646 R_028214_PA_SC_CLIPRECT_0_BR
, br
,
648 r600_pipe_state_add_reg(rstate
,
649 R_028218_PA_SC_CLIPRECT_1_TL
, tl
,
651 r600_pipe_state_add_reg(rstate
,
652 R_02821C_PA_SC_CLIPRECT_1_BR
, br
,
654 r600_pipe_state_add_reg(rstate
,
655 R_028220_PA_SC_CLIPRECT_2_TL
, tl
,
657 r600_pipe_state_add_reg(rstate
,
658 R_028224_PA_SC_CLIPRECT_2_BR
, br
,
660 r600_pipe_state_add_reg(rstate
,
661 R_028228_PA_SC_CLIPRECT_3_TL
, tl
,
663 r600_pipe_state_add_reg(rstate
,
664 R_02822C_PA_SC_CLIPRECT_3_BR
, br
,
667 free(rctx
->states
[R600_PIPE_STATE_SCISSOR
]);
668 rctx
->states
[R600_PIPE_STATE_SCISSOR
] = rstate
;
669 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
672 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
673 const struct pipe_stencil_ref
*state
)
675 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
676 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
682 rctx
->stencil_ref
= *state
;
683 rstate
->id
= R600_PIPE_STATE_STENCIL_REF
;
684 tmp
= S_028430_STENCILREF(state
->ref_value
[0]);
685 r600_pipe_state_add_reg(rstate
,
686 R_028430_DB_STENCILREFMASK
, tmp
,
687 ~C_028430_STENCILREF
, NULL
);
688 tmp
= S_028434_STENCILREF_BF(state
->ref_value
[1]);
689 r600_pipe_state_add_reg(rstate
,
690 R_028434_DB_STENCILREFMASK_BF
, tmp
,
691 ~C_028434_STENCILREF_BF
, NULL
);
693 free(rctx
->states
[R600_PIPE_STATE_STENCIL_REF
]);
694 rctx
->states
[R600_PIPE_STATE_STENCIL_REF
] = rstate
;
695 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
698 static void r600_set_viewport_state(struct pipe_context
*ctx
,
699 const struct pipe_viewport_state
*state
)
701 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
702 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
707 rctx
->viewport
= *state
;
708 rstate
->id
= R600_PIPE_STATE_VIEWPORT
;
709 r600_pipe_state_add_reg(rstate
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 0x00000000, 0xFFFFFFFF, NULL
);
710 r600_pipe_state_add_reg(rstate
, R_0282D4_PA_SC_VPORT_ZMAX_0
, 0x3F800000, 0xFFFFFFFF, NULL
);
711 r600_pipe_state_add_reg(rstate
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]), 0xFFFFFFFF, NULL
);
712 r600_pipe_state_add_reg(rstate
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]), 0xFFFFFFFF, NULL
);
713 r600_pipe_state_add_reg(rstate
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]), 0xFFFFFFFF, NULL
);
714 r600_pipe_state_add_reg(rstate
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]), 0xFFFFFFFF, NULL
);
715 r600_pipe_state_add_reg(rstate
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]), 0xFFFFFFFF, NULL
);
716 r600_pipe_state_add_reg(rstate
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]), 0xFFFFFFFF, NULL
);
717 r600_pipe_state_add_reg(rstate
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F, 0xFFFFFFFF, NULL
);
719 free(rctx
->states
[R600_PIPE_STATE_VIEWPORT
]);
720 rctx
->states
[R600_PIPE_STATE_VIEWPORT
] = rstate
;
721 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
724 static void r600_cb(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
,
725 const struct pipe_framebuffer_state
*state
, int cb
)
727 struct r600_resource_texture
*rtex
;
728 struct r600_resource
*rbuffer
;
729 struct r600_surface
*surf
;
730 unsigned level
= state
->cbufs
[cb
]->u
.tex
.level
;
731 unsigned pitch
, slice
;
733 unsigned format
, swap
, ntype
, endian
;
735 const struct util_format_description
*desc
;
736 struct r600_bo
*bo
[3];
739 surf
= (struct r600_surface
*)state
->cbufs
[cb
];
740 rtex
= (struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
;
743 rctx
->have_depth_fb
= TRUE
;
745 if (rtex
->depth
&& !rtex
->is_flushing_texture
) {
746 r600_texture_depth_flush(&rctx
->context
, state
->cbufs
[cb
]->texture
, TRUE
);
747 rtex
= rtex
->flushed_depth_texture
;
750 rbuffer
= &rtex
->resource
;
755 /* XXX quite sure for dx10+ hw don't need any offset hacks */
756 offset
= r600_texture_get_offset(rtex
,
757 level
, state
->cbufs
[cb
]->u
.tex
.first_layer
);
758 pitch
= rtex
->pitch_in_blocks
[level
] / 8 - 1;
759 slice
= rtex
->pitch_in_blocks
[level
] * surf
->aligned_height
/ 64 - 1;
760 desc
= util_format_description(surf
->base
.format
);
762 for (i
= 0; i
< 4; i
++) {
763 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
767 ntype
= V_0280A0_NUMBER_UNORM
;
768 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
769 ntype
= V_0280A0_NUMBER_SRGB
;
770 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
)
771 ntype
= V_0280A0_NUMBER_SNORM
;
773 format
= r600_translate_colorformat(surf
->base
.format
);
774 swap
= r600_translate_colorswap(surf
->base
.format
);
775 if(rbuffer
->b
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
776 endian
= ENDIAN_NONE
;
778 endian
= r600_colorformat_endian_swap(format
);
781 /* disable when gallium grows int textures */
782 if ((format
== FMT_32_32_32_32
|| format
== FMT_16_16_16_16
) && rtex
->force_int_type
)
783 ntype
= V_0280A0_NUMBER_UINT
;
785 color_info
= S_0280A0_FORMAT(format
) |
786 S_0280A0_COMP_SWAP(swap
) |
787 S_0280A0_ARRAY_MODE(rtex
->array_mode
[level
]) |
788 S_0280A0_BLEND_CLAMP(1) |
789 S_0280A0_NUMBER_TYPE(ntype
) |
790 S_0280A0_ENDIAN(endian
);
792 /* EXPORT_NORM is an optimzation that can be enabled for better
793 * performance in certain cases
795 if (rctx
->family
< CHIP_RV770
) {
796 /* EXPORT_NORM can be enabled if:
797 * - 11-bit or smaller UNORM/SNORM/SRGB
798 * - BLEND_CLAMP is enabled
799 * - BLEND_FLOAT32 is disabled
801 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
802 (desc
->channel
[i
].size
< 12 &&
803 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
804 ntype
!= V_0280A0_NUMBER_UINT
&&
805 ntype
!= V_0280A0_NUMBER_SINT
) &&
806 G_0280A0_BLEND_CLAMP(color_info
) &&
807 !G_0280A0_BLEND_FLOAT32(color_info
))
808 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
810 /* EXPORT_NORM can be enabled if:
811 * - 11-bit or smaller UNORM/SNORM/SRGB
812 * - 16-bit or smaller FLOAT
814 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
815 ((desc
->channel
[i
].size
< 12 &&
816 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
817 ntype
!= V_0280A0_NUMBER_UINT
&& ntype
!= V_0280A0_NUMBER_SINT
) ||
818 (desc
->channel
[i
].size
< 17 &&
819 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)))
820 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
823 r600_pipe_state_add_reg(rstate
,
824 R_028040_CB_COLOR0_BASE
+ cb
* 4,
825 (offset
+ r600_bo_offset(bo
[0])) >> 8, 0xFFFFFFFF, bo
[0]);
826 r600_pipe_state_add_reg(rstate
,
827 R_0280A0_CB_COLOR0_INFO
+ cb
* 4,
828 color_info
, 0xFFFFFFFF, bo
[0]);
829 r600_pipe_state_add_reg(rstate
,
830 R_028060_CB_COLOR0_SIZE
+ cb
* 4,
831 S_028060_PITCH_TILE_MAX(pitch
) |
832 S_028060_SLICE_TILE_MAX(slice
),
834 r600_pipe_state_add_reg(rstate
,
835 R_028080_CB_COLOR0_VIEW
+ cb
* 4,
836 0x00000000, 0xFFFFFFFF, NULL
);
837 r600_pipe_state_add_reg(rstate
,
838 R_0280E0_CB_COLOR0_FRAG
+ cb
* 4,
839 r600_bo_offset(bo
[1]) >> 8, 0xFFFFFFFF, bo
[1]);
840 r600_pipe_state_add_reg(rstate
,
841 R_0280C0_CB_COLOR0_TILE
+ cb
* 4,
842 r600_bo_offset(bo
[2]) >> 8, 0xFFFFFFFF, bo
[2]);
843 r600_pipe_state_add_reg(rstate
,
844 R_028100_CB_COLOR0_MASK
+ cb
* 4,
845 0x00000000, 0xFFFFFFFF, NULL
);
848 static void r600_db(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
,
849 const struct pipe_framebuffer_state
*state
)
851 struct r600_resource_texture
*rtex
;
852 struct r600_resource
*rbuffer
;
853 struct r600_surface
*surf
;
855 unsigned pitch
, slice
, format
;
858 if (state
->zsbuf
== NULL
)
861 level
= state
->zsbuf
->u
.tex
.level
;
863 surf
= (struct r600_surface
*)state
->zsbuf
;
864 rtex
= (struct r600_resource_texture
*)state
->zsbuf
->texture
;
866 rbuffer
= &rtex
->resource
;
868 /* XXX quite sure for dx10+ hw don't need any offset hacks */
869 offset
= r600_texture_get_offset((struct r600_resource_texture
*)state
->zsbuf
->texture
,
870 level
, state
->zsbuf
->u
.tex
.first_layer
);
871 pitch
= rtex
->pitch_in_blocks
[level
] / 8 - 1;
872 slice
= rtex
->pitch_in_blocks
[level
] * surf
->aligned_height
/ 64 - 1;
873 format
= r600_translate_dbformat(state
->zsbuf
->texture
->format
);
875 r600_pipe_state_add_reg(rstate
, R_02800C_DB_DEPTH_BASE
,
876 (offset
+ r600_bo_offset(rbuffer
->bo
)) >> 8, 0xFFFFFFFF, rbuffer
->bo
);
877 r600_pipe_state_add_reg(rstate
, R_028000_DB_DEPTH_SIZE
,
878 S_028000_PITCH_TILE_MAX(pitch
) | S_028000_SLICE_TILE_MAX(slice
),
880 r600_pipe_state_add_reg(rstate
, R_028004_DB_DEPTH_VIEW
, 0x00000000, 0xFFFFFFFF, NULL
);
881 r600_pipe_state_add_reg(rstate
, R_028010_DB_DEPTH_INFO
,
882 S_028010_ARRAY_MODE(rtex
->array_mode
[level
]) | S_028010_FORMAT(format
),
883 0xFFFFFFFF, rbuffer
->bo
);
884 r600_pipe_state_add_reg(rstate
, R_028D34_DB_PREFETCH_LIMIT
,
885 (surf
->aligned_height
/ 8) - 1, 0xFFFFFFFF, NULL
);
888 static void r600_set_framebuffer_state(struct pipe_context
*ctx
,
889 const struct pipe_framebuffer_state
*state
)
891 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
892 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
893 u32 shader_mask
, tl
, br
, shader_control
, target_mask
;
898 r600_context_flush_dest_caches(&rctx
->ctx
);
899 rctx
->ctx
.num_dest_buffers
= state
->nr_cbufs
;
901 /* unreference old buffer and reference new one */
902 rstate
->id
= R600_PIPE_STATE_FRAMEBUFFER
;
904 util_copy_framebuffer_state(&rctx
->framebuffer
, state
);
907 rctx
->have_depth_fb
= 0;
908 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
909 r600_cb(rctx
, rstate
, state
, i
);
912 r600_db(rctx
, rstate
, state
);
913 rctx
->ctx
.num_dest_buffers
++;
916 target_mask
= 0x00000000;
917 target_mask
= 0xFFFFFFFF;
920 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
921 target_mask
^= 0xf << (i
* 4);
922 shader_mask
|= 0xf << (i
* 4);
923 shader_control
|= 1 << i
;
925 tl
= S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
926 br
= S_028244_BR_X(state
->width
) | S_028244_BR_Y(state
->height
);
928 r600_pipe_state_add_reg(rstate
,
929 R_028030_PA_SC_SCREEN_SCISSOR_TL
, tl
,
931 r600_pipe_state_add_reg(rstate
,
932 R_028034_PA_SC_SCREEN_SCISSOR_BR
, br
,
934 r600_pipe_state_add_reg(rstate
,
935 R_028204_PA_SC_WINDOW_SCISSOR_TL
, tl
,
937 r600_pipe_state_add_reg(rstate
,
938 R_028208_PA_SC_WINDOW_SCISSOR_BR
, br
,
940 r600_pipe_state_add_reg(rstate
,
941 R_028240_PA_SC_GENERIC_SCISSOR_TL
, tl
,
943 r600_pipe_state_add_reg(rstate
,
944 R_028244_PA_SC_GENERIC_SCISSOR_BR
, br
,
946 r600_pipe_state_add_reg(rstate
,
947 R_028250_PA_SC_VPORT_SCISSOR_0_TL
, tl
,
949 r600_pipe_state_add_reg(rstate
,
950 R_028254_PA_SC_VPORT_SCISSOR_0_BR
, br
,
952 r600_pipe_state_add_reg(rstate
,
953 R_028200_PA_SC_WINDOW_OFFSET
, 0x00000000,
955 if (rctx
->family
>= CHIP_RV770
) {
956 r600_pipe_state_add_reg(rstate
,
957 R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA,
961 r600_pipe_state_add_reg(rstate
, R_0287A0_CB_SHADER_CONTROL
,
962 shader_control
, 0xFFFFFFFF, NULL
);
963 r600_pipe_state_add_reg(rstate
, R_028238_CB_TARGET_MASK
,
964 0x00000000, target_mask
, NULL
);
965 r600_pipe_state_add_reg(rstate
, R_02823C_CB_SHADER_MASK
,
966 shader_mask
, 0xFFFFFFFF, NULL
);
967 r600_pipe_state_add_reg(rstate
, R_028C04_PA_SC_AA_CONFIG
,
968 0x00000000, 0xFFFFFFFF, NULL
);
969 r600_pipe_state_add_reg(rstate
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
,
970 0x00000000, 0xFFFFFFFF, NULL
);
971 r600_pipe_state_add_reg(rstate
, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX
,
972 0x00000000, 0xFFFFFFFF, NULL
);
973 r600_pipe_state_add_reg(rstate
, R_028C30_CB_CLRCMP_CONTROL
,
974 0x01000000, 0xFFFFFFFF, NULL
);
975 r600_pipe_state_add_reg(rstate
, R_028C34_CB_CLRCMP_SRC
,
976 0x00000000, 0xFFFFFFFF, NULL
);
977 r600_pipe_state_add_reg(rstate
, R_028C38_CB_CLRCMP_DST
,
978 0x000000FF, 0xFFFFFFFF, NULL
);
979 r600_pipe_state_add_reg(rstate
, R_028C3C_CB_CLRCMP_MSK
,
980 0xFFFFFFFF, 0xFFFFFFFF, NULL
);
981 r600_pipe_state_add_reg(rstate
, R_028C48_PA_SC_AA_MASK
,
982 0xFFFFFFFF, 0xFFFFFFFF, NULL
);
984 free(rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
]);
985 rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
] = rstate
;
986 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
989 r600_polygon_offset_update(rctx
);
993 static void r600_texture_barrier(struct pipe_context
*ctx
)
995 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
997 r600_context_flush_all(&rctx
->ctx
, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
998 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
999 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1000 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1001 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1));
1004 void r600_init_state_functions(struct r600_pipe_context
*rctx
)
1006 rctx
->context
.create_blend_state
= r600_create_blend_state
;
1007 rctx
->context
.create_depth_stencil_alpha_state
= r600_create_dsa_state
;
1008 rctx
->context
.create_fs_state
= r600_create_shader_state
;
1009 rctx
->context
.create_rasterizer_state
= r600_create_rs_state
;
1010 rctx
->context
.create_sampler_state
= r600_create_sampler_state
;
1011 rctx
->context
.create_sampler_view
= r600_create_sampler_view
;
1012 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
1013 rctx
->context
.create_vs_state
= r600_create_shader_state
;
1014 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
1015 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
1016 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_sampler
;
1017 rctx
->context
.bind_fs_state
= r600_bind_ps_shader
;
1018 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
1019 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
1020 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_sampler
;
1021 rctx
->context
.bind_vs_state
= r600_bind_vs_shader
;
1022 rctx
->context
.delete_blend_state
= r600_delete_state
;
1023 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
1024 rctx
->context
.delete_fs_state
= r600_delete_ps_shader
;
1025 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
1026 rctx
->context
.delete_sampler_state
= r600_delete_state
;
1027 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_element
;
1028 rctx
->context
.delete_vs_state
= r600_delete_vs_shader
;
1029 rctx
->context
.set_blend_color
= r600_set_blend_color
;
1030 rctx
->context
.set_clip_state
= r600_set_clip_state
;
1031 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1032 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_view
;
1033 rctx
->context
.set_framebuffer_state
= r600_set_framebuffer_state
;
1034 rctx
->context
.set_polygon_stipple
= r600_set_polygon_stipple
;
1035 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
1036 rctx
->context
.set_scissor_state
= r600_set_scissor_state
;
1037 rctx
->context
.set_stencil_ref
= r600_set_stencil_ref
;
1038 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1039 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1040 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_view
;
1041 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
1042 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1043 rctx
->context
.redefine_user_buffer
= u_default_redefine_user_buffer
;
1044 rctx
->context
.texture_barrier
= r600_texture_barrier
;
1047 void r600_adjust_gprs(struct r600_pipe_context
*rctx
)
1049 enum radeon_family family
;
1050 struct r600_pipe_state rstate
;
1051 unsigned num_ps_gprs
= rctx
->default_ps_gprs
;
1052 unsigned num_vs_gprs
= rctx
->default_vs_gprs
;
1056 family
= r600_get_family(rctx
->radeon
);
1058 if (family
>= CHIP_CEDAR
)
1061 if (!rctx
->ps_shader
&& !rctx
->vs_shader
)
1064 if (rctx
->ps_shader
->shader
.bc
.ngpr
> rctx
->default_ps_gprs
)
1066 diff
= rctx
->ps_shader
->shader
.bc
.ngpr
- rctx
->default_ps_gprs
;
1067 num_vs_gprs
-= diff
;
1068 num_ps_gprs
+= diff
;
1071 if (rctx
->vs_shader
->shader
.bc
.ngpr
> rctx
->default_vs_gprs
)
1073 diff
= rctx
->vs_shader
->shader
.bc
.ngpr
- rctx
->default_vs_gprs
;
1074 num_ps_gprs
-= diff
;
1075 num_vs_gprs
+= diff
;
1079 tmp
|= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
1080 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
1082 r600_pipe_state_add_reg(&rstate
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, tmp
, 0x0FFFFFFF, NULL
);
1084 r600_context_pipe_state_set(&rctx
->ctx
, &rstate
);
1087 void r600_init_config(struct r600_pipe_context
*rctx
)
1102 int num_ps_stack_entries
;
1103 int num_vs_stack_entries
;
1104 int num_gs_stack_entries
;
1105 int num_es_stack_entries
;
1106 enum radeon_family family
;
1107 struct r600_pipe_state
*rstate
= &rctx
->config
;
1110 family
= r600_get_family(rctx
->radeon
);
1122 num_ps_threads
= 136;
1123 num_vs_threads
= 48;
1126 num_ps_stack_entries
= 128;
1127 num_vs_stack_entries
= 128;
1128 num_gs_stack_entries
= 0;
1129 num_es_stack_entries
= 0;
1138 num_ps_threads
= 144;
1139 num_vs_threads
= 40;
1142 num_ps_stack_entries
= 40;
1143 num_vs_stack_entries
= 40;
1144 num_gs_stack_entries
= 32;
1145 num_es_stack_entries
= 16;
1157 num_ps_threads
= 136;
1158 num_vs_threads
= 48;
1161 num_ps_stack_entries
= 40;
1162 num_vs_stack_entries
= 40;
1163 num_gs_stack_entries
= 32;
1164 num_es_stack_entries
= 16;
1172 num_ps_threads
= 136;
1173 num_vs_threads
= 48;
1176 num_ps_stack_entries
= 40;
1177 num_vs_stack_entries
= 40;
1178 num_gs_stack_entries
= 32;
1179 num_es_stack_entries
= 16;
1187 num_ps_threads
= 188;
1188 num_vs_threads
= 60;
1191 num_ps_stack_entries
= 256;
1192 num_vs_stack_entries
= 256;
1193 num_gs_stack_entries
= 0;
1194 num_es_stack_entries
= 0;
1203 num_ps_threads
= 188;
1204 num_vs_threads
= 60;
1207 num_ps_stack_entries
= 128;
1208 num_vs_stack_entries
= 128;
1209 num_gs_stack_entries
= 0;
1210 num_es_stack_entries
= 0;
1218 num_ps_threads
= 144;
1219 num_vs_threads
= 48;
1222 num_ps_stack_entries
= 128;
1223 num_vs_stack_entries
= 128;
1224 num_gs_stack_entries
= 0;
1225 num_es_stack_entries
= 0;
1229 rctx
->default_ps_gprs
= num_ps_gprs
;
1230 rctx
->default_vs_gprs
= num_vs_gprs
;
1232 rstate
->id
= R600_PIPE_STATE_CONFIG
;
1244 tmp
|= S_008C00_VC_ENABLE(1);
1247 tmp
|= S_008C00_DX9_CONSTS(0);
1248 tmp
|= S_008C00_ALU_INST_PREFER_VECTOR(1);
1249 tmp
|= S_008C00_PS_PRIO(ps_prio
);
1250 tmp
|= S_008C00_VS_PRIO(vs_prio
);
1251 tmp
|= S_008C00_GS_PRIO(gs_prio
);
1252 tmp
|= S_008C00_ES_PRIO(es_prio
);
1253 r600_pipe_state_add_reg(rstate
, R_008C00_SQ_CONFIG
, tmp
, 0xFFFFFFFF, NULL
);
1255 /* SQ_GPR_RESOURCE_MGMT_1 */
1257 tmp
|= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
1258 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
1259 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
1260 r600_pipe_state_add_reg(rstate
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
);
1262 /* SQ_GPR_RESOURCE_MGMT_2 */
1264 tmp
|= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
1265 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
1266 r600_pipe_state_add_reg(rstate
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
);
1268 /* SQ_THREAD_RESOURCE_MGMT */
1270 tmp
|= S_008C0C_NUM_PS_THREADS(num_ps_threads
);
1271 tmp
|= S_008C0C_NUM_VS_THREADS(num_vs_threads
);
1272 tmp
|= S_008C0C_NUM_GS_THREADS(num_gs_threads
);
1273 tmp
|= S_008C0C_NUM_ES_THREADS(num_es_threads
);
1274 r600_pipe_state_add_reg(rstate
, R_008C0C_SQ_THREAD_RESOURCE_MGMT
, tmp
, 0xFFFFFFFF, NULL
);
1276 /* SQ_STACK_RESOURCE_MGMT_1 */
1278 tmp
|= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
1279 tmp
|= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
1280 r600_pipe_state_add_reg(rstate
, R_008C10_SQ_STACK_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
);
1282 /* SQ_STACK_RESOURCE_MGMT_2 */
1284 tmp
|= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
1285 tmp
|= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
1286 r600_pipe_state_add_reg(rstate
, R_008C14_SQ_STACK_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
);
1288 r600_pipe_state_add_reg(rstate
, R_009714_VC_ENHANCE
, 0x00000000, 0xFFFFFFFF, NULL
);
1289 r600_pipe_state_add_reg(rstate
, R_028350_SX_MISC
, 0x00000000, 0xFFFFFFFF, NULL
);
1291 if (family
>= CHIP_RV770
) {
1292 r600_pipe_state_add_reg(rstate
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x00004000, 0xFFFFFFFF, NULL
);
1293 r600_pipe_state_add_reg(rstate
, R_009508_TA_CNTL_AUX
, 0x07000002, 0xFFFFFFFF, NULL
);
1294 r600_pipe_state_add_reg(rstate
, R_009830_DB_DEBUG
, 0x00000000, 0xFFFFFFFF, NULL
);
1295 r600_pipe_state_add_reg(rstate
, R_009838_DB_WATERMARKS
, 0x00420204, 0xFFFFFFFF, NULL
);
1296 r600_pipe_state_add_reg(rstate
, R_0286C8_SPI_THREAD_GROUPING
, 0x00000000, 0xFFFFFFFF, NULL
);
1297 r600_pipe_state_add_reg(rstate
, R_028A4C_PA_SC_MODE_CNTL
, 0x00514002, 0xFFFFFFFF, NULL
);
1299 r600_pipe_state_add_reg(rstate
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x00000000, 0xFFFFFFFF, NULL
);
1300 r600_pipe_state_add_reg(rstate
, R_009508_TA_CNTL_AUX
, 0x07000003, 0xFFFFFFFF, NULL
);
1301 r600_pipe_state_add_reg(rstate
, R_009830_DB_DEBUG
, 0x82000000, 0xFFFFFFFF, NULL
);
1302 r600_pipe_state_add_reg(rstate
, R_009838_DB_WATERMARKS
, 0x01020204, 0xFFFFFFFF, NULL
);
1303 r600_pipe_state_add_reg(rstate
, R_0286C8_SPI_THREAD_GROUPING
, 0x00000001, 0xFFFFFFFF, NULL
);
1304 r600_pipe_state_add_reg(rstate
, R_028A4C_PA_SC_MODE_CNTL
, 0x00004012, 0xFFFFFFFF, NULL
);
1306 r600_pipe_state_add_reg(rstate
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1307 r600_pipe_state_add_reg(rstate
, R_0288AC_SQ_GSVS_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1308 r600_pipe_state_add_reg(rstate
, R_0288B0_SQ_ESTMP_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1309 r600_pipe_state_add_reg(rstate
, R_0288B4_SQ_GSTMP_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1310 r600_pipe_state_add_reg(rstate
, R_0288B8_SQ_VSTMP_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1311 r600_pipe_state_add_reg(rstate
, R_0288BC_SQ_PSTMP_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1312 r600_pipe_state_add_reg(rstate
, R_0288C0_SQ_FBUF_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1313 r600_pipe_state_add_reg(rstate
, R_0288C4_SQ_REDUC_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1314 r600_pipe_state_add_reg(rstate
, R_0288C8_SQ_GS_VERT_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
1315 r600_pipe_state_add_reg(rstate
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1316 r600_pipe_state_add_reg(rstate
, R_028A14_VGT_HOS_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1317 r600_pipe_state_add_reg(rstate
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0x00000000, 0xFFFFFFFF, NULL
);
1318 r600_pipe_state_add_reg(rstate
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0x00000000, 0xFFFFFFFF, NULL
);
1319 r600_pipe_state_add_reg(rstate
, R_028A20_VGT_HOS_REUSE_DEPTH
, 0x00000000, 0xFFFFFFFF, NULL
);
1320 r600_pipe_state_add_reg(rstate
, R_028A24_VGT_GROUP_PRIM_TYPE
, 0x00000000, 0xFFFFFFFF, NULL
);
1321 r600_pipe_state_add_reg(rstate
, R_028A28_VGT_GROUP_FIRST_DECR
, 0x00000000, 0xFFFFFFFF, NULL
);
1322 r600_pipe_state_add_reg(rstate
, R_028A2C_VGT_GROUP_DECR
, 0x00000000, 0xFFFFFFFF, NULL
);
1323 r600_pipe_state_add_reg(rstate
, R_028A30_VGT_GROUP_VECT_0_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1324 r600_pipe_state_add_reg(rstate
, R_028A34_VGT_GROUP_VECT_1_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1325 r600_pipe_state_add_reg(rstate
, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1326 r600_pipe_state_add_reg(rstate
, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1327 r600_pipe_state_add_reg(rstate
, R_028A40_VGT_GS_MODE
, 0x00000000, 0xFFFFFFFF, NULL
);
1328 r600_pipe_state_add_reg(rstate
, R_028AB0_VGT_STRMOUT_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
1329 r600_pipe_state_add_reg(rstate
, R_028AB4_VGT_REUSE_OFF
, 0x00000001, 0xFFFFFFFF, NULL
);
1330 r600_pipe_state_add_reg(rstate
, R_028AB8_VGT_VTX_CNT_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
1331 r600_pipe_state_add_reg(rstate
, R_028B20_VGT_STRMOUT_BUFFER_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
1333 r600_pipe_state_add_reg(rstate
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, 0x00000000, 0xFFFFFFFF, NULL
);
1334 r600_pipe_state_add_reg(rstate
, R_028A84_VGT_PRIMITIVEID_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
1335 r600_pipe_state_add_reg(rstate
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
1336 r600_pipe_state_add_reg(rstate
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 0x00000000, 0xFFFFFFFF, NULL
);
1337 r600_pipe_state_add_reg(rstate
, R_028AA4_VGT_INSTANCE_STEP_RATE_1
, 0x00000000, 0xFFFFFFFF, NULL
);
1338 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1341 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
1343 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1344 struct r600_pipe_state
*rstate
= &shader
->rstate
;
1345 struct r600_shader
*rshader
= &shader
->shader
;
1346 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
1347 int pos_index
= -1, face_index
= -1;
1351 for (i
= 0; i
< rshader
->ninput
; i
++) {
1352 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
1354 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
1358 db_shader_control
= 0;
1359 for (i
= 0; i
< rshader
->noutput
; i
++) {
1360 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
1361 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(1);
1362 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
1363 db_shader_control
|= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
1365 if (rshader
->uses_kill
)
1366 db_shader_control
|= S_02880C_KILL_ENABLE(1);
1370 for (i
= 0; i
< rshader
->noutput
; i
++) {
1371 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
1372 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
1374 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
1378 exports_ps
|= S_028854_EXPORT_COLORS(num_cout
);
1380 /* always at least export 1 component per pixel */
1384 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(rshader
->ninput
) |
1385 S_0286CC_PERSP_GRADIENT_ENA(1);
1387 if (pos_index
!= -1) {
1388 spi_ps_in_control_0
|= (S_0286CC_POSITION_ENA(1) |
1389 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
1390 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
) |
1391 S_0286CC_BARYC_SAMPLE_CNTL(1));
1395 spi_ps_in_control_1
= 0;
1396 if (face_index
!= -1) {
1397 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
1398 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
1401 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
, spi_ps_in_control_0
, 0xFFFFFFFF, NULL
);
1402 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
, spi_ps_in_control_1
, 0xFFFFFFFF, NULL
);
1403 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
, 0xFFFFFFFF, NULL
);
1404 r600_pipe_state_add_reg(rstate
,
1405 R_028840_SQ_PGM_START_PS
,
1406 r600_bo_offset(shader
->bo
) >> 8, 0xFFFFFFFF, shader
->bo
);
1407 r600_pipe_state_add_reg(rstate
,
1408 R_028850_SQ_PGM_RESOURCES_PS
,
1409 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
1410 S_028868_STACK_SIZE(rshader
->bc
.nstack
),
1412 r600_pipe_state_add_reg(rstate
,
1413 R_028854_SQ_PGM_EXPORTS_PS
,
1414 exports_ps
, 0xFFFFFFFF, NULL
);
1415 r600_pipe_state_add_reg(rstate
,
1416 R_0288CC_SQ_PGM_CF_OFFSET_PS
,
1417 0x00000000, 0xFFFFFFFF, NULL
);
1418 r600_pipe_state_add_reg(rstate
, R_028808_CB_COLOR_CONTROL
,
1419 S_028808_MULTIWRITE_ENABLE(!!rshader
->fs_write_all
),
1420 S_028808_MULTIWRITE_ENABLE(1),
1422 /* only set some bits here, the other bits are set in the dsa state */
1423 r600_pipe_state_add_reg(rstate
, R_02880C_DB_SHADER_CONTROL
,
1425 S_02880C_Z_EXPORT_ENABLE(1) |
1426 S_02880C_STENCIL_REF_EXPORT_ENABLE(1) |
1427 S_02880C_KILL_ENABLE(1),
1430 r600_pipe_state_add_reg(rstate
,
1431 R_03E200_SQ_LOOP_CONST_0
, 0x01000FFF,
1435 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
1437 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1438 struct r600_pipe_state
*rstate
= &shader
->rstate
;
1439 struct r600_shader
*rshader
= &shader
->shader
;
1440 unsigned spi_vs_out_id
[10];
1443 /* clear previous register */
1446 /* so far never got proper semantic id from tgsi */
1447 /* FIXME better to move this in config things so they get emited
1448 * only one time per cs
1450 for (i
= 0; i
< 10; i
++) {
1451 spi_vs_out_id
[i
] = 0;
1453 for (i
= 0; i
< 32; i
++) {
1454 tmp
= i
<< ((i
& 3) * 8);
1455 spi_vs_out_id
[i
/ 4] |= tmp
;
1457 for (i
= 0; i
< 10; i
++) {
1458 r600_pipe_state_add_reg(rstate
,
1459 R_028614_SPI_VS_OUT_ID_0
+ i
* 4,
1460 spi_vs_out_id
[i
], 0xFFFFFFFF, NULL
);
1463 r600_pipe_state_add_reg(rstate
,
1464 R_0286C4_SPI_VS_OUT_CONFIG
,
1465 S_0286C4_VS_EXPORT_COUNT(rshader
->noutput
- 2),
1467 r600_pipe_state_add_reg(rstate
,
1468 R_028868_SQ_PGM_RESOURCES_VS
,
1469 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
1470 S_028868_STACK_SIZE(rshader
->bc
.nstack
),
1472 r600_pipe_state_add_reg(rstate
,
1473 R_0288D0_SQ_PGM_CF_OFFSET_VS
,
1474 0x00000000, 0xFFFFFFFF, NULL
);
1475 r600_pipe_state_add_reg(rstate
,
1476 R_028858_SQ_PGM_START_VS
,
1477 r600_bo_offset(shader
->bo
) >> 8, 0xFFFFFFFF, shader
->bo
);
1479 r600_pipe_state_add_reg(rstate
,
1480 R_03E200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF,
1484 void r600_fetch_shader(struct pipe_context
*ctx
,
1485 struct r600_vertex_element
*ve
)
1487 struct r600_pipe_state
*rstate
;
1488 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1490 rstate
= &ve
->rstate
;
1491 rstate
->id
= R600_PIPE_STATE_FETCH_SHADER
;
1493 r600_pipe_state_add_reg(rstate
, R_0288A4_SQ_PGM_RESOURCES_FS
,
1494 0x00000000, 0xFFFFFFFF, NULL
);
1495 r600_pipe_state_add_reg(rstate
, R_0288DC_SQ_PGM_CF_OFFSET_FS
,
1496 0x00000000, 0xFFFFFFFF, NULL
);
1497 r600_pipe_state_add_reg(rstate
, R_028894_SQ_PGM_START_FS
,
1498 r600_bo_offset(ve
->fetch_shader
) >> 8,
1499 0xFFFFFFFF, ve
->fetch_shader
);
1502 void *r600_create_db_flush_dsa(struct r600_pipe_context
*rctx
)
1504 struct pipe_depth_stencil_alpha_state dsa
;
1505 struct r600_pipe_state
*rstate
;
1506 boolean quirk
= false;
1508 if (rctx
->family
== CHIP_RV610
|| rctx
->family
== CHIP_RV630
||
1509 rctx
->family
== CHIP_RV620
|| rctx
->family
== CHIP_RV635
)
1512 memset(&dsa
, 0, sizeof(dsa
));
1515 dsa
.depth
.enabled
= 1;
1516 dsa
.depth
.func
= PIPE_FUNC_LEQUAL
;
1517 dsa
.stencil
[0].enabled
= 1;
1518 dsa
.stencil
[0].func
= PIPE_FUNC_ALWAYS
;
1519 dsa
.stencil
[0].zpass_op
= PIPE_STENCIL_OP_KEEP
;
1520 dsa
.stencil
[0].zfail_op
= PIPE_STENCIL_OP_INCR
;
1521 dsa
.stencil
[0].writemask
= 0xff;
1524 rstate
= rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
1525 r600_pipe_state_add_reg(rstate
,
1526 R_02880C_DB_SHADER_CONTROL
,
1528 S_02880C_DUAL_EXPORT_ENABLE(1), NULL
);
1529 r600_pipe_state_add_reg(rstate
,
1530 R_028D0C_DB_RENDER_CONTROL
,
1531 S_028D0C_DEPTH_COPY_ENABLE(1) |
1532 S_028D0C_STENCIL_COPY_ENABLE(1) |
1533 S_028D0C_COPY_CENTROID(1),
1534 S_028D0C_DEPTH_COPY_ENABLE(1) |
1535 S_028D0C_STENCIL_COPY_ENABLE(1) |
1536 S_028D0C_COPY_CENTROID(1), NULL
);
1540 void r600_pipe_init_buffer_resource(struct r600_pipe_context
*rctx
,
1541 struct r600_pipe_resource_state
*rstate
)
1543 rstate
->id
= R600_PIPE_STATE_RESOURCE
;
1545 rstate
->bo
[0] = NULL
;
1552 rstate
->val
[6] = 0xc0000000;
1555 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state
*rstate
,
1556 struct r600_resource
*rbuffer
,
1557 unsigned offset
, unsigned stride
)
1559 rstate
->val
[0] = offset
;
1560 rstate
->bo
[0] = rbuffer
->bo
;
1561 rstate
->val
[1] = rbuffer
->bo_size
- offset
- 1;
1562 rstate
->val
[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1563 S_038008_STRIDE(stride
);